repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
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PhicoinProject/PhicoinProject | 28,173 | src/secp256k1/src/asm/field_10x26_arm.s | @ vim: set tabstop=8 softtabstop=8 shiftwidth=8 noexpandtab syntax=armasm:
/**********************************************************************
* Copyright (c) 2014 Wladimir J. van der Laan *
* Distributed under the MIT software license, see the accompanying *
* file COPYING or http://www.opensource.org/licenses/mit-license.php.*
**********************************************************************/
/*
ARM implementation of field_10x26 inner loops.
Note:
- To avoid unnecessary loads and make use of available registers, two
'passes' have every time been interleaved, with the odd passes accumulating c' and d'
which will be added to c and d respectively in the even passes
*/
.syntax unified
@ eabi attributes - see readelf -A
.eabi_attribute 24, 1 @ Tag_ABI_align_needed = 8-byte
.eabi_attribute 25, 1 @ Tag_ABI_align_preserved = 8-byte, except leaf SP
.text
@ Field constants
.set field_R0, 0x3d10
.set field_R1, 0x400
.set field_not_M, 0xfc000000 @ ~M = ~0x3ffffff
.align 2
.global secp256k1_fe_mul_inner
.type secp256k1_fe_mul_inner, %function
@ Arguments:
@ r0 r Restrict: can overlap with a, not with b
@ r1 a
@ r2 b
@ Stack (total 4+10*4 = 44)
@ sp + #0 saved 'r' pointer
@ sp + #4 + 4*X t0,t1,t2,t3,t4,t5,t6,t7,u8,t9
secp256k1_fe_mul_inner:
stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, r14}
sub sp, sp, #48 @ frame=44 + alignment
str r0, [sp, #0] @ save result address, we need it only at the end
/******************************************
* Main computation code.
******************************************
Allocation:
r0,r14,r7,r8 scratch
r1 a (pointer)
r2 b (pointer)
r3:r4 c
r5:r6 d
r11:r12 c'
r9:r10 d'
Note: do not write to r[] here, it may overlap with a[]
*/
/* A - interleaved with B */
ldr r7, [r1, #0*4] @ a[0]
ldr r8, [r2, #9*4] @ b[9]
ldr r0, [r1, #1*4] @ a[1]
umull r5, r6, r7, r8 @ d = a[0] * b[9]
ldr r14, [r2, #8*4] @ b[8]
umull r9, r10, r0, r8 @ d' = a[1] * b[9]
ldr r7, [r1, #2*4] @ a[2]
umlal r5, r6, r0, r14 @ d += a[1] * b[8]
ldr r8, [r2, #7*4] @ b[7]
umlal r9, r10, r7, r14 @ d' += a[2] * b[8]
ldr r0, [r1, #3*4] @ a[3]
umlal r5, r6, r7, r8 @ d += a[2] * b[7]
ldr r14, [r2, #6*4] @ b[6]
umlal r9, r10, r0, r8 @ d' += a[3] * b[7]
ldr r7, [r1, #4*4] @ a[4]
umlal r5, r6, r0, r14 @ d += a[3] * b[6]
ldr r8, [r2, #5*4] @ b[5]
umlal r9, r10, r7, r14 @ d' += a[4] * b[6]
ldr r0, [r1, #5*4] @ a[5]
umlal r5, r6, r7, r8 @ d += a[4] * b[5]
ldr r14, [r2, #4*4] @ b[4]
umlal r9, r10, r0, r8 @ d' += a[5] * b[5]
ldr r7, [r1, #6*4] @ a[6]
umlal r5, r6, r0, r14 @ d += a[5] * b[4]
ldr r8, [r2, #3*4] @ b[3]
umlal r9, r10, r7, r14 @ d' += a[6] * b[4]
ldr r0, [r1, #7*4] @ a[7]
umlal r5, r6, r7, r8 @ d += a[6] * b[3]
ldr r14, [r2, #2*4] @ b[2]
umlal r9, r10, r0, r8 @ d' += a[7] * b[3]
ldr r7, [r1, #8*4] @ a[8]
umlal r5, r6, r0, r14 @ d += a[7] * b[2]
ldr r8, [r2, #1*4] @ b[1]
umlal r9, r10, r7, r14 @ d' += a[8] * b[2]
ldr r0, [r1, #9*4] @ a[9]
umlal r5, r6, r7, r8 @ d += a[8] * b[1]
ldr r14, [r2, #0*4] @ b[0]
umlal r9, r10, r0, r8 @ d' += a[9] * b[1]
ldr r7, [r1, #0*4] @ a[0]
umlal r5, r6, r0, r14 @ d += a[9] * b[0]
@ r7,r14 used in B
bic r0, r5, field_not_M @ t9 = d & M
str r0, [sp, #4 + 4*9]
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
/* B */
umull r3, r4, r7, r14 @ c = a[0] * b[0]
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u0 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u0 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t0 = c & M
str r14, [sp, #4 + 0*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u0 * R1
umlal r3, r4, r0, r14
/* C - interleaved with D */
ldr r7, [r1, #0*4] @ a[0]
ldr r8, [r2, #2*4] @ b[2]
ldr r14, [r2, #1*4] @ b[1]
umull r11, r12, r7, r8 @ c' = a[0] * b[2]
ldr r0, [r1, #1*4] @ a[1]
umlal r3, r4, r7, r14 @ c += a[0] * b[1]
ldr r8, [r2, #0*4] @ b[0]
umlal r11, r12, r0, r14 @ c' += a[1] * b[1]
ldr r7, [r1, #2*4] @ a[2]
umlal r3, r4, r0, r8 @ c += a[1] * b[0]
ldr r14, [r2, #9*4] @ b[9]
umlal r11, r12, r7, r8 @ c' += a[2] * b[0]
ldr r0, [r1, #3*4] @ a[3]
umlal r5, r6, r7, r14 @ d += a[2] * b[9]
ldr r8, [r2, #8*4] @ b[8]
umull r9, r10, r0, r14 @ d' = a[3] * b[9]
ldr r7, [r1, #4*4] @ a[4]
umlal r5, r6, r0, r8 @ d += a[3] * b[8]
ldr r14, [r2, #7*4] @ b[7]
umlal r9, r10, r7, r8 @ d' += a[4] * b[8]
ldr r0, [r1, #5*4] @ a[5]
umlal r5, r6, r7, r14 @ d += a[4] * b[7]
ldr r8, [r2, #6*4] @ b[6]
umlal r9, r10, r0, r14 @ d' += a[5] * b[7]
ldr r7, [r1, #6*4] @ a[6]
umlal r5, r6, r0, r8 @ d += a[5] * b[6]
ldr r14, [r2, #5*4] @ b[5]
umlal r9, r10, r7, r8 @ d' += a[6] * b[6]
ldr r0, [r1, #7*4] @ a[7]
umlal r5, r6, r7, r14 @ d += a[6] * b[5]
ldr r8, [r2, #4*4] @ b[4]
umlal r9, r10, r0, r14 @ d' += a[7] * b[5]
ldr r7, [r1, #8*4] @ a[8]
umlal r5, r6, r0, r8 @ d += a[7] * b[4]
ldr r14, [r2, #3*4] @ b[3]
umlal r9, r10, r7, r8 @ d' += a[8] * b[4]
ldr r0, [r1, #9*4] @ a[9]
umlal r5, r6, r7, r14 @ d += a[8] * b[3]
ldr r8, [r2, #2*4] @ b[2]
umlal r9, r10, r0, r14 @ d' += a[9] * b[3]
umlal r5, r6, r0, r8 @ d += a[9] * b[2]
bic r0, r5, field_not_M @ u1 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u1 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t1 = c & M
str r14, [sp, #4 + 1*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u1 * R1
umlal r3, r4, r0, r14
/* D */
adds r3, r3, r11 @ c += c'
adc r4, r4, r12
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u2 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u2 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t2 = c & M
str r14, [sp, #4 + 2*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u2 * R1
umlal r3, r4, r0, r14
/* E - interleaved with F */
ldr r7, [r1, #0*4] @ a[0]
ldr r8, [r2, #4*4] @ b[4]
umull r11, r12, r7, r8 @ c' = a[0] * b[4]
ldr r8, [r2, #3*4] @ b[3]
umlal r3, r4, r7, r8 @ c += a[0] * b[3]
ldr r7, [r1, #1*4] @ a[1]
umlal r11, r12, r7, r8 @ c' += a[1] * b[3]
ldr r8, [r2, #2*4] @ b[2]
umlal r3, r4, r7, r8 @ c += a[1] * b[2]
ldr r7, [r1, #2*4] @ a[2]
umlal r11, r12, r7, r8 @ c' += a[2] * b[2]
ldr r8, [r2, #1*4] @ b[1]
umlal r3, r4, r7, r8 @ c += a[2] * b[1]
ldr r7, [r1, #3*4] @ a[3]
umlal r11, r12, r7, r8 @ c' += a[3] * b[1]
ldr r8, [r2, #0*4] @ b[0]
umlal r3, r4, r7, r8 @ c += a[3] * b[0]
ldr r7, [r1, #4*4] @ a[4]
umlal r11, r12, r7, r8 @ c' += a[4] * b[0]
ldr r8, [r2, #9*4] @ b[9]
umlal r5, r6, r7, r8 @ d += a[4] * b[9]
ldr r7, [r1, #5*4] @ a[5]
umull r9, r10, r7, r8 @ d' = a[5] * b[9]
ldr r8, [r2, #8*4] @ b[8]
umlal r5, r6, r7, r8 @ d += a[5] * b[8]
ldr r7, [r1, #6*4] @ a[6]
umlal r9, r10, r7, r8 @ d' += a[6] * b[8]
ldr r8, [r2, #7*4] @ b[7]
umlal r5, r6, r7, r8 @ d += a[6] * b[7]
ldr r7, [r1, #7*4] @ a[7]
umlal r9, r10, r7, r8 @ d' += a[7] * b[7]
ldr r8, [r2, #6*4] @ b[6]
umlal r5, r6, r7, r8 @ d += a[7] * b[6]
ldr r7, [r1, #8*4] @ a[8]
umlal r9, r10, r7, r8 @ d' += a[8] * b[6]
ldr r8, [r2, #5*4] @ b[5]
umlal r5, r6, r7, r8 @ d += a[8] * b[5]
ldr r7, [r1, #9*4] @ a[9]
umlal r9, r10, r7, r8 @ d' += a[9] * b[5]
ldr r8, [r2, #4*4] @ b[4]
umlal r5, r6, r7, r8 @ d += a[9] * b[4]
bic r0, r5, field_not_M @ u3 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u3 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t3 = c & M
str r14, [sp, #4 + 3*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u3 * R1
umlal r3, r4, r0, r14
/* F */
adds r3, r3, r11 @ c += c'
adc r4, r4, r12
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u4 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u4 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t4 = c & M
str r14, [sp, #4 + 4*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u4 * R1
umlal r3, r4, r0, r14
/* G - interleaved with H */
ldr r7, [r1, #0*4] @ a[0]
ldr r8, [r2, #6*4] @ b[6]
ldr r14, [r2, #5*4] @ b[5]
umull r11, r12, r7, r8 @ c' = a[0] * b[6]
ldr r0, [r1, #1*4] @ a[1]
umlal r3, r4, r7, r14 @ c += a[0] * b[5]
ldr r8, [r2, #4*4] @ b[4]
umlal r11, r12, r0, r14 @ c' += a[1] * b[5]
ldr r7, [r1, #2*4] @ a[2]
umlal r3, r4, r0, r8 @ c += a[1] * b[4]
ldr r14, [r2, #3*4] @ b[3]
umlal r11, r12, r7, r8 @ c' += a[2] * b[4]
ldr r0, [r1, #3*4] @ a[3]
umlal r3, r4, r7, r14 @ c += a[2] * b[3]
ldr r8, [r2, #2*4] @ b[2]
umlal r11, r12, r0, r14 @ c' += a[3] * b[3]
ldr r7, [r1, #4*4] @ a[4]
umlal r3, r4, r0, r8 @ c += a[3] * b[2]
ldr r14, [r2, #1*4] @ b[1]
umlal r11, r12, r7, r8 @ c' += a[4] * b[2]
ldr r0, [r1, #5*4] @ a[5]
umlal r3, r4, r7, r14 @ c += a[4] * b[1]
ldr r8, [r2, #0*4] @ b[0]
umlal r11, r12, r0, r14 @ c' += a[5] * b[1]
ldr r7, [r1, #6*4] @ a[6]
umlal r3, r4, r0, r8 @ c += a[5] * b[0]
ldr r14, [r2, #9*4] @ b[9]
umlal r11, r12, r7, r8 @ c' += a[6] * b[0]
ldr r0, [r1, #7*4] @ a[7]
umlal r5, r6, r7, r14 @ d += a[6] * b[9]
ldr r8, [r2, #8*4] @ b[8]
umull r9, r10, r0, r14 @ d' = a[7] * b[9]
ldr r7, [r1, #8*4] @ a[8]
umlal r5, r6, r0, r8 @ d += a[7] * b[8]
ldr r14, [r2, #7*4] @ b[7]
umlal r9, r10, r7, r8 @ d' += a[8] * b[8]
ldr r0, [r1, #9*4] @ a[9]
umlal r5, r6, r7, r14 @ d += a[8] * b[7]
ldr r8, [r2, #6*4] @ b[6]
umlal r9, r10, r0, r14 @ d' += a[9] * b[7]
umlal r5, r6, r0, r8 @ d += a[9] * b[6]
bic r0, r5, field_not_M @ u5 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u5 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t5 = c & M
str r14, [sp, #4 + 5*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u5 * R1
umlal r3, r4, r0, r14
/* H */
adds r3, r3, r11 @ c += c'
adc r4, r4, r12
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u6 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u6 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t6 = c & M
str r14, [sp, #4 + 6*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u6 * R1
umlal r3, r4, r0, r14
/* I - interleaved with J */
ldr r8, [r2, #8*4] @ b[8]
ldr r7, [r1, #0*4] @ a[0]
ldr r14, [r2, #7*4] @ b[7]
umull r11, r12, r7, r8 @ c' = a[0] * b[8]
ldr r0, [r1, #1*4] @ a[1]
umlal r3, r4, r7, r14 @ c += a[0] * b[7]
ldr r8, [r2, #6*4] @ b[6]
umlal r11, r12, r0, r14 @ c' += a[1] * b[7]
ldr r7, [r1, #2*4] @ a[2]
umlal r3, r4, r0, r8 @ c += a[1] * b[6]
ldr r14, [r2, #5*4] @ b[5]
umlal r11, r12, r7, r8 @ c' += a[2] * b[6]
ldr r0, [r1, #3*4] @ a[3]
umlal r3, r4, r7, r14 @ c += a[2] * b[5]
ldr r8, [r2, #4*4] @ b[4]
umlal r11, r12, r0, r14 @ c' += a[3] * b[5]
ldr r7, [r1, #4*4] @ a[4]
umlal r3, r4, r0, r8 @ c += a[3] * b[4]
ldr r14, [r2, #3*4] @ b[3]
umlal r11, r12, r7, r8 @ c' += a[4] * b[4]
ldr r0, [r1, #5*4] @ a[5]
umlal r3, r4, r7, r14 @ c += a[4] * b[3]
ldr r8, [r2, #2*4] @ b[2]
umlal r11, r12, r0, r14 @ c' += a[5] * b[3]
ldr r7, [r1, #6*4] @ a[6]
umlal r3, r4, r0, r8 @ c += a[5] * b[2]
ldr r14, [r2, #1*4] @ b[1]
umlal r11, r12, r7, r8 @ c' += a[6] * b[2]
ldr r0, [r1, #7*4] @ a[7]
umlal r3, r4, r7, r14 @ c += a[6] * b[1]
ldr r8, [r2, #0*4] @ b[0]
umlal r11, r12, r0, r14 @ c' += a[7] * b[1]
ldr r7, [r1, #8*4] @ a[8]
umlal r3, r4, r0, r8 @ c += a[7] * b[0]
ldr r14, [r2, #9*4] @ b[9]
umlal r11, r12, r7, r8 @ c' += a[8] * b[0]
ldr r0, [r1, #9*4] @ a[9]
umlal r5, r6, r7, r14 @ d += a[8] * b[9]
ldr r8, [r2, #8*4] @ b[8]
umull r9, r10, r0, r14 @ d' = a[9] * b[9]
umlal r5, r6, r0, r8 @ d += a[9] * b[8]
bic r0, r5, field_not_M @ u7 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u7 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t7 = c & M
str r14, [sp, #4 + 7*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u7 * R1
umlal r3, r4, r0, r14
/* J */
adds r3, r3, r11 @ c += c'
adc r4, r4, r12
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u8 = d & M
str r0, [sp, #4 + 8*4]
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u8 * R0
umlal r3, r4, r0, r14
/******************************************
* compute and write back result
******************************************
Allocation:
r0 r
r3:r4 c
r5:r6 d
r7 t0
r8 t1
r9 t2
r11 u8
r12 t9
r1,r2,r10,r14 scratch
Note: do not read from a[] after here, it may overlap with r[]
*/
ldr r0, [sp, #0]
add r1, sp, #4 + 3*4 @ r[3..7] = t3..7, r11=u8, r12=t9
ldmia r1, {r2,r7,r8,r9,r10,r11,r12}
add r1, r0, #3*4
stmia r1, {r2,r7,r8,r9,r10}
bic r2, r3, field_not_M @ r[8] = c & M
str r2, [r0, #8*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u8 * R1
umlal r3, r4, r11, r14
movw r14, field_R0 @ c += d * R0
umlal r3, r4, r5, r14
adds r3, r3, r12 @ c += t9
adc r4, r4, #0
add r1, sp, #4 + 0*4 @ r7,r8,r9 = t0,t1,t2
ldmia r1, {r7,r8,r9}
ubfx r2, r3, #0, #22 @ r[9] = c & (M >> 4)
str r2, [r0, #9*4]
mov r3, r3, lsr #22 @ c >>= 22
orr r3, r3, r4, asl #10
mov r4, r4, lsr #22
movw r14, field_R1 << 4 @ c += d * (R1 << 4)
umlal r3, r4, r5, r14
movw r14, field_R0 >> 4 @ d = c * (R0 >> 4) + t0 (64x64 multiply+add)
umull r5, r6, r3, r14 @ d = c.lo * (R0 >> 4)
adds r5, r5, r7 @ d.lo += t0
mla r6, r14, r4, r6 @ d.hi += c.hi * (R0 >> 4)
adc r6, r6, 0 @ d.hi += carry
bic r2, r5, field_not_M @ r[0] = d & M
str r2, [r0, #0*4]
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R1 >> 4 @ d += c * (R1 >> 4) + t1 (64x64 multiply+add)
umull r1, r2, r3, r14 @ tmp = c.lo * (R1 >> 4)
adds r5, r5, r8 @ d.lo += t1
adc r6, r6, #0 @ d.hi += carry
adds r5, r5, r1 @ d.lo += tmp.lo
mla r2, r14, r4, r2 @ tmp.hi += c.hi * (R1 >> 4)
adc r6, r6, r2 @ d.hi += carry + tmp.hi
bic r2, r5, field_not_M @ r[1] = d & M
str r2, [r0, #1*4]
mov r5, r5, lsr #26 @ d >>= 26 (ignore hi)
orr r5, r5, r6, asl #6
add r5, r5, r9 @ d += t2
str r5, [r0, #2*4] @ r[2] = d
add sp, sp, #48
ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc}
.size secp256k1_fe_mul_inner, .-secp256k1_fe_mul_inner
.align 2
.global secp256k1_fe_sqr_inner
.type secp256k1_fe_sqr_inner, %function
@ Arguments:
@ r0 r Can overlap with a
@ r1 a
@ Stack (total 4+10*4 = 44)
@ sp + #0 saved 'r' pointer
@ sp + #4 + 4*X t0,t1,t2,t3,t4,t5,t6,t7,u8,t9
secp256k1_fe_sqr_inner:
stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, r14}
sub sp, sp, #48 @ frame=44 + alignment
str r0, [sp, #0] @ save result address, we need it only at the end
/******************************************
* Main computation code.
******************************************
Allocation:
r0,r14,r2,r7,r8 scratch
r1 a (pointer)
r3:r4 c
r5:r6 d
r11:r12 c'
r9:r10 d'
Note: do not write to r[] here, it may overlap with a[]
*/
/* A interleaved with B */
ldr r0, [r1, #1*4] @ a[1]*2
ldr r7, [r1, #0*4] @ a[0]
mov r0, r0, asl #1
ldr r14, [r1, #9*4] @ a[9]
umull r3, r4, r7, r7 @ c = a[0] * a[0]
ldr r8, [r1, #8*4] @ a[8]
mov r7, r7, asl #1
umull r5, r6, r7, r14 @ d = a[0]*2 * a[9]
ldr r7, [r1, #2*4] @ a[2]*2
umull r9, r10, r0, r14 @ d' = a[1]*2 * a[9]
ldr r14, [r1, #7*4] @ a[7]
umlal r5, r6, r0, r8 @ d += a[1]*2 * a[8]
mov r7, r7, asl #1
ldr r0, [r1, #3*4] @ a[3]*2
umlal r9, r10, r7, r8 @ d' += a[2]*2 * a[8]
ldr r8, [r1, #6*4] @ a[6]
umlal r5, r6, r7, r14 @ d += a[2]*2 * a[7]
mov r0, r0, asl #1
ldr r7, [r1, #4*4] @ a[4]*2
umlal r9, r10, r0, r14 @ d' += a[3]*2 * a[7]
ldr r14, [r1, #5*4] @ a[5]
mov r7, r7, asl #1
umlal r5, r6, r0, r8 @ d += a[3]*2 * a[6]
umlal r9, r10, r7, r8 @ d' += a[4]*2 * a[6]
umlal r5, r6, r7, r14 @ d += a[4]*2 * a[5]
umlal r9, r10, r14, r14 @ d' += a[5] * a[5]
bic r0, r5, field_not_M @ t9 = d & M
str r0, [sp, #4 + 9*4]
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
/* B */
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u0 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u0 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t0 = c & M
str r14, [sp, #4 + 0*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u0 * R1
umlal r3, r4, r0, r14
/* C interleaved with D */
ldr r0, [r1, #0*4] @ a[0]*2
ldr r14, [r1, #1*4] @ a[1]
mov r0, r0, asl #1
ldr r8, [r1, #2*4] @ a[2]
umlal r3, r4, r0, r14 @ c += a[0]*2 * a[1]
mov r7, r8, asl #1 @ a[2]*2
umull r11, r12, r14, r14 @ c' = a[1] * a[1]
ldr r14, [r1, #9*4] @ a[9]
umlal r11, r12, r0, r8 @ c' += a[0]*2 * a[2]
ldr r0, [r1, #3*4] @ a[3]*2
ldr r8, [r1, #8*4] @ a[8]
umlal r5, r6, r7, r14 @ d += a[2]*2 * a[9]
mov r0, r0, asl #1
ldr r7, [r1, #4*4] @ a[4]*2
umull r9, r10, r0, r14 @ d' = a[3]*2 * a[9]
ldr r14, [r1, #7*4] @ a[7]
umlal r5, r6, r0, r8 @ d += a[3]*2 * a[8]
mov r7, r7, asl #1
ldr r0, [r1, #5*4] @ a[5]*2
umlal r9, r10, r7, r8 @ d' += a[4]*2 * a[8]
ldr r8, [r1, #6*4] @ a[6]
mov r0, r0, asl #1
umlal r5, r6, r7, r14 @ d += a[4]*2 * a[7]
umlal r9, r10, r0, r14 @ d' += a[5]*2 * a[7]
umlal r5, r6, r0, r8 @ d += a[5]*2 * a[6]
umlal r9, r10, r8, r8 @ d' += a[6] * a[6]
bic r0, r5, field_not_M @ u1 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u1 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t1 = c & M
str r14, [sp, #4 + 1*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u1 * R1
umlal r3, r4, r0, r14
/* D */
adds r3, r3, r11 @ c += c'
adc r4, r4, r12
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u2 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u2 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t2 = c & M
str r14, [sp, #4 + 2*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u2 * R1
umlal r3, r4, r0, r14
/* E interleaved with F */
ldr r7, [r1, #0*4] @ a[0]*2
ldr r0, [r1, #1*4] @ a[1]*2
ldr r14, [r1, #2*4] @ a[2]
mov r7, r7, asl #1
ldr r8, [r1, #3*4] @ a[3]
ldr r2, [r1, #4*4]
umlal r3, r4, r7, r8 @ c += a[0]*2 * a[3]
mov r0, r0, asl #1
umull r11, r12, r7, r2 @ c' = a[0]*2 * a[4]
mov r2, r2, asl #1 @ a[4]*2
umlal r11, r12, r0, r8 @ c' += a[1]*2 * a[3]
ldr r8, [r1, #9*4] @ a[9]
umlal r3, r4, r0, r14 @ c += a[1]*2 * a[2]
ldr r0, [r1, #5*4] @ a[5]*2
umlal r11, r12, r14, r14 @ c' += a[2] * a[2]
ldr r14, [r1, #8*4] @ a[8]
mov r0, r0, asl #1
umlal r5, r6, r2, r8 @ d += a[4]*2 * a[9]
ldr r7, [r1, #6*4] @ a[6]*2
umull r9, r10, r0, r8 @ d' = a[5]*2 * a[9]
mov r7, r7, asl #1
ldr r8, [r1, #7*4] @ a[7]
umlal r5, r6, r0, r14 @ d += a[5]*2 * a[8]
umlal r9, r10, r7, r14 @ d' += a[6]*2 * a[8]
umlal r5, r6, r7, r8 @ d += a[6]*2 * a[7]
umlal r9, r10, r8, r8 @ d' += a[7] * a[7]
bic r0, r5, field_not_M @ u3 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u3 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t3 = c & M
str r14, [sp, #4 + 3*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u3 * R1
umlal r3, r4, r0, r14
/* F */
adds r3, r3, r11 @ c += c'
adc r4, r4, r12
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u4 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u4 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t4 = c & M
str r14, [sp, #4 + 4*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u4 * R1
umlal r3, r4, r0, r14
/* G interleaved with H */
ldr r7, [r1, #0*4] @ a[0]*2
ldr r0, [r1, #1*4] @ a[1]*2
mov r7, r7, asl #1
ldr r8, [r1, #5*4] @ a[5]
ldr r2, [r1, #6*4] @ a[6]
umlal r3, r4, r7, r8 @ c += a[0]*2 * a[5]
ldr r14, [r1, #4*4] @ a[4]
mov r0, r0, asl #1
umull r11, r12, r7, r2 @ c' = a[0]*2 * a[6]
ldr r7, [r1, #2*4] @ a[2]*2
umlal r11, r12, r0, r8 @ c' += a[1]*2 * a[5]
mov r7, r7, asl #1
ldr r8, [r1, #3*4] @ a[3]
umlal r3, r4, r0, r14 @ c += a[1]*2 * a[4]
mov r0, r2, asl #1 @ a[6]*2
umlal r11, r12, r7, r14 @ c' += a[2]*2 * a[4]
ldr r14, [r1, #9*4] @ a[9]
umlal r3, r4, r7, r8 @ c += a[2]*2 * a[3]
ldr r7, [r1, #7*4] @ a[7]*2
umlal r11, r12, r8, r8 @ c' += a[3] * a[3]
mov r7, r7, asl #1
ldr r8, [r1, #8*4] @ a[8]
umlal r5, r6, r0, r14 @ d += a[6]*2 * a[9]
umull r9, r10, r7, r14 @ d' = a[7]*2 * a[9]
umlal r5, r6, r7, r8 @ d += a[7]*2 * a[8]
umlal r9, r10, r8, r8 @ d' += a[8] * a[8]
bic r0, r5, field_not_M @ u5 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u5 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t5 = c & M
str r14, [sp, #4 + 5*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u5 * R1
umlal r3, r4, r0, r14
/* H */
adds r3, r3, r11 @ c += c'
adc r4, r4, r12
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u6 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u6 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t6 = c & M
str r14, [sp, #4 + 6*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u6 * R1
umlal r3, r4, r0, r14
/* I interleaved with J */
ldr r7, [r1, #0*4] @ a[0]*2
ldr r0, [r1, #1*4] @ a[1]*2
mov r7, r7, asl #1
ldr r8, [r1, #7*4] @ a[7]
ldr r2, [r1, #8*4] @ a[8]
umlal r3, r4, r7, r8 @ c += a[0]*2 * a[7]
ldr r14, [r1, #6*4] @ a[6]
mov r0, r0, asl #1
umull r11, r12, r7, r2 @ c' = a[0]*2 * a[8]
ldr r7, [r1, #2*4] @ a[2]*2
umlal r11, r12, r0, r8 @ c' += a[1]*2 * a[7]
ldr r8, [r1, #5*4] @ a[5]
umlal r3, r4, r0, r14 @ c += a[1]*2 * a[6]
ldr r0, [r1, #3*4] @ a[3]*2
mov r7, r7, asl #1
umlal r11, r12, r7, r14 @ c' += a[2]*2 * a[6]
ldr r14, [r1, #4*4] @ a[4]
mov r0, r0, asl #1
umlal r3, r4, r7, r8 @ c += a[2]*2 * a[5]
mov r2, r2, asl #1 @ a[8]*2
umlal r11, r12, r0, r8 @ c' += a[3]*2 * a[5]
umlal r3, r4, r0, r14 @ c += a[3]*2 * a[4]
umlal r11, r12, r14, r14 @ c' += a[4] * a[4]
ldr r8, [r1, #9*4] @ a[9]
umlal r5, r6, r2, r8 @ d += a[8]*2 * a[9]
@ r8 will be used in J
bic r0, r5, field_not_M @ u7 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u7 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t7 = c & M
str r14, [sp, #4 + 7*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u7 * R1
umlal r3, r4, r0, r14
/* J */
adds r3, r3, r11 @ c += c'
adc r4, r4, r12
umlal r5, r6, r8, r8 @ d += a[9] * a[9]
bic r0, r5, field_not_M @ u8 = d & M
str r0, [sp, #4 + 8*4]
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u8 * R0
umlal r3, r4, r0, r14
/******************************************
* compute and write back result
******************************************
Allocation:
r0 r
r3:r4 c
r5:r6 d
r7 t0
r8 t1
r9 t2
r11 u8
r12 t9
r1,r2,r10,r14 scratch
Note: do not read from a[] after here, it may overlap with r[]
*/
ldr r0, [sp, #0]
add r1, sp, #4 + 3*4 @ r[3..7] = t3..7, r11=u8, r12=t9
ldmia r1, {r2,r7,r8,r9,r10,r11,r12}
add r1, r0, #3*4
stmia r1, {r2,r7,r8,r9,r10}
bic r2, r3, field_not_M @ r[8] = c & M
str r2, [r0, #8*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u8 * R1
umlal r3, r4, r11, r14
movw r14, field_R0 @ c += d * R0
umlal r3, r4, r5, r14
adds r3, r3, r12 @ c += t9
adc r4, r4, #0
add r1, sp, #4 + 0*4 @ r7,r8,r9 = t0,t1,t2
ldmia r1, {r7,r8,r9}
ubfx r2, r3, #0, #22 @ r[9] = c & (M >> 4)
str r2, [r0, #9*4]
mov r3, r3, lsr #22 @ c >>= 22
orr r3, r3, r4, asl #10
mov r4, r4, lsr #22
movw r14, field_R1 << 4 @ c += d * (R1 << 4)
umlal r3, r4, r5, r14
movw r14, field_R0 >> 4 @ d = c * (R0 >> 4) + t0 (64x64 multiply+add)
umull r5, r6, r3, r14 @ d = c.lo * (R0 >> 4)
adds r5, r5, r7 @ d.lo += t0
mla r6, r14, r4, r6 @ d.hi += c.hi * (R0 >> 4)
adc r6, r6, 0 @ d.hi += carry
bic r2, r5, field_not_M @ r[0] = d & M
str r2, [r0, #0*4]
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R1 >> 4 @ d += c * (R1 >> 4) + t1 (64x64 multiply+add)
umull r1, r2, r3, r14 @ tmp = c.lo * (R1 >> 4)
adds r5, r5, r8 @ d.lo += t1
adc r6, r6, #0 @ d.hi += carry
adds r5, r5, r1 @ d.lo += tmp.lo
mla r2, r14, r4, r2 @ tmp.hi += c.hi * (R1 >> 4)
adc r6, r6, r2 @ d.hi += carry + tmp.hi
bic r2, r5, field_not_M @ r[1] = d & M
str r2, [r0, #1*4]
mov r5, r5, lsr #26 @ d >>= 26 (ignore hi)
orr r5, r5, r6, asl #6
add r5, r5, r9 @ d += t2
str r5, [r0, #2*4] @ r[2] = d
add sp, sp, #48
ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc}
.size secp256k1_fe_sqr_inner, .-secp256k1_fe_sqr_inner
|
LearningOS/arceos-classroom-2025s-arceos-2025s-oscamp-stage3 | 4,857 | arceos/exercises/simple_hv/src/guest.S |
/// Enter the guest given in `VmCpuRegisters` from `a0`
.global _run_guest
_run_guest:
/* Save hypervisor state */
/* Save hypervisor GPRs (except T0-T6 and a0, which is GuestInfo and stashed in sscratch) */
sd ra, ({hyp_ra})(a0)
sd gp, ({hyp_gp})(a0)
sd tp, ({hyp_tp})(a0)
sd s0, ({hyp_s0})(a0)
sd s1, ({hyp_s1})(a0)
sd a1, ({hyp_a1})(a0)
sd a2, ({hyp_a2})(a0)
sd a3, ({hyp_a3})(a0)
sd a4, ({hyp_a4})(a0)
sd a5, ({hyp_a5})(a0)
sd a6, ({hyp_a6})(a0)
sd a7, ({hyp_a7})(a0)
sd s2, ({hyp_s2})(a0)
sd s3, ({hyp_s3})(a0)
sd s4, ({hyp_s4})(a0)
sd s5, ({hyp_s5})(a0)
sd s6, ({hyp_s6})(a0)
sd s7, ({hyp_s7})(a0)
sd s8, ({hyp_s8})(a0)
sd s9, ({hyp_s9})(a0)
sd s10, ({hyp_s10})(a0)
sd s11, ({hyp_s11})(a0)
sd sp, ({hyp_sp})(a0)
/* Swap in guest CSRs. */
ld t1, ({guest_sstatus})(a0)
csrrw t1, sstatus, t1
sd t1, ({hyp_sstatus})(a0)
ld t1, ({guest_hstatus})(a0)
csrrw t1, hstatus, t1
ld t1, ({guest_scounteren})(a0)
csrrw t1, scounteren, t1
sd t1, ({hyp_scounteren})(a0)
ld t1, ({guest_sepc})(a0)
csrw sepc, t1
/* Set stvec so that hypervisor resumes after the sret when the guest exits. */
la t1, _guest_exit
csrrw t1, stvec, t1
sd t1, ({hyp_stvec})(a0)
/* Save sscratch and replace with pointer to GuestInfo. */
csrrw t1, sscratch, a0
sd t1, ({hyp_sscratch})(a0)
/* Restore the gprs from this GuestInfo */
ld ra, ({guest_ra})(a0)
ld gp, ({guest_gp})(a0)
ld tp, ({guest_tp})(a0)
ld s0, ({guest_s0})(a0)
ld s1, ({guest_s1})(a0)
ld a1, ({guest_a1})(a0)
ld a2, ({guest_a2})(a0)
ld a3, ({guest_a3})(a0)
ld a4, ({guest_a4})(a0)
ld a5, ({guest_a5})(a0)
ld a6, ({guest_a6})(a0)
ld a7, ({guest_a7})(a0)
ld s2, ({guest_s2})(a0)
ld s3, ({guest_s3})(a0)
ld s4, ({guest_s4})(a0)
ld s5, ({guest_s5})(a0)
ld s6, ({guest_s6})(a0)
ld s7, ({guest_s7})(a0)
ld s8, ({guest_s8})(a0)
ld s9, ({guest_s9})(a0)
ld s10, ({guest_s10})(a0)
ld s11, ({guest_s11})(a0)
ld t0, ({guest_t0})(a0)
ld t1, ({guest_t1})(a0)
ld t2, ({guest_t2})(a0)
ld t3, ({guest_t3})(a0)
ld t4, ({guest_t4})(a0)
ld t5, ({guest_t5})(a0)
ld t6, ({guest_t6})(a0)
ld sp, ({guest_sp})(a0)
ld a0, ({guest_a0})(a0)
sret
.align 2
_guest_exit:
/* Pull GuestInfo out of sscratch, swapping with guest's a0 */
csrrw a0, sscratch, a0
/* Save guest GPRs. */
sd ra, ({guest_ra})(a0)
sd gp, ({guest_gp})(a0)
sd tp, ({guest_tp})(a0)
sd s0, ({guest_s0})(a0)
sd s1, ({guest_s1})(a0)
sd a1, ({guest_a1})(a0)
sd a2, ({guest_a2})(a0)
sd a3, ({guest_a3})(a0)
sd a4, ({guest_a4})(a0)
sd a5, ({guest_a5})(a0)
sd a6, ({guest_a6})(a0)
sd a7, ({guest_a7})(a0)
sd s2, ({guest_s2})(a0)
sd s3, ({guest_s3})(a0)
sd s4, ({guest_s4})(a0)
sd s5, ({guest_s5})(a0)
sd s6, ({guest_s6})(a0)
sd s7, ({guest_s7})(a0)
sd s8, ({guest_s8})(a0)
sd s9, ({guest_s9})(a0)
sd s10, ({guest_s10})(a0)
sd s11, ({guest_s11})(a0)
sd t0, ({guest_t0})(a0)
sd t1, ({guest_t1})(a0)
sd t2, ({guest_t2})(a0)
sd t3, ({guest_t3})(a0)
sd t4, ({guest_t4})(a0)
sd t5, ({guest_t5})(a0)
sd t6, ({guest_t6})(a0)
sd sp, ({guest_sp})(a0)
/* Save Guest a0 after recovering from sscratch. */
csrr t0, sscratch
sd t0, ({guest_a0})(a0)
_restore_csrs:
/* Swap in hypervisor CSRs. */
ld t1, ({hyp_sstatus})(a0)
csrrw t1, sstatus, t1
sd t1, ({guest_sstatus})(a0)
csrr t1, hstatus
sd t1, ({guest_hstatus})(a0)
ld t1, ({hyp_scounteren})(a0)
csrrw t1, scounteren, t1
sd t1, ({guest_scounteren})(a0)
ld t1, ({hyp_stvec})(a0)
csrw stvec, t1
ld t1, ({hyp_sscratch})(a0)
csrw sscratch, t1
/* Save guest EPC. */
csrr t1, sepc
sd t1, ({guest_sepc})(a0)
/* Restore hypervisor GPRs. */
ld ra, ({hyp_ra})(a0)
ld gp, ({hyp_gp})(a0)
ld tp, ({hyp_tp})(a0)
ld s0, ({hyp_s0})(a0)
ld s1, ({hyp_s1})(a0)
ld a1, ({hyp_a1})(a0)
ld a2, ({hyp_a2})(a0)
ld a3, ({hyp_a3})(a0)
ld a4, ({hyp_a4})(a0)
ld a5, ({hyp_a5})(a0)
ld a6, ({hyp_a6})(a0)
ld a7, ({hyp_a7})(a0)
ld s2, ({hyp_s2})(a0)
ld s3, ({hyp_s3})(a0)
ld s4, ({hyp_s4})(a0)
ld s5, ({hyp_s5})(a0)
ld s6, ({hyp_s6})(a0)
ld s7, ({hyp_s7})(a0)
ld s8, ({hyp_s8})(a0)
ld s9, ({hyp_s9})(a0)
ld s10, ({hyp_s10})(a0)
ld s11, ({hyp_s11})(a0)
ld sp, ({hyp_sp})(a0)
ret
|
LearningOS/arceos-classroom-2025s-arceos-2025s-oscamp-stage3 | 2,544 | arceos/tools/raspi4/chainloader/src/_arch/aarch64/cpu/boot.s | // SPDX-License-Identifier: MIT OR Apache-2.0
//
// Copyright (c) 2021-2022 Andre Richter <andre.o.richter@gmail.com>
//--------------------------------------------------------------------------------------------------
// Definitions
//--------------------------------------------------------------------------------------------------
// Load the address of a symbol into a register, PC-relative.
//
// The symbol must lie within +/- 4 GiB of the Program Counter.
//
// # Resources
//
// - https://sourceware.org/binutils/docs-2.36/as/AArch64_002dRelocations.html
.macro ADR_REL register, symbol
adrp \register, \symbol
add \register, \register, #:lo12:\symbol
.endm
// Load the address of a symbol into a register, absolute.
//
// # Resources
//
// - https://sourceware.org/binutils/docs-2.36/as/AArch64_002dRelocations.html
.macro ADR_ABS register, symbol
movz \register, #:abs_g2:\symbol
movk \register, #:abs_g1_nc:\symbol
movk \register, #:abs_g0_nc:\symbol
.endm
//--------------------------------------------------------------------------------------------------
// Public Code
//--------------------------------------------------------------------------------------------------
.section .text._start
//------------------------------------------------------------------------------
// fn _start()
//------------------------------------------------------------------------------
_start:
// Only proceed on the boot core. Park it otherwise.
mrs x0, MPIDR_EL1
and x0, x0, {CONST_CORE_ID_MASK}
ldr x1, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
cmp x0, x1
b.ne .L_parking_loop
// If execution reaches here, it is the boot core.
// Initialize DRAM.
ADR_ABS x0, __bss_start
ADR_ABS x1, __bss_end_exclusive
.L_bss_init_loop:
cmp x0, x1
b.eq .L_relocate_binary
stp xzr, xzr, [x0], #16
b .L_bss_init_loop
// Next, relocate the binary.
.L_relocate_binary:
ADR_REL x0, __binary_nonzero_start // The address the binary got loaded to.
ADR_ABS x1, __binary_nonzero_start // The address the binary was linked to.
ADR_ABS x2, __binary_nonzero_end_exclusive
.L_copy_loop:
ldr x3, [x0], #8
str x3, [x1], #8
cmp x1, x2
b.lo .L_copy_loop
// Prepare the jump to Rust code.
// Set the stack pointer.
ADR_ABS x0, __boot_core_stack_end_exclusive
mov sp, x0
// Jump to the relocated Rust code.
ADR_ABS x1, _start_rust
br x1
// Infinitely wait for events (aka "park the core").
.L_parking_loop:
wfe
b .L_parking_loop
.size _start, . - _start
.type _start, function
.global _start
|
LearningOS/arceos-classroom-2025s-arceos-2025s-oscamp-stage3 | 1,827 | arceos/modules/axhal/linker.lds.S | OUTPUT_ARCH(%ARCH%)
BASE_ADDRESS = %KERNEL_BASE%;
ENTRY(_start)
SECTIONS
{
. = BASE_ADDRESS;
_skernel = .;
.text : ALIGN(4K) {
_stext = .;
*(.text.boot)
*(.text .text.*)
. = ALIGN(4K);
_etext = .;
}
.rodata : ALIGN(4K) {
_srodata = .;
*(.rodata .rodata.*)
*(.srodata .srodata.*)
*(.sdata2 .sdata2.*)
. = ALIGN(4K);
_erodata = .;
}
.data : ALIGN(4K) {
_sdata = .;
*(.data.boot_page_table)
. = ALIGN(4K);
*(.data .data.*)
*(.sdata .sdata.*)
*(.got .got.*)
}
.tdata : ALIGN(0x10) {
_stdata = .;
*(.tdata .tdata.*)
_etdata = .;
}
.tbss : ALIGN(0x10) {
_stbss = .;
*(.tbss .tbss.*)
*(.tcommon)
_etbss = .;
}
. = ALIGN(4K);
_percpu_start = .;
_percpu_end = _percpu_start + SIZEOF(.percpu);
.percpu 0x0 : AT(_percpu_start) {
_percpu_load_start = .;
*(.percpu .percpu.*)
_percpu_load_end = .;
. = _percpu_load_start + ALIGN(64) * %SMP%;
}
. = _percpu_end;
. = ALIGN(4K);
_edata = .;
.bss : ALIGN(4K) {
boot_stack = .;
*(.bss.stack)
. = ALIGN(4K);
boot_stack_top = .;
_sbss = .;
*(.bss .bss.*)
*(.sbss .sbss.*)
*(COMMON)
. = ALIGN(4K);
_ebss = .;
}
_ekernel = .;
/DISCARD/ : {
*(.comment) *(.gnu*) *(.note*) *(.eh_frame*)
}
}
SECTIONS {
linkme_IRQ : { *(linkme_IRQ) }
linkm2_IRQ : { *(linkm2_IRQ) }
linkme_PAGE_FAULT : { *(linkme_PAGE_FAULT) }
linkm2_PAGE_FAULT : { *(linkm2_PAGE_FAULT) }
linkme_SYSCALL : { *(linkme_SYSCALL) }
linkm2_SYSCALL : { *(linkm2_SYSCALL) }
}
INSERT AFTER .tbss;
|
LearningOS/arceos-classroom-2025s-arceos-2025s-oscamp-stage3 | 4,857 | arceos/modules/riscv_vcpu/src/guest.S |
/// Enter the guest given in `VmCpuRegisters` from `a0`
.global _run_guest
_run_guest:
/* Save hypervisor state */
/* Save hypervisor GPRs (except T0-T6 and a0, which is GuestInfo and stashed in sscratch) */
sd ra, ({hyp_ra})(a0)
sd gp, ({hyp_gp})(a0)
sd tp, ({hyp_tp})(a0)
sd s0, ({hyp_s0})(a0)
sd s1, ({hyp_s1})(a0)
sd a1, ({hyp_a1})(a0)
sd a2, ({hyp_a2})(a0)
sd a3, ({hyp_a3})(a0)
sd a4, ({hyp_a4})(a0)
sd a5, ({hyp_a5})(a0)
sd a6, ({hyp_a6})(a0)
sd a7, ({hyp_a7})(a0)
sd s2, ({hyp_s2})(a0)
sd s3, ({hyp_s3})(a0)
sd s4, ({hyp_s4})(a0)
sd s5, ({hyp_s5})(a0)
sd s6, ({hyp_s6})(a0)
sd s7, ({hyp_s7})(a0)
sd s8, ({hyp_s8})(a0)
sd s9, ({hyp_s9})(a0)
sd s10, ({hyp_s10})(a0)
sd s11, ({hyp_s11})(a0)
sd sp, ({hyp_sp})(a0)
/* Swap in guest CSRs. */
ld t1, ({guest_sstatus})(a0)
csrrw t1, sstatus, t1
sd t1, ({hyp_sstatus})(a0)
ld t1, ({guest_hstatus})(a0)
csrrw t1, hstatus, t1
ld t1, ({guest_scounteren})(a0)
csrrw t1, scounteren, t1
sd t1, ({hyp_scounteren})(a0)
ld t1, ({guest_sepc})(a0)
csrw sepc, t1
/* Set stvec so that hypervisor resumes after the sret when the guest exits. */
la t1, _guest_exit
csrrw t1, stvec, t1
sd t1, ({hyp_stvec})(a0)
/* Save sscratch and replace with pointer to GuestInfo. */
csrrw t1, sscratch, a0
sd t1, ({hyp_sscratch})(a0)
/* Restore the gprs from this GuestInfo */
ld ra, ({guest_ra})(a0)
ld gp, ({guest_gp})(a0)
ld tp, ({guest_tp})(a0)
ld s0, ({guest_s0})(a0)
ld s1, ({guest_s1})(a0)
ld a1, ({guest_a1})(a0)
ld a2, ({guest_a2})(a0)
ld a3, ({guest_a3})(a0)
ld a4, ({guest_a4})(a0)
ld a5, ({guest_a5})(a0)
ld a6, ({guest_a6})(a0)
ld a7, ({guest_a7})(a0)
ld s2, ({guest_s2})(a0)
ld s3, ({guest_s3})(a0)
ld s4, ({guest_s4})(a0)
ld s5, ({guest_s5})(a0)
ld s6, ({guest_s6})(a0)
ld s7, ({guest_s7})(a0)
ld s8, ({guest_s8})(a0)
ld s9, ({guest_s9})(a0)
ld s10, ({guest_s10})(a0)
ld s11, ({guest_s11})(a0)
ld t0, ({guest_t0})(a0)
ld t1, ({guest_t1})(a0)
ld t2, ({guest_t2})(a0)
ld t3, ({guest_t3})(a0)
ld t4, ({guest_t4})(a0)
ld t5, ({guest_t5})(a0)
ld t6, ({guest_t6})(a0)
ld sp, ({guest_sp})(a0)
ld a0, ({guest_a0})(a0)
sret
.align 2
_guest_exit:
/* Pull GuestInfo out of sscratch, swapping with guest's a0 */
csrrw a0, sscratch, a0
/* Save guest GPRs. */
sd ra, ({guest_ra})(a0)
sd gp, ({guest_gp})(a0)
sd tp, ({guest_tp})(a0)
sd s0, ({guest_s0})(a0)
sd s1, ({guest_s1})(a0)
sd a1, ({guest_a1})(a0)
sd a2, ({guest_a2})(a0)
sd a3, ({guest_a3})(a0)
sd a4, ({guest_a4})(a0)
sd a5, ({guest_a5})(a0)
sd a6, ({guest_a6})(a0)
sd a7, ({guest_a7})(a0)
sd s2, ({guest_s2})(a0)
sd s3, ({guest_s3})(a0)
sd s4, ({guest_s4})(a0)
sd s5, ({guest_s5})(a0)
sd s6, ({guest_s6})(a0)
sd s7, ({guest_s7})(a0)
sd s8, ({guest_s8})(a0)
sd s9, ({guest_s9})(a0)
sd s10, ({guest_s10})(a0)
sd s11, ({guest_s11})(a0)
sd t0, ({guest_t0})(a0)
sd t1, ({guest_t1})(a0)
sd t2, ({guest_t2})(a0)
sd t3, ({guest_t3})(a0)
sd t4, ({guest_t4})(a0)
sd t5, ({guest_t5})(a0)
sd t6, ({guest_t6})(a0)
sd sp, ({guest_sp})(a0)
/* Save Guest a0 after recovering from sscratch. */
csrr t0, sscratch
sd t0, ({guest_a0})(a0)
_restore_csrs:
/* Swap in hypervisor CSRs. */
ld t1, ({hyp_sstatus})(a0)
csrrw t1, sstatus, t1
sd t1, ({guest_sstatus})(a0)
csrr t1, hstatus
sd t1, ({guest_hstatus})(a0)
ld t1, ({hyp_scounteren})(a0)
csrrw t1, scounteren, t1
sd t1, ({guest_scounteren})(a0)
ld t1, ({hyp_stvec})(a0)
csrw stvec, t1
ld t1, ({hyp_sscratch})(a0)
csrw sscratch, t1
/* Save guest EPC. */
csrr t1, sepc
sd t1, ({guest_sepc})(a0)
/* Restore hypervisor GPRs. */
ld ra, ({hyp_ra})(a0)
ld gp, ({hyp_gp})(a0)
ld tp, ({hyp_tp})(a0)
ld s0, ({hyp_s0})(a0)
ld s1, ({hyp_s1})(a0)
ld a1, ({hyp_a1})(a0)
ld a2, ({hyp_a2})(a0)
ld a3, ({hyp_a3})(a0)
ld a4, ({hyp_a4})(a0)
ld a5, ({hyp_a5})(a0)
ld a6, ({hyp_a6})(a0)
ld a7, ({hyp_a7})(a0)
ld s2, ({hyp_s2})(a0)
ld s3, ({hyp_s3})(a0)
ld s4, ({hyp_s4})(a0)
ld s5, ({hyp_s5})(a0)
ld s6, ({hyp_s6})(a0)
ld s7, ({hyp_s7})(a0)
ld s8, ({hyp_s8})(a0)
ld s9, ({hyp_s9})(a0)
ld s10, ({hyp_s10})(a0)
ld s11, ({hyp_s11})(a0)
ld sp, ({hyp_sp})(a0)
ret
|
LearningOS/arceos-classroom-2025s-arceos-2025s-oscamp-stage3 | 3,437 | arceos/modules/riscv_vcpu/src/mem_extable.S | // Copyright (c) 2022 by Rivos Inc.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
// Very unoptimized memcpy() to/from guest memory functions, using the HLV/HSV instructions.
// Adds the instruction at 'lbl' to the exception table.
.macro add_extable lbl
.pushsection .extable, "a"
.balign 8
.quad \lbl
.popsection
.endm
.option push
.option arch, +h
.section .text
// memcpy() to a guest physical address using HSV.
.global _copy_to_guest
_copy_to_guest:
// handle_trap assumes t0 holds the address of where we want to jump to when we encounter
// a fault and will stick SCAUSE in t1.
la t0, _ret_from_copy
// _ret_from_copy assumes the return value is in t2.
mv t2, zero
1:
beq t2, a2, _ret_from_copy
lb t3, (a1)
2:
hsv.b t3, (a0)
add_extable 2b
addi a0, a0, 1
addi a1, a1, 1
addi t2, t2, 1
j 1b
// memcpy() from a guest physical address using HLV.
.global _copy_from_guest
_copy_from_guest:
// handle_trap assumes t0 holds the address of where we want to jump to when we encounter
// a fault and will stick SCAUSE in t1.
la t0, _ret_from_copy
// _ret_from_copy assumes the return value is in t2.
mv t2, zero
1:
beq t2, a2, _ret_from_copy
2:
hlv.b t3, (a1)
add_extable 2b
sb t3, (a0)
addi a0, a0, 1
addi a1, a1, 1
addi t2, t2, 1
j 1b
// Fetch an instruction from guest memory using HLVX. Only supports 2 or 4 byte instructions.
//
// Arguments:
// A0: Guest address of the instruction to fetch, using the translation modes/tables currently
// programmed in HGATP and VSATP.
// A1: Pointer to a u32 where the instruction will be written.
//
// Returns -1 on error.
.global _fetch_guest_instruction
_fetch_guest_instruction:
// handle_trap assumes t0 holds the address of where we want to jump to when we encounter
// a fault and will stick SCAUSE in t1.
la t0, 4f
1:
hlvx.hu t2, (a0)
add_extable 1b
sh t2, (a1)
addi a0, a0, 2
addi a1, a1, 2
// If it's a compressed instrution (bits [1:0] != 'b11) then we're done.
li t3, 3
and t2, t2, t3
bne t2, t3, 3f
// Load the next half-word.
2:
hlvx.hu t2, (a0)
add_extable 2b
sh t2, (a1)
3:
mv a0, zero
ret
4:
// Took a fault, return -1.
not a0, zero
ret
// memcpy() to a user address.
.global _copy_to_user
_copy_to_user:
// handle_trap assumes t0 holds the address of where we want to jump to when we encounter
// a fault and will stick SCAUSE in t1.
la t0, _ret_from_copy
// _ret_from_copy assumes the return value is in t2.
mv t2, zero
1:
beq t2, a2, _ret_from_copy
lb t3, (a1)
2:
sb t3, (a0)
add_extable 2b
addi a0, a0, 1
addi a1, a1, 1
addi t2, t2, 1
j 1b
// memcpy() from a user address.
.global _copy_from_user
_copy_from_user:
// handle_trap assumes t0 holds the address of where we want to jump to when we encounter
// a fault and will stick SCAUSE in t1.
la t0, _ret_from_copy
// _ret_from_copy assumes the return value is in t2.
mv t2, zero
1:
beq t2, a2, _ret_from_copy
2:
lb t3, (a1)
add_extable 2b
sb t3, (a0)
addi a0, a0, 1
addi a1, a1, 1
addi t2, t2, 1
j 1b
.align 2
_ret_from_copy:
mv a0, t2
ret
.option pop |
LearningOS/arceos-classroom-2025s-arceos-2025s-oscamp-stage3 | 4,307 | arceos/modules/axhal/src/platform/x86_pc/multiboot.S | # Bootstrapping from 32-bit with the Multiboot specification.
# See https://www.gnu.org/software/grub/manual/multiboot/multiboot.html
.section .text.boot
.code32
.global _start
_start:
mov edi, eax # arg1: magic: 0x2BADB002
mov esi, ebx # arg2: multiboot info
jmp bsp_entry32
.balign 4
.type multiboot_header, STT_OBJECT
multiboot_header:
.int {mb_hdr_magic} # magic: 0x1BADB002
.int {mb_hdr_flags} # flags
.int -({mb_hdr_magic} + {mb_hdr_flags}) # checksum
.int multiboot_header - {offset} # header_addr
.int _skernel - {offset} # load_addr
.int _edata - {offset} # load_end
.int _ebss - {offset} # bss_end_addr
.int _start - {offset} # entry_addr
# Common code in 32-bit, prepare states to enter 64-bit.
.macro ENTRY32_COMMON
# set data segment selectors
mov ax, 0x18
mov ss, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
# set PAE, PGE bit in CR4
mov eax, {cr4}
mov cr4, eax
# load the temporary page table
lea eax, [.Ltmp_pml4 - {offset}]
mov cr3, eax
# set LME, NXE bit in IA32_EFER
mov ecx, {efer_msr}
mov edx, 0
mov eax, {efer}
wrmsr
# set protected mode, write protect, paging bit in CR0
mov eax, {cr0}
mov cr0, eax
.endm
# Common code in 64-bit
.macro ENTRY64_COMMON
# clear segment selectors
xor ax, ax
mov ss, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
.endm
.code32
bsp_entry32:
lgdt [.Ltmp_gdt_desc - {offset}] # load the temporary GDT
ENTRY32_COMMON
ljmp 0x10, offset bsp_entry64 - {offset} # 0x10 is code64 segment
.code32
.global ap_entry32
ap_entry32:
ENTRY32_COMMON
ljmp 0x10, offset ap_entry64 - {offset} # 0x10 is code64 segment
.code64
bsp_entry64:
ENTRY64_COMMON
# set RSP to boot stack
movabs rsp, offset {boot_stack}
add rsp, {boot_stack_size}
# call rust_entry(magic, mbi)
movabs rax, offset {entry}
call rax
jmp .Lhlt
.code64
ap_entry64:
ENTRY64_COMMON
# set RSP to high address (already set in ap_start.S)
mov rax, {offset}
add rsp, rax
# call rust_entry_secondary(magic)
mov rdi, {mb_magic}
movabs rax, offset {entry_secondary}
call rax
jmp .Lhlt
.Lhlt:
hlt
jmp .Lhlt
.section .rodata
.balign 8
.Ltmp_gdt_desc:
.short .Ltmp_gdt_end - .Ltmp_gdt - 1 # limit
.long .Ltmp_gdt - {offset} # base
.section .data
.balign 16
.Ltmp_gdt:
.quad 0x0000000000000000 # 0x00: null
.quad 0x00cf9b000000ffff # 0x08: code segment (base=0, limit=0xfffff, type=32bit code exec/read, DPL=0, 4k)
.quad 0x00af9b000000ffff # 0x10: code segment (base=0, limit=0xfffff, type=64bit code exec/read, DPL=0, 4k)
.quad 0x00cf93000000ffff # 0x18: data segment (base=0, limit=0xfffff, type=32bit data read/write, DPL=0, 4k)
.Ltmp_gdt_end:
.balign 4096
.Ltmp_pml4:
# 0x0000_0000 ~ 0xffff_ffff
.quad .Ltmp_pdpt_low - {offset} + 0x3 # PRESENT | WRITABLE | paddr(tmp_pdpt)
.zero 8 * 510
# 0xffff_ff80_0000_0000 ~ 0xffff_ff80_ffff_ffff
.quad .Ltmp_pdpt_high - {offset} + 0x3 # PRESENT | WRITABLE | paddr(tmp_pdpt)
# FIXME: may not work on macOS using hvf as the CPU does not support 1GB page (pdpe1gb)
.Ltmp_pdpt_low:
.quad 0x0000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x0)
.quad 0x40000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x4000_0000)
.quad 0x80000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x8000_0000)
.quad 0xc0000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0xc000_0000)
.zero 8 * 508
.Ltmp_pdpt_high:
.quad 0x0000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x0)
.quad 0x40000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x4000_0000)
.quad 0x80000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x8000_0000)
.quad 0xc0000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0xc000_0000)
.zero 8 * 508
|
LearningOS/arceos-classroom-2025s-arceos-2025s-oscamp-stage3 | 1,965 | arceos/modules/axhal/src/platform/x86_pc/ap_start.S | # Boot application processors into the protected mode.
# Each non-boot CPU ("AP") is started up in response to a STARTUP
# IPI from the boot CPU. Section B.4.2 of the Multi-Processor
# Specification says that the AP will start in real mode with CS:IP
# set to XY00:0000, where XY is an 8-bit value sent with the
# STARTUP. Thus this code must start at a 4096-byte boundary.
#
# Because this code sets DS to zero, it must sit
# at an address in the low 2^16 bytes.
.equ pa_ap_start32, ap_start32 - ap_start + {start_page_paddr}
.equ pa_ap_gdt, .Lap_tmp_gdt - ap_start + {start_page_paddr}
.equ pa_ap_gdt_desc, .Lap_tmp_gdt_desc - ap_start + {start_page_paddr}
.equ stack_ptr, {start_page_paddr} + 0xff0
.equ entry_ptr, {start_page_paddr} + 0xff8
# 0x6000
.section .text
.code16
.p2align 12
.global ap_start
ap_start:
cli
wbinvd
xor ax, ax
mov ds, ax
mov es, ax
mov ss, ax
mov fs, ax
mov gs, ax
# load the 64-bit GDT
lgdt [pa_ap_gdt_desc]
# switch to protected-mode
mov eax, cr0
or eax, (1 << 0)
mov cr0, eax
# far jump to 32-bit code. 0x8 is code32 segment selector
ljmp 0x8, offset pa_ap_start32
.code32
ap_start32:
mov esp, [stack_ptr]
mov eax, [entry_ptr]
jmp eax
.balign 8
# .type multiboot_header, STT_OBJECT
.Lap_tmp_gdt_desc:
.short .Lap_tmp_gdt_end - .Lap_tmp_gdt - 1 # limit
.long pa_ap_gdt # base
.balign 16
.Lap_tmp_gdt:
.quad 0x0000000000000000 # 0x00: null
.quad 0x00cf9b000000ffff # 0x08: code segment (base=0, limit=0xfffff, type=32bit code exec/read, DPL=0, 4k)
.quad 0x00af9b000000ffff # 0x10: code segment (base=0, limit=0xfffff, type=64bit code exec/read, DPL=0, 4k)
.quad 0x00cf93000000ffff # 0x18: data segment (base=0, limit=0xfffff, type=32bit data read/write, DPL=0, 4k)
.Lap_tmp_gdt_end:
# 0x7000
.p2align 12
.global ap_end
ap_end:
|
LearningOS/arceos-classroom-2025s-arceos-2025s-oscamp-stage3 | 2,415 | arceos/modules/axhal/src/arch/aarch64/trap.S | .macro SAVE_REGS
sub sp, sp, 34 * 8
stp x0, x1, [sp]
stp x2, x3, [sp, 2 * 8]
stp x4, x5, [sp, 4 * 8]
stp x6, x7, [sp, 6 * 8]
stp x8, x9, [sp, 8 * 8]
stp x10, x11, [sp, 10 * 8]
stp x12, x13, [sp, 12 * 8]
stp x14, x15, [sp, 14 * 8]
stp x16, x17, [sp, 16 * 8]
stp x18, x19, [sp, 18 * 8]
stp x20, x21, [sp, 20 * 8]
stp x22, x23, [sp, 22 * 8]
stp x24, x25, [sp, 24 * 8]
stp x26, x27, [sp, 26 * 8]
stp x28, x29, [sp, 28 * 8]
mrs x9, sp_el0
mrs x10, elr_el1
mrs x11, spsr_el1
stp x30, x9, [sp, 30 * 8]
stp x10, x11, [sp, 32 * 8]
.endm
.macro RESTORE_REGS
ldp x10, x11, [sp, 32 * 8]
ldp x30, x9, [sp, 30 * 8]
msr sp_el0, x9
msr elr_el1, x10
msr spsr_el1, x11
ldp x28, x29, [sp, 28 * 8]
ldp x26, x27, [sp, 26 * 8]
ldp x24, x25, [sp, 24 * 8]
ldp x22, x23, [sp, 22 * 8]
ldp x20, x21, [sp, 20 * 8]
ldp x18, x19, [sp, 18 * 8]
ldp x16, x17, [sp, 16 * 8]
ldp x14, x15, [sp, 14 * 8]
ldp x12, x13, [sp, 12 * 8]
ldp x10, x11, [sp, 10 * 8]
ldp x8, x9, [sp, 8 * 8]
ldp x6, x7, [sp, 6 * 8]
ldp x4, x5, [sp, 4 * 8]
ldp x2, x3, [sp, 2 * 8]
ldp x0, x1, [sp]
add sp, sp, 34 * 8
.endm
.macro INVALID_EXCP, kind, source
.p2align 7
SAVE_REGS
mov x0, sp
mov x1, \kind
mov x2, \source
bl invalid_exception
b .Lexception_return
.endm
.macro HANDLE_SYNC
.p2align 7
SAVE_REGS
mov x0, sp
bl handle_sync_exception
b .Lexception_return
.endm
.macro HANDLE_IRQ
.p2align 7
SAVE_REGS
mov x0, sp
bl handle_irq_exception
b .Lexception_return
.endm
.section .text
.p2align 11
.global exception_vector_base
exception_vector_base:
// current EL, with SP_EL0
INVALID_EXCP 0 0
INVALID_EXCP 1 0
INVALID_EXCP 2 0
INVALID_EXCP 3 0
// current EL, with SP_ELx
HANDLE_SYNC
HANDLE_IRQ
INVALID_EXCP 2 1
INVALID_EXCP 3 1
// lower EL, aarch64
HANDLE_SYNC
HANDLE_IRQ
INVALID_EXCP 2 2
INVALID_EXCP 3 2
// lower EL, aarch32
INVALID_EXCP 0 3
INVALID_EXCP 1 3
INVALID_EXCP 2 3
INVALID_EXCP 3 3
.Lexception_return:
RESTORE_REGS
eret
|
LearningOS/arceos-classroom-2025s-arceos-2025s-oscamp-stage3 | 1,839 | arceos/modules/axhal/src/arch/riscv/trap.S | .macro SAVE_REGS, from_user
addi sp, sp, -{trapframe_size}
PUSH_GENERAL_REGS
csrr t0, sepc
csrr t1, sstatus
csrrw t2, sscratch, zero // save sscratch (sp) and zero it
STR t0, sp, 31 // tf.sepc
STR t1, sp, 32 // tf.sstatus
STR t2, sp, 1 // tf.regs.sp
.if \from_user == 1
LDR t0, sp, 2 // load supervisor gp
LDR t1, sp, 3 // load supervisor tp
STR gp, sp, 2 // save user gp and tp
STR tp, sp, 3
mv gp, t0
mv tp, t1
.endif
.endm
.macro RESTORE_REGS, from_user
.if \from_user == 1
LDR t1, sp, 2 // load user gp and tp
LDR t0, sp, 3
STR gp, sp, 2 // save supervisor gp
STR tp, sp, 3 // save supervisor gp and tp
mv gp, t1
mv tp, t0
addi t0, sp, {trapframe_size} // put supervisor sp to scratch
csrw sscratch, t0
.endif
LDR t0, sp, 31
LDR t1, sp, 32
csrw sepc, t0
csrw sstatus, t1
POP_GENERAL_REGS
LDR sp, sp, 1 // load sp from tf.regs.sp
.endm
.section .text
.balign 4
.global trap_vector_base
trap_vector_base:
// sscratch == 0: trap from S mode
// sscratch != 0: trap from U mode
csrrw sp, sscratch, sp // swap sscratch and sp
bnez sp, .Ltrap_entry_u
csrr sp, sscratch // put supervisor sp back
j .Ltrap_entry_s
.Ltrap_entry_s:
SAVE_REGS 0
mv a0, sp
li a1, 0
call riscv_trap_handler
RESTORE_REGS 0
sret
.Ltrap_entry_u:
SAVE_REGS 1
mv a0, sp
li a1, 1
call riscv_trap_handler
RESTORE_REGS 1
sret
|
LearningOS/arceos-classroom-2025s-arceos-2025s-oscamp-stage3 | 1,505 | arceos/modules/axhal/src/arch/x86_64/trap.S | .equ NUM_INT, 256
.altmacro
.macro DEF_HANDLER, i
.Ltrap_handler_\i:
.if \i == 8 || (\i >= 10 && \i <= 14) || \i == 17
# error code pushed by CPU
push \i # interrupt vector
jmp .Ltrap_common
.else
push 0 # fill in error code in TrapFrame
push \i # interrupt vector
jmp .Ltrap_common
.endif
.endm
.macro DEF_TABLE_ENTRY, i
.quad .Ltrap_handler_\i
.endm
.section .text
.code64
_trap_handlers:
.set i, 0
.rept NUM_INT
DEF_HANDLER %i
.set i, i + 1
.endr
.Ltrap_common:
test byte ptr [rsp + 3 * 8], 3 # swap GS if it comes from user space
jz 1f
swapgs
1:
push r15
push r14
push r13
push r12
push r11
push r10
push r9
push r8
push rdi
push rsi
push rbp
push rbx
push rdx
push rcx
push rax
mov rdi, rsp
call x86_trap_handler
pop rax
pop rcx
pop rdx
pop rbx
pop rbp
pop rsi
pop rdi
pop r8
pop r9
pop r10
pop r11
pop r12
pop r13
pop r14
pop r15
test byte ptr [rsp + 3 * 8], 3 # swap GS back if return to user space
jz 2f
swapgs
2:
add rsp, 16 # pop vector, error_code
iretq
.section .rodata
.global trap_handler_table
trap_handler_table:
.set i, 0
.rept NUM_INT
DEF_TABLE_ENTRY %i
.set i, i + 1
.endr
|
LearningOS/arceos-classroom-2025s-arceos-2025s-oscamp-stage3 | 4,857 | arceos/tour/h_1_0/src/guest.S |
/// Enter the guest given in `VmCpuRegisters` from `a0`
.global _run_guest
_run_guest:
/* Save hypervisor state */
/* Save hypervisor GPRs (except T0-T6 and a0, which is GuestInfo and stashed in sscratch) */
sd ra, ({hyp_ra})(a0)
sd gp, ({hyp_gp})(a0)
sd tp, ({hyp_tp})(a0)
sd s0, ({hyp_s0})(a0)
sd s1, ({hyp_s1})(a0)
sd a1, ({hyp_a1})(a0)
sd a2, ({hyp_a2})(a0)
sd a3, ({hyp_a3})(a0)
sd a4, ({hyp_a4})(a0)
sd a5, ({hyp_a5})(a0)
sd a6, ({hyp_a6})(a0)
sd a7, ({hyp_a7})(a0)
sd s2, ({hyp_s2})(a0)
sd s3, ({hyp_s3})(a0)
sd s4, ({hyp_s4})(a0)
sd s5, ({hyp_s5})(a0)
sd s6, ({hyp_s6})(a0)
sd s7, ({hyp_s7})(a0)
sd s8, ({hyp_s8})(a0)
sd s9, ({hyp_s9})(a0)
sd s10, ({hyp_s10})(a0)
sd s11, ({hyp_s11})(a0)
sd sp, ({hyp_sp})(a0)
/* Swap in guest CSRs. */
ld t1, ({guest_sstatus})(a0)
csrrw t1, sstatus, t1
sd t1, ({hyp_sstatus})(a0)
ld t1, ({guest_hstatus})(a0)
csrrw t1, hstatus, t1
ld t1, ({guest_scounteren})(a0)
csrrw t1, scounteren, t1
sd t1, ({hyp_scounteren})(a0)
ld t1, ({guest_sepc})(a0)
csrw sepc, t1
/* Set stvec so that hypervisor resumes after the sret when the guest exits. */
la t1, _guest_exit
csrrw t1, stvec, t1
sd t1, ({hyp_stvec})(a0)
/* Save sscratch and replace with pointer to GuestInfo. */
csrrw t1, sscratch, a0
sd t1, ({hyp_sscratch})(a0)
/* Restore the gprs from this GuestInfo */
ld ra, ({guest_ra})(a0)
ld gp, ({guest_gp})(a0)
ld tp, ({guest_tp})(a0)
ld s0, ({guest_s0})(a0)
ld s1, ({guest_s1})(a0)
ld a1, ({guest_a1})(a0)
ld a2, ({guest_a2})(a0)
ld a3, ({guest_a3})(a0)
ld a4, ({guest_a4})(a0)
ld a5, ({guest_a5})(a0)
ld a6, ({guest_a6})(a0)
ld a7, ({guest_a7})(a0)
ld s2, ({guest_s2})(a0)
ld s3, ({guest_s3})(a0)
ld s4, ({guest_s4})(a0)
ld s5, ({guest_s5})(a0)
ld s6, ({guest_s6})(a0)
ld s7, ({guest_s7})(a0)
ld s8, ({guest_s8})(a0)
ld s9, ({guest_s9})(a0)
ld s10, ({guest_s10})(a0)
ld s11, ({guest_s11})(a0)
ld t0, ({guest_t0})(a0)
ld t1, ({guest_t1})(a0)
ld t2, ({guest_t2})(a0)
ld t3, ({guest_t3})(a0)
ld t4, ({guest_t4})(a0)
ld t5, ({guest_t5})(a0)
ld t6, ({guest_t6})(a0)
ld sp, ({guest_sp})(a0)
ld a0, ({guest_a0})(a0)
sret
.align 2
_guest_exit:
/* Pull GuestInfo out of sscratch, swapping with guest's a0 */
csrrw a0, sscratch, a0
/* Save guest GPRs. */
sd ra, ({guest_ra})(a0)
sd gp, ({guest_gp})(a0)
sd tp, ({guest_tp})(a0)
sd s0, ({guest_s0})(a0)
sd s1, ({guest_s1})(a0)
sd a1, ({guest_a1})(a0)
sd a2, ({guest_a2})(a0)
sd a3, ({guest_a3})(a0)
sd a4, ({guest_a4})(a0)
sd a5, ({guest_a5})(a0)
sd a6, ({guest_a6})(a0)
sd a7, ({guest_a7})(a0)
sd s2, ({guest_s2})(a0)
sd s3, ({guest_s3})(a0)
sd s4, ({guest_s4})(a0)
sd s5, ({guest_s5})(a0)
sd s6, ({guest_s6})(a0)
sd s7, ({guest_s7})(a0)
sd s8, ({guest_s8})(a0)
sd s9, ({guest_s9})(a0)
sd s10, ({guest_s10})(a0)
sd s11, ({guest_s11})(a0)
sd t0, ({guest_t0})(a0)
sd t1, ({guest_t1})(a0)
sd t2, ({guest_t2})(a0)
sd t3, ({guest_t3})(a0)
sd t4, ({guest_t4})(a0)
sd t5, ({guest_t5})(a0)
sd t6, ({guest_t6})(a0)
sd sp, ({guest_sp})(a0)
/* Save Guest a0 after recovering from sscratch. */
csrr t0, sscratch
sd t0, ({guest_a0})(a0)
_restore_csrs:
/* Swap in hypervisor CSRs. */
ld t1, ({hyp_sstatus})(a0)
csrrw t1, sstatus, t1
sd t1, ({guest_sstatus})(a0)
csrr t1, hstatus
sd t1, ({guest_hstatus})(a0)
ld t1, ({hyp_scounteren})(a0)
csrrw t1, scounteren, t1
sd t1, ({guest_scounteren})(a0)
ld t1, ({hyp_stvec})(a0)
csrw stvec, t1
ld t1, ({hyp_sscratch})(a0)
csrw sscratch, t1
/* Save guest EPC. */
csrr t1, sepc
sd t1, ({guest_sepc})(a0)
/* Restore hypervisor GPRs. */
ld ra, ({hyp_ra})(a0)
ld gp, ({hyp_gp})(a0)
ld tp, ({hyp_tp})(a0)
ld s0, ({hyp_s0})(a0)
ld s1, ({hyp_s1})(a0)
ld a1, ({hyp_a1})(a0)
ld a2, ({hyp_a2})(a0)
ld a3, ({hyp_a3})(a0)
ld a4, ({hyp_a4})(a0)
ld a5, ({hyp_a5})(a0)
ld a6, ({hyp_a6})(a0)
ld a7, ({hyp_a7})(a0)
ld s2, ({hyp_s2})(a0)
ld s3, ({hyp_s3})(a0)
ld s4, ({hyp_s4})(a0)
ld s5, ({hyp_s5})(a0)
ld s6, ({hyp_s6})(a0)
ld s7, ({hyp_s7})(a0)
ld s8, ({hyp_s8})(a0)
ld s9, ({hyp_s9})(a0)
ld s10, ({hyp_s10})(a0)
ld s11, ({hyp_s11})(a0)
ld sp, ({hyp_sp})(a0)
ret
|
leapmotion/ProjectNorthStar | 8,555 | Electronics/Firmware/src/ArduinoCore/src/core/pulse_asm.S | /*
Copyright (c) 2015 Arduino LLC. All right reserved.
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
The following function has been compiled to ASM with gcc
unsigned long countPulseASM(const volatile uint32_t *port, uint32_t bit, uint32_t stateMask, unsigned long maxloops)
{
unsigned long width = 0;
// wait for any previous pulse to end
while ((*port & bit) == stateMask)
if (--maxloops == 0)
return 0;
// wait for the pulse to start
while ((*port & bit) != stateMask)
if (--maxloops == 0)
return 0;
// wait for the pulse to stop
while ((*port & bit) == stateMask) {
if (++width == maxloops)
return 0;
}
return width;
}
using the command line:
arm-none-eabi-gcc -mcpu=cortex-m0plus -mthumb -c -Os -W -ffunction-sections -fdata-sections \
-nostdlib --param max-inline-insns-single=500 -fno-exceptions -MMD \
-DF_CPU=48000000L -DARDUINO=10602 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD \
-D__SAMD21G18A__ -DUSB_VID=0x2341 -DUSB_PID=0x004d -DUSBCON \
-DUSB_MANUFACTURER="Arduino LLC" -DUSB_PRODUCT="Arduino Zero" \
-I/Code/arduino/build/linux/work/hardware/tools/CMSIS/CMSIS/Include/ \
-I/Code/arduino/build/linux/work/hardware/tools/CMSIS/Device/ATMEL/ \
-I/Code/arduino/build/linux/work/hardware/arduino/samd/cores/arduino \
-I/Code/arduino/build/linux/work/hardware/arduino/samd/variants/arduino_zero \
count.c -Wa,-ahlmsd=output.lst -dp -fverbose-asm -S
The result has been slightly edited to increase readability.
*/
.cpu cortex-m0plus
.fpu softvfp
.eabi_attribute 20, 1 @ Tag_ABI_FP_denormal
.eabi_attribute 21, 1 @ Tag_ABI_FP_exceptions
.eabi_attribute 23, 3 @ Tag_ABI_FP_number_model
.eabi_attribute 24, 1 @ Tag_ABI_align8_needed
.eabi_attribute 25, 1 @ Tag_ABI_align8_preserved
.eabi_attribute 26, 1 @ Tag_ABI_enum_size
.eabi_attribute 30, 4 @ Tag_ABI_optimization_goals
.eabi_attribute 34, 0 @ Tag_CPU_unaligned_access
.eabi_attribute 18, 4 @ Tag_ABI_PCS_wchar_t
.file "count.c"
@ GNU C (GNU Tools for ARM Embedded Processors (Arduino build)) version 4.8.3 20140228 (release) [ARM/embedded-4_8-branch revision 208322] (arm-none-eabi)
@ compiled by GNU C version 4.3.2, GMP version 4.3.2, MPFR version 2.4.2, MPC version 0.8.1
@ GGC heuristics: --param ggc-min-expand=100 --param ggc-min-heapsize=131072
@ options passed:
@ -I /Code/arduino/build/linux/work/hardware/tools/CMSIS/CMSIS/Include/
@ -I /Code/arduino/build/linux/work/hardware/tools/CMSIS/Device/ATMEL/
@ -I /Code/arduino/build/linux/work/hardware/arduino/samd/cores/arduino
@ -I /Code/arduino/build/linux/work/hardware/arduino/samd/variants/arduino_zero
@ -imultilib armv6-m
@ -iprefix /Code/arduino/build/linux/work/hardware/tools/gcc-arm-none-eabi-4.8.3-2014q1/bin/../lib/gcc/arm-none-eabi/4.8.3/
@ -isysroot /Code/arduino/build/linux/work/hardware/tools/gcc-arm-none-eabi-4.8.3-2014q1/bin/../arm-none-eabi
@ -MMD count.d -D__USES_INITFINI__ -D F_CPU=48000000L -D ARDUINO=10602
@ -D ARDUINO_SAMD_ZERO -D ARDUINO_ARCH_SAMD -D __SAMD21G18A__
@ -D USB_VID=0x2341 -D USB_PID=0x004d -D USBCON
@ -D USB_MANUFACTURER=Arduino LLC -D USB_PRODUCT=Arduino Zero count.c
@ -mcpu=cortex-m0plus -mthumb -Os -Wextra -ffunction-sections
@ -fdata-sections -fno-exceptions -fverbose-asm
@ --param max-inline-insns-single=500
@ options enabled: -faggressive-loop-optimizations -fauto-inc-dec
@ -fbranch-count-reg -fcaller-saves -fcombine-stack-adjustments -fcommon
@ -fcompare-elim -fcprop-registers -fcrossjumping -fcse-follow-jumps
@ -fdata-sections -fdefer-pop -fdelete-null-pointer-checks -fdevirtualize
@ -fdwarf2-cfi-asm -fearly-inlining -feliminate-unused-debug-types
@ -fexpensive-optimizations -fforward-propagate -ffunction-cse
@ -ffunction-sections -fgcse -fgcse-lm -fgnu-runtime
@ -fguess-branch-probability -fhoist-adjacent-loads -fident -fif-conversion
@ -fif-conversion2 -findirect-inlining -finline -finline-atomics
@ -finline-functions -finline-functions-called-once
@ -finline-small-functions -fipa-cp -fipa-profile -fipa-pure-const
@ -fipa-reference -fipa-sra -fira-hoist-pressure -fira-share-save-slots
@ -fira-share-spill-slots -fivopts -fkeep-static-consts
@ -fleading-underscore -fmath-errno -fmerge-constants -fmerge-debug-strings
@ -fomit-frame-pointer -foptimize-register-move -foptimize-sibling-calls
@ -fpartial-inlining -fpeephole -fpeephole2 -fprefetch-loop-arrays
@ -freg-struct-return -fregmove -freorder-blocks -freorder-functions
@ -frerun-cse-after-loop -fsched-critical-path-heuristic
@ -fsched-dep-count-heuristic -fsched-group-heuristic -fsched-interblock
@ -fsched-last-insn-heuristic -fsched-pressure -fsched-rank-heuristic
@ -fsched-spec -fsched-spec-insn-heuristic -fsched-stalled-insns-dep
@ -fschedule-insns2 -fsection-anchors -fshow-column -fshrink-wrap
@ -fsigned-zeros -fsplit-ivs-in-unroller -fsplit-wide-types
@ -fstrict-aliasing -fstrict-overflow -fstrict-volatile-bitfields
@ -fsync-libcalls -fthread-jumps -ftoplevel-reorder -ftrapping-math
@ -ftree-bit-ccp -ftree-builtin-call-dce -ftree-ccp -ftree-ch
@ -ftree-coalesce-vars -ftree-copy-prop -ftree-copyrename -ftree-cselim
@ -ftree-dce -ftree-dominator-opts -ftree-dse -ftree-forwprop -ftree-fre
@ -ftree-loop-if-convert -ftree-loop-im -ftree-loop-ivcanon
@ -ftree-loop-optimize -ftree-parallelize-loops= -ftree-phiprop -ftree-pre
@ -ftree-pta -ftree-reassoc -ftree-scev-cprop -ftree-sink
@ -ftree-slp-vectorize -ftree-slsr -ftree-sra -ftree-switch-conversion
@ -ftree-tail-merge -ftree-ter -ftree-vect-loop-version -ftree-vrp
@ -funit-at-a-time -fverbose-asm -fzero-initialized-in-bss -mlittle-endian
@ -mpic-data-is-text-relative -msched-prolog -mthumb
@ -mvectorize-with-neon-quad
.section .text.countPulseASM,"ax",%progbits
.align 1
.global countPulseASM
.code 16
.thumb_func
.type countPulseASM, %function
countPulseASM:
push {r4, r5, lr} @ @ 112 *push_multi [length = 2]
.L2:
ldr r4, [r0] @ D.11539, *port_7(D) @ 22 *thumb1_movsi_insn/7 [length = 2]
and r4, r1 @ D.11539, bit @ 24 *thumb1_andsi3_insn [length = 2]
cmp r4, r2 @ D.11539, stateMask @ 25 cbranchsi4_insn/1 [length = 4]
bne .L5 @,
sub r3, r3, #1 @ maxloops, @ 17 *thumb1_addsi3/2 [length = 2]
cmp r3, #0 @ maxloops, @ 18 cbranchsi4_insn/1 [length = 4]
bne .L2 @,
b .L10 @ @ 127 *thumb_jump [length = 2]
.L6:
sub r3, r3, #1 @ maxloops, @ 30 *thumb1_addsi3/2 [length = 2]
cmp r3, #0 @ maxloops, @ 31 cbranchsi4_insn/1 [length = 4]
beq .L10 @,
.L5:
ldr r4, [r0] @ D.11539, *port_7(D) @ 35 *thumb1_movsi_insn/7 [length = 2]
and r4, r1 @ D.11539, bit @ 37 *thumb1_andsi3_insn [length = 2]
cmp r4, r2 @ D.11539, stateMask @ 38 cbranchsi4_insn/1 [length = 4]
bne .L6 @,
mov r4, #0 @ width, @ 7 *thumb1_movsi_insn/2 [length = 2]
.L7:
ldr r5, [r0] @ D.11539, *port_7(D) @ 48 *thumb1_movsi_insn/7 [length = 2]
and r5, r1 @ D.11539, bit @ 50 *thumb1_andsi3_insn [length = 2]
cmp r5, r2 @ D.11539, stateMask @ 51 cbranchsi4_insn/1 [length = 4]
bne .L13 @,
add r4, r4, #1 @ width, @ 43 *thumb1_addsi3/1 [length = 2]
cmp r4, r3 @ width, maxloops @ 44 cbranchsi4_insn/1 [length = 4]
bne .L7 @,
mov r0, #0 @ D.11539, @ 11 *thumb1_movsi_insn/2 [length = 2]
b .L3 @ @ 130 *thumb_jump [length = 2]
.L13:
mov r0, r4 @ D.11539, width @ 9 *thumb1_movsi_insn/1 [length = 2]
b .L3 @ @ 132 *thumb_jump [length = 2]
.L10:
mov r0, r3 @ D.11539, maxloops @ 8 *thumb1_movsi_insn/1 [length = 2]
.L3:
@ sp needed @ @ 115 force_register_use [length = 0]
pop {r4, r5, pc}
.size countPulseASM, .-countPulseASM
.ident "GCC: (GNU Tools for ARM Embedded Processors (Arduino build)) 4.8.3 20140228 (release) [ARM/embedded-4_8-branch revision 208322]"
|
leapmotion/ProjectNorthStar | 8,555 | Electronics/Firmware/src/ArduinoCore/src/core/PreprocessingAssembly/pulse_asm.S | /*
Copyright (c) 2015 Arduino LLC. All right reserved.
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
The following function has been compiled to ASM with gcc
unsigned long countPulseASM(const volatile uint32_t *port, uint32_t bit, uint32_t stateMask, unsigned long maxloops)
{
unsigned long width = 0;
// wait for any previous pulse to end
while ((*port & bit) == stateMask)
if (--maxloops == 0)
return 0;
// wait for the pulse to start
while ((*port & bit) != stateMask)
if (--maxloops == 0)
return 0;
// wait for the pulse to stop
while ((*port & bit) == stateMask) {
if (++width == maxloops)
return 0;
}
return width;
}
using the command line:
arm-none-eabi-gcc -mcpu=cortex-m0plus -mthumb -c -Os -W -ffunction-sections -fdata-sections \
-nostdlib --param max-inline-insns-single=500 -fno-exceptions -MMD \
-DF_CPU=48000000L -DARDUINO=10602 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD \
-D__SAMD21G18A__ -DUSB_VID=0x2341 -DUSB_PID=0x004d -DUSBCON \
-DUSB_MANUFACTURER="Arduino LLC" -DUSB_PRODUCT="Arduino Zero" \
-I/Code/arduino/build/linux/work/hardware/tools/CMSIS/CMSIS/Include/ \
-I/Code/arduino/build/linux/work/hardware/tools/CMSIS/Device/ATMEL/ \
-I/Code/arduino/build/linux/work/hardware/arduino/samd/cores/arduino \
-I/Code/arduino/build/linux/work/hardware/arduino/samd/variants/arduino_zero \
count.c -Wa,-ahlmsd=output.lst -dp -fverbose-asm -S
The result has been slightly edited to increase readability.
*/
.cpu cortex-m0plus
.fpu softvfp
.eabi_attribute 20, 1 @ Tag_ABI_FP_denormal
.eabi_attribute 21, 1 @ Tag_ABI_FP_exceptions
.eabi_attribute 23, 3 @ Tag_ABI_FP_number_model
.eabi_attribute 24, 1 @ Tag_ABI_align8_needed
.eabi_attribute 25, 1 @ Tag_ABI_align8_preserved
.eabi_attribute 26, 1 @ Tag_ABI_enum_size
.eabi_attribute 30, 4 @ Tag_ABI_optimization_goals
.eabi_attribute 34, 0 @ Tag_CPU_unaligned_access
.eabi_attribute 18, 4 @ Tag_ABI_PCS_wchar_t
.file "count.c"
@ GNU C (GNU Tools for ARM Embedded Processors (Arduino build)) version 4.8.3 20140228 (release) [ARM/embedded-4_8-branch revision 208322] (arm-none-eabi)
@ compiled by GNU C version 4.3.2, GMP version 4.3.2, MPFR version 2.4.2, MPC version 0.8.1
@ GGC heuristics: --param ggc-min-expand=100 --param ggc-min-heapsize=131072
@ options passed:
@ -I /Code/arduino/build/linux/work/hardware/tools/CMSIS/CMSIS/Include/
@ -I /Code/arduino/build/linux/work/hardware/tools/CMSIS/Device/ATMEL/
@ -I /Code/arduino/build/linux/work/hardware/arduino/samd/cores/arduino
@ -I /Code/arduino/build/linux/work/hardware/arduino/samd/variants/arduino_zero
@ -imultilib armv6-m
@ -iprefix /Code/arduino/build/linux/work/hardware/tools/gcc-arm-none-eabi-4.8.3-2014q1/bin/../lib/gcc/arm-none-eabi/4.8.3/
@ -isysroot /Code/arduino/build/linux/work/hardware/tools/gcc-arm-none-eabi-4.8.3-2014q1/bin/../arm-none-eabi
@ -MMD count.d -D__USES_INITFINI__ -D F_CPU=48000000L -D ARDUINO=10602
@ -D ARDUINO_SAMD_ZERO -D ARDUINO_ARCH_SAMD -D __SAMD21G18A__
@ -D USB_VID=0x2341 -D USB_PID=0x004d -D USBCON
@ -D USB_MANUFACTURER=Arduino LLC -D USB_PRODUCT=Arduino Zero count.c
@ -mcpu=cortex-m0plus -mthumb -Os -Wextra -ffunction-sections
@ -fdata-sections -fno-exceptions -fverbose-asm
@ --param max-inline-insns-single=500
@ options enabled: -faggressive-loop-optimizations -fauto-inc-dec
@ -fbranch-count-reg -fcaller-saves -fcombine-stack-adjustments -fcommon
@ -fcompare-elim -fcprop-registers -fcrossjumping -fcse-follow-jumps
@ -fdata-sections -fdefer-pop -fdelete-null-pointer-checks -fdevirtualize
@ -fdwarf2-cfi-asm -fearly-inlining -feliminate-unused-debug-types
@ -fexpensive-optimizations -fforward-propagate -ffunction-cse
@ -ffunction-sections -fgcse -fgcse-lm -fgnu-runtime
@ -fguess-branch-probability -fhoist-adjacent-loads -fident -fif-conversion
@ -fif-conversion2 -findirect-inlining -finline -finline-atomics
@ -finline-functions -finline-functions-called-once
@ -finline-small-functions -fipa-cp -fipa-profile -fipa-pure-const
@ -fipa-reference -fipa-sra -fira-hoist-pressure -fira-share-save-slots
@ -fira-share-spill-slots -fivopts -fkeep-static-consts
@ -fleading-underscore -fmath-errno -fmerge-constants -fmerge-debug-strings
@ -fomit-frame-pointer -foptimize-register-move -foptimize-sibling-calls
@ -fpartial-inlining -fpeephole -fpeephole2 -fprefetch-loop-arrays
@ -freg-struct-return -fregmove -freorder-blocks -freorder-functions
@ -frerun-cse-after-loop -fsched-critical-path-heuristic
@ -fsched-dep-count-heuristic -fsched-group-heuristic -fsched-interblock
@ -fsched-last-insn-heuristic -fsched-pressure -fsched-rank-heuristic
@ -fsched-spec -fsched-spec-insn-heuristic -fsched-stalled-insns-dep
@ -fschedule-insns2 -fsection-anchors -fshow-column -fshrink-wrap
@ -fsigned-zeros -fsplit-ivs-in-unroller -fsplit-wide-types
@ -fstrict-aliasing -fstrict-overflow -fstrict-volatile-bitfields
@ -fsync-libcalls -fthread-jumps -ftoplevel-reorder -ftrapping-math
@ -ftree-bit-ccp -ftree-builtin-call-dce -ftree-ccp -ftree-ch
@ -ftree-coalesce-vars -ftree-copy-prop -ftree-copyrename -ftree-cselim
@ -ftree-dce -ftree-dominator-opts -ftree-dse -ftree-forwprop -ftree-fre
@ -ftree-loop-if-convert -ftree-loop-im -ftree-loop-ivcanon
@ -ftree-loop-optimize -ftree-parallelize-loops= -ftree-phiprop -ftree-pre
@ -ftree-pta -ftree-reassoc -ftree-scev-cprop -ftree-sink
@ -ftree-slp-vectorize -ftree-slsr -ftree-sra -ftree-switch-conversion
@ -ftree-tail-merge -ftree-ter -ftree-vect-loop-version -ftree-vrp
@ -funit-at-a-time -fverbose-asm -fzero-initialized-in-bss -mlittle-endian
@ -mpic-data-is-text-relative -msched-prolog -mthumb
@ -mvectorize-with-neon-quad
.section .text.countPulseASM,"ax",%progbits
.align 1
.global countPulseASM
.code 16
.thumb_func
.type countPulseASM, %function
countPulseASM:
push {r4, r5, lr} @ @ 112 *push_multi [length = 2]
.L2:
ldr r4, [r0] @ D.11539, *port_7(D) @ 22 *thumb1_movsi_insn/7 [length = 2]
and r4, r1 @ D.11539, bit @ 24 *thumb1_andsi3_insn [length = 2]
cmp r4, r2 @ D.11539, stateMask @ 25 cbranchsi4_insn/1 [length = 4]
bne .L5 @,
sub r3, r3, #1 @ maxloops, @ 17 *thumb1_addsi3/2 [length = 2]
cmp r3, #0 @ maxloops, @ 18 cbranchsi4_insn/1 [length = 4]
bne .L2 @,
b .L10 @ @ 127 *thumb_jump [length = 2]
.L6:
sub r3, r3, #1 @ maxloops, @ 30 *thumb1_addsi3/2 [length = 2]
cmp r3, #0 @ maxloops, @ 31 cbranchsi4_insn/1 [length = 4]
beq .L10 @,
.L5:
ldr r4, [r0] @ D.11539, *port_7(D) @ 35 *thumb1_movsi_insn/7 [length = 2]
and r4, r1 @ D.11539, bit @ 37 *thumb1_andsi3_insn [length = 2]
cmp r4, r2 @ D.11539, stateMask @ 38 cbranchsi4_insn/1 [length = 4]
bne .L6 @,
mov r4, #0 @ width, @ 7 *thumb1_movsi_insn/2 [length = 2]
.L7:
ldr r5, [r0] @ D.11539, *port_7(D) @ 48 *thumb1_movsi_insn/7 [length = 2]
and r5, r1 @ D.11539, bit @ 50 *thumb1_andsi3_insn [length = 2]
cmp r5, r2 @ D.11539, stateMask @ 51 cbranchsi4_insn/1 [length = 4]
bne .L13 @,
add r4, r4, #1 @ width, @ 43 *thumb1_addsi3/1 [length = 2]
cmp r4, r3 @ width, maxloops @ 44 cbranchsi4_insn/1 [length = 4]
bne .L7 @,
mov r0, #0 @ D.11539, @ 11 *thumb1_movsi_insn/2 [length = 2]
b .L3 @ @ 130 *thumb_jump [length = 2]
.L13:
mov r0, r4 @ D.11539, width @ 9 *thumb1_movsi_insn/1 [length = 2]
b .L3 @ @ 132 *thumb_jump [length = 2]
.L10:
mov r0, r3 @ D.11539, maxloops @ 8 *thumb1_movsi_insn/1 [length = 2]
.L3:
@ sp needed @ @ 115 force_register_use [length = 0]
pop {r4, r5, pc}
.size countPulseASM, .-countPulseASM
.ident "GCC: (GNU Tools for ARM Embedded Processors (Arduino build)) 4.8.3 20140228 (release) [ARM/embedded-4_8-branch revision 208322]"
|
MeganGrass/Resident-Evil-2-Starter-Kit | 76,263 | source/assembly/directive.s |
/*
* Controller
*/
PAD_NULL: equ 0x0000
PAD_L2: equ 0x0001
PAD_R2: equ 0x0002
PAD_L1: equ 0x0004
PAD_R1: equ 0x0008
PAD_TRIANGLE: equ 0x0010
PAD_CIRCLE: equ 0x0020
PAD_X: equ 0x0040
PAD_SQUARE: equ 0x0080
PAD_SELECT: equ 0x0100
PAD_START: equ 0x0800
PAD_UP: equ 0x1000
PAD_RIGHT: equ 0x2000
PAD_DOWN: equ 0x4000
PAD_LEFT: equ 0x8000
/*
* Defines
*/
RDTFile: equ 0x8011A000
BSSFile: equ 0x80190000
TIMFile: equ 0x80198000
LZin: equ 0x80198000
LZout: equ 0x801A5800
ScratchPad: equ 0x1F800000
/*
* Structure Fields
*/
Global: equ 0x800CC1E8 // G
G_Padd1: equ 0x800CE304 // G.Padd1
G_Padd1Trg: equ 0x800CE306 // G.Padd1_trg
G_pPl_emd_top: equ 0x800CE31C // G.pPl_emd_top
G_pRoom: equ 0x800CE324 // G.pRoom
G_pFree_work: equ 0x800CE32C // G.pFree_work
G_pEm: equ 0x800CE330 // G.pEm
G_Status_flg: equ 0x800CFBD8 // G.Status_flg
G_Ctpage: equ 0x800CFBF0 // G.Ctpage
G_Room_player_flg: equ 0x800CFBF6 // G.Room_player_flg
G_Player: equ 0x800CFBF8 // G.Player
Player_Id: equ 0x800CFC00 // G.Player.Id
Player_Cdir_y: equ 0x800CFC6E // G.Player.Cdir_y
Player_Type: equ 0x800CFD06 // G.Player.Type
Player_pNow_seq: equ 0x800CFD70 // G.Player.pNow_seq
Player_Poison_Flg0: equ 0x800CFE10 // G.Player.Poison_Flg0
Savegame_Room_no: equ 0x800D481E // G.Savegame.Room_no
Savegame_Cut_no: equ 0x800D4820 // G.Savegame.Cut_no
/*
* Routine
*/
desld_set: equ 0x80010000
desld: equ 0x80010084
memcpy16: equ 0x80010778
setexmask: equ 0x800107B4
Cd_init: equ 0x800128C4
Cd_system_control: equ 0x80012984
Xa_play: equ 0x800129B4
Xa_control: equ 0x80012C68
Xa_control_stop: equ 0x80012CA4
Xa_control_init: equ 0x80012CD8
Xa_seek: equ 0x80012D30
Xa_control_play: equ 0x80012E70
Xa_control_end: equ 0x80012F48
Cd_read: equ 0x80012FB8
Cd_read_s: equ 0x800132B0
Cd_seek: equ 0x80013714
Cd_ready_cb: equ 0x8001376C
Cd_set_stereo: equ 0x80013A7C
Set_volume: equ 0x80013AC8
Change_volume: equ 0x80013B4C
Door_main: equ 0x80013BC4
Door_init: equ 0x80013C1C
Door_move: equ 0x80013EB4
Door_scheduler_main: equ 0x80014058
Door_exit: equ 0x8001417C
Door_Trans: equ 0x80014234
DoorSort: equ 0x8001468C
Door_model_init: equ 0x80014B40
Door_model_set: equ 0x80014BA4
Door_snd_trans: equ 0x80014CD0
Door_texture_load: equ 0x80015064
Hani_ck: equ 0x80015280
Add_speedXZ: equ 0x800152C8
Add_speedXYZ: equ 0x80015350
Add_speedXYZsuper: equ 0x800153F4
Direction_ck: equ 0x800154AC
Goto00: equ 0x80015558
Goto00_ck: equ 0x80015614
Goto01: equ 0x8001569C
Goto01_ck: equ 0x80015714
Dir_pos_ck: equ 0x80015758
L_pos_ckXZ: equ 0x800157D4
L_pos_ckXZM: equ 0x80015834
Cdir_ck: equ 0x80015910
Cdir_ck2: equ 0x80015930
Gacha_ch: equ 0x8001598C
Sikai_ck: equ 0x800159A4
Set_base_pos: equ 0x80015B94
Null_pos_set: equ 0x80015CB8
get_null_pos: equ 0x80015DB0
Spd_get: equ 0x80015E7C
Rnd: equ 0x80015FE8
Em_seq_sound: equ 0x80016028
Tex_Ani_move: equ 0x80016068
Foot_set_pl: equ 0x80016200
Kage_work_init: equ 0x8001633C
Kage_work9_init: equ 0x8001645C
Kage_work_set: equ 0x80016480
Kage_work9_set: equ 0x8001653C
MulKage: equ 0x800168B4
Kage_work_sort: equ 0x8001699C
Kage_work9_sort: equ 0x80016C14
Kage_work_color_set: equ 0x80016FE4
Kage_work9_color_set: equ 0x8001700C
Texture_Move: equ 0x80017054
Texture_Move_GT3: equ 0x800171D0
Texture_Move_GT4: equ 0x800172F8
Texture_Move_GT4_up: equ 0x8001745C
Rot_neck: equ 0x800177C0
Rot_neck_em: equ 0x80017D98
Rot_neck_em_n: equ 0x80017FDC
Neck_Dir_ZY: equ 0x8001820C
Op_PartsSort00: equ 0x80018378
Op_PartsSort05: equ 0x8001844C
Op_PartsSort06: equ 0x80018648
Kami_rot05: equ 0x80018728
W_rot: equ 0x80018CC8
W_rot_x: equ 0x80018D64
Rbj_set: equ 0x80018E08
Em_dead_flg_on: equ 0x80018FB0
Aida_Jh_init: equ 0x80019024
Aida_Jh_move: equ 0x800190C0
Kg_Jh_init: equ 0x800193C0
Kg_Jh_move: equ 0x800193F0
Jh_set: equ 0x80019628
MulJh: equ 0x800197F4
Aida_Jh_sort: equ 0x80019B3C
Jh_sort: equ 0x80019CD0
Approach: equ 0x8001A0E0
Approach_one: equ 0x8001A1E0
Mot_play: equ 0x8001A240
Mot_play2: equ 0x8001A2A4
Mot_play_init: equ 0x8001A308
Mot_play_sp: equ 0x8001A330
Mot_play2_sp: equ 0x8001A3E8
Mot_play2_spxz: equ 0x8001A4A0
Em_init_super: equ 0x8001A558
Branch: equ 0x8001A58C
Ck_em_id: equ 0x8001A5C0
Goto00_super: equ 0x8001A644
Goto01_super: equ 0x8001A858
Get_parts_world_dir: equ 0x8001A9BC
Enemy_work_set: equ 0x8001AA38
Em_set: equ 0x8001AAA0
Emd_load: equ 0x8001AAA8
Set_enemy_work: equ 0x8001AD3C
Kill_enemy_work: equ 0x8001B250
Em_move_tbl_set: equ 0x8001B274
Em_bin_load: equ 0x8001B710
Emd_load_file: equ 0x8001b934
Esp_init_C: equ 0x8001BABC
Esp_init_R: equ 0x8001BBA4
Esp_data_set0: equ 0x8001BCA0
Esp_data_set1: equ 0x8001BD38
Esp_call: equ 0x8001BF10
Esp_call3D: equ 0x8001C224
Esp_call3D2: equ 0x8001C56C
Esp_call2: equ 0x8001C8C4
Esp_call3: equ 0x8001CBE8
Esp_kill: equ 0x8001CEFC
Esp_kill2: equ 0x8001CFBC
Esp_die: equ 0x8001CFFC
Esp_ctrl: equ 0x8001D0AC
Esp_ctrl2: equ 0x8001D15C
Esp_ctrl3: equ 0x8001D180
Esp_ctrl4: equ 0x8001D240
Esp_move: equ 0x8001D300
Esp_pos: equ 0x8001D68C
Esp_00: equ 0x8001DC28
Esp_01: equ 0x8001DC30
Esp_02: equ 0x8001DD2C
Esp_03: equ 0x8001DE88
Esp_04: equ 0x8001DF50
Esp_05: equ 0x8001DF90
Esp_06: equ 0x8001E11C
Esp_07: equ 0x8001E154
Esp_08: equ 0x8001E200
Esp_09: equ 0x8001E390
Esp_0a: equ 0x8001E3C4
Esp_0b: equ 0x8001E4B4
Esp_0c: equ 0x8001E638
Esp_0d: equ 0x8001E898
Esp_0e: equ 0x8001E8B0
Esp_0f: equ 0x8001ED9C
Esp_10: equ 0x8001F128
Esp_11: equ 0x8001F198
Esp_12: equ 0x8001F2A0
Esp_13: equ 0x8001F2C0
Esp_14: equ 0x8001F530
Esp_15: equ 0x8001F5A4
Esp_16: equ 0x8001F634
Esp_17: equ 0x8001F6A4
Esp_18: equ 0x8001F6E0
Esp_19: equ 0x8001FA08
Esp_1a: equ 0x8001FA6C
Esp_1b: equ 0x8001FA9C
Esp_1c: equ 0x8001FBD0
Esp_1d: equ 0x8001FD5C
Esp_1e: equ 0x8001FECC
Esp_1f: equ 0x8001FF98
Esp_20: equ 0x800200B0
Esp_21: equ 0x80020298
Esp_22: equ 0x80020364
Esp_23: equ 0x800204F8
Esp_24: equ 0x80020510
Esp_25: equ 0x80020660
Esp_26: equ 0x800206E0
Esp_27: equ 0x800206FC
Esp_28: equ 0x80020758
Esp_29: equ 0x800207E4
Esp_2a: equ 0x800208B8
Esp_2b: equ 0x80020950
Esp_2c: equ 0x800209CC
Esp_2d: equ 0x80020ABC
Esp_2e: equ 0x80020B60
Esp_2f: equ 0x80020C3C
Esp_30: equ 0x80020F3C
Esp_31: equ 0x800215C8
Esp_32: equ 0x80021970
Esp_33: equ 0x800219B4
Esp_34: equ 0x80021A48
Esp_35: equ 0x80021B00
Esp_36: equ 0x80021CE4
Esp_37: equ 0x80021D24
Esp_38: equ 0x80021E14
Esp_39: equ 0x80022094
Esp_3a: equ 0x80022254
Esp_3b: equ 0x800223F8
Esp_3c: equ 0x80022454
Esp_3d: equ 0x80022474
Esp_3e: equ 0x8002256C
Esp_3f: equ 0x800226AC
Esp_40: equ 0x80022728
Esp_41: equ 0x80022774
Esp_42: equ 0x800228D8
Esp_43: equ 0x800229E4
Esp_44: equ 0x80022ABC
Esp_45: equ 0x80022EBC
Esp_46: equ 0x80023204
Esp_47: equ 0x80023554
Esp_48: equ 0x8002373C
Esp_49: equ 0x8002387C
Esp_4a: equ 0x800238E4
Esp_4b: equ 0x800239C4
Esp_4c: equ 0x80023B94
Esp_4d: equ 0x80023C70
Esp_4e: equ 0x800241C8
Esp_4f: equ 0x8002434C
Esp_50: equ 0x8002453C
Esp_51: equ 0x800246E8
Esp_52: equ 0x80024818
Esp_53: equ 0x800252B8
Esp_54: equ 0x80025348
Esp_55: equ 0x8002539C
Esp_56: equ 0x80025408
Esp_57: equ 0x8002563C
SeVibOn: equ 0x8002574C
Esp_58: equ 0x80025754
Esp_59: equ 0x8002575C
Esp_5a: equ 0x80025764
Esp_5b: equ 0x8002576C
Esp_5c: equ 0x80025774
Esp_5d: equ 0x8002577C
Esp_5e: equ 0x80025784
Esp_5f: equ 0x8002578C
Game_loop: equ 0x80025794
Set_door: equ 0x80026B7C
Gun_light_set: equ 0x80026ED8
Gun_light_reset: equ 0x800270EC
Joint_trans2: equ 0x80027160
ko_joint_trans2: equ 0x80027434
SortGT3_neo: equ 0x80027BEC
SortGT4_neo: equ 0x80027DBC
ko_joint_trans3: equ 0x80027FF0
PartsWork_set: equ 0x80028324
PartsWork_link: equ 0x80028368
Init_Parts_work: equ 0x80028648
Mem_ck_Parts_work: equ 0x800289B4
Joint_pos_trans: equ 0x80028A24
Parts_down: equ 0x80028AD8
Parts_bomb: equ 0x80028DAC
Parts_ryu: equ 0x80028EA4
HMatrix: equ 0x80028F48
HMatrix1: equ 0x80029120
Model_color_plus: equ 0x8002940C
Joint_move: equ 0x8002959C
J_seq: equ 0x80029614
hokan_svec: equ 0x80029B70
Pl_set_packet: equ 0x80029C94
Joint_move_p: equ 0x80029E10
Joint_move2: equ 0x8002A490
J_seq2: equ 0x8002A508
Scr_effect: equ 0x8002AA28
Scr_quake: equ 0x8002AA6C
Scr_rasta: equ 0x8002AB84
line_trans: equ 0x8002AC94
line_scr_end: equ 0x8002ADDC
line_mode_set: equ 0x8002AE10
Line_work_init: equ 0x8002AEC8
;;main: equ 0x8002AEE0
Init_system: equ 0x8002B48C
InitGeom_func: equ 0x8002B6AC
Init_main: equ 0x8002B6D4
Swap_Cbuff: equ 0x8002B968
Bg_set_mode: equ 0x8002BDA8
Bg_draw: equ 0x8002BDF4
Fade_set: equ 0x8002C1A0
Fade_adjust: equ 0x8002C2B0
Fade_off: equ 0x8002C324
Fade_status: equ 0x8002C350
System_trans: equ 0x8002C378
Init_global: equ 0x8002C610
Cut_check: equ 0x8002C6B4
Cut_change: equ 0x8002C7AC
Ccut_serach: equ 0x8002C7DC
Hit_ck_point4: equ 0x8002C820
Hit_ck_box: equ 0x8002C904
Card_event_set: equ 0x8002C94C
Logo: equ 0x8002CAC4
PresetObjectGT3_neo: equ 0x8002CBC4
PresetObjectGT4_neo: equ 0x8002CD24
CompM: equ 0x8002CE94
mapModelingData: equ 0x8002CFD8
MulLMatrix: equ 0x8002D030
SortGT3_lno: equ 0x8002D0E8
SortGT4_lno: equ 0x8002D244
Bomb_Parts_SortGT3: equ 0x8002D3C8
Bomb_Parts_SortGT4: equ 0x8002D718
Ryu_Parts_SortGT3: equ 0x8002DA80
Ryu_Parts_SortGT4: equ 0x8002DDF0
mirror_TMD_GT3: equ 0x8002E1B4
mirror_PACKET_GT3: equ 0x8002E1FC
mirror_TMD_GT4: equ 0x8002E240
mirror_PACKET_GT4: equ 0x8002E288
Mirror_model_cp: equ 0x8002E2D8
Init_mirror_weapon: equ 0x8002E4F8
Mirror_weapon_cp: equ 0x8002E548
Parts_work_cp: equ 0x8002E788
Mirror_view: equ 0x8002E93C
Mirror_in_view: equ 0x8002EA40
Mirror_trans: equ 0x8002EAF8
Mirror_matrix_set: equ 0x8002ED30
Late_set: equ 0x8002EEB4
Mizu_trans: equ 0x8002EF50
Mizu_div_ck: equ 0x8002F29C
Mizu_div_main: equ 0x8002F3FC
Print8: equ 0x8002FA00
Print14: equ 0x8002FA28
Print_main: equ 0x8002FA54
Mess_set: equ 0x8002FE38
Moji_trans_main: equ 0x8003022C
Mess_disp: equ 0x8003027C
Branch_disp: equ 0x80030844
name_ptr_set: equ 0x80030B9C
mess_trans: equ 0x80030C9C
Name_disp: equ 0x80031070
Mess_print: equ 0x800313A4
;;moji_trans_main: equ 0x800316A8 ;; commented out because armips has trouble with character casing and a variable at 0x8003022C has similar name
moji_trans_8: equ 0x80031734
moji_trans_14: equ 0x800318A4
Moji_buff_init: equ 0x80031AC4
Moji_init: equ 0x80031AF4
Moji_mode_init: equ 0x80031BF0
Init_scheduler: equ 0x80031CC0
Scheduler: equ 0x80031D8C
Task_lexecute: equ 0x80031E80
Task_lchain: equ 0x80031F00
Task_execute: equ 0x80031F6C
Task_sleep: equ 0x80031F94
Task_exit: equ 0x80031FE4
Task_kill: equ 0x80032030
Task_chain: equ 0x8003208C
Task_suspend: equ 0x800320E0
Task_signal: equ 0x8003210C
Task_status: equ 0x80032138
Init_movie_work: equ 0x80032150
Movie: equ 0x80032340
Movie_init: equ 0x80032450
Movie_main: equ 0x80032700
Movie_end: equ 0x80032984
Movie_exit: equ 0x80032AB8
Open_movie: equ 0x80032CE8
Play_movie: equ 0x80032FCC
Close_movie: equ 0x80033118
RuntoImage: equ 0x8003317C
Mdec_callback: equ 0x8003324C
Movie_xa_start: equ 0x8003331C
Movie_xa_stop: equ 0x80033370
Set_movie_volume2: equ 0x800333C4
CdReset2: equ 0x80033440
Oba_ck_hit: equ 0x80034D0C
Oba_ck_only: equ 0x800352D8
Oba_set_ofs: equ 0x80035408
Oba_ck_em: equ 0x80035530
Oba_ck_em2: equ 0x800355C4
Sca_ck_em: equ 0x8003567C
Om_init: equ 0x80035710
Col_chg_init: equ 0x800357D8
Tex_chg_init: equ 0x800358F0
Tex_ctr: equ 0x80035994
Col_chg: equ 0x80035AD0
Tex_chg: equ 0x80035C98
Om_move: equ 0x80035F68
Om_trans: equ 0x800363F0
Om_move_box: equ 0x80036710
Om_set_fall_dir: equ 0x80036C5C
Ob_test_load2: equ 0x80036CF8
Oma_set_ofs: equ 0x80036E30
Oma_ck_oba: equ 0x80036EF8
Oma_ck_om: equ 0x80037258
Oma_ck_front: equ 0x80037450
Oma_pl_updown_ck: equ 0x800375C8
Oma_Spl_updown_ck: equ 0x80037940
Oma_front_ck: equ 0x80037D48
Oma_on_check: equ 0x80037EAC
Oma_pull: equ 0x80037F60
Oma_pull_hosei_x: equ 0x80038664
Oma_pull_hosei_z: equ 0x800386D0
Oma_get_on_om: equ 0x8003873C
Oma_ob_pull2: equ 0x80038818
Omd_in_check: equ 0x80038950
Oma_obj_ck_all: equ 0x800389E8
Oma_hit_ck_all: equ 0x80038A98
Om_Jump_ck: equ 0x80038B84
Pad_set: equ 0x80038BBC
Pad_rep_set: equ 0x80039464
Windows: equ 0x80039818
Keyboard_Input: equ 0x800398AC
Keyboard_set: equ 0x80039B30
Keyboard: equ 0x80039B88
Wframe_in_out: equ 0x80039ED4
Wframe_set: equ 0x8003A034
Wframe_move: equ 0x8003A148
Get_moji_code: equ 0x8003A28C
Cprint: equ 0x8003A298
Console_put: equ 0x8003A56C
Console_roll_up: equ 0x8003A5A4
Console_clr: equ 0x8003A668
Console_trans: equ 0x8003A6AC
Sprite_Trans: equ 0x8003A794
Set_sp_work: equ 0x8003A8CC
Dr_mode_set: equ 0x8003A92C
Computer200: equ 0x8003A9F4
Computer613: equ 0x8003B264
Computer_init: equ 0x8003B7E8
Computer_exit: equ 0x8003B918
Player_set: equ 0x8003BAF0
Pl_before: equ 0x8003BED8
Pl_after: equ 0x8003BF7C
Player_move: equ 0x8003BFAC
Pl_init: equ 0x8003C210
Pl_move: equ 0x8003C57C
pl_mv00_pad: equ 0x8003C5F8
pl_mv00: equ 0x8003C780
pl_mv01_pad: equ 0x8003C924
pl_mv01: equ 0x8003CBDC
pl_mv02_pad: equ 0x8003CE24
pl_mv02: equ 0x8003D0E8
pl_mv03_pad: equ 0x8003D3E0
pl_mv03: equ 0x8003D5F4
Lim_dir_ck: equ 0x8003D96C
Pl_neck: equ 0x8003DB38
pl_mv04_pad: equ 0x8003DD48
pl_mv04: equ 0x8003DFF4
pl_mv06_pad: equ 0x8003E1D4
pl_mv06: equ 0x8003E1DC
pl_mv07_pad: equ 0x8003E314
pl_mv07: equ 0x8003E31C
pl_mv08_pad: equ 0x8003E8CC
pl_mv08: equ 0x8003E8DC
pl_mv09_pad: equ 0x8003EC60
pl_mv09: equ 0x8003EC70
pl_mv0a_pad: equ 0x8003F0FC
pl_mv0a: equ 0x8003F174
pl_mv0b_pad: equ 0x8003F420
pl_mv0b: equ 0x8003F428
Pl_damage: equ 0x8003F600
pl_dm00: equ 0x8003F658
pl_dm01: equ 0x8003F778
pl_dm02: equ 0x8003F8E4
pl_dm03: equ 0x8003FC3C
Pl_die: equ 0x8003FEE4
pl_die00: equ 0x8003FF3C
Pl_Em_damage: equ 0x8004006C
Pl_Em_die: equ 0x800400D0
Pl_dead: equ 0x80040134
Pl_life_down: equ 0x800401D4
Pl_life_up: equ 0x800402F4
Pl_weapon_ch: equ 0x800408C8
Non_init: equ 0x80040C40
Plw02_init: equ 0x80040C48
Plw09_init: equ 0x80040CF4
Plw0c_init: equ 0x80040D68
Plw0f_init: equ 0x80040EDC
Plw12_init: equ 0x80040F5C
Weapon_cls: equ 0x80041060
Init_W_Tool: equ 0x80041088
W_Tool: equ 0x80041090
init_Weapon_at: equ 0x80041098
Weapon_at_ck: equ 0x800410CC
Set_MinMax: equ 0x80041B20
Attack_r_ck0: equ 0x80041CE4
Attack_r_ck1: equ 0x80041EF8
Em_ck: equ 0x80042144
Hand_ck: equ 0x80042368
Mag_set: equ 0x80042470
Mag_down: equ 0x80042644
G_rot_st: equ 0x800428A0
G_rot: equ 0x800428CC
Gat_lp_st: equ 0x8004297C
Gat_rot: equ 0x800429C0
Pl_water: equ 0x80042AAC
pl_mv05_pad: equ 0x80042C20
pl_mv05_w0: equ 0x80042C28
pl_mv05_w0_t2: equ 0x80042C64
pl_mv05_w0_t6: equ 0x800431F8
pl_mv05_w1: equ 0x80043230
pl_mv05_w1_t0: equ 0x8004326C
pl_mv05_w1_t1: equ 0x8004362C
pl_mv05_w1_t2: equ 0x80043908
pl_mv05: equ 0x80043DF8
pl_w01_t2_init: equ 0x80043ECC
pl_w02_t2_init: equ 0x80043ED4
pl_w03_t2_init: equ 0x80043EFC
pl_w04_t2_init: equ 0x80043F24
pl_w05_t2_init: equ 0x80043F2C
pl_w06_t2_init: equ 0x80043F54
pl_w07_t2_init: equ 0x80043F7C
pl_w08_t2_init: equ 0x80043FA4
pl_w09_t2_init: equ 0x80043FCC
pl_w0a_t2_init: equ 0x80043FF4
pl_w0b_t2_init: equ 0x8004401C
pl_w0c_t2_init: equ 0x80044044
pl_w0d_t2_init: equ 0x800440CC
pl_w0e_t2_init: equ 0x800440F4
pl_w0f_t2_init: equ 0x800440FC
pl_w10_t2_init: equ 0x80044104
pl_w11_t2_init: equ 0x8004410C
pl_w12_t2_init: equ 0x80044134
pl_w01_t2_move: equ 0x8004413C
pl_w02_t2_move: equ 0x8004418C
pl_w03_t2_move: equ 0x8004429C
pl_w04_t2_move: equ 0x800443AC
pl_w05_t2_move: equ 0x800444E0
pl_w06_t2_move: equ 0x800445EC
pl_w07_t2_move: equ 0x80044730
pl_w08_t2_move: equ 0x80044908
pl_w09_t2_move: equ 0x80044B44
pl_w0a_t2_move: equ 0x80044F44
pl_w0b_t2_move: equ 0x80045090
pl_w0c_t2_move: equ 0x800451DC
pl_w0d_t2_move: equ 0x8004522C
pl_w0e_t2_move: equ 0x8004534C
pl_w0f_t2_move: equ 0x80045354
pl_w10_t2_move: equ 0x800454A0
pl_w11_t2_move: equ 0x80045588
pl_w12_t2_move: equ 0x80045648
pl_mv05_w1_t3: equ 0x80045850
pl_mv05_w1_t4: equ 0x800459E4
pl_mv05_w1_t5: equ 0x80045B38
pl_mv05_sub: equ 0x80045C10
pl_bow_init: equ 0x80045E78
pl_bow_clr: equ 0x800460AC
Bow_Lim_dir_ck: equ 0x8004618C
pl_bow: equ 0x80046304
Goto_pro: equ 0x80046F44
Bow_3D: equ 0x80046F98
Rot_3D: equ 0x80047030
Pos_em_at_ck: equ 0x800470C0
Pos_pl_at_ck: equ 0x80047664
Bow_goto_parts_no: equ 0x80047858
pl_mv05_w2: equ 0x8004799C
pl_mv05_w2_t1: equ 0x800479D8
pl_mv05_w2_t2: equ 0x80047C6C
pl_mv05_w2_t4: equ 0x800481CC
pl_mv05_w3: equ 0x800482D8
pl_mv05_w3_t2: equ 0x80048314
pl_mv05_w4: equ 0x8004879C
pl_mv05_w4_t2: equ 0x800487D8
pl_mv05_w5: equ 0x80048B50
pl_mv05_w5_t2: equ 0x80048B8C
Poly_eff2_init: equ 0x80048F24
Move_poly_eff2: equ 0x80048FFC
Sort_poly_eff2: equ 0x800493A0
Poly_eff_init: equ 0x80049644
Set_poly_eff: equ 0x800496B8
Sort_poly_eff: equ 0x800498F4
Psp_init0: equ 0x80049A9C
Psp_init1: equ 0x80049AD0
Psp_set: equ 0x80049B1C
Psp_trans: equ 0x80049CA8
Psp_ctr: equ 0x80049DF0
Set_room: equ 0x80049E48
Set_stage: equ 0x8004A3C0
Replace_rdt: equ 0x8004A414
Em_init_move: equ 0x8004A694
Root_ck: equ 0x8004A808
Rnd_area: equ 0x8004AA50
Guide_check: equ 0x8004AAB8
kara_rootck2: equ 0x8004AB60
Sa_dat_set: equ 0x8004B3B8
Sa_parts_mod: equ 0x8004B434
Sa_parts_allmv2: equ 0x8004B734
Sa_parts_allmv: equ 0x8004BAF0
Sa_parts_offset_allmv: equ 0x8004BE28
Sca_get_area: equ 0x8004C198
Sca_ck_hit: equ 0x8004C1BC
Sca_ck_hit_om: equ 0x8004C658
Sca_hit_box2: equ 0x8004C858
Sca_hit_box: equ 0x8004C900
Sca_hosei_box: equ 0x8004CA68
Sca_hit_naname_a: equ 0x8004CBD0
Sca_ck_naname_a: equ 0x8004CFC8
Sca_hit_naname_b: equ 0x8004D048
Sca_ck_naname_b: equ 0x8004D484
Sca_hit_naname_c: equ 0x8004D508
Sca_ck_naname_c: equ 0x8004D940
Sca_hit_naname_d: equ 0x8004D9B4
Sca_ck_naname_d: equ 0x8004DDE8
Sca_hit_hishi: equ 0x8004DE64
Sca_ck_hishi: equ 0x8004EA14
Sca_hit_circle: equ 0x8004EC50
Sca_ck_circle: equ 0x8004ED84
Sca_hit_koban_x: equ 0x8004EDF0
Sca_ck_koban_x: equ 0x8004EF0C
Sca_hit_koban_z: equ 0x8004F044
Sca_ck_koban_z: equ 0x8004F17C
Sca_hit_slope: equ 0x8004F2AC
Sca_hit_stairs: equ 0x8004F49C
Sca_hit_curve: equ 0x8004F6F8
Sca_get_slope_high: equ 0x8004F8B8
Sca_get_stairs_high: equ 0x8004FA28
Sca_get_curve_high: equ 0x8004FB38
Sca_get_ground: equ 0x8004FBA0
Sca_get_dir: equ 0x80050110
Sca_get_dir_super: equ 0x800501BC
Sca_get_dir_super_tmp: equ 0x800503BC
Get_axis: equ 0x80050454
Get_axis2: equ 0x800504DC
Sca_get_pos: equ 0x8005057C
Sca_get_pos_super: equ 0x800505FC
Sca_get_pos_super_tmp: equ 0x8005075C
Sca_ck_line: equ 0x80050858
Sca_get_high: equ 0x80050F80
Sca_get_low: equ 0x80050FC8
Sca_search: equ 0x80050FF4
Sce_at_check: equ 0x80051088
Nothing: equ 0x800514EC
Sce_Door: equ 0x80051514
Key_lost: equ 0x80051718
Sce_Item: equ 0x80051884
Sce_Normal: equ 0x80051940
Sce_Message: equ 0x80051948
Sce_Event: equ 0x80051980
Sce_Flg_chg: equ 0x800519C0
Sce_Water: equ 0x80051A2C
Sce_Move: equ 0x80051A48
Sce_Save: equ 0x80051AB0
Save_entrance: equ 0x80051B04
Sce_Itembox: equ 0x80051C20
Item_box_entrance: equ 0x80051C64
Sce_Damage: equ 0x80051E74
Sce_Status: equ 0x80052004
Sce_Hikidashi: equ 0x80052044
Hikidashi_entrance: equ 0x800522CC
Sce_Windows: equ 0x80052620
Sce_at: equ 0x8005264C
Water_ck: equ 0x800527B4
Floor_check: equ 0x800528E8
Sce_test_init: equ 0x800529B4
Em_kind_search: equ 0x80052AF4
Sce_se_set: equ 0x80052B38
Sce_rnd_set: equ 0x80052CA0
Sce_model_init: equ 0x80052D14
Sce_work_clr: equ 0x80052E20
Sce_work_clr_at: equ 0x80052E7C
Sce_work_clr_set: equ 0x80052F3C
Sce_aot_init: equ 0x800530C0
Event_init: equ 0x800530EC
Event_exec: equ 0x80053138
Sce_col_chg_init: equ 0x80053244
Sce_mirror_init: equ 0x800532D8
Sce_kirakira_set: equ 0x80053394
Sce_scheduler_set: equ 0x80053528
Sce_scheduler: equ 0x80053644
Sce_scheduler_main: equ 0x800536C4
Break_point: equ 0x800537CC
;;Nop: equ 0x800537E4 ;; commented out because this causes problems with armips
Evt_end: equ 0x800537FC
Evt_next: equ 0x80053860
Evt_chain: equ 0x80053878
Evt_exec: equ 0x800538A4
Evt_kill: equ 0x800538DC
Ifel_ck: equ 0x80053924
Else_ck: equ 0x80053964
Endif: equ 0x800539A0
Sleep: equ 0x800539DC
Sleeping: equ 0x80053A24
Wsleep: equ 0x80053A8C
Wsleeping: equ 0x80053AC0
For: equ 0x80053B1C
For2: equ 0x80053BD4
Next: equ 0x80053CBC
While: equ 0x80053D3C
Ewhile: equ 0x80053E0C
Do: equ 0x80053E50
Edwhile: equ 0x80053EC4
While_main: equ 0x80053F50
Switch: equ 0x80054020
Case: equ 0x800540F8
Default: equ 0x80054110
Eswitch: equ 0x80054128
Goto: equ 0x8005415C
Gosub: equ 0x800541A8
Return: equ 0x80054210
Break: equ 0x80054268
Work_copy: equ 0x800542B4
Rbj_reset: equ 0x80054310
Ck: equ 0x80054354
Set: equ 0x800543B4
Cmp: equ 0x80054474
Save: equ 0x8005451C
Copy: equ 0x8005454C
Calc: equ 0x8005458C
Calc2: equ 0x800545D8
Calc_branch: equ 0x80054634
Sce_rnd: equ 0x80054760
Cut_chg: equ 0x8005478C
Cut_old: equ 0x8005481C
Cut_chg_main: equ 0x80054884
Cut_auto: equ 0x800548C8
Cut_replace: equ 0x80054930
Cut_be_set: equ 0x80054A14
Message_on: equ 0x80054A8C
Aot_set: equ 0x80054AF4
Aot_set_4p: equ 0x80054B60
Door_aot_set: equ 0x80054BE4
Door_aot_set_4p: equ 0x80054C50
Item_aot_set: equ 0x80054CD4
Item_aot_set_4p: equ 0x80055008
Aot_reset: equ 0x80055154
Aot_on: equ 0x800551C8
Obj_model_set: equ 0x80055260
Super_set: equ 0x8005550C
Super_on: equ 0x80055680
Super_reset: equ 0x800558B0
Work_set: equ 0x80055904
Parts_set: equ 0x800559D0
Speed_set: equ 0x80055A84
Add_speed: equ 0x80055AB0
Add_aspeed: equ 0x80055B2C
Pos_set: equ 0x80055BA0
Dir_set: equ 0x80055BD0
Member_set: equ 0x80055C00
Member_set2: equ 0x80055C50
Member_set_branch: equ 0x80055CB0
Member_copy: equ 0x80055E38
Member_cmp: equ 0x80055E8C
Load_member_branch: equ 0x80055F50
Member_calc: equ 0x80056188
Member_calc2: equ 0x800561F4
Load_member_addr_branch: equ 0x80056264
Dir_ck: equ 0x800563E8
Se_on: equ 0x80056428
Sca_id_set: equ 0x8005655C
Sce_espr_on: equ 0x800565A4
Sce_espr_on2: equ 0x80056644
Sce_espr3d_on: equ 0x800566F0
Sce_espr3d_on2: equ 0x800567B4
Sce_espr_kill: equ 0x80056884
Sce_espr_kill2: equ 0x800568E8
Sce_espr_control: equ 0x800569D4
Get_matrix: equ 0x80056A38
Plc_motion: equ 0x80056B8C
Plc_dest: equ 0x80056BD8
Plc_gun: equ 0x80056DC0
Plc_gun_eff: equ 0x80056DF8
Plc_neck: equ 0x80056E5C
Plc_ret: equ 0x80056F9C
Plc_stop: equ 0x80056FF0
Plc_flg: equ 0x80057038
Plc_rot: equ 0x800570BC
Plc_cnt: equ 0x80057120
Sce_em_set: equ 0x8005714C
Sce_key_ck: equ 0x80057DA8
Sce_trg_ck: equ 0x80057DE4
Sce_bgm_control: equ 0x80057E20
Sce_bgmtbl_set: equ 0x80057E98
Sce_fade_set: equ 0x80057EF0
Sce_fade_adjust: equ 0x80057FD8
Xa_on: equ 0x80058028
Xa_vol: equ 0x80058090
Se_vol: equ 0x800580CC
Sce_shake_on: equ 0x80058164
Sce_line_start: equ 0x80058214
Sce_line_main: equ 0x80058260
Sce_line_end: equ 0x800582B8
Mizu_div_set: equ 0x800582F0
Keep_Item_ck: equ 0x800584F0
Sce_Item_lost: equ 0x800585E4
Sce_Item_lost2: equ 0x80058660
Weapon_chg: equ 0x80058704
Sce_Item_get: equ 0x800587B8
Kage_set: equ 0x80058898
Light_pos_set: equ 0x800589D4
Light_kido_set: equ 0x80058A8C
Light_color_set: equ 0x80058AD8
Light_pos_set2: equ 0x80058B40
Light_kido_set2: equ 0x80058BFC
Light_color_set2: equ 0x80058C4C
Sce_scr_move: equ 0x80058CB8
Flr_set: equ 0x80058CE4
Movie_on: equ 0x80058D64
Splc_ret: equ 0x80058DAC
Splc_sce: equ 0x80058E48
Evt_next2: equ 0x80058EB0
Mirror_set: equ 0x80058EF8
Sce_parts_bomb: equ 0x80058F78
Sce_parts_down: equ 0x80059030
Col_chg_set: equ 0x800590E0
Poison_ck: equ 0x800592F8
Poison_clr: equ 0x80059318
Vib_set0: equ 0x80059348
Vib_set1: equ 0x80059394
Vib_fade_set: equ 0x800593E4
Snd_sys_init: equ 0x80059438
Snd_sys_init2: equ 0x80059514
Snd_sys_Allvoff: equ 0x80059634
Snd_sys_init_sub: equ 0x80059654
Snd_sys_init_sub2: equ 0x800598A8
Snd_sys_start: equ 0x8005990C
Snd_sys_stereo: equ 0x8005998C
Snd_sys_core_set: equ 0x80059A00
Snd_sys_arms_set: equ 0x80059C74
Snd_sys_room_set: equ 0x80059E54
Snd_sys_enem_set: equ 0x8005A09C
Snd_sys_pset: equ 0x8005A338
Snd_bgm_data: equ 0x8005A414
Snd_bgm_set: equ 0x8005A444
Snd_bgm_ck: equ 0x8005A714
Snd_bgm_play_ck: equ 0x8005A888
Snd_bgm_main: equ 0x8005A97C
Snd_bgm_sub: equ 0x8005AE50
Snd_bgm_fade_ON: equ 0x8005B2E4
Snd_bgm_fade: equ 0x8005B3B0
Snd_bgm_ctr: equ 0x8005B6F0
Snd_bgm_tbl_set: equ 0x8005B9F4
Snd_se_stad: equ 0x8005BA28
Snd_se_enem: equ 0x8005BD6C
Snd_se_walk: equ 0x8005C040
Snd_se_call: equ 0x8005C5E4
Snd_se_pri_ck: equ 0x8005C92C
Snd_se_3D: equ 0x8005C970
Snd_se_dir_ck: equ 0x8005CDA4
Spl: equ 0x8005CFC8
Spl_mv40: equ 0x8005D0BC
Spl_mv42: equ 0x8005D10C
Spl_mv41: equ 0x8005D12C
Spl_mv44: equ 0x8005D1D0
Spl_mv45: equ 0x8005D238
Spl_mv47: equ 0x8005D27C
Spl_mv49: equ 0x8005D29C
Spl_mv48: equ 0x8005D2BC
Spl_mv4a: equ 0x8005D2DC
Spl_mv4b: equ 0x8005D30C
Spl_mv50: equ 0x8005D314
Spl_mv51: equ 0x8005D3A4
Spl_mv00: equ 0x8005D3C4
Spl_Init: equ 0x8005D3CC
Spl_in40: equ 0x8005D85C
Spl_in42: equ 0x8005DA3C
Spl_in41: equ 0x8005DA94
Spl_in44: equ 0x8005DC74
Spl_in45: equ 0x8005DDDC
Spl_in47: equ 0x8005DED8
Spl_in48: equ 0x8005DF30
Spl_in4a: equ 0x8005DF38
Spl_in4b: equ 0x8005E1C0
Spl_in50: equ 0x8005E1F8
Spl_in51: equ 0x8005E2A0
Spl_in00: equ 0x8005E358
Spl_Damage: equ 0x8005E360
Spl_Die: equ 0x8005E39C
Spl_Dead: equ 0x8005E3D8
Spl_dead00: equ 0x8005E414
Spl_set: equ 0x8005E41C
Spl_chenge00: equ 0x8005E50C
Spl_chenge01: equ 0x8005E6F0
Spl_kizu00: equ 0x8005EAAC
Spl_chenge02: equ 0x8005EB80
Spl_chenge04: equ 0x8005ECFC
Spl_chenge05: equ 0x8005F044
Spl_chenge06: equ 0x8005F354
Spl_chenge07: equ 0x8005F634
Spl_chenge08: equ 0x8005FBB4
Spl_chenge09: equ 0x8005FE6C
Spl_chenge10: equ 0x800600B8
Spl_Root_ck_sys: equ 0x80060374
Spl_Auto: equ 0x800605AC
Aida: equ 0x80060648
Aida_move: equ 0x80060650
Aida_Move_type00: equ 0x80060750
Aida_Move_type01: equ 0x800607D4
Aida_Move_type02: equ 0x80060858
Aida_Move_type03: equ 0x800608DC
Aida_Move_type04: equ 0x80060960
Aida_Move_type05: equ 0x800609E4
Aida_Move_type06: equ 0x80060A68
Aida_Move_type07: equ 0x80060AEC
Aida_Move_type08: equ 0x80060B70
Aida_Move_type09: equ 0x80060BF4
Aida_Move_type0a: equ 0x80060C78
Aida_em10_at00_pl: equ 0x80060CFC
Aida_em10_at00_spl: equ 0x80060E08
Aida_em25_at00_pl: equ 0x80060EE4
Aida_em25_at00_spl: equ 0x80060FEC
Aida_em26_at00_pl: equ 0x80061140
Aida_em26_at00_spl: equ 0x80061148
Aida_mv00_br: equ 0x80061150
Aida_mv00_br_1: equ 0x800613C0
Aida_mv00: equ 0x800614F8
Aida_em10_at01: equ 0x80061594
Aida_em25_at01: equ 0x80061654
Aida_em26_at01: equ 0x8006170C
Aida_mv01_br: equ 0x80061714
Aida_mv01_br_1: equ 0x800619E4
Aida_mv01: equ 0x80061BBC
Aida_mv02_br: equ 0x80061D90
Aida_mv02_br_1: equ 0x80061F68
Aida_mv02: equ 0x800620EC
Aida_mv03_br: equ 0x80062248
Aida_mv03: equ 0x80062318
Aida_mv04_br: equ 0x80062490
Aida_mv04: equ 0x800624F8
Aida_mv05_br: equ 0x800625DC
Aida_mv05: equ 0x80062618
Aida_mv05_w1: equ 0x80062678
Aida_mv05_w1_t0_br: equ 0x800626B4
Aida_mv05_w1_t0: equ 0x800626BC
Aida_em10_at05: equ 0x800627DC
Aida_mv05_w1_t1_br: equ 0x800628C4
Aida_mv05_w1_t1: equ 0x80062954
Aida_mv05_w1_t2_br: equ 0x80062A20
Aida_mv05_w1_t2: equ 0x80062A28
Aida_mv05_w1_t3_br: equ 0x80062C44
Aida_mv05_w1_t3: equ 0x80062C4C
Aida_mv05_w1_t4_br: equ 0x80062CC0
Aida_mv05_w1_t4: equ 0x80062CC8
Aida_mv05_w1_t5_br: equ 0x80062D24
Aida_mv05_w1_t5: equ 0x80062D2C
Aida_mv06_br: equ 0x80062DC4
Aida_mv06: equ 0x80062DCC
Aida_mv07_br: equ 0x80062E90
Aida_mv07: equ 0x80062E98
Aida_mv08_br: equ 0x80063164
Aida_mv08: equ 0x8006316C
Aida_mv09_br: equ 0x8006351C
Aida_mv09: equ 0x80063524
Aida_mv0a_br: equ 0x800638C0
Aida_mv0a: equ 0x800638C8
Aida_mv0b_br: equ 0x800638D0
Aida_mv0b_br_1: equ 0x80063930
Aida_mv0b: equ 0x80063998
Aida_mv0c_br: equ 0x800639A0
Aida_mv0c_br_1: equ 0x80063ABC
Aida_mv0d_br: equ 0x80063B94
Sherry_move: equ 0x80063BEC
Sherry_Move_type00: equ 0x80063CEC
Sherry_Move_type01: equ 0x80063D8C
Sherry_Move_type02: equ 0x80063E2C
Sherry_Move_type03: equ 0x80063ECC
Sherry_Move_type04: equ 0x80063F6C
Sherry_Move_type05: equ 0x8006400C
Sherry_Move_type06: equ 0x800640AC
Sherry_Move_type07: equ 0x8006414C
Sherry_Move_type08: equ 0x800641EC
Sherry_Move_type09: equ 0x8006428C
Sherry_Move_type0a: equ 0x8006432C
Sherry_mv00_br: equ 0x800643CC
Sherry_mv00: equ 0x800645D8
Sherry_mv01_br: equ 0x80064814
Sherry_mv02_br: equ 0x80064ACC
Sherry_mv06_br: equ 0x80064D90
Sherry_mv0b_br: equ 0x80064E5C
Sherry_mv0c_br: equ 0x80064EBC
Spl_dm00: equ 0x80064FA8
Spl_dm01: equ 0x800650A8
Spl_die00: equ 0x800651F0
Aida_before: equ 0x800652FC
Aida_after: equ 0x8006531C
Spl_soba_pos_set: equ 0x80065324
Spl_enemy_ck: equ 0x80065518
Spl_em_pos_ck: equ 0x80065890
Spl_em_cdir_ck: equ 0x80065A0C
Spl_pllock_get: equ 0x80065B18
GsGetWorkBase: equ 0x80065B8C
Spl_life_down: equ 0x80065B9C
Spl_Scenario: equ 0x80065C88
Spl_sce00: equ 0x80065DD0
Spl_sce01: equ 0x80065DF8
Spl_sce02: equ 0x80065E18
Spl_sce03: equ 0x80065E40
Spl_sce04: equ 0x80065E68
Spl_sce05: equ 0x80065FB8
Spl_sce06: equ 0x80066138
Spl_sce07: equ 0x800661C0
Spl_sce08: equ 0x8006629C
Spl_sce09: equ 0x8006637C
Spl_sce0a: equ 0x80066450
Spl_sce0b: equ 0x80066478
Spl_sce0c: equ 0x80066498
Spl_sce0d: equ 0x800664C0
Spl_sce0e: equ 0x800664E8
Spl_sce0f: equ 0x800664F0
Spl_sce10: equ 0x800664F8
Spl_sce11: equ 0x80066500
Spl_sce12: equ 0x80066508
Spl_sce13: equ 0x8006667C
Spl_sce14: equ 0x80066684
Spl_sce15: equ 0x8006668C
Spl_sce16: equ 0x80066760
Spl_sce17: equ 0x80066768
Spl_sce18: equ 0x80066770
Spl_sce20: equ 0x80066778
Spl_sce_mv00: equ 0x800669B0
Spl_sce_mv01: equ 0x80066AFC
Spl_sce_mv02: equ 0x80066BCC
Spl_sce_mv03: equ 0x80066D24
Spl_sce_mv04: equ 0x80066DEC
Spl_Sp_Move: equ 0x80067004
Spl_sp40_00: equ 0x8006704C
Spl_sp44_00: equ 0x80067984
Status_init: equ 0x80068068
Status_init_m: equ 0x80068484
Status: equ 0x800689BC
St_exit: equ 0x80068CD4
St_fade_out_set: equ 0x80068F08
St_fade_out_wait: equ 0x80068F40
St_chenge_pl: equ 0x80068F9C
pl_tim_load: equ 0x80069210
St_file_set: equ 0x800692DC
St_room_set: equ 0x8006931C
St_disp_name: equ 0x800693D0
Set_iwork: equ 0x8006947C
Set_iwork_num: equ 0x800694B8
Check_pl_life: equ 0x80069538
Check_item_space: equ 0x80069590
Check_item_mix: equ 0x800695B0
Search_item: equ 0x80069668
Search_item_id: equ 0x800696CC
Sort_item: equ 0x80069714
Shift_item: equ 0x800698B4
Set_item: equ 0x80069ADC
Pix_trans: equ 0x80069BB4
Pix_trans_pl: equ 0x80069C40
Pix_move: equ 0x80069D88
Pix_clear: equ 0x80069E54
St_pltex_operation: equ 0x80069EEC
Tama_ck_i: equ 0x80069F54
Tama_decrease_i: equ 0x8006A0CC
Tama_reload_ck: equ 0x8006A23C
Tama_reload: equ 0x8006A2B4
Check_cursol_distance: equ 0x8006A38C
St_init00: equ 0x8006A574
St_main00: equ 0x8006A774
St_menu0_select: equ 0x8006A7F0
St_menu0_item: equ 0x8006A994
St_com_use_equip: equ 0x8006AFFC
St_com_mix: equ 0x8006B358
St_com_inspect: equ 0x8006C2B0
St_menu0_file: equ 0x8006C6E4
file_moji_load: equ 0x8006D444
move_file_tag: equ 0x8006D550
St_menu0_map: equ 0x8006D650
St_init_disp_map: equ 0x8006DEA0
St_disp_map: equ 0x8006E120
Check_map_no: equ 0x8006E7F0
Check_room_no: equ 0x8006EAE8
St_menu1_map: equ 0x8006ECB8
St_init03: equ 0x8006EFD8
St_main03: equ 0x8006F164
St_init04: equ 0x8006F6A8
St_main04: equ 0x8006F8B4
St_init01: equ 0x8006F900
St_main01: equ 0x8006FB64
St_select_menu_m: equ 0x8006FBD4
St_select_item_m: equ 0x8006FC58
Exchange_item: equ 0x800703B8
St_init_itembox: equ 0x80070E58
St_disp_itembox: equ 0x800710DC
St_init02: equ 0x80071BA0
St_main02: equ 0x80071E14
St_get_check: equ 0x80071EB4
St_get_item: equ 0x80072050
St_disp_file2: equ 0x800724B4
St_get_file: equ 0x8007274C
St_init_disp_num: equ 0x80072C1C
St_disp_num: equ 0x80072C6C
print_num: equ 0x8007300C
St_init_disp_cursol0: equ 0x80073250
St_disp_cursol0: equ 0x80073350
St_init_disp_cursol1: equ 0x80073578
St_disp_cursol1: equ 0x80073674
St_init_disp_face: equ 0x80073880
St_disp_face: equ 0x80073AB0
St_init_disp_message: equ 0x80073DA0
St_disp_message: equ 0x80073ED0
St_init_disp_frame: equ 0x80074014
St_disp_frame: equ 0x80074160
St_init_disp_menu0: equ 0x80074300
St_disp_menu0: equ 0x800743F8
St_init_disp_menu1: equ 0x80074610
St_disp_menu1: equ 0x80074888
St_init_disp_itemlist: equ 0x80074A94
St_disp_itemlist: equ 0x80074BB0
St_init_disp_equip: equ 0x80074E80
St_disp_equip: equ 0x80074F4C
St_init_disp_wall: equ 0x800751EC
St_disp_wall: equ 0x8007526C
St_init_disp_ECG: equ 0x80075360
St_disp_ECG: equ 0x800754AC
St_init_disp_itp: equ 0x80075A00
St_disp_itp: equ 0x80075C28
St_init_disp_filesel: equ 0x80075DC4
St_disp_filesel: equ 0x80075E98
St_init_disp_file: equ 0x80075FD0
St_disp_file: equ 0x800761B8
ST_Om_trans: equ 0x80076498
model_disp: equ 0x80076640
Vram_clr: equ 0x800769C4
Memcpy: equ 0x80076A00
Memclr: equ 0x80076A28
Mapping_tim: equ 0x80076A40
Mapping_tmd: equ 0x80076B60
Set_view: equ 0x80076CB0
Set_light: equ 0x80076F88
Set_Light_data: equ 0x80077200
Flg_on: equ 0x8007730C
Flg_off: equ 0x80077334
Flg_ck: equ 0x80077360
Enemy_st_view: equ 0x80077384
Rot_vector_super: equ 0x800773EC
Rot_add_matrix: equ 0x8007746C
Set_front_pos: equ 0x80077600
SetSpadStack: equ 0x8007769C
ResetSpadStack: equ 0x800776D8
SetSpadStack2: equ 0x80077708
ResetSpadStack2: equ 0x8007774C
Get_work: equ 0x8007777C
Free_work: equ 0x800777F4
Prim_trans: equ 0x80077874
Trans_pointer_set: equ 0x800778F8
Eff_sprt_trans: equ 0x80077924
Esp_trans_main: equ 0x80077ED0
Esp_trans_3d: equ 0x80078174
Trans_work_init: equ 0x800783B4
__main: equ 0x80078400
start: equ 0x80078408
stup1: equ 0x8007842C
stup0: equ 0x800784A8
SpuClearReverbWorkArea: equ 0x800784C4
_spu_init: equ 0x80078660
_spu_writeByIO: equ 0x800788F4
_spu_FiDMA: equ 0x80078AC0
_spu_r_: equ 0x80078B80
_spu_t: equ 0x80078C2C
_spu_write: equ 0x80078EBC
_spu_read: equ 0x80078F44
_spu_FsetRXX: equ 0x80078FAC
_spu_FsetRXXa: equ 0x80078FF4
_spu_FgetRXXa: equ 0x80079098
_spu_FsetPCR: equ 0x800790D4
_spu_FsetDelayW: equ 0x80079134
_spu_FsetDelayR: equ 0x80079160
_spu_FwaitFs: equ 0x8007918C
_SpuInit: equ 0x800791F4
SpuStart: equ 0x800792EC
_SpuDataCallback: equ 0x80079368
_SpuIsInAllocateArea: equ 0x8007938C
_SpuIsInAllocateArea_: equ 0x8007940C
SpuGetKeyStatus: equ 0x80079694
SpuSetTransferMode: equ 0x80079728
_SsClose: equ 0x80079E34
SsSeqClose: equ 0x80079FB0
SsSepClose: equ 0x80079FD4
_SsSndSetDecres: equ 0x80079FF8
SsSeqSetDecrescendo_0: equ 0x8007A120
SsSeqSetDecrescendo: equ 0x8007A188
SsEnd: equ 0x8007A280
_SsInit: equ 0x8007A344
SsInit: equ 0x8007A42C
SpuInit: equ 0x8007A45C
SsSetLoop: equ 0x8007A47C
SsIsEos: equ 0x8007A4BC
SsSeqOpen: equ 0x8007A4FC
_SsContBankChange: equ 0x8007A81C
_SsContDataEntry: equ 0x8007A894
_SsContMainVol: equ 0x8007ACBC
_SsContPanpot: equ 0x8007AD8C
_SsContExpression: equ 0x8007AE54
_SsContDamper: equ 0x8007AF3C
SsSetTempo: equ 0x8007AF50
_SsContExternal: equ 0x8007AFE4
_SsContNrpn1: equ 0x8007B06C
_SsContNrpn2: equ 0x8007B19C
_SsContRpn1: equ 0x8007B2D0
_SsContRpn2: equ 0x8007B340
_SsContResetAll: equ 0x8007B3B0
_SsSetNrpnVabAttr0: equ 0x8007B46C
_SsSetNrpnVabAttr1: equ 0x8007B4FC
_SsSetNrpnVabAttr2: equ 0x8007B5B8
_SsSetNrpnVabAttr3: equ 0x8007B648
_SsSetNrpnVabAttr4: equ 0x8007B6D8
_SsUtResolveADSR: equ 0x8007B78C
_SsUtBuildADSR: equ 0x8007B7E8
_SsSetNrpnVabAttr5: equ 0x8007B888
_SsSetNrpnVabAttr6: equ 0x8007B940
_SsSetNrpnVabAttr7: equ 0x8007B9F0
_SsSetNrpnVabAttr8: equ 0x8007BAA0
_SsSetNrpnVabAttr9: equ 0x8007BB54
_SsSetNrpnVabAttr10: equ 0x8007BC0C
_SsSetNrpnVabAttr11: equ 0x8007BCC0
_SsSetNrpnVabAttr12: equ 0x8007BD68
_SsSetNrpnVabAttr13: equ 0x8007BE44
_SsSetNrpnVabAttr14: equ 0x8007BEE4
_SsSetNrpnVabAttr15: equ 0x8007BF84
_SsSetNrpnVabAttr16: equ 0x8007BFA8
_SsSetNrpnVabAttr17: equ 0x8007BFD0
_SsSetNrpnVabAttr18: equ 0x8007BFF4
_SsSetNrpnVabAttr19: equ 0x8007C018
_SsSetPitchBend: equ 0x8007C03C
_SsSetControlChange: equ 0x8007C0EC
_SsGetMetaEvent: equ 0x8007C324
_SsNoteOn: equ 0x8007C4F4
_SsSetProgramChange: equ 0x8007C5C8
_SsReadDeltaValue: equ 0x8007C638
_SsInitSoundSeq: equ 0x8007C6E8
_SsSndSetPauseMode: equ 0x8007CA34
SsSeqPause: equ 0x8007CB04
SsSepPause: equ 0x8007CB2C
SsSeqPlay: equ 0x8007CB58
SsSepPlay: equ 0x8007CB90
SsQuit: equ 0x8007CBC8
SpuQuit: equ 0x8007CBE8
_SsSndSetReplayMode: equ 0x8007CC64
SsSeqReplay: equ 0x8007CD00
SsSepReplay: equ 0x8007CD28
Snd_SetPlayMode: equ 0x8007CD54
SsSetSerialAttr: equ 0x8007CE70
SpuSetCommonAttr: equ 0x8007CF04
SsSetMVol: equ 0x8007D298
SsSetRVol: equ 0x8007D2E8
SpuSetReverbDepth: equ 0x8007D370
_SsStart: equ 0x8007D3E8
SsStart: equ 0x8007D650
SsStart2: equ 0x8007D670
_SsTrapIntrVSync: equ 0x8007D690
_SsSeqCalledTbyT_1per2: equ 0x8007D6D0
SsSeqCalledTbyT: equ 0x8007D720
_SsSndCrescendo: equ 0x8007D994
_SsSndDecrescendo: equ 0x8007DCB4
_SsSndPause: equ 0x8007E060
_SsSndPlay: equ 0x8007E0FC
_SsSeqPlay: equ 0x8007E128
_SsSeqGetEof: equ 0x8007E230
_SsGetSeqData: equ 0x8007E474
_SsSndNextSep: equ 0x8007E818
_SsSndReplay: equ 0x8007E914
_SsSndStop: equ 0x8007E974
SsSeqStop: equ 0x8007EAF8
SsSepStop: equ 0x8007EB20
SsSetSerialVol: equ 0x8007EB4C
SsSetTableSize: equ 0x8007EC48
SsSetTickMode: equ 0x8007EE20
_SsSndSetVol: equ 0x8007EF8C
SsSeqSetVol: equ 0x8007F018
SsSepSetVol: equ 0x8007F078
SsSeqGetVol: equ 0x8007F104
_SsSndTempo: equ 0x8007F138
SsUtAllKeyOff: equ 0x8007F358
SsUtGetProgAtr: equ 0x8007FA84
SsUtGetVagAtr: equ 0x8007FB8C
SsUtKeyOn: equ 0x8007FDC8
SsUtKeyOff: equ 0x80080164
SsUtKeyOnV: equ 0x800802B8
SsUtKeyOffV: equ 0x8008064C
SsUtSetReverbDelay: equ 0x800806C4
SpuSetReverbModeParam: equ 0x80080704
_spu_setReverbAttr: equ 0x80080BFC
SsUtSetReverbDepth: equ 0x800810CC
SsUtSetReverbType: equ 0x80081164
SsUtGetReverbType: equ 0x80081208
SpuSetReverb: equ 0x80081218
SsUtSetReverbFeedback: equ 0x800812E8
SsUtReverbOff: equ 0x80081328
SsUtReverbOn: equ 0x80081348
SsUtSetVagAtr: equ 0x80081368
SsUtGetDetVVol: equ 0x80081530
SsUtSetDetVVol: equ 0x8008156C
SsUtGetVVol: equ 0x800815D8
SsUtSetVVol: equ 0x80081688
SpuGetVoiceVolume: equ 0x80081714
_SsVmAlloc: equ 0x80081774
SpuSetNoiseVoice: equ 0x80081A00
_SpuSetAnyVoice: equ 0x80081A24
_SsVmDoAllocate: equ 0x80081CEC
_SsVmDamperOff: equ 0x80081EFC
_SsVmDamperOn: equ 0x80081F0C
_SsVmFlush: equ 0x80081F20
_SsVmInit: equ 0x8008239C
SpuInitMalloc: equ 0x800826BC
_spu_setInTransfer: equ 0x80082710
_spu_getInTransfer: equ 0x8008273C
_SsVmKeyOn: equ 0x80082754
_SsVmKeyOff: equ 0x80082CD8
_SsVmSeKeyOn: equ 0x80082E24
_SsVmSeKeyOff: equ 0x80082F10
KeyOnCheck: equ 0x80082F44
note2pitch: equ 0x80082F4C
note2pitch2: equ 0x80083010
vmNoiseOn: equ 0x8008310C
_SsVmKeyOffNow: equ 0x80083690
_SsVmKeyOnNow: equ 0x80083760
_SsVmPBVoice: equ 0x80083C2C
_SsVmPitchBend: equ 0x80083E2C
_SsVmSetProgVol: equ 0x80083F1C
_SsVmGetProgVol: equ 0x80083F90
_SsVmSetProgPan: equ 0x80083FE4
_SsVmGetProgPan: equ 0x80084058
_SsVmSetSeqVol: equ 0x800840AC
_SsVmGetSeqVol: equ 0x800845E8
_SsVmGetSeqLVol: equ 0x8008464C
_SsVmGetSeqRVol: equ 0x80084694
_SsVmSeqKeyOff: equ 0x800846DC
_SsVmSelectToneAndVag: equ 0x80084778
_SsVmSetVol: equ 0x8008482C
_SsVmVSetUp: equ 0x80084DA8
SsSetMono: equ 0x80084E6C
SsSetStereo: equ 0x80084E80
SsSetReservedVoice: equ 0x80084E90
SsVabClose: equ 0x80084EC0
SpuFree: equ 0x80084F44
_spu_gcSPU: equ 0x80084FC0
SsVabFakeBody: equ 0x800852C8
SsVabOpenHead: equ 0x80085338
SsVabOpenHeadSticky: equ 0x80085368
SsVabFakeHead: equ 0x80085398
SsVabOpenHeadWithMode: equ 0x800853C8
SpuMalloc: equ 0x800857A4
SsVabTransBody: equ 0x80085A6C
SpuWrite: equ 0x80085B2C
SpuSetTransferStartAddr: equ 0x80085B8C
SsVabTransBodyPartly: equ 0x80085BE4
SpuWritePartly: equ 0x80085D44
SsVabTransCompleted: equ 0x80085DD0
SpuIsTransferCompleted: equ 0x80085DF8
VSync: equ 0x80085EA0
v_wait: equ 0x80085FE8
ResetCallback: equ 0x80086084
InterruptCallback: equ 0x800860B4
DMACallback: equ 0x800860E4
VSyncCallback: equ 0x80086114
VSyncCallbacks: equ 0x80086148
StopCallback: equ 0x80086178
RestartCallback: equ 0x800861A8
CheckCallback: equ 0x800861D8
GetIntrMask: equ 0x800861E8
SetIntrMask: equ 0x80086200
startIntr: equ 0x8008621C
trapIntr: equ 0x800862F8
setIntr: equ 0x800864E0
stopIntr: equ 0x80086634
restartIntr: equ 0x800866E0
startIntrVSync: equ 0x80086794
trapIntrVSync: equ 0x800867EC
setIntrVSync: equ 0x80086864
startIntrDMA: equ 0x800868BC
trapIntrDMA: equ 0x8008690C
setIntrDMA: equ 0x80086A90
;;memclr: equ 0x80086B38 ;; commented out because armips has trouble with character casing and a variable at 0x80076A28 has similar name
SetVideoMode: equ 0x80086B64
GsGetWorkBase_0: equ 0x80086B7C
StSetRing: equ 0x80086B8C
StClearRing: equ 0x80086BBC
StUnSetRing: equ 0x80086C1C
CdStatus: equ 0x80086CA0
;;CdMode: equ 0x80086CB0 ;; commented out because armips has trouble with character casing and a variable at 0x8009a414 has similar name
CdLastCom: equ 0x80086CC0
CdLastPos: equ 0x80086CD0
CdReset: equ 0x80086CE0
CdFlush: equ 0x80086D4C
CdSetDebug: equ 0x80086D6C
CdComstr: equ 0x80086D84
CdIntstr: equ 0x80086DB8
CdSync: equ 0x80086DEC
CdReady: equ 0x80086E0C
CdSyncCallback: equ 0x80086E2C
CdReadyCallback: equ 0x80086E44
CdControl: equ 0x80086E5C
CdControlF: equ 0x80086F94
CdControlB: equ 0x800870C0
CdMix: equ 0x80087204
CdGetSector: equ 0x80087224
CdGetSector2: equ 0x80087244
CdDataCallback: equ 0x80087264
CdDataSync: equ 0x80087288
CdIntToPos: equ 0x800872AC
CdPosToInt: equ 0x800873AC
getintr: equ 0x8008742C
CD_sync: equ 0x800879B4
CD_ready: equ 0x80087C34
CD_cw: equ 0x80087F00
CD_vol: equ 0x8008831C
CD_flush: equ 0x800883A4
CD_initvol: equ 0x80088484
CD_initintr: equ 0x80088578
;;CD_init: equ 0x800885C8 ;; commented out because armips has trouble with character casing and a variable at 0x800128C4 has similar name
CD_datasync: equ 0x800887B4
CD_getsector: equ 0x80088920
CD_getsector2: equ 0x80088A20
CD_set_test_parmnum: equ 0x80088B10
callback: equ 0x80088B20
StSetStream: equ 0x80088C04
StFreeRing: equ 0x80088C8C
init_ring_status: equ 0x80088D44
StGetNext: equ 0x80088D80
StSetMask: equ 0x80088E44
StCdInterrupt: equ 0x80088E64
mem2mem: equ 0x800897D4
dma_execute: equ 0x80089808
data_ready_callback: equ 0x800899C4
StGetBackloc: equ 0x80089A50
StGetBackloc_0: equ 0x80089A54
CQ_clear_queue: equ 0x80089AB4
CQ_delete_command: equ 0x80089AE4
CQ_last_queue: equ 0x80089BD4
CQ_error_flush: equ 0x80089C2C
CQ_execute: equ 0x80089DE0
CQ_sync_system: equ 0x80089E58
CQ_add_result: equ 0x8008A080
DsInit: equ 0x8008A110
DsReset: equ 0x8008A254
DsClose: equ 0x8008A360
DsCommand: equ 0x8008A380
DsPacket: equ 0x8008A5A8
DsSync: equ 0x8008A8C4
DsReady: equ 0x8008AAC4
DsFlush: equ 0x8008AB74
DsSystemStatus: equ 0x8008AC04
GsGetWorkBase_1: equ 0x8008AC54
DsStatus: equ 0x8008AC64
DsShellOpen: equ 0x8008AC84
DsLastCom: equ 0x8008ACA4
CQ_vsync_system: equ 0x8008ACC4
CQ_ready_system: equ 0x8008AD6C
DS_init: equ 0x8008AE68
DS_reset_members: equ 0x8008AF04
DS_close: equ 0x8008B014
DS_cw: equ 0x8008B058
DS_vsync_callback: equ 0x8008B0DC
DS_sync_callback: equ 0x8008B0EC
DS_ready_callback: equ 0x8008B0FC
DS_system_status: equ 0x8008B10C
DS_lastcom: equ 0x8008B124
DS_lastmode: equ 0x8008B134
DS_lastpos: equ 0x8008B144
DS_lastseek: equ 0x8008B154
DS_lastread: equ 0x8008B164
DS_status: equ 0x8008B174
DS_sync: equ 0x8008B184
DS_ready: equ 0x8008B1A8
GsGetWorkBase_2: equ 0x8008B1CC
DS_cw_root: equ 0x8008B1DC
DS_vsync_system: equ 0x8008B2FC
DS_sync_system: equ 0x8008B5EC
DS_sync_for_user: equ 0x8008B6E0
DS_sync_for_system: equ 0x8008B8D8
DS_sync_for_void: equ 0x8008BA60
DS_ready_system: equ 0x8008BB70
DS_scan_result: equ 0x8008BC3C
DS_stop: equ 0x8008BCBC
DS_restart: equ 0x8008BD1C
GsGetWorkBase_3: equ 0x8008BD30
parcpy: equ 0x8008BD40
rescpy: equ 0x8008BD88
tipDsSystem: equ 0x8008BDD0
DsMix: equ 0x8008BEBC
DsGetSector: equ 0x8008BEDC
DsGetSector2: equ 0x8008BEFC
DsDataSync: equ 0x8008BF1C
DsIntToPos: equ 0x8008BF3C
DsPosToInt: equ 0x8008C040
DsSetDebug: equ 0x8008C0C0
DsLastPos: equ 0x8008C0D8
DsControlF: equ 0x8008C130
DsControl: equ 0x8008C158
DsControlB: equ 0x8008C1C4
DsRead: equ 0x8008C230
DS_read_cbsync: equ 0x8008C340
DS_read_cbready: equ 0x8008C374
DS_read_cbdata: equ 0x8008C534
DsReadSync: equ 0x8008C628
DsReadCallback: equ 0x8008C69C
DsReadBreak: equ 0x8008C6B4
DsReadMode: equ 0x8008C730
DsRead2: equ 0x8008C74C
StCdInterrupt2: equ 0x8008C82C
DsStartReadySystem: equ 0x8008C84C
DsEndReadySystem: equ 0x8008C8D8
ER_cbready: equ 0x8008C938
ER_retry: equ 0x8008CBC4
ER_cbsync: equ 0x8008CC44
DsSyncCallback: equ 0x8008cc78
DsReadyCallback: equ 0x8008cc8c
DsStartCallback: equ 0x8008CCA0
rsin: equ 0x8008CCC4
sin_1: equ 0x8008CD00
rcos: equ 0x8008CD90
MatrixNormal_0: equ 0x8008CE30
MatrixNormal_1: equ 0x8008CF50
MatrixNormal_2: equ 0x8008D068
MatrixNormal_3: equ 0x8008D070
catan: equ 0x8008D190
InitGeom: equ 0x8008D26C
SquareRoot0: equ 0x8008D2F4
InvSquareRoot: equ 0x8008D384
VectorNormalS: equ 0x8008D410
VectorNormal: equ 0x8008D424
VectorNormalSS: equ 0x8008D450
MatrixNormal: equ 0x8008D53C
SquareRoot12: equ 0x8008D624
MulMatrix0: equ 0x8008D6C4
ApplyMatrixLV: equ 0x8008D7D4
MulMatrix: equ 0x8008D934
MulMatrix2: equ 0x8008DA44
ApplyMatrix: equ 0x8008DB54
ApplyMatrixSV: equ 0x8008DBA4
ScaleMatrix: equ 0x8008DC04
SetRotMatrix: equ 0x8008DD34
SetLightMatrix: equ 0x8008DD64
SetColorMatrix: equ 0x8008DD94
SetTransMatrix: equ 0x8008DDC4
SetBackColor: equ 0x8008DDE4
SetGeomOffset: equ 0x8008DE04
SetGeomScreen: equ 0x8008DE24
LightColor: equ 0x8008DE34
DpqColorLight: equ 0x8008DE5C
DpqColor3: equ 0x8008DE84
Intpl: equ 0x8008DEC0
Square12: equ 0x8008DEE4
Square0: equ 0x8008DF0C
AverageZ3: equ 0x8008DF34
AverageZ4: equ 0x8008DF54
OuterProduct12: equ 0x8008DF78
OuterProduct0: equ 0x8008DFD0
Lzc: equ 0x8008E028
RotTransPers: equ 0x8008E044
RotTransPers3: equ 0x8008E074
RotAverage3: equ 0x8008E0D4
RotAverage4: equ 0x8008E134
TransposeMatrix: equ 0x8008E1B4
RotMatrix: equ 0x8008E1F4
RotMatrixYXZ: equ 0x8008E484
RotMatrixX: equ 0x8008E714
RotMatrixY: equ 0x8008E8B4
RotMatrixZ: equ 0x8008EA54
DivideGT3: equ 0x8008EBF4
ReadSZfifo3: equ 0x8008EDCC
RotAverageNclip3: equ 0x8008EDEC
RCpolyGT3: equ 0x8008EE7C
RCpolyGT3A: equ 0x8008EE84
ratan2: equ 0x8008F31C
_patch_gte: equ 0x8008F49C
LoadTPage: equ 0x8008F53C
LoadClut: equ 0x8008F628
LoadClut2: equ 0x8008F690
SetDefDrawEnv: equ 0x8008F6F8
SetDefDispEnv: equ 0x8008F7B0
GetTPage: equ 0x8008F7EC
GetClut: equ 0x8008F828
DumpTPage: equ 0x8008F840
DumpClut: equ 0x8008F8A0
NextPrim: equ 0x8008F8E0
IsEndPrim: equ 0x8008F8FC
AddPrim: equ 0x8008F918
AddPrims: equ 0x8008F954
CatPrim: equ 0x8008F990
TermPrim: equ 0x8008F9B4
SetSemiTrans: equ 0x8008F9CC
SetShadeTex: equ 0x8008F9F4
SetPolyF3: equ 0x8008FA1C
SetPolyFT3: equ 0x8008FA30
SetPolyG3: equ 0x8008FA44
SetPolyGT3: equ 0x8008FA58
SetPolyF4: equ 0x8008FA6C
SetPolyFT4: equ 0x8008FA80
SetPolyG4: equ 0x8008FA94
SetPolyGT4: equ 0x8008FAA8
SetSprt8: equ 0x8008FABC
SetSprt16: equ 0x8008FAD0
SetSprt: equ 0x8008FAE4
SetTile1: equ 0x8008FAF8
SetTile8: equ 0x8008FB0C
SetTile16: equ 0x8008FB20
SetTile: equ 0x8008FB34
SetLineF2: equ 0x8008FB48
SetLineG2: equ 0x8008FB5C
SetLineF3: equ 0x8008FB70
SetLineG3: equ 0x8008FB90
SetLineF4: equ 0x8008FBB0
SetLineG4: equ 0x8008FBD0
SetDrawTPage: equ 0x8008FBF0
SetDrawMove: equ 0x8008FC1C
SetDrawLoad: equ 0x8008FC7C
MargePrim: equ 0x8008FCE8
DumpDrawEnv: equ 0x8008FD20
DumpDispEnv: equ 0x8008FE34
ResetGraph: equ 0x8008FEE0
SetGraphReverse: equ 0x80090064
SetGraphDebug: equ 0x80090178
SetGraphQueue: equ 0x800901DC
GetGraphType: equ 0x80090288
GetGraphDebug: equ 0x80090298
DrawSyncCallback: equ 0x800902A8
SetDispMask: equ 0x80090304
DrawSync: equ 0x800903A0
checkRECT: equ 0x8009040C
ClearImage: equ 0x80090534
ClearImage2: equ 0x800905C8
LoadImage: equ 0x80090664
StoreImage: equ 0x800906C8
MoveImage: equ 0x8009072C
ClearOTag: equ 0x800907F0
ClearOTagR: equ 0x800908A8
DrawPrim: equ 0x80090940
DrawOTag: equ 0x800909A0
PutDrawEnv: equ 0x80090A14
DrawOTagEnv: equ 0x80090B18
GetDrawEnv: equ 0x80090C34
PutDispEnv: equ 0x80090C6C
GetDispEnv: equ 0x80091114
GetODE: equ 0x8009114C
SetTexWindow: equ 0x8009117C
SetDrawArea: equ 0x800911B8
SetDrawOffset: equ 0x8009123C
SetPriority: equ 0x80091280
SetDrawMode: equ 0x800912AC
SetDrawEnv: equ 0x80091304
SetDrawEnv2: equ 0x8009151C
get_mode: equ 0x800917AC
get_cs: equ 0x80091804
get_ce: equ 0x800918D0
get_ofs: equ 0x8009199C
get_tw: equ 0x800919E0
get_dx: equ 0x80091A64
_status: equ 0x80091B14
_otc: equ 0x80091B2C
_clr: equ 0x80091C14
_dws: equ 0x80091E70
_drs: equ 0x800920AC
_ctl: equ 0x80092330
_getctl: equ 0x80092358
_cwb: equ 0x8009236C
_cwc: equ 0x800923BC
_param: equ 0x80092408
_addque: equ 0x80092438
_addque2: equ 0x8009245C
_exeque: equ 0x8009273C
_reset: equ 0x80092A28
_sync: equ 0x80092B84
set_alarm: equ 0x80092CCC
get_alarm: equ 0x80092D00
_version: equ 0x80092E6C
OpenTIM: equ 0x80092F74
ReadTIM: equ 0x80092F84
OpenTMD: equ 0x80092FEC
ReadTMD: equ 0x8009302C
get_tim_addr: equ 0x800932D8
get_tmd_addr: equ 0x800933F8
unpack_packet: equ 0x80093590
DecDCTReset: equ 0x80094870
DecDCTGetEnv: equ 0x800948A8
DecDCTPutEnv: equ 0x80094934
DecDCTBufSize: equ 0x800949D0
DecDCTin: equ 0x800949DC
DecDCTout: equ 0x80094A58
DecDCTinSync: equ 0x80094A78
DecDCToutSync: equ 0x80094AB4
DecDCTinCallback: equ 0x80094AF0
DecDCToutCallback: equ 0x80094B14
MDEC_reset: equ 0x80094B38
MDEC_in: equ 0x80094C34
MDEC_out: equ 0x80094CC8
MDEC_in_sync: equ 0x80094D58
MDEC_out_sync: equ 0x80094DF0
MDEC_status: equ 0x80094E88
timeout: equ 0x80094EA0
DecDCTvlcSize2: equ 0x80094FD4
DecDCTvlc2: equ 0x80095004
_bu_init: equ 0x80095368
InitCARD: equ 0x80095378
StartCARD: equ 0x800953CC
StopCARD: equ 0x80095404
InitCARD2: equ 0x80095434
StartCARD2: equ 0x80095444
StopCARD2: equ 0x80095454
_ExitCard: equ 0x80095464
_patch_card: equ 0x8009553C
_patch_card2: equ 0x800955F4
InitHeap: equ 0x80095684
FlushCache: equ 0x80095694
GPU_cw: equ 0x800956A4
_96_remove: equ 0x800956BC
DeliverEvent: equ 0x800956D4
OpenEvent: equ 0x800956E4
CloseEvent: equ 0x800956F4
WaitEvent: equ 0x80095704
TestEvent: equ 0x80095714
EnableEvent: equ 0x80095724
DisableEvent: equ 0x80095734
OpenTh: equ 0x80095744
CloseTh: equ 0x80095754
ChangeTh: equ 0x80095764
ReturnFromException: equ 0x80095774
ResetEntryInt: equ 0x80095784
HookEntryInt: equ 0x80095794
EnterCriticalSection: equ 0x800957A4
ExitCriticalSection: equ 0x800957B4
open: equ 0x800957C4
lseek: equ 0x800957D4
read: equ 0x800957E4
write: equ 0x800957F4
close: equ 0x80095804
format: equ 0x80095814
nextfile: equ 0x80095824
ChangeClearPAD: equ 0x80095834
GetGp: equ 0x80095844
ChangeClearRCnt: equ 0x80095854
SetRCnt: equ 0x80095864
GetRCnt: equ 0x80095900
StartRCnt: equ 0x80095938
StopRCnt: equ 0x80095968
ResetRCnt: equ 0x8009599C
firstfile: equ 0x800959D4
firstfile2: equ 0x80095C74
PadEnableCom: equ 0x80096134
_padSetVsyncParam: equ 0x8009624C
_IsVSync: equ 0x80096278
_padChkVsync: equ 0x8009644C
_padStartCom: equ 0x80096460
_padStopCom: equ 0x8009652C
_padInitSioMode: equ 0x80096570
_padSioRW: equ 0x8009696C
_padSioRW2: equ 0x80096B44
SysEnqIntRP: equ 0x80096D14
SysDeqIntRP: equ 0x80096D24
_padClrIntSio0: equ 0x80096D7C
_padWaitRXready: equ 0x80096E0C
PadInitDirect: equ 0x80097C74
setRC2wait: equ 0x80098754
chkRC2wait: equ 0x80098774
puts: equ 0x8009881C
setjmp: equ 0x80098834
strcpy: equ 0x80098854
bzero: equ 0x80098864
;;memcpy: equ 0x80098874 ;; commented out because armips has trouble with character casing and a variable at 0x80076A00 has similar name
memset: equ 0x80098884
printf: equ 0x80098894
FUN_8003947c: equ 0x8003947c
FUN_80039514: equ 0x80039514
FUN_800395b8: equ 0x800395b8
FUN_80039694: equ 0x80039694
FUN_800529fc: equ 0x800529fc
/*
* Data
*/
Xa_no: equ 0x80010818
floc: equ 0x800988a4
Xa_sector00: equ 0x8009a37c
Serial_no: equ 0x8009a3e0
cdmode: equ 0x8009a414
xa_cdmode: equ 0x8009a415
xa_control_tbl: equ 0x8009a418
xacontrol_cdmode: equ 0x8009a428
cdread_cdmode: equ 0x8009a429
cdread_s_cdmode: equ 0x8009a42a
door_msg: equ 0x8009a42c
door_msg_ofs: equ 0x8009a468
D_LIGHTMATRIX: equ 0x8009a470
D_COLORMATRIX: equ 0x8009a490
Dtex_file: equ 0x8009a4b0
Dinfo: equ 0x8009a520
pDoor_proc_tbl: equ 0x8009a7b4
Aida_jh0_tbl: equ 0x8009a7c4
Aida_jh0_head: equ 0x8009a8e8
Aida_jh1_tbl: equ 0x8009a920
Aida_jh1_head: equ 0x8009a97c
Aida_jh2_tbl: equ 0x8009a9b4
Aida_jh2_head: equ 0x8009aa10
Aida_jh3_tbl: equ 0x8009aa48
Aida_jh3_head: equ 0x8009aa58
Aida_jh4_tbl: equ 0x8009aa90
Aida_jh4_head: equ 0x8009aad8
Aida_jh5_tbl: equ 0x8009ab10
Aida_jh5_head: equ 0x8009ab58
Kg_jh0_tbl: equ 0x8009ab90
Kg_jh0_head: equ 0x8009ac60
cdemd0_pos: equ 0x8009adf4
cdemd0_sum: equ 0x8009b754
cdemd1_pos: equ 0x8009b754 ;; relocated from 0x8009b880
cdemd1_sum: equ 0x8009c1e0
cdemd2_pos: equ 0x8009c30c
cdemd2_sum: equ 0x8009cc6c
cdemd3_pos: equ 0x8009cd98
cdemd3_sum: equ 0x8009d358
Emd_name: equ 0x8009d410
Emd_tim_name: equ 0x8009d444
Room_100: equ 0x8009d478
Room_102: equ 0x8009d498
Room_101: equ 0x8009d4a8
Room_202: equ 0x8009d4b8
Room_109: equ 0x8009d4c8
Room_10B: equ 0x8009d4d8
Room_110: equ 0x8009d4e8
Room_117: equ 0x8009d528
Room_700: equ 0x8009d598
Room_702: equ 0x8009d5b8
Room_703: equ 0x8009d5d8
Room_705: equ 0x8009d5f8
Em_stbl_st1: equ 0x8009d648
Em_stbl_st2: equ 0x8009d728
Em_stbl_st7: equ 0x8009d818
Room_Enemy_tbl: equ 0x8009d848
Esp_tblj: equ 0x8009d868
sin_tbl: equ 0x8009d9f4
quake_tbl1: equ 0x8009daf4
quake_tbl2: equ 0x8009db14
sinpuku: equ 0x8009db34
hacho: equ 0x8009db38
speed: equ 0x8009db3c
mode: equ 0x8009db40
GsIDMATRIX: equ 0x8009db44
LIGHTMATRIX: equ 0x8009db64
COLORMATRIX: equ 0x8009db84
Bgm_sw_timer: equ 0x8009dba2
No_death_timer: equ 0x8009dba3
Curtain: equ 0x8009dbac
Pause: equ 0x8009dbec
Scrl_h: equ 0x8009dc0c
Rect: equ 0x8009dc10
Rect_bg: equ 0x8009dc20
Bomb_tbl: equ 0x8009dc28
Mizu_size_tbl: equ 0x8009dca0
Mizu_tbl: equ 0x8009dcc0
Mizu_struct_tbl: equ 0x8009dcd0
Div_prim_coord: equ 0x8009ddcc
msg_space: equ 0x8009de34
namelist_tbl_data: equ 0x8009df3c
namelist_tbl_ofs: equ 0x8009e438
namelist_u_data: equ 0x8009e550
namelist_u_ofs: equ 0x8009ebac
mess_tbl_data: equ 0x8009ecc4
mess_tbl_ofs: equ 0x8009ef9c
mess_u_data: equ 0x8009efcc
mess_u_ofs: equ 0x8009f368
mess_sub_data: equ 0x8009f398
mess_sub_ofs: equ 0x800a0674
mess_etc_data: equ 0x800a075c
mess_etc_ofs: equ 0x800a1e7c
branch_data: equ 0x800a1f64
branch_ofs: equ 0x800a2040
ascii_tbl: equ 0x800a2094
Ld_task_tbl: equ 0x800a20b8
Movie_tbl: equ 0x800a216c
pMovie_proc_tbl: equ 0x800a23ac
pDoor_proc_tbl_ex: equ 0x800a242c
;;Subpl_walk: equ 0x800a2444
;;Subpl_back: equ 0x800a2484
;;Subpl_dir: equ 0x800a24c4
;;Subpl_ato: equ 0x800a2504
;;Subpl_run: equ 0x800a2544
;;Em4a_zobiparts_tbl: equ 0x800a2584
Up_add_tbl: equ 0x800a2594
Down_add_tbl: equ 0x800a25bc
Box_sub_tbl: equ 0x800a25e4
Up_add_Spl_tbl: equ 0x800a260c
Down_add_Spl_tbl: equ 0x800a264c
Key_type: equ 0x800a26a0 ;; Pad_set
Stp_bak: equ 0x800a2700
Key_wait: equ 0x800a2704
Init_work_tbl: equ 0x800a2708
pc_mes_data: equ 0x800a3dc8
pc_mes_ofs: equ 0x800a3e68
;;Kend: equ 0x800a3e7c ;; Computer200
;;Mend: equ 0x800a3e80 ;; Computer200
;;Key_type: equ 0x800a3e84 ;; Computer200
;;Kend: equ 0x800a3e88 ;; Computer613
;;Mend: equ 0x800a3e8c ;; Computer613
;;Key_type: equ 0x800a3e90 ;; Computer613
;;Subpl_walk: equ 0x800a3e94
;;Subpl_back: equ 0x800a3ed4
;;Subpl_dir: equ 0x800a3f14
;;Subpl_ato: equ 0x800a3f54
;;Subpl_run: equ 0x800a3f94
;;Em4a_zobiparts_tbl: equ 0x800a3fd4
Pld_no: equ 0x800a3fe4
Pl_neck_timer: equ 0x800a4004
Pld_name: equ 0x800a4008
Pl_routine: equ 0x800a4030
Pl_mv_pad: equ 0x800a4054
Pl_mv: equ 0x800a4084
Pl_kage_pos: equ 0x800a40b4
;;pl_water: equ 0x800a40c4 ;; commented out because armips has trouble with character casing and a variable at 0x80042AAC has similar name
Wat_vec00: equ 0x800a40d4
Pl_dm: equ 0x800a40e4
Pl_die_t: equ 0x800a40fc
Em10_damage_tbl: equ 0x800a412c
Em15_damage_tbl: equ 0x800a42a8
Em20_damage_tbl: equ 0x800a4424
Em21_damage_tbl: equ 0x800a45a0
Em22_damage_tbl: equ 0x800a471c
Em24_damage_tbl: equ 0x800a4898
Em23_damage_tbl: equ 0x800a4a14
Em25_damage_tbl: equ 0x800a4b90
Em27_damage_tbl: equ 0x800a4d0c
Em28_damage_tbl: equ 0x800a4e88
Em29_damage_tbl: equ 0x800a5004
Em2d_damage_tbl: equ 0x800a5180
Em2a_damage_tbl: equ 0x800a52fc
Em2b_damage_tbl: equ 0x800a5478
Em2e_damage_tbl: equ 0x800a55f4
Em30_damage_tbl: equ 0x800a5770
Em31_damage_tbl: equ 0x800a58ec
Em33_damage_tbl: equ 0x800a5a68
Em34_damage_tbl0: equ 0x800a5be4
Em34_damage_tbl1: equ 0x800a5d60
Em36_damage_tbl: equ 0x800a5edc
Em3a_damage_tbl: equ 0x800a6058
Em3b_damage_tbl: equ 0x800a61d4
PLW00_W: equ 0x800a6350
PLW00_S: equ 0x800a63a4
Pl_w011: equ 0x800a63a8
Pl_w01_s1: equ 0x800a6434
Pl_w0111: equ 0x800a6444
Pl_w0111_s1: equ 0x800a64d0
Pl_w010: equ 0x800a64e0
Pl_w01_s0: equ 0x800a656c
Pl_w012: equ 0x800a657c
Pl_w01_s2: equ 0x800a6608
PLW02_W: equ 0x800a6618
PLW02_S: equ 0x800a666c
PLW05_W: equ 0x800a6670
PLW05_S: equ 0x800a66c4
PLW13_W: equ 0x800a66c8
PLW13_S: equ 0x800a671c
PLW07_W: equ 0x800a6724
PLW07_S: equ 0x800a6778
PLW08_W: equ 0x800a6788
PLW08_S: equ 0x800a67dc
PLW0E_W: equ 0x800a67f0
PLW0E_S: equ 0x800a6844
PLW0F_W: equ 0x800a6848
PLW0F_S: equ 0x800a689c
PLW12_W: equ 0x800a68a4
PLW12_S: equ 0x800a68f8
Pl_weapon_tbl: equ 0x800a6900
pEnemy_damage_tbl: equ 0x800a6ac8
Pl_bow_hit_parts: equ 0x800a6b88
Plw_no: equ 0x800a6d08
Pl_weapon_init: equ 0x800a6d28
Pl_weapon_kyan: equ 0x800a6d78
W_at_ck: equ 0x800a6db4
Ghand_len: equ 0x800a6dd0
Mw_ck: equ 0x800a6e68
Pl_wep_mag_type: equ 0x800a6e78
Pl_mag: equ 0x800a6e90
G_rot_data_z: equ 0x800a6ea8
pl_mv05_w_tbl: equ 0x800a6f3c
Gun_jtg_bit: equ 0x800a6f8c
pl_mv05_t2_init: equ 0x800a6f94
pl_mv05_t2_spr: equ 0x800a6fe0
pl_mv05_w0_tbl: equ 0x800a702c
pl_mv05_w1_tbl: equ 0x800a7048
Bow_Room509: equ 0x800a7060
pl_mv05_w2_tbl: equ 0x800a7068
pl_mv05_w3_tbl: equ 0x800a7080
pl_mv05_w4_tbl: equ 0x800a7098
pl_mv05_w5_tbl: equ 0x800a70b0
Poly_test4: equ 0x800a70c8
ascii_tbl_2: equ 0x800a70e8
Rdt_tbl1: equ 0x800a70fc
Rdt_tbl2: equ 0x800a7138
Rdt_tbl3: equ 0x800a7170
Rdt_tbl4: equ 0x800a7190
Rdt_tbl5: equ 0x800a71b8
Rdt_tbl6: equ 0x800a71d0
Rdt_tbl7: equ 0x800a7200
Rdt_tbl: equ 0x800a7210
;;Subpl_walk: equ 0x800a722c
;;Subpl_back: equ 0x800a726c
;;Subpl_dir: equ 0x800a72ac
;;Subpl_ato: equ 0x800a72ec
;;Subpl_run: equ 0x800a732c
;;Em4a_zobiparts_tbl: equ 0x800a736c
Sca_rtn_tbl: equ 0x800a737c
Sca_no_ck_tbl: equ 0x800a73b4
Sce_at_jump_tbl: equ 0x800a73c4
em_se_tbl: equ 0x800a7400
Sce_jmp_tbl: equ 0x800a74c8
Em_kind_tbl: equ 0x800a7704
;;Subpl_walk: equ 0x800a7778
;;Subpl_back: equ 0x800a77b8
;;Subpl_dir: equ 0x800a77f8
;;Subpl_ato: equ 0x800a7838
;;Subpl_run: equ 0x800a7878
;;Em4a_zobiparts_tbl: equ 0x800a78b8
Flg_addr: equ 0x800a78c8
;;Subpl_walk: equ 0x800a7968
;;Subpl_back: equ 0x800a79a8
;;Subpl_dir: equ 0x800a79e8
;;Subpl_ato: equ 0x800a7a28
;;Subpl_run: equ 0x800a7a68
;;Em4a_zobiparts_tbl: equ 0x800a7aa8
Itp_check_sum: equ 0x800a7ab8
EnemSE_floc: equ 0x800a7b1c
LRVT: equ 0x800a7fb0
PANVT: equ 0x800a8030
nroom: equ 0x800a80b0
Core_edh: equ 0x800a80b8
Core_vbd: equ 0x800a80e8
Arms_edh: equ 0x800a8118
Arms_vbd: equ 0x800a8140
Main_bgm: equ 0x800a8168
Sub_bgm: equ 0x800a81e8
;;Subpl_walk: equ 0x800a8268
;;Subpl_back: equ 0x800a82a8
;;Subpl_dir: equ 0x800a82e8
;;Subpl_ato: equ 0x800a8328
;;Subpl_run: equ 0x800a8368
;;Em4a_zobiparts_tbl: equ 0x800a83a8
Spl_routine_0: equ 0x800a83b8
Spl_mv: equ 0x800a83dc
Spl_in: equ 0x800a844c
Spl_dm: equ 0x800a84bc
;;Spl_die: equ 0x800a84cc ;; commented out because armips has trouble with character casing and a variable at 0x8005E39C has similar name
;;Spl_dead: equ 0x800a84d0 ;; commented out because armips has trouble with character casing and a variable at 0x8005E3D8 has similar name
;;Subpl_walk: equ 0x800a84d4
;;Subpl_back: equ 0x800a8514
;;Subpl_dir: equ 0x800a8554
;;Subpl_ato: equ 0x800a8594
;;Subpl_run: equ 0x800a85d4
;;Em4a_zobiparts_tbl: equ 0x800a8614
Spl_r_pos: equ 0x800a8624
Aida_Move_type: equ 0x800a863c
Aida_St_pos: equ 0x800a8668
Spl_pos_ck_timer: equ 0x800a8673
Aida_mv_br_type00: equ 0x800a8674
Aida_mv_type00: equ 0x800a86ac
Aida_mv_br_type01: equ 0x800a86e4
Aida_mv_br_type02: equ 0x800a871c
Aida_mv_br_type03: equ 0x800a8754
Aida_mv_br_type04: equ 0x800a878c
Aida_mv_br_type05: equ 0x800a87c4
Aida_mv_br_type06: equ 0x800a87fc
Aida_mv_br_type07: equ 0x800a8834
Aida_mv_br_type08: equ 0x800a886c
Aida_mv_br_type09: equ 0x800a88a4
Aida_mv_br_type0a: equ 0x800a88dc
E_A_at_tbl: equ 0x800a8914
Aida_em_at00_pl: equ 0x800a8944
Aida_em_at00_spl: equ 0x800a8950
Aida_em_at01: equ 0x800a895c
Aida_mv05_w1_br_tbl: equ 0x800a8968
Aida_mv05_w1_tbl: equ 0x800a8980
Aida_em_at05: equ 0x800a8998
Sherry_Move_type: equ 0x800a89a0
Sherry_St_pos: equ 0x800a89cc
Sherry_mv_br_type00: equ 0x800a89d8
Sherry_mv_br_type01: equ 0x800a8a10
Sherry_mv_br_type02: equ 0x800a8a48
Sherry_mv_br_type03: equ 0x800a8a80
Sherry_mv_br_type04: equ 0x800a8ab8
Sherry_mv_br_type05: equ 0x800a8af0
Sherry_mv_br_type06: equ 0x800a8b28
Sherry_mv_br_type07: equ 0x800a8b60
Sherry_mv_br_type08: equ 0x800a8b98
Sherry_mv_br_type09: equ 0x800a8bd0
Sherry_mv_br_type0a: equ 0x800a8c08
;;Subpl_walk: equ 0x800a8c40
;;Subpl_back: equ 0x800a8c80
;;Subpl_dir: equ 0x800a8cc0
;;Subpl_ato: equ 0x800a8d00
;;Subpl_run: equ 0x800a8d40
;;Em4a_zobiparts_tbl: equ 0x800a8d80
Spl_sce: equ 0x800a8d90
;;Subpl_walk: equ 0x800a8e14
;;Subpl_back: equ 0x800a8e54
;;Subpl_dir: equ 0x800a8e94
;;Subpl_ato: equ 0x800a8ed4
;;Subpl_run: equ 0x800a8f14
;;Em4a_zobiparts_tbl: equ 0x800a8f54
Spl_sp: equ 0x800a8f62
init_item_tbl_Leon: equ 0x800a9264
init_item_tbl_Claire: equ 0x800a9285
init_item_tbl_Hunk: equ 0x800a92a6
init_item_tbl_ToFu: equ 0x800a92c7
init_item_tbl_Leon_Ex: equ 0x800a92e8
init_item_tbl_Claire_Ex: equ 0x800a9309
init_item_tbl_Ada_Ex: equ 0x800a932a
init_item_tbl_Chris_Ex: equ 0x800a934b
Status_proc_tbl: equ 0x800a936c
st_light: equ 0x800a93a8
init_item_tbl_Ada: equ 0x800a93d0
init_item_tbl_Sherry: equ 0x800a93f1
maps_floc: equ 0x800a9414
fits_floc: equ 0x800a94b4
Status_menu0_proc_tbl: equ 0x800a9aac
;;add: equ 0x800a9ac4 ;; St_menu0_file
File_offset: equ 0x800a9ad0
map_up_floor: equ 0x800a9aec
map_down_floor: equ 0x800a9b04
Map_char_tbl: equ 0x800a9b8c
Status_direct_map_proc_tbl0: equ 0x800a9b94
Status_direct_map_proc_tbl1: equ 0x800a9ba8
St_itembox_proc_tbl: equ 0x800a9bb4
Ibox_char_tbl: equ 0x800a9bc4
f4_tbl: equ 0x800a9c28
Ibox_pos_tbl: equ 0x800a9c38
St_getitem_proc_tbl: equ 0x800a9c9c
move_tbl: equ 0x800a9cb0
;;add: equ 0x800a9cdc ;; St_get_file
Mix_nodata: equ 0x800a9ce8
Mix_beretta: equ 0x800a9cec
Mix_magnam: equ 0x800a9cf4
Mix_shotgun: equ 0x800a9cfc
Mix_machinegun: equ 0x800a9d04
Mix_fire: equ 0x800a9d08
Mix_bowgun: equ 0x800a9d0c
Mix_g_n: equ 0x800a9d10
Mix_g_f: equ 0x800a9d1c
Mix_g_a: equ 0x800a9d28
Mix_spark: equ 0x800a9d34
Mix_bullet: equ 0x800a9d38
Mix_dot380: equ 0x800a9d50
Mix_shot_dan: equ 0x800a9d58
Mix_arrow: equ 0x800a9d64
Mix_mag_dan: equ 0x800a9d6c
Mix_nen: equ 0x800a9d78
Mix_battley: equ 0x800a9d80
Mix_g_normal: equ 0x800a9d88
Mix_g_fire: equ 0x800a9d98
Mix_g_acid: equ 0x800a9da8
Mix_ink_ribbon: equ 0x800a9db8
Mix_parts_a: equ 0x800a9dbc
Mix_parts_b: equ 0x800a9dc0
Mix_parts_c: equ 0x800a9dc4
Mix_g: equ 0x800a9dd0
Mix_r: equ 0x800a9de4
Mix_b: equ 0x800a9dec
Mix_gr: equ 0x800a9df8
Mix_gg: equ 0x800a9dfc
Mix_gb: equ 0x800a9e04
Mix_p_bomb: equ 0x800a9e0c
Mix_fuse: equ 0x800a9e10
Mix_Jaguar_a: equ 0x800a9e14
Mix_Jaguar_b: equ 0x800a9e18
Item_data_tbl: equ 0x800a9e1c
File_data: equ 0x800aa144
Map_stage1_0: equ 0x800aa1a8
Map_stage1_1: equ 0x800aa228
Map_stage1_2: equ 0x800aa268
Map_stage1_3: equ 0x800aa358
Map_stage2_0: equ 0x800aa388
Map_stage2_1: equ 0x800aa4a8
Map_stage3_0: equ 0x800aa558
Map_stage4_0: equ 0x800aa608
Map_stage4_1: equ 0x800aa668
Map_stage5_0: equ 0x800aa738
Map_stage5_1: equ 0x800aa778
Map_stage5_2: equ 0x800aa7a8
Map_stage5_3: equ 0x800aa7d8
Map_stage6_0: equ 0x800aa7f8
Map_stage6_1: equ 0x800aa858
Map_stage6_2: equ 0x800aa868
Map_stage6_3: equ 0x800aa878
Map_stage6_4: equ 0x800aa948
Map_stage6_5: equ 0x800aa988
Map_stage7_0: equ 0x800aa9b8
Map_stage7_1: equ 0x800aaa18
Map_info: equ 0x800aaa38
Ecg_normal_tbl: equ 0x800aaad8
Ecg_caution0_tbl: equ 0x800aab78
Ecg_caution1_tbl: equ 0x800aac18
Ecg_danger_tbl: equ 0x800aacb8
Ecg_poison_tbl: equ 0x800aad58
N_pos: equ 0x800aadf8
Cursol0_char_tbl: equ 0x800aae40
Cursol0_pos_tbl: equ 0x800aae4c
Cursol1_char_tbl: equ 0x800aae70
Cursol1_pos_tbl: equ 0x800aae7c
Face_char_tbl: equ 0x800aaea0
Face_subchar_tbl: equ 0x800aaed4
Face_pos_tbl: equ 0x800aaefc
Face_subpos_tbl: equ 0x800aaf30
Message_char_tbl: equ 0x800aaf58
Message_pos_tbl: equ 0x800aaf9c
Frame_char_tbl: equ 0x800aafe0
Frame_pos_tbl: equ 0x800ab024
Menu0_char_tbl: equ 0x800ab068
Menu0_pos_tbl: equ 0x800ab088
Menu1_char_tbl: equ 0x800ab0a8
Menu1_pos_tbl: equ 0x800ab0cc
Itemlist_char_tbl: equ 0x800ab0f0
Itemlist_pos_tbl: equ 0x800ab10c
Equip_char_tbl: equ 0x800ab128
Equip_pos_tbl: equ 0x800ab144
Ecg_col_tbl: equ 0x800ab160
Ecg_line_tbl: equ 0x800ab180
ECG_char_tbl: equ 0x800ab194
Itemget_char: equ 0x800ab19c
Itemget_pos_tbl: equ 0x800ab1bc
v_p: equ 0x800ab1dc
v_r: equ 0x800ab1e8
pp: equ 0x800ab1f4
pMem_man: equ 0x800ab204
;;Svec: equ 0x800ab208 ;; Rot_vector
;;Svec: equ 0x800ab210 ;; Rot_vector_super
Poly_ft4_count: equ 0x800ab218
_spu_RXX: equ 0x800ab21c
_spu_tsa: equ 0x800ab234
_spu_transMode: equ 0x800ab238
_spu_mem_mode_plus: equ 0x800ab244
_spu_mem_mode_unitM: equ 0x800ab24c
_spu_inTransfer: equ 0x800ab250
_spu_transferCallback: equ 0x800ab254
_spu_IRQCallback: equ 0x800ab258
_spu_EVdma: equ 0x800ab280
_spu_keystat: equ 0x800ab284
_spu_trans_mode: equ 0x800ab288
_spu_rev_flag: equ 0x800ab28c
_spu_rev_reserve_wa: equ 0x800ab290
_spu_rev_offsetaddr: equ 0x800ab294
_spu_rev_attr: equ 0x800ab29c
_spu_RQvoice: equ 0x800ab2ac
_spu_RQmask: equ 0x800ab2b0
_spu_zerobuf: equ 0x800ab2e4
_spu_env: equ 0x800ab6e4
_spu_isCalled: equ 0x800ab6e8
_spu_AllocBlockNum: equ 0x800ab6ec
_spu_AllocLastNum: equ 0x800ab6f0
_spu_memList: equ 0x800ab6f4
_spu_rev_startaddr: equ 0x800ab6f8
_snd_seq_tick_env: equ 0x800aba28
;;rsin_tbl: equ 0x800abb48 ;; rcos
_stacksize: equ 0x800abbcc
;;rsin_tbl: equ 0x800ac348 ;; sin_1
;;rsin_tbl: equ 0x800acb48 ;; rcos
Vcount: equ 0x800acd00
GsCLIP3near: equ 0x800acd30
GsCLIP3far: equ 0x800acd30
GsOUT_PACKET_P: equ 0x800acd30
CD_cbsync: equ 0x800acdec
CD_cbready: equ 0x800acdf0
CD_debug: equ 0x800acdf8
CD_status: equ 0x800acdfc
CD_pos: equ 0x800ace08
CD_mode: equ 0x800ace0c
CD_com: equ 0x800ace0d
DS_active: equ 0x800ace10
CD_comstr: equ 0x800ace14
CD_intstr: equ 0x800ace94
CDROM_DELAY: equ 0x800ad0e8
CDROM_REG0: equ 0x800ad14c
CDROM_REG1: equ 0x800ad150
CDROM_REG2: equ 0x800ad154
CDROM_REG3: equ 0x800ad158
;;CDROM_DELAY: equ 0x800ad15c
COMMON_DELAY: equ 0x800ad160
DMA_DPCR: equ 0x800ad164
DMA_DICR: equ 0x800ad168
DMA_MDEC_OUT_CHCR: equ 0x800ad16c
DMA_CDROM_CHCR: equ 0x800ad17c
;;rsin_tbl: equ 0x800ad348 ;; rcos, sin_1
SQRT: equ 0x800adb8c
rcossin_tbl: equ 0x800adeac
ratan_tbl: equ 0x800b1eac
GPU_printf: equ 0x800b26fc
DecDctEnv: equ 0x800b2824
DCL_DVLC: equ 0x800b296c
DCC_DVLC: equ 0x800b2d6c
CF_DVLC: equ 0x800b316c
CF2_DVLC: equ 0x800c316c
_padFuncNextPort: equ 0x800c399c
_padFuncClrInfo: equ 0x800c39a0
_padFuncGetTxd: equ 0x800c39a4
_padFuncCurrLimit: equ 0x800c39a8
_padFuncPtr2Port: equ 0x800c39ac
_padFuncPort2Info: equ 0x800c39b0
_padFuncSendAuto: equ 0x800c39b4
_padFuncChkEng: equ 0x800c39b8
_padFuncRecvAuto: equ 0x800c39bc
_padFuncClrCmdNo: equ 0x800c39c0
_padInfoDir: equ 0x800c39d0
_padIntExec: equ 0x800c39d4
_padSioChan: equ 0x800c39dc
_padSioState: equ 0x800c39e0
_padTotalCurr: equ 0x800c39e4
_padModeMtap: equ 0x800c39e8
_padChanStart: equ 0x800c39ec
_padChanStop: equ 0x800c39f0
_padFixResult: equ 0x800c39f4
_padCalledIntPad: equ 0x800c3a04
;;__sbss_obj: equ 0x800c3a48
pDoor: equ 0x800c3a80
Stop_bak: equ 0x800c3a88
V: equ 0x800c3a8c
Kpos: equ 0x800c3a9c
Kofs: equ 0x800c3ab0
pPc: equ 0x800c3ab8
;;Hit_flg: equ 0x800c3b68 ;; Sca_ck_hit
pSca_data: equ 0x800c3b6c
Old_x: equ 0x800c3b70
Old_z: equ 0x800c3b74
;;Hit_flg: equ 0x800c3b78 ;; Sca_ck_hit_om
Gnd_y: equ 0x800c3b7c
In_flg: equ 0x800c3b80
Tmp_Sca: equ 0x800c3b84
Key_work: equ 0x800c3b98
Dir_spd: equ 0x800c3b9c
Spd_add: equ 0x800c3ba0
pOwork: equ 0x800c3ba4
Key_work_0: equ 0x800c3ba8
pItem_dat: equ 0x800c3bac
pAot: equ 0x800c3bb0
EM40_Prim: equ 0x800c3bb8
shot: equ 0x800c3bd0
num: equ 0x800c3bd8
Tmp_matrix: equ 0x800c3be0
;;Svec: equ 0x800c3c20 ;; Set_front_pos
pStack_bak: equ 0x800c3c28
_padVsyncParam: equ 0x800c40a8
_padRestPeriod: equ 0x800c40b8
;;_padIntExec: equ 0x800c40bc ;; copy of _padIntExec
Poly2_work: equ 0x800c4348
add_y: equ 0x800c4408
Reverb_flg: equ 0x800c4410
Trans: equ 0x800c4418
PadActData: equ 0x800cbc20
Stframe_no: equ 0x800cbc24
Sedir2: equ 0x800cbc30
SsFCALL: equ 0x800cbc38
m_pl_weapon_tmd: equ 0x800cc1e0
G: equ 0x800cc1e8
Vab_id: equ 0x800d4c48
_svm_rattr: equ 0x800d4c50
Stsector_offset: equ 0x800d4c64
StRgb24: equ 0x800d4c68
StMode: equ 0x800d4c6c
Em_dir: equ 0x800d4c70
;;Cd_vol: equ 0x800d4c78 ;; commented out because armips has trouble with character casing and a variable at 0x8008831C has similar name
Se_pri: equ 0x800d4ca0
Move_x: equ 0x800d4cd0
pEspdt: equ 0x800d4cd8
pDwork: equ 0x800d4dd8
bk_cut: equ 0x800d4e00
pEspmv: equ 0x800d4e18
sel_no: equ 0x800d4f18
Entory: equ 0x800d4f20
StFunc1: equ 0x800d5218
StFunc2: equ 0x800d521c
_svm_vab_pg: equ 0x800d5228
StCdIntrFlag: equ 0x800d5268
;;_svm_vab_pg: equ 0x800d5268
_svm_vab_vh: equ 0x800d5270
_svm_damper: equ 0x800d52b0
;;_svm_vab_vh: equ 0x800d52b0
_svm_vab_tn: equ 0x800d52b8
;;_svm_vab_tn: equ 0x800d52f8
CD: equ 0x800d5300
Channel: equ 0x800d5b80
_spu_RQ: equ 0x800d5b88
Mem_man: equ 0x800d5ba0
m_pl_w00_tmd2: equ 0x800d5be0
Ceiling: equ 0x800d5be4
pSce_em: equ 0x800d5be8
St: equ 0x800d5bf0
StCHANNEL: equ 0x800d6c38
StStartFrame: equ 0x800d6c3c
_svm_stereo_mono: equ 0x800d6c40
Cc_work: equ 0x800d6c48
Pan_vol: equ 0x800d7598
pVh_tbl: equ 0x800d75a0
Seq_ctr: equ 0x800d75c0
Vm_disp: equ 0x800d75d8
Om_fall_old_dir_x: equ 0x800d7638
pVm_frm: equ 0x800d763c
Om_fall_old_dir_z: equ 0x800d7642
pSpl_near_em: equ 0x800d7648
UnknownPadInfoByte: equ 0x800d7654
_snd_ev_flag: equ 0x800d7658
Rev_vol: equ 0x800d765c
gpPl_pac_ptr: equ 0x800d7660
kMaxPrograms: equ 0x800d7664
CdReadSoundCnt: equ 0x800d7668
;;sw: equ 0x800d766c ;; commented out because this causes problems with armips
Vm_work: equ 0x800d7670
pStairs: equ 0x800d7694
Ev0: equ 0x800d7698
Monitor: equ 0x800d76a0
Ev1: equ 0x800d7828
Ev2: equ 0x800d782c
Ev3: equ 0x800d7830
xx: equ 0x800d7834
_svm_pg: equ 0x800d7838
UnkSndSysInitSubFlg: equ 0x800d783c
yy: equ 0x800d783e
gpPl_tmd_ptr: equ 0x800d7840
_svm_vg: equ 0x800d7844
_svm_vh: equ 0x800d7848
_svm_tn: equ 0x800d784c
CChannel: equ 0x800d7850
_SsVmMaxVoice: equ 0x800d7854
Bgm: equ 0x800d7856
gpPl_pac2_ptr: equ 0x800d7858
UnkMvPadFlg: equ 0x800d785c
Sce: equ 0x800d7860
Ev10: equ 0x800d8cd4
Loc: equ 0x800d8cd8
Ev11: equ 0x800d8cdc
Ev13: equ 0x800d8ce0
RevD_vol: equ 0x800d8ce4
m_pl_weapon_parts: equ 0x800d8ce8
gpPl_tmd2_ptr: equ 0x800d8cec
Esp: equ 0x800d8cf0
pEdt_adr: equ 0x800dbb70
UnkSndFlg0: equ 0x800dbb88
UnkSndSysFlg0: equ 0x800dbb8c
StFinalSector: equ 0x800dbb90
Poly_eff: equ 0x800dbb98
Om_fall_dir_x: equ 0x800dcb98
Main_vol: equ 0x800dcb9c
Om_fall_dir_y: equ 0x800dcba0
Om_fall_dir_z: equ 0x800dcba2
f_x: equ 0x800dcba4
f_y: equ 0x800dcba6
GsWSMATRIX: equ 0x800dcba8
Ground_in_flg: equ 0x800dcbc8
bk_light: equ 0x800dcbcc
pESP: equ 0x800dcbd0
_snd_openflag: equ 0x800dcbd4
_autopan: equ 0x800dcbd8
Ex_battle_rcut: equ 0x800dcbe0
_svm_cur: equ 0x800dcc31
Ex_battle_vcut: equ 0x800dcc50
_svm_vab_used: equ 0x800dcc68
Poly_eff2: equ 0x800dce30
_autovol: equ 0x800df330
m_pl_weapon_packet: equ 0x800df334
pMovie_result: equ 0x800df338
StEmu_Idx: equ 0x800df33c
Fade_mode: equ 0x800df340
Game: equ 0x800df348
Demo: equ 0x800df390
Key_idx_bak: equ 0x800dfad6
UnknownSetRoomByte: equ 0x800dfad7
Em_l: equ 0x800dfad8
_svm_auto_kof_mode: equ 0x800dfade
Main: equ 0x800dfae0
pBgm: equ 0x800dfd64
Line: equ 0x800dfd68
UnknownPadSetFlag: equ 0x800e2a80
Ret_Value: equ 0x800e2a88
GsMWSMATRIX: equ 0x800e2a90
Moji: equ 0x800e2ab0
Moji_buff: equ 0x800e8438
_svm_envx_ptr: equ 0x800e8764
Volume_Se: equ 0x800e8768
Seq_table: equ 0x800e8770
pAtv: equ 0x800e8980
_que: equ 0x800e8998
Ceiling_in_pos: equ 0x800ea198
VBLANK_MINUS: equ 0x800ea228
StRingIdx1: equ 0x800ea22c
StRingIdx2: equ 0x800ea230
StRingIdx3: equ 0x800ea234
pCom_work: equ 0x800ea23c
pPsp_prim: equ 0x800ea240
m_pl_w00_packet: equ 0x800ea248
_ss_score: equ 0x800ea250
_SsMarkCallback: equ 0x800ea2d0
pPsp_work: equ 0x800eaad0
_snd_seq_s_max: equ 0x800ead72
StEmu_Addr: equ 0x800ead74
_snd_seq_t_max: equ 0x800ead78
StEndFrame: equ 0x800ead7c
StSTART_FLAG: equ 0x800ead90
pCAot: equ 0x800ead94
StRingBase: equ 0x800ead98
StRingAddr: equ 0x800ead9c
_svm_vab_total: equ 0x800eada0
Old_Fatari: equ 0x800eade0
MainVbSize: equ 0x800eade4
_svm_vab_count: equ 0x800eade8
_svm_vab_start: equ 0x800eadf0
Old_Uatari: equ 0x800eae30
pFile: equ 0x800eae34
m_pl_w00_packet2: equ 0x800eae38
Volume_Bgm: equ 0x800eae3c
RoomVbSize: equ 0x800eae40
Espid: equ 0x800eae48
_svm_envx_hist: equ 0x800eae5c
Sedir: equ 0x800eae98
StRingSize: equ 0x800eae9c
_svm_okof1: equ 0x800eaea0
_svm_okof2: equ 0x800eaea2
|
MeganGrass/Resident-Evil-2-Starter-Kit | 114,386 | source/assembly/bio2.s |
opt c+
OVERLAY group
section OVERLAY.data
;; CUSTOM
global BuildDate
global CdxLbaBin
global CdxLbaBss
global CdxLbaDat
global CdxLbaDo2
global CdxLbaEmd0
global CdxLbaEmd1
global CdxLbaPld
global CdxLbaPlw
global CdxLbaSndArms
global CdxLbaSndCore
global CdxLbaSndEmd
global CdxLbaSndMain
global CdxLbaSndSub
global CdxLbaRdt
global CdxLbaXa
global CdxLbaStr
global SysDisk
global SysLanguage
global SysScenario
global SysController
global SysAutoAim
global BootWeapon
global DebugValue
global DebugFlag
global CdReadMode
global ItoxBuffer
global CdReadEx
global LoadPlwTable
global SetDisk
;; ASSEMBLY
global desld_set
global desld
global memcpy16
global setexmask
;; CD.C
global Cd_init
global Cd_system_control
global Xa_play
global Xa_control
global Xa_control_stop
global Xa_control_init
global Xa_control_play
global Xa_seek
global Xa_control_end
global Cd_read
global Cd_read_s
global Cd_seek
global Cd_cdsync_cb
global Cd_ready_cb
global Cd_set_stereo
global Set_volume
global Change_volume
;; DOOR.C
global Door_main
global Door_init
global Door_move
global Door_scheduler_main
global Door_exit
global Door_Trans
global DoorSort
global Door_model_init
global Door_model_set
global Door_snd_trans
global Door_texture_load
;; EM_SUB.C
global Hani_ck
global Add_speedXZ
global Add_speedXYZ
global Add_speedXYZsuper
global Direction_ck
global Goto00
global Goto00_ck
global Goto01
global Goto01_ck
global Dir_pos_ck
global L_pos_ckXZ
global L_pos_ckXZM
global Cdir_ck
global Cdir_ck2
global Gacha_ch
global Sikai_ck
global Set_base_pos
global Null_pos_set
global get_null_pos
global Spd_get
global Rnd
global Em_seq_sound
global move_kuchi
global Tex_Ani_move
global Foot_set_pl
global Kage_work_init
global Kage_work9_init
global Kage_work_set
global Kage_work9_set
global MulKage
global Kage_work_sort
global Kage_work9_sort
global Kage_work_color_set
global Kage_work9_color_set
global Texture_Move
global Texture_Move_GT3
global Texture_Move_GT4
global Texture_Move_GT4_up
global Rot_neck
global Rot_neck_em
global Rot_neck_em_n
global Neck_Dir_ZY
global Op_PartsSort00
global Op_PartsSort05
global Op_PartsSort06
global Kami_rot05
global W_rot
global W_rot_x
global Rbj_set
global Em_dead_flg_on
global Aida_Jh_init
global Aida_Jh_move
global Kg_Jh_init
global Kg_Jh_move
global Jh_set
global MulJh
global Aida_Jh_sort
global Jh_sort
;; EM_SUB2.C
global Approach
global Approach_one
global Mot_play
global Mot_play2
global Mot_play_init
global Mot_play_sp
global Mot_play2_sp
global Mot_play2_spxz
global Em_init_super
global Branch
global Ck_em_id
global Goto00_super
global Goto01_super
global Get_parts_world_dir
;; EM_SET.C
global Enemy_work_set
global Em_set
global Emd_load
global Set_enemy_work
global Kill_enemy_work
global Em_move_tbl_set
global Em_bin_load
global Emd_load_file
;; ESP
global Esp_init_C
global Esp_init_R
global Esp_data_set0
global Esp_data_set1
global Esp_call
global Esp_call3D
global Esp_call3D2
global Esp_call2
global Esp_call3
global Esp_kill
global Esp_kill2
global Esp_die
global Esp_ctrl
global Esp_ctrl2
global Esp_ctrl3
global Esp_ctrl4
global Esp_move
global Esp_pos
;; GAME.C
global Game_loop
global Set_door
global Gun_light_set
global Gun_light_reset
;; JOINT.C
global Joint_trans2
global ko_joint_trans2
global SortGT3_neo
global SortGT4_neo
global ko_joint_trans3
global PartsWork_set
global PartsWork_link
global Init_Parts_work
global Mem_ck_Parts_work
global Joint_pos_trans
global Parts_down
global Parts_bomb
global Parts_ryu
global HMatrix
global HMatrix1
global Model_color_plus
global Joint_move
global J_seq
global J_seq_hokan
global rot_data_set02
global rot_data_set03
global hokan_svec
global Pl_set_packet2
global Pl_set_packet
global Joint_move_p
global Joint_move2
global J_seq2
;; LINE_SCR.C
global Scr_effect
global Scr_quake
global Scr_rasta
global line_trans
global line_scr_end
global line_mode_set
global Line_work_init
;; MAIN.C
global main
global Init_system
global InitGeom_func
global Init_main
global Swap_Cbuff
global Bg_set_mode
global Bg_draw
global Fade_set
global Fade_start
global Fade_adjust
global Fade_off
global Fade_status
global System_trans
global Init_global
global Cut_check
global Cut_change
global Ccut_serach
global Hit_ck_point4
global Hit_ck_box
global Card_event_set
global Logo
;; MD_SUB.C
global PresetObjectGT3_neo
global PresetObjectGT4_neo
global CompM
global mapModelingData
global MulLMatrix
global SortGT3_lno
global SortGT4_lno
global Bomb_Parts_SortGT3
global Bomb_Parts_SortGT4
global Ryu_Parts_SortGT3
global Ryu_Parts_SortGT4
global mirror_TMD_GT3
global mirror_PACKET_GT3
global mirror_TMD_GT4
global mirror_PACKET_GT4
global Mirror_model_cp
global Init_mirror_weapon
global Mirror_weapon_cp
global Parts_work_cp
global Mirror_view
global Mirror_in_view
global Mirror_trans
global Mirror_matrix_set
global Late_set
;; MEM_CARD.C
global Mem_card
global Card_access
global Cardaccess_init
global Cardaccess_exit
global MC_Mess_disp
global Cursor_disp
global Search_f_num
global Check_card
global Wslot_check
global Card_mess_make
global Save_push
global Load_pop
global Clear_event
global Clear_event2
global Card_write
global Card_read
global Card_search
global Card_check
global Card_format_check
global Card_format
global Get_card_event
global Get_card_event2
global Card_clear
;; MIZU_SYS.C
global Mizu_trans
global Mizu_div_ck
global Mizu_div_main
;; MOJIDISP.C
global Print8
global Print14
global Print_main
global Mess_set
global Moji_trans_main
global Mess_disp
global Branch_disp
global name_ptr_set
global mess_trans
global Name_disp
global Mess_print
global moji_trans_main
global moji_trans_8
global moji_trans_14
global Moji_buff_init
global Moji_init
global Moji_mode_init
;; MONITOR.C
global Init_scheduler
global Scheduler
global Task_lexecute
global Task_lchain
global Task_execute
global Task_sleep
global Task_exit
global Task_kill
global Task_chain
global Task_suspend
global Task_signal
global Task_status
;; MOVIE.C
global Init_movie_work
global Movie
global Movie_init
global Movie_main
global Movie_end
global Movie_exit
global Open_movie
global Play_movie
global Close_movie
global RuntoImage
global Mdec_callback
global Movie_cinesco_init
global Movie_cinesco_set
global Fwd_movie
global Movie_xa_start
global Movie_xa_stop
global Set_movie_volume2
global CdReset2
global Caption_set
global Caption_print
global Decomp_caption
;; OBA.C
global Oba_ck_hit
global Oba_ck_only
global Oba_set_ofs
global Oba_ck_em
global Oba_ck_em2
global Sca_ck_em
;; OM.C
global Om_init
global Col_chg_init
global Tex_chg_init
global Tex_ctr
global Col_chg
global Tex_chg
global Om_move
global Om_trans
global Om_move_box
global Om_set_fall_dir
global Ob_test_load2
global Oma_set_ofs
global Om_explosion_set
;; OMA.C
global Oma_ck_oba
global Oma_ck_om
global Oma_ck_front
global Oma_pl_updown_ck
global Oma_Spl_updown_ck
global Oma_front_ck
global Oma_on_check
global Oma_pull
global Oma_pull_hosei_x
global Oma_pull_hosei_z
global Oma_get_on_om
global Oma_ob_pull2
global Omd_in_check
global Oma_obj_ck_all
global Oma_hit_ck_all
global Om_Jump_ck
;; PAD.C
global Pad_set
global Pad_rep_set
global FUN_8003947c
global FUN_80039514
global FUN_800395b8
global FUN_80039694
global Init_demo_moji
global Set_moji_work
global Free_demo_moji
;; PC_SYS.C
global Windows
global Keyboard_Input
global Keyboard_set
global Keyboard
global Wframe_in_out
global Wframe_set
global Wframe_move
global Get_moji_code
global Cprint
global Console_put
global Console_roll_up
global Console_clr
global Console_trans
global Sprite_Trans
global Set_sp_work
global Dr_mode_set
;; PC_EVENT.C
global Computer200
global Computer613
global Computer_init
global Computer_exit
;; PLAYER.C
global Player_set
global Pl_before
global Pl_after
global Player_move
global Pl_init
global Pl_move
global pl_mv00_pad
global pl_mv00
global pl_mv01_pad
global pl_mv01
global pl_mv02_pad
global pl_mv02
global pl_mv03_pad
global pl_mv03
global Lim_dir_ck
global Pl_neck
global pl_mv04_pad
global pl_mv04
global pl_mv06_pad
global pl_mv06
global pl_mv07_pad
global pl_mv07
global pl_mv08_pad
global pl_mv08
global pl_mv09_pad
global pl_mv09
global pl_mv0a_pad
global pl_mv0a
global pl_mv0b_pad
global pl_mv0b
global Pl_damage
global pl_dm00
global pl_dm01
global pl_dm02
global pl_dm03
global Pl_die
global pl_die00
global Pl_Em_damage
global Pl_Em_die
global Pl_dead
global Pl_life_down
global Pl_life_up
;; PL_WEP.C
global Pl_weapon_ch
global Non_init
global Plw02_init
global Plw09_init
global Plw0c_init
global Plw0f_init
global Plw12_init
global Weapon_cls
global Init_W_Tool
global W_Tool
global init_Weapon_at
global Weapon_at_ck
global Set_MinMax
global Attack_r_ck0
global Attack_r_ck1
global Em_ck
global Hand_ck
global Mag_set
global Mag_down
global G_rot_st
global G_rot
global Gat_lp_st
global Gat_rot
global Pl_water
global pl_mv05_pad
global pl_mv05_w0
global pl_mv05_w0_t2
global pl_mv05_w0_t6
global pl_mv05_w1
global pl_mv05_w1_t0
global pl_mv05_w1_t1
global pl_mv05_w1_t2
global pl_mv05
global pl_w01_t2_init
global pl_w02_t2_init
global pl_w03_t2_init
global pl_w04_t2_init
global pl_w05_t2_init
global pl_w06_t2_init
global pl_w07_t2_init
global pl_w08_t2_init
global pl_w09_t2_init
global pl_w0a_t2_init
global pl_w0b_t2_init
global pl_w0c_t2_init
global pl_w0d_t2_init
global pl_w0e_t2_init
global pl_w0f_t2_init
global pl_w10_t2_init
global pl_w11_t2_init
global pl_w12_t2_init
global pl_w01_t2_move
global pl_w02_t2_move
global pl_w03_t2_move
global pl_w04_t2_move
global pl_w05_t2_move
global pl_w06_t2_move
global pl_w07_t2_move
global pl_w08_t2_move
global pl_w09_t2_move
global pl_w0a_t2_move
global pl_w0b_t2_move
global pl_w0c_t2_move
global pl_w0d_t2_move
global pl_w0e_t2_move
global pl_w0f_t2_move
global pl_w10_t2_move
global pl_w11_t2_move
global pl_w12_t2_move
global pl_mv05_w1_t3
global pl_mv05_w1_t4
global pl_mv05_w1_t5
global pl_mv05_sub
global pl_bow_init
global pl_bow_clr
global Bow_Lim_dir_ck
global pl_bow
global Goto_pro
global Bow_3D
global Rot_3D
global Pos_em_at_ck
global Pos_pl_at_ck
global Bow_goto_parts_no
global pl_mv05_w2
global pl_mv05_w2_t1
global pl_mv05_w2_t2
global pl_mv05_w2_t4
global pl_mv05_w3
global pl_mv05_w3_t2
global pl_mv05_w4
global pl_mv05_w4_t2
global pl_mv05_w5
global pl_mv05_w5_t2
;; POLY_SUB.C
global Poly_eff2_init
global Move_poly_eff2
global Sort_poly_eff2
global Poly_eff_init
global Set_poly_eff
global Sort_poly_eff
;; PSP.C
global Psp_init0
global Psp_init1
global Psp_set
global Psp_trans
global Psp_ctr
;; ROOM.C
global Set_room
global Set_stage
global Replace_rdt
global Em_init_move
;; ROOT_CK.C
global Root_ck
global Rnd_area
global Guide_check
global kara_rootck2
;; SABUN.C
global Sa_dat_set
global Sa_parts_mod
global Sa_parts_allmv2
global Sa_parts_allmv
global Sa_parts_offset_allmv
;; SCA.C
global Sca_get_area
global Sca_ck_hit
global Sca_ck_hit_om
global Sca_hit_box2
global Sca_hit_box
global Sca_hosei_box
global Sca_hit_naname_a
global Sca_ck_naname_a
global Sca_hit_naname_b
global Sca_ck_naname_b
global Sca_hit_naname_c
global Sca_ck_naname_c
global Sca_hit_naname_d
global Sca_ck_naname_d
global Sca_hit_hishi
global Sca_ck_hishi
global Sca_hit_circle
global Sca_ck_circle
global Sca_hit_koban_x
global Sca_ck_koban_x
global Sca_hit_koban_z
global Sca_ck_koban_z
global Sca_hit_slope
global Sca_hit_stairs
global Sca_hit_curve
global Sca_get_slope_high
global Sca_get_stairs_high
global Sca_get_curve_high
global Sca_get_ground
global Sca_get_dir
global Sca_get_dir_super
global Sca_get_dir_super_tmp
global Get_axis
global Get_axis2
global Sca_get_pos
global Sca_get_pos_super
global Sca_get_pos_super_tmp
global Sca_ck_line
global Sca_get_high
global Sca_get_low
global Sca_search
;; SCE_AT.C
global Sce_at_check
global Nothing
global Sce_Door
global Key_lost
global Sce_Item
global Sce_Normal
global Sce_Message
global Sce_Event
global Sce_Flg_chg
global Sce_Water
global Sce_Move
global Sce_Save
global Save_entrance
global Sce_Itembox
global Item_box_entrance
global Sce_Damage
global Sce_Status
global Sce_Hikidashi
global Hikidashi_entrance
global Sce_Windows
global Sce_at
global Water_ck
global Floor_check
;; SCE0.C
global Sce_test_init
global FUN_800529fc
global Em_kind_search
global Sce_se_set
global Sce_rnd_set
global Sce_model_init
global Sce_work_clr
global Sce_work_clr_at
global Sce_work_clr_set
global Sce_aot_init
global Event_init
global Event_exec
global Sce_col_chg_init
global Sce_mirror_init
global Sce_kirakira_set
global Sce_scheduler_set
global Sce_scheduler
global Sce_scheduler_main
;; SCE1.C
global Break_point
global Nop
global Evt_end
global Evt_next
global Evt_chain
global Evt_exec
global Evt_kill
global Ifel_ck
global Else_ck
global Endif
global Sleep
global Sleeping
global Wsleep
global Wsleeping
global For
global For2
global Next
global While
global Ewhile
global Do
global Edwhile
global While_main
global Switch
global Case
global Default
global Eswitch
global Goto
global Gosub
global Return
global Break
global Work_copy
global Rbj_reset
global Ck
global Set
global Cmp
global Save
global Copy
global Calc
global Calc2
global Calc_branch
global Sce_rnd
global Cut_chg
global Cut_old
global Cut_chg_main
global Cut_auto
global Cut_replace
global Cut_be_set
global Message_on
global Aot_set
global Aot_set_4p
global Door_aot_set
global Door_aot_set_4p
global Item_aot_set
global Item_aot_set_4p
global Aot_reset
global Aot_on
global Obj_model_set
global Super_set
global Super_on
global Super_reset
global Work_set
global Parts_set
global Speed_set
global Add_speed
global Add_aspeed
global Pos_set
global Dir_set
global Member_set
global Member_set2
global Member_set_branch
global Member_copy
global Member_cmp
global Load_member_branch
global Member_calc
global Member_calc2
global Load_member_addr_branch
global Dir_ck
;; SCE2.C
global Se_on
global Sca_id_set
global Sce_espr_on
global Sce_espr_on2
global Sce_espr3d_on
global Sce_espr3d_on2
global Sce_espr_kill
global Sce_espr_kill2
global Sce_espr_control
global Get_matrix
global Plc_motion
global Plc_dest
global Plc_gun
global Plc_gun_eff
global Plc_neck
global Plc_ret
global Plc_stop
global Plc_flg
global Plc_rot
global Plc_cnt
global Sce_em_set
global Sce_key_ck
global Sce_trg_ck
global Sce_bgm_control
global Sce_bgmtbl_set
global Sce_fade_set
global Sce_fade_adjust
global Xa_on
global Xa_vol
global Se_vol
global Weapon_chg
global Sce_shake_on
global Sce_line_start
global Sce_line_main
global Sce_line_end
global Mizu_div_set
global Keep_Item_ck
global Sce_Item_lost
global Sce_Item_get
global Kage_set
global Light_pos_set
global Light_kido_set
global Light_color_set
global Light_pos_set2
global Light_kido_set2
global Light_color_set2
global Sce_scr_move
global Flr_set
global Movie_on
global Splc_ret
global Splc_sce
global Mirror_set
global Sce_parts_bomb
global Sce_parts_down
global Col_chg_set
;; SND.C
global Snd_sys_init
global FUN_800594c8
global Snd_sys_init2
global Snd_sys_Allvoff
global Snd_sys_init_sub
global Snd_sys_init_sub2
global Snd_sys_start
global Snd_sys_stereo
global Snd_sys_core_set
global Snd_sys_arms_set
global Snd_sys_room_set
global Snd_sys_enem_set
global Snd_sys_pset
global Snd_bgm_data
global Snd_bgm_set
global Snd_bgm_ck
global Snd_bgm_play_ck
global Snd_bgm_main
global Snd_bgm_sub
global Snd_bgm_fade_ON
global Snd_bgm_fade
global Snd_bgm_ctr
global Snd_bgm_tbl_set
global Snd_se_stad
global Snd_se_enem
global Snd_se_walk
global Snd_se_call
global Snd_se_pri_ck
global Snd_se_3D
global Snd_se_dir_ck
;; SPL.C
global Spl
global Spl_mv40
global Spl_mv42
global Spl_mv41
global Spl_mv44
global Spl_mv45
global Spl_mv47
global Spl_mv49
global Spl_mv48
global Spl_mv4a
global Spl_mv4b
global Spl_mv50
global Spl_mv51
global Spl_mv00
global Spl_Init
global Spl_in40
global Spl_in42
global Spl_in41
global Spl_in44
global Spl_in45
global Spl_in47
global Spl_in48
global Spl_in4a
global Spl_in4b
global Spl_in50
global Spl_in51
global Spl_in00
global Spl_Damage
global Spl_Die
global Spl_Dead
global Spl_dead00
global Spl_set
global Spl_chenge00
global Spl_chenge01
global Spl_kizu00
global Spl_chenge02
global Spl_chenge04
global Spl_chenge05
global Spl_chenge06
global Spl_chenge07
global Spl_chenge08
global Spl_chenge09
global Spl_chenge10
global Spl_chenge03
;; SPL_AUTO.C
global Spl_Root_ck_sys
global Spl_Auto
global Aida
global Aida_move
global Aida_Move_type00
global Aida_Move_type01
global Aida_Move_type02
global Aida_Move_type03
global Aida_Move_type04
global Aida_Move_type05
global Aida_Move_type06
global Aida_Move_type07
global Aida_Move_type08
global Aida_Move_type09
global Aida_Move_type0a
global Aida_em10_at00_pl
global Aida_em10_at00_spl
global Aida_em25_at00_pl
global Aida_em25_at00_spl
global Aida_em26_at00_pl
global Aida_em26_at00_spl
global Aida_mv00_br
global Aida_mv00_br_1
global Aida_mv00
global Aida_em10_at01
global Aida_em25_at01
global Aida_em26_at01
global Aida_mv01_br
global Aida_mv01_br_1
global Aida_mv01
global Aida_mv02_br
global Aida_mv02_br_1
global Aida_mv02
global Aida_mv03_br
global Aida_mv03
global Aida_mv04_br
global Aida_mv04
global Aida_mv05_br
global Aida_mv05
global Aida_mv05_w1
global Aida_mv05_w1_t0_br
global Aida_mv05_w1_t0
global Aida_em10_at05
global Aida_mv05_w1_t1_br
global Aida_mv05_w1_t1
global Aida_mv05_w1_t2_br
global Aida_mv05_w1_t2
global Aida_mv05_w1_t3_br
global Aida_mv05_w1_t3
global Aida_mv05_w1_t4_br
global Aida_mv05_w1_t4
global Aida_mv05_w1_t5_br
global Aida_mv05_w1_t5
global Aida_mv06_br
global Aida_mv06
global Aida_mv07_br
global Aida_mv07
global Aida_mv08_br
global Aida_mv08
global Aida_mv09_br
global Aida_mv09
global Aida_mv0a_br
global Aida_mv0a
global Aida_mv0b_br
global Aida_mv0b_br_1
global Aida_mv0b
global Aida_mv0c_br
global Aida_mv0c_br_1
global Aida_mv0d_br
global Sherry_move
global Sherry_Move_type00
global Sherry_Move_type01
global Sherry_Move_type02
global Sherry_Move_type03
global Sherry_Move_type04
global Sherry_Move_type05
global Sherry_Move_type06
global Sherry_Move_type07
global Sherry_Move_type08
global Sherry_Move_type09
global Sherry_Move_type0a
global Sherry_mv00_br
global Sherry_mv00
global Sherry_mv01_br
global Sherry_mv02_br
global Sherry_mv06_br
global Sherry_mv06
global Sherry_mv0b_br
global Sherry_mv0c_br
global Spl_dm00
global Spl_dm01
global Spl_die00
global Aida_before
global Aida_after
global Spl_soba_pos_set
global Spl_enemy_ck
global Spl_em_pos_ck
global Spl_em_cdir_ck
global Spl_pllock_get
global Spl_life_down
;; SPL_SCE.C
global Spl_Scenario
global Spl_sce00
global Spl_sce01
global Spl_sce02
global Spl_sce03
global Spl_sce04
global Spl_sce05
global Spl_sce06
global Spl_sce07
global Spl_sce08
global Spl_sce09
global Spl_sce0a
global Spl_sce0b
global Spl_sce0c
global Spl_sce0d
global Spl_sce0e
global Spl_sce0f
global Spl_sce10
global Spl_sce11
global Spl_sce12
global Spl_sce13
global Spl_sce14
global Spl_sce15
global Spl_sce16
global Spl_sce17
global Spl_sce18
global Spl_sce20
global Spl_sce_mv00
global Spl_sce_mv01
global Spl_sce_mv02
global Spl_sce_mv03
global Spl_sce_mv04
;; SPL_SP.C
global Spl_Sp_Move
global Spl_sp40_00
global Spl_sp44_00
;; STAGE1.C
global Stage1
;; STAGE2.C
global Stage2
;; STAGE3.C
global Stage3
;; STAGE4.C
global Stage4
;; STAGE5.C
global Stage5
;; STAGE6.C
global Stage6
;; STAGE7.C
global Stage7
;; STATUS.C
global Status_init
global Status_init_m
global Status
global St_exit
global St_fade_out_set
global St_fade_out_wait
global St_chenge_pl
global pl_tim_load
global St_file_set
global St_room_set
global St_disp_name
global Set_iwork
global Set_iwork_num
global Check_pl_life
global Check_item_space
global Check_item_mix
global Search_item
global Search_item_id
global Sort_item
global Shift_item
global Set_item
global Pix_trans
global Pix_trans_pl
global Pix_move
global Pix_clear
global St_pltex_operation
global Tama_ck_i
global Tama_decrease_i
global Tama_reload_ck
global Tama_reload
global Check_cursol_distance
;; ST_SUB00.C
global St_init00
global St_main00
global St_menu0_select
global St_menu0_item
global St_com_use_equip
global St_com_mix
global St_com_inspect
global St_menu0_file
global file_moji_load
global move_file_tag
global St_menu0_map
global St_init_disp_map
global St_disp_map
global Check_map_no
global Check_room_no
global St_menu1_map
global St_init03
global St_main03
;; ST_SUB01.C
global St_init01
global St_main01
global St_select_menu_m
global St_select_item_m
global Exchange_item
global St_init_itembox
global St_disp_itembox
;; ST_SUB02.C
global St_init02
global St_main02
global St_get_check
global St_get_item
global St_disp_file2
global St_get_file
;; ST_SUB04.C
global St_init_disp_num
global St_disp_num
global print_num
global St_init_disp_cursol0
global St_disp_cursol0
global St_init_disp_cursol1
global St_disp_cursol1
global St_init_disp_face
global St_disp_face
global St_init_disp_message
global St_disp_message
global St_init_disp_frame
global St_disp_frame
global St_init_disp_menu0
global St_disp_menu0
global St_init_disp_menu1
global St_disp_menu1
global St_init_disp_itemlist
global St_disp_itemlist
global St_init_disp_equip
global St_disp_equip
global St_init_disp_wall
global St_disp_wall
global St_init_disp_ECG
global St_disp_ECG
global St_init_disp_itp
global St_disp_itp
global St_init_disp_filesel
global St_disp_filesel
global St_init_disp_file
global St_disp_file
global ST_Om_trans
global model_disp
;; SUB.C
global Vram_clr
global Memcpy
global Memclr
global Mapping_tim
global Mapping_tmd
global Set_view
global Set_light
global Set_Light_data
global Flg_on
global Flg_off
global Flg_ck
global Rot_vector
global Rot_vector_super
global Rot_add_matrix
global Set_front_pos
global SetSpadStack
global ResetSpadStack
global SetSpadStack2
global ResetSpadStack2
global Get_work
global Free_work
;; T_ATVIEW.C
global Disp_atari
global Disp_atari_id_inc
global Disp_atari_id_dec
global Disp_atari_trans
global Disp_atari_trans2
;; T_RVIEW.C
global Rview
;; T_BLOCK.C
global Block_data
;; T_FLOOR.C
global Floor_data
;; T_PSP.C
global T_Psp
;; T_LIGHT.C
global Light_data
;; T_SCA.C
global Sc_hit
;; T_SND.C
global T_Snd
;; T_KAT0.C
global init_KI2
global init_KI2_LINE_F3
global color_plus_KI2_LINE_F3
global ki2_set
global ki_sort
global Maker_line_sort
global Enemy_move_tool
global Enemy_motion_view
global Enemy_st_view
global init_Enemy_tool_sitenn
global Enemy_tool_sitenn
global Weapon_maker_sort
;; T_EM_SET.C
global Tool_em_set
;; T_SCE_AT.C
global Tool_sce_at_set
;; T_ESP.C
global T_Esp
;; TRANS.C
global Prim_trans
global Trans_pointer_set
global Eff_sprt_trans
global Esp_trans_main
global Esp_trans_3d
global Trans_work_init
;; PSYQ
global start
global VSync
global DsPacket
global SetGeomOffset
global DsFlush
global DsIntToPos
global DsSyncCallback
global DsReadyCallback
global DsGetSector
global DsPosToInt
global DsCommand
global DsSystemStatus
global DsStatus
global SetTile
global SetSemiTrans
global SetDrawMode
global AddPrim
global EnterCriticalSection
global SsSetSerialAttr
global printf
global memset
global DrawSync
global SsVabTransCompleted
global SsVabTransBodyPartly
global DeliverEvent
global ExitCriticalSection
global SpuSetTransferMode
global SsVabOpenHeadSticky
global SsVabClose
;; DATA
global Xa_no
global Enemy_edt
global floc
global Xa_sector00
global Serial_no
global cdmode
global xa_cdmode
global xa_control_tbl
global xacontrol_cdmode
global cdread_cdmode
global cdread_s_cdmode
global door_msg
global door_msg_ofs
global D_LIGHTMATRIX
global D_COLORMATRIX
global Dtex_file
global Dinfo
global pDoor_proc_tbl
global Aida_jh0_tbl
global Aida_jh0_head
global Aida_jh1_tbl
global Aida_jh1_head
global Aida_jh2_tbl
global Aida_jh2_head
global Aida_jh3_tbl
global Aida_jh3_head
global Aida_jh4_tbl
global Aida_jh4_head
global Aida_jh5_tbl
global Aida_jh5_head
global Kg_jh0_tbl
global Kg_jh0_head
global cdemd0_pos
global cdemd0_sum
global cdemd1_pos
global cdemd1_sum
global cdemd2_pos
global cdemd2_sum
global cdemd3_pos
global cdemd3_sum
global Emd_name
global Emd_tim_name
global Room_100
global Room_102
global Room_101
global Room_202
global Room_109
global Room_10B
global Room_110
global Room_117
global Room_700
global Room_702
global Room_703
global Room_705
global Em_stbl_st1
global Em_stbl_st2
global Em_stbl_st7
global Room_Enemy_tbl
global Esp_tblj
global sin_tbl
global quake_tbl1
global quake_tbl2
global sinpuku
global hacho
global speed
global mode
global GsIDMATRIX
global LIGHTMATRIX
global COLORMATRIX
global Bgm_sw_timer
global No_death_timer
global Curtain
global Pause
global Scrl_h
global Rect
global Rect_bg
global Bomb_tbl
global Mizu_size_tbl
global Mizu_tbl
global Mizu_struct_tbl
global Div_prim_coord
global msg_space
global namelist_tbl_data
global namelist_tbl_ofs
global namelist_u_data
global namelist_u_ofs
global mess_tbl_data
global mess_tbl_ofs
global mess_u_data
global mess_u_ofs
global mess_sub_data
global mess_sub_ofs
global mess_etc_data
global mess_etc_ofs
global branch_data
global branch_ofs
global ascii_tbl
global Ld_task_tbl
global Movie_tbl
global pMovie_proc_tbl
global pDoor_proc_tbl_ex
;;global Subpl_walk
;;global Subpl_back
;;global Subpl_dir
;;global Subpl_ato
;;global Subpl_run
;;global Em4a_zobiparts_tbl
global Up_add_tbl
global Down_add_tbl
global Box_sub_tbl
global Up_add_Spl_tbl
global Down_add_Spl_tbl
global Key_type
global Stp_bak
global Key_wait
global Init_work_tbl
global pc_mes_data
global pc_mes_ofs
;;global Kend
;;global Mend
;;global Key_type
;;global Kend
;;global Mend
;;global Key_type
;;global Subpl_walk
;;global Subpl_back
;;global Subpl_dir
;;global Subpl_ato
;;global Subpl_run
;;global Em4a_zobiparts_tbl
global Pld_no
global Pl_neck_timer
global Pld_name
global Pl_routine
global Pl_mv_pad
global Pl_mv
global Pl_kage_pos
global pl_water
global Wat_vec00
global Pl_dm
global Pl_die_t
global Em10_damage_tbl
global Em15_damage_tbl
global Em20_damage_tbl
global Em21_damage_tbl
global Em22_damage_tbl
global Em24_damage_tbl
global Em23_damage_tbl
global Em25_damage_tbl
global Em27_damage_tbl
global Em28_damage_tbl
global Em29_damage_tbl
global Em2d_damage_tbl
global Em2a_damage_tbl
global Em2b_damage_tbl
global Em2e_damage_tbl
global Em30_damage_tbl
global Em31_damage_tbl
global Em33_damage_tbl
global Em34_damage_tbl0
global Em34_damage_tbl1
global Em36_damage_tbl
global Em3a_damage_tbl
global Em3b_damage_tbl
global PLW00_W
global PLW00_S
global Pl_w011
global Pl_w01_s1
global Pl_w0111
global Pl_w0111_s1
global Pl_w010
global Pl_w01_s0
global Pl_w012
global Pl_w01_s2
global PLW02_W
global PLW02_S
global PLW05_W
global PLW05_S
global PLW13_W
global PLW13_S
global PLW07_W
global PLW07_S
global PLW08_W
global PLW08_S
global PLW0E_W
global PLW0E_S
global PLW0F_W
global PLW0F_S
global PLW12_W
global PLW12_S
global Pl_weapon_tbl
global pEnemy_damage_tbl
global Pl_bow_hit_parts
global Plw_no
global Pl_weapon_init
global Pl_weapon_kyan
global W_at_ck
global Ghand_len
global Mw_ck
global Pl_wep_mag_type
global Pl_mag
global G_rot_data_z
global pl_mv05_w_tbl
global Gun_jtg_bit
global pl_mv05_t2_init
global pl_mv05_t2_spr
global pl_mv05_w0_tbl
global pl_mv05_w1_tbl
global Bow_Room509
global pl_mv05_w2_tbl
global pl_mv05_w3_tbl
global pl_mv05_w4_tbl
global pl_mv05_w5_tbl
global Poly_test4
global ascii_tbl_2
global Rdt_tbl1
global Rdt_tbl2
global Rdt_tbl3
global Rdt_tbl4
global Rdt_tbl5
global Rdt_tbl6
global Rdt_tbl7
global Rdt_tbl
;;global Subpl_walk
;;global Subpl_back
;;global Subpl_dir
;;global Subpl_ato
;;global Subpl_run
;;global Em4a_zobiparts_tbl
global Sca_rtn_tbl
global Sca_no_ck_tbl
global Sce_at_jump_tbl
global em_se_tbl
global Sce_jmp_tbl
global Em_kind_tbl
;;global Subpl_walk
;;global Subpl_back
;;global Subpl_dir
;;global Subpl_ato
;;global Subpl_run
;;global Em4a_zobiparts_tbl
global Flg_addr
;;global Subpl_walk
;;global Subpl_back
;;global Subpl_dir
;;global Subpl_ato
;;global Subpl_run
;;global Em4a_zobiparts_tbl
global Itp_check_sum
global EnemSE_floc
global LRVT
global PANVT
global nroom
global Core_edh
global Core_vbd
global Arms_edh
global Arms_vbd
global Main_bgm
global Sub_bgm
;;global Subpl_walk
;;global Subpl_back
;;global Subpl_dir
;;global Subpl_ato
;;global Subpl_run
;;global Em4a_zobiparts_tbl
global Spl_routine_0
global Spl_mv
global Spl_in
global Spl_dm
global Spl_die
global Spl_dead
;;global Subpl_walk
;;global Subpl_back
;;global Subpl_dir
;;global Subpl_ato
;;global Subpl_run
;;global Em4a_zobiparts_tbl
global Spl_r_pos
global Aida_Move_type
global Aida_St_pos
global Spl_pos_ck_timer
global Aida_mv_br_type00
global Aida_mv_type00
global Aida_mv_br_type01
global Aida_mv_br_type02
global Aida_mv_br_type03
global Aida_mv_br_type04
global Aida_mv_br_type05
global Aida_mv_br_type06
global Aida_mv_br_type07
global Aida_mv_br_type08
global Aida_mv_br_type09
global Aida_mv_br_type0a
global E_A_at_tbl
global Aida_em_at00_pl
global Aida_em_at00_spl
global Aida_em_at01
global Aida_mv05_w1_br_tbl
global Aida_mv05_w1_tbl
global Aida_em_at05
global Sherry_Move_type
global Sherry_St_pos
global Sherry_mv_br_type00
global Sherry_mv_br_type01
global Sherry_mv_br_type02
global Sherry_mv_br_type03
global Sherry_mv_br_type04
global Sherry_mv_br_type05
global Sherry_mv_br_type06
global Sherry_mv_br_type07
global Sherry_mv_br_type08
global Sherry_mv_br_type09
global Sherry_mv_br_type0a
;;global Subpl_walk
;;global Subpl_back
;;global Subpl_dir
;;global Subpl_ato
;;global Subpl_run
;;global Em4a_zobiparts_tbl
global Spl_sce
;;global Subpl_walk
;;global Subpl_back
;;global Subpl_dir
;;global Subpl_ato
;;global Subpl_run
;;global Em4a_zobiparts_tbl
global Spl_sp
global init_item_tbl_Leon
global init_item_tbl_Claire
global init_item_tbl_Hunk
global init_item_tbl_ToFu
global init_item_tbl_Leon_Ex
global init_item_tbl_Claire_Ex
global init_item_tbl_Ada_Ex
global init_item_tbl_Chris_Ex
global Status_proc_tbl
global st_light
global init_item_tbl_Ada
global init_item_tbl_Sherry
global maps_floc
global fits_floc
global Status_menu0_proc_tbl
;;global add
global File_offset
global map_up_floor
global map_down_floor
global Map_char_tbl
global Status_direct_map_proc_tbl0
global Status_direct_map_proc_tbl1
global St_itembox_proc_tbl
global Ibox_char_tbl
global f4_tbl
global Ibox_pos_tbl
global St_getitem_proc_tbl
global move_tbl
;;global add
global Mix_nodata
global Mix_beretta
global Mix_magnam
global Mix_shotgun
global Mix_machinegun
global Mix_fire
global Mix_bowgun
global Mix_g_n
global Mix_g_f
global Mix_g_a
global Mix_spark
global Mix_bullet
global Mix_dot380
global Mix_shot_dan
global Mix_arrow
global Mix_mag_dan
global Mix_nen
global Mix_battley
global Mix_g_normal
global Mix_g_fire
global Mix_g_acid
global Mix_ink_ribbon
global Mix_parts_a
global Mix_parts_b
global Mix_parts_c
global Mix_g
global Mix_r
global Mix_b
global Mix_gr
global Mix_gg
global Mix_gb
global Mix_p_bomb
global Mix_fuse
global Mix_Jaguar_a
global Mix_Jaguar_b
global Item_data_tbl
global File_data
global Map_stage1_0
global Map_stage1_1
global Map_stage1_2
global Map_stage1_3
global Map_stage2_0
global Map_stage2_1
global Map_stage3_0
global Map_stage4_0
global Map_stage4_1
global Map_stage5_0
global Map_stage5_1
global Map_stage5_2
global Map_stage5_3
global Map_stage6_0
global Map_stage6_1
global Map_stage6_2
global Map_stage6_3
global Map_stage6_4
global Map_stage6_5
global Map_stage7_0
global Map_stage7_1
global Map_info
global Ecg_normal_tbl
global Ecg_caution0_tbl
global Ecg_caution1_tbl
global Ecg_danger_tbl
global Ecg_poison_tbl
global N_pos
global Cursol0_char_tbl
global Cursol0_pos_tbl
global Cursol1_char_tbl
global Cursol1_pos_tbl
global Face_char_tbl
global Face_subchar_tbl
global Face_pos_tbl
global Face_subpos_tbl
global Message_char_tbl
global Message_pos_tbl
global Frame_char_tbl
global Frame_pos_tbl
global Menu0_char_tbl
global Menu0_pos_tbl
global Menu1_char_tbl
global Menu1_pos_tbl
global Itemlist_char_tbl
global Itemlist_pos_tbl
global Equip_char_tbl
global Equip_pos_tbl
global Ecg_col_tbl
global Ecg_line_tbl
global ECG_char_tbl
global Itemget_char
global Itemget_pos_tbl
global v_p
global v_r
global pp
global pMem_man
;;global Svec
;;global Svec
global Poly_ft4_count
global _spu_RXX
global _spu_tsa
global _spu_transMode
global _spu_mem_mode_plus
global _spu_mem_mode_unitM
global _spu_inTransfer
global _spu_transferCallback
global _spu_IRQCallback
global _spu_EVdma
global _spu_keystat
global _spu_trans_mode
global _spu_rev_flag
global _spu_rev_reserve_wa
global _spu_rev_offsetaddr
global _spu_rev_attr
global _spu_RQvoice
global _spu_RQmask
global _spu_zerobuf
global _spu_env
global _spu_isCalled
global _spu_AllocBlockNum
global _spu_AllocLastNum
global _spu_memList
global _spu_rev_startaddr
global _snd_seq_tick_env
;;global rsin_tbl
global _stacksize
;;global rsin_tbl
;;global rsin_tbl
global Vcount
global GsCLIP3near
global GsCLIP3far
global GsOUT_PACKET_P
global CD_cbsync
global CD_cbready
global CD_debug
global CD_status
global CD_pos
global CD_mode
global CD_com
global DS_active
global CD_comstr
global CD_intstr
global CDROM_DELAY
global CDROM_REG0
global CDROM_REG1
global CDROM_REG2
global CDROM_REG3
;;global CDROM_DELAY
global COMMON_DELAY
global DMA_DPCR
global DMA_DICR
global DMA_MDEC_OUT_CHCR
global DMA_CDROM_CHCR
;;global rsin_tbl
global SQRT
global rcossin_tbl
global ratan_tbl
global GPU_printf
global DecDctEnv
global DCL_DVLC
global DCC_DVLC
global CF_DVLC
global CF2_DVLC
global _padFuncNextPort
global _padFuncClrInfo
global _padFuncGetTxd
global _padFuncCurrLimit
global _padFuncPtr2Port
global _padFuncPort2Info
global _padFuncSendAuto
global _padFuncChkEng
global _padFuncRecvAuto
global _padFuncClrCmdNo
global _padInfoDir
global _padIntExec
global _padSioChan
global _padSioState
global _padTotalCurr
global _padModeMtap
global _padChanStart
global _padChanStop
global _padFixResult
global _padCalledIntPad
;;global __sbss_obj
global pDoor
global Stop_bak
global V
global Kpos
global Kofs
global pPc
global Hit_flg_0
global pSca_data
global Old_x
global Old_z
global Hit_flg
global Gnd_y
global In_flg
global Tmp_Sca
global Key_work
global Dir_spd
global Spd_add
global pOwork
global Key_work_0
global pItem_dat
global pAot
global EM40_Prim
global shot
global num
global Tmp_matrix
;;global Svec
global pStack_bak
global _padVsyncParam
global _padRestPeriod
;;global _padIntExec
global Poly2_work
global add_y
global Reverb_flg
global Trans
global PadActData
global Stframe_no
global Sedir2
global SsFCALL
global m_pl_weapon_tmd
global G
global Vab_id
global _svm_rattr
global Stsector_offset
global StRgb24
global StMode
global Em_dir
global Cd_vol
global Se_pri
global Move_x
global pEspdt
global pDwork
global bk_cut
global pEspmv
global sel_no
global Entory
global StFunc1
global StFunc2
global _svm_vab_pg
global StCdIntrFlag
;;global _svm_vab_pg
global _svm_vab_vh
global _svm_damper
;;global _svm_vab_vh
global _svm_vab_tn
;;global _svm_vab_tn
global CD
global Channel
global _spu_RQ
global Mem_man
global m_pl_w00_tmd2
global Ceiling
global pSce_em
global St
global StCHANNEL
global StStartFrame
global _svm_stereo_mono
global Cc_work
global Pan_vol
global pVh_tbl
global Seq_ctr
global Vm_disp
global Om_fall_old_dir_x
global pVm_frm
global Om_fall_old_dir_z
global pSpl_near_em
global UnknownPadInfoByte
global _snd_ev_flag
global Rev_vol
global gpPl_pac_ptr
global kMaxPrograms
global CdReadSoundCnt
global sw
global Vm_work
global pStairs
global Ev0
global Monitor
global Ev1
global Ev2
global Ev3
global xx
global _svm_pg
global UnkSndSysInitSubFlg
global yy
global gpPl_tmd_ptr
global _svm_vg
global _svm_vh
global _svm_tn
global CChannel
global _SsVmMaxVoice
global Bgm
global gpPl_pac2_ptr
global UnkMvPadFlg
global Sce
global Ev10
global Loc
global Ev11
global Ev13
global RevD_vol
global m_pl_weapon_parts
global gpPl_tmd2_ptr
global Esp
global pEdt_adr
global UnkSndFlg0
global UnkSndSysFlg0
global StFinalSector
global Poly_eff
global Om_fall_dir_x
global Main_vol
global Om_fall_dir_y
global Om_fall_dir_z
global f_x
global f_y
global GsWSMATRIX
global Ground_in_flg
global bk_light
global pESP
global _snd_openflag
global _autopan
global Ex_battle_rcut
global _svm_cur
global Ex_battle_vcut
global _svm_vab_used
global Poly_eff2
global _autovol
global m_pl_weapon_packet
global pMovie_result
global StEmu_Idx
global Fade_mode
global Game
global Demo
global Key_idx_bak
global UnknownSetRoomByte
global Em_l
global _svm_auto_kof_mode
global Main
global pBgm
global Line
global UnknownPadSetFlag
global UnknownSndSysFlg
global Ret_Value
global GsMWSMATRIX
global Moji
global Moji_buff
global _svm_envx_ptr
global Volume_Se
global Seq_table
global pAtv
global _que
global Ceiling_in_pos
global VBLANK_MINUS
global StRingIdx1
global StRingIdx2
global StRingIdx3
global pCom_work
global pPsp_prim
global m_pl_w00_packet
global _ss_score
global _SsMarkCallback
global pPsp_work
global _snd_seq_s_max
global StEmu_Addr
global _snd_seq_t_max
global StEndFrame
global StSTART_FLAG
global pCAot
global StRingBase
global StRingAddr
global _svm_vab_total
global Old_Fatari
global MainVbSize
global _svm_vab_count
global _svm_vab_start
global Old_Uatari
global pFile
global m_pl_w00_packet2
global Volume_Bgm
global RoomVbSize
global Espid
global _svm_envx_hist
global Sedir
global StRingSize
global _svm_okof1
global _svm_okof2
;;
;; Routine
;;
desld_set: equ 0x80010000
desld: equ 0x80010084
memcpy16: equ 0x80010778
setexmask: equ 0x800107B4
Cd_init: equ 0x800128C4
Cd_system_control: equ 0x80012984
Xa_play: equ 0x800129B4
Xa_control: equ 0x80012C68
Xa_control_stop: equ 0x80012CA4
Xa_control_init: equ 0x80012CD8
Xa_seek: equ 0x80012D30
Xa_control_play: equ 0x80012E70
Xa_control_end: equ 0x80012F48
Cd_read: equ 0x80012FB8
Cd_read_s: equ 0x800132B0
Cd_seek: equ 0x80013714
Cd_ready_cb: equ 0x8001376C
Cd_set_stereo: equ 0x80013A7C
Set_volume: equ 0x80013AC8
Change_volume: equ 0x80013B4C
Door_main: equ 0x80013BC4
Door_init: equ 0x80013C1C
Door_move: equ 0x80013EB4
Door_scheduler_main: equ 0x80014058
Door_exit: equ 0x8001417C
Door_Trans: equ 0x80014234
DoorSort: equ 0x8001468C
Door_model_init: equ 0x80014B40
Door_model_set: equ 0x80014BA4
Door_snd_trans: equ 0x80014CD0
Door_texture_load: equ 0x80015064
Hani_ck: equ 0x80015280
Add_speedXZ: equ 0x800152C8
Add_speedXYZ: equ 0x80015350
Add_speedXYZsuper: equ 0x800153F4
Direction_ck: equ 0x800154AC
Goto00: equ 0x80015558
Goto00_ck: equ 0x80015614
Goto01: equ 0x8001569C
Goto01_ck: equ 0x80015714
Dir_pos_ck: equ 0x80015758
L_pos_ckXZ: equ 0x800157D4
L_pos_ckXZM: equ 0x80015834
Cdir_ck: equ 0x80015910
Cdir_ck2: equ 0x80015930
Gacha_ch: equ 0x8001598C
Sikai_ck: equ 0x800159A4
Set_base_pos: equ 0x80015B94
Null_pos_set: equ 0x80015CB8
get_null_pos: equ 0x80015DB0
Spd_get: equ 0x80015E7C
Rnd: equ 0x80015FE8
Em_seq_sound: equ 0x80016028
Tex_Ani_move: equ 0x80016068
Foot_set_pl: equ 0x80016200
Kage_work_init: equ 0x8001633C
Kage_work9_init: equ 0x8001645C
Kage_work_set: equ 0x80016480
Kage_work9_set: equ 0x8001653C
MulKage: equ 0x800168B4
Kage_work_sort: equ 0x8001699C
Kage_work9_sort: equ 0x80016C14
Kage_work_color_set: equ 0x80016FE4
Kage_work9_color_set: equ 0x8001700C
Texture_Move: equ 0x80017054
Texture_Move_GT3: equ 0x800171D0
Texture_Move_GT4: equ 0x800172F8
Texture_Move_GT4_up: equ 0x8001745C
Rot_neck: equ 0x800177C0
Rot_neck_em: equ 0x80017D98
Rot_neck_em_n: equ 0x80017FDC
Neck_Dir_ZY: equ 0x8001820C
Op_PartsSort00: equ 0x80018378
Op_PartsSort05: equ 0x8001844C
Op_PartsSort06: equ 0x80018648
Kami_rot05: equ 0x80018728
W_rot: equ 0x80018CC8
W_rot_x: equ 0x80018D64
Rbj_set: equ 0x80018E08
Em_dead_flg_on: equ 0x80018FB0
Aida_Jh_init: equ 0x80019024
Aida_Jh_move: equ 0x800190C0
Kg_Jh_init: equ 0x800193C0
Kg_Jh_move: equ 0x800193F0
Jh_set: equ 0x80019628
MulJh: equ 0x800197F4
Aida_Jh_sort: equ 0x80019B3C
Jh_sort: equ 0x80019CD0
Approach: equ 0x8001A0E0
Approach_one: equ 0x8001A1E0
Mot_play: equ 0x8001A240
Mot_play2: equ 0x8001A2A4
Mot_play_init: equ 0x8001A308
Mot_play_sp: equ 0x8001A330
Mot_play2_sp: equ 0x8001A3E8
Mot_play2_spxz: equ 0x8001A4A0
Em_init_super: equ 0x8001A558
Branch: equ 0x8001A58C
Ck_em_id: equ 0x8001A5C0
Goto00_super: equ 0x8001A644
Goto01_super: equ 0x8001A858
Get_parts_world_dir: equ 0x8001A9BC
Enemy_work_set: equ 0x8001AA38
Em_set: equ 0x8001AAA0
Emd_load: equ 0x8001AAA8
Set_enemy_work: equ 0x8001AD3C
Kill_enemy_work: equ 0x8001B250
Em_move_tbl_set: equ 0x8001B274
Em_bin_load: equ 0x8001B710
Emd_load_file: equ 0x8001b934
Esp_init_C: equ 0x8001BABC
Esp_init_R: equ 0x8001BBA4
Esp_data_set0: equ 0x8001BCA0
Esp_data_set1: equ 0x8001BD38
Esp_call: equ 0x8001BF10
Esp_call3D: equ 0x8001C224
Esp_call3D2: equ 0x8001C56C
Esp_call2: equ 0x8001C8C4
Esp_call3: equ 0x8001CBE8
Esp_kill: equ 0x8001CEFC
Esp_kill2: equ 0x8001CFBC
Esp_die: equ 0x8001CFFC
Esp_ctrl: equ 0x8001D0AC
Esp_ctrl2: equ 0x8001D15C
Esp_ctrl3: equ 0x8001D180
Esp_ctrl4: equ 0x8001D240
Esp_move: equ 0x8001D300
Esp_pos: equ 0x8001D68C
Esp_00: equ 0x8001DC28
Esp_01: equ 0x8001DC30
Esp_02: equ 0x8001DD2C
Esp_03: equ 0x8001DE88
Esp_04: equ 0x8001DF50
Esp_05: equ 0x8001DF90
Esp_06: equ 0x8001E11C
Esp_07: equ 0x8001E154
Esp_08: equ 0x8001E200
Esp_09: equ 0x8001E390
Esp_0a: equ 0x8001E3C4
Esp_0b: equ 0x8001E4B4
Esp_0c: equ 0x8001E638
Esp_0d: equ 0x8001E898
Esp_0e: equ 0x8001E8B0
Esp_0f: equ 0x8001ED9C
Esp_10: equ 0x8001F128
Esp_11: equ 0x8001F198
Esp_12: equ 0x8001F2A0
Esp_13: equ 0x8001F2C0
Esp_14: equ 0x8001F530
Esp_15: equ 0x8001F5A4
Esp_16: equ 0x8001F634
Esp_17: equ 0x8001F6A4
Esp_18: equ 0x8001F6E0
Esp_19: equ 0x8001FA08
Esp_1a: equ 0x8001FA6C
Esp_1b: equ 0x8001FA9C
Esp_1c: equ 0x8001FBD0
Esp_1d: equ 0x8001FD5C
Esp_1e: equ 0x8001FECC
Esp_1f: equ 0x8001FF98
Esp_20: equ 0x800200B0
Esp_21: equ 0x80020298
Esp_22: equ 0x80020364
Esp_23: equ 0x800204F8
Esp_24: equ 0x80020510
Esp_25: equ 0x80020660
Esp_26: equ 0x800206E0
Esp_27: equ 0x800206FC
Esp_28: equ 0x80020758
Esp_29: equ 0x800207E4
Esp_2a: equ 0x800208B8
Esp_2b: equ 0x80020950
Esp_2c: equ 0x800209CC
Esp_2d: equ 0x80020ABC
Esp_2e: equ 0x80020B60
Esp_2f: equ 0x80020C3C
Esp_30: equ 0x80020F3C
Esp_31: equ 0x800215C8
Esp_32: equ 0x80021970
Esp_33: equ 0x800219B4
Esp_34: equ 0x80021A48
Esp_35: equ 0x80021B00
Esp_36: equ 0x80021CE4
Esp_37: equ 0x80021D24
Esp_38: equ 0x80021E14
Esp_39: equ 0x80022094
Esp_3a: equ 0x80022254
Esp_3b: equ 0x800223F8
Esp_3c: equ 0x80022454
Esp_3d: equ 0x80022474
Esp_3e: equ 0x8002256C
Esp_3f: equ 0x800226AC
Esp_40: equ 0x80022728
Esp_41: equ 0x80022774
Esp_42: equ 0x800228D8
Esp_43: equ 0x800229E4
Esp_44: equ 0x80022ABC
Esp_45: equ 0x80022EBC
Esp_46: equ 0x80023204
Esp_47: equ 0x80023554
Esp_48: equ 0x8002373C
Esp_49: equ 0x8002387C
Esp_4a: equ 0x800238E4
Esp_4b: equ 0x800239C4
Esp_4c: equ 0x80023B94
Esp_4d: equ 0x80023C70
Esp_4e: equ 0x800241C8
Esp_4f: equ 0x8002434C
Esp_50: equ 0x8002453C
Esp_51: equ 0x800246E8
Esp_52: equ 0x80024818
Esp_53: equ 0x800252B8
Esp_54: equ 0x80025348
Esp_55: equ 0x8002539C
Esp_56: equ 0x80025408
Esp_57: equ 0x8002563C
SeVibOn: equ 0x8002574C
Esp_58: equ 0x80025754
Esp_59: equ 0x8002575C
Esp_5a: equ 0x80025764
Esp_5b: equ 0x8002576C
Esp_5c: equ 0x80025774
Esp_5d: equ 0x8002577C
Esp_5e: equ 0x80025784
Esp_5f: equ 0x8002578C
Game_loop: equ 0x80025794
Set_door: equ 0x80026B7C
Gun_light_set: equ 0x80026ED8
Gun_light_reset: equ 0x800270EC
Joint_trans2: equ 0x80027160
ko_joint_trans2: equ 0x80027434
SortGT3_neo: equ 0x80027BEC
SortGT4_neo: equ 0x80027DBC
ko_joint_trans3: equ 0x80027FF0
PartsWork_set: equ 0x80028324
PartsWork_link: equ 0x80028368
Init_Parts_work: equ 0x80028648
Mem_ck_Parts_work: equ 0x800289B4
Joint_pos_trans: equ 0x80028A24
Parts_down: equ 0x80028AD8
Parts_bomb: equ 0x80028DAC
Parts_ryu: equ 0x80028EA4
HMatrix: equ 0x80028F48
HMatrix1: equ 0x80029120
Model_color_plus: equ 0x8002940C
Joint_move: equ 0x8002959C
J_seq: equ 0x80029614
hokan_svec: equ 0x80029B70
Pl_set_packet: equ 0x80029C94
Joint_move_p: equ 0x80029E10
Joint_move2: equ 0x8002A490
J_seq2: equ 0x8002A508
Scr_effect: equ 0x8002AA28
Scr_quake: equ 0x8002AA6C
Scr_rasta: equ 0x8002AB84
line_trans: equ 0x8002AC94
line_scr_end: equ 0x8002ADDC
line_mode_set: equ 0x8002AE10
Line_work_init: equ 0x8002AEC8
main: equ 0x8002AEE0
Init_system: equ 0x8002B48C
InitGeom_func: equ 0x8002B6AC
Init_main: equ 0x8002B6D4
Swap_Cbuff: equ 0x8002B968
Bg_set_mode: equ 0x8002BDA8
Bg_draw: equ 0x8002BDF4
Fade_set: equ 0x8002C1A0
Fade_adjust: equ 0x8002C2B0
Fade_off: equ 0x8002C324
Fade_status: equ 0x8002C350
System_trans: equ 0x8002C378
Init_global: equ 0x8002C610
Cut_check: equ 0x8002C6B4
Cut_change: equ 0x8002C7AC
Ccut_serach: equ 0x8002C7DC
Hit_ck_point4: equ 0x8002C820
Hit_ck_box: equ 0x8002C904
Card_event_set: equ 0x8002C94C
Logo: equ 0x8002CAC4
PresetObjectGT3_neo: equ 0x8002CBC4
PresetObjectGT4_neo: equ 0x8002CD24
CompM: equ 0x8002CE94
mapModelingData: equ 0x8002CFD8
MulLMatrix: equ 0x8002D030
SortGT3_lno: equ 0x8002D0E8
SortGT4_lno: equ 0x8002D244
Bomb_Parts_SortGT3: equ 0x8002D3C8
Bomb_Parts_SortGT4: equ 0x8002D718
Ryu_Parts_SortGT3: equ 0x8002DA80
Ryu_Parts_SortGT4: equ 0x8002DDF0
mirror_TMD_GT3: equ 0x8002E1B4
mirror_PACKET_GT3: equ 0x8002E1FC
mirror_TMD_GT4: equ 0x8002E240
mirror_PACKET_GT4: equ 0x8002E288
Mirror_model_cp: equ 0x8002E2D8
Init_mirror_weapon: equ 0x8002E4F8
Mirror_weapon_cp: equ 0x8002E548
Parts_work_cp: equ 0x8002E788
Mirror_view: equ 0x8002E93C
Mirror_in_view: equ 0x8002EA40
Mirror_trans: equ 0x8002EAF8
Mirror_matrix_set: equ 0x8002ED30
Late_set: equ 0x8002EEB4
Mizu_trans: equ 0x8002EF50
Mizu_div_ck: equ 0x8002F29C
Mizu_div_main: equ 0x8002F3FC
Print8: equ 0x8002FA00
Print14: equ 0x8002FA28
Print_main: equ 0x8002FA54
Mess_set: equ 0x8002FE38
Moji_trans_main: equ 0x8003022C
Mess_disp: equ 0x8003027C
Branch_disp: equ 0x80030844
name_ptr_set: equ 0x80030B9C
mess_trans: equ 0x80030C9C
Name_disp: equ 0x80031070
Mess_print: equ 0x800313A4
moji_trans_main: equ 0x800316A8
moji_trans_8: equ 0x80031734
moji_trans_14: equ 0x800318A4
Moji_buff_init: equ 0x80031AC4
Moji_init: equ 0x80031AF4
Moji_mode_init: equ 0x80031BF0
Init_scheduler: equ 0x80031CC0
Scheduler: equ 0x80031D8C
Task_lexecute: equ 0x80031E80
Task_lchain: equ 0x80031F00
Task_execute: equ 0x80031F6C
Task_sleep: equ 0x80031F94
Task_exit: equ 0x80031FE4
Task_kill: equ 0x80032030
Task_chain: equ 0x8003208C
Task_suspend: equ 0x800320E0
Task_signal: equ 0x8003210C
Task_status: equ 0x80032138
Init_movie_work: equ 0x80032150
Movie: equ 0x80032340
Movie_init: equ 0x80032450
Movie_main: equ 0x80032700
Movie_end: equ 0x80032984
Movie_exit: equ 0x80032AB8
Open_movie: equ 0x80032CE8
Play_movie: equ 0x80032FCC
Close_movie: equ 0x80033118
RuntoImage: equ 0x8003317C
Mdec_callback: equ 0x8003324C
Movie_xa_start: equ 0x8003331C
Movie_xa_stop: equ 0x80033370
Set_movie_volume2: equ 0x800333C4
CdReset2: equ 0x80033440
Oba_ck_hit: equ 0x80034D0C
Oba_ck_only: equ 0x800352D8
Oba_set_ofs: equ 0x80035408
Oba_ck_em: equ 0x80035530
Oba_ck_em2: equ 0x800355C4
Sca_ck_em: equ 0x8003567C
Om_init: equ 0x80035710
Col_chg_init: equ 0x800357D8
Tex_chg_init: equ 0x800358F0
Tex_ctr: equ 0x80035994
Col_chg: equ 0x80035AD0
Tex_chg: equ 0x80035C98
Om_move: equ 0x80035F68
Om_trans: equ 0x800363F0
Om_move_box: equ 0x80036710
Om_set_fall_dir: equ 0x80036C5C
Ob_test_load2: equ 0x80036CF8
Oma_set_ofs: equ 0x80036E30
Oma_ck_oba: equ 0x80036EF8
Oma_ck_om: equ 0x80037258
Oma_ck_front: equ 0x80037450
Oma_pl_updown_ck: equ 0x800375C8
Oma_Spl_updown_ck: equ 0x80037940
Oma_front_ck: equ 0x80037D48
Oma_on_check: equ 0x80037EAC
Oma_pull: equ 0x80037F60
Oma_pull_hosei_x: equ 0x80038664
Oma_pull_hosei_z: equ 0x800386D0
Oma_get_on_om: equ 0x8003873C
Oma_ob_pull2: equ 0x80038818
Omd_in_check: equ 0x80038950
Oma_obj_ck_all: equ 0x800389E8
Oma_hit_ck_all: equ 0x80038A98
Om_Jump_ck: equ 0x80038B84
Pad_set: equ 0x80038BBC
Pad_rep_set: equ 0x80039464
Windows: equ 0x80039818
Keyboard_Input: equ 0x800398AC
Keyboard_set: equ 0x80039B30
Keyboard: equ 0x80039B88
Wframe_in_out: equ 0x80039ED4
Wframe_set: equ 0x8003A034
Wframe_move: equ 0x8003A148
Get_moji_code: equ 0x8003A28C
Cprint: equ 0x8003A298
Console_put: equ 0x8003A56C
Console_roll_up: equ 0x8003A5A4
Console_clr: equ 0x8003A668
Console_trans: equ 0x8003A6AC
Sprite_Trans: equ 0x8003A794
Set_sp_work: equ 0x8003A8CC
Dr_mode_set: equ 0x8003A92C
Computer200: equ 0x8003A9F4
Computer613: equ 0x8003B264
Computer_init: equ 0x8003B7E8
Computer_exit: equ 0x8003B918
Player_set: equ 0x8003BAF0
Pl_before: equ 0x8003BED8
Pl_after: equ 0x8003BF7C
Player_move: equ 0x8003BFAC
Pl_init: equ 0x8003C210
Pl_move: equ 0x8003C57C
pl_mv00_pad: equ 0x8003C5F8
pl_mv00: equ 0x8003C780
pl_mv01_pad: equ 0x8003C924
pl_mv01: equ 0x8003CBDC
pl_mv02_pad: equ 0x8003CE24
pl_mv02: equ 0x8003D0E8
pl_mv03_pad: equ 0x8003D3E0
pl_mv03: equ 0x8003D5F4
Lim_dir_ck: equ 0x8003D96C
Pl_neck: equ 0x8003DB38
pl_mv04_pad: equ 0x8003DD48
pl_mv04: equ 0x8003DFF4
pl_mv06_pad: equ 0x8003E1D4
pl_mv06: equ 0x8003E1DC
pl_mv07_pad: equ 0x8003E314
pl_mv07: equ 0x8003E31C
pl_mv08_pad: equ 0x8003E8CC
pl_mv08: equ 0x8003E8DC
pl_mv09_pad: equ 0x8003EC60
pl_mv09: equ 0x8003EC70
pl_mv0a_pad: equ 0x8003F0FC
pl_mv0a: equ 0x8003F174
pl_mv0b_pad: equ 0x8003F420
pl_mv0b: equ 0x8003F428
Pl_damage: equ 0x8003F600
pl_dm00: equ 0x8003F658
pl_dm01: equ 0x8003F778
pl_dm02: equ 0x8003F8E4
pl_dm03: equ 0x8003FC3C
Pl_die: equ 0x8003FEE4
pl_die00: equ 0x8003FF3C
Pl_Em_damage: equ 0x8004006C
Pl_Em_die: equ 0x800400D0
Pl_dead: equ 0x80040134
Pl_life_down: equ 0x800401D4
Pl_life_up: equ 0x800402F4
Pl_weapon_ch: equ 0x800408C8
Non_init: equ 0x80040C40
Plw02_init: equ 0x80040C48
Plw09_init: equ 0x80040CF4
Plw0c_init: equ 0x80040D68
Plw0f_init: equ 0x80040EDC
Plw12_init: equ 0x80040F5C
Weapon_cls: equ 0x80041060
Init_W_Tool: equ 0x80041088
W_Tool: equ 0x80041090
init_Weapon_at: equ 0x80041098
Weapon_at_ck: equ 0x800410CC
Set_MinMax: equ 0x80041B20
Attack_r_ck0: equ 0x80041CE4
Attack_r_ck1: equ 0x80041EF8
Em_ck: equ 0x80042144
Hand_ck: equ 0x80042368
Mag_set: equ 0x80042470
Mag_down: equ 0x80042644
G_rot_st: equ 0x800428A0
G_rot: equ 0x800428CC
Gat_lp_st: equ 0x8004297C
Gat_rot: equ 0x800429C0
Pl_water: equ 0x80042AAC
pl_mv05_pad: equ 0x80042C20
pl_mv05_w0: equ 0x80042C28
pl_mv05_w0_t2: equ 0x80042C64
pl_mv05_w0_t6: equ 0x800431F8
pl_mv05_w1: equ 0x80043230
pl_mv05_w1_t0: equ 0x8004326C
pl_mv05_w1_t1: equ 0x8004362C
pl_mv05_w1_t2: equ 0x80043908
pl_mv05: equ 0x80043DF8
pl_w01_t2_init: equ 0x80043ECC
pl_w02_t2_init: equ 0x80043ED4
pl_w03_t2_init: equ 0x80043EFC
pl_w04_t2_init: equ 0x80043F24
pl_w05_t2_init: equ 0x80043F2C
pl_w06_t2_init: equ 0x80043F54
pl_w07_t2_init: equ 0x80043F7C
pl_w08_t2_init: equ 0x80043FA4
pl_w09_t2_init: equ 0x80043FCC
pl_w0a_t2_init: equ 0x80043FF4
pl_w0b_t2_init: equ 0x8004401C
pl_w0c_t2_init: equ 0x80044044
pl_w0d_t2_init: equ 0x800440CC
pl_w0e_t2_init: equ 0x800440F4
pl_w0f_t2_init: equ 0x800440FC
pl_w10_t2_init: equ 0x80044104
pl_w11_t2_init: equ 0x8004410C
pl_w12_t2_init: equ 0x80044134
pl_w01_t2_move: equ 0x8004413C
pl_w02_t2_move: equ 0x8004418C
pl_w03_t2_move: equ 0x8004429C
pl_w04_t2_move: equ 0x800443AC
pl_w05_t2_move: equ 0x800444E0
pl_w06_t2_move: equ 0x800445EC
pl_w07_t2_move: equ 0x80044730
pl_w08_t2_move: equ 0x80044908
pl_w09_t2_move: equ 0x80044B44
pl_w0a_t2_move: equ 0x80044F44
pl_w0b_t2_move: equ 0x80045090
pl_w0c_t2_move: equ 0x800451DC
pl_w0d_t2_move: equ 0x8004522C
pl_w0e_t2_move: equ 0x8004534C
pl_w0f_t2_move: equ 0x80045354
pl_w10_t2_move: equ 0x800454A0
pl_w11_t2_move: equ 0x80045588
pl_w12_t2_move: equ 0x80045648
pl_mv05_w1_t3: equ 0x80045850
pl_mv05_w1_t4: equ 0x800459E4
pl_mv05_w1_t5: equ 0x80045B38
pl_mv05_sub: equ 0x80045C10
pl_bow_init: equ 0x80045E78
pl_bow_clr: equ 0x800460AC
Bow_Lim_dir_ck: equ 0x8004618C
pl_bow: equ 0x80046304
Goto_pro: equ 0x80046F44
Bow_3D: equ 0x80046F98
Rot_3D: equ 0x80047030
Pos_em_at_ck: equ 0x800470C0
Pos_pl_at_ck: equ 0x80047664
Bow_goto_parts_no: equ 0x80047858
pl_mv05_w2: equ 0x8004799C
pl_mv05_w2_t1: equ 0x800479D8
pl_mv05_w2_t2: equ 0x80047C6C
pl_mv05_w2_t4: equ 0x800481CC
pl_mv05_w3: equ 0x800482D8
pl_mv05_w3_t2: equ 0x80048314
pl_mv05_w4: equ 0x8004879C
pl_mv05_w4_t2: equ 0x800487D8
pl_mv05_w5: equ 0x80048B50
pl_mv05_w5_t2: equ 0x80048B8C
Poly_eff2_init: equ 0x80048F24
Move_poly_eff2: equ 0x80048FFC
Sort_poly_eff2: equ 0x800493A0
Poly_eff_init: equ 0x80049644
Set_poly_eff: equ 0x800496B8
Sort_poly_eff: equ 0x800498F4
Psp_init0: equ 0x80049A9C
Psp_init1: equ 0x80049AD0
Psp_set: equ 0x80049B1C
Psp_trans: equ 0x80049CA8
Psp_ctr: equ 0x80049DF0
Set_room: equ 0x80049E48
Set_stage: equ 0x8004A3C0
Replace_rdt: equ 0x8004A414
Em_init_move: equ 0x8004A694
Root_ck: equ 0x8004A808
Rnd_area: equ 0x8004AA50
Guide_check: equ 0x8004AAB8
kara_rootck2: equ 0x8004AB60
Sa_dat_set: equ 0x8004B3B8
Sa_parts_mod: equ 0x8004B434
Sa_parts_allmv2: equ 0x8004B734
Sa_parts_allmv: equ 0x8004BAF0
Sa_parts_offset_allmv: equ 0x8004BE28
Sca_get_area: equ 0x8004C198
Sca_ck_hit: equ 0x8004C1BC
Sca_ck_hit_om: equ 0x8004C658
Sca_hit_box2: equ 0x8004C858
Sca_hit_box: equ 0x8004C900
Sca_hosei_box: equ 0x8004CA68
Sca_hit_naname_a: equ 0x8004CBD0
Sca_ck_naname_a: equ 0x8004CFC8
Sca_hit_naname_b: equ 0x8004D048
Sca_ck_naname_b: equ 0x8004D484
Sca_hit_naname_c: equ 0x8004D508
Sca_ck_naname_c: equ 0x8004D940
Sca_hit_naname_d: equ 0x8004D9B4
Sca_ck_naname_d: equ 0x8004DDE8
Sca_hit_hishi: equ 0x8004DE64
Sca_ck_hishi: equ 0x8004EA14
Sca_hit_circle: equ 0x8004EC50
Sca_ck_circle: equ 0x8004ED84
Sca_hit_koban_x: equ 0x8004EDF0
Sca_ck_koban_x: equ 0x8004EF0C
Sca_hit_koban_z: equ 0x8004F044
Sca_ck_koban_z: equ 0x8004F17C
Sca_hit_slope: equ 0x8004F2AC
Sca_hit_stairs: equ 0x8004F49C
Sca_hit_curve: equ 0x8004F6F8
Sca_get_slope_high: equ 0x8004F8B8
Sca_get_stairs_high: equ 0x8004FA28
Sca_get_curve_high: equ 0x8004FB38
Sca_get_ground: equ 0x8004FBA0
Sca_get_dir: equ 0x80050110
Sca_get_dir_super: equ 0x800501BC
Sca_get_dir_super_tmp: equ 0x800503BC
Get_axis: equ 0x80050454
Get_axis2: equ 0x800504DC
Sca_get_pos: equ 0x8005057C
Sca_get_pos_super: equ 0x800505FC
Sca_get_pos_super_tmp: equ 0x8005075C
Sca_ck_line: equ 0x80050858
Sca_get_high: equ 0x80050F80
Sca_get_low: equ 0x80050FC8
Sca_search: equ 0x80050FF4
Sce_at_check: equ 0x80051088
Nothing: equ 0x800514EC
Sce_Door: equ 0x80051514
Key_lost: equ 0x80051718
Sce_Item: equ 0x80051884
Sce_Normal: equ 0x80051940
Sce_Message: equ 0x80051948
Sce_Event: equ 0x80051980
Sce_Flg_chg: equ 0x800519C0
Sce_Water: equ 0x80051A2C
Sce_Move: equ 0x80051A48
Sce_Save: equ 0x80051AB0
Save_entrance: equ 0x80051B04
Sce_Itembox: equ 0x80051C20
Item_box_entrance: equ 0x80051C64
Sce_Damage: equ 0x80051E74
Sce_Status: equ 0x80052004
Sce_Hikidashi: equ 0x80052044
Hikidashi_entrance: equ 0x800522CC
Sce_Windows: equ 0x80052620
Sce_at: equ 0x8005264C
Water_ck: equ 0x800527B4
Floor_check: equ 0x800528E8
Sce_test_init: equ 0x800529B4
Em_kind_search: equ 0x80052AF4
Sce_se_set: equ 0x80052B38
Sce_rnd_set: equ 0x80052CA0
Sce_model_init: equ 0x80052D14
Sce_work_clr: equ 0x80052E20
Sce_work_clr_at: equ 0x80052E7C
Sce_work_clr_set: equ 0x80052F3C
Sce_aot_init: equ 0x800530C0
Event_init: equ 0x800530EC
Event_exec: equ 0x80053138
Sce_col_chg_init: equ 0x80053244
Sce_mirror_init: equ 0x800532D8
Sce_kirakira_set: equ 0x80053394
Sce_scheduler_set: equ 0x80053528
Sce_scheduler: equ 0x80053644
Sce_scheduler_main: equ 0x800536C4
Break_point: equ 0x800537CC
Nop: equ 0x800537E4
Evt_end: equ 0x800537FC
Evt_next: equ 0x80053860
Evt_chain: equ 0x80053878
Evt_exec: equ 0x800538A4
Evt_kill: equ 0x800538DC
Ifel_ck: equ 0x80053924
Else_ck: equ 0x80053964
Endif: equ 0x800539A0
Sleep: equ 0x800539DC
Sleeping: equ 0x80053A24
Wsleep: equ 0x80053A8C
Wsleeping: equ 0x80053AC0
For: equ 0x80053B1C
For2: equ 0x80053BD4
Next: equ 0x80053CBC
While: equ 0x80053D3C
Ewhile: equ 0x80053E0C
Do: equ 0x80053E50
Edwhile: equ 0x80053EC4
While_main: equ 0x80053F50
Switch: equ 0x80054020
Case: equ 0x800540F8
Default: equ 0x80054110
Eswitch: equ 0x80054128
Goto: equ 0x8005415C
Gosub: equ 0x800541A8
Return: equ 0x80054210
Break: equ 0x80054268
Work_copy: equ 0x800542B4
Rbj_reset: equ 0x80054310
Ck: equ 0x80054354
Set: equ 0x800543B4
Cmp: equ 0x80054474
Save: equ 0x8005451C
Copy: equ 0x8005454C
Calc: equ 0x8005458C
Calc2: equ 0x800545D8
Calc_branch: equ 0x80054634
Sce_rnd: equ 0x80054760
Cut_chg: equ 0x8005478C
Cut_old: equ 0x8005481C
Cut_chg_main: equ 0x80054884
Cut_auto: equ 0x800548C8
Cut_replace: equ 0x80054930
Cut_be_set: equ 0x80054A14
Message_on: equ 0x80054A8C
Aot_set: equ 0x80054AF4
Aot_set_4p: equ 0x80054B60
Door_aot_set: equ 0x80054BE4
Door_aot_set_4p: equ 0x80054C50
Item_aot_set: equ 0x80054CD4
Item_aot_set_4p: equ 0x80055008
Aot_reset: equ 0x80055154
Aot_on: equ 0x800551C8
Obj_model_set: equ 0x80055260
Super_set: equ 0x8005550C
Super_on: equ 0x80055680
Super_reset: equ 0x800558B0
Work_set: equ 0x80055904
Parts_set: equ 0x800559D0
Speed_set: equ 0x80055A84
Add_speed: equ 0x80055AB0
Add_aspeed: equ 0x80055B2C
Pos_set: equ 0x80055BA0
Dir_set: equ 0x80055BD0
Member_set: equ 0x80055C00
Member_set2: equ 0x80055C50
Member_set_branch: equ 0x80055CB0
Member_copy: equ 0x80055E38
Member_cmp: equ 0x80055E8C
Load_member_branch: equ 0x80055F50
Member_calc: equ 0x80056188
Member_calc2: equ 0x800561F4
Load_member_addr_branch: equ 0x80056264
Dir_ck: equ 0x800563E8
Se_on: equ 0x80056428
Sca_id_set: equ 0x8005655C
Sce_espr_on: equ 0x800565A4
Sce_espr_on2: equ 0x80056644
Sce_espr3d_on: equ 0x800566F0
Sce_espr3d_on2: equ 0x800567B4
Sce_espr_kill: equ 0x80056884
Sce_espr_kill2: equ 0x800568E8
Sce_espr_control: equ 0x800569D4
Get_matrix: equ 0x80056A38
Plc_motion: equ 0x80056B8C
Plc_dest: equ 0x80056BD8
Plc_gun: equ 0x80056DC0
Plc_gun_eff: equ 0x80056DF8
Plc_neck: equ 0x80056E5C
Plc_ret: equ 0x80056F9C
Plc_stop: equ 0x80056FF0
Plc_flg: equ 0x80057038
Plc_rot: equ 0x800570BC
Plc_cnt: equ 0x80057120
Sce_em_set: equ 0x8005714C
Sce_key_ck: equ 0x80057DA8
Sce_trg_ck: equ 0x80057DE4
Sce_bgm_control: equ 0x80057E20
Sce_bgmtbl_set: equ 0x80057E98
Sce_fade_set: equ 0x80057EF0
Sce_fade_adjust: equ 0x80057FD8
Xa_on: equ 0x80058028
Xa_vol: equ 0x80058090
Se_vol: equ 0x800580CC
Sce_shake_on: equ 0x80058164
Sce_line_start: equ 0x80058214
Sce_line_main: equ 0x80058260
Sce_line_end: equ 0x800582B8
Mizu_div_set: equ 0x800582F0
Keep_Item_ck: equ 0x800584F0
Sce_Item_lost: equ 0x800585E4
Sce_Item_lost2: equ 0x80058660
Weapon_chg: equ 0x80058704
Sce_Item_get: equ 0x800587B8
Kage_set: equ 0x80058898
Light_pos_set: equ 0x800589D4
Light_kido_set: equ 0x80058A8C
Light_color_set: equ 0x80058AD8
Light_pos_set2: equ 0x80058B40
Light_kido_set2: equ 0x80058BFC
Light_color_set2: equ 0x80058C4C
Sce_scr_move: equ 0x80058CB8
Flr_set: equ 0x80058CE4
Movie_on: equ 0x80058D64
Splc_ret: equ 0x80058DAC
Splc_sce: equ 0x80058E48
Evt_next2: equ 0x80058EB0
Mirror_set: equ 0x80058EF8
Sce_parts_bomb: equ 0x80058F78
Sce_parts_down: equ 0x80059030
Col_chg_set: equ 0x800590E0
Poison_ck: equ 0x800592F8
Poison_clr: equ 0x80059318
Vib_set0: equ 0x80059348
Vib_set1: equ 0x80059394
Vib_fade_set: equ 0x800593E4
Snd_sys_init: equ 0x80059438
FUN_800594c8: equ 0x800594c8
Snd_sys_init2: equ 0x80059514
Snd_sys_Allvoff: equ 0x80059634
Snd_sys_init_sub: equ 0x80059654
Snd_sys_init_sub2: equ 0x800598A8
Snd_sys_start: equ 0x8005990C
Snd_sys_stereo: equ 0x8005998C
Snd_sys_core_set: equ 0x80059A00
Snd_sys_arms_set: equ 0x80059C74
Snd_sys_room_set: equ 0x80059E54
Snd_sys_enem_set: equ 0x8005A09C
Snd_sys_pset: equ 0x8005A338
Snd_bgm_data: equ 0x8005A414
Snd_bgm_set: equ 0x8005A444
Snd_bgm_ck: equ 0x8005A714
Snd_bgm_play_ck: equ 0x8005A888
Snd_bgm_main: equ 0x8005A97C
Snd_bgm_sub: equ 0x8005AE50
Snd_bgm_fade_ON: equ 0x8005B2E4
Snd_bgm_fade: equ 0x8005B3B0
Snd_bgm_ctr: equ 0x8005B6F0
Snd_bgm_tbl_set: equ 0x8005B9F4
Snd_se_stad: equ 0x8005BA28
Snd_se_enem: equ 0x8005BD6C
Snd_se_walk: equ 0x8005C040
Snd_se_call: equ 0x8005C5E4
Snd_se_pri_ck: equ 0x8005C92C
Snd_se_3D: equ 0x8005C970
Snd_se_dir_ck: equ 0x8005CDA4
Spl: equ 0x8005CFC8
Spl_mv40: equ 0x8005D0BC
Spl_mv42: equ 0x8005D10C
Spl_mv41: equ 0x8005D12C
Spl_mv44: equ 0x8005D1D0
Spl_mv45: equ 0x8005D238
Spl_mv47: equ 0x8005D27C
Spl_mv49: equ 0x8005D29C
Spl_mv48: equ 0x8005D2BC
Spl_mv4a: equ 0x8005D2DC
Spl_mv4b: equ 0x8005D30C
Spl_mv50: equ 0x8005D314
Spl_mv51: equ 0x8005D3A4
Spl_mv00: equ 0x8005D3C4
Spl_Init: equ 0x8005D3CC
Spl_in40: equ 0x8005D85C
Spl_in42: equ 0x8005DA3C
Spl_in41: equ 0x8005DA94
Spl_in44: equ 0x8005DC74
Spl_in45: equ 0x8005DDDC
Spl_in47: equ 0x8005DED8
Spl_in48: equ 0x8005DF30
Spl_in4a: equ 0x8005DF38
Spl_in4b: equ 0x8005E1C0
Spl_in50: equ 0x8005E1F8
Spl_in51: equ 0x8005E2A0
Spl_in00: equ 0x8005E358
Spl_Damage: equ 0x8005E360
Spl_Die: equ 0x8005E39C
Spl_Dead: equ 0x8005E3D8
Spl_dead00: equ 0x8005E414
Spl_set: equ 0x8005E41C
Spl_chenge00: equ 0x8005E50C
Spl_chenge01: equ 0x8005E6F0
Spl_kizu00: equ 0x8005EAAC
Spl_chenge02: equ 0x8005EB80
Spl_chenge04: equ 0x8005ECFC
Spl_chenge05: equ 0x8005F044
Spl_chenge06: equ 0x8005F354
Spl_chenge07: equ 0x8005F634
Spl_chenge08: equ 0x8005FBB4
Spl_chenge09: equ 0x8005FE6C
Spl_chenge10: equ 0x800600B8
Spl_Root_ck_sys: equ 0x80060374
Spl_Auto: equ 0x800605AC
Aida: equ 0x80060648
Aida_move: equ 0x80060650
Aida_Move_type00: equ 0x80060750
Aida_Move_type01: equ 0x800607D4
Aida_Move_type02: equ 0x80060858
Aida_Move_type03: equ 0x800608DC
Aida_Move_type04: equ 0x80060960
Aida_Move_type05: equ 0x800609E4
Aida_Move_type06: equ 0x80060A68
Aida_Move_type07: equ 0x80060AEC
Aida_Move_type08: equ 0x80060B70
Aida_Move_type09: equ 0x80060BF4
Aida_Move_type0a: equ 0x80060C78
Aida_em10_at00_pl: equ 0x80060CFC
Aida_em10_at00_spl: equ 0x80060E08
Aida_em25_at00_pl: equ 0x80060EE4
Aida_em25_at00_spl: equ 0x80060FEC
Aida_em26_at00_pl: equ 0x80061140
Aida_em26_at00_spl: equ 0x80061148
Aida_mv00_br: equ 0x80061150
Aida_mv00_br_1: equ 0x800613C0
Aida_mv00: equ 0x800614F8
Aida_em10_at01: equ 0x80061594
Aida_em25_at01: equ 0x80061654
Aida_em26_at01: equ 0x8006170C
Aida_mv01_br: equ 0x80061714
Aida_mv01_br_1: equ 0x800619E4
Aida_mv01: equ 0x80061BBC
Aida_mv02_br: equ 0x80061D90
Aida_mv02_br_1: equ 0x80061F68
Aida_mv02: equ 0x800620EC
Aida_mv03_br: equ 0x80062248
Aida_mv03: equ 0x80062318
Aida_mv04_br: equ 0x80062490
Aida_mv04: equ 0x800624F8
Aida_mv05_br: equ 0x800625DC
Aida_mv05: equ 0x80062618
Aida_mv05_w1: equ 0x80062678
Aida_mv05_w1_t0_br: equ 0x800626B4
Aida_mv05_w1_t0: equ 0x800626BC
Aida_em10_at05: equ 0x800627DC
Aida_mv05_w1_t1_br: equ 0x800628C4
Aida_mv05_w1_t1: equ 0x80062954
Aida_mv05_w1_t2_br: equ 0x80062A20
Aida_mv05_w1_t2: equ 0x80062A28
Aida_mv05_w1_t3_br: equ 0x80062C44
Aida_mv05_w1_t3: equ 0x80062C4C
Aida_mv05_w1_t4_br: equ 0x80062CC0
Aida_mv05_w1_t4: equ 0x80062CC8
Aida_mv05_w1_t5_br: equ 0x80062D24
Aida_mv05_w1_t5: equ 0x80062D2C
Aida_mv06_br: equ 0x80062DC4
Aida_mv06: equ 0x80062DCC
Aida_mv07_br: equ 0x80062E90
Aida_mv07: equ 0x80062E98
Aida_mv08_br: equ 0x80063164
Aida_mv08: equ 0x8006316C
Aida_mv09_br: equ 0x8006351C
Aida_mv09: equ 0x80063524
Aida_mv0a_br: equ 0x800638C0
Aida_mv0a: equ 0x800638C8
Aida_mv0b_br: equ 0x800638D0
Aida_mv0b_br_1: equ 0x80063930
Aida_mv0b: equ 0x80063998
Aida_mv0c_br: equ 0x800639A0
Aida_mv0c_br_1: equ 0x80063ABC
Aida_mv0d_br: equ 0x80063B94
Sherry_move: equ 0x80063BEC
Sherry_Move_type00: equ 0x80063CEC
Sherry_Move_type01: equ 0x80063D8C
Sherry_Move_type02: equ 0x80063E2C
Sherry_Move_type03: equ 0x80063ECC
Sherry_Move_type04: equ 0x80063F6C
Sherry_Move_type05: equ 0x8006400C
Sherry_Move_type06: equ 0x800640AC
Sherry_Move_type07: equ 0x8006414C
Sherry_Move_type08: equ 0x800641EC
Sherry_Move_type09: equ 0x8006428C
Sherry_Move_type0a: equ 0x8006432C
Sherry_mv00_br: equ 0x800643CC
Sherry_mv00: equ 0x800645D8
Sherry_mv01_br: equ 0x80064814
Sherry_mv02_br: equ 0x80064ACC
Sherry_mv06_br: equ 0x80064D90
Sherry_mv0b_br: equ 0x80064E5C
Sherry_mv0c_br: equ 0x80064EBC
Spl_dm00: equ 0x80064FA8
Spl_dm01: equ 0x800650A8
Spl_die00: equ 0x800651F0
Aida_before: equ 0x800652FC
Aida_after: equ 0x8006531C
Spl_soba_pos_set: equ 0x80065324
Spl_enemy_ck: equ 0x80065518
Spl_em_pos_ck: equ 0x80065890
Spl_em_cdir_ck: equ 0x80065A0C
Spl_pllock_get: equ 0x80065B18
GsGetWorkBase: equ 0x80065B8C
Spl_life_down: equ 0x80065B9C
Spl_Scenario: equ 0x80065C88
Spl_sce00: equ 0x80065DD0
Spl_sce01: equ 0x80065DF8
Spl_sce02: equ 0x80065E18
Spl_sce03: equ 0x80065E40
Spl_sce04: equ 0x80065E68
Spl_sce05: equ 0x80065FB8
Spl_sce06: equ 0x80066138
Spl_sce07: equ 0x800661C0
Spl_sce08: equ 0x8006629C
Spl_sce09: equ 0x8006637C
Spl_sce0a: equ 0x80066450
Spl_sce0b: equ 0x80066478
Spl_sce0c: equ 0x80066498
Spl_sce0d: equ 0x800664C0
Spl_sce0e: equ 0x800664E8
Spl_sce0f: equ 0x800664F0
Spl_sce10: equ 0x800664F8
Spl_sce11: equ 0x80066500
Spl_sce12: equ 0x80066508
Spl_sce13: equ 0x8006667C
Spl_sce14: equ 0x80066684
Spl_sce15: equ 0x8006668C
Spl_sce16: equ 0x80066760
Spl_sce17: equ 0x80066768
Spl_sce18: equ 0x80066770
Spl_sce20: equ 0x80066778
Spl_sce_mv00: equ 0x800669B0
Spl_sce_mv01: equ 0x80066AFC
Spl_sce_mv02: equ 0x80066BCC
Spl_sce_mv03: equ 0x80066D24
Spl_sce_mv04: equ 0x80066DEC
Spl_Sp_Move: equ 0x80067004
Spl_sp40_00: equ 0x8006704C
Spl_sp44_00: equ 0x80067984
Status_init: equ 0x80068068
Status_init_m: equ 0x80068484
Status: equ 0x800689BC
St_exit: equ 0x80068CD4
St_fade_out_set: equ 0x80068F08
St_fade_out_wait: equ 0x80068F40
St_chenge_pl: equ 0x80068F9C
pl_tim_load: equ 0x80069210
St_file_set: equ 0x800692DC
St_room_set: equ 0x8006931C
St_disp_name: equ 0x800693D0
Set_iwork: equ 0x8006947C
Set_iwork_num: equ 0x800694B8
Check_pl_life: equ 0x80069538
Check_item_space: equ 0x80069590
Check_item_mix: equ 0x800695B0
Search_item: equ 0x80069668
Search_item_id: equ 0x800696CC
Sort_item: equ 0x80069714
Shift_item: equ 0x800698B4
Set_item: equ 0x80069ADC
Pix_trans: equ 0x80069BB4
Pix_trans_pl: equ 0x80069C40
Pix_move: equ 0x80069D88
Pix_clear: equ 0x80069E54
St_pltex_operation: equ 0x80069EEC
Tama_ck_i: equ 0x80069F54
Tama_decrease_i: equ 0x8006A0CC
Tama_reload_ck: equ 0x8006A23C
Tama_reload: equ 0x8006A2B4
Check_cursol_distance: equ 0x8006A38C
St_init00: equ 0x8006A574
St_main00: equ 0x8006A774
St_menu0_select: equ 0x8006A7F0
St_menu0_item: equ 0x8006A994
St_com_use_equip: equ 0x8006AFFC
St_com_mix: equ 0x8006B358
St_com_inspect: equ 0x8006C2B0
St_menu0_file: equ 0x8006C6E4
file_moji_load: equ 0x8006D444
move_file_tag: equ 0x8006D550
St_menu0_map: equ 0x8006D650
St_init_disp_map: equ 0x8006DEA0
St_disp_map: equ 0x8006E120
Check_map_no: equ 0x8006E7F0
Check_room_no: equ 0x8006EAE8
St_menu1_map: equ 0x8006ECB8
St_init03: equ 0x8006EFD8
St_main03: equ 0x8006F164
St_init04: equ 0x8006F6A8
St_main04: equ 0x8006F8B4
St_init01: equ 0x8006F900
St_main01: equ 0x8006FB64
St_select_menu_m: equ 0x8006FBD4
St_select_item_m: equ 0x8006FC58
Exchange_item: equ 0x800703B8
St_init_itembox: equ 0x80070E58
St_disp_itembox: equ 0x800710DC
St_init02: equ 0x80071BA0
St_main02: equ 0x80071E14
St_get_check: equ 0x80071EB4
St_get_item: equ 0x80072050
St_disp_file2: equ 0x800724B4
St_get_file: equ 0x8007274C
St_init_disp_num: equ 0x80072C1C
St_disp_num: equ 0x80072C6C
print_num: equ 0x8007300C
St_init_disp_cursol0: equ 0x80073250
St_disp_cursol0: equ 0x80073350
St_init_disp_cursol1: equ 0x80073578
St_disp_cursol1: equ 0x80073674
St_init_disp_face: equ 0x80073880
St_disp_face: equ 0x80073AB0
St_init_disp_message: equ 0x80073DA0
St_disp_message: equ 0x80073ED0
St_init_disp_frame: equ 0x80074014
St_disp_frame: equ 0x80074160
St_init_disp_menu0: equ 0x80074300
St_disp_menu0: equ 0x800743F8
St_init_disp_menu1: equ 0x80074610
St_disp_menu1: equ 0x80074888
St_init_disp_itemlist: equ 0x80074A94
St_disp_itemlist: equ 0x80074BB0
St_init_disp_equip: equ 0x80074E80
St_disp_equip: equ 0x80074F4C
St_init_disp_wall: equ 0x800751EC
St_disp_wall: equ 0x8007526C
St_init_disp_ECG: equ 0x80075360
St_disp_ECG: equ 0x800754AC
St_init_disp_itp: equ 0x80075A00
St_disp_itp: equ 0x80075C28
St_init_disp_filesel: equ 0x80075DC4
St_disp_filesel: equ 0x80075E98
St_init_disp_file: equ 0x80075FD0
St_disp_file: equ 0x800761B8
ST_Om_trans: equ 0x80076498
model_disp: equ 0x80076640
Vram_clr: equ 0x800769C4
Memcpy: equ 0x80076A00
Memclr: equ 0x80076A28
Mapping_tim: equ 0x80076A40
Mapping_tmd: equ 0x80076B60
Set_view: equ 0x80076CB0
Set_light: equ 0x80076F88
Set_Light_data: equ 0x80077200
Flg_on: equ 0x8007730C
Flg_off: equ 0x80077334
Flg_ck: equ 0x80077360
Enemy_st_view: equ 0x80077384
Rot_vector_super: equ 0x800773EC
Rot_add_matrix: equ 0x8007746C
Set_front_pos: equ 0x80077600
SetSpadStack: equ 0x8007769C
ResetSpadStack: equ 0x800776D8
SetSpadStack2: equ 0x80077708
ResetSpadStack2: equ 0x8007774C
Get_work: equ 0x8007777C
Free_work: equ 0x800777F4
Prim_trans: equ 0x80077874
Trans_pointer_set: equ 0x800778F8
Eff_sprt_trans: equ 0x80077924
Esp_trans_main: equ 0x80077ED0
Esp_trans_3d: equ 0x80078174
Trans_work_init: equ 0x800783B4
__main: equ 0x80078400
start: equ 0x80078408
stup1: equ 0x8007842C
stup0: equ 0x800784A8
SpuClearReverbWorkArea: equ 0x800784C4
_spu_init: equ 0x80078660
_spu_writeByIO: equ 0x800788F4
_spu_FiDMA: equ 0x80078AC0
_spu_r_: equ 0x80078B80
_spu_t: equ 0x80078C2C
_spu_write: equ 0x80078EBC
_spu_read: equ 0x80078F44
_spu_FsetRXX: equ 0x80078FAC
_spu_FsetRXXa: equ 0x80078FF4
_spu_FgetRXXa: equ 0x80079098
_spu_FsetPCR: equ 0x800790D4
_spu_FsetDelayW: equ 0x80079134
_spu_FsetDelayR: equ 0x80079160
_spu_FwaitFs: equ 0x8007918C
_SpuInit: equ 0x800791F4
SpuStart: equ 0x800792EC
_SpuDataCallback: equ 0x80079368
_SpuIsInAllocateArea: equ 0x8007938C
_SpuIsInAllocateArea_: equ 0x8007940C
SpuGetKeyStatus: equ 0x80079694
SpuSetTransferMode: equ 0x80079728
_SsClose: equ 0x80079E34
SsSeqClose: equ 0x80079FB0
SsSepClose: equ 0x80079FD4
_SsSndSetDecres: equ 0x80079FF8
SsSeqSetDecrescendo_0: equ 0x8007A120
SsSeqSetDecrescendo: equ 0x8007A188
SsEnd: equ 0x8007A280
_SsInit: equ 0x8007A344
SsInit: equ 0x8007A42C
SpuInit: equ 0x8007A45C
SsSetLoop: equ 0x8007A47C
SsIsEos: equ 0x8007A4BC
SsSeqOpen: equ 0x8007A4FC
_SsContBankChange: equ 0x8007A81C
_SsContDataEntry: equ 0x8007A894
_SsContMainVol: equ 0x8007ACBC
_SsContPanpot: equ 0x8007AD8C
_SsContExpression: equ 0x8007AE54
_SsContDamper: equ 0x8007AF3C
SsSetTempo: equ 0x8007AF50
_SsContExternal: equ 0x8007AFE4
_SsContNrpn1: equ 0x8007B06C
_SsContNrpn2: equ 0x8007B19C
_SsContRpn1: equ 0x8007B2D0
_SsContRpn2: equ 0x8007B340
_SsContResetAll: equ 0x8007B3B0
_SsSetNrpnVabAttr0: equ 0x8007B46C
_SsSetNrpnVabAttr1: equ 0x8007B4FC
_SsSetNrpnVabAttr2: equ 0x8007B5B8
_SsSetNrpnVabAttr3: equ 0x8007B648
_SsSetNrpnVabAttr4: equ 0x8007B6D8
_SsUtResolveADSR: equ 0x8007B78C
_SsUtBuildADSR: equ 0x8007B7E8
_SsSetNrpnVabAttr5: equ 0x8007B888
_SsSetNrpnVabAttr6: equ 0x8007B940
_SsSetNrpnVabAttr7: equ 0x8007B9F0
_SsSetNrpnVabAttr8: equ 0x8007BAA0
_SsSetNrpnVabAttr9: equ 0x8007BB54
_SsSetNrpnVabAttr10: equ 0x8007BC0C
_SsSetNrpnVabAttr11: equ 0x8007BCC0
_SsSetNrpnVabAttr12: equ 0x8007BD68
_SsSetNrpnVabAttr13: equ 0x8007BE44
_SsSetNrpnVabAttr14: equ 0x8007BEE4
_SsSetNrpnVabAttr15: equ 0x8007BF84
_SsSetNrpnVabAttr16: equ 0x8007BFA8
_SsSetNrpnVabAttr17: equ 0x8007BFD0
_SsSetNrpnVabAttr18: equ 0x8007BFF4
_SsSetNrpnVabAttr19: equ 0x8007C018
_SsSetPitchBend: equ 0x8007C03C
_SsSetControlChange: equ 0x8007C0EC
_SsGetMetaEvent: equ 0x8007C324
_SsNoteOn: equ 0x8007C4F4
_SsSetProgramChange: equ 0x8007C5C8
_SsReadDeltaValue: equ 0x8007C638
_SsInitSoundSeq: equ 0x8007C6E8
_SsSndSetPauseMode: equ 0x8007CA34
SsSeqPause: equ 0x8007CB04
SsSepPause: equ 0x8007CB2C
SsSeqPlay: equ 0x8007CB58
SsSepPlay: equ 0x8007CB90
SsQuit: equ 0x8007CBC8
SpuQuit: equ 0x8007CBE8
_SsSndSetReplayMode: equ 0x8007CC64
SsSeqReplay: equ 0x8007CD00
SsSepReplay: equ 0x8007CD28
Snd_SetPlayMode: equ 0x8007CD54
SsSetSerialAttr: equ 0x8007CE70
SpuSetCommonAttr: equ 0x8007CF04
SsSetMVol: equ 0x8007D298
SsSetRVol: equ 0x8007D2E8
SpuSetReverbDepth: equ 0x8007D370
_SsStart: equ 0x8007D3E8
SsStart: equ 0x8007D650
SsStart2: equ 0x8007D670
_SsTrapIntrVSync: equ 0x8007D690
_SsSeqCalledTbyT_1per2: equ 0x8007D6D0
SsSeqCalledTbyT: equ 0x8007D720
_SsSndCrescendo: equ 0x8007D994
_SsSndDecrescendo: equ 0x8007DCB4
_SsSndPause: equ 0x8007E060
_SsSndPlay: equ 0x8007E0FC
_SsSeqPlay: equ 0x8007E128
_SsSeqGetEof: equ 0x8007E230
_SsGetSeqData: equ 0x8007E474
_SsSndNextSep: equ 0x8007E818
_SsSndReplay: equ 0x8007E914
_SsSndStop: equ 0x8007E974
SsSeqStop: equ 0x8007EAF8
SsSepStop: equ 0x8007EB20
SsSetSerialVol: equ 0x8007EB4C
SsSetTableSize: equ 0x8007EC48
SsSetTickMode: equ 0x8007EE20
_SsSndSetVol: equ 0x8007EF8C
SsSeqSetVol: equ 0x8007F018
SsSepSetVol: equ 0x8007F078
SsSeqGetVol: equ 0x8007F104
_SsSndTempo: equ 0x8007F138
SsUtAllKeyOff: equ 0x8007F358
SsUtGetProgAtr: equ 0x8007FA84
SsUtGetVagAtr: equ 0x8007FB8C
SsUtKeyOn: equ 0x8007FDC8
SsUtKeyOff: equ 0x80080164
SsUtKeyOnV: equ 0x800802B8
SsUtKeyOffV: equ 0x8008064C
SsUtSetReverbDelay: equ 0x800806C4
SpuSetReverbModeParam: equ 0x80080704
_spu_setReverbAttr: equ 0x80080BFC
SsUtSetReverbDepth: equ 0x800810CC
SsUtSetReverbType: equ 0x80081164
SsUtGetReverbType: equ 0x80081208
SpuSetReverb: equ 0x80081218
SsUtSetReverbFeedback: equ 0x800812E8
SsUtReverbOff: equ 0x80081328
SsUtReverbOn: equ 0x80081348
SsUtSetVagAtr: equ 0x80081368
SsUtGetDetVVol: equ 0x80081530
SsUtSetDetVVol: equ 0x8008156C
SsUtGetVVol: equ 0x800815D8
SsUtSetVVol: equ 0x80081688
SpuGetVoiceVolume: equ 0x80081714
_SsVmAlloc: equ 0x80081774
SpuSetNoiseVoice: equ 0x80081A00
_SpuSetAnyVoice: equ 0x80081A24
_SsVmDoAllocate: equ 0x80081CEC
_SsVmDamperOff: equ 0x80081EFC
_SsVmDamperOn: equ 0x80081F0C
_SsVmFlush: equ 0x80081F20
_SsVmInit: equ 0x8008239C
SpuInitMalloc: equ 0x800826BC
_spu_setInTransfer: equ 0x80082710
_spu_getInTransfer: equ 0x8008273C
_SsVmKeyOn: equ 0x80082754
_SsVmKeyOff: equ 0x80082CD8
_SsVmSeKeyOn: equ 0x80082E24
_SsVmSeKeyOff: equ 0x80082F10
KeyOnCheck: equ 0x80082F44
note2pitch: equ 0x80082F4C
note2pitch2: equ 0x80083010
vmNoiseOn: equ 0x8008310C
_SsVmKeyOffNow: equ 0x80083690
_SsVmKeyOnNow: equ 0x80083760
_SsVmPBVoice: equ 0x80083C2C
_SsVmPitchBend: equ 0x80083E2C
_SsVmSetProgVol: equ 0x80083F1C
_SsVmGetProgVol: equ 0x80083F90
_SsVmSetProgPan: equ 0x80083FE4
_SsVmGetProgPan: equ 0x80084058
_SsVmSetSeqVol: equ 0x800840AC
_SsVmGetSeqVol: equ 0x800845E8
_SsVmGetSeqLVol: equ 0x8008464C
_SsVmGetSeqRVol: equ 0x80084694
_SsVmSeqKeyOff: equ 0x800846DC
_SsVmSelectToneAndVag: equ 0x80084778
_SsVmSetVol: equ 0x8008482C
_SsVmVSetUp: equ 0x80084DA8
SsSetMono: equ 0x80084E6C
SsSetStereo: equ 0x80084E80
SsSetReservedVoice: equ 0x80084E90
SsVabClose: equ 0x80084EC0
SpuFree: equ 0x80084F44
_spu_gcSPU: equ 0x80084FC0
SsVabFakeBody: equ 0x800852C8
SsVabOpenHead: equ 0x80085338
SsVabOpenHeadSticky: equ 0x80085368
SsVabFakeHead: equ 0x80085398
SsVabOpenHeadWithMode: equ 0x800853C8
SpuMalloc: equ 0x800857A4
SsVabTransBody: equ 0x80085A6C
SpuWrite: equ 0x80085B2C
SpuSetTransferStartAddr: equ 0x80085B8C
SsVabTransBodyPartly: equ 0x80085BE4
SpuWritePartly: equ 0x80085D44
SsVabTransCompleted: equ 0x80085DD0
SpuIsTransferCompleted: equ 0x80085DF8
VSync: equ 0x80085EA0
v_wait: equ 0x80085FE8
ResetCallback: equ 0x80086084
InterruptCallback: equ 0x800860B4
DMACallback: equ 0x800860E4
VSyncCallback: equ 0x80086114
VSyncCallbacks: equ 0x80086148
StopCallback: equ 0x80086178
RestartCallback: equ 0x800861A8
CheckCallback: equ 0x800861D8
GetIntrMask: equ 0x800861E8
SetIntrMask: equ 0x80086200
startIntr: equ 0x8008621C
trapIntr: equ 0x800862F8
setIntr: equ 0x800864E0
stopIntr: equ 0x80086634
restartIntr: equ 0x800866E0
startIntrVSync: equ 0x80086794
trapIntrVSync: equ 0x800867EC
setIntrVSync: equ 0x80086864
startIntrDMA: equ 0x800868BC
trapIntrDMA: equ 0x8008690C
setIntrDMA: equ 0x80086A90
memclr: equ 0x80086B38
SetVideoMode: equ 0x80086B64
GsGetWorkBase_0: equ 0x80086B7C
StSetRing: equ 0x80086B8C
StClearRing: equ 0x80086BBC
StUnSetRing: equ 0x80086C1C
CdStatus: equ 0x80086CA0
CdMode: equ 0x80086CB0
CdLastCom: equ 0x80086CC0
CdLastPos: equ 0x80086CD0
CdReset: equ 0x80086CE0
CdFlush: equ 0x80086D4C
CdSetDebug: equ 0x80086D6C
CdComstr: equ 0x80086D84
CdIntstr: equ 0x80086DB8
CdSync: equ 0x80086DEC
CdReady: equ 0x80086E0C
CdSyncCallback: equ 0x80086E2C
CdReadyCallback: equ 0x80086E44
CdControl: equ 0x80086E5C
CdControlF: equ 0x80086F94
CdControlB: equ 0x800870C0
CdMix: equ 0x80087204
CdGetSector: equ 0x80087224
CdGetSector2: equ 0x80087244
CdDataCallback: equ 0x80087264
CdDataSync: equ 0x80087288
CdIntToPos: equ 0x800872AC
CdPosToInt: equ 0x800873AC
getintr: equ 0x8008742C
CD_sync: equ 0x800879B4
CD_ready: equ 0x80087C34
CD_cw: equ 0x80087F00
CD_vol: equ 0x8008831C
CD_flush: equ 0x800883A4
CD_initvol: equ 0x80088484
CD_initintr: equ 0x80088578
CD_init: equ 0x800885C8
CD_datasync: equ 0x800887B4
CD_getsector: equ 0x80088920
CD_getsector2: equ 0x80088A20
CD_set_test_parmnum: equ 0x80088B10
callback: equ 0x80088B20
StSetStream: equ 0x80088C04
StFreeRing: equ 0x80088C8C
init_ring_status: equ 0x80088D44
StGetNext: equ 0x80088D80
StSetMask: equ 0x80088E44
StCdInterrupt: equ 0x80088E64
mem2mem: equ 0x800897D4
dma_execute: equ 0x80089808
data_ready_callback: equ 0x800899C4
StGetBackloc: equ 0x80089A50
StGetBackloc_0: equ 0x80089A54
CQ_clear_queue: equ 0x80089AB4
CQ_delete_command: equ 0x80089AE4
CQ_last_queue: equ 0x80089BD4
CQ_error_flush: equ 0x80089C2C
CQ_execute: equ 0x80089DE0
CQ_sync_system: equ 0x80089E58
CQ_add_result: equ 0x8008A080
DsInit: equ 0x8008A110
DsReset: equ 0x8008A254
DsClose: equ 0x8008A360
DsCommand: equ 0x8008A380
DsPacket: equ 0x8008A5A8
DsSync: equ 0x8008A8C4
DsReady: equ 0x8008AAC4
DsFlush: equ 0x8008AB74
DsSystemStatus: equ 0x8008AC04
GsGetWorkBase_1: equ 0x8008AC54
DsStatus: equ 0x8008AC64
DsShellOpen: equ 0x8008AC84
DsLastCom: equ 0x8008ACA4
CQ_vsync_system: equ 0x8008ACC4
CQ_ready_system: equ 0x8008AD6C
DS_init: equ 0x8008AE68
DS_reset_members: equ 0x8008AF04
DS_close: equ 0x8008B014
DS_cw: equ 0x8008B058
DS_vsync_callback: equ 0x8008B0DC
DS_sync_callback: equ 0x8008B0EC
DS_ready_callback: equ 0x8008B0FC
DS_system_status: equ 0x8008B10C
DS_lastcom: equ 0x8008B124
DS_lastmode: equ 0x8008B134
DS_lastpos: equ 0x8008B144
DS_lastseek: equ 0x8008B154
DS_lastread: equ 0x8008B164
DS_status: equ 0x8008B174
DS_sync: equ 0x8008B184
DS_ready: equ 0x8008B1A8
GsGetWorkBase_2: equ 0x8008B1CC
DS_cw_root: equ 0x8008B1DC
DS_vsync_system: equ 0x8008B2FC
DS_sync_system: equ 0x8008B5EC
DS_sync_for_user: equ 0x8008B6E0
DS_sync_for_system: equ 0x8008B8D8
DS_sync_for_void: equ 0x8008BA60
DS_ready_system: equ 0x8008BB70
DS_scan_result: equ 0x8008BC3C
DS_stop: equ 0x8008BCBC
DS_restart: equ 0x8008BD1C
GsGetWorkBase_3: equ 0x8008BD30
parcpy: equ 0x8008BD40
rescpy: equ 0x8008BD88
tipDsSystem: equ 0x8008BDD0
DsMix: equ 0x8008BEBC
DsGetSector: equ 0x8008BEDC
DsGetSector2: equ 0x8008BEFC
DsDataSync: equ 0x8008BF1C
DsIntToPos: equ 0x8008BF3C
DsPosToInt: equ 0x8008C040
DsSetDebug: equ 0x8008C0C0
DsLastPos: equ 0x8008C0D8
DsControlF: equ 0x8008C130
DsControl: equ 0x8008C158
DsControlB: equ 0x8008C1C4
DsRead: equ 0x8008C230
DS_read_cbsync: equ 0x8008C340
DS_read_cbready: equ 0x8008C374
DS_read_cbdata: equ 0x8008C534
DsReadSync: equ 0x8008C628
DsReadCallback: equ 0x8008C69C
DsReadBreak: equ 0x8008C6B4
DsReadMode: equ 0x8008C730
DsRead2: equ 0x8008C74C
StCdInterrupt2: equ 0x8008C82C
DsStartReadySystem: equ 0x8008C84C
DsEndReadySystem: equ 0x8008C8D8
ER_cbready: equ 0x8008C938
ER_retry: equ 0x8008CBC4
ER_cbsync: equ 0x8008CC44
DsSyncCallback: equ 0x8008cc78
DsReadyCallback: equ 0x8008cc8c
DsStartCallback: equ 0x8008CCA0
rsin: equ 0x8008CCC4
sin_1: equ 0x8008CD00
rcos: equ 0x8008CD90
MatrixNormal_0: equ 0x8008CE30
MatrixNormal_1: equ 0x8008CF50
MatrixNormal_2: equ 0x8008D068
MatrixNormal_3: equ 0x8008D070
catan: equ 0x8008D190
InitGeom: equ 0x8008D26C
SquareRoot0: equ 0x8008D2F4
InvSquareRoot: equ 0x8008D384
VectorNormalS: equ 0x8008D410
VectorNormal: equ 0x8008D424
VectorNormalSS: equ 0x8008D450
MatrixNormal: equ 0x8008D53C
SquareRoot12: equ 0x8008D624
MulMatrix0: equ 0x8008D6C4
ApplyMatrixLV: equ 0x8008D7D4
MulMatrix: equ 0x8008D934
MulMatrix2: equ 0x8008DA44
ApplyMatrix: equ 0x8008DB54
ApplyMatrixSV: equ 0x8008DBA4
ScaleMatrix: equ 0x8008DC04
SetRotMatrix: equ 0x8008DD34
SetLightMatrix: equ 0x8008DD64
SetColorMatrix: equ 0x8008DD94
SetTransMatrix: equ 0x8008DDC4
SetBackColor: equ 0x8008DDE4
SetGeomOffset: equ 0x8008DE04
SetGeomScreen: equ 0x8008DE24
LightColor: equ 0x8008DE34
DpqColorLight: equ 0x8008DE5C
DpqColor3: equ 0x8008DE84
Intpl: equ 0x8008DEC0
Square12: equ 0x8008DEE4
Square0: equ 0x8008DF0C
AverageZ3: equ 0x8008DF34
AverageZ4: equ 0x8008DF54
OuterProduct12: equ 0x8008DF78
OuterProduct0: equ 0x8008DFD0
Lzc: equ 0x8008E028
RotTransPers: equ 0x8008E044
RotTransPers3: equ 0x8008E074
RotAverage3: equ 0x8008E0D4
RotAverage4: equ 0x8008E134
TransposeMatrix: equ 0x8008E1B4
RotMatrix: equ 0x8008E1F4
RotMatrixYXZ: equ 0x8008E484
RotMatrixX: equ 0x8008E714
RotMatrixY: equ 0x8008E8B4
RotMatrixZ: equ 0x8008EA54
DivideGT3: equ 0x8008EBF4
ReadSZfifo3: equ 0x8008EDCC
RotAverageNclip3: equ 0x8008EDEC
RCpolyGT3: equ 0x8008EE7C
RCpolyGT3A: equ 0x8008EE84
ratan2: equ 0x8008F31C
_patch_gte: equ 0x8008F49C
LoadTPage: equ 0x8008F53C
LoadClut: equ 0x8008F628
LoadClut2: equ 0x8008F690
SetDefDrawEnv: equ 0x8008F6F8
SetDefDispEnv: equ 0x8008F7B0
GetTPage: equ 0x8008F7EC
GetClut: equ 0x8008F828
DumpTPage: equ 0x8008F840
DumpClut: equ 0x8008F8A0
NextPrim: equ 0x8008F8E0
IsEndPrim: equ 0x8008F8FC
AddPrim: equ 0x8008F918
AddPrims: equ 0x8008F954
CatPrim: equ 0x8008F990
TermPrim: equ 0x8008F9B4
SetSemiTrans: equ 0x8008F9CC
SetShadeTex: equ 0x8008F9F4
SetPolyF3: equ 0x8008FA1C
SetPolyFT3: equ 0x8008FA30
SetPolyG3: equ 0x8008FA44
SetPolyGT3: equ 0x8008FA58
SetPolyF4: equ 0x8008FA6C
SetPolyFT4: equ 0x8008FA80
SetPolyG4: equ 0x8008FA94
SetPolyGT4: equ 0x8008FAA8
SetSprt8: equ 0x8008FABC
SetSprt16: equ 0x8008FAD0
SetSprt: equ 0x8008FAE4
SetTile1: equ 0x8008FAF8
SetTile8: equ 0x8008FB0C
SetTile16: equ 0x8008FB20
SetTile: equ 0x8008FB34
SetLineF2: equ 0x8008FB48
SetLineG2: equ 0x8008FB5C
SetLineF3: equ 0x8008FB70
SetLineG3: equ 0x8008FB90
SetLineF4: equ 0x8008FBB0
SetLineG4: equ 0x8008FBD0
SetDrawTPage: equ 0x8008FBF0
SetDrawMove: equ 0x8008FC1C
SetDrawLoad: equ 0x8008FC7C
MargePrim: equ 0x8008FCE8
DumpDrawEnv: equ 0x8008FD20
DumpDispEnv: equ 0x8008FE34
ResetGraph: equ 0x8008FEE0
SetGraphReverse: equ 0x80090064
SetGraphDebug: equ 0x80090178
SetGraphQueue: equ 0x800901DC
GetGraphType: equ 0x80090288
GetGraphDebug: equ 0x80090298
DrawSyncCallback: equ 0x800902A8
SetDispMask: equ 0x80090304
DrawSync: equ 0x800903A0
checkRECT: equ 0x8009040C
ClearImage: equ 0x80090534
ClearImage2: equ 0x800905C8
LoadImage: equ 0x80090664
StoreImage: equ 0x800906C8
MoveImage: equ 0x8009072C
ClearOTag: equ 0x800907F0
ClearOTagR: equ 0x800908A8
DrawPrim: equ 0x80090940
DrawOTag: equ 0x800909A0
PutDrawEnv: equ 0x80090A14
DrawOTagEnv: equ 0x80090B18
GetDrawEnv: equ 0x80090C34
PutDispEnv: equ 0x80090C6C
GetDispEnv: equ 0x80091114
GetODE: equ 0x8009114C
SetTexWindow: equ 0x8009117C
SetDrawArea: equ 0x800911B8
SetDrawOffset: equ 0x8009123C
SetPriority: equ 0x80091280
SetDrawMode: equ 0x800912AC
SetDrawEnv: equ 0x80091304
SetDrawEnv2: equ 0x8009151C
get_mode: equ 0x800917AC
get_cs: equ 0x80091804
get_ce: equ 0x800918D0
get_ofs: equ 0x8009199C
get_tw: equ 0x800919E0
get_dx: equ 0x80091A64
_status: equ 0x80091B14
_otc: equ 0x80091B2C
_clr: equ 0x80091C14
_dws: equ 0x80091E70
_drs: equ 0x800920AC
_ctl: equ 0x80092330
_getctl: equ 0x80092358
_cwb: equ 0x8009236C
_cwc: equ 0x800923BC
_param: equ 0x80092408
_addque: equ 0x80092438
_addque2: equ 0x8009245C
_exeque: equ 0x8009273C
_reset: equ 0x80092A28
_sync: equ 0x80092B84
set_alarm: equ 0x80092CCC
get_alarm: equ 0x80092D00
_version: equ 0x80092E6C
OpenTIM: equ 0x80092F74
ReadTIM: equ 0x80092F84
OpenTMD: equ 0x80092FEC
ReadTMD: equ 0x8009302C
get_tim_addr: equ 0x800932D8
get_tmd_addr: equ 0x800933F8
unpack_packet: equ 0x80093590
DecDCTReset: equ 0x80094870
DecDCTGetEnv: equ 0x800948A8
DecDCTPutEnv: equ 0x80094934
DecDCTBufSize: equ 0x800949D0
DecDCTin: equ 0x800949DC
DecDCTout: equ 0x80094A58
DecDCTinSync: equ 0x80094A78
DecDCToutSync: equ 0x80094AB4
DecDCTinCallback: equ 0x80094AF0
DecDCToutCallback: equ 0x80094B14
MDEC_reset: equ 0x80094B38
MDEC_in: equ 0x80094C34
MDEC_out: equ 0x80094CC8
MDEC_in_sync: equ 0x80094D58
MDEC_out_sync: equ 0x80094DF0
MDEC_status: equ 0x80094E88
timeout: equ 0x80094EA0
DecDCTvlcSize2: equ 0x80094FD4
DecDCTvlc2: equ 0x80095004
_bu_init: equ 0x80095368
InitCARD: equ 0x80095378
StartCARD: equ 0x800953CC
StopCARD: equ 0x80095404
InitCARD2: equ 0x80095434
StartCARD2: equ 0x80095444
StopCARD2: equ 0x80095454
_ExitCard: equ 0x80095464
_patch_card: equ 0x8009553C
_patch_card2: equ 0x800955F4
InitHeap: equ 0x80095684
FlushCache: equ 0x80095694
GPU_cw: equ 0x800956A4
_96_remove: equ 0x800956BC
DeliverEvent: equ 0x800956D4
OpenEvent: equ 0x800956E4
CloseEvent: equ 0x800956F4
WaitEvent: equ 0x80095704
TestEvent: equ 0x80095714
EnableEvent: equ 0x80095724
DisableEvent: equ 0x80095734
OpenTh: equ 0x80095744
CloseTh: equ 0x80095754
ChangeTh: equ 0x80095764
ReturnFromException: equ 0x80095774
ResetEntryInt: equ 0x80095784
HookEntryInt: equ 0x80095794
EnterCriticalSection: equ 0x800957A4
ExitCriticalSection: equ 0x800957B4
open: equ 0x800957C4
lseek: equ 0x800957D4
read: equ 0x800957E4
write: equ 0x800957F4
close: equ 0x80095804
format: equ 0x80095814
nextfile: equ 0x80095824
ChangeClearPAD: equ 0x80095834
GetGp: equ 0x80095844
ChangeClearRCnt: equ 0x80095854
SetRCnt: equ 0x80095864
GetRCnt: equ 0x80095900
StartRCnt: equ 0x80095938
StopRCnt: equ 0x80095968
ResetRCnt: equ 0x8009599C
firstfile: equ 0x800959D4
firstfile2: equ 0x80095C74
PadEnableCom: equ 0x80096134
_padSetVsyncParam: equ 0x8009624C
_IsVSync: equ 0x80096278
_padChkVsync: equ 0x8009644C
_padStartCom: equ 0x80096460
_padStopCom: equ 0x8009652C
_padInitSioMode: equ 0x80096570
_padSioRW: equ 0x8009696C
_padSioRW2: equ 0x80096B44
SysEnqIntRP: equ 0x80096D14
SysDeqIntRP: equ 0x80096D24
_padClrIntSio0: equ 0x80096D7C
_padWaitRXready: equ 0x80096E0C
PadInitDirect: equ 0x80097C74
setRC2wait: equ 0x80098754
chkRC2wait: equ 0x80098774
puts: equ 0x8009881C
setjmp: equ 0x80098834
strcpy: equ 0x80098854
bzero: equ 0x80098864
memcpy: equ 0x80098874
memset: equ 0x80098884
printf: equ 0x80098894
FUN_80039694: equ 0x80039694
FUN_800529fc: equ 0x800529fc
FUN_8003947c: equ 0x8003947c
FUN_80039514: equ 0x80039514
FUN_800395b8: equ 0x800395b8
;;
;; Data
;;
Xa_no: equ 0x80010818
Enemy_edt: equ 0x801f8e10
floc: equ 0x800988a4
Xa_sector00: equ 0x8009a37c
Serial_no: equ 0x8009a3e0
cdmode: equ 0x8009a414
xa_cdmode: equ 0x8009a415
xa_control_tbl: equ 0x8009a418
xacontrol_cdmode: equ 0x8009a428
cdread_cdmode: equ 0x8009a429
cdread_s_cdmode: equ 0x8009a42a
door_msg: equ 0x8009a42c
door_msg_ofs: equ 0x8009a468
D_LIGHTMATRIX: equ 0x8009a470
D_COLORMATRIX: equ 0x8009a490
Dtex_file: equ 0x8009a4b0
Dinfo: equ 0x8009a520
pDoor_proc_tbl: equ 0x8009a7b4
Aida_jh0_tbl: equ 0x8009a7c4
Aida_jh0_head: equ 0x8009a8e8
Aida_jh1_tbl: equ 0x8009a920
Aida_jh1_head: equ 0x8009a97c
Aida_jh2_tbl: equ 0x8009a9b4
Aida_jh2_head: equ 0x8009aa10
Aida_jh3_tbl: equ 0x8009aa48
Aida_jh3_head: equ 0x8009aa58
Aida_jh4_tbl: equ 0x8009aa90
Aida_jh4_head: equ 0x8009aad8
Aida_jh5_tbl: equ 0x8009ab10
Aida_jh5_head: equ 0x8009ab58
Kg_jh0_tbl: equ 0x8009ab90
Kg_jh0_head: equ 0x8009ac60
cdemd0_pos: equ 0x8009adf4
cdemd0_sum: equ 0x8009b754
cdemd1_pos: equ 0x8009b754 ;; relocated from 0x8009b880
cdemd1_sum: equ 0x8009c1e0
cdemd2_pos: equ 0x8009c30c
cdemd2_sum: equ 0x8009cc6c
cdemd3_pos: equ 0x8009cd98
cdemd3_sum: equ 0x8009d358
Emd_name: equ 0x8009d410
Emd_tim_name: equ 0x8009d444
Room_100: equ 0x8009d478
Room_102: equ 0x8009d498
Room_101: equ 0x8009d4a8
Room_202: equ 0x8009d4b8
Room_109: equ 0x8009d4c8
Room_10B: equ 0x8009d4d8
Room_110: equ 0x8009d4e8
Room_117: equ 0x8009d528
Room_700: equ 0x8009d598
Room_702: equ 0x8009d5b8
Room_703: equ 0x8009d5d8
Room_705: equ 0x8009d5f8
Em_stbl_st1: equ 0x8009d648
Em_stbl_st2: equ 0x8009d728
Em_stbl_st7: equ 0x8009d818
Room_Enemy_tbl: equ 0x8009d848
Esp_tblj: equ 0x8009d868
sin_tbl: equ 0x8009d9f4
quake_tbl1: equ 0x8009daf4
quake_tbl2: equ 0x8009db14
sinpuku: equ 0x8009db34
hacho: equ 0x8009db38
speed: equ 0x8009db3c
mode: equ 0x8009db40
GsIDMATRIX: equ 0x8009db44
LIGHTMATRIX: equ 0x8009db64
COLORMATRIX: equ 0x8009db84
Bgm_sw_timer: equ 0x8009dba2
No_death_timer: equ 0x8009dba3
Curtain: equ 0x8009dbac
Pause: equ 0x8009dbec
Scrl_h: equ 0x8009dc0c
Rect: equ 0x8009dc10
Rect_bg: equ 0x8009dc20
Bomb_tbl: equ 0x8009dc28
Mizu_size_tbl: equ 0x8009dca0
Mizu_tbl: equ 0x8009dcc0
Mizu_struct_tbl: equ 0x8009dcd0
Div_prim_coord: equ 0x8009ddcc
msg_space: equ 0x8009de34
namelist_tbl_data: equ 0x8009df3c
namelist_tbl_ofs: equ 0x8009e438
namelist_u_data: equ 0x8009e550
namelist_u_ofs: equ 0x8009ebac
mess_tbl_data: equ 0x8009ecc4
mess_tbl_ofs: equ 0x8009ef9c
mess_u_data: equ 0x8009efcc
mess_u_ofs: equ 0x8009f368
mess_sub_data: equ 0x8009f398
mess_sub_ofs: equ 0x800a0674
mess_etc_data: equ 0x800a075c
mess_etc_ofs: equ 0x800a1e7c
branch_data: equ 0x800a1f64
branch_ofs: equ 0x800a2040
ascii_tbl: equ 0x800a2094
Ld_task_tbl: equ 0x800a20b8
Movie_tbl: equ 0x800a216c
pMovie_proc_tbl: equ 0x800a23ac
pDoor_proc_tbl_ex: equ 0x800a242c
;;Subpl_walk: equ 0x800a2444
;;Subpl_back: equ 0x800a2484
;;Subpl_dir: equ 0x800a24c4
;;Subpl_ato: equ 0x800a2504
;;Subpl_run: equ 0x800a2544
;;Em4a_zobiparts_tbl: equ 0x800a2584
Up_add_tbl: equ 0x800a2594
Down_add_tbl: equ 0x800a25bc
Box_sub_tbl: equ 0x800a25e4
Up_add_Spl_tbl: equ 0x800a260c
Down_add_Spl_tbl: equ 0x800a264c
Key_type: equ 0x800a26a0 ;; Pad_set
Stp_bak: equ 0x800a2700
Key_wait: equ 0x800a2704
Init_work_tbl: equ 0x800a2708
pc_mes_data: equ 0x800a3dc8
pc_mes_ofs: equ 0x800a3e68
;;Kend: equ 0x800a3e7c ;; Computer200
;;Mend: equ 0x800a3e80 ;; Computer200
;;Key_type: equ 0x800a3e84 ;; Computer200
;;Kend: equ 0x800a3e88 ;; Computer613
;;Mend: equ 0x800a3e8c ;; Computer613
;;Key_type: equ 0x800a3e90 ;; Computer613
;;Subpl_walk: equ 0x800a3e94
;;Subpl_back: equ 0x800a3ed4
;;Subpl_dir: equ 0x800a3f14
;;Subpl_ato: equ 0x800a3f54
;;Subpl_run: equ 0x800a3f94
;;Em4a_zobiparts_tbl: equ 0x800a3fd4
Pld_no: equ 0x800a3fe4
Pl_neck_timer: equ 0x800a4004
Pld_name: equ 0x800a4008
Pl_routine: equ 0x800a4030
Pl_mv_pad: equ 0x800a4054
Pl_mv: equ 0x800a4084
Pl_kage_pos: equ 0x800a40b4
pl_water: equ 0x800a40c4
Wat_vec00: equ 0x800a40d4
Pl_dm: equ 0x800a40e4
Pl_die_t: equ 0x800a40fc
Em10_damage_tbl: equ 0x800a412c
Em15_damage_tbl: equ 0x800a42a8
Em20_damage_tbl: equ 0x800a4424
Em21_damage_tbl: equ 0x800a45a0
Em22_damage_tbl: equ 0x800a471c
Em24_damage_tbl: equ 0x800a4898
Em23_damage_tbl: equ 0x800a4a14
Em25_damage_tbl: equ 0x800a4b90
Em27_damage_tbl: equ 0x800a4d0c
Em28_damage_tbl: equ 0x800a4e88
Em29_damage_tbl: equ 0x800a5004
Em2d_damage_tbl: equ 0x800a5180
Em2a_damage_tbl: equ 0x800a52fc
Em2b_damage_tbl: equ 0x800a5478
Em2e_damage_tbl: equ 0x800a55f4
Em30_damage_tbl: equ 0x800a5770
Em31_damage_tbl: equ 0x800a58ec
Em33_damage_tbl: equ 0x800a5a68
Em34_damage_tbl0: equ 0x800a5be4
Em34_damage_tbl1: equ 0x800a5d60
Em36_damage_tbl: equ 0x800a5edc
Em3a_damage_tbl: equ 0x800a6058
Em3b_damage_tbl: equ 0x800a61d4
PLW00_W: equ 0x800a6350
PLW00_S: equ 0x800a63a4
Pl_w011: equ 0x800a63a8
Pl_w01_s1: equ 0x800a6434
Pl_w0111: equ 0x800a6444
Pl_w0111_s1: equ 0x800a64d0
Pl_w010: equ 0x800a64e0
Pl_w01_s0: equ 0x800a656c
Pl_w012: equ 0x800a657c
Pl_w01_s2: equ 0x800a6608
PLW02_W: equ 0x800a6618
PLW02_S: equ 0x800a666c
PLW05_W: equ 0x800a6670
PLW05_S: equ 0x800a66c4
PLW13_W: equ 0x800a66c8
PLW13_S: equ 0x800a671c
PLW07_W: equ 0x800a6724
PLW07_S: equ 0x800a6778
PLW08_W: equ 0x800a6788
PLW08_S: equ 0x800a67dc
PLW0E_W: equ 0x800a67f0
PLW0E_S: equ 0x800a6844
PLW0F_W: equ 0x800a6848
PLW0F_S: equ 0x800a689c
PLW12_W: equ 0x800a68a4
PLW12_S: equ 0x800a68f8
Pl_weapon_tbl: equ 0x800a6900
pEnemy_damage_tbl: equ 0x800a6ac8
Pl_bow_hit_parts: equ 0x800a6b88
Plw_no: equ 0x800a6d08
Pl_weapon_init: equ 0x800a6d28
Pl_weapon_kyan: equ 0x800a6d78
W_at_ck: equ 0x800a6db4
Ghand_len: equ 0x800a6dd0
Mw_ck: equ 0x800a6e68
Pl_wep_mag_type: equ 0x800a6e78
Pl_mag: equ 0x800a6e90
G_rot_data_z: equ 0x800a6ea8
pl_mv05_w_tbl: equ 0x800a6f3c
Gun_jtg_bit: equ 0x800a6f8c
pl_mv05_t2_init: equ 0x800a6f94
pl_mv05_t2_spr: equ 0x800a6fe0
pl_mv05_w0_tbl: equ 0x800a702c
pl_mv05_w1_tbl: equ 0x800a7048
Bow_Room509: equ 0x800a7060
pl_mv05_w2_tbl: equ 0x800a7068
pl_mv05_w3_tbl: equ 0x800a7080
pl_mv05_w4_tbl: equ 0x800a7098
pl_mv05_w5_tbl: equ 0x800a70b0
Poly_test4: equ 0x800a70c8
ascii_tbl_2: equ 0x800a70e8
Rdt_tbl1: equ 0x800a70fc
Rdt_tbl2: equ 0x800a7138
Rdt_tbl3: equ 0x800a7170
Rdt_tbl4: equ 0x800a7190
Rdt_tbl5: equ 0x800a71b8
Rdt_tbl6: equ 0x800a71d0
Rdt_tbl7: equ 0x800a7200
Rdt_tbl: equ 0x800a7210
;;Subpl_walk: equ 0x800a722c
;;Subpl_back: equ 0x800a726c
;;Subpl_dir: equ 0x800a72ac
;;Subpl_ato: equ 0x800a72ec
;;Subpl_run: equ 0x800a732c
;;Em4a_zobiparts_tbl: equ 0x800a736c
Sca_rtn_tbl: equ 0x800a737c
Sca_no_ck_tbl: equ 0x800a73b4
Sce_at_jump_tbl: equ 0x800a73c4
em_se_tbl: equ 0x800a7400
Sce_jmp_tbl: equ 0x800a74c8
Em_kind_tbl: equ 0x800a7704
;;Subpl_walk: equ 0x800a7778
;;Subpl_back: equ 0x800a77b8
;;Subpl_dir: equ 0x800a77f8
;;Subpl_ato: equ 0x800a7838
;;Subpl_run: equ 0x800a7878
;;Em4a_zobiparts_tbl: equ 0x800a78b8
Flg_addr: equ 0x800a78c8
;;Subpl_walk: equ 0x800a7968
;;Subpl_back: equ 0x800a79a8
;;Subpl_dir: equ 0x800a79e8
;;Subpl_ato: equ 0x800a7a28
;;Subpl_run: equ 0x800a7a68
;;Em4a_zobiparts_tbl: equ 0x800a7aa8
Itp_check_sum: equ 0x800a7ab8
EnemSE_floc: equ 0x800a7b1c
LRVT: equ 0x800a7fb0
PANVT: equ 0x800a8030
nroom: equ 0x800a80b0
Core_edh: equ 0x800a80b8
Core_vbd: equ 0x800a80e8
Arms_edh: equ 0x800a8118
Arms_vbd: equ 0x800a8140
Main_bgm: equ 0x800a8168
Sub_bgm: equ 0x800a81e8
;;Subpl_walk: equ 0x800a8268
;;Subpl_back: equ 0x800a82a8
;;Subpl_dir: equ 0x800a82e8
;;Subpl_ato: equ 0x800a8328
;;Subpl_run: equ 0x800a8368
;;Em4a_zobiparts_tbl: equ 0x800a83a8
Spl_routine_0: equ 0x800a83b8
Spl_mv: equ 0x800a83dc
Spl_in: equ 0x800a844c
Spl_dm: equ 0x800a84bc
Spl_die: equ 0x800a84cc
Spl_dead: equ 0x800a84d0
;;Subpl_walk: equ 0x800a84d4
;;Subpl_back: equ 0x800a8514
;;Subpl_dir: equ 0x800a8554
;;Subpl_ato: equ 0x800a8594
;;Subpl_run: equ 0x800a85d4
;;Em4a_zobiparts_tbl: equ 0x800a8614
Spl_r_pos: equ 0x800a8624
Aida_Move_type: equ 0x800a863c
Aida_St_pos: equ 0x800a8668
Spl_pos_ck_timer: equ 0x800a8673
Aida_mv_br_type00: equ 0x800a8674
Aida_mv_type00: equ 0x800a86ac
Aida_mv_br_type01: equ 0x800a86e4
Aida_mv_br_type02: equ 0x800a871c
Aida_mv_br_type03: equ 0x800a8754
Aida_mv_br_type04: equ 0x800a878c
Aida_mv_br_type05: equ 0x800a87c4
Aida_mv_br_type06: equ 0x800a87fc
Aida_mv_br_type07: equ 0x800a8834
Aida_mv_br_type08: equ 0x800a886c
Aida_mv_br_type09: equ 0x800a88a4
Aida_mv_br_type0a: equ 0x800a88dc
E_A_at_tbl: equ 0x800a8914
Aida_em_at00_pl: equ 0x800a8944
Aida_em_at00_spl: equ 0x800a8950
Aida_em_at01: equ 0x800a895c
Aida_mv05_w1_br_tbl: equ 0x800a8968
Aida_mv05_w1_tbl: equ 0x800a8980
Aida_em_at05: equ 0x800a8998
Sherry_Move_type: equ 0x800a89a0
Sherry_St_pos: equ 0x800a89cc
Sherry_mv_br_type00: equ 0x800a89d8
Sherry_mv_br_type01: equ 0x800a8a10
Sherry_mv_br_type02: equ 0x800a8a48
Sherry_mv_br_type03: equ 0x800a8a80
Sherry_mv_br_type04: equ 0x800a8ab8
Sherry_mv_br_type05: equ 0x800a8af0
Sherry_mv_br_type06: equ 0x800a8b28
Sherry_mv_br_type07: equ 0x800a8b60
Sherry_mv_br_type08: equ 0x800a8b98
Sherry_mv_br_type09: equ 0x800a8bd0
Sherry_mv_br_type0a: equ 0x800a8c08
;;Subpl_walk: equ 0x800a8c40
;;Subpl_back: equ 0x800a8c80
;;Subpl_dir: equ 0x800a8cc0
;;Subpl_ato: equ 0x800a8d00
;;Subpl_run: equ 0x800a8d40
;;Em4a_zobiparts_tbl: equ 0x800a8d80
Spl_sce: equ 0x800a8d90
;;Subpl_walk: equ 0x800a8e14
;;Subpl_back: equ 0x800a8e54
;;Subpl_dir: equ 0x800a8e94
;;Subpl_ato: equ 0x800a8ed4
;;Subpl_run: equ 0x800a8f14
;;Em4a_zobiparts_tbl: equ 0x800a8f54
Spl_sp: equ 0x800a8f62
init_item_tbl_Leon: equ 0x800a9264
init_item_tbl_Claire: equ 0x800a9285
init_item_tbl_Hunk: equ 0x800a92a6
init_item_tbl_ToFu: equ 0x800a92c7
init_item_tbl_Leon_Ex: equ 0x800a92e8
init_item_tbl_Claire_Ex: equ 0x800a9309
init_item_tbl_Ada_Ex: equ 0x800a932a
init_item_tbl_Chris_Ex: equ 0x800a934b
Status_proc_tbl: equ 0x800a936c
st_light: equ 0x800a93a8
init_item_tbl_Ada: equ 0x800a93d0
init_item_tbl_Sherry: equ 0x800a93f1
maps_floc: equ 0x800a9414
fits_floc: equ 0x800a94b4
Status_menu0_proc_tbl: equ 0x800a9aac
;;add: equ 0x800a9ac4 ;; St_menu0_file
File_offset: equ 0x800a9ad0
map_up_floor: equ 0x800a9aec
map_down_floor: equ 0x800a9b04
Map_char_tbl: equ 0x800a9b8c
Status_direct_map_proc_tbl0: equ 0x800a9b94
Status_direct_map_proc_tbl1: equ 0x800a9ba8
St_itembox_proc_tbl: equ 0x800a9bb4
Ibox_char_tbl: equ 0x800a9bc4
f4_tbl: equ 0x800a9c28
Ibox_pos_tbl: equ 0x800a9c38
St_getitem_proc_tbl: equ 0x800a9c9c
move_tbl: equ 0x800a9cb0
;;add: equ 0x800a9cdc ;; St_get_file
Mix_nodata: equ 0x800a9ce8
Mix_beretta: equ 0x800a9cec
Mix_magnam: equ 0x800a9cf4
Mix_shotgun: equ 0x800a9cfc
Mix_machinegun: equ 0x800a9d04
Mix_fire: equ 0x800a9d08
Mix_bowgun: equ 0x800a9d0c
Mix_g_n: equ 0x800a9d10
Mix_g_f: equ 0x800a9d1c
Mix_g_a: equ 0x800a9d28
Mix_spark: equ 0x800a9d34
Mix_bullet: equ 0x800a9d38
Mix_dot380: equ 0x800a9d50
Mix_shot_dan: equ 0x800a9d58
Mix_arrow: equ 0x800a9d64
Mix_mag_dan: equ 0x800a9d6c
Mix_nen: equ 0x800a9d78
Mix_battley: equ 0x800a9d80
Mix_g_normal: equ 0x800a9d88
Mix_g_fire: equ 0x800a9d98
Mix_g_acid: equ 0x800a9da8
Mix_ink_ribbon: equ 0x800a9db8
Mix_parts_a: equ 0x800a9dbc
Mix_parts_b: equ 0x800a9dc0
Mix_parts_c: equ 0x800a9dc4
Mix_g: equ 0x800a9dd0
Mix_r: equ 0x800a9de4
Mix_b: equ 0x800a9dec
Mix_gr: equ 0x800a9df8
Mix_gg: equ 0x800a9dfc
Mix_gb: equ 0x800a9e04
Mix_p_bomb: equ 0x800a9e0c
Mix_fuse: equ 0x800a9e10
Mix_Jaguar_a: equ 0x800a9e14
Mix_Jaguar_b: equ 0x800a9e18
Item_data_tbl: equ 0x800a9e1c
File_data: equ 0x800aa144
Map_stage1_0: equ 0x800aa1a8
Map_stage1_1: equ 0x800aa228
Map_stage1_2: equ 0x800aa268
Map_stage1_3: equ 0x800aa358
Map_stage2_0: equ 0x800aa388
Map_stage2_1: equ 0x800aa4a8
Map_stage3_0: equ 0x800aa558
Map_stage4_0: equ 0x800aa608
Map_stage4_1: equ 0x800aa668
Map_stage5_0: equ 0x800aa738
Map_stage5_1: equ 0x800aa778
Map_stage5_2: equ 0x800aa7a8
Map_stage5_3: equ 0x800aa7d8
Map_stage6_0: equ 0x800aa7f8
Map_stage6_1: equ 0x800aa858
Map_stage6_2: equ 0x800aa868
Map_stage6_3: equ 0x800aa878
Map_stage6_4: equ 0x800aa948
Map_stage6_5: equ 0x800aa988
Map_stage7_0: equ 0x800aa9b8
Map_stage7_1: equ 0x800aaa18
Map_info: equ 0x800aaa38
Ecg_normal_tbl: equ 0x800aaad8
Ecg_caution0_tbl: equ 0x800aab78
Ecg_caution1_tbl: equ 0x800aac18
Ecg_danger_tbl: equ 0x800aacb8
Ecg_poison_tbl: equ 0x800aad58
N_pos: equ 0x800aadf8
Cursol0_char_tbl: equ 0x800aae40
Cursol0_pos_tbl: equ 0x800aae4c
Cursol1_char_tbl: equ 0x800aae70
Cursol1_pos_tbl: equ 0x800aae7c
Face_char_tbl: equ 0x800aaea0
Face_subchar_tbl: equ 0x800aaed4
Face_pos_tbl: equ 0x800aaefc
Face_subpos_tbl: equ 0x800aaf30
Message_char_tbl: equ 0x800aaf58
Message_pos_tbl: equ 0x800aaf9c
Frame_char_tbl: equ 0x800aafe0
Frame_pos_tbl: equ 0x800ab024
Menu0_char_tbl: equ 0x800ab068
Menu0_pos_tbl: equ 0x800ab088
Menu1_char_tbl: equ 0x800ab0a8
Menu1_pos_tbl: equ 0x800ab0cc
Itemlist_char_tbl: equ 0x800ab0f0
Itemlist_pos_tbl: equ 0x800ab10c
Equip_char_tbl: equ 0x800ab128
Equip_pos_tbl: equ 0x800ab144
Ecg_col_tbl: equ 0x800ab160
Ecg_line_tbl: equ 0x800ab180
ECG_char_tbl: equ 0x800ab194
Itemget_char: equ 0x800ab19c
Itemget_pos_tbl: equ 0x800ab1bc
v_p: equ 0x800ab1dc
v_r: equ 0x800ab1e8
pp: equ 0x800ab1f4
pMem_man: equ 0x800ab204
;;Svec: equ 0x800ab208 ;; Rot_vector
;;Svec: equ 0x800ab210 ;; Rot_vector_super
Poly_ft4_count: equ 0x800ab218
_spu_RXX: equ 0x800ab21c
_spu_tsa: equ 0x800ab234
_spu_transMode: equ 0x800ab238
_spu_mem_mode_plus: equ 0x800ab244
_spu_mem_mode_unitM: equ 0x800ab24c
_spu_inTransfer: equ 0x800ab250
_spu_transferCallback: equ 0x800ab254
_spu_IRQCallback: equ 0x800ab258
_spu_EVdma: equ 0x800ab280
_spu_keystat: equ 0x800ab284
_spu_trans_mode: equ 0x800ab288
_spu_rev_flag: equ 0x800ab28c
_spu_rev_reserve_wa: equ 0x800ab290
_spu_rev_offsetaddr: equ 0x800ab294
_spu_rev_attr: equ 0x800ab29c
_spu_RQvoice: equ 0x800ab2ac
_spu_RQmask: equ 0x800ab2b0
_spu_zerobuf: equ 0x800ab2e4
_spu_env: equ 0x800ab6e4
_spu_isCalled: equ 0x800ab6e8
_spu_AllocBlockNum: equ 0x800ab6ec
_spu_AllocLastNum: equ 0x800ab6f0
_spu_memList: equ 0x800ab6f4
_spu_rev_startaddr: equ 0x800ab6f8
_snd_seq_tick_env: equ 0x800aba28
;;rsin_tbl: equ 0x800abb48 ;; rcos
_stacksize: equ 0x800abbcc
;;rsin_tbl: equ 0x800ac348 ;; sin_1
;;rsin_tbl: equ 0x800acb48 ;; rcos
Vcount: equ 0x800acd00
GsCLIP3near: equ 0x800acd30
GsCLIP3far: equ 0x800acd30
GsOUT_PACKET_P: equ 0x800acd30
CD_cbsync: equ 0x800acdec
CD_cbready: equ 0x800acdf0
CD_debug: equ 0x800acdf8
CD_status: equ 0x800acdfc
CD_pos: equ 0x800ace08
CD_mode: equ 0x800ace0c
CD_com: equ 0x800ace0d
DS_active: equ 0x800ace10
CD_comstr: equ 0x800ace14
CD_intstr: equ 0x800ace94
CDROM_DELAY: equ 0x800ad0e8
CDROM_REG0: equ 0x800ad14c
CDROM_REG1: equ 0x800ad150
CDROM_REG2: equ 0x800ad154
CDROM_REG3: equ 0x800ad158
;;CDROM_DELAY: equ 0x800ad15c
COMMON_DELAY: equ 0x800ad160
DMA_DPCR: equ 0x800ad164
DMA_DICR: equ 0x800ad168
DMA_MDEC_OUT_CHCR: equ 0x800ad16c
DMA_CDROM_CHCR: equ 0x800ad17c
;;rsin_tbl: equ 0x800ad348 ;; rcos, sin_1
SQRT: equ 0x800adb8c
rcossin_tbl: equ 0x800adeac
ratan_tbl: equ 0x800b1eac
GPU_printf: equ 0x800b26fc
DecDctEnv: equ 0x800b2824
DCL_DVLC: equ 0x800b296c
DCC_DVLC: equ 0x800b2d6c
CF_DVLC: equ 0x800b316c
CF2_DVLC: equ 0x800c316c
_padFuncNextPort: equ 0x800c399c
_padFuncClrInfo: equ 0x800c39a0
_padFuncGetTxd: equ 0x800c39a4
_padFuncCurrLimit: equ 0x800c39a8
_padFuncPtr2Port: equ 0x800c39ac
_padFuncPort2Info: equ 0x800c39b0
_padFuncSendAuto: equ 0x800c39b4
_padFuncChkEng: equ 0x800c39b8
_padFuncRecvAuto: equ 0x800c39bc
_padFuncClrCmdNo: equ 0x800c39c0
_padInfoDir: equ 0x800c39d0
_padIntExec: equ 0x800c39d4
_padSioChan: equ 0x800c39dc
_padSioState: equ 0x800c39e0
_padTotalCurr: equ 0x800c39e4
_padModeMtap: equ 0x800c39e8
_padChanStart: equ 0x800c39ec
_padChanStop: equ 0x800c39f0
_padFixResult: equ 0x800c39f4
_padCalledIntPad: equ 0x800c3a04
;;__sbss_obj: equ 0x800c3a48
pDoor: equ 0x800c3a80
Stop_bak: equ 0x800c3a88
V: equ 0x800c3a8c
Kpos: equ 0x800c3a9c
Kofs: equ 0x800c3ab0
pPc: equ 0x800c3ab8
;;Hit_flg: equ 0x800c3b68 ;; Sca_ck_hit
pSca_data: equ 0x800c3b6c
Old_x: equ 0x800c3b70
Old_z: equ 0x800c3b74
;;Hit_flg: equ 0x800c3b78 ;; Sca_ck_hit_om
Gnd_y: equ 0x800c3b7c
In_flg: equ 0x800c3b80
Tmp_Sca: equ 0x800c3b84
Key_work: equ 0x800c3b98
Dir_spd: equ 0x800c3b9c
Spd_add: equ 0x800c3ba0
pOwork: equ 0x800c3ba4
Key_work_0: equ 0x800c3ba8
pItem_dat: equ 0x800c3bac
pAot: equ 0x800c3bb0
EM40_Prim: equ 0x800c3bb8
shot: equ 0x800c3bd0
num: equ 0x800c3bd8
Tmp_matrix: equ 0x800c3be0
;;Svec: equ 0x800c3c20 ;; Set_front_pos
pStack_bak: equ 0x800c3c28
_padVsyncParam: equ 0x800c40a8
_padRestPeriod: equ 0x800c40b8
;;_padIntExec: equ 0x800c40bc ;; copy of _padIntExec
Poly2_work: equ 0x800c4348
add_y: equ 0x800c4408
Reverb_flg: equ 0x800c4410
Trans: equ 0x800c4418
PadActData: equ 0x800cbc20
Stframe_no: equ 0x800cbc24
Sedir2: equ 0x800cbc30
SsFCALL: equ 0x800cbc38
m_pl_weapon_tmd: equ 0x800cc1e0
G: equ 0x800cc1e8
Vab_id: equ 0x800d4c48
_svm_rattr: equ 0x800d4c50
Stsector_offset: equ 0x800d4c64
StRgb24: equ 0x800d4c68
StMode: equ 0x800d4c6c
Em_dir: equ 0x800d4c70
Cd_vol: equ 0x800d4c78
Se_pri: equ 0x800d4ca0
Move_x: equ 0x800d4cd0
pEspdt: equ 0x800d4cd8
pDwork: equ 0x800d4dd8
bk_cut: equ 0x800d4e00
pEspmv: equ 0x800d4e18
sel_no: equ 0x800d4f18
Entory: equ 0x800d4f20
StFunc1: equ 0x800d5218
StFunc2: equ 0x800d521c
_svm_vab_pg: equ 0x800d5228
StCdIntrFlag: equ 0x800d5268
;;_svm_vab_pg: equ 0x800d5268
_svm_vab_vh: equ 0x800d5270
_svm_damper: equ 0x800d52b0
;;_svm_vab_vh: equ 0x800d52b0
_svm_vab_tn: equ 0x800d52b8
;;_svm_vab_tn: equ 0x800d52f8
CD: equ 0x800d5300
Channel: equ 0x800d5b80
_spu_RQ: equ 0x800d5b88
Mem_man: equ 0x800d5ba0
m_pl_w00_tmd2: equ 0x800d5be0
Ceiling: equ 0x800d5be4
pSce_em: equ 0x800d5be8
St: equ 0x800d5bf0
StCHANNEL: equ 0x800d6c38
StStartFrame: equ 0x800d6c3c
_svm_stereo_mono: equ 0x800d6c40
Cc_work: equ 0x800d6c48
Pan_vol: equ 0x800d7598
pVh_tbl: equ 0x800d75a0
Seq_ctr: equ 0x800d75c0
Vm_disp: equ 0x800d75d8
Om_fall_old_dir_x: equ 0x800d7638
pVm_frm: equ 0x800d763c
Om_fall_old_dir_z: equ 0x800d7642
pSpl_near_em: equ 0x800d7648
UnknownPadInfoByte: equ 0x800d7654
_snd_ev_flag: equ 0x800d7658
Rev_vol: equ 0x800d765c
gpPl_pac_ptr: equ 0x800d7660
kMaxPrograms: equ 0x800d7664
CdReadSoundCnt: equ 0x800d7668
sw: equ 0x800d766c
Vm_work: equ 0x800d7670
pStairs: equ 0x800d7694
Ev0: equ 0x800d7698
Monitor: equ 0x800d76a0
Ev1: equ 0x800d7828
Ev2: equ 0x800d782c
Ev3: equ 0x800d7830
xx: equ 0x800d7834
_svm_pg: equ 0x800d7838
UnkSndSysInitSubFlg: equ 0x800d783c
yy: equ 0x800d783e
gpPl_tmd_ptr: equ 0x800d7840
_svm_vg: equ 0x800d7844
_svm_vh: equ 0x800d7848
_svm_tn: equ 0x800d784c
CChannel: equ 0x800d7850
_SsVmMaxVoice: equ 0x800d7854
Bgm: equ 0x800d7856
gpPl_pac2_ptr: equ 0x800d7858
UnkMvPadFlg: equ 0x800d785c
Sce: equ 0x800d7860
Ev10: equ 0x800d8cd4
Loc: equ 0x800d8cd8
Ev11: equ 0x800d8cdc
Ev13: equ 0x800d8ce0
RevD_vol: equ 0x800d8ce4
m_pl_weapon_parts: equ 0x800d8ce8
gpPl_tmd2_ptr: equ 0x800d8cec
Esp: equ 0x800d8cf0
pEdt_adr: equ 0x800dbb70
UnkSndFlg0: equ 0x800dbb88
UnkSndSysFlg0: equ 0x800dbb8c
StFinalSector: equ 0x800dbb90
Poly_eff: equ 0x800dbb98
Om_fall_dir_x: equ 0x800dcb98
Main_vol: equ 0x800dcb9c
Om_fall_dir_y: equ 0x800dcba0
Om_fall_dir_z: equ 0x800dcba2
f_x: equ 0x800dcba4
f_y: equ 0x800dcba6
GsWSMATRIX: equ 0x800dcba8
Ground_in_flg: equ 0x800dcbc8
bk_light: equ 0x800dcbcc
pESP: equ 0x800dcbd0
_snd_openflag: equ 0x800dcbd4
_autopan: equ 0x800dcbd8
Ex_battle_rcut: equ 0x800dcbe0
_svm_cur: equ 0x800dcc31
Ex_battle_vcut: equ 0x800dcc50
_svm_vab_used: equ 0x800dcc68
Poly_eff2: equ 0x800dce30
_autovol: equ 0x800df330
m_pl_weapon_packet: equ 0x800df334
pMovie_result: equ 0x800df338
StEmu_Idx: equ 0x800df33c
Fade_mode: equ 0x800df340
Game: equ 0x800df348
Demo: equ 0x800df390
Key_idx_bak: equ 0x800dfad6
UnknownSetRoomByte: equ 0x800dfad7
Em_l: equ 0x800dfad8
_svm_auto_kof_mode: equ 0x800dfade
Main: equ 0x800dfae0
pBgm: equ 0x800dfd64
Line: equ 0x800dfd68
UnknownPadSetFlag: equ 0x800e2a80
UnknownSndSysFlg: equ 0x800e2a84
Ret_Value: equ 0x800e2a88
GsMWSMATRIX: equ 0x800e2a90
Moji: equ 0x800e2ab0
Moji_buff: equ 0x800e8438
_svm_envx_ptr: equ 0x800e8764
Volume_Se: equ 0x800e8768
Seq_table: equ 0x800e8770
pAtv: equ 0x800e8980
_que: equ 0x800e8998
Ceiling_in_pos: equ 0x800ea198
VBLANK_MINUS: equ 0x800ea228
StRingIdx1: equ 0x800ea22c
StRingIdx2: equ 0x800ea230
StRingIdx3: equ 0x800ea234
pCom_work: equ 0x800ea23c
pPsp_prim: equ 0x800ea240
m_pl_w00_packet: equ 0x800ea248
_ss_score: equ 0x800ea250
_SsMarkCallback: equ 0x800ea2d0
pPsp_work: equ 0x800eaad0
_snd_seq_s_max: equ 0x800ead72
StEmu_Addr: equ 0x800ead74
_snd_seq_t_max: equ 0x800ead78
StEndFrame: equ 0x800ead7c
StSTART_FLAG: equ 0x800ead90
pCAot: equ 0x800ead94
StRingBase: equ 0x800ead98
StRingAddr: equ 0x800ead9c
_svm_vab_total: equ 0x800eada0
Old_Fatari: equ 0x800eade0
MainVbSize: equ 0x800eade4
_svm_vab_count: equ 0x800eade8
_svm_vab_start: equ 0x800eadf0
Old_Uatari: equ 0x800eae30
pFile: equ 0x800eae34
m_pl_w00_packet2: equ 0x800eae38
Volume_Bgm: equ 0x800eae3c
RoomVbSize: equ 0x800eae40
Espid: equ 0x800eae48
_svm_envx_hist: equ 0x800eae5c
Sedir: equ 0x800eae98
StRingSize: equ 0x800eae9c
_svm_okof1: equ 0x800eaea0
_svm_okof2: equ 0x800eaea2
;;
;; Custom Data
;;
BuildDate: equ 0x80010000 ;; CHAR[16] Build Date (written after assembly)
CdxLbaBin: equ 0x80010010 ;; ULONG pDiscTable (BIN)
CdxLbaBss: equ 0x80010014 ;; ULONG pDiscTable (BSS)
CdxLbaDat: equ 0x80010018 ;; ULONG pDiscTable (DATA)
CdxLbaDo2: equ 0x8001001C ;; ULONG pDiscTable (DOOR)
CdxLbaEmd0: equ 0x80010020 ;; ULONG pDiscTable (CDEMD0)
CdxLbaEmd1: equ 0x80010024 ;; ULONG pDiscTable (CDEMD1)
CdxLbaPld: equ 0x80010028 ;; ULONG pDiscTable (PLD)
CdxLbaPlw: equ 0x8001002C ;; ULONG pDiscTable (PLW)
CdxLbaSndArms: equ 0x80010030 ;; ULONG pDiscTable (SNDARMS)
CdxLbaSndCore: equ 0x80010034 ;; ULONG pDiscTable (SNDCORE)
CdxLbaSndEmd: equ 0x80010038 ;; ULONG pDiscTable (SNDEMD)
CdxLbaSndMain: equ 0x8001003C ;; ULONG pDiscTable (SNDMAIN)
CdxLbaSndSub: equ 0x80010040 ;; ULONG pDiscTable (SNDSUB)
CdxLbaRdt: equ 0x80010044 ;; ULONG pDiscTable (RDT)
CdxLbaXa: equ 0x80010048 ;; ULONG pDiscTable (XA)
CdxLbaStr: equ 0x8001004C ;; ULONG pDiscTable (STR)
SysDisk: equ 0x80010050
SysScenario: equ 0x80010051
SysController: equ 0x80010052
SysLanguage: equ 0x80010053
DebugFlag: equ 0x80010054
DebugValue: equ 0x80010058
CdReadMode: equ 0x8001005C
ItoxBuffer: equ 0x800107C0
;;
;; CDX Function
;;
CdReadEx: equ 0x80013038
SetDisk: equ 0x800A70FC
LoadPlwTable: equ 0x8009CEB8
|
MeganGrass/Resident-Evil-2-Starter-Kit | 2,247 | source/assembly/custom.s |
/*
* bio2.s must be updated when this file is modified
*/
/*
* Custom Variable
*/
BuildDate: equ 0x80010000
CdxLbaBin: equ 0x80010010
CdxLbaBss: equ 0x80010014
CdxLbaDat: equ 0x80010018
CdxLbaDo2: equ 0x8001001C
CdxLbaEmd0: equ 0x80010020
CdxLbaEmd1: equ 0x80010024
CdxLbaPld: equ 0x80010028
CdxLbaPlw: equ 0x8001002C
CdxLbaSndArms: equ 0x80010030
CdxLbaSndCore: equ 0x80010034
CdxLbaSndEmd: equ 0x80010038
CdxLbaSndMain: equ 0x8001003C
CdxLbaSndSub: equ 0x80010040
CdxLbaRdt: equ 0x80010044
CdxLbaXa: equ 0x80010048
CdxLbaStr: equ 0x8001004C
SysDisk: equ 0x80010050
SysScenario: equ 0x80010051
SysController: equ 0x80010052
SysLanguage: equ 0x80010053
DebugFlag: equ 0x80010054
DebugValue: equ 0x80010058
CdReadMode: equ 0x8001005C
pPlMvTbl: equ 0x80010080
pPlMvPadTbl: equ 0x800100C0
ItoxBuffer: equ 0x800107C0
/*
* Custom Function
*/
Dec_lz: equ 0x80010100
/*
* Debug Function
*/
DebugOrg: equ 0x8009C300
Debug_Menu: equ 0x8009C328
Debug_Status: equ 0x8009C8E8
/*
* CDX Function
*/
Cd_read_ex: equ 0x80013038 // do not modify
Set_disk: equ 0x800A70FC
Load_bgm: equ 0x800A7194
Load_stage: equ 0x8009CB58
Load_pld: equ 0x8009CE70
Load_plw_index: equ 0x8009CEB8
/*
* Enemy Table
*/
emd00_pos: equ cdemd0_pos
emd01_pos: equ cdemd1_pos
/*
* Player Function
*/
Plmv00_pad: equ 0x8009CF00
pl_mv0c: equ 0x8009D094
pl_mv03_action: equ 0x8009D1CC
pl_mv05_action: equ 0x8009D210
TamaReload: equ 0x8009D348
/*
* Overlay Function
*/
Boot_Game_Set: equ 0x801904C4
/*
* CDX File Buffer
*/
pFileIndex: equ 0x800988A4
pBssIndex: equ 0x80099254
pBgmTable: equ 0x800993D4
pRdtIndex: equ 0x80099434
pPlwIndex: equ 0x800995B4
pPldIndex: equ 0x8009965C
pSndMainIndex: equ 0x8009975C
pSndSubIndex: equ 0x8009995C
pDo2Index: equ 0x80099B5C
pSndArmsIndex: equ 0x80099D5C
pSndCoreIndex: equ 0x80099E9C
pXasTable: equ 0x80099FFC
/*
* Custom Controller
*/
PAD_DEBUG: equ PAD_TRIANGLE
PAD_ANTI_FREEZE: equ PAD_L1+PAD_SQUARE |
MeganGrass/Resident-Evil-2-Starter-Kit | 1,330 | source/assembly/clean.s |
/*
* desld has been replaced with lz compression
*/
.org 0x80010000
.fill 0x778
/*
* Task_lexecute and Task_lchain have been patched to read direct pointers and Ld_adr table is no longer used
*
* 80010804 is reserved for a pointer to a routine in STAGE6.BIN, which is currently unimplemented
*/
.org 0x800107C0
.fill 0x44
.org 0x80010808
.fill 0x10
/*
* floc structure has been replaced and is this area is updated before the iso is created
*/
.org 0x800988A4
.fill 0x1AD8
/*
* cdemd0_pos & cdemd1_pos tables are updated here before the iso is created
*
* CD routines have been rewritten to ignore file integrity, so cdemd*_sum tables are no longer used
*
* cdemd2/cdemd3 tables were never used
*/
.org 0x8009ADF4
.fill 0x261C
/*
* unused strings
*/
.org 0x8009D410
.fill 0x68
/*
* RDT filecode ids are no longer used
*/
.org 0x800A70FC
.fill 0x130
/*
* nroom is no longer used to parse the bgm table in savegame data
*/
.org 0x800A80B0
.fill 0x08
/*
* arms, core, main and sub filecode ids are no longer used
*/
.org 0x800A80B8
.fill 0x1B0
/*
* Due to a compile error, there are 9 copies of Subpl_walk, Subpl_back, Subpl_dir, Subpl_ato, Subpl_run, and Em4a_zobiparts_tbl in only the main executable alone, 0x150 bytes for every occurrence
*
* It would take a herculean effort to patch every xref to these...
*/
|
MeganGrass/Resident-Evil-2-Starter-Kit | 2,935 | source/assembly/slus_00748.s |
.erroronwarning on
.psx
.open "./disc/SLUS_007.48",0x8000F800
/*
* Preprocessor
*/
DebugRelease: equ 1
FALSE: equ 0
TRUE: equ 1
/*
* Clean
*/
.include "./source/assembly/clean.s"
/*
* Predefined
*/
.include "./source/assembly/directive.s"
/*
* Disk
*/
.include "./source/assembly/disk/filecode.s"
.include "./source/assembly/disk/task.s"
/*
* Custom
*/
.include "./source/assembly/custom.s"
/*
* Compression
*/
.include "./source/assembly/compression/lz_dec.s"
/*
* Boot
*/
.include "./source/assembly/boot/hook.s"
.include "./source/assembly/boot/logo.s"
/*
* CD
*/
.include "./source/function/Cd_read/Cd_read.asm"
.include "./source/function/Cd_read_ex/Cd_read_ex.asm"
.include "./source/function/Cd_read_s/Cd_read_s.asm"
.include "./source/function/Cd_ready_cb/Cd_ready_cb.asm"
.include "./source/function/Set_disk/Set_disk.asm"
/*
* Debug
*/
.include "./source/function/Debug_menu/Debug_menu.asm"
/*
* Enemy
*/
.include "./source/function/Emd_load_file/Emd_load_file.asm"
.include "./source/assembly/enemy/emd00.s"
.include "./source/assembly/enemy/emd01.s"
/*
* Movie
*/
.include "./source/assembly/str/Movie_tbl.s"
/*
* Player
*/
.include "./source/function/Load_pld/Load_pld.asm"
.include "./source/function/Load_plw_index/Load_plw_index.asm"
.include "./source/assembly/player/Player_set.s"
.include "./source/assembly/player/Pl_weapon_ch.s"
.include "./source/assembly/player/Player_move.s"
.include "./source/function/pl_mv00_pad/pl_mv00_pad.asm"
.include "./source/assembly/player/pl_mv05.s"
/*
* Stage
*/
.include "./source/assembly/stage/Load_bss.s"
.include "./source/assembly/stage/Load_rdt.s"
.include "./source/assembly/stage/Set_stage.s"
.include "./source/function/Load_stage/Load_stage.asm"
/*
* Sound
*/
.include "./source/assembly/Sound/Snd_bgm.s"
.include "./source/assembly/Sound/Snd_bgm_set.s"
.include "./source/assembly/Sound/Snd_bgm_ck.s"
.include "./source/function/Load_bgm/Load_bgm.asm"
//.include "./source/function/Snd_sys_enem_set/Snd_sys_enem_set.asm"
/*
* Status
*/
//.include "./source/function/file_moji_load/file_moji_load.asm"
/*
* Voice
*/
.include "./source/function/Xa_play/Xa_play.asm"
/*
* Filecode
*/
FILE_DO2: equ 0x257 ;; x8 + 0x800988A4 = 0x8009A1DC
FILE_ARMS_EDH: equ 0x297 ;;
FILE_ARMS_VBD: equ 0x2AB ;; FILE_ARMS_EDH+0x14
FILE_CORE_EDH: equ 0x2BF ;;
FILE_CORE_VBD: equ 0x2D5 ;; FILE_CORE_EDH+0x16
.org 0x80059CE8
addiu $a0, $s2, FILE_ARMS_EDH
nop
nop
.org 0x80059DFC
addiu $a0, $s2, FILE_ARMS_VBD
nop
nop
.org 0x80059A94
addiu $a0, $s3, FILE_CORE_EDH
nop
nop
.org 0x80059B58
addiu $a0, $s3, FILE_CORE_VBD
nop
nop
.org 0x80059C04
addiu $a0, $s3, FILE_CORE_VBD
nop
nop
.org 0x80014D88
addiu $a0, $s6, FILE_DO2
nop
nop
.org 0x80015094
addiu $a0, $v1, FILE_DO2
nop
nop
sll $a2, $v1, 1
addu $v1, $a2, $v1
sll $v1, 2
addu $v1, $v0
.close
|
MeganGrass/Resident-Evil-2-Starter-Kit | 4,445 | source/assembly/disk/task.s |
/*
* BOOT.BIN
*/
LoadTaskBoot: equ 0 ;; Task_no
LoadTaskFileBoot: equ BOOT_BIN ;; File_no
LoadTaskAddrBoot: equ 0x80190000 ;; Ld_adr
LoadTaskFuncBoot: equ 0x80190478 ;; Func
/*
* CONFIG.BIN
*/
LoadTaskConfig: equ 4 ;; Task_no
LoadTaskFileConfig: equ CONFIG_BIN ;; File_no
LoadTaskAddrConfig: equ 0x801BFA18 ;; Ld_adr
LoadTaskFuncConfig: equ 0x801BFA84 ;; Func
/*
* DEBUG.BIN
*/
LoadTaskDebug: equ 9 ;; Task_no
LoadTaskFileDebug: equ DEBUG_BIN ;; File_no
LoadTaskAddrDebug: equ 0x801BFA18 ;; Ld_adr
LoadTaskFuncDebug: equ 0x801BFD1C ;; Func
/*
* DIEDEMO.BIN
*/
LoadTaskDieDemo: equ 2 ;; Task_no
LoadTaskFileDieDemo: equ DIEDEMO_BIN ;; File_no
LoadTaskAddrDieDemo: equ 0x80190000 ;; Ld_adr
LoadTaskFuncDieDemo: equ 0x8019009C ;; Func
/*
* ENDING.BIN
*/
LoadTaskEnding: equ 6 ;; Task_no
LoadTaskFileEnding: equ ENDING_BIN ;; File_no
LoadTaskAddrEnding: equ 0x8011A000 ;; Ld_adr
LoadTaskFuncEnding: equ 0x8011A0FC ;; Func
/*
* MEM_CARD.BIN
*/
LoadTaskMemCard: equ 1 ;; Task_no
LoadTaskFileMemory: equ MEM_CARD_BIN ;; File_no
LoadTaskAddrMemory: equ 0x801BFA18 ;; Ld_adr
LoadTaskFuncMemory: equ 0x801BFD14 ;; Func
/*
* OPENING.BIN
*/
LoadTaskOpening: equ 5 ;; Task_no
LoadTaskFileOpening: equ OPENING_BIN ;; File_no
LoadTaskAddrOpening: equ 0x801BFA18 ;; Ld_adr
LoadTaskFuncOpening: equ 0x801BFAD8 ;; Func
/*
* RESULT.BIN
*/
LoadTaskResult: equ 7 ;; Task_no
LoadTaskFileResult: equ RESULT_BIN ;; File_no
LoadTaskAddrResult: equ 0x80158000 ;; Ld_adr
LoadTaskFuncResult: equ 0x80158020 ;; Func
/*
* ROOMJUMP.BIN
*/
LoadTaskRoomJump: equ 8 ;; Task_no
LoadTaskFileRoomJump: equ ROOMJUMP_BIN ;; File_no
LoadTaskAddrRoomJump: equ 0x801BFA18 ;; Ld_adr
LoadTaskFuncRoomJump: equ 0x801BFA54 ;; Func
/*
* SELECT.BIN
*/
LoadTaskSelect: equ 3 ;; Task_no
LoadTaskFileSelect: equ SELECT_BIN ;; File_no
LoadTaskAddrSelect: equ 0x801BFA18 ;; Ld_adr
LoadTaskFuncSelect: equ 0x801BFAA8 ;; Func
/*
* TITLE.BIN
*/
;;LoadTaskTitle: equ 0 ;; Task_no
;;LoadTaskFileTitle: equ TITLE_BIN ;; File_no
;;LoadTaskAddrTitle: equ 0x80190000 ;; Ld_adr
;;LoadTaskFuncTitle: equ 0x80191808 ;; Func
/*
* Task_lexecute
*
* Patch to read direct pointer
*/
.org 0x80031EA0
lui at, (Ld_task_tbl >> 16)
addu at, $s0
lw $a1, (Ld_task_tbl & 0xFFFF)+8(at)
.org 0x80031EB8
nop
/*
* Task_lchain
*
* Patch to read direct pointer
*/
.org 0x80031F18
lui at, (Ld_task_tbl >> 16)
addu at, $s0
lw $a1, (Ld_task_tbl & 0xFFFF)+8(at)
.org 0x80031F30
nop
/*
* Ld_task_tbl
*/
.org Ld_task_tbl
.word LoadTaskFileBoot ;; File_no ;; BOOT
.word LoadTaskFuncBoot ;; Func
.word LoadTaskAddrBoot ;; Ld_adr
.word LoadTaskFileMemory ;; File_no ;; MEM_CARD
.word LoadTaskFuncMemory ;; Func
.word LoadTaskAddrMemory ;; Ld_adr
.word LoadTaskFileDieDemo ;; File_no ;; DIEDEMO
.word LoadTaskFuncDieDemo ;; Func
.word LoadTaskAddrDieDemo ;; Ld_adr
.word LoadTaskFileSelect ;; File_no ;; SELECT
.word LoadTaskFuncSelect ;; Func
.word LoadTaskAddrSelect ;; Ld_adr
.word LoadTaskFileConfig ;; File_no ;; CONFIG
.word LoadTaskFuncConfig ;; Func
.word LoadTaskAddrConfig ;; Ld_adr
.word LoadTaskFileOpening ;; File_no ;; OPENING
.word LoadTaskFuncOpening ;; Func
.word LoadTaskAddrOpening ;; Ld_adr
.word LoadTaskFileEnding ;; File_no ;; ENDING
.word LoadTaskFuncEnding ;; Func
.word LoadTaskAddrEnding ;; Ld_adr
.word LoadTaskFileResult ;; File_no ;; RESULT
.word LoadTaskFuncResult ;; Func
.word LoadTaskAddrResult ;; Ld_adr
.word LoadTaskFileRoomJump ;; File_no ;; ROOMJUMP
.word LoadTaskFuncRoomJump ;; Func
.word LoadTaskAddrRoomJump ;; Ld_adr
.word LoadTaskFileDebug ;; File_no ;; DEBUG
.word LoadTaskFuncDebug ;; Func
.word LoadTaskAddrDebug ;; Ld_adr
.word 0x00000000 ;; File_no ;;
.word 0x00000000 ;; Func
.word 0x00000000 ;; Ld_adr
.word 0x00000000 ;; File_no ;;
.word 0x00000000 ;; Func
.word 0x00000000 ;; Ld_adr
.word 0x00000000 ;; File_no ;;
.word 0x00000000 ;; Func
.word 0x00000000 ;; Ld_adr
.word 0x00000000 ;; File_no ;;
.word 0x00000000 ;; Func
.word 0x00000000 ;; Ld_adr
.word 0x00000000 ;; File_no ;;
.word 0x00000000 ;; Func
.word 0x00000000 ;; Ld_adr
|
MeganGrass/Resident-Evil-2-Starter-Kit | 4,164 | source/assembly/disk/filecode.s | BOOT_BIN: equ 0
CONFIG_BIN: equ 1
DEBUG_BIN: equ 2
DIEDEMO_BIN: equ 3
ENDING_BIN: equ 4
MEM_CARD_BIN: equ 5
OPENING_BIN: equ 6
RESULT_BIN: equ 7
ROOMJUMP_BIN: equ 8
SELECT_BIN: equ 9
PDEMO00_DAT: equ 15
PDEMO01_DAT: equ 16
PDEMO02_DAT: equ 17
PDEMO10_DAT: equ 18
PDEMO11_DAT: equ 19
PDEMO12_DAT: equ 20
ROOM800_SND: equ 21
CLEAR1_PIX: equ 140
CLEAR2_PIX: equ 141
COLOR_TIM: equ 142
CONFIG_TIM: equ 143
CORE00_ESP: equ 144
CORE01_TIM: equ 145
DIED00_DIE: equ 146
DIED01_DIE: equ 147
DIED0B_DIE: equ 148
DIED0C_DIE: equ 149
DIED0D_DIE: equ 150
DIED0E_DIE: equ 151
DIED0F_DIE: equ 152
END00_TIM: equ 153
END10_TIM: equ 154
END11_TIM: equ 155
END12_TIM: equ 156
END13_TIM: equ 157
END14_TIM: equ 158
END15_TIM: equ 159
END16_TIM: equ 160
END17_TIM: equ 161
END18_TIM: equ 162
END19_TIM: equ 163
EXTITLE_TIM: equ 164
EXTITLE1_TIM: equ 165
FILES_TIM: equ 166
GWARNING_TIM: equ 167
INIT_TBL_DAT: equ 168
ITEMALL_PIX: equ 169
ITPS_ITP: equ 170
MAPS_PIX: equ 171
MIX_PIX: equ 172
OPEN00_TIM: equ 173
OPEN01_TIM: equ 174
OPEN02_TIM: equ 175
OPEN03_TIM: equ 176
OPEN04_TIM: equ 177
OPEN05_TIM: equ 178
OPEN06_TIM: equ 179
OPEN07_TIM: equ 180
OPEN10_TIM: equ 181
OPEN11_TIM: equ 182
OPEN12_TIM: equ 183
OPEN13_TIM: equ 184
OPEN14_TIM: equ 185
OPNC_CPT: equ 186
OPNL_CPT: equ 187
OPNW_CPT: equ 188
PADDDSU_TIM: equ 189
PADDU_TIM: equ 190
R108_CPT: equ 191
R204C16_PIX: equ 192
R204L16_PIX: equ 193
R40X_CPT: equ 194
R700C_CPT: equ 195
R700L_CPT: equ 196
R703C_CPT: equ 197
R703L_CPT: equ 198
R704C_CPT: equ 199
R704L_CPT: equ 200
RES_MOJI_TIM: equ 201
RESULT_TIM: equ 202
SELECT_TIM: equ 203
SELECTH_TIM: equ 204
SELECTH2_TIM: equ 205
SELECTH3_TIM: equ 206
SELECT_B_TIM: equ 207
SELECT_W_TIM: equ 208
SPY_LOGO_TIM: equ 209
ST0_TIM: equ 210
ST1_TIM: equ 211
ST1__TIM: equ 212
ST1_FONT_TIM: equ 213
ST2_FONT_TIM: equ 214
ST3_FONT_TIM: equ 215
ST4_FONT_TIM: equ 216
ST5_FONT_TIM: equ 217
ST6_FONT_TIM: equ 218
ST7_FONT_TIM: equ 219
ST_FILE_TIM: equ 220
ST_FILE_TM2: equ 221
ST_FILE_TS: equ 222
ST_MOJI_TIM: equ 223
STG_NXT: equ 224
TEX_TIM: equ 225
TEX_PAL_TIM: equ 226
TITLE_O_TIM: equ 227
TITLE_O2_TIM: equ 228
TIT_BG_TIM: equ 229
TMOJI_TIM: equ 230
TOFULOGO_TIM: equ 231
TYPE00_PIX: equ 232
WARNING_TIM: equ 233
BSS01_CDX: equ 234
BSS02_CDX: equ 235
BSS03_CDX: equ 236
BSS04_CDX: equ 237
BSS05_CDX: equ 238
BSS06_CDX: equ 239
BSS07_CDX: equ 240
DO2_CDX: equ 241
EMD00_CDX: equ 242
EMD01_CDX: equ 243
PLD_CDX: equ 244
PLW00_CDX: equ 245
PLW01_CDX: equ 246
PLW02_CDX: equ 247
PLW03_CDX: equ 248
PLW04_CDX: equ 249
PLW05_CDX: equ 250
PLW06_CDX: equ 251
PLW07_CDX: equ 252
PLW08_CDX: equ 253
PLW09_CDX: equ 254
PLW0A_CDX: equ 255
PLW0B_CDX: equ 256
PLW0C_CDX: equ 257
PLW0D_CDX: equ 258
PLW0E_CDX: equ 259
PLW0F_CDX: equ 260
SNDARMS_CDX: equ 261
SNDCORE_CDX: equ 262
SNDEMD_CDX: equ 263
SNDMAIN_CDX: equ 264
SNDSUB_CDX: equ 265
STG0001_CDX: equ 266
STG0002_CDX: equ 267
STG0003_CDX: equ 268
STG0004_CDX: equ 269
STG0005_CDX: equ 270
STG0006_CDX: equ 271
STG0007_CDX: equ 272
STG0101_CDX: equ 273
STG0102_CDX: equ 274
STG0103_CDX: equ 275
STG0104_CDX: equ 276
STG0105_CDX: equ 277
STG0106_CDX: equ 278
STG0107_CDX: equ 279
STGEX01_CDX: equ 280
STGEX02_CDX: equ 281
STGEX03_CDX: equ 282
STGEX04_CDX: equ 283
STGEX05_CDX: equ 284
STGEX06_CDX: equ 285
STGEX07_CDX: equ 286
VOICE00_XAS: equ 287
VOICE01_XAS: equ 288
VOICE02_XAS: equ 289
VOICE03_XAS: equ 290
VOICE04_XAS: equ 291
VOICE05_XAS: equ 292
VOICE06_XAS: equ 293
VOICE07_XAS: equ 294
VOICE08_XAS: equ 295
VOICE09_XAS: equ 296
VOICE10_XAS: equ 297
VOICE11_XAS: equ 298
VOICE12_XAS: equ 299
VOICE13_XAS: equ 300
VOICE14_XAS: equ 301
VOICE15_XAS: equ 302
VOICE16_XAS: equ 303
VOICE17_XAS: equ 304
VOICE18_XAS: equ 305
VOICE19_XAS: equ 306
MAX_FILE: equ 307 |
MeganGrass/Resident-Evil-2-Starter-Kit | 2,825 | source/assembly/player/Player_move.s |
;; Add quick-turn to pl_mv03_pad
/*
* Relocate Pl_mv table
*/
.org 0x8003C5CC
lui $v1, (pPlMvTbl >> 16)
addu $v1, $v0
lw $v0, (pPlMvTbl & 0xFFFF)($v1)
/*
* Relocate Pl_mv_pad table
*/
.org 0x8003C5A4
lui $v1, (pPlMvPadTbl >> 16)
addu $v1, $v0
lw $v0, (pPlMvPadTbl & 0xFFFF)($v1)
/*
* Pl_mv
*/
.org pPlMvTbl
.word pl_mv00 // Idle
.word pl_mv01 // Walk-Forward
.word pl_mv02 // Run
.word pl_mv03 // Walk-Backward
.word pl_mv04 // Turn
.word pl_mv05 // Aim
.word pl_mv06 // Kneel to pickup Item
.word pl_mv07 // Turn toward stairs + stairs routine
.word pl_mv08 // Climb Up
.word pl_mv09 // Jump Down
.word pl_mv0a // Push Object
.word pl_mv0b // Rotate to divisible of 1024, walk forward
.word pl_mv0c // Quick-Turn
.word 0
.word 0
.word 0
/*
* Pl_mv_pad
*/
.org pPlMvPadTbl
.word Plmv00_pad // Idle
.word pl_mv01_pad // Walk-Forward
.word pl_mv02_pad // Run
.word pl_mv03_pad // Walk-Backward
.word pl_mv04_pad // Turn
.word pl_mv05_pad // Aim
.word pl_mv06_pad // Kneel to pickup Item
.word pl_mv07_pad // Turn toward stairs + stairs routine
.word pl_mv08_pad // Climb Up
.word pl_mv09_pad // Jump Down
.word pl_mv0a_pad // Push Object
.word pl_mv0b_pad // Rotate to divisible of 1024, walk forward
.word pl_mv06_pad // Quick-Turn, using pl_mv06_pad (null func)
.word 0
.word 0
.word 0
/*
* Patch pl_mv03 to call pl_mv03_action
*/
.org 0x8003d944
jal pl_mv03_action
nop
/*
* Patch pl_mv05_w1_t1 to call pl_mv05_action
*/
.org 0x800438a4
move $a0, $s0 // pEm
move $a1, $s2 // Kan
move $a2, $s3 // Seq
jal pl_mv05_action
move $a3, $s1 // Key
j 0x800438e8
nop
/*
* Patch pl_mv05_w2_t1 to call pl_mv05_action
*/
.org 0x80047c08
move $a0, $s0 // pEm
move $a1, $s2 // Kan
move $a2, $s3 // Seq
jal pl_mv05_action
move $a3, $s1 // Key
j 0x80047c4c
nop
/*
* Patch pl_mv05_w1_t4 to call rewritten Tama_reload
*/
.org 0x80045b0c
jal TamaReload
move $a0, $s0 // pEm
/*
* Patch pl_mv05_w2_t4 to call rewritten Tama_reload
*/
.org 0x800482ac
jal TamaReload
move $a0, $s0 // pEm
/*
* remove G.System_flg requirements for auto-aim during pl_mv05_w1_t0
*
* Control Type C is kept as a requirement
*/
.org 0x80043458
nop
nop
nop
nop
nop
nop
/*
* remove G.System_flg requirements for target change during pl_mv05_w1_t1
*
* Control Type C is kept as a requirement
*/
.org 0x800437e8
nop
nop
nop
nop
nop
nop
/*
* remove G.System_flg requirements for target change during pl_mv05_w2_t1
*
* Control Type C is kept as a requirement
*/
.org 0x80047b68
nop
nop
nop
nop
nop
nop
|
MeganGrass/Resident-Evil-2-Starter-Kit | 1,225 | source/assembly/player/Pl_weapon_ch.s |
.org Pl_weapon_ch
;; Stack
addiu $sp, -0x58
sw $s4, 0x58+-0x18($sp)
move $s4, $a0 ;; PLAYER_WORK
sw $s3, 0x58+-0x1C($sp)
lw $s3, G_pPl_emd_top
sw $ra, 0x58+-0x04($sp)
sw $fp, 0x58+-0x08($sp)
sw $s7, 0x58+-0x0C($sp)
sw $s6, 0x58+-0x10($sp)
sw $s5, 0x58+-0x14($sp)
sw $s2, 0x58+-0x20($sp)
sw $s1, 0x58+-0x24($sp)
sw $s0, 0x58+-0x28($sp)
addiu $s5, $s3, 0xD70 ;; Address
sw $s3, 0x58+-0x30($sp)
move $s0, $s5 ;; Address
;; Update Plw Index?
li $v0, pPlwIndex+0xA0
lw $a0, 0($v0)
lbu $v1, Player_Id
nop
beq $a0, $v1, @ReadIndex
nop
jal Load_plw_index
nop
@ReadIndex:
la $a0, pPlwIndex
lh $v0, Player_Type
nop
li $v1, 0x14
bge $v0, $v1, @Complete ;; 2024, ensure unsupported ids dont get through
nop
li $v1, 8
multu $v1, $v0
mflo $v1
addu $v0, $v1, $a0 ;; LBA Index
;; Load PLW
lw $a0, 0x04($v0) ;; Sector
lw $a1, 0x00($v0) ;; Size
move $a2, $s5 ;; Address
jal Cd_read_ex
li $a3, 0 ;; Auto-Parse Index
@Complete:
j 0x800409B4
nop
|
MeganGrass/Resident-Evil-2-Starter-Kit | 12,815 | source/assembly/enemy/emd00.s | .org emd00_pos
.word 0x00000000, 0x0000CF4C ;; EMD1000
.word 0x0000001A, 0x0000CF4C ;; EMD1001
.word 0x00000034, 0x00010420 ;; EMD10
.word 0x00000055, 0x00023DCC ;; EMD10
.word 0x00000000, 0x00000000 ;; EMD1100
.word 0x00000000, 0x00000000 ;; EMD1101
.word 0x0000009D, 0x00010420 ;; EMD11
.word 0x000000BE, 0x000247DC ;; EMD11
.word 0x00000000, 0x00000000 ;; EMD1200
.word 0x00000000, 0x00000000 ;; EMD1201
.word 0x00000107, 0x00020820 ;; EMD12
.word 0x00000149, 0x00023B5C ;; EMD12
.word 0x00000000, 0x00000000 ;; EMD1300
.word 0x00000000, 0x00000000 ;; EMD1301
.word 0x00000191, 0x00010420 ;; EMD13
.word 0x000001B2, 0x00023D2C ;; EMD13
.word 0x00000000, 0x00000000 ;; EMD1400
.word 0x00000000, 0x00000000 ;; EMD1401
.word 0x00000000, 0x00000000 ;; EMD14
.word 0x00000000, 0x00000000 ;; EMD14
.word 0x00000000, 0x00000000 ;; EMD1500
.word 0x00000000, 0x00000000 ;; EMD1501
.word 0x000001FA, 0x00010420 ;; EMD15
.word 0x0000021B, 0x00023CAC ;; EMD15
.word 0x00000000, 0x00000000 ;; EMD1600
.word 0x00000000, 0x00000000 ;; EMD1601
.word 0x00000263, 0x00010420 ;; EMD16
.word 0x00000284, 0x00023A5C ;; EMD16
.word 0x00000000, 0x00000000 ;; EMD1700
.word 0x00000000, 0x00000000 ;; EMD1701
.word 0x000002CC, 0x00010420 ;; EMD17
.word 0x000002ED, 0x00024E98 ;; EMD17
.word 0x00000000, 0x00000000 ;; EMD1800
.word 0x00000000, 0x00000000 ;; EMD1801
.word 0x00000337, 0x00010420 ;; EMD18
.word 0x00000358, 0x00022604 ;; EMD18
.word 0x00000000, 0x00000000 ;; EMD1900
.word 0x00000000, 0x00000000 ;; EMD1901
.word 0x00000000, 0x00000000 ;; EMD19
.word 0x00000000, 0x00000000 ;; EMD19
.word 0x00000000, 0x00000000 ;; EMD1A00
.word 0x00000000, 0x00000000 ;; EMD1A01
.word 0x00000000, 0x00000000 ;; EMD1A
.word 0x00000000, 0x00000000 ;; EMD1A
.word 0x00000000, 0x00000000 ;; EMD1B00
.word 0x00000000, 0x00000000 ;; EMD1B01
.word 0x00000000, 0x00000000 ;; EMD1B
.word 0x00000000, 0x00000000 ;; EMD1B
.word 0x00000000, 0x00000000 ;; EMD1C00
.word 0x00000000, 0x00000000 ;; EMD1C01
.word 0x00000000, 0x00000000 ;; EMD1C
.word 0x00000000, 0x00000000 ;; EMD1C
.word 0x00000000, 0x00000000 ;; EMD1D00
.word 0x00000000, 0x00000000 ;; EMD1D01
.word 0x00000000, 0x00000000 ;; EMD1D
.word 0x00000000, 0x00000000 ;; EMD1D
.word 0x00000000, 0x00000000 ;; EMD1E00
.word 0x00000000, 0x00000000 ;; EMD1E01
.word 0x0000039D, 0x00020820 ;; EMD1E
.word 0x000003DF, 0x00022798 ;; EMD1E
.word 0x00000000, 0x00000000 ;; EMD1F00
.word 0x00000000, 0x00000000 ;; EMD1F01
.word 0x00000424, 0x00020820 ;; EMD1F
.word 0x00000466, 0x00022604 ;; EMD1F
.word 0x000004AB, 0x000056FA ;; EMD2000
.word 0x000004B6, 0x000056FA ;; EMD2001
.word 0x000004C1, 0x00010420 ;; EMD20
.word 0x000004E2, 0x0001D938 ;; EMD20
.word 0x0000051E, 0x00004A88 ;; EMD2100
.word 0x00000528, 0x00004A88 ;; EMD2101
.word 0x00000532, 0x00008220 ;; EMD21
.word 0x00000543, 0x00007E28 ;; EMD21
.word 0x00000553, 0x00007698 ;; EMD2200
.word 0x00000562, 0x00007698 ;; EMD2201
.word 0x00000571, 0x00010420 ;; EMD22
.word 0x00000592, 0x0002AB74 ;; EMD22
.word 0x000005E8, 0x000048E8 ;; EMD2300
.word 0x000005F2, 0x000048E8 ;; EMD2301
.word 0x000005FC, 0x00020820 ;; EMD23
.word 0x0000063E, 0x0002E318 ;; EMD23
.word 0x0000069B, 0x00005DA0 ;; EMD2400
.word 0x000006A7, 0x00005DA0 ;; EMD2401
.word 0x000006B3, 0x00010420 ;; EMD24
.word 0x000006D4, 0x0001FAB0 ;; EMD24
.word 0x00000714, 0x000066D4 ;; EMD2500
.word 0x00000721, 0x000066D4 ;; EMD2501
.word 0x0000072E, 0x00010420 ;; EMD25
.word 0x0000074F, 0x0000D0C8 ;; EMD25
.word 0x0000076A, 0x000010FA ;; EMD2600
.word 0x0000076D, 0x000010FA ;; EMD2601
.word 0x00000770, 0x00008220 ;; EMD26
.word 0x00000781, 0x00001A14 ;; EMD26
.word 0x00000785, 0x0000389C ;; EMD2700
.word 0x0000078D, 0x0000389C ;; EMD2701
.word 0x00000795, 0x00008220 ;; EMD27
.word 0x000007A6, 0x00009AD0 ;; EMD27
.word 0x000007BA, 0x000067B0 ;; EMD2800
.word 0x000007C7, 0x000067B0 ;; EMD2801
.word 0x000007D4, 0x00020820 ;; EMD28
.word 0x00000816, 0x0002DF0C ;; EMD28
.word 0x00000872, 0x00001EFC ;; EMD2900
.word 0x00000876, 0x00001EFC ;; EMD2901
.word 0x0000087A, 0x00008220 ;; EMD29
.word 0x0000088B, 0x00003110 ;; EMD29
.word 0x00000892, 0x00004F10 ;; EMD2A00
.word 0x0000089C, 0x00004F10 ;; EMD2A01
.word 0x000008A6, 0x00010420 ;; EMD2A
.word 0x000008C7, 0x00021C84 ;; EMD2A
.word 0x0000090B, 0x00004D68 ;; EMD2B00
.word 0x00000915, 0x00004D68 ;; EMD2B01
.word 0x0000091F, 0x00018620 ;; EMD2B
.word 0x00000950, 0x00022278 ;; EMD2B
.word 0x00000995, 0x000001F4 ;; EMD2C00
.word 0x00000996, 0x000001F4 ;; EMD2C01
.word 0x00000997, 0x00008220 ;; EMD2C
.word 0x000009A8, 0x00003E5C ;; EMD2C
.word 0x000009B0, 0x00001528 ;; EMD2D00
.word 0x000009B3, 0x00001528 ;; EMD2D01
.word 0x000009B6, 0x00008220 ;; EMD2D
.word 0x000009C7, 0x00006020 ;; EMD2D
.word 0x000009D4, 0x00005A7A ;; EMD2E00
.word 0x000009E0, 0x00005A7A ;; EMD2E01
.word 0x000009EC, 0x00010420 ;; EMD2E
.word 0x00000A0D, 0x00034ECC ;; EMD2E
.word 0x00000A77, 0x00002464 ;; EMD2F00
.word 0x00000A7C, 0x00002464 ;; EMD2F01
.word 0x00000A81, 0x00008220 ;; EMD2F
.word 0x00000A92, 0x00001578 ;; EMD2F
.word 0x00000A95, 0x000076AC ;; EMD3000
.word 0x00000AA4, 0x000076AC ;; EMD3001
.word 0x00000AB3, 0x00018620 ;; EMD30
.word 0x00000AE4, 0x0002527C ;; EMD30
.word 0x00000B2F, 0x00007D58 ;; EMD3100
.word 0x00000B3F, 0x00007D58 ;; EMD3101
.word 0x00000B4F, 0x00018620 ;; EMD31
.word 0x00000B80, 0x0002F264 ;; EMD31
.word 0x00000000, 0x00000000 ;; EMD3200
.word 0x00000000, 0x00000000 ;; EMD3201
.word 0x00000000, 0x00000000 ;; EMD32
.word 0x00000000, 0x00000000 ;; EMD32
.word 0x00000BDF, 0x000067B8 ;; EMD3300
.word 0x00000BEC, 0x000067B8 ;; EMD3301
.word 0x00000BF9, 0x00018620 ;; EMD33
.word 0x00000C2A, 0x000320A8 ;; EMD33
.word 0x00000C8F, 0x0000B2D4 ;; EMD3400
.word 0x00000CA6, 0x0000B2D4 ;; EMD3401
.word 0x00000CBD, 0x00018620 ;; EMD34
.word 0x00000CEE, 0x00042D94 ;; EMD34
.word 0x00000000, 0x00000000 ;; EMD3500
.word 0x00000000, 0x00000000 ;; EMD3501
.word 0x00000000, 0x00000000 ;; EMD35
.word 0x00000000, 0x00000000 ;; EMD35
.word 0x00000D74, 0x00005BB4 ;; EMD3600
.word 0x00000D80, 0x00005BB4 ;; EMD3601
.word 0x00000D8C, 0x00020620 ;; EMD36
.word 0x00000DCD, 0x0001B6D4 ;; EMD36
.word 0x00000E04, 0x000059F0 ;; EMD3700
.word 0x00000E10, 0x000059F0 ;; EMD3701
.word 0x00000E1C, 0x00008220 ;; EMD37
.word 0x00000E2D, 0x0000E7F0 ;; EMD37
.word 0x00000000, 0x00000000 ;; EMD3800
.word 0x00000000, 0x00000000 ;; EMD3801
.word 0x00000000, 0x00000000 ;; EMD38
.word 0x00000000, 0x00000000 ;; EMD38
.word 0x00000E4A, 0x00005A7A ;; EMD3900
.word 0x00000E56, 0x00005A7A ;; EMD3901
.word 0x00000E62, 0x00010420 ;; EMD39
.word 0x00000E83, 0x00034ECC ;; EMD39
.word 0x00000EED, 0x00004E80 ;; EMD3A00
.word 0x00000EF7, 0x00004E80 ;; EMD3A01
.word 0x00000F01, 0x00010420 ;; EMD3A
.word 0x00000F22, 0x0000AA5C ;; EMD3A
.word 0x00000F38, 0x000014D6 ;; EMD3B00
.word 0x00000F3B, 0x000014D6 ;; EMD3B01
.word 0x00000F3E, 0x00008220 ;; EMD3B
.word 0x00000F4F, 0x00000D98 ;; EMD3B
.word 0x00000000, 0x00000000 ;; EMD3C00
.word 0x00000000, 0x00000000 ;; EMD3C01
.word 0x00000000, 0x00000000 ;; EMD3C
.word 0x00000000, 0x00000000 ;; EMD3C
.word 0x00000000, 0x00000000 ;; EMD3D00
.word 0x00000000, 0x00000000 ;; EMD3D01
.word 0x00000000, 0x00000000 ;; EMD3D
.word 0x00000000, 0x00000000 ;; EMD3D
.word 0x00000F51, 0x00000270 ;; EMD3E00
.word 0x00000F52, 0x00000270 ;; EMD3E01
.word 0x00000F53, 0x00008220 ;; EMD3E
.word 0x00000F64, 0x0000D810 ;; EMD3E
.word 0x00000F80, 0x0000037C ;; EMD3F00
.word 0x00000F81, 0x0000037C ;; EMD3F01
.word 0x00000F82, 0x00008220 ;; EMD3F
.word 0x00000F93, 0x00006574 ;; EMD3F
.word 0x00000000, 0x00000000 ;; EMD4000
.word 0x00000000, 0x00000000 ;; EMD4001
.word 0x00000FA0, 0x00018620 ;; EMD40
.word 0x00000FD1, 0x0000D648 ;; EMD40
.word 0x00000000, 0x00000000 ;; EMD4100
.word 0x00000000, 0x00000000 ;; EMD4101
.word 0x00000FEC, 0x00010420 ;; EMD41
.word 0x0000100D, 0x00012DF0 ;; EMD41
.word 0x00000000, 0x00000000 ;; EMD4200
.word 0x00000000, 0x00000000 ;; EMD4201
.word 0x00000000, 0x00000000 ;; EMD42
.word 0x00000000, 0x00000000 ;; EMD42
.word 0x00000000, 0x00000000 ;; EMD4300
.word 0x00000000, 0x00000000 ;; EMD4301
.word 0x00001033, 0x00018620 ;; EMD43
.word 0x00001064, 0x00012DF0 ;; EMD43
.word 0x00000000, 0x00000000 ;; EMD4400
.word 0x00000000, 0x00000000 ;; EMD4401
.word 0x0000108A, 0x00018620 ;; EMD44
.word 0x000010BB, 0x00012638 ;; EMD44
.word 0x00000000, 0x00000000 ;; EMD4500
.word 0x00000000, 0x00000000 ;; EMD4501
.word 0x000010E0, 0x00010420 ;; EMD45
.word 0x00001101, 0x000120FC ;; EMD45
.word 0x00000000, 0x00000000 ;; EMD4600
.word 0x00000000, 0x00000000 ;; EMD4601
.word 0x00001126, 0x00018620 ;; EMD46
.word 0x00001157, 0x00012638 ;; EMD46
.word 0x00000000, 0x00000000 ;; EMD4700
.word 0x00000000, 0x00000000 ;; EMD4701
.word 0x0000117C, 0x00018620 ;; EMD47
.word 0x000011AD, 0x0000C834 ;; EMD47
.word 0x00000000, 0x00000000 ;; EMD4800
.word 0x00000000, 0x00000000 ;; EMD4801
.word 0x000011C7, 0x00018620 ;; EMD48
.word 0x000011F8, 0x0000789C ;; EMD48
.word 0x00000000, 0x00000000 ;; EMD4900
.word 0x00000000, 0x00000000 ;; EMD4901
.word 0x00001208, 0x00018620 ;; EMD49
.word 0x00001239, 0x0000C834 ;; EMD49
.word 0x00000000, 0x00000000 ;; EMD4A00
.word 0x00000000, 0x00000000 ;; EMD4A01
.word 0x00001253, 0x00018620 ;; EMD4A
.word 0x00001284, 0x00027338 ;; EMD4A
.word 0x00000000, 0x00000000 ;; EMD4B00
.word 0x00000000, 0x00000000 ;; EMD4B01
.word 0x00000000, 0x00000000 ;; EMD4B
.word 0x00000000, 0x00000000 ;; EMD4B
.word 0x00000000, 0x00000000 ;; EMD4C00
.word 0x00000000, 0x00000000 ;; EMD4C01
.word 0x00000000, 0x00000000 ;; EMD4C
.word 0x00000000, 0x00000000 ;; EMD4C
.word 0x00000000, 0x00000000 ;; EMD4D00
.word 0x00000000, 0x00000000 ;; EMD4D01
.word 0x00000000, 0x00000000 ;; EMD4D
.word 0x00000000, 0x00000000 ;; EMD4D
.word 0x00000000, 0x00000000 ;; EMD4E00
.word 0x00000000, 0x00000000 ;; EMD4E01
.word 0x00000000, 0x00000000 ;; EMD4E
.word 0x00000000, 0x00000000 ;; EMD4E
.word 0x00000000, 0x00000000 ;; EMD4F00
.word 0x00000000, 0x00000000 ;; EMD4F01
.word 0x000012D3, 0x00010420 ;; EMD4F
.word 0x000012F4, 0x0001230C ;; EMD4F
.word 0x00000000, 0x00000000 ;; EMD5000
.word 0x00000000, 0x00000000 ;; EMD5001
.word 0x00001319, 0x00018620 ;; EMD50
.word 0x0000134A, 0x000124D8 ;; EMD50
.word 0x00000000, 0x00000000 ;; EMD5100
.word 0x00000000, 0x00000000 ;; EMD5101
.word 0x0000136F, 0x00010420 ;; EMD51
.word 0x00001390, 0x00012AE4 ;; EMD51
.word 0x00000000, 0x00000000 ;; EMD5200
.word 0x00000000, 0x00000000 ;; EMD5201
.word 0x00000000, 0x00000000 ;; EMD52
.word 0x00000000, 0x00000000 ;; EMD52
.word 0x00000000, 0x00000000 ;; EMD5300
.word 0x00000000, 0x00000000 ;; EMD5301
.word 0x00000000, 0x00000000 ;; EMD53
.word 0x00000000, 0x00000000 ;; EMD53
.word 0x00000000, 0x00000000 ;; EMD5400
.word 0x00000000, 0x00000000 ;; EMD5401
.word 0x000013B6, 0x00010420 ;; EMD54
.word 0x000013D7, 0x000124D8 ;; EMD54
.word 0x00000000, 0x00000000 ;; EMD5500
.word 0x00000000, 0x00000000 ;; EMD5501
.word 0x000013FC, 0x00010420 ;; EMD55
.word 0x0000141D, 0x00012A34 ;; EMD55
.word 0x00000000, 0x00000000 ;; EMD5600
.word 0x00000000, 0x00000000 ;; EMD5601
.word 0x00000000, 0x00000000 ;; EMD56
.word 0x00000000, 0x00000000 ;; EMD56
.word 0x00000000, 0x00000000 ;; EMD5700
.word 0x00000000, 0x00000000 ;; EMD5701
.word 0x00000000, 0x00000000 ;; EMD57
.word 0x00000000, 0x00000000 ;; EMD57
.word 0x00000000, 0x00000000 ;; EMD5800
.word 0x00000000, 0x00000000 ;; EMD5801
.word 0x00001443, 0x00010420 ;; EMD58
.word 0x00001464, 0x000124F0 ;; EMD58
.word 0x00000000, 0x00000000 ;; EMD5900
.word 0x00000000, 0x00000000 ;; EMD5901
.word 0x00001489, 0x00018620 ;; EMD59
.word 0x000014BA, 0x00012C2C ;; EMD59
.word 0x00000000, 0x00000000 ;; EMD5A00
.word 0x00000000, 0x00000000 ;; EMD5A01
.word 0x000014E0, 0x00018620 ;; EMD5A
.word 0x00001511, 0x000130F0 ;; EMD5A
.word 0x00000000, 0x00000000 ;; EMD5B00
.word 0x00000000, 0x00000000 ;; EMD5B01
.word 0x00000000, 0x00000000 ;; EMD5B
.word 0x00000000, 0x00000000 ;; EMD5B
.word 0x00000000, 0x00000000 ;; EMD5C00
.word 0x00000000, 0x00000000 ;; EMD5C01
.word 0x00000000, 0x00000000 ;; EMD5C
.word 0x00000000, 0x00000000 ;; EMD5C
.word 0x00000000, 0x00000000 ;; EMD5D00
.word 0x00000000, 0x00000000 ;; EMD5D01
.word 0x00000000, 0x00000000 ;; EMD5D
.word 0x00000000, 0x00000000 ;; EMD5D
.word 0x00000000, 0x00000000 ;; EMD5E00
.word 0x00000000, 0x00000000 ;; EMD5E01
.word 0x00000000, 0x00000000 ;; EMD5E
.word 0x00000000, 0x00000000 ;; EMD5E
.word 0x00000000, 0x00000000 ;; EMD5F00
.word 0x00000000, 0x00000000 ;; EMD5F01
.word 0x00000000, 0x00000000 ;; EMD5F
.word 0x00000000, 0x00000000 ;; EMD5F
|
MeganGrass/Resident-Evil-2-Starter-Kit | 12,815 | source/assembly/enemy/emd01.s | .org emd01_pos
.word 0x00000000, 0x0000CF4C ;; EMD1000
.word 0x0000001A, 0x0000CF4C ;; EMD1001
.word 0x00000034, 0x00010420 ;; EMD10
.word 0x00000055, 0x00023F60 ;; EMD10
.word 0x00000000, 0x00000000 ;; EMD1100
.word 0x00000000, 0x00000000 ;; EMD1101
.word 0x0000009D, 0x00010420 ;; EMD11
.word 0x000000BE, 0x00024970 ;; EMD11
.word 0x00000000, 0x00000000 ;; EMD1200
.word 0x00000000, 0x00000000 ;; EMD1201
.word 0x00000108, 0x00020820 ;; EMD12
.word 0x0000014A, 0x00023CF0 ;; EMD12
.word 0x00000000, 0x00000000 ;; EMD1300
.word 0x00000000, 0x00000000 ;; EMD1301
.word 0x00000192, 0x00010420 ;; EMD13
.word 0x000001B3, 0x00023EC0 ;; EMD13
.word 0x00000000, 0x00000000 ;; EMD1400
.word 0x00000000, 0x00000000 ;; EMD1401
.word 0x00000000, 0x00000000 ;; EMD14
.word 0x00000000, 0x00000000 ;; EMD14
.word 0x00000000, 0x00000000 ;; EMD1500
.word 0x00000000, 0x00000000 ;; EMD1501
.word 0x000001FB, 0x00010420 ;; EMD15
.word 0x0000021C, 0x00023E40 ;; EMD15
.word 0x00000000, 0x00000000 ;; EMD1600
.word 0x00000000, 0x00000000 ;; EMD1601
.word 0x00000264, 0x00010420 ;; EMD16
.word 0x00000285, 0x00023BF0 ;; EMD16
.word 0x00000000, 0x00000000 ;; EMD1700
.word 0x00000000, 0x00000000 ;; EMD1701
.word 0x000002CD, 0x00010420 ;; EMD17
.word 0x000002EE, 0x0002502C ;; EMD17
.word 0x00000000, 0x00000000 ;; EMD1800
.word 0x00000000, 0x00000000 ;; EMD1801
.word 0x00000339, 0x00010420 ;; EMD18
.word 0x0000035A, 0x00022798 ;; EMD18
.word 0x00000000, 0x00000000 ;; EMD1900
.word 0x00000000, 0x00000000 ;; EMD1901
.word 0x00000000, 0x00000000 ;; EMD19
.word 0x00000000, 0x00000000 ;; EMD19
.word 0x00000000, 0x00000000 ;; EMD1A00
.word 0x00000000, 0x00000000 ;; EMD1A01
.word 0x00000000, 0x00000000 ;; EMD1A
.word 0x00000000, 0x00000000 ;; EMD1A
.word 0x00000000, 0x00000000 ;; EMD1B00
.word 0x00000000, 0x00000000 ;; EMD1B01
.word 0x00000000, 0x00000000 ;; EMD1B
.word 0x00000000, 0x00000000 ;; EMD1B
.word 0x00000000, 0x00000000 ;; EMD1C00
.word 0x00000000, 0x00000000 ;; EMD1C01
.word 0x00000000, 0x00000000 ;; EMD1C
.word 0x00000000, 0x00000000 ;; EMD1C
.word 0x00000000, 0x00000000 ;; EMD1D00
.word 0x00000000, 0x00000000 ;; EMD1D01
.word 0x00000000, 0x00000000 ;; EMD1D
.word 0x00000000, 0x00000000 ;; EMD1D
.word 0x00000000, 0x00000000 ;; EMD1E00
.word 0x00000000, 0x00000000 ;; EMD1E01
.word 0x0000039F, 0x00020820 ;; EMD1E
.word 0x000003E1, 0x00022798 ;; EMD1E
.word 0x00000000, 0x00000000 ;; EMD1F00
.word 0x00000000, 0x00000000 ;; EMD1F01
.word 0x00000426, 0x00020820 ;; EMD1F
.word 0x00000468, 0x00022798 ;; EMD1F
.word 0x000004AD, 0x000056FA ;; EMD2000
.word 0x000004B8, 0x000056FA ;; EMD2001
.word 0x000004C3, 0x00010420 ;; EMD20
.word 0x000004E4, 0x0001D938 ;; EMD20
.word 0x00000520, 0x00004A88 ;; EMD2100
.word 0x0000052A, 0x00004A88 ;; EMD2101
.word 0x00000534, 0x00008220 ;; EMD21
.word 0x00000545, 0x00007FCC ;; EMD21
.word 0x00000555, 0x00007698 ;; EMD2200
.word 0x00000564, 0x00007698 ;; EMD2201
.word 0x00000573, 0x00010420 ;; EMD22
.word 0x00000594, 0x0002AB70 ;; EMD22
.word 0x000005EA, 0x000048E8 ;; EMD2300
.word 0x000005F4, 0x000048E8 ;; EMD2301
.word 0x000005FE, 0x00020820 ;; EMD23
.word 0x00000640, 0x0002E318 ;; EMD23
.word 0x0000069D, 0x00005DA0 ;; EMD2400
.word 0x000006A9, 0x00005DA0 ;; EMD2401
.word 0x000006B5, 0x00010420 ;; EMD24
.word 0x000006D6, 0x0001FAB0 ;; EMD24
.word 0x00000716, 0x000066D4 ;; EMD2500
.word 0x00000723, 0x000066D4 ;; EMD2501
.word 0x00000730, 0x00010420 ;; EMD25
.word 0x00000751, 0x0000D0C8 ;; EMD25
.word 0x0000076C, 0x000010FA ;; EMD2600
.word 0x0000076F, 0x000010FA ;; EMD2601
.word 0x00000772, 0x00008220 ;; EMD26
.word 0x00000783, 0x00001BB8 ;; EMD26
.word 0x00000787, 0x0000389C ;; EMD2700
.word 0x0000078F, 0x0000389C ;; EMD2701
.word 0x00000797, 0x00008220 ;; EMD27
.word 0x000007A8, 0x00009AD0 ;; EMD27
.word 0x000007BC, 0x000067B0 ;; EMD2800
.word 0x000007C9, 0x000067B0 ;; EMD2801
.word 0x000007D6, 0x00020820 ;; EMD28
.word 0x00000818, 0x0002DF0C ;; EMD28
.word 0x00000874, 0x00001EFC ;; EMD2900
.word 0x00000878, 0x00001EFC ;; EMD2901
.word 0x0000087C, 0x00008220 ;; EMD29
.word 0x0000088D, 0x000028D8 ;; EMD29
.word 0x00000893, 0x00004F10 ;; EMD2A00
.word 0x0000089D, 0x00004F10 ;; EMD2A01
.word 0x000008A7, 0x00010420 ;; EMD2A
.word 0x000008C8, 0x00021C84 ;; EMD2A
.word 0x0000090C, 0x00004D68 ;; EMD2B00
.word 0x00000916, 0x00004D68 ;; EMD2B01
.word 0x00000920, 0x00018620 ;; EMD2B
.word 0x00000951, 0x00023484 ;; EMD2B
.word 0x00000998, 0x000001F4 ;; EMD2C00
.word 0x00000999, 0x000001F4 ;; EMD2C01
.word 0x0000099A, 0x00008220 ;; EMD2C
.word 0x000009AB, 0x00004000 ;; EMD2C
.word 0x000009B3, 0x00001528 ;; EMD2D00
.word 0x000009B6, 0x00001528 ;; EMD2D01
.word 0x000009B9, 0x00008220 ;; EMD2D
.word 0x000009CA, 0x00006020 ;; EMD2D
.word 0x000009D7, 0x00005A7A ;; EMD2E00
.word 0x000009E3, 0x00005A7A ;; EMD2E01
.word 0x000009EF, 0x00010420 ;; EMD2E
.word 0x00000A10, 0x00034ECC ;; EMD2E
.word 0x00000A7A, 0x00002464 ;; EMD2F00
.word 0x00000A7F, 0x00002464 ;; EMD2F01
.word 0x00000A84, 0x00008220 ;; EMD2F
.word 0x00000A95, 0x00001578 ;; EMD2F
.word 0x00000A98, 0x000076AC ;; EMD3000
.word 0x00000AA7, 0x000076AC ;; EMD3001
.word 0x00000AB6, 0x00018620 ;; EMD30
.word 0x00000AE7, 0x0002527C ;; EMD30
.word 0x00000B32, 0x00007D58 ;; EMD3100
.word 0x00000B42, 0x00007D58 ;; EMD3101
.word 0x00000B52, 0x00018620 ;; EMD31
.word 0x00000B83, 0x0002F264 ;; EMD31
.word 0x00000000, 0x00000000 ;; EMD3200
.word 0x00000000, 0x00000000 ;; EMD3201
.word 0x00000000, 0x00000000 ;; EMD32
.word 0x00000000, 0x00000000 ;; EMD32
.word 0x00000BE2, 0x000067B8 ;; EMD3300
.word 0x00000BEF, 0x000067B8 ;; EMD3301
.word 0x00000BFC, 0x00018620 ;; EMD33
.word 0x00000C2D, 0x000320A8 ;; EMD33
.word 0x00000C92, 0x0000B2D4 ;; EMD3400
.word 0x00000CA9, 0x0000B2D4 ;; EMD3401
.word 0x00000CC0, 0x00018620 ;; EMD34
.word 0x00000CF1, 0x00042D94 ;; EMD34
.word 0x00000000, 0x00000000 ;; EMD3500
.word 0x00000000, 0x00000000 ;; EMD3501
.word 0x00000000, 0x00000000 ;; EMD35
.word 0x00000000, 0x00000000 ;; EMD35
.word 0x00000D77, 0x00005BB4 ;; EMD3600
.word 0x00000D83, 0x00005BB4 ;; EMD3601
.word 0x00000D8F, 0x00020620 ;; EMD36
.word 0x00000DD0, 0x0001B6D4 ;; EMD36
.word 0x00000E07, 0x000059F0 ;; EMD3700
.word 0x00000E13, 0x000059F0 ;; EMD3701
.word 0x00000E1F, 0x00008220 ;; EMD37
.word 0x00000E30, 0x0000E7F0 ;; EMD37
.word 0x00000000, 0x00000000 ;; EMD3800
.word 0x00000000, 0x00000000 ;; EMD3801
.word 0x00000000, 0x00000000 ;; EMD38
.word 0x00000000, 0x00000000 ;; EMD38
.word 0x00000E4D, 0x00005A7A ;; EMD3900
.word 0x00000E59, 0x00005A7A ;; EMD3901
.word 0x00000E65, 0x00010420 ;; EMD39
.word 0x00000E86, 0x00034ECC ;; EMD39
.word 0x00000EF0, 0x00004E80 ;; EMD3A00
.word 0x00000EFA, 0x00004E80 ;; EMD3A01
.word 0x00000F04, 0x00010420 ;; EMD3A
.word 0x00000F25, 0x0000AC00 ;; EMD3A
.word 0x00000F3B, 0x000014D6 ;; EMD3B00
.word 0x00000F3E, 0x000014D6 ;; EMD3B01
.word 0x00000F41, 0x00008220 ;; EMD3B
.word 0x00000F52, 0x00000D98 ;; EMD3B
.word 0x00000000, 0x00000000 ;; EMD3C00
.word 0x00000000, 0x00000000 ;; EMD3C01
.word 0x00000000, 0x00000000 ;; EMD3C
.word 0x00000000, 0x00000000 ;; EMD3C
.word 0x00000000, 0x00000000 ;; EMD3D00
.word 0x00000000, 0x00000000 ;; EMD3D01
.word 0x00000000, 0x00000000 ;; EMD3D
.word 0x00000000, 0x00000000 ;; EMD3D
.word 0x00000F54, 0x00000270 ;; EMD3E00
.word 0x00000F55, 0x00000270 ;; EMD3E01
.word 0x00000F56, 0x00008220 ;; EMD3E
.word 0x00000F67, 0x0000D810 ;; EMD3E
.word 0x00000F83, 0x0000037C ;; EMD3F00
.word 0x00000F84, 0x0000037C ;; EMD3F01
.word 0x00000F85, 0x00008220 ;; EMD3F
.word 0x00000F96, 0x00006574 ;; EMD3F
.word 0x00000000, 0x00000000 ;; EMD4000
.word 0x00000000, 0x00000000 ;; EMD4001
.word 0x00000FA3, 0x00018620 ;; EMD40
.word 0x00000FD4, 0x0000D648 ;; EMD40
.word 0x00000000, 0x00000000 ;; EMD4100
.word 0x00000000, 0x00000000 ;; EMD4101
.word 0x00000FEF, 0x00010420 ;; EMD41
.word 0x00001010, 0x00013718 ;; EMD41
.word 0x00000000, 0x00000000 ;; EMD4200
.word 0x00000000, 0x00000000 ;; EMD4201
.word 0x00001037, 0x00018620 ;; EMD42
.word 0x00001068, 0x0000C600 ;; EMD42
.word 0x00000000, 0x00000000 ;; EMD4300
.word 0x00000000, 0x00000000 ;; EMD4301
.word 0x00001081, 0x00018620 ;; EMD43
.word 0x000010B2, 0x00013718 ;; EMD43
.word 0x00000000, 0x00000000 ;; EMD4400
.word 0x00000000, 0x00000000 ;; EMD4401
.word 0x000010D9, 0x00018620 ;; EMD44
.word 0x0000110A, 0x00012638 ;; EMD44
.word 0x00000000, 0x00000000 ;; EMD4500
.word 0x00000000, 0x00000000 ;; EMD4501
.word 0x0000112F, 0x00010420 ;; EMD45
.word 0x00001150, 0x000120FC ;; EMD45
.word 0x00000000, 0x00000000 ;; EMD4600
.word 0x00000000, 0x00000000 ;; EMD4601
.word 0x00000000, 0x00000000 ;; EMD46
.word 0x00000000, 0x00000000 ;; EMD46
.word 0x00000000, 0x00000000 ;; EMD4700
.word 0x00000000, 0x00000000 ;; EMD4701
.word 0x00001175, 0x00018620 ;; EMD47
.word 0x000011A6, 0x0000C834 ;; EMD47
.word 0x00000000, 0x00000000 ;; EMD4800
.word 0x00000000, 0x00000000 ;; EMD4801
.word 0x000011C0, 0x00018620 ;; EMD48
.word 0x000011F1, 0x00007A0C ;; EMD48
.word 0x00000000, 0x00000000 ;; EMD4900
.word 0x00000000, 0x00000000 ;; EMD4901
.word 0x00001201, 0x00018620 ;; EMD49
.word 0x00001232, 0x0000C834 ;; EMD49
.word 0x00000000, 0x00000000 ;; EMD4A00
.word 0x00000000, 0x00000000 ;; EMD4A01
.word 0x0000124C, 0x00018620 ;; EMD4A
.word 0x0000127D, 0x000274CC ;; EMD4A
.word 0x00000000, 0x00000000 ;; EMD4B00
.word 0x00000000, 0x00000000 ;; EMD4B01
.word 0x000012CC, 0x00010420 ;; EMD4B
.word 0x000012ED, 0x0000478C ;; EMD4B
.word 0x00000000, 0x00000000 ;; EMD4C00
.word 0x00000000, 0x00000000 ;; EMD4C01
.word 0x00000000, 0x00000000 ;; EMD4C
.word 0x00000000, 0x00000000 ;; EMD4C
.word 0x00000000, 0x00000000 ;; EMD4D00
.word 0x00000000, 0x00000000 ;; EMD4D01
.word 0x00000000, 0x00000000 ;; EMD4D
.word 0x00000000, 0x00000000 ;; EMD4D
.word 0x00000000, 0x00000000 ;; EMD4E00
.word 0x00000000, 0x00000000 ;; EMD4E01
.word 0x00000000, 0x00000000 ;; EMD4E
.word 0x00000000, 0x00000000 ;; EMD4E
.word 0x00000000, 0x00000000 ;; EMD4F00
.word 0x00000000, 0x00000000 ;; EMD4F01
.word 0x000012F6, 0x00010420 ;; EMD4F
.word 0x00001317, 0x0001230C ;; EMD4F
.word 0x00000000, 0x00000000 ;; EMD5000
.word 0x00000000, 0x00000000 ;; EMD5001
.word 0x0000133C, 0x00018620 ;; EMD50
.word 0x0000136D, 0x000124D8 ;; EMD50
.word 0x00000000, 0x00000000 ;; EMD5100
.word 0x00000000, 0x00000000 ;; EMD5101
.word 0x00001392, 0x00010420 ;; EMD51
.word 0x000013B3, 0x00012AE4 ;; EMD51
.word 0x00000000, 0x00000000 ;; EMD5200
.word 0x00000000, 0x00000000 ;; EMD5201
.word 0x00000000, 0x00000000 ;; EMD52
.word 0x00000000, 0x00000000 ;; EMD52
.word 0x00000000, 0x00000000 ;; EMD5300
.word 0x00000000, 0x00000000 ;; EMD5301
.word 0x00000000, 0x00000000 ;; EMD53
.word 0x00000000, 0x00000000 ;; EMD53
.word 0x00000000, 0x00000000 ;; EMD5400
.word 0x00000000, 0x00000000 ;; EMD5401
.word 0x000013D9, 0x00010420 ;; EMD54
.word 0x000013FA, 0x000124D8 ;; EMD54
.word 0x00000000, 0x00000000 ;; EMD5500
.word 0x00000000, 0x00000000 ;; EMD5501
.word 0x0000141F, 0x00010420 ;; EMD55
.word 0x00001440, 0x00012A34 ;; EMD55
.word 0x00000000, 0x00000000 ;; EMD5600
.word 0x00000000, 0x00000000 ;; EMD5601
.word 0x00000000, 0x00000000 ;; EMD56
.word 0x00000000, 0x00000000 ;; EMD56
.word 0x00000000, 0x00000000 ;; EMD5700
.word 0x00000000, 0x00000000 ;; EMD5701
.word 0x00000000, 0x00000000 ;; EMD57
.word 0x00000000, 0x00000000 ;; EMD57
.word 0x00000000, 0x00000000 ;; EMD5800
.word 0x00000000, 0x00000000 ;; EMD5801
.word 0x00001466, 0x00010420 ;; EMD58
.word 0x00001487, 0x000124F0 ;; EMD58
.word 0x00000000, 0x00000000 ;; EMD5900
.word 0x00000000, 0x00000000 ;; EMD5901
.word 0x000014AC, 0x00018620 ;; EMD59
.word 0x000014DD, 0x00012C2C ;; EMD59
.word 0x00000000, 0x00000000 ;; EMD5A00
.word 0x00000000, 0x00000000 ;; EMD5A01
.word 0x00001503, 0x00018620 ;; EMD5A
.word 0x00001534, 0x000130F0 ;; EMD5A
.word 0x00000000, 0x00000000 ;; EMD5B00
.word 0x00000000, 0x00000000 ;; EMD5B01
.word 0x00000000, 0x00000000 ;; EMD5B
.word 0x00000000, 0x00000000 ;; EMD5B
.word 0x00000000, 0x00000000 ;; EMD5C00
.word 0x00000000, 0x00000000 ;; EMD5C01
.word 0x00000000, 0x00000000 ;; EMD5C
.word 0x00000000, 0x00000000 ;; EMD5C
.word 0x00000000, 0x00000000 ;; EMD5D00
.word 0x00000000, 0x00000000 ;; EMD5D01
.word 0x00000000, 0x00000000 ;; EMD5D
.word 0x00000000, 0x00000000 ;; EMD5D
.word 0x00000000, 0x00000000 ;; EMD5E00
.word 0x00000000, 0x00000000 ;; EMD5E01
.word 0x00000000, 0x00000000 ;; EMD5E
.word 0x00000000, 0x00000000 ;; EMD5E
.word 0x00000000, 0x00000000 ;; EMD5F00
.word 0x00000000, 0x00000000 ;; EMD5F01
.word 0x00000000, 0x00000000 ;; EMD5F
.word 0x00000000, 0x00000000 ;; EMD5F
|
MeganGrass/Resident-Evil-2-Starter-Kit | 13,777 | source/assembly/enemy/cdemd0.s |
.org 0x8009ADF4
.word 0x00000000, 0x0000CF4C ;; EM1000.BIN
.word 0x0000001A, 0x0000CF4C ;; EM1001.BIN
.word 0x00000034, 0x00010420 ;; EM10.TIM
.word 0x00000055, 0x00023DCC ;; EM10.EMD
.word 0x00000000, 0x00000000 ;; EM1100.BIN
.word 0x00000000, 0x00000000 ;; EM1101.BIN
.word 0x0000009D, 0x00010420 ;; EM11.TIM
.word 0x000000BE, 0x000247DC ;; EM11.EMD
.word 0x00000000, 0x00000000 ;; EM1200.BIN
.word 0x00000000, 0x00000000 ;; EM1201.BIN
.word 0x00000107, 0x00020820 ;; EM12.TIM
.word 0x00000149, 0x00023B5C ;; EM12.EMD
.word 0x00000000, 0x00000000 ;; EM1300.BIN
.word 0x00000000, 0x00000000 ;; EM1301.BIN
.word 0x00000191, 0x00010420 ;; EM13.TIM
.word 0x000001B2, 0x00023D2C ;; EM13.EMD
.word 0x00000000, 0x00000000 ;; EM1400.BIN
.word 0x00000000, 0x00000000 ;; EM1401.BIN
.word 0x00000000, 0x00000000 ;; EM14.TIM
.word 0x00000000, 0x00000000 ;; EM14.EMD
.word 0x00000000, 0x00000000 ;; EM1500.BIN
.word 0x00000000, 0x00000000 ;; EM1501.BIN
.word 0x000001FA, 0x00010420 ;; EM15.TIM
.word 0x0000021B, 0x00023CAC ;; EM15.EMD
.word 0x00000000, 0x00000000 ;; EM1600.BIN
.word 0x00000000, 0x00000000 ;; EM1601.BIN
.word 0x00000263, 0x00010420 ;; EM16.TIM
.word 0x00000284, 0x00023A5C ;; EM16.EMD
.word 0x00000000, 0x00000000 ;; EM1700.BIN
.word 0x00000000, 0x00000000 ;; EM1701.BIN
.word 0x000002CC, 0x00010420 ;; EM17.TIM
.word 0x000002ED, 0x00024E98 ;; EM17.EMD
.word 0x00000000, 0x00000000 ;; EM1800.BIN
.word 0x00000000, 0x00000000 ;; EM1801.BIN
.word 0x00000337, 0x00010420 ;; EM18.TIM
.word 0x00000358, 0x00022604 ;; EM18.EMD
.word 0x00000000, 0x00000000 ;; EM1900.BIN
.word 0x00000000, 0x00000000 ;; EM1901.BIN
.word 0x00000000, 0x00000000 ;; EM19.TIM
.word 0x00000000, 0x00000000 ;; EM19.EMD
.word 0x00000000, 0x00000000 ;; EM1A00.BIN
.word 0x00000000, 0x00000000 ;; EM1A01.BIN
.word 0x00000000, 0x00000000 ;; EM1A.TIM
.word 0x00000000, 0x00000000 ;; EM1A.EMD
.word 0x00000000, 0x00000000 ;; EM1B00.BIN
.word 0x00000000, 0x00000000 ;; EM1B01.BIN
.word 0x00000000, 0x00000000 ;; EM1B.TIM
.word 0x00000000, 0x00000000 ;; EM1B.EMD
.word 0x00000000, 0x00000000 ;; EM1C00.BIN
.word 0x00000000, 0x00000000 ;; EM1C01.BIN
.word 0x00000000, 0x00000000 ;; EM1C.TIM
.word 0x00000000, 0x00000000 ;; EM1C.EMD
.word 0x00000000, 0x00000000 ;; EM1D00.BIN
.word 0x00000000, 0x00000000 ;; EM1D01.BIN
.word 0x00000000, 0x00000000 ;; EM1D.TIM
.word 0x00000000, 0x00000000 ;; EM1D.EMD
.word 0x00000000, 0x00000000 ;; EM1E00.BIN
.word 0x00000000, 0x00000000 ;; EM1E01.BIN
.word 0x0000039D, 0x00020820 ;; EM1E.TIM
.word 0x000003DF, 0x00022604 ;; EM1E.EMD
.word 0x00000000, 0x00000000 ;; EM1F00.BIN
.word 0x00000000, 0x00000000 ;; EM1F01.BIN
.word 0x00000424, 0x00020820 ;; EM1F.TIM
.word 0x00000466, 0x00022604 ;; EM1F.EMD
.word 0x000004AB, 0x000056FA ;; EM2000.BIN
.word 0x000004B6, 0x000056FA ;; EM2001.BIN
.word 0x000004C1, 0x00010420 ;; EM20.TIM
.word 0x000004E2, 0x0001D938 ;; EM20.EMD
.word 0x0000051E, 0x00004A88 ;; EM2100.BIN
.word 0x00000528, 0x00004A88 ;; EM2101.BIN
.word 0x00000532, 0x00008220 ;; EM21.TIM
.word 0x00000543, 0x00007E28 ;; EM21.EMD
.word 0x00000553, 0x00007698 ;; EM2200.BIN
.word 0x00000562, 0x00007698 ;; EM2201.BIN
.word 0x00000571, 0x00010420 ;; EM22.TIM
.word 0x00000592, 0x0002AB74 ;; EM22.EMD
.word 0x000005E8, 0x000048E8 ;; EM2300.BIN
.word 0x000005F2, 0x000048E8 ;; EM2301.BIN
.word 0x000005FC, 0x00020820 ;; EM23.TIM
.word 0x0000063E, 0x0002E318 ;; EM23.EMD
.word 0x0000069B, 0x00005DA0 ;; EM2400.BIN
.word 0x000006A7, 0x00005DA0 ;; EM2401.BIN
.word 0x000006B3, 0x00010420 ;; EM24.TIM
.word 0x000006D4, 0x0001FAB0 ;; EM24.EMD
.word 0x00000714, 0x000066D4 ;; EM2500.BIN
.word 0x00000721, 0x000066D4 ;; EM2501.BIN
.word 0x0000072E, 0x00010420 ;; EM25.TIM
.word 0x0000074F, 0x0000D0C8 ;; EM25.EMD
.word 0x0000076A, 0x000010FA ;; EM2600.BIN
.word 0x0000076D, 0x000010FA ;; EM2601.BIN
.word 0x00000770, 0x00008220 ;; EM26.TIM
.word 0x00000781, 0x00001A14 ;; EM26.EMD
.word 0x00000785, 0x0000389C ;; EM2700.BIN
.word 0x0000078D, 0x0000389C ;; EM2701.BIN
.word 0x00000795, 0x00008220 ;; EM27.TIM
.word 0x000007A6, 0x00009AD0 ;; EM27.EMD
.word 0x000007BA, 0x000067B0 ;; EM2800.BIN
.word 0x000007C7, 0x000067B0 ;; EM2801.BIN
.word 0x000007D4, 0x00020820 ;; EM28.TIM
.word 0x00000816, 0x0002DF0C ;; EM28.EMD
.word 0x00000872, 0x00001EFC ;; EM2900.BIN
.word 0x00000876, 0x00001EFC ;; EM2901.BIN
.word 0x0000087A, 0x00008220 ;; EM29.TIM
.word 0x0000088B, 0x00003110 ;; EM29.EMD
.word 0x00000892, 0x00004F10 ;; EM2A00.BIN
.word 0x0000089C, 0x00004F10 ;; EM2A01.BIN
.word 0x000008A6, 0x00010420 ;; EM2A.TIM
.word 0x000008C7, 0x00021C84 ;; EM2A.EMD
.word 0x0000090B, 0x00004D68 ;; EM2B00.BIN
.word 0x00000915, 0x00004D68 ;; EM2B01.BIN
.word 0x0000091F, 0x00018620 ;; EM2B.TIM
.word 0x00000950, 0x00022278 ;; EM2B.EMD
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.word 0x00000997, 0x00008220 ;; EM2C.TIM
.word 0x000009A8, 0x00003E5C ;; EM2C.EMD
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.word 0x000009B6, 0x00008220 ;; EM2D.TIM
.word 0x000009C7, 0x00006020 ;; EM2D.EMD
.word 0x000009D4, 0x00005A7A ;; EM2E00.BIN
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.word 0x000009EC, 0x00010420 ;; EM2E.TIM
.word 0x00000A0D, 0x00034ECC ;; EM2E.EMD
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.word 0x00000A81, 0x00008220 ;; EM2F.TIM
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.word 0x00000AA4, 0x000076AC ;; EM3001.BIN
.word 0x00000AB3, 0x00018620 ;; EM30.TIM
.word 0x00000AE4, 0x0002527C ;; EM30.EMD
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.word 0x00000B4F, 0x00018620 ;; EM31.TIM
.word 0x00000B80, 0x0002F264 ;; EM31.EMD
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.word 0x00000000, 0x00000000 ;; EM32.TIM
.word 0x00000000, 0x00000000 ;; EM32.EMD
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.word 0x00000BF9, 0x00018620 ;; EM33.TIM
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.word 0x00000F16, 0x00010420 ;; EM3A.TIM
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.word 0x00000F53, 0x00008220 ;; EM3B.TIM
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.word 0x00000000, 0x00000000 ;; EM3C.TIM
.word 0x00000000, 0x00000000 ;; EM3C.EMD
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.word 0x00000000, 0x00000000 ;; EM3D.TIM
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.word 0x00000F68, 0x00008220 ;; EM3E.TIM
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.word 0x000010C4, 0x00012DD0 ;; EM43.EMD
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.word 0x000010EA, 0x00018620 ;; EM44.TIM
.word 0x0000111B, 0x00012638 ;; EM44.EMD
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.word 0x00001140, 0x00010420 ;; EM45.TIM
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.word 0x00001186, 0x00018620 ;; EM46.TIM
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.word 0x00000000, 0x00000000 ;; EM4D.TIM
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.word 0x00000000, 0x00000000 ;; EM5C.TIM
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.word 0x00000000, 0x00000000 ;; EM5D.TIM
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.word 0x00000000, 0x00000000 ;; EM5F.EMD
|
MeganGrass/Resident-Evil-2-Starter-Kit | 13,777 | source/assembly/enemy/cdemd1.s |
.org cdemd1_pos
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.word 0x00001025, 0x000136F8 ;; EM41.EMD
.word 0x00000000, 0x00000000 ;; EM4200.BIN
.word 0x00000000, 0x00000000 ;; EM4201.BIN
.word 0x0000104C, 0x00018620 ;; EM42.TIM
.word 0x0000107D, 0x0000C600 ;; EM42.EMD
.word 0x00000000, 0x00000000 ;; EM4300.BIN
.word 0x00000000, 0x00000000 ;; EM4301.BIN
.word 0x00001096, 0x00018620 ;; EM43.TIM
.word 0x000010C7, 0x000136F8 ;; EM43.EMD
.word 0x00000000, 0x00000000 ;; EM4400.BIN
.word 0x00000000, 0x00000000 ;; EM4401.BIN
.word 0x000010EE, 0x00018620 ;; EM44.TIM
.word 0x0000111F, 0x00012638 ;; EM44.EMD
.word 0x00000000, 0x00000000 ;; EM4500.BIN
.word 0x00000000, 0x00000000 ;; EM4501.BIN
.word 0x00001144, 0x00010420 ;; EM45.TIM
.word 0x00001165, 0x000120FC ;; EM45.EMD
.word 0x00000000, 0x00000000 ;; EM4600.BIN
.word 0x00000000, 0x00000000 ;; EM4601.BIN
.word 0x0000118A, 0x00018620 ;; EM46.TIM
.word 0x000011BB, 0x00012638 ;; EM46.EMD
.word 0x00000000, 0x00000000 ;; EM4700.BIN
.word 0x00000000, 0x00000000 ;; EM4701.BIN
.word 0x000011E0, 0x00018620 ;; EM47.TIM
.word 0x00001211, 0x0000C834 ;; EM47.EMD
.word 0x00000000, 0x00000000 ;; EM4800.BIN
.word 0x00000000, 0x00000000 ;; EM4801.BIN
.word 0x0000122B, 0x00018620 ;; EM48.TIM
.word 0x0000125C, 0x00007A0C ;; EM48.EMD
.word 0x00000000, 0x00000000 ;; EM4900.BIN
.word 0x00000000, 0x00000000 ;; EM4901.BIN
.word 0x0000126C, 0x00018620 ;; EM49.TIM
.word 0x0000129D, 0x0000C834 ;; EM49.EMD
.word 0x00000000, 0x00000000 ;; EM4A00.BIN
.word 0x00000000, 0x00000000 ;; EM4A01.BIN
.word 0x000012B7, 0x00018620 ;; EM4A.TIM
.word 0x000012E8, 0x000274CC ;; EM4A.EMD
.word 0x00000000, 0x00000000 ;; EM4B00.BIN
.word 0x00000000, 0x00000000 ;; EM4B01.BIN
.word 0x00001337, 0x00010420 ;; EM4B.TIM
.word 0x00001358, 0x0000478C ;; EM4B.EMD
.word 0x00000000, 0x00000000 ;; EM4C00.BIN
.word 0x00000000, 0x00000000 ;; EM4C01.BIN
.word 0x00001361, 0x00010420 ;; EM4C.TIM
.word 0x00000000, 0x00000000 ;; EM4C.EMD
.word 0x00000000, 0x00000000 ;; EM4D00.BIN
.word 0x00000000, 0x00000000 ;; EM4D01.BIN
.word 0x00000000, 0x00000000 ;; EM4D.TIM
.word 0x00000000, 0x00000000 ;; EM4D.EMD
.word 0x00000000, 0x00000000 ;; EM4E00.BIN
.word 0x00000000, 0x00000000 ;; EM4E01.BIN
.word 0x00000000, 0x00000000 ;; EM4E.TIM
.word 0x00000000, 0x00000000 ;; EM4E.EMD
.word 0x00000000, 0x00000000 ;; EM4F00.BIN
.word 0x00000000, 0x00000000 ;; EM4F01.BIN
.word 0x00001382, 0x00010420 ;; EM4F.TIM
.word 0x000013A3, 0x0001230C ;; EM4F.EMD
.word 0x00000000, 0x00000000 ;; EM5000.BIN
.word 0x00000000, 0x00000000 ;; EM5001.BIN
.word 0x000013C8, 0x00018620 ;; EM50.TIM
.word 0x000013F9, 0x000124D8 ;; EM50.EMD
.word 0x00000000, 0x00000000 ;; EM5100.BIN
.word 0x00000000, 0x00000000 ;; EM5101.BIN
.word 0x0000141E, 0x00010420 ;; EM51.TIM
.word 0x0000143F, 0x00012AE4 ;; EM51.EMD
.word 0x00000000, 0x00000000 ;; EM5200.BIN
.word 0x00000000, 0x00000000 ;; EM5201.BIN
.word 0x00000000, 0x00000000 ;; EM52.TIM
.word 0x00000000, 0x00000000 ;; EM52.EMD
.word 0x00000000, 0x00000000 ;; EM5300.BIN
.word 0x00000000, 0x00000000 ;; EM5301.BIN
.word 0x00000000, 0x00000000 ;; EM53.TIM
.word 0x00000000, 0x00000000 ;; EM53.EMD
.word 0x00000000, 0x00000000 ;; EM5400.BIN
.word 0x00000000, 0x00000000 ;; EM5401.BIN
.word 0x00001465, 0x00010420 ;; EM54.TIM
.word 0x00001486, 0x000124D8 ;; EM54.EMD
.word 0x00000000, 0x00000000 ;; EM5500.BIN
.word 0x00000000, 0x00000000 ;; EM5501.BIN
.word 0x000014AB, 0x00010420 ;; EM55.TIM
.word 0x000014CC, 0x00012A34 ;; EM55.EMD
.word 0x00000000, 0x00000000 ;; EM5600.BIN
.word 0x00000000, 0x00000000 ;; EM5601.BIN
.word 0x00000000, 0x00000000 ;; EM56.TIM
.word 0x00000000, 0x00000000 ;; EM56.EMD
.word 0x00000000, 0x00000000 ;; EM5700.BIN
.word 0x00000000, 0x00000000 ;; EM5701.BIN
.word 0x00000000, 0x00000000 ;; EM57.TIM
.word 0x00000000, 0x00000000 ;; EM57.EMD
.word 0x00000000, 0x00000000 ;; EM5800.BIN
.word 0x00000000, 0x00000000 ;; EM5801.BIN
.word 0x000014F2, 0x00010420 ;; EM58.TIM
.word 0x00001513, 0x000124F0 ;; EM58.EMD
.word 0x00000000, 0x00000000 ;; EM5900.BIN
.word 0x00000000, 0x00000000 ;; EM5901.BIN
.word 0x00001538, 0x00018620 ;; EM59.TIM
.word 0x00001569, 0x00012C2C ;; EM59.EMD
.word 0x00000000, 0x00000000 ;; EM5A00.BIN
.word 0x00000000, 0x00000000 ;; EM5A01.BIN
.word 0x0000158F, 0x00018620 ;; EM5A.TIM
.word 0x000015C0, 0x000130F0 ;; EM5A.EMD
.word 0x00000000, 0x00000000 ;; EM5B00.BIN
.word 0x00000000, 0x00000000 ;; EM5B01.BIN
.word 0x00000000, 0x00000000 ;; EM5B.TIM
.word 0x00000000, 0x00000000 ;; EM5B.EMD
.word 0x00000000, 0x00000000 ;; EM5C00.BIN
.word 0x00000000, 0x00000000 ;; EM5C01.BIN
.word 0x00000000, 0x00000000 ;; EM5C.TIM
.word 0x00000000, 0x00000000 ;; EM5C.EMD
.word 0x00000000, 0x00000000 ;; EM5D00.BIN
.word 0x00000000, 0x00000000 ;; EM5D01.BIN
.word 0x00000000, 0x00000000 ;; EM5D.TIM
.word 0x00000000, 0x00000000 ;; EM5D.EMD
.word 0x00000000, 0x00000000 ;; EM5E00.BIN
.word 0x00000000, 0x00000000 ;; EM5E01.BIN
.word 0x00000000, 0x00000000 ;; EM5E.TIM
.word 0x00000000, 0x00000000 ;; EM5E.EMD
.word 0x00000000, 0x00000000 ;; EM5F00.BIN
.word 0x00000000, 0x00000000 ;; EM5F01.BIN
.word 0x00000000, 0x00000000 ;; EM5F.TIM
.word 0x00000000, 0x00000000 ;; EM5F.EMD
|
MeganGrass/Resident-Evil-2-Starter-Kit | 3,496 | source/assembly/compression/lz_dec.s |
/*
* desld has been replaced with lz compression
*/
.org Dec_lz
lui $t6, 0x1F80
move $t3, $0
li $v1, 0x20
loc_20C:
addu $v0, $t6, $t3
sb $v1, 0($v0)
addiu $t3, 1
sltiu $v0, $t3, 0x1EF
bnez $v0, loc_20C
move $a3, $0
li $t3, 0x1EF
lw $t7, 0($a0)
addiu $a0, 4
beqz $t7, locret_374
move $t1, $0
loc_238:
bnez $a3, loc_250
and $v1, $t2, $a3
lbu $t2, 0($a0)
addiu $a0, 1
li $a3, 0x80
and $v1, $t2, $a3
loc_250:
beqz $v1, loc_2B4
srl $a3, 1
li $a2, 8
move $v1, $0
addu $t5, $t6, $t3
addiu $t3, 1
addu $t4, $a1, $t1
addiu $t0, $t1, 1
loc_270:
bnez $a3, loc_288
and $v0, $t2, $a3
lbu $t2, 0($a0)
addiu $a0, 1
li $a3, 0x80
and $v0, $t2, $a3
loc_288:
beqz $v0, loc_294
sll $v1, 1
ori $v1, 1
loc_294:
addiu $a2, 0xFFFF
bnez $a2, loc_270
srl $a3, 1
move $t1, $t0
andi $t3, 0x1FF
sb $v1, 0($t4)
j loc_368
sb $v1, 0($t5)
loc_2B4:
li $v1, 9
move $t4, $0
loc_2BC:
bnez $a3, loc_2D4
and $v0, $t2, $a3
lbu $t2, 0($a0)
addiu $a0, 1
li $a3, 0x80
and $v0, $t2, $a3
loc_2D4:
beqz $v0, loc_2E0
sll $t4, 1
ori $t4, 1
loc_2E0:
addiu $v1, 0xFFFF
bnez $v1, loc_2BC
srl $a3, 1
li $a2, 4
move $v1, $0
loc_2F4:
bnez $a3, loc_30C
and $v0, $t2, $a3
lbu $t2, 0($a0)
addiu $a0, 1
li $a3, 0x80
and $v0, $t2, $a3
loc_30C:
beqz $v0, loc_318
sll $v1, 1
ori $v1, 1
loc_318:
addiu $a2, 0xFFFF
bnez $a2, loc_2F4
srl $a3, 1
move $t0, $0
addiu $t5, $v1, 1
addu $a2, $t1, $a1
loc_330:
addiu $t1, 1
addu $v0, $t6, $t3
addiu $t3, 1
andi $t3, 0x1FF
addu $v1, $t4, $t0
andi $v1, 0x1FF
addu $v1, $t6, $v1
lbu $v1, 0($v1)
addiu $t0, 1
sb $v1, 0($a2)
sb $v1, 0($v0)
sltu $v1, $t5, $t0
beqz $v1, loc_330
addiu $a2, 1
loc_368:
sltu $v0, $t1, $t7
bnez $v0, loc_238
nop
locret_374:
jr $ra
nop |
MeganGrass/Resident-Evil-2-Starter-Kit | 1,156 | source/assembly/overlay/opening.s |
/*
* Game_loop hook for BOOT.BIN
*/
;;.org 0x801BFB00
;; jal Boot_patch
;; nop
/*
* Disable XA audio and STR video playback
*/
.org 0x801C070C ;; Xa_play
nop
.org 0x801C07C8 ;; Xa_play
nop
.org 0x801C08F0 ;; Xa_play
nop
.org 0x801C09FC ;; Xa_play
nop
.org 0x801C0AD0 ;; Xa_play
nop
.org 0x801C0DF8 ;; Xa_play
nop
.org 0x801C0E70 ;; Xa_play
nop
.org 0x801C0EB8 ;; Xa_play
nop
.org 0x801C0F2C ;; Xa_play
nop
.org 0x801C0FD0 ;; Xa_play
nop
.org 0x801C1048 ;; Xa_play
nop
.org 0x801C10F8 ;; Xa_play
nop
.org 0x801C13A4 ;; Xa_play
nop
.org 0x801C141C ;; Xa_play
nop
.org 0x801C1494 ;; Xa_play
nop
.org 0x801C150C ;; Xa_play
nop
.org 0x801C15A8 ;; Xa_play
nop
.org 0x801C15F8 ;; Xa_play
nop
.org 0x801C1670 ;; Xa_play
nop
.org 0x801C16E8 ;; Xa_play
nop
.org 0x801C1800 ;; Xa_play
nop
.org 0x801C0C84 ;; Init_movie_work
nop
.org 0x801C0CC8 ;; Init_movie_work
nop
.org 0x801C1230 ;; Init_movie_work
nop
.org 0x801C1274 ;; Init_movie_work
nop
.org 0x801C1938 ;; Init_movie_work
nop
.org 0x801C197C ;; Init_movie_work
nop
|
MeganGrass/Resident-Evil-2-Starter-Kit | 8,285 | source/assembly/sound/stage7.s |
.org 0x80000180
.fill 0x240, 0xFF
.org 0x800003C0
.fill 0x440, 0x00
;; BGM Table
.org 0x80000180 ;; PL0 [Scenario A]
.byte 0x11, 0xFF ;; R700
.byte 0x11, 0xFF ;; R701
.byte 0x11, 0xAF ;; R702
.byte 0x11, 0xFF ;; R703
.byte 0x11, 0xFF ;; R704
.byte 0xFF, 0xFF ;; R705
.byte 0xFF, 0xFF ;; R706
.byte 0xFF, 0xFF ;; R707
.byte 0xFF, 0xFF ;; R708
.byte 0xFF, 0xFF ;; R709
.byte 0xFF, 0xFF ;; R70A
.byte 0xFF, 0xFF ;; R70B
.byte 0xFF, 0xFF ;; R70C
.byte 0xFF, 0xFF ;; R70D
.byte 0xFF, 0xFF ;; R70E
.byte 0xFF, 0xFF ;; R70F
.byte 0xFF, 0xFF ;; R710
.byte 0xFF, 0xFF ;; R711
.byte 0xFF, 0xFF ;; R712
.byte 0xFF, 0xFF ;; R713
.byte 0xFF, 0xFF ;; R714
.byte 0xFF, 0xFF ;; R715
.byte 0xFF, 0xFF ;; R716
.byte 0xFF, 0xFF ;; R717
.byte 0xFF, 0xFF ;; R718
.byte 0xFF, 0xFF ;; R719
.byte 0xFF, 0xFF ;; R71A
.byte 0xFF, 0xFF ;; R71B
.byte 0xFF, 0xFF ;; R71C
.byte 0xFF, 0xFF ;; R71D
.byte 0xFF, 0xFF ;; R71E
.byte 0xFF, 0xFF ;; R71F
.byte 0xFF, 0xFF ;; R720
.byte 0xFF, 0xFF ;; R721
.byte 0xFF, 0xFF ;; R722
.byte 0xFF, 0xFF ;; R723
.byte 0xFF, 0xFF ;; R724
.byte 0xFF, 0xFF ;; R725
.byte 0xFF, 0xFF ;; R726
.byte 0xFF, 0xFF ;; R727
.byte 0xFF, 0xFF ;; R728
.byte 0xFF, 0xFF ;; R729
.byte 0xFF, 0xFF ;; R72A
.byte 0xFF, 0xFF ;; R72B
.byte 0xFF, 0xFF ;; R72C
.byte 0xFF, 0xFF ;; R72D
.byte 0xFF, 0xFF ;; R72E
.byte 0xFF, 0xFF ;; R72F
.org 0x800001E0 ;; PL0 [Scenario B]
.byte 0x11, 0xFF ;; R700
.byte 0x11, 0xFF ;; R701
.byte 0x11, 0xAF ;; R702
.byte 0x11, 0xFF ;; R703
.byte 0x11, 0xFF ;; R704
.byte 0xFF, 0xFF ;; R705
.byte 0xFF, 0xFF ;; R706
.byte 0xFF, 0xFF ;; R707
.byte 0xFF, 0xFF ;; R708
.byte 0xFF, 0xFF ;; R709
.byte 0xFF, 0xFF ;; R70A
.byte 0xFF, 0xFF ;; R70B
.byte 0xFF, 0xFF ;; R70C
.byte 0xFF, 0xFF ;; R70D
.byte 0xFF, 0xFF ;; R70E
.byte 0xFF, 0xFF ;; R70F
.byte 0xFF, 0xFF ;; R710
.byte 0xFF, 0xFF ;; R711
.byte 0xFF, 0xFF ;; R712
.byte 0xFF, 0xFF ;; R713
.byte 0xFF, 0xFF ;; R714
.byte 0xFF, 0xFF ;; R715
.byte 0xFF, 0xFF ;; R716
.byte 0xFF, 0xFF ;; R717
.byte 0xFF, 0xFF ;; R718
.byte 0xFF, 0xFF ;; R719
.byte 0xFF, 0xFF ;; R71A
.byte 0xFF, 0xFF ;; R71B
.byte 0xFF, 0xFF ;; R71C
.byte 0xFF, 0xFF ;; R71D
.byte 0xFF, 0xFF ;; R71E
.byte 0xFF, 0xFF ;; R71F
.byte 0xFF, 0xFF ;; R720
.byte 0xFF, 0xFF ;; R721
.byte 0xFF, 0xFF ;; R722
.byte 0xFF, 0xFF ;; R723
.byte 0xFF, 0xFF ;; R724
.byte 0xFF, 0xFF ;; R725
.byte 0xFF, 0xFF ;; R726
.byte 0xFF, 0xFF ;; R727
.byte 0xFF, 0xFF ;; R728
.byte 0xFF, 0xFF ;; R729
.byte 0xFF, 0xFF ;; R72A
.byte 0xFF, 0xFF ;; R72B
.byte 0xFF, 0xFF ;; R72C
.byte 0xFF, 0xFF ;; R72D
.byte 0xFF, 0xFF ;; R72E
.byte 0xFF, 0xFF ;; R72F
.org 0x80000240 ;; PL1 [Scenario A]
.byte 0x11, 0xFF ;; R700
.byte 0x11, 0xFF ;; R701
.byte 0x11, 0xAF ;; R702
.byte 0x11, 0xFF ;; R703
.byte 0x11, 0xFF ;; R704
.byte 0xFF, 0xFF ;; R705
.byte 0xFF, 0xFF ;; R706
.byte 0xFF, 0xFF ;; R707
.byte 0xFF, 0xFF ;; R708
.byte 0xFF, 0xFF ;; R709
.byte 0xFF, 0xFF ;; R70A
.byte 0xFF, 0xFF ;; R70B
.byte 0xFF, 0xFF ;; R70C
.byte 0xFF, 0xFF ;; R70D
.byte 0xFF, 0xFF ;; R70E
.byte 0xFF, 0xFF ;; R70F
.byte 0xFF, 0xFF ;; R710
.byte 0xFF, 0xFF ;; R711
.byte 0xFF, 0xFF ;; R712
.byte 0xFF, 0xFF ;; R713
.byte 0xFF, 0xFF ;; R714
.byte 0xFF, 0xFF ;; R715
.byte 0xFF, 0xFF ;; R716
.byte 0xFF, 0xFF ;; R717
.byte 0xFF, 0xFF ;; R718
.byte 0xFF, 0xFF ;; R719
.byte 0xFF, 0xFF ;; R71A
.byte 0xFF, 0xFF ;; R71B
.byte 0xFF, 0xFF ;; R71C
.byte 0xFF, 0xFF ;; R71D
.byte 0xFF, 0xFF ;; R71E
.byte 0xFF, 0xFF ;; R71F
.byte 0xFF, 0xFF ;; R720
.byte 0xFF, 0xFF ;; R721
.byte 0xFF, 0xFF ;; R722
.byte 0xFF, 0xFF ;; R723
.byte 0xFF, 0xFF ;; R724
.byte 0xFF, 0xFF ;; R725
.byte 0xFF, 0xFF ;; R726
.byte 0xFF, 0xFF ;; R727
.byte 0xFF, 0xFF ;; R728
.byte 0xFF, 0xFF ;; R729
.byte 0xFF, 0xFF ;; R72A
.byte 0xFF, 0xFF ;; R72B
.byte 0xFF, 0xFF ;; R72C
.byte 0xFF, 0xFF ;; R72D
.byte 0xFF, 0xFF ;; R72E
.byte 0xFF, 0xFF ;; R72F
.org 0x800002A0 ;; PL1 [Scenario B]
.byte 0x11, 0xFF ;; R700
.byte 0x11, 0xFF ;; R701
.byte 0x11, 0xAF ;; R702
.byte 0x11, 0xFF ;; R703
.byte 0x11, 0xFF ;; R704
.byte 0xFF, 0xFF ;; R705
.byte 0xFF, 0xFF ;; R706
.byte 0xFF, 0xFF ;; R707
.byte 0xFF, 0xFF ;; R708
.byte 0xFF, 0xFF ;; R709
.byte 0xFF, 0xFF ;; R70A
.byte 0xFF, 0xFF ;; R70B
.byte 0xFF, 0xFF ;; R70C
.byte 0xFF, 0xFF ;; R70D
.byte 0xFF, 0xFF ;; R70E
.byte 0xFF, 0xFF ;; R70F
.byte 0xFF, 0xFF ;; R710
.byte 0xFF, 0xFF ;; R711
.byte 0xFF, 0xFF ;; R712
.byte 0xFF, 0xFF ;; R713
.byte 0xFF, 0xFF ;; R714
.byte 0xFF, 0xFF ;; R715
.byte 0xFF, 0xFF ;; R716
.byte 0xFF, 0xFF ;; R717
.byte 0xFF, 0xFF ;; R718
.byte 0xFF, 0xFF ;; R719
.byte 0xFF, 0xFF ;; R71A
.byte 0xFF, 0xFF ;; R71B
.byte 0xFF, 0xFF ;; R71C
.byte 0xFF, 0xFF ;; R71D
.byte 0xFF, 0xFF ;; R71E
.byte 0xFF, 0xFF ;; R71F
.byte 0xFF, 0xFF ;; R720
.byte 0xFF, 0xFF ;; R721
.byte 0xFF, 0xFF ;; R722
.byte 0xFF, 0xFF ;; R723
.byte 0xFF, 0xFF ;; R724
.byte 0xFF, 0xFF ;; R725
.byte 0xFF, 0xFF ;; R726
.byte 0xFF, 0xFF ;; R727
.byte 0xFF, 0xFF ;; R728
.byte 0xFF, 0xFF ;; R729
.byte 0xFF, 0xFF ;; R72A
.byte 0xFF, 0xFF ;; R72B
.byte 0xFF, 0xFF ;; R72C
.byte 0xFF, 0xFF ;; R72D
.byte 0xFF, 0xFF ;; R72E
.byte 0xFF, 0xFF ;; R72F
.org 0x80000300 ;; 4th Survivor
.byte 0xFF, 0xFF ;; R700
.byte 0xFF, 0xFF ;; R701
.byte 0xFF, 0xFF ;; R702
.byte 0xFF, 0xFF ;; R703
.byte 0xFF, 0xFF ;; R704
.byte 0xFF, 0xFF ;; R705
.byte 0xFF, 0xFF ;; R706
.byte 0xFF, 0xFF ;; R707
.byte 0xFF, 0xFF ;; R708
.byte 0xFF, 0xFF ;; R709
.byte 0xFF, 0xFF ;; R70A
.byte 0xFF, 0xFF ;; R70B
.byte 0xFF, 0xFF ;; R70C
.byte 0xFF, 0xFF ;; R70D
.byte 0xFF, 0xFF ;; R70E
.byte 0xFF, 0xFF ;; R70F
.byte 0xFF, 0xFF ;; R710
.byte 0xFF, 0xFF ;; R711
.byte 0xFF, 0xFF ;; R712
.byte 0xFF, 0xFF ;; R713
.byte 0xFF, 0xFF ;; R714
.byte 0xFF, 0xFF ;; R715
.byte 0xFF, 0xFF ;; R716
.byte 0xFF, 0xFF ;; R717
.byte 0xFF, 0xFF ;; R718
.byte 0xFF, 0xFF ;; R719
.byte 0xFF, 0xFF ;; R71A
.byte 0xFF, 0xFF ;; R71B
.byte 0xFF, 0xFF ;; R71C
.byte 0xFF, 0xFF ;; R71D
.byte 0xFF, 0xFF ;; R71E
.byte 0xFF, 0xFF ;; R71F
.byte 0xFF, 0xFF ;; R720
.byte 0xFF, 0xFF ;; R721
.byte 0xFF, 0xFF ;; R722
.byte 0xFF, 0xFF ;; R723
.byte 0xFF, 0xFF ;; R724
.byte 0xFF, 0xFF ;; R725
.byte 0xFF, 0xFF ;; R726
.byte 0xFF, 0xFF ;; R727
.byte 0xFF, 0xFF ;; R728
.byte 0xFF, 0xFF ;; R729
.byte 0xFF, 0xFF ;; R72A
.byte 0xFF, 0xFF ;; R72B
.byte 0xFF, 0xFF ;; R72C
.byte 0xFF, 0xFF ;; R72D
.byte 0xFF, 0xFF ;; R72E
.byte 0xFF, 0xFF ;; R72F
.org 0x80000360 ;; Ex-Battle
.byte 0x34, 0xFF ;; R700
.byte 0xFF, 0xFF ;; R701
.byte 0xFF, 0xFF ;; R702
.byte 0xFF, 0xFF ;; R703
.byte 0xFF, 0xFF ;; R704
.byte 0xFF, 0xFF ;; R705
.byte 0xFF, 0xFF ;; R706
.byte 0xFF, 0xFF ;; R707
.byte 0xFF, 0xFF ;; R708
.byte 0xFF, 0xFF ;; R709
.byte 0xFF, 0xFF ;; R70A
.byte 0xFF, 0xFF ;; R70B
.byte 0xFF, 0xFF ;; R70C
.byte 0xFF, 0xFF ;; R70D
.byte 0xFF, 0xFF ;; R70E
.byte 0xFF, 0xFF ;; R70F
.byte 0xFF, 0xFF ;; R710
.byte 0xFF, 0xFF ;; R711
.byte 0xFF, 0xFF ;; R712
.byte 0xFF, 0xFF ;; R713
.byte 0xFF, 0xFF ;; R714
.byte 0xFF, 0xFF ;; R715
.byte 0xFF, 0xFF ;; R716
.byte 0xFF, 0xFF ;; R717
.byte 0xFF, 0xFF ;; R718
.byte 0xFF, 0xFF ;; R719
.byte 0xFF, 0xFF ;; R71A
.byte 0xFF, 0xFF ;; R71B
.byte 0xFF, 0xFF ;; R71C
.byte 0xFF, 0xFF ;; R71D
.byte 0xFF, 0xFF ;; R71E
.byte 0xFF, 0xFF ;; R71F
.byte 0xFF, 0xFF ;; R720
.byte 0xFF, 0xFF ;; R721
.byte 0xFF, 0xFF ;; R722
.byte 0xFF, 0xFF ;; R723
.byte 0xFF, 0xFF ;; R724
.byte 0xFF, 0xFF ;; R725
.byte 0xFF, 0xFF ;; R726
.byte 0xFF, 0xFF ;; R727
.byte 0xFF, 0xFF ;; R728
.byte 0xFF, 0xFF ;; R729
.byte 0xFF, 0xFF ;; R72A
.byte 0xFF, 0xFF ;; R72B
.byte 0xFF, 0xFF ;; R72C
.byte 0xFF, 0xFF ;; R72D
.byte 0xFF, 0xFF ;; R72E
.byte 0xFF, 0xFF ;; R72F
;; XA Table
.org 0x800003C0 ;; PL0
.dh 0x06, 0x5C, 0x18 ;;
.dh 0x04, 0x54, 0x1D ;;
.dh 0x01, 0x6B, 0x0C ;;
.dh 0x05, 0x00, 0x42 ;;
.dh 0x06, 0x41, 0x1B ;;
.dh 0x03, 0x00, 0x55 ;;
.dh 0x03, 0x55, 0x1E ;;
.dh 0x02, 0x63, 0x0C ;;
.dh 0x02, 0x00, 0x63 ;;
.dh 0x07, 0x15, 0x0B ;;
.dh 0x07, 0x00, 0x15 ;;
.dh 0x04, 0x00, 0x54 ;;
.dh 0x01, 0x00, 0x6B ;;
.dh 0x05, 0x42, 0x2B ;;
.dh 0x06, 0x00, 0x41 ;;
.dh 0x00, 0x00, 0x77 ;;
.org 0x800005E0 ;; PL1 |
MeganGrass/Resident-Evil-2-Starter-Kit | 8,415 | source/assembly/sound/stage5.s |
.org 0x80000180
.fill 0x240, 0xFF
.org 0x800003C0
.fill 0x440, 0x00
;; BGM Table
.org 0x80000180 ;; PL0 [Scenario A]
.byte 0x5C, 0xDE ;; R500
.byte 0x0E, 0xFF ;; R501
.byte 0x0E, 0xFF ;; R502
.byte 0x13, 0xFF ;; R503
.byte 0x13, 0x1F ;; R504
.byte 0x20, 0xC9 ;; R505
.byte 0x13, 0x1F ;; R506
.byte 0xFF, 0x21 ;; R507
.byte 0x0E, 0xFF ;; R508
.byte 0x20, 0xE4 ;; R509
.byte 0xFF, 0xFF ;; R50A
.byte 0xFF, 0xFF ;; R50B
.byte 0xFF, 0xFF ;; R50C
.byte 0xFF, 0xFF ;; R50D
.byte 0xFF, 0xFF ;; R50E
.byte 0xFF, 0xFF ;; R50F
.byte 0xFF, 0xFF ;; R510
.byte 0xFF, 0xFF ;; R511
.byte 0xFF, 0xFF ;; R512
.byte 0xFF, 0xFF ;; R513
.byte 0xFF, 0xFF ;; R514
.byte 0xFF, 0xFF ;; R515
.byte 0xFF, 0xFF ;; R516
.byte 0xFF, 0xFF ;; R517
.byte 0xFF, 0xFF ;; R518
.byte 0xFF, 0xFF ;; R519
.byte 0xFF, 0xFF ;; R51A
.byte 0xFF, 0xFF ;; R51B
.byte 0xFF, 0xFF ;; R51C
.byte 0xFF, 0xFF ;; R51D
.byte 0xFF, 0xFF ;; R51E
.byte 0xFF, 0xFF ;; R51F
.byte 0xFF, 0xFF ;; R520
.byte 0xFF, 0xFF ;; R521
.byte 0xFF, 0xFF ;; R522
.byte 0xFF, 0xFF ;; R523
.byte 0xFF, 0xFF ;; R524
.byte 0xFF, 0xFF ;; R525
.byte 0xFF, 0xFF ;; R526
.byte 0xFF, 0xFF ;; R527
.byte 0xFF, 0xFF ;; R528
.byte 0xFF, 0xFF ;; R529
.byte 0xFF, 0xFF ;; R52A
.byte 0xFF, 0xFF ;; R52B
.byte 0xFF, 0xFF ;; R52C
.byte 0xFF, 0xFF ;; R52D
.byte 0xFF, 0xFF ;; R52E
.byte 0xFF, 0xFF ;; R52F
.org 0x800001E0 ;; PL0 [Scenario B]
.byte 0x5C, 0xDE ;; R500
.byte 0x0E, 0xFF ;; R501
.byte 0x0E, 0xFF ;; R502
.byte 0x13, 0xFF ;; R503
.byte 0x13, 0x1F ;; R504
.byte 0x20, 0xC9 ;; R505
.byte 0x13, 0x1F ;; R506
.byte 0x5E, 0x21 ;; R507
.byte 0x0E, 0xFF ;; R508
.byte 0x20, 0xE4 ;; R509
.byte 0xFF, 0xFF ;; R50A
.byte 0xFF, 0xFF ;; R50B
.byte 0xFF, 0xFF ;; R50C
.byte 0xFF, 0xFF ;; R50D
.byte 0xFF, 0xFF ;; R50E
.byte 0xFF, 0xFF ;; R50F
.byte 0xFF, 0xFF ;; R510
.byte 0xFF, 0xFF ;; R511
.byte 0xFF, 0xFF ;; R512
.byte 0xFF, 0xFF ;; R513
.byte 0xFF, 0xFF ;; R514
.byte 0xFF, 0xFF ;; R515
.byte 0xFF, 0xFF ;; R516
.byte 0xFF, 0xFF ;; R517
.byte 0xFF, 0xFF ;; R518
.byte 0xFF, 0xFF ;; R519
.byte 0xFF, 0xFF ;; R51A
.byte 0xFF, 0xFF ;; R51B
.byte 0xFF, 0xFF ;; R51C
.byte 0xFF, 0xFF ;; R51D
.byte 0xFF, 0xFF ;; R51E
.byte 0xFF, 0xFF ;; R51F
.byte 0xFF, 0xFF ;; R520
.byte 0xFF, 0xFF ;; R521
.byte 0xFF, 0xFF ;; R522
.byte 0xFF, 0xFF ;; R523
.byte 0xFF, 0xFF ;; R524
.byte 0xFF, 0xFF ;; R525
.byte 0xFF, 0xFF ;; R526
.byte 0xFF, 0xFF ;; R527
.byte 0xFF, 0xFF ;; R528
.byte 0xFF, 0xFF ;; R529
.byte 0xFF, 0xFF ;; R52A
.byte 0xFF, 0xFF ;; R52B
.byte 0xFF, 0xFF ;; R52C
.byte 0xFF, 0xFF ;; R52D
.byte 0xFF, 0xFF ;; R52E
.byte 0xFF, 0xFF ;; R52F
.org 0x80000240 ;; PL1 [Scenario A]
.byte 0x1C, 0xFF ;; R500
.byte 0x0E, 0xFF ;; R501
.byte 0x0E, 0xFF ;; R502
.byte 0x13, 0xFF ;; R503
.byte 0x13, 0x1F ;; R504
.byte 0x20, 0xC9 ;; R505
.byte 0x13, 0x1F ;; R506
.byte 0xFF, 0x21 ;; R507
.byte 0x0E, 0xFF ;; R508
.byte 0x20, 0xE4 ;; R509
.byte 0xFF, 0xFF ;; R50A
.byte 0xFF, 0xFF ;; R50B
.byte 0xFF, 0xFF ;; R50C
.byte 0xFF, 0xFF ;; R50D
.byte 0xFF, 0xFF ;; R50E
.byte 0xFF, 0xFF ;; R50F
.byte 0xFF, 0xFF ;; R510
.byte 0xFF, 0xFF ;; R511
.byte 0xFF, 0xFF ;; R512
.byte 0xFF, 0xFF ;; R513
.byte 0xFF, 0xFF ;; R514
.byte 0xFF, 0xFF ;; R515
.byte 0xFF, 0xFF ;; R516
.byte 0xFF, 0xFF ;; R517
.byte 0xFF, 0xFF ;; R518
.byte 0xFF, 0xFF ;; R519
.byte 0xFF, 0xFF ;; R51A
.byte 0xFF, 0xFF ;; R51B
.byte 0xFF, 0xFF ;; R51C
.byte 0xFF, 0xFF ;; R51D
.byte 0xFF, 0xFF ;; R51E
.byte 0xFF, 0xFF ;; R51F
.byte 0xFF, 0xFF ;; R520
.byte 0xFF, 0xFF ;; R521
.byte 0xFF, 0xFF ;; R522
.byte 0xFF, 0xFF ;; R523
.byte 0xFF, 0xFF ;; R524
.byte 0xFF, 0xFF ;; R525
.byte 0xFF, 0xFF ;; R526
.byte 0xFF, 0xFF ;; R527
.byte 0xFF, 0xFF ;; R528
.byte 0xFF, 0xFF ;; R529
.byte 0xFF, 0xFF ;; R52A
.byte 0xFF, 0xFF ;; R52B
.byte 0xFF, 0xFF ;; R52C
.byte 0xFF, 0xFF ;; R52D
.byte 0xFF, 0xFF ;; R52E
.byte 0xFF, 0xFF ;; R52F
.org 0x800002A0 ;; PL1 [Scenario B]
.byte 0x1C, 0xFF ;; R500
.byte 0x0E, 0xFF ;; R501
.byte 0x0E, 0xFF ;; R502
.byte 0x13, 0xFF ;; R503
.byte 0x13, 0x1F ;; R504
.byte 0x20, 0xC9 ;; R505
.byte 0x13, 0x1F ;; R506
.byte 0x5E, 0x21 ;; R507
.byte 0x0E, 0xFF ;; R508
.byte 0x20, 0xE4 ;; R509
.byte 0xFF, 0xFF ;; R50A
.byte 0xFF, 0xFF ;; R50B
.byte 0xFF, 0xFF ;; R50C
.byte 0xFF, 0xFF ;; R50D
.byte 0xFF, 0xFF ;; R50E
.byte 0xFF, 0xFF ;; R50F
.byte 0xFF, 0xFF ;; R510
.byte 0xFF, 0xFF ;; R511
.byte 0xFF, 0xFF ;; R512
.byte 0xFF, 0xFF ;; R513
.byte 0xFF, 0xFF ;; R514
.byte 0xFF, 0xFF ;; R515
.byte 0xFF, 0xFF ;; R516
.byte 0xFF, 0xFF ;; R517
.byte 0xFF, 0xFF ;; R518
.byte 0xFF, 0xFF ;; R519
.byte 0xFF, 0xFF ;; R51A
.byte 0xFF, 0xFF ;; R51B
.byte 0xFF, 0xFF ;; R51C
.byte 0xFF, 0xFF ;; R51D
.byte 0xFF, 0xFF ;; R51E
.byte 0xFF, 0xFF ;; R51F
.byte 0xFF, 0xFF ;; R520
.byte 0xFF, 0xFF ;; R521
.byte 0xFF, 0xFF ;; R522
.byte 0xFF, 0xFF ;; R523
.byte 0xFF, 0xFF ;; R524
.byte 0xFF, 0xFF ;; R525
.byte 0xFF, 0xFF ;; R526
.byte 0xFF, 0xFF ;; R527
.byte 0xFF, 0xFF ;; R528
.byte 0xFF, 0xFF ;; R529
.byte 0xFF, 0xFF ;; R52A
.byte 0xFF, 0xFF ;; R52B
.byte 0xFF, 0xFF ;; R52C
.byte 0xFF, 0xFF ;; R52D
.byte 0xFF, 0xFF ;; R52E
.byte 0xFF, 0xFF ;; R52F
.org 0x80000300 ;; 4th Survivor
.byte 0xFF, 0xFF ;; R500
.byte 0xFF, 0xFF ;; R501
.byte 0xFF, 0xFF ;; R502
.byte 0xFF, 0xFF ;; R503
.byte 0xFF, 0xFF ;; R504
.byte 0xFF, 0xFF ;; R505
.byte 0xFF, 0xFF ;; R506
.byte 0xFF, 0xFF ;; R507
.byte 0xFF, 0xFF ;; R508
.byte 0xFF, 0xFF ;; R509
.byte 0xFF, 0xFF ;; R50A
.byte 0xFF, 0xFF ;; R50B
.byte 0xFF, 0xFF ;; R50C
.byte 0xFF, 0xFF ;; R50D
.byte 0xFF, 0xFF ;; R50E
.byte 0xFF, 0xFF ;; R50F
.byte 0xFF, 0xFF ;; R510
.byte 0xFF, 0xFF ;; R511
.byte 0xFF, 0xFF ;; R512
.byte 0xFF, 0xFF ;; R513
.byte 0xFF, 0xFF ;; R514
.byte 0xFF, 0xFF ;; R515
.byte 0xFF, 0xFF ;; R516
.byte 0xFF, 0xFF ;; R517
.byte 0xFF, 0xFF ;; R518
.byte 0xFF, 0xFF ;; R519
.byte 0xFF, 0xFF ;; R51A
.byte 0xFF, 0xFF ;; R51B
.byte 0xFF, 0xFF ;; R51C
.byte 0xFF, 0xFF ;; R51D
.byte 0xFF, 0xFF ;; R51E
.byte 0xFF, 0xFF ;; R51F
.byte 0xFF, 0xFF ;; R520
.byte 0xFF, 0xFF ;; R521
.byte 0xFF, 0xFF ;; R522
.byte 0xFF, 0xFF ;; R523
.byte 0xFF, 0xFF ;; R524
.byte 0xFF, 0xFF ;; R525
.byte 0xFF, 0xFF ;; R526
.byte 0xFF, 0xFF ;; R527
.byte 0xFF, 0xFF ;; R528
.byte 0xFF, 0xFF ;; R529
.byte 0xFF, 0xFF ;; R52A
.byte 0xFF, 0xFF ;; R52B
.byte 0xFF, 0xFF ;; R52C
.byte 0xFF, 0xFF ;; R52D
.byte 0xFF, 0xFF ;; R52E
.byte 0xFF, 0xFF ;; R52F
.org 0x80000360 ;; Ex-Battle
.byte 0x36, 0xFF ;; R500
.byte 0x36, 0xFF ;; R501
.byte 0x36, 0xFF ;; R502
.byte 0x0C, 0xFF ;; R503
.byte 0x36, 0xFF ;; R504
.byte 0x36, 0xFF ;; R505
.byte 0xFF, 0xFF ;; R506
.byte 0xFF, 0xFF ;; R507
.byte 0x36, 0xFF ;; R508
.byte 0xFF, 0xFF ;; R509
.byte 0xFF, 0xFF ;; R50A
.byte 0xFF, 0xFF ;; R50B
.byte 0xFF, 0xFF ;; R50C
.byte 0xFF, 0xFF ;; R50D
.byte 0xFF, 0xFF ;; R50E
.byte 0xFF, 0xFF ;; R50F
.byte 0xFF, 0xFF ;; R510
.byte 0xFF, 0xFF ;; R511
.byte 0xFF, 0xFF ;; R512
.byte 0xFF, 0xFF ;; R513
.byte 0xFF, 0xFF ;; R514
.byte 0xFF, 0xFF ;; R515
.byte 0xFF, 0xFF ;; R516
.byte 0xFF, 0xFF ;; R517
.byte 0xFF, 0xFF ;; R518
.byte 0xFF, 0xFF ;; R519
.byte 0xFF, 0xFF ;; R51A
.byte 0xFF, 0xFF ;; R51B
.byte 0xFF, 0xFF ;; R51C
.byte 0xFF, 0xFF ;; R51D
.byte 0xFF, 0xFF ;; R51E
.byte 0xFF, 0xFF ;; R51F
.byte 0xFF, 0xFF ;; R520
.byte 0xFF, 0xFF ;; R521
.byte 0xFF, 0xFF ;; R522
.byte 0xFF, 0xFF ;; R523
.byte 0xFF, 0xFF ;; R524
.byte 0xFF, 0xFF ;; R525
.byte 0xFF, 0xFF ;; R526
.byte 0xFF, 0xFF ;; R527
.byte 0xFF, 0xFF ;; R528
.byte 0xFF, 0xFF ;; R529
.byte 0xFF, 0xFF ;; R52A
.byte 0xFF, 0xFF ;; R52B
.byte 0xFF, 0xFF ;; R52C
.byte 0xFF, 0xFF ;; R52D
.byte 0xFF, 0xFF ;; R52E
.byte 0xFF, 0xFF ;; R52F
;; XA Table
.org 0x800003C0 ;; PL0
.dh 0x04, 0x49, 0x28 ;;
.dh 0x06, 0x6D, 0x0C ;;
.dh 0x07, 0x24, 0x23 ;;
.dh 0x04, 0x71, 0x08 ;;
.dh 0x07, 0x00, 0x24 ;;
.dh 0x01, 0x66, 0x11 ;;
.dh 0x03, 0x4B, 0x29 ;;
.dh 0x07, 0x66, 0x0B ;;
.dh 0x05, 0x66, 0x11 ;;
.dh 0x03, 0x00, 0x4B ;;
.dh 0x05, 0x00, 0x40 ;;
.dh 0x06, 0x00, 0x3A ;;
.dh 0x01, 0x00, 0x66 ;;
.dh 0x06, 0x60, 0x0D ;;
.dh 0x04, 0x00, 0x49 ;;
.dh 0x05, 0x40, 0x26 ;;
.dh 0x07, 0x47, 0x1F ;;
.dh 0x02, 0x5E, 0x1A ;;
.dh 0x06, 0x3A, 0x26 ;;
.dh 0x00, 0x00, 0x79 ;;
.dh 0x02, 0x00, 0x5E ;;
.org 0x800005E0 ;; PL1 |
MeganGrass/Resident-Evil-2-Starter-Kit | 8,961 | source/assembly/sound/stage4.s |
.org 0x80000180
.fill 0x240, 0xFF
.org 0x800003C0
.fill 0x440, 0x00
;; BGM Table
.org 0x80000180 ;; PL0 [Scenario A]
.byte 0x0F, 0x99 ;; R400
.byte 0x4C, 0xFF ;; R401
.byte 0x0F, 0xFF ;; R402
.byte 0x0C, 0xFF ;; R403
.byte 0x58, 0xFF ;; R404
.byte 0x0F, 0x98 ;; R405
.byte 0xFF, 0xFF ;; R406
.byte 0x0F, 0x99 ;; R407
.byte 0x14, 0x18 ;; R408
.byte 0x14, 0x9A ;; R409
.byte 0x5A, 0xFF ;; R40A
.byte 0x1B, 0xC3 ;; R40B
.byte 0xFF, 0xFF ;; R40C
.byte 0x17, 0xFF ;; R40D
.byte 0x17, 0xFF ;; R40E
.byte 0x1B, 0xC3 ;; R40F
.byte 0x14, 0xE2 ;; R410
.byte 0xFF, 0xFF ;; R411
.byte 0xFF, 0xFF ;; R412
.byte 0xFF, 0xFF ;; R413
.byte 0xFF, 0xFF ;; R414
.byte 0xFF, 0xFF ;; R415
.byte 0xFF, 0xFF ;; R416
.byte 0xFF, 0xFF ;; R417
.byte 0xFF, 0xFF ;; R418
.byte 0xFF, 0xFF ;; R419
.byte 0xFF, 0xFF ;; R41A
.byte 0xFF, 0xFF ;; R41B
.byte 0xFF, 0xFF ;; R41C
.byte 0xFF, 0xFF ;; R41D
.byte 0xFF, 0xFF ;; R41E
.byte 0xFF, 0xFF ;; R41F
.byte 0xFF, 0xFF ;; R420
.byte 0xFF, 0xFF ;; R421
.byte 0xFF, 0xFF ;; R422
.byte 0xFF, 0xFF ;; R423
.byte 0xFF, 0xFF ;; R424
.byte 0xFF, 0xFF ;; R425
.byte 0xFF, 0xFF ;; R426
.byte 0xFF, 0xFF ;; R427
.byte 0xFF, 0xFF ;; R428
.byte 0xFF, 0xFF ;; R429
.byte 0xFF, 0xFF ;; R42A
.byte 0xFF, 0xFF ;; R42B
.byte 0xFF, 0xFF ;; R42C
.byte 0xFF, 0xFF ;; R42D
.byte 0xFF, 0xFF ;; R42E
.byte 0xFF, 0xFF ;; R42F
.org 0x800001E0 ;; PL0 [Scenario B]
.byte 0x0F, 0x99 ;; R400
.byte 0x4C, 0xFF ;; R401
.byte 0x0F, 0xFF ;; R402
.byte 0x0C, 0xFF ;; R403
.byte 0x58, 0xFF ;; R404
.byte 0x0F, 0x98 ;; R405
.byte 0xFF, 0xFF ;; R406
.byte 0x0F, 0x99 ;; R407
.byte 0x14, 0x18 ;; R408
.byte 0x14, 0x9A ;; R409
.byte 0x5A, 0xFF ;; R40A
.byte 0x1B, 0xC3 ;; R40B
.byte 0xFF, 0xFF ;; R40C
.byte 0x17, 0xFF ;; R40D
.byte 0x17, 0xFF ;; R40E
.byte 0x1B, 0xC3 ;; R40F
.byte 0x14, 0xE2 ;; R410
.byte 0xFF, 0xFF ;; R411
.byte 0xFF, 0xFF ;; R412
.byte 0xFF, 0xFF ;; R413
.byte 0xFF, 0xFF ;; R414
.byte 0xFF, 0xFF ;; R415
.byte 0xFF, 0xFF ;; R416
.byte 0xFF, 0xFF ;; R417
.byte 0xFF, 0xFF ;; R418
.byte 0xFF, 0xFF ;; R419
.byte 0xFF, 0xFF ;; R41A
.byte 0xFF, 0xFF ;; R41B
.byte 0xFF, 0xFF ;; R41C
.byte 0xFF, 0xFF ;; R41D
.byte 0xFF, 0xFF ;; R41E
.byte 0xFF, 0xFF ;; R41F
.byte 0xFF, 0xFF ;; R420
.byte 0xFF, 0xFF ;; R421
.byte 0xFF, 0xFF ;; R422
.byte 0xFF, 0xFF ;; R423
.byte 0xFF, 0xFF ;; R424
.byte 0xFF, 0xFF ;; R425
.byte 0xFF, 0xFF ;; R426
.byte 0xFF, 0xFF ;; R427
.byte 0xFF, 0xFF ;; R428
.byte 0xFF, 0xFF ;; R429
.byte 0xFF, 0xFF ;; R42A
.byte 0xFF, 0xFF ;; R42B
.byte 0xFF, 0xFF ;; R42C
.byte 0xFF, 0xFF ;; R42D
.byte 0xFF, 0xFF ;; R42E
.byte 0xFF, 0xFF ;; R42F
.org 0x80000240 ;; PL1 [Scenario A]
.byte 0x5F, 0x96 ;; R400
.byte 0x1F, 0xFF ;; R401
.byte 0x0F, 0xFF ;; R402
.byte 0x0C, 0xFF ;; R403
.byte 0xFF, 0xFF ;; R404
.byte 0x0F, 0x98 ;; R405
.byte 0xFF, 0xFF ;; R406
.byte 0x0F, 0x99 ;; R407
.byte 0x14, 0x9A ;; R408
.byte 0x14, 0x98 ;; R409
.byte 0x5A, 0xFF ;; R40A
.byte 0x1B, 0xC3 ;; R40B
.byte 0x1F, 0x57 ;; R40C
.byte 0x17, 0xFF ;; R40D
.byte 0x17, 0xFF ;; R40E
.byte 0x1F, 0xA3 ;; R40F
.byte 0x14, 0xF6 ;; R410
.byte 0xFF, 0xFF ;; R411
.byte 0xFF, 0xFF ;; R412
.byte 0xFF, 0xFF ;; R413
.byte 0xFF, 0xFF ;; R414
.byte 0xFF, 0xFF ;; R415
.byte 0xFF, 0xFF ;; R416
.byte 0xFF, 0xFF ;; R417
.byte 0xFF, 0xFF ;; R418
.byte 0xFF, 0xFF ;; R419
.byte 0xFF, 0xFF ;; R41A
.byte 0xFF, 0xFF ;; R41B
.byte 0xFF, 0xFF ;; R41C
.byte 0xFF, 0xFF ;; R41D
.byte 0xFF, 0xFF ;; R41E
.byte 0xFF, 0xFF ;; R41F
.byte 0xFF, 0xFF ;; R420
.byte 0xFF, 0xFF ;; R421
.byte 0xFF, 0xFF ;; R422
.byte 0xFF, 0xFF ;; R423
.byte 0xFF, 0xFF ;; R424
.byte 0xFF, 0xFF ;; R425
.byte 0xFF, 0xFF ;; R426
.byte 0xFF, 0xFF ;; R427
.byte 0xFF, 0xFF ;; R428
.byte 0xFF, 0xFF ;; R429
.byte 0xFF, 0xFF ;; R42A
.byte 0xFF, 0xFF ;; R42B
.byte 0xFF, 0xFF ;; R42C
.byte 0xFF, 0xFF ;; R42D
.byte 0xFF, 0xFF ;; R42E
.byte 0xFF, 0xFF ;; R42F
.org 0x800002A0 ;; PL1 [Scenario B]
.byte 0xFF, 0x96 ;; R400
.byte 0x1F, 0xFF ;; R401
.byte 0x0F, 0xFF ;; R402
.byte 0x0C, 0xFF ;; R403
.byte 0xFF, 0xFF ;; R404
.byte 0x0F, 0x98 ;; R405
.byte 0xFF, 0xFF ;; R406
.byte 0x0F, 0x99 ;; R407
.byte 0x14, 0x9A ;; R408
.byte 0x14, 0x98 ;; R409
.byte 0x5A, 0xFF ;; R40A
.byte 0x1B, 0xC3 ;; R40B
.byte 0x1F, 0x57 ;; R40C
.byte 0x17, 0xFF ;; R40D
.byte 0x17, 0xDC ;; R40E
.byte 0x1F, 0xA3 ;; R40F
.byte 0x14, 0xFF ;; R410
.byte 0xFF, 0xFF ;; R411
.byte 0xFF, 0xFF ;; R412
.byte 0xFF, 0xFF ;; R413
.byte 0xFF, 0xFF ;; R414
.byte 0xFF, 0xFF ;; R415
.byte 0xFF, 0xFF ;; R416
.byte 0xFF, 0xFF ;; R417
.byte 0xFF, 0xFF ;; R418
.byte 0xFF, 0xFF ;; R419
.byte 0xFF, 0xFF ;; R41A
.byte 0xFF, 0xFF ;; R41B
.byte 0xFF, 0xFF ;; R41C
.byte 0xFF, 0xFF ;; R41D
.byte 0xFF, 0xFF ;; R41E
.byte 0xFF, 0xFF ;; R41F
.byte 0xFF, 0xFF ;; R420
.byte 0xFF, 0xFF ;; R421
.byte 0xFF, 0xFF ;; R422
.byte 0xFF, 0xFF ;; R423
.byte 0xFF, 0xFF ;; R424
.byte 0xFF, 0xFF ;; R425
.byte 0xFF, 0xFF ;; R426
.byte 0xFF, 0xFF ;; R427
.byte 0xFF, 0xFF ;; R428
.byte 0xFF, 0xFF ;; R429
.byte 0xFF, 0xFF ;; R42A
.byte 0xFF, 0xFF ;; R42B
.byte 0xFF, 0xFF ;; R42C
.byte 0xFF, 0xFF ;; R42D
.byte 0xFF, 0xFF ;; R42E
.byte 0xFF, 0xFF ;; R42F
.org 0x80000300 ;; 4th Survivor
.byte 0xFF, 0xFF ;; R400
.byte 0xFF, 0xFF ;; R401
.byte 0xFF, 0xFF ;; R402
.byte 0xFF, 0xFF ;; R403
.byte 0xFF, 0xFF ;; R404
.byte 0xFF, 0xFF ;; R405
.byte 0xFF, 0xFF ;; R406
.byte 0xFF, 0xFF ;; R407
.byte 0xFF, 0xFF ;; R408
.byte 0xFF, 0xFF ;; R409
.byte 0xFF, 0xFF ;; R40A
.byte 0xFF, 0xFF ;; R40B
.byte 0xFF, 0xFF ;; R40C
.byte 0xFF, 0xFF ;; R40D
.byte 0xFF, 0xFF ;; R40E
.byte 0xFF, 0xFF ;; R40F
.byte 0xFF, 0xFF ;; R410
.byte 0xFF, 0xFF ;; R411
.byte 0xFF, 0xFF ;; R412
.byte 0xFF, 0xFF ;; R413
.byte 0xFF, 0xFF ;; R414
.byte 0xFF, 0xFF ;; R415
.byte 0xFF, 0xFF ;; R416
.byte 0xFF, 0xFF ;; R417
.byte 0xFF, 0xFF ;; R418
.byte 0xFF, 0xFF ;; R419
.byte 0xFF, 0xFF ;; R41A
.byte 0xFF, 0xFF ;; R41B
.byte 0xFF, 0xFF ;; R41C
.byte 0xFF, 0xFF ;; R41D
.byte 0xFF, 0xFF ;; R41E
.byte 0xFF, 0xFF ;; R41F
.byte 0xFF, 0xFF ;; R420
.byte 0xFF, 0xFF ;; R421
.byte 0xFF, 0xFF ;; R422
.byte 0xFF, 0xFF ;; R423
.byte 0xFF, 0xFF ;; R424
.byte 0xFF, 0xFF ;; R425
.byte 0xFF, 0xFF ;; R426
.byte 0xFF, 0xFF ;; R427
.byte 0xFF, 0xFF ;; R428
.byte 0xFF, 0xFF ;; R429
.byte 0xFF, 0xFF ;; R42A
.byte 0xFF, 0xFF ;; R42B
.byte 0xFF, 0xFF ;; R42C
.byte 0xFF, 0xFF ;; R42D
.byte 0xFF, 0xFF ;; R42E
.byte 0xFF, 0xFF ;; R42F
.org 0x80000360 ;; Ex-Battle
.byte 0x35, 0xB7 ;; R400
.byte 0x4C, 0xFF ;; R401
.byte 0x35, 0xFF ;; R402
.byte 0x0C, 0xFF ;; R403
.byte 0x35, 0xFF ;; R404
.byte 0x35, 0xFF ;; R405
.byte 0xFF, 0xFF ;; R406
.byte 0x35, 0xFF ;; R407
.byte 0x35, 0xFF ;; R408
.byte 0x35, 0xFF ;; R409
.byte 0x35, 0xFF ;; R40A
.byte 0xFF, 0xFF ;; R40B
.byte 0xFF, 0xFF ;; R40C
.byte 0x35, 0xFF ;; R40D
.byte 0x35, 0xFF ;; R40E
.byte 0xFF, 0xFF ;; R40F
.byte 0x35, 0xFF ;; R410
.byte 0xFF, 0xFF ;; R411
.byte 0xFF, 0xFF ;; R412
.byte 0xFF, 0xFF ;; R413
.byte 0xFF, 0xFF ;; R414
.byte 0xFF, 0xFF ;; R415
.byte 0xFF, 0xFF ;; R416
.byte 0xFF, 0xFF ;; R417
.byte 0xFF, 0xFF ;; R418
.byte 0xFF, 0xFF ;; R419
.byte 0xFF, 0xFF ;; R41A
.byte 0xFF, 0xFF ;; R41B
.byte 0xFF, 0xFF ;; R41C
.byte 0xFF, 0xFF ;; R41D
.byte 0xFF, 0xFF ;; R41E
.byte 0xFF, 0xFF ;; R41F
.byte 0xFF, 0xFF ;; R420
.byte 0xFF, 0xFF ;; R421
.byte 0xFF, 0xFF ;; R422
.byte 0xFF, 0xFF ;; R423
.byte 0xFF, 0xFF ;; R424
.byte 0xFF, 0xFF ;; R425
.byte 0xFF, 0xFF ;; R426
.byte 0xFF, 0xFF ;; R427
.byte 0xFF, 0xFF ;; R428
.byte 0xFF, 0xFF ;; R429
.byte 0xFF, 0xFF ;; R42A
.byte 0xFF, 0xFF ;; R42B
.byte 0xFF, 0xFF ;; R42C
.byte 0xFF, 0xFF ;; R42D
.byte 0xFF, 0xFF ;; R42E
.byte 0xFF, 0xFF ;; R42F
;; XA Table
.org 0x800003C0 ;; PL0
.dh 0x0C, 0x56, 0x06 ;;
.dh 0x02, 0x54, 0x08 ;;
.dh 0x0E, 0x00, 0x1C ;;
.dh 0x08, 0x31, 0x2A ;;
.dh 0x09, 0x52, 0x0A ;;
.dh 0x04, 0x47, 0x13 ;;
.dh 0x0E, 0x1C, 0x1C ;;
.dh 0x00, 0x00, 0x5A ;;
.dh 0x0F, 0x00, 0x19 ;;
.dh 0x06, 0x00, 0x44 ;;
.dh 0x0C, 0x4D, 0x09 ;;
.dh 0x0B, 0x00, 0x2F ;;
.dh 0x01, 0x00, 0x5A ;;
.dh 0x0F, 0x2B, 0x10 ;;
.dh 0x07, 0x00, 0x41 ;;
.dh 0x0B, 0x2F, 0x2C ;;
.dh 0x09, 0x31, 0x21 ;;
.dh 0x04, 0x00, 0x47 ;;
.dh 0x08, 0x00, 0x31 ;;
.dh 0x0C, 0x2F, 0x1E ;;
.dh 0x03, 0x00, 0x4E ;;
.dh 0x02, 0x00, 0x54 ;;
.dh 0x0D, 0x00, 0x1E ;;
.dh 0x05, 0x00, 0x46 ;;
.dh 0x0F, 0x19, 0x12 ;;
.dh 0x07, 0x41, 0x1B ;;
.dh 0x0F, 0x44, 0x08 ;;
.dh 0x09, 0x00, 0x31 ;;
.dh 0x0D, 0x1E, 0x1E ;;
.dh 0x06, 0x44, 0x17 ;;
.dh 0x0A, 0x50, 0x0B ;;
.dh 0x03, 0x4E, 0x0D ;;
.dh 0x0F, 0x54, 0x07 ;;
.dh 0x0E, 0x52, 0x09 ;;
.dh 0x0A, 0x00, 0x31 ;;
.dh 0x0A, 0x31, 0x1F ;;
.dh 0x05, 0x46, 0x13 ;;
.dh 0x0F, 0x3B, 0x09 ;;
.dh 0x0E, 0x38, 0x1A ;;
.dh 0x0F, 0x4C, 0x08 ;;
.dh 0x0C, 0x00, 0x2F ;;
.dh 0x0D, 0x3C, 0x1E ;;
.org 0x800005E0 ;; PL1 |
MeganGrass/Resident-Evil-2-Starter-Kit | 9,585 | source/assembly/sound/stage6.s |
.org 0x80000180
.fill 0x240, 0xFF
.org 0x800003C0
.fill 0x440, 0x00
;; BGM Table
.org 0x80000180 ;; PL0 [Scenario A]
.byte 0xFF, 0x94 ;; R600
.byte 0xFF, 0xFF ;; R601
.byte 0x5E, 0xA0 ;; R602
.byte 0x5E, 0xA0 ;; R603
.byte 0x5D, 0xA5 ;; R604
.byte 0xFF, 0xA5 ;; R605
.byte 0x22, 0xFF ;; R606
.byte 0xFF, 0xD5 ;; R607
.byte 0x22, 0xA7 ;; R608
.byte 0xFF, 0xFF ;; R609
.byte 0xFF, 0xFF ;; R60A
.byte 0x22, 0xFF ;; R60B
.byte 0x22, 0xFF ;; R60C
.byte 0xFF, 0xFF ;; R60D
.byte 0xFF, 0x94 ;; R60E
.byte 0x24, 0xFF ;; R60F
.byte 0xFF, 0xFF ;; R610
.byte 0x11, 0xA8 ;; R611
.byte 0x22, 0xFF ;; R612
.byte 0x25, 0xFF ;; R613
.byte 0x22, 0xFF ;; R614
.byte 0xFF, 0xAD ;; R615
.byte 0x22, 0xFF ;; R616
.byte 0x52, 0xB4 ;; R617
.byte 0xFF, 0xFF ;; R618
.byte 0xFF, 0xFF ;; R619
.byte 0xFF, 0xFF ;; R61A
.byte 0xFF, 0xFF ;; R61B
.byte 0xFF, 0xFF ;; R61C
.byte 0xFF, 0xFF ;; R61D
.byte 0xFF, 0xFF ;; R61E
.byte 0xFF, 0xFF ;; R61F
.byte 0xFF, 0xFF ;; R620
.byte 0xFF, 0xFF ;; R621
.byte 0xFF, 0xFF ;; R622
.byte 0xFF, 0xFF ;; R623
.byte 0xFF, 0xFF ;; R624
.byte 0xFF, 0xFF ;; R625
.byte 0xFF, 0xFF ;; R626
.byte 0xFF, 0xFF ;; R627
.byte 0xFF, 0xFF ;; R628
.byte 0xFF, 0xFF ;; R629
.byte 0xFF, 0xFF ;; R62A
.byte 0xFF, 0xFF ;; R62B
.byte 0xFF, 0xFF ;; R62C
.byte 0xFF, 0xFF ;; R62D
.byte 0xFF, 0xFF ;; R62E
.byte 0xFF, 0xFF ;; R62F
.org 0x800001E0 ;; PL0 [Scenario B]
.byte 0xFF, 0x94 ;; R600
.byte 0xFF, 0xFF ;; R601
.byte 0x5E, 0xA0 ;; R602
.byte 0x5E, 0xA0 ;; R603
.byte 0x5D, 0xA5 ;; R604
.byte 0xFF, 0xA5 ;; R605
.byte 0x22, 0xFF ;; R606
.byte 0x0C, 0xFF ;; R607
.byte 0x22, 0xA7 ;; R608
.byte 0xFF, 0xFF ;; R609
.byte 0xFF, 0xFF ;; R60A
.byte 0x22, 0xFF ;; R60B
.byte 0x22, 0xFF ;; R60C
.byte 0xFF, 0xFF ;; R60D
.byte 0xFF, 0x94 ;; R60E
.byte 0x24, 0xFF ;; R60F
.byte 0xFF, 0xFF ;; R610
.byte 0x11, 0xA8 ;; R611
.byte 0x22, 0xFF ;; R612
.byte 0x25, 0xFF ;; R613
.byte 0x22, 0xFF ;; R614
.byte 0xFF, 0xAD ;; R615
.byte 0x22, 0xFF ;; R616
.byte 0x52, 0xB4 ;; R617
.byte 0xFF, 0xFF ;; R618
.byte 0xFF, 0xFF ;; R619
.byte 0xFF, 0xFF ;; R61A
.byte 0xFF, 0xFF ;; R61B
.byte 0xFF, 0xFF ;; R61C
.byte 0xFF, 0xFF ;; R61D
.byte 0xFF, 0xFF ;; R61E
.byte 0xFF, 0xFF ;; R61F
.byte 0xFF, 0xFF ;; R620
.byte 0xFF, 0xFF ;; R621
.byte 0xFF, 0xFF ;; R622
.byte 0xFF, 0xFF ;; R623
.byte 0xFF, 0xFF ;; R624
.byte 0xFF, 0xFF ;; R625
.byte 0xFF, 0xFF ;; R626
.byte 0xFF, 0xFF ;; R627
.byte 0xFF, 0xFF ;; R628
.byte 0xFF, 0xFF ;; R629
.byte 0xFF, 0xFF ;; R62A
.byte 0xFF, 0xFF ;; R62B
.byte 0xFF, 0xFF ;; R62C
.byte 0xFF, 0xFF ;; R62D
.byte 0xFF, 0xFF ;; R62E
.byte 0xFF, 0xFF ;; R62F
.org 0x80000240 ;; PL1 [Scenario A]
.byte 0xFF, 0x94 ;; R600
.byte 0xFF, 0xFF ;; R601
.byte 0xFF, 0xA0 ;; R602
.byte 0xFF, 0xA0 ;; R603
.byte 0x5D, 0xA5 ;; R604
.byte 0xFF, 0xA5 ;; R605
.byte 0x22, 0xFF ;; R606
.byte 0xFF, 0xE6 ;; R607
.byte 0x22, 0xA7 ;; R608
.byte 0xFF, 0xFF ;; R609
.byte 0xFF, 0xFF ;; R60A
.byte 0x22, 0xFF ;; R60B
.byte 0x22, 0xFF ;; R60C
.byte 0xFF, 0xFF ;; R60D
.byte 0xFF, 0x94 ;; R60E
.byte 0x24, 0xFF ;; R60F
.byte 0xFF, 0xFF ;; R610
.byte 0x22, 0xFF ;; R611
.byte 0x22, 0xFF ;; R612
.byte 0x25, 0xFF ;; R613
.byte 0x22, 0xFF ;; R614
.byte 0xFF, 0xAD ;; R615
.byte 0x22, 0xFF ;; R616
.byte 0x52, 0xB4 ;; R617
.byte 0xFF, 0xFF ;; R618
.byte 0xFF, 0xFF ;; R619
.byte 0xFF, 0xFF ;; R61A
.byte 0xFF, 0xFF ;; R61B
.byte 0xFF, 0xFF ;; R61C
.byte 0xFF, 0xFF ;; R61D
.byte 0xFF, 0xFF ;; R61E
.byte 0xFF, 0xFF ;; R61F
.byte 0xFF, 0xFF ;; R620
.byte 0xFF, 0xFF ;; R621
.byte 0xFF, 0xFF ;; R622
.byte 0xFF, 0xFF ;; R623
.byte 0xFF, 0xFF ;; R624
.byte 0xFF, 0xFF ;; R625
.byte 0xFF, 0xFF ;; R626
.byte 0xFF, 0xFF ;; R627
.byte 0xFF, 0xFF ;; R628
.byte 0xFF, 0xFF ;; R629
.byte 0xFF, 0xFF ;; R62A
.byte 0xFF, 0xFF ;; R62B
.byte 0xFF, 0xFF ;; R62C
.byte 0xFF, 0xFF ;; R62D
.byte 0xFF, 0xFF ;; R62E
.byte 0xFF, 0xFF ;; R62F
.org 0x800002A0 ;; PL1 [Scenario B]
.byte 0xFF, 0x94 ;; R600
.byte 0xFF, 0xFF ;; R601
.byte 0xFF, 0xA0 ;; R602
.byte 0xFF, 0xA0 ;; R603
.byte 0x5D, 0xA5 ;; R604
.byte 0xFF, 0xA5 ;; R605
.byte 0x22, 0xFF ;; R606
.byte 0x0C, 0xFF ;; R607
.byte 0x22, 0xA7 ;; R608
.byte 0xFF, 0xFF ;; R609
.byte 0xFF, 0xFF ;; R60A
.byte 0x22, 0xFF ;; R60B
.byte 0x22, 0xFF ;; R60C
.byte 0xFF, 0xFF ;; R60D
.byte 0xFF, 0x94 ;; R60E
.byte 0x24, 0xFF ;; R60F
.byte 0xFF, 0xFF ;; R610
.byte 0x22, 0xFF ;; R611
.byte 0x22, 0xFF ;; R612
.byte 0x25, 0xFF ;; R613
.byte 0x22, 0xFF ;; R614
.byte 0xFF, 0xAD ;; R615
.byte 0x22, 0xFF ;; R616
.byte 0x52, 0xB4 ;; R617
.byte 0xFF, 0xFF ;; R618
.byte 0xFF, 0xFF ;; R619
.byte 0xFF, 0xFF ;; R61A
.byte 0xFF, 0xFF ;; R61B
.byte 0xFF, 0xFF ;; R61C
.byte 0xFF, 0xFF ;; R61D
.byte 0xFF, 0xFF ;; R61E
.byte 0xFF, 0xFF ;; R61F
.byte 0xFF, 0xFF ;; R620
.byte 0xFF, 0xFF ;; R621
.byte 0xFF, 0xFF ;; R622
.byte 0xFF, 0xFF ;; R623
.byte 0xFF, 0xFF ;; R624
.byte 0xFF, 0xFF ;; R625
.byte 0xFF, 0xFF ;; R626
.byte 0xFF, 0xFF ;; R627
.byte 0xFF, 0xFF ;; R628
.byte 0xFF, 0xFF ;; R629
.byte 0xFF, 0xFF ;; R62A
.byte 0xFF, 0xFF ;; R62B
.byte 0xFF, 0xFF ;; R62C
.byte 0xFF, 0xFF ;; R62D
.byte 0xFF, 0xFF ;; R62E
.byte 0xFF, 0xFF ;; R62F
.org 0x80000300 ;; 4th Survivor
.byte 0xFF, 0xFF ;; R600
.byte 0xFF, 0xFF ;; R601
.byte 0xFF, 0xFF ;; R602
.byte 0xFF, 0xFF ;; R603
.byte 0xFF, 0xFF ;; R604
.byte 0xFF, 0xFF ;; R605
.byte 0xFF, 0xFF ;; R606
.byte 0xFF, 0xFF ;; R607
.byte 0xFF, 0xFF ;; R608
.byte 0xFF, 0xFF ;; R609
.byte 0xFF, 0xFF ;; R60A
.byte 0xFF, 0xFF ;; R60B
.byte 0xFF, 0xFF ;; R60C
.byte 0xFF, 0xFF ;; R60D
.byte 0xFF, 0xFF ;; R60E
.byte 0xFF, 0xFF ;; R60F
.byte 0xFF, 0xFF ;; R610
.byte 0xFF, 0xFF ;; R611
.byte 0xFF, 0xFF ;; R612
.byte 0xFF, 0xFF ;; R613
.byte 0xFF, 0xFF ;; R614
.byte 0xFF, 0xFF ;; R615
.byte 0xFF, 0xFF ;; R616
.byte 0xFF, 0xFF ;; R617
.byte 0xFF, 0xFF ;; R618
.byte 0xFF, 0xFF ;; R619
.byte 0xFF, 0xFF ;; R61A
.byte 0xFF, 0xFF ;; R61B
.byte 0xFF, 0xFF ;; R61C
.byte 0xFF, 0xFF ;; R61D
.byte 0xFF, 0xFF ;; R61E
.byte 0xFF, 0xFF ;; R61F
.byte 0xFF, 0xFF ;; R620
.byte 0xFF, 0xFF ;; R621
.byte 0xFF, 0xFF ;; R622
.byte 0xFF, 0xFF ;; R623
.byte 0xFF, 0xFF ;; R624
.byte 0xFF, 0xFF ;; R625
.byte 0xFF, 0xFF ;; R626
.byte 0xFF, 0xFF ;; R627
.byte 0xFF, 0xFF ;; R628
.byte 0xFF, 0xFF ;; R629
.byte 0xFF, 0xFF ;; R62A
.byte 0xFF, 0xFF ;; R62B
.byte 0xFF, 0xFF ;; R62C
.byte 0xFF, 0xFF ;; R62D
.byte 0xFF, 0xFF ;; R62E
.byte 0xFF, 0xFF ;; R62F
.org 0x80000360 ;; Ex-Battle
.byte 0xFF, 0xFF ;; R600
.byte 0x37, 0xFF ;; R601
.byte 0x37, 0xFF ;; R602
.byte 0x37, 0xFF ;; R603
.byte 0x37, 0xFF ;; R604
.byte 0x37, 0xFF ;; R605
.byte 0x37, 0xFF ;; R606
.byte 0x0C, 0xFF ;; R607
.byte 0x37, 0xFF ;; R608
.byte 0x37, 0xFF ;; R609
.byte 0x37, 0xFF ;; R60A
.byte 0x37, 0xFF ;; R60B
.byte 0x37, 0xFF ;; R60C
.byte 0x37, 0xFF ;; R60D
.byte 0x37, 0xFF ;; R60E
.byte 0x37, 0xFF ;; R60F
.byte 0x37, 0xFF ;; R610
.byte 0xFF, 0xFF ;; R611
.byte 0x77, 0xFF ;; R612
.byte 0x37, 0xFF ;; R613
.byte 0x37, 0xFF ;; R614
.byte 0x37, 0xFF ;; R615
.byte 0x37, 0xFF ;; R616
.byte 0xFF, 0xFF ;; R617
.byte 0xFF, 0xFF ;; R618
.byte 0xFF, 0xFF ;; R619
.byte 0xFF, 0xFF ;; R61A
.byte 0xFF, 0xFF ;; R61B
.byte 0xFF, 0xFF ;; R61C
.byte 0xFF, 0xFF ;; R61D
.byte 0xFF, 0xFF ;; R61E
.byte 0xFF, 0xFF ;; R61F
.byte 0xFF, 0xFF ;; R620
.byte 0xFF, 0xFF ;; R621
.byte 0xFF, 0xFF ;; R622
.byte 0xFF, 0xFF ;; R623
.byte 0xFF, 0xFF ;; R624
.byte 0xFF, 0xFF ;; R625
.byte 0xFF, 0xFF ;; R626
.byte 0xFF, 0xFF ;; R627
.byte 0xFF, 0xFF ;; R628
.byte 0xFF, 0xFF ;; R629
.byte 0xFF, 0xFF ;; R62A
.byte 0xFF, 0xFF ;; R62B
.byte 0xFF, 0xFF ;; R62C
.byte 0xFF, 0xFF ;; R62D
.byte 0xFF, 0xFF ;; R62E
.byte 0xFF, 0xFF ;; R62F
;; XA Table
.org 0x800003C0 ;; PL0
.dh 0x0D, 0x86, 0x1B ;;
.dh 0x06, 0xBF, 0x0D ;;
.dh 0x03, 0x00, 0x80 ;;
.dh 0x07, 0x68, 0x48 ;;
.dh 0x0B, 0xC2, 0x0B ;;
.dh 0x04, 0x00, 0x7C ;;
.dh 0x0F, 0x31, 0x0D ;;
.dh 0x07, 0x00, 0x68 ;;
.dh 0x0A, 0x6F, 0x35 ;;
.dh 0x0B, 0x34, 0x33 ;;
.dh 0x0E, 0x32, 0x16 ;;
.dh 0x0E, 0x48, 0x16 ;;
.dh 0x0D, 0x46, 0x20 ;;
.dh 0x05, 0x00, 0x6C ;;
.dh 0x0D, 0x66, 0x20 ;;
.dh 0x0C, 0x00, 0x2B ;;
.dh 0x08, 0x66, 0x48 ;;
.dh 0x0F, 0x77, 0x09 ;;
.dh 0x05, 0xC6, 0x06 ;;
.dh 0x0F, 0x63, 0x0A ;;
.dh 0x01, 0xA7, 0x26 ;;
.dh 0x09, 0x7F, 0x3C ;;
.dh 0x06, 0x6B, 0x54 ;;
.dh 0x0F, 0x6D, 0x0A ;;
.dh 0x0E, 0x9F, 0x14 ;;
.dh 0x0E, 0xB3, 0x13 ;;
.dh 0x0B, 0x67, 0x2E ;;
.dh 0x0A, 0xA4, 0x29 ;;
.dh 0x02, 0x00, 0x88 ;;
.dh 0x0F, 0x58, 0x0B ;;
.dh 0x09, 0xBB, 0x11 ;;
.dh 0x03, 0x80, 0x4B ;;
.dh 0x09, 0x00, 0x40 ;;
.dh 0x07, 0xB0, 0x1C ;;
.dh 0x08, 0x00, 0x66 ;;
.dh 0x0F, 0x3E, 0x0D ;;
.dh 0x04, 0x7C, 0x49 ;;
.dh 0x0C, 0xA4, 0x26 ;;
.dh 0x08, 0xAE, 0x1F ;;
.dh 0x0C, 0x2B, 0x2A ;;
.dh 0x0D, 0xBC, 0x0F ;;
.dh 0x0E, 0x00, 0x1A ;;
.dh 0x0E, 0x5E, 0x16 ;;
.dh 0x0E, 0x74, 0x16 ;;
.dh 0x0A, 0x39, 0x36 ;;
.dh 0x0B, 0x00, 0x34 ;;
.dh 0x0C, 0x55, 0x28 ;;
.dh 0x0D, 0x00, 0x23 ;;
.dh 0x0F, 0x13, 0x0F ;;
.dh 0x0E, 0x1A, 0x18 ;;
.dh 0x04, 0xC5, 0x08 ;;
.dh 0x0D, 0xA1, 0x1B ;;
.dh 0x0C, 0x7D, 0x27 ;;
.dh 0x02, 0x88, 0x41 ;;
.dh 0x0E, 0x8A, 0x15 ;;
.dh 0x09, 0x40, 0x3F ;;
.dh 0x0A, 0x00, 0x39 ;;
.dh 0x05, 0x6C, 0x5A ;;
.dh 0x0F, 0x00, 0x13 ;;
.dh 0x0F, 0x22, 0x0F ;;
.dh 0x0D, 0x23, 0x23 ;;
.dh 0x0B, 0x95, 0x2D ;;
.dh 0x0F, 0x4B, 0x0D ;;
.dh 0x00, 0x00, 0xCD ;;
.dh 0x01, 0x00, 0xA7 ;;
.dh 0x06, 0x00, 0x6B ;;
.org 0x800005E0 ;; PL1 |
MeganGrass/Resident-Evil-2-Starter-Kit | 8,649 | source/assembly/sound/stage1.s |
.org 0x80000180
.fill 0x240, 0xFF
.org 0x800003C0
.fill 0x440, 0x00
;; BGM Table
.org 0x80000180 ;; PL0 [Scenario A]
.byte 0x0B, 0x01 ;; R100
.byte 0x41, 0xC0 ;; R101
.byte 0x00, 0xFF ;; R102
.byte 0x00, 0x05 ;; R103
.byte 0x0B, 0x01 ;; R104
.byte 0x00, 0x05 ;; R105
.byte 0xFF, 0xC3 ;; R106
.byte 0x00, 0x05 ;; R107
.byte 0x00, 0xC2 ;; R108
.byte 0x08, 0xC3 ;; R109
.byte 0x04, 0xFF ;; R10A
.byte 0x08, 0xFF ;; R10B
.byte 0x08, 0xFF ;; R10C
.byte 0xFF, 0xFF ;; R10D
.byte 0x08, 0xFF ;; R10E
.byte 0x0C, 0xFF ;; R10F
.byte 0x05, 0xFF ;; R110
.byte 0xFF, 0xCB ;; R111
.byte 0x02, 0xFF ;; R112
.byte 0x08, 0xFF ;; R113
.byte 0xFF, 0xFF ;; R114
.byte 0x4D, 0xFF ;; R115
.byte 0x2F, 0xFF ;; R116
.byte 0x05, 0xFF ;; R117
.byte 0x00, 0xFF ;; R118
.byte 0x00, 0xFF ;; R119
.byte 0x29, 0xFF ;; R11A
.byte 0x00, 0xFF ;; R11B
.byte 0xFF, 0xFF ;; R11C
.byte 0xFF, 0xFF ;; R11D
.byte 0xFF, 0xFF ;; R11E
.byte 0xFF, 0xFF ;; R11F
.byte 0xFF, 0xFF ;; R120
.byte 0xFF, 0xFF ;; R121
.byte 0xFF, 0xFF ;; R122
.byte 0xFF, 0xFF ;; R123
.byte 0xFF, 0xFF ;; R124
.byte 0xFF, 0xFF ;; R125
.byte 0xFF, 0xFF ;; R126
.byte 0xFF, 0xFF ;; R127
.byte 0xFF, 0xFF ;; R128
.byte 0xFF, 0xFF ;; R129
.byte 0xFF, 0xFF ;; R12A
.byte 0xFF, 0xFF ;; R12B
.byte 0xFF, 0xFF ;; R12C
.byte 0xFF, 0xFF ;; R12D
.byte 0xFF, 0xFF ;; R12E
.byte 0xFF, 0xFF ;; R12F
.org 0x800001E0 ;; PL0 [Scenario B]
.byte 0x0B, 0x01 ;; R100
.byte 0x41, 0xC0 ;; R101
.byte 0x00, 0xFF ;; R102
.byte 0x00, 0x05 ;; R103
.byte 0x0B, 0x01 ;; R104
.byte 0x00, 0x05 ;; R105
.byte 0xFF, 0xC3 ;; R106
.byte 0x00, 0x05 ;; R107
.byte 0x00, 0xC2 ;; R108
.byte 0x08, 0x07 ;; R109
.byte 0x04, 0xFF ;; R10A
.byte 0x56, 0xC4 ;; R10B
.byte 0x08, 0xFF ;; R10C
.byte 0xFF, 0xFF ;; R10D
.byte 0x08, 0xFF ;; R10E
.byte 0x0C, 0xFF ;; R10F
.byte 0x05, 0xFF ;; R110
.byte 0xFF, 0xCB ;; R111
.byte 0x02, 0xFF ;; R112
.byte 0xFF, 0xCA ;; R113
.byte 0xFF, 0xFF ;; R114
.byte 0x31, 0xFF ;; R115
.byte 0x2F, 0xFF ;; R116
.byte 0x05, 0xFF ;; R117
.byte 0x00, 0xFF ;; R118
.byte 0x00, 0xFF ;; R119
.byte 0x29, 0xFF ;; R11A
.byte 0x00, 0xFF ;; R11B
.byte 0xFF, 0xFF ;; R11C
.byte 0xFF, 0xFF ;; R11D
.byte 0xFF, 0xFF ;; R11E
.byte 0xFF, 0xFF ;; R11F
.byte 0xFF, 0xFF ;; R120
.byte 0xFF, 0xFF ;; R121
.byte 0xFF, 0xFF ;; R122
.byte 0xFF, 0xFF ;; R123
.byte 0xFF, 0xFF ;; R124
.byte 0xFF, 0xFF ;; R125
.byte 0xFF, 0xFF ;; R126
.byte 0xFF, 0xFF ;; R127
.byte 0xFF, 0xFF ;; R128
.byte 0xFF, 0xFF ;; R129
.byte 0xFF, 0xFF ;; R12A
.byte 0xFF, 0xFF ;; R12B
.byte 0xFF, 0xFF ;; R12C
.byte 0xFF, 0xFF ;; R12D
.byte 0xFF, 0xFF ;; R12E
.byte 0xFF, 0xFF ;; R12F
.org 0x80000240 ;; PL1 [Scenario A]
.byte 0x0B, 0x01 ;; R100
.byte 0x41, 0xC0 ;; R101
.byte 0x00, 0xFF ;; R102
.byte 0x00, 0x05 ;; R103
.byte 0x0B, 0x01 ;; R104
.byte 0x00, 0x05 ;; R105
.byte 0xFF, 0xC3 ;; R106
.byte 0x00, 0x05 ;; R107
.byte 0x00, 0xC2 ;; R108
.byte 0x08, 0xC3 ;; R109
.byte 0x04, 0xFF ;; R10A
.byte 0x08, 0xFF ;; R10B
.byte 0x08, 0xFF ;; R10C
.byte 0xFF, 0xFF ;; R10D
.byte 0x4A, 0xC9 ;; R10E
.byte 0x0C, 0xFF ;; R10F
.byte 0x05, 0xFF ;; R110
.byte 0xFF, 0xCB ;; R111
.byte 0x02, 0xFF ;; R112
.byte 0xFF, 0xCA ;; R113
.byte 0xFF, 0xCA ;; R114
.byte 0x31, 0xCC ;; R115
.byte 0x2F, 0xFF ;; R116
.byte 0x05, 0xFF ;; R117
.byte 0x00, 0xFF ;; R118
.byte 0x00, 0xFF ;; R119
.byte 0x29, 0xFF ;; R11A
.byte 0x00, 0xFF ;; R11B
.byte 0xFF, 0xFF ;; R11C
.byte 0xFF, 0xFF ;; R11D
.byte 0xFF, 0xFF ;; R11E
.byte 0xFF, 0xFF ;; R11F
.byte 0xFF, 0xFF ;; R120
.byte 0xFF, 0xFF ;; R121
.byte 0xFF, 0xFF ;; R122
.byte 0xFF, 0xFF ;; R123
.byte 0xFF, 0xFF ;; R124
.byte 0xFF, 0xFF ;; R125
.byte 0xFF, 0xFF ;; R126
.byte 0xFF, 0xFF ;; R127
.byte 0xFF, 0xFF ;; R128
.byte 0xFF, 0xFF ;; R129
.byte 0xFF, 0xFF ;; R12A
.byte 0xFF, 0xFF ;; R12B
.byte 0xFF, 0xFF ;; R12C
.byte 0xFF, 0xFF ;; R12D
.byte 0xFF, 0xFF ;; R12E
.byte 0xFF, 0xFF ;; R12F
.org 0x800002A0 ;; PL1 [Scenario B]
.byte 0x0B, 0x01 ;; R100
.byte 0x41, 0xC0 ;; R101
.byte 0x00, 0xFF ;; R102
.byte 0x00, 0x05 ;; R103
.byte 0x0B, 0x01 ;; R104
.byte 0x00, 0x05 ;; R105
.byte 0xFF, 0xC3 ;; R106
.byte 0x00, 0x05 ;; R107
.byte 0x00, 0xC2 ;; R108
.byte 0x08, 0x87 ;; R109
.byte 0x04, 0xFF ;; R10A
.byte 0x56, 0xC4 ;; R10B
.byte 0x08, 0xFF ;; R10C
.byte 0xFF, 0xFF ;; R10D
.byte 0x4A, 0xC9 ;; R10E
.byte 0x0C, 0xFF ;; R10F
.byte 0x05, 0xFF ;; R110
.byte 0xFF, 0xCB ;; R111
.byte 0x02, 0xFF ;; R112
.byte 0x08, 0xFF ;; R113
.byte 0xFF, 0xCA ;; R114
.byte 0x4D, 0xCC ;; R115
.byte 0x2F, 0xFF ;; R116
.byte 0x05, 0xFF ;; R117
.byte 0x00, 0xFF ;; R118
.byte 0x00, 0xFF ;; R119
.byte 0x29, 0xFF ;; R11A
.byte 0x00, 0xFF ;; R11B
.byte 0xFF, 0xFF ;; R11C
.byte 0xFF, 0xFF ;; R11D
.byte 0xFF, 0xFF ;; R11E
.byte 0xFF, 0xFF ;; R11F
.byte 0xFF, 0xFF ;; R120
.byte 0xFF, 0xFF ;; R121
.byte 0xFF, 0xFF ;; R122
.byte 0xFF, 0xFF ;; R123
.byte 0xFF, 0xFF ;; R124
.byte 0xFF, 0xFF ;; R125
.byte 0xFF, 0xFF ;; R126
.byte 0xFF, 0xFF ;; R127
.byte 0xFF, 0xFF ;; R128
.byte 0xFF, 0xFF ;; R129
.byte 0xFF, 0xFF ;; R12A
.byte 0xFF, 0xFF ;; R12B
.byte 0xFF, 0xFF ;; R12C
.byte 0xFF, 0xFF ;; R12D
.byte 0xFF, 0xFF ;; R12E
.byte 0xFF, 0xFF ;; R12F
.org 0x80000300 ;; 4th Survivor
.byte 0xFF, 0xFF ;; R100
.byte 0xFF, 0xFF ;; R101
.byte 0xFF, 0xFF ;; R102
.byte 0xFF, 0xFF ;; R103
.byte 0xFF, 0xFF ;; R104
.byte 0xFF, 0xFF ;; R105
.byte 0xFF, 0xFF ;; R106
.byte 0xFF, 0xFF ;; R107
.byte 0xFF, 0xFF ;; R108
.byte 0x28, 0xFF ;; R109
.byte 0x28, 0xFF ;; R10A
.byte 0xFF, 0xFF ;; R10B
.byte 0x28, 0xFF ;; R10C
.byte 0xFF, 0xFF ;; R10D
.byte 0xFF, 0xFF ;; R10E
.byte 0x28, 0xFF ;; R10F
.byte 0x28, 0xFF ;; R110
.byte 0xFF, 0xFF ;; R111
.byte 0x28, 0xFF ;; R112
.byte 0x28, 0xFF ;; R113
.byte 0x28, 0xFF ;; R114
.byte 0xFF, 0xFF ;; R115
.byte 0xFF, 0xFF ;; R116
.byte 0xFF, 0xFF ;; R117
.byte 0xFF, 0xFF ;; R118
.byte 0xFF, 0xFF ;; R119
.byte 0xFF, 0xFF ;; R11A
.byte 0xFF, 0xFF ;; R11B
.byte 0x2D, 0xF1 ;; R11C
.byte 0xFF, 0xFF ;; R11D
.byte 0xFF, 0xFF ;; R11E
.byte 0xFF, 0xFF ;; R11F
.byte 0xFF, 0xFF ;; R120
.byte 0xFF, 0xFF ;; R121
.byte 0xFF, 0xFF ;; R122
.byte 0xFF, 0xFF ;; R123
.byte 0xFF, 0xFF ;; R124
.byte 0xFF, 0xFF ;; R125
.byte 0xFF, 0xFF ;; R126
.byte 0xFF, 0xFF ;; R127
.byte 0xFF, 0xFF ;; R128
.byte 0xFF, 0xFF ;; R129
.byte 0xFF, 0xFF ;; R12A
.byte 0xFF, 0xFF ;; R12B
.byte 0xFF, 0xFF ;; R12C
.byte 0xFF, 0xFF ;; R12D
.byte 0xFF, 0xFF ;; R12E
.byte 0xFF, 0xFF ;; R12F
.org 0x80000360 ;; Ex-Battle
.byte 0xFF, 0xFF ;; R100
.byte 0xFF, 0xFF ;; R101
.byte 0xFF, 0xFF ;; R102
.byte 0xFF, 0xFF ;; R103
.byte 0xFF, 0xFF ;; R104
.byte 0x33, 0xFF ;; R105
.byte 0x0C, 0xFF ;; R106
.byte 0x33, 0xFF ;; R107
.byte 0x33, 0xFF ;; R108
.byte 0x33, 0xFF ;; R109
.byte 0x33, 0xFF ;; R10A
.byte 0x33, 0xFF ;; R10B
.byte 0x33, 0xFF ;; R10C
.byte 0x33, 0xFF ;; R10D
.byte 0x33, 0xFF ;; R10E
.byte 0x0C, 0xFF ;; R10F
.byte 0x33, 0xFF ;; R110
.byte 0x33, 0xFF ;; R111
.byte 0x33, 0xFF ;; R112
.byte 0x33, 0xFF ;; R113
.byte 0x33, 0xFF ;; R114
.byte 0x33, 0xFF ;; R115
.byte 0x33, 0xFF ;; R116
.byte 0x33, 0xFF ;; R117
.byte 0xFF, 0xFF ;; R118
.byte 0xFF, 0xFF ;; R119
.byte 0xFF, 0xFF ;; R11A
.byte 0xFF, 0xFF ;; R11B
.byte 0xFF, 0xFF ;; R11C
.byte 0xFF, 0xFF ;; R11D
.byte 0xFF, 0xFF ;; R11E
.byte 0xFF, 0xFF ;; R11F
.byte 0xFF, 0xFF ;; R120
.byte 0xFF, 0xFF ;; R121
.byte 0xFF, 0xFF ;; R122
.byte 0xFF, 0xFF ;; R123
.byte 0xFF, 0xFF ;; R124
.byte 0xFF, 0xFF ;; R125
.byte 0xFF, 0xFF ;; R126
.byte 0xFF, 0xFF ;; R127
.byte 0xFF, 0xFF ;; R128
.byte 0xFF, 0xFF ;; R129
.byte 0xFF, 0xFF ;; R12A
.byte 0xFF, 0xFF ;; R12B
.byte 0xFF, 0xFF ;; R12C
.byte 0xFF, 0xFF ;; R12D
.byte 0xFF, 0xFF ;; R12E
.byte 0xFF, 0xFF ;; R12F
;; XA Table
.org 0x800003C0 ;; PL0
.dh 0x08, 0x49, 0x06 ;;
.dh 0x08, 0x32, 0x17 ;;
.dh 0x02, 0x3B, 0x14 ;;
.dh 0x05, 0x28, 0x1E ;;
.dh 0x06, 0x3B, 0x12 ;;
.dh 0x0A, 0x1E, 0x08 ;;
.dh 0x00, 0x00, 0x50 ;;
.dh 0x03, 0x00, 0x2F ;;
.dh 0x01, 0x47, 0x09 ;;
.dh 0x03, 0x2F, 0x20 ;;
.dh 0x09, 0x16, 0x11 ;;
.dh 0x04, 0x2E, 0x20 ;;
.dh 0x09, 0x27, 0x10 ;;
.dh 0x0A, 0x10, 0x0E ;;
.dh 0x09, 0x37, 0x10 ;;
.dh 0x05, 0x00, 0x28 ;;
.dh 0x07, 0x36, 0x1A ;;
.dh 0x05, 0x46, 0x09 ;;
.dh 0x02, 0x00, 0x3B ;;
.dh 0x08, 0x00, 0x19 ;;
.dh 0x09, 0x00, 0x16 ;;
.dh 0x06, 0x00, 0x1E ;;
.dh 0x0A, 0x00, 0x10 ;;
.dh 0x07, 0x00, 0x1B ;;
.dh 0x04, 0x00, 0x2E ;;
.dh 0x01, 0x00, 0x47 ;;
.dh 0x09, 0x47, 0x09 ;;
.dh 0x06, 0x1E, 0x1D ;;
.dh 0x08, 0x19, 0x19 ;;
.dh 0x07, 0x1B, 0x1B ;;
.org 0x800005E0 ;; PL1 |
MeganGrass/Resident-Evil-2-Starter-Kit | 8,727 | source/assembly/sound/stage2.s |
.org 0x80000180
.fill 0x240, 0xFF
.org 0x800003C0
.fill 0x440, 0x00
;; BGM Table
.org 0x80000180 ;; PL0 [Scenario A]
.byte 0x05, 0xFF ;; R200
.byte 0xFF, 0xFF ;; R201
.byte 0x06, 0xFF ;; R202
.byte 0x07, 0xFF ;; R203
.byte 0x49, 0xC4 ;; R204
.byte 0x07, 0xFF ;; R205
.byte 0x07, 0xC8 ;; R206
.byte 0x07, 0xFF ;; R207
.byte 0x0C, 0xFF ;; R208
.byte 0xFF, 0xFF ;; R209
.byte 0x07, 0xFF ;; R20A
.byte 0x19, 0xFF ;; R20B
.byte 0x07, 0xFF ;; R20C
.byte 0x07, 0xFF ;; R20D
.byte 0xFF, 0xC4 ;; R20E
.byte 0x07, 0xFF ;; R20F
.byte 0xFF, 0xFF ;; R210
.byte 0x03, 0xFF ;; R211
.byte 0x00, 0xFF ;; R212
.byte 0xFF, 0x0D ;; R213
.byte 0x03, 0xFF ;; R214
.byte 0x41, 0xC0 ;; R215
.byte 0xFF, 0xCE ;; R216
.byte 0xFF, 0xFF ;; R217
.byte 0xFF, 0xFF ;; R218
.byte 0x03, 0xFF ;; R219
.byte 0xFF, 0xC3 ;; R21A
.byte 0x08, 0xFF ;; R21B
.byte 0xFF, 0xFF ;; R21C
.byte 0xFF, 0xFF ;; R21D
.byte 0xFF, 0xFF ;; R21E
.byte 0xFF, 0xFF ;; R21F
.byte 0xFF, 0xFF ;; R220
.byte 0xFF, 0xFF ;; R221
.byte 0xFF, 0xFF ;; R222
.byte 0xFF, 0xFF ;; R223
.byte 0xFF, 0xFF ;; R224
.byte 0xFF, 0xFF ;; R225
.byte 0xFF, 0xFF ;; R226
.byte 0xFF, 0xFF ;; R227
.byte 0xFF, 0xFF ;; R228
.byte 0xFF, 0xFF ;; R229
.byte 0xFF, 0xFF ;; R22A
.byte 0xFF, 0xFF ;; R22B
.byte 0xFF, 0xFF ;; R22C
.byte 0xFF, 0xFF ;; R22D
.byte 0xFF, 0xFF ;; R22E
.byte 0xFF, 0xFF ;; R22F
.org 0x800001E0 ;; PL0 [Scenario B]
.byte 0x05, 0xFF ;; R200
.byte 0x07, 0xFF ;; R201
.byte 0x06, 0xFF ;; R202
.byte 0x07, 0xFF ;; R203
.byte 0x07, 0xFF ;; R204
.byte 0x07, 0xFF ;; R205
.byte 0x07, 0xC8 ;; R206
.byte 0x07, 0xFF ;; R207
.byte 0x0C, 0xFF ;; R208
.byte 0xFF, 0xFF ;; R209
.byte 0x07, 0xFF ;; R20A
.byte 0x19, 0xFF ;; R20B
.byte 0x07, 0xFF ;; R20C
.byte 0x5E, 0xFF ;; R20D
.byte 0xFF, 0xC4 ;; R20E
.byte 0x07, 0xFF ;; R20F
.byte 0xFF, 0xFF ;; R210
.byte 0x03, 0xFF ;; R211
.byte 0x00, 0xFF ;; R212
.byte 0xFF, 0x0D ;; R213
.byte 0x03, 0xFF ;; R214
.byte 0x41, 0xC0 ;; R215
.byte 0xFF, 0xCE ;; R216
.byte 0xFF, 0xFF ;; R217
.byte 0xFF, 0xFF ;; R218
.byte 0x03, 0xFF ;; R219
.byte 0xFF, 0xC3 ;; R21A
.byte 0x08, 0xFF ;; R21B
.byte 0xFF, 0xFF ;; R21C
.byte 0xFF, 0xFF ;; R21D
.byte 0xFF, 0xFF ;; R21E
.byte 0xFF, 0xFF ;; R21F
.byte 0xFF, 0xFF ;; R220
.byte 0xFF, 0xFF ;; R221
.byte 0xFF, 0xFF ;; R222
.byte 0xFF, 0xFF ;; R223
.byte 0xFF, 0xFF ;; R224
.byte 0xFF, 0xFF ;; R225
.byte 0xFF, 0xFF ;; R226
.byte 0xFF, 0xFF ;; R227
.byte 0xFF, 0xFF ;; R228
.byte 0xFF, 0xFF ;; R229
.byte 0xFF, 0xFF ;; R22A
.byte 0xFF, 0xFF ;; R22B
.byte 0xFF, 0xFF ;; R22C
.byte 0xFF, 0xFF ;; R22D
.byte 0xFF, 0xFF ;; R22E
.byte 0xFF, 0xFF ;; R22F
.org 0x80000240 ;; PL1 [Scenario A]
.byte 0x05, 0xFF ;; R200
.byte 0xFF, 0xFF ;; R201
.byte 0x06, 0xFF ;; R202
.byte 0x07, 0xFF ;; R203
.byte 0x49, 0xC4 ;; R204
.byte 0x07, 0xFF ;; R205
.byte 0x07, 0xC8 ;; R206
.byte 0x07, 0xFF ;; R207
.byte 0x0C, 0xFF ;; R208
.byte 0xFF, 0xFF ;; R209
.byte 0x07, 0xFF ;; R20A
.byte 0x19, 0xFF ;; R20B
.byte 0x07, 0xFF ;; R20C
.byte 0x07, 0xFF ;; R20D
.byte 0xFF, 0xC4 ;; R20E
.byte 0xFF, 0xFF ;; R20F
.byte 0xFF, 0xFF ;; R210
.byte 0x03, 0xFF ;; R211
.byte 0x00, 0xFF ;; R212
.byte 0xFF, 0x0D ;; R213
.byte 0x03, 0xFF ;; R214
.byte 0x41, 0xC0 ;; R215
.byte 0x03, 0xFF ;; R216
.byte 0xFF, 0xFF ;; R217
.byte 0xFF, 0xFF ;; R218
.byte 0x03, 0xFF ;; R219
.byte 0xFF, 0xC3 ;; R21A
.byte 0xFF, 0xD1 ;; R21B
.byte 0xFF, 0xFF ;; R21C
.byte 0xFF, 0xFF ;; R21D
.byte 0xFF, 0xFF ;; R21E
.byte 0xFF, 0xFF ;; R21F
.byte 0xFF, 0xFF ;; R220
.byte 0xFF, 0xFF ;; R221
.byte 0xFF, 0xFF ;; R222
.byte 0xFF, 0xFF ;; R223
.byte 0xFF, 0xFF ;; R224
.byte 0xFF, 0xFF ;; R225
.byte 0xFF, 0xFF ;; R226
.byte 0xFF, 0xFF ;; R227
.byte 0xFF, 0xFF ;; R228
.byte 0xFF, 0xFF ;; R229
.byte 0xFF, 0xFF ;; R22A
.byte 0xFF, 0xFF ;; R22B
.byte 0xFF, 0xFF ;; R22C
.byte 0xFF, 0xFF ;; R22D
.byte 0xFF, 0xFF ;; R22E
.byte 0xFF, 0xFF ;; R22F
.org 0x800002A0 ;; PL1 [Scenario B]
.byte 0x05, 0xFF ;; R200
.byte 0x07, 0xFF ;; R201
.byte 0x06, 0xFF ;; R202
.byte 0x07, 0xFF ;; R203
.byte 0x07, 0xFF ;; R204
.byte 0x07, 0xFF ;; R205
.byte 0x07, 0xC8 ;; R206
.byte 0x07, 0xFF ;; R207
.byte 0x0C, 0xFF ;; R208
.byte 0xFF, 0xFF ;; R209
.byte 0x07, 0xFF ;; R20A
.byte 0x19, 0xFF ;; R20B
.byte 0x07, 0xFF ;; R20C
.byte 0x5E, 0xFF ;; R20D
.byte 0xFF, 0xC4 ;; R20E
.byte 0xFF, 0xFF ;; R20F
.byte 0xFF, 0xFF ;; R210
.byte 0x03, 0xFF ;; R211
.byte 0x00, 0xFF ;; R212
.byte 0xFF, 0x0D ;; R213
.byte 0x03, 0xFF ;; R214
.byte 0x41, 0xC0 ;; R215
.byte 0x03, 0xFF ;; R216
.byte 0xFF, 0xFF ;; R217
.byte 0xFF, 0xFF ;; R218
.byte 0x03, 0xFF ;; R219
.byte 0xFF, 0xC3 ;; R21A
.byte 0xFF, 0xD1 ;; R21B
.byte 0xFF, 0xFF ;; R21C
.byte 0xFF, 0xFF ;; R21D
.byte 0xFF, 0xFF ;; R21E
.byte 0xFF, 0xFF ;; R21F
.byte 0xFF, 0xFF ;; R220
.byte 0xFF, 0xFF ;; R221
.byte 0xFF, 0xFF ;; R222
.byte 0xFF, 0xFF ;; R223
.byte 0xFF, 0xFF ;; R224
.byte 0xFF, 0xFF ;; R225
.byte 0xFF, 0xFF ;; R226
.byte 0xFF, 0xFF ;; R227
.byte 0xFF, 0xFF ;; R228
.byte 0xFF, 0xFF ;; R229
.byte 0xFF, 0xFF ;; R22A
.byte 0xFF, 0xFF ;; R22B
.byte 0xFF, 0xFF ;; R22C
.byte 0xFF, 0xFF ;; R22D
.byte 0xFF, 0xFF ;; R22E
.byte 0xFF, 0xFF ;; R22F
.org 0x80000300 ;; 4th Survivor
.byte 0x05, 0xFF ;; R200
.byte 0x28, 0xFF ;; R201
.byte 0xFF, 0xFF ;; R202
.byte 0xFF, 0xFF ;; R203
.byte 0x28, 0xFF ;; R204
.byte 0x28, 0xFF ;; R205
.byte 0xFF, 0xFF ;; R206
.byte 0x28, 0xFF ;; R207
.byte 0xFF, 0xFF ;; R208
.byte 0xFF, 0xFF ;; R209
.byte 0x27, 0xFF ;; R20A
.byte 0x27, 0xFF ;; R20B
.byte 0xFF, 0xFF ;; R20C
.byte 0xFF, 0xFF ;; R20D
.byte 0xFF, 0xFF ;; R20E
.byte 0x27, 0xFF ;; R20F
.byte 0xFF, 0xFF ;; R210
.byte 0x27, 0xFF ;; R211
.byte 0xFF, 0xFF ;; R212
.byte 0xFF, 0xFF ;; R213
.byte 0xFF, 0xFF ;; R214
.byte 0xFF, 0xFF ;; R215
.byte 0x27, 0xFF ;; R216
.byte 0xFF, 0xFF ;; R217
.byte 0xFF, 0xFF ;; R218
.byte 0x27, 0xFF ;; R219
.byte 0x27, 0xFF ;; R21A
.byte 0xFF, 0xFF ;; R21B
.byte 0xFF, 0xFF ;; R21C
.byte 0xFF, 0xFF ;; R21D
.byte 0xFF, 0xFF ;; R21E
.byte 0xFF, 0xFF ;; R21F
.byte 0xFF, 0xFF ;; R220
.byte 0xFF, 0xFF ;; R221
.byte 0xFF, 0xFF ;; R222
.byte 0xFF, 0xFF ;; R223
.byte 0xFF, 0xFF ;; R224
.byte 0xFF, 0xFF ;; R225
.byte 0xFF, 0xFF ;; R226
.byte 0xFF, 0xFF ;; R227
.byte 0xFF, 0xFF ;; R228
.byte 0xFF, 0xFF ;; R229
.byte 0xFF, 0xFF ;; R22A
.byte 0xFF, 0xFF ;; R22B
.byte 0xFF, 0xFF ;; R22C
.byte 0xFF, 0xFF ;; R22D
.byte 0xFF, 0xFF ;; R22E
.byte 0xFF, 0xFF ;; R22F
.org 0x80000360 ;; Ex-Battle
.byte 0x33, 0xFF ;; R200
.byte 0x33, 0xFF ;; R201
.byte 0x33, 0xFF ;; R202
.byte 0x33, 0xFF ;; R203
.byte 0x33, 0xFF ;; R204
.byte 0x33, 0xFF ;; R205
.byte 0x33, 0xFF ;; R206
.byte 0x33, 0xFF ;; R207
.byte 0x0C, 0xFF ;; R208
.byte 0x33, 0xFF ;; R209
.byte 0x33, 0xFF ;; R20A
.byte 0x33, 0xFF ;; R20B
.byte 0x33, 0xFF ;; R20C
.byte 0x33, 0xFF ;; R20D
.byte 0x33, 0xFF ;; R20E
.byte 0x33, 0xFF ;; R20F
.byte 0x33, 0xFF ;; R210
.byte 0x33, 0xFF ;; R211
.byte 0x33, 0xFF ;; R212
.byte 0x33, 0xFF ;; R213
.byte 0x33, 0xFF ;; R214
.byte 0x33, 0xFF ;; R215
.byte 0x33, 0xFF ;; R216
.byte 0xFF, 0xFF ;; R217
.byte 0xFF, 0xFF ;; R218
.byte 0x33, 0xFF ;; R219
.byte 0x33, 0xFF ;; R21A
.byte 0x33, 0xFF ;; R21B
.byte 0xFF, 0xFF ;; R21C
.byte 0xFF, 0xFF ;; R21D
.byte 0xFF, 0xFF ;; R21E
.byte 0xFF, 0xFF ;; R21F
.byte 0xFF, 0xFF ;; R220
.byte 0xFF, 0xFF ;; R221
.byte 0xFF, 0xFF ;; R222
.byte 0xFF, 0xFF ;; R223
.byte 0xFF, 0xFF ;; R224
.byte 0xFF, 0xFF ;; R225
.byte 0xFF, 0xFF ;; R226
.byte 0xFF, 0xFF ;; R227
.byte 0xFF, 0xFF ;; R228
.byte 0xFF, 0xFF ;; R229
.byte 0xFF, 0xFF ;; R22A
.byte 0xFF, 0xFF ;; R22B
.byte 0xFF, 0xFF ;; R22C
.byte 0xFF, 0xFF ;; R22D
.byte 0xFF, 0xFF ;; R22E
.byte 0xFF, 0xFF ;; R22F
;; XA Table
.org 0x800003C0 ;; PL0
.dh 0x02, 0x4D, 0x20 ;;
.dh 0x04, 0x62, 0x0D ;;
.dh 0x06, 0x3F, 0x16 ;;
.dh 0x06, 0x55, 0x13 ;;
.dh 0x00, 0x00, 0x70 ;;
.dh 0x01, 0x6E, 0x01 ;;
.dh 0x0A, 0x2F, 0x0B ;;
.dh 0x01, 0x00, 0x6B ;;
.dh 0x04, 0x00, 0x4A ;;
.dh 0x08, 0x36, 0x35 ;;
.dh 0x06, 0x00, 0x3F ;;
.dh 0x0A, 0x3A, 0x0B ;;
.dh 0x09, 0x34, 0x33 ;;
.dh 0x05, 0x00, 0x44 ;;
.dh 0x01, 0x6B, 0x03 ;;
.dh 0x03, 0x66, 0x0A ;;
.dh 0x06, 0x68, 0x08 ;;
.dh 0x03, 0x4C, 0x1A ;;
.dh 0x07, 0x3E, 0x13 ;;
.dh 0x08, 0x00, 0x36 ;;
.dh 0x07, 0x51, 0x11 ;;
.dh 0x0A, 0x20, 0x0F ;;
.dh 0x05, 0x5B, 0x14 ;;
.dh 0x07, 0x00, 0x3E ;;
.dh 0x02, 0x00, 0x4D ;;
.dh 0x09, 0x00, 0x34 ;;
.dh 0x0A, 0x00, 0x10 ;;
.dh 0x04, 0x4A, 0x18 ;;
.dh 0x05, 0x44, 0x17 ;;
.dh 0x03, 0x00, 0x4C ;;
.dh 0x07, 0x62, 0x0C ;;
.dh 0x0A, 0x10, 0x10 ;;
.dh 0x0A, 0x45, 0x0A ;;
.org 0x800005E0 ;; PL1 |
MeganGrass/Resident-Evil-2-Starter-Kit | 9,741 | source/assembly/sound/stage3.s |
.org 0x80000180
.fill 0x240, 0xFF
.org 0x800003C0
.fill 0x440, 0x00
;; BGM Table
.org 0x80000180 ;; PL0 [Scenario A]
.byte 0xFF, 0xFF ;; R300
.byte 0xFF, 0xC9 ;; R301
.byte 0x0F, 0xFF ;; R302
.byte 0x55, 0xFF ;; R303
.byte 0x0F, 0xC9 ;; R304
.byte 0x2E, 0xFF ;; R305
.byte 0x14, 0xFF ;; R306
.byte 0xFF, 0x14 ;; R307
.byte 0x04, 0xFF ;; R308
.byte 0xFF, 0x2E ;; R309
.byte 0x0F, 0xFF ;; R30A
.byte 0x0F, 0xFF ;; R30B
.byte 0x0C, 0xFF ;; R30C
.byte 0x0C, 0xFF ;; R30D
.byte 0xFF, 0xFF ;; R30E
.byte 0xFF, 0xFF ;; R30F
.byte 0xFF, 0xFF ;; R310
.byte 0xFF, 0xFF ;; R311
.byte 0xFF, 0xFF ;; R312
.byte 0xFF, 0xFF ;; R313
.byte 0xFF, 0xFF ;; R314
.byte 0xFF, 0xFF ;; R315
.byte 0xFF, 0xFF ;; R316
.byte 0xFF, 0xFF ;; R317
.byte 0xFF, 0xFF ;; R318
.byte 0xFF, 0xFF ;; R319
.byte 0xFF, 0xFF ;; R31A
.byte 0xFF, 0xFF ;; R31B
.byte 0xFF, 0xFF ;; R31C
.byte 0xFF, 0xFF ;; R31D
.byte 0xFF, 0xFF ;; R31E
.byte 0xFF, 0xFF ;; R31F
.byte 0xFF, 0xFF ;; R320
.byte 0xFF, 0xFF ;; R321
.byte 0xFF, 0xFF ;; R322
.byte 0xFF, 0xFF ;; R323
.byte 0xFF, 0xFF ;; R324
.byte 0xFF, 0xFF ;; R325
.byte 0xFF, 0xFF ;; R326
.byte 0xFF, 0xFF ;; R327
.byte 0xFF, 0xFF ;; R328
.byte 0xFF, 0xFF ;; R329
.byte 0xFF, 0xFF ;; R32A
.byte 0xFF, 0xFF ;; R32B
.byte 0xFF, 0xFF ;; R32C
.byte 0xFF, 0xFF ;; R32D
.byte 0xFF, 0xFF ;; R32E
.byte 0xFF, 0xFF ;; R32F
.org 0x800001E0 ;; PL0 [Scenario B]
.byte 0xFF, 0xFF ;; R300
.byte 0xFF, 0xC9 ;; R301
.byte 0x0F, 0xFF ;; R302
.byte 0x50, 0xFF ;; R303
.byte 0x0F, 0xC9 ;; R304
.byte 0x2E, 0xFF ;; R305
.byte 0x14, 0xFF ;; R306
.byte 0xFF, 0x14 ;; R307
.byte 0x04, 0xFF ;; R308
.byte 0xFF, 0x2E ;; R309
.byte 0x0F, 0xFF ;; R30A
.byte 0x0F, 0xC9 ;; R30B
.byte 0x0C, 0xFF ;; R30C
.byte 0x0C, 0xFF ;; R30D
.byte 0xFF, 0xFF ;; R30E
.byte 0xFF, 0xFF ;; R30F
.byte 0xFF, 0xFF ;; R310
.byte 0xFF, 0xFF ;; R311
.byte 0xFF, 0xFF ;; R312
.byte 0xFF, 0xFF ;; R313
.byte 0xFF, 0xFF ;; R314
.byte 0xFF, 0xFF ;; R315
.byte 0xFF, 0xFF ;; R316
.byte 0xFF, 0xFF ;; R317
.byte 0xFF, 0xFF ;; R318
.byte 0xFF, 0xFF ;; R319
.byte 0xFF, 0xFF ;; R31A
.byte 0xFF, 0xFF ;; R31B
.byte 0xFF, 0xFF ;; R31C
.byte 0xFF, 0xFF ;; R31D
.byte 0xFF, 0xFF ;; R31E
.byte 0xFF, 0xFF ;; R31F
.byte 0xFF, 0xFF ;; R320
.byte 0xFF, 0xFF ;; R321
.byte 0xFF, 0xFF ;; R322
.byte 0xFF, 0xFF ;; R323
.byte 0xFF, 0xFF ;; R324
.byte 0xFF, 0xFF ;; R325
.byte 0xFF, 0xFF ;; R326
.byte 0xFF, 0xFF ;; R327
.byte 0xFF, 0xFF ;; R328
.byte 0xFF, 0xFF ;; R329
.byte 0xFF, 0xFF ;; R32A
.byte 0xFF, 0xFF ;; R32B
.byte 0xFF, 0xFF ;; R32C
.byte 0xFF, 0xFF ;; R32D
.byte 0xFF, 0xFF ;; R32E
.byte 0xFF, 0xFF ;; R32F
.org 0x80000240 ;; PL1 [Scenario A]
.byte 0xFF, 0xD3 ;; R300
.byte 0xFF, 0xFF ;; R301
.byte 0x0F, 0xFF ;; R302
.byte 0xFF, 0xFF ;; R303
.byte 0x0F, 0xFF ;; R304
.byte 0x2E, 0xFF ;; R305
.byte 0x14, 0xFF ;; R306
.byte 0xFF, 0x14 ;; R307
.byte 0x04, 0xD2 ;; R308
.byte 0x55, 0x2E ;; R309
.byte 0x0F, 0xD0 ;; R30A
.byte 0x0F, 0xFF ;; R30B
.byte 0x0C, 0xFF ;; R30C
.byte 0x0C, 0xFF ;; R30D
.byte 0xFF, 0xFF ;; R30E
.byte 0xFF, 0xFF ;; R30F
.byte 0xFF, 0xFF ;; R310
.byte 0xFF, 0xFF ;; R311
.byte 0xFF, 0xFF ;; R312
.byte 0xFF, 0xFF ;; R313
.byte 0xFF, 0xFF ;; R314
.byte 0xFF, 0xFF ;; R315
.byte 0xFF, 0xFF ;; R316
.byte 0xFF, 0xFF ;; R317
.byte 0xFF, 0xFF ;; R318
.byte 0xFF, 0xFF ;; R319
.byte 0xFF, 0xFF ;; R31A
.byte 0xFF, 0xFF ;; R31B
.byte 0xFF, 0xFF ;; R31C
.byte 0xFF, 0xFF ;; R31D
.byte 0xFF, 0xFF ;; R31E
.byte 0xFF, 0xFF ;; R31F
.byte 0xFF, 0xFF ;; R320
.byte 0xFF, 0xFF ;; R321
.byte 0xFF, 0xFF ;; R322
.byte 0xFF, 0xFF ;; R323
.byte 0xFF, 0xFF ;; R324
.byte 0xFF, 0xFF ;; R325
.byte 0xFF, 0xFF ;; R326
.byte 0xFF, 0xFF ;; R327
.byte 0xFF, 0xFF ;; R328
.byte 0xFF, 0xFF ;; R329
.byte 0xFF, 0xFF ;; R32A
.byte 0xFF, 0xFF ;; R32B
.byte 0xFF, 0xFF ;; R32C
.byte 0xFF, 0xFF ;; R32D
.byte 0xFF, 0xFF ;; R32E
.byte 0xFF, 0xFF ;; R32F
.org 0x800002A0 ;; PL1 [Scenario B]
.byte 0x61, 0xF2 ;; R300
.byte 0xFF, 0xFF ;; R301
.byte 0x0F, 0xFF ;; R302
.byte 0xFF, 0xFF ;; R303
.byte 0x0F, 0xFF ;; R304
.byte 0x2E, 0xFF ;; R305
.byte 0x14, 0xFF ;; R306
.byte 0xFF, 0x14 ;; R307
.byte 0x04, 0xFF ;; R308
.byte 0x50, 0x2E ;; R309
.byte 0x0F, 0xD0 ;; R30A
.byte 0x0F, 0xFF ;; R30B
.byte 0x0C, 0xFF ;; R30C
.byte 0x0C, 0xFF ;; R30D
.byte 0xFF, 0xFF ;; R30E
.byte 0xFF, 0xFF ;; R30F
.byte 0xFF, 0xFF ;; R310
.byte 0xFF, 0xFF ;; R311
.byte 0xFF, 0xFF ;; R312
.byte 0xFF, 0xFF ;; R313
.byte 0xFF, 0xFF ;; R314
.byte 0xFF, 0xFF ;; R315
.byte 0xFF, 0xFF ;; R316
.byte 0xFF, 0xFF ;; R317
.byte 0xFF, 0xFF ;; R318
.byte 0xFF, 0xFF ;; R319
.byte 0xFF, 0xFF ;; R31A
.byte 0xFF, 0xFF ;; R31B
.byte 0xFF, 0xFF ;; R31C
.byte 0xFF, 0xFF ;; R31D
.byte 0xFF, 0xFF ;; R31E
.byte 0xFF, 0xFF ;; R31F
.byte 0xFF, 0xFF ;; R320
.byte 0xFF, 0xFF ;; R321
.byte 0xFF, 0xFF ;; R322
.byte 0xFF, 0xFF ;; R323
.byte 0xFF, 0xFF ;; R324
.byte 0xFF, 0xFF ;; R325
.byte 0xFF, 0xFF ;; R326
.byte 0xFF, 0xFF ;; R327
.byte 0xFF, 0xFF ;; R328
.byte 0xFF, 0xFF ;; R329
.byte 0xFF, 0xFF ;; R32A
.byte 0xFF, 0xFF ;; R32B
.byte 0xFF, 0xFF ;; R32C
.byte 0xFF, 0xFF ;; R32D
.byte 0xFF, 0xFF ;; R32E
.byte 0xFF, 0xFF ;; R32F
.org 0x80000300 ;; 4th Survivor
.byte 0xFF, 0xFF ;; R300
.byte 0xFF, 0xFF ;; R301
.byte 0x27, 0xFF ;; R302
.byte 0x27, 0xFF ;; R303
.byte 0x67, 0xFF ;; R304
.byte 0xFF, 0xFF ;; R305
.byte 0xFF, 0xFF ;; R306
.byte 0xFF, 0xFF ;; R307
.byte 0xFF, 0xFF ;; R308
.byte 0xFF, 0xFF ;; R309
.byte 0xFF, 0xFF ;; R30A
.byte 0x27, 0xFF ;; R30B
.byte 0xFF, 0xFF ;; R30C
.byte 0xFF, 0xFF ;; R30D
.byte 0xFF, 0xFF ;; R30E
.byte 0xFF, 0xFF ;; R30F
.byte 0xFF, 0xFF ;; R310
.byte 0xFF, 0xFF ;; R311
.byte 0xFF, 0xFF ;; R312
.byte 0xFF, 0xFF ;; R313
.byte 0xFF, 0xFF ;; R314
.byte 0xFF, 0xFF ;; R315
.byte 0xFF, 0xFF ;; R316
.byte 0xFF, 0xFF ;; R317
.byte 0xFF, 0xFF ;; R318
.byte 0xFF, 0xFF ;; R319
.byte 0xFF, 0xFF ;; R31A
.byte 0xFF, 0xFF ;; R31B
.byte 0xFF, 0xFF ;; R31C
.byte 0xFF, 0xFF ;; R31D
.byte 0xFF, 0xFF ;; R31E
.byte 0xFF, 0xFF ;; R31F
.byte 0xFF, 0xFF ;; R320
.byte 0xFF, 0xFF ;; R321
.byte 0xFF, 0xFF ;; R322
.byte 0xFF, 0xFF ;; R323
.byte 0xFF, 0xFF ;; R324
.byte 0xFF, 0xFF ;; R325
.byte 0xFF, 0xFF ;; R326
.byte 0xFF, 0xFF ;; R327
.byte 0xFF, 0xFF ;; R328
.byte 0xFF, 0xFF ;; R329
.byte 0xFF, 0xFF ;; R32A
.byte 0xFF, 0xFF ;; R32B
.byte 0xFF, 0xFF ;; R32C
.byte 0xFF, 0xFF ;; R32D
.byte 0xFF, 0xFF ;; R32E
.byte 0xFF, 0xFF ;; R32F
.org 0x80000360 ;; Ex-Battle
.byte 0x33, 0xFF ;; R300
.byte 0x33, 0xFF ;; R301
.byte 0x33, 0xFF ;; R302
.byte 0x33, 0xFF ;; R303
.byte 0x33, 0xFF ;; R304
.byte 0xFF, 0xFF ;; R305
.byte 0xFF, 0xFF ;; R306
.byte 0x33, 0xFF ;; R307
.byte 0x33, 0xFF ;; R308
.byte 0x33, 0xFF ;; R309
.byte 0x33, 0xFF ;; R30A
.byte 0x33, 0xFF ;; R30B
.byte 0x0C, 0xFF ;; R30C
.byte 0x0C, 0xFF ;; R30D
.byte 0xFF, 0xFF ;; R30E
.byte 0xFF, 0xFF ;; R30F
.byte 0xFF, 0xFF ;; R310
.byte 0xFF, 0xFF ;; R311
.byte 0xFF, 0xFF ;; R312
.byte 0xFF, 0xFF ;; R313
.byte 0xFF, 0xFF ;; R314
.byte 0xFF, 0xFF ;; R315
.byte 0xFF, 0xFF ;; R316
.byte 0xFF, 0xFF ;; R317
.byte 0xFF, 0xFF ;; R318
.byte 0xFF, 0xFF ;; R319
.byte 0xFF, 0xFF ;; R31A
.byte 0xFF, 0xFF ;; R31B
.byte 0xFF, 0xFF ;; R31C
.byte 0xFF, 0xFF ;; R31D
.byte 0xFF, 0xFF ;; R31E
.byte 0xFF, 0xFF ;; R31F
.byte 0xFF, 0xFF ;; R320
.byte 0xFF, 0xFF ;; R321
.byte 0xFF, 0xFF ;; R322
.byte 0xFF, 0xFF ;; R323
.byte 0xFF, 0xFF ;; R324
.byte 0xFF, 0xFF ;; R325
.byte 0xFF, 0xFF ;; R326
.byte 0xFF, 0xFF ;; R327
.byte 0xFF, 0xFF ;; R328
.byte 0xFF, 0xFF ;; R329
.byte 0xFF, 0xFF ;; R32A
.byte 0xFF, 0xFF ;; R32B
.byte 0xFF, 0xFF ;; R32C
.byte 0xFF, 0xFF ;; R32D
.byte 0xFF, 0xFF ;; R32E
.byte 0xFF, 0xFF ;; R32F
;; XA Table
.org 0x800003C0 ;; PL0
.dh 0x06, 0x38, 0x35 ;;
.dh 0x04, 0x8C, 0x1C ;;
.dh 0x0F, 0x00, 0x12 ;;
.dh 0x03, 0x53, 0x52 ;;
.dh 0x0E, 0x81, 0x13 ;;
.dh 0x0F, 0x24, 0x11 ;;
.dh 0x01, 0x00, 0x60 ;;
.dh 0x0D, 0x8B, 0x18 ;;
.dh 0x09, 0x57, 0x29 ;;
.dh 0x07, 0x00, 0x34 ;;
.dh 0x05, 0x76, 0x33 ;;
.dh 0x0C, 0x42, 0x20 ;;
.dh 0x0F, 0x62, 0x0D ;;
.dh 0x0B, 0x25, 0x24 ;;
.dh 0x0C, 0x81, 0x1E ;;
.dh 0x09, 0x00, 0x2C ;;
.dh 0x0F, 0x6F, 0x0D ;;
.dh 0x0B, 0x6B, 0x21 ;;
.dh 0x0B, 0x49, 0x22 ;;
.dh 0x03, 0x00, 0x53 ;;
.dh 0x0E, 0x17, 0x16 ;;
.dh 0x0F, 0x88, 0x0B ;;
.dh 0x05, 0x00, 0x3C ;;
.dh 0x0F, 0x93, 0x0B ;;
.dh 0x02, 0x00, 0x54 ;;
.dh 0x01, 0x60, 0x46 ;;
.dh 0x07, 0x9A, 0x0F ;;
.dh 0x05, 0x3C, 0x3A ;;
.dh 0x0E, 0x94, 0x13 ;;
.dh 0x08, 0x92, 0x17 ;;
.dh 0x07, 0x34, 0x33 ;;
.dh 0x0D, 0x57, 0x1A ;;
.dh 0x0E, 0x6D, 0x14 ;;
.dh 0x0A, 0x99, 0x0F ;;
.dh 0x0A, 0x4F, 0x25 ;;
.dh 0x0F, 0x12, 0x12 ;;
.dh 0x0A, 0x74, 0x25 ;;
.dh 0x0C, 0x00, 0x21 ;;
.dh 0x09, 0x80, 0x29 ;;
.dh 0x0F, 0x35, 0x0F ;;
.dh 0x0A, 0x28, 0x27 ;;
.dh 0x0F, 0x44, 0x0F ;;
.dh 0x0C, 0x62, 0x1F ;;
.dh 0x0B, 0x00, 0x25 ;;
.dh 0x06, 0x6D, 0x35 ;;
.dh 0x00, 0x68, 0x3D ;;
.dh 0x00, 0x00, 0x68 ;;
.dh 0x02, 0x54, 0x54 ;;
.dh 0x04, 0x00, 0x4F ;;
.dh 0x06, 0xA2, 0x06 ;;
.dh 0x08, 0x00, 0x31 ;;
.dh 0x0B, 0x8C, 0x1B ;;
.dh 0x09, 0x2C, 0x2B ;;
.dh 0x08, 0x62, 0x30 ;;
.dh 0x0C, 0x21, 0x21 ;;
.dh 0x0A, 0x00, 0x28 ;;
.dh 0x0E, 0x00, 0x17 ;;
.dh 0x0D, 0x3C, 0x1B ;;
.dh 0x0F, 0x7C, 0x0C ;;
.dh 0x08, 0x31, 0x31 ;;
.dh 0x0F, 0x53, 0x0F ;;
.dh 0x0D, 0x00, 0x1E ;;
.dh 0x0E, 0x2D, 0x16 ;;
.dh 0x07, 0x67, 0x33 ;;
.dh 0x0E, 0x43, 0x15 ;;
.dh 0x0D, 0x71, 0x1A ;;
.dh 0x0C, 0x9F, 0x0A ;;
.dh 0x0E, 0x58, 0x15 ;;
.dh 0x04, 0x4F, 0x3D ;;
.dh 0x0D, 0x1E, 0x1E ;;
.dh 0x06, 0x00, 0x38 ;;
.dh 0x0D, 0xA3, 0x06 ;;
.org 0x800005E0 ;; PL1 |
PLSysSec/tock-veri-asm | 2,464 | dis_riscv.s | 00000000 <_start_trap>:
0: 34041473 .insn 4, 0x34041473
4: 00040863 beqz s0,14 <.Lpcrel_hi0>
8: 00942023 sw s1,0(s0)
c: 00442483 lw s1,4(s0)
10: 00048067 jr s1
00000014 <.Lpcrel_hi0>:
14: 00000417 auipc s0,0x0
18: 00040413 mv s0,s0
1c: 00246663 bltu s0,sp,28 <.Lpcrel_hi1+0x8>
00000020 <.Lpcrel_hi1>:
20: 00000117 auipc sp,0x0
24: 00010113 mv sp,sp
28: 34001473 .insn 4, 0x34001473
2c: fc010113 add sp,sp,-64 # ffffffe0 <.Lpcrel_hi1+0xffffffc0>
30: 00112023 sw ra,0(sp)
34: 00512223 sw t0,4(sp)
38: 00612423 sw t1,8(sp)
3c: 00712623 sw t2,12(sp)
40: 01c12823 sw t3,16(sp)
44: 01d12a23 sw t4,20(sp)
48: 01e12c23 sw t5,24(sp)
4c: 01f12e23 sw t6,28(sp)
50: 02a12023 sw a0,32(sp)
54: 02b12223 sw a1,36(sp)
58: 02c12423 sw a2,40(sp)
5c: 02d12623 sw a3,44(sp)
60: 02e12823 sw a4,48(sp)
64: 02f12a23 sw a5,52(sp)
68: 03012c23 sw a6,56(sp)
6c: 03112e23 sw a7,60(sp)
70: 000000ef jal 70 <.Lpcrel_hi1+0x50>
74: 00012083 lw ra,0(sp)
78: 00412283 lw t0,4(sp)
7c: 00812303 lw t1,8(sp)
80: 00c12383 lw t2,12(sp)
84: 01012e03 lw t3,16(sp)
88: 01412e83 lw t4,20(sp)
8c: 01812f03 lw t5,24(sp)
90: 01c12f83 lw t6,28(sp)
94: 02012503 lw a0,32(sp)
98: 02412583 lw a1,36(sp)
9c: 02812603 lw a2,40(sp)
a0: 02c12683 lw a3,44(sp)
a4: 03012703 lw a4,48(sp)
a8: 03412783 lw a5,52(sp)
ac: 03812803 lw a6,56(sp)
b0: 03c12883 lw a7,60(sp)
b4: 04010113 add sp,sp,64
b8: 30200073 mret
|
PLSysSec/tock-veri-asm | 1,963 | dis_arm6.s | 0: 4815 ldr r0, [pc, #84] @ (58 <generic_isr+0x58>)
2: 4586 cmp lr, r0
4: d110 bne.n 28 <generic_isr+0x28>
6: 4669 mov r1, sp
8: 6849 ldr r1, [r1, #4]
a: 610c str r4, [r1, #16]
c: 614d str r5, [r1, #20]
e: 618e str r6, [r1, #24]
10: 61cf str r7, [r1, #28]
12: b4f0 push {r4, r5, r6, r7}
14: 4644 mov r4, r8
16: 464d mov r5, r9
18: 4656 mov r6, sl
1a: 465f mov r7, fp
1c: 600c str r4, [r1, #0]
1e: 604d str r5, [r1, #4]
20: 608e str r6, [r1, #8]
22: 60cf str r7, [r1, #12]
24: bcf0 pop {r4, r5, r6, r7}
26: 480b ldr r0, [pc, #44] @ (54 <generic_isr+0x54>)
28: f3ef 8005 mrs r0, IPSR
2c: 21ff movs r1, #255 @ 0xff
2e: 4008 ands r0, r1
30: 3810 subs r0, #16
32: 4a07 ldr r2, [pc, #28] @ (50 <generic_isr+0x50>)
34: 0943 lsrs r3, r0, #5
36: 009b lsls r3, r3, #2
38: 189b adds r3, r3, r2
3a: 221f movs r2, #31
3c: 4010 ands r0, r2
3e: 3a1e subs r2, #30
40: 4082 lsls r2, r0
42: 601a str r2, [r3, #0]
44: 3320 adds r3, #32
46: 601a str r2, [r3, #0]
48: 4770 bx lr
4a: 46c0 nop @ (mov r8, r8)
4c: 46c0 nop @ (mov r8, r8)
4e: 46c0 nop @ (mov r8, r8)
50: e000e180 .word 0xe000e180
54: fffffff9 .word 0xfffffff9
58: fffffffd .word 0xfffffffd
|
Project-Gamblitz/Project-Gamblitz-Starlight | 8,068 | include/libnx/nx/source/kernel/svc.s | .macro SVC_BEGIN name
.section .text.\name, "ax", %progbits
.global \name
.type \name, %function
.align 2
.cfi_startproc
\name:
.endm
.macro SVC_END
.cfi_endproc
.endm
SVC_BEGIN svcSetHeapSize
str x0, [sp, #-16]!
svc 0x1
ldr x2, [sp], #16
str x1, [x2]
ret
SVC_END
SVC_BEGIN svcSetMemoryPermission
svc 0x2
ret
SVC_END
SVC_BEGIN svcSetMemoryAttribute
svc 0x3
ret
SVC_END
SVC_BEGIN svcMapMemory
svc 0x4
ret
SVC_END
SVC_BEGIN svcUnmapMemory
svc 0x5
ret
SVC_END
SVC_BEGIN svcQueryMemory
str x1, [sp, #-16]!
svc 0x6
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcExitProcess
svc 0x7
ret
SVC_END
SVC_BEGIN svcCreateThread
str x0, [sp, #-16]!
svc 0x8
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcStartThread
svc 0x9
ret
SVC_END
SVC_BEGIN svcExitThread
svc 0xA
ret
SVC_END
SVC_BEGIN svcSleepThread
svc 0xB
ret
SVC_END
SVC_BEGIN svcGetThreadPriority
str x0, [sp, #-16]!
svc 0xC
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcSetThreadPriority
svc 0xD
ret
SVC_END
SVC_BEGIN svcGetThreadCoreMask
stp x0, x1, [sp, #-16]!
svc 0xE
ldp x3, x4, [sp], #16
str w1, [x3]
str w2, [x4]
ret
SVC_END
SVC_BEGIN svcSetThreadCoreMask
svc 0xF
ret
SVC_END
SVC_BEGIN svcGetCurrentProcessorNumber
svc 0x10
ret
SVC_END
SVC_BEGIN svcSignalEvent
svc 0x11
ret
SVC_END
SVC_BEGIN svcClearEvent
svc 0x12
ret
SVC_END
SVC_BEGIN svcMapSharedMemory
svc 0x13
ret
SVC_END
SVC_BEGIN svcUnmapSharedMemory
svc 0x14
ret
SVC_END
SVC_BEGIN svcCreateTransferMemory
str x0, [sp, #-16]!
svc 0x15
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcCloseHandle
svc 0x16
ret
SVC_END
SVC_BEGIN svcResetSignal
svc 0x17
ret
SVC_END
SVC_BEGIN svcWaitSynchronization
str x0, [sp, #-16]!
svc 0x18
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcCancelSynchronization
svc 0x19
ret
SVC_END
SVC_BEGIN svcArbitrateLock
svc 0x1A
ret
SVC_END
SVC_BEGIN svcArbitrateUnlock
svc 0x1B
ret
SVC_END
SVC_BEGIN svcWaitProcessWideKeyAtomic
svc 0x1C
ret
SVC_END
SVC_BEGIN svcSignalProcessWideKey
svc 0x1D
ret
SVC_END
SVC_BEGIN svcGetSystemTick
svc 0x1E
ret
SVC_END
SVC_BEGIN svcConnectToNamedPort
str x0, [sp, #-16]!
svc 0x1F
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcSendSyncRequest
svc 0x21
ret
SVC_END
SVC_BEGIN svcSendSyncRequestWithUserBuffer
svc 0x22
ret
SVC_END
SVC_BEGIN svcSendAsyncRequestWithUserBuffer
str x0, [sp, #-16]!
svc 0x23
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcGetProcessId
str x0, [sp, #-16]!
svc 0x24
ldr x2, [sp], #16
str x1, [x2]
ret
SVC_END
SVC_BEGIN svcGetThreadId
str x0, [sp, #-16]!
svc 0x25
ldr x2, [sp], #16
str x1, [x2]
ret
SVC_END
SVC_BEGIN svcBreak
svc 0x26
ret
SVC_END
SVC_BEGIN svcOutputDebugString
svc 0x27
ret
SVC_END
SVC_BEGIN svcReturnFromException
svc 0x28
ret
SVC_END
SVC_BEGIN svcGetInfo
str x0, [sp, #-16]!
svc 0x29
ldr x2, [sp], #16
str x1, [x2]
ret
SVC_END
SVC_BEGIN svcMapPhysicalMemory
svc 0x2C
ret
SVC_END
SVC_BEGIN svcUnmapPhysicalMemory
svc 0x2D
ret
SVC_END
SVC_BEGIN svcGetResourceLimitLimitValue
str x0, [sp, #-16]!
svc 0x30
ldr x2, [sp], #16
str x1, [x2]
ret
SVC_END
SVC_BEGIN svcGetResourceLimitCurrentValue
str x0, [sp, #-16]!
svc 0x31
ldr x2, [sp], #16
str x1, [x2]
ret
SVC_END
SVC_BEGIN svcSetThreadActivity
svc 0x32
ret
SVC_END
SVC_BEGIN svcGetThreadContext3
svc 0x33
ret
SVC_END
SVC_BEGIN svcCreateSession
stp x0, x1, [sp, #-16]!
svc 0x40
ldp x3, x4, [sp], #16
str w1, [x3]
str w2, [x4]
ret
SVC_END
SVC_BEGIN svcAcceptSession
str x0, [sp, #-16]!
svc 0x41
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcReplyAndReceive
str x0, [sp, #-16]!
svc 0x43
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcReplyAndReceiveWithUserBuffer
str x0, [sp, #-16]!
svc 0x44
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcCreateEvent
stp x0, x1, [sp, #-16]!
svc 0x45
ldp x3, x4, [sp], #16
str w1, [x3]
str w2, [x4]
ret
SVC_END
SVC_BEGIN svcMapPhysicalMemoryUnsafe
svc 0x48
ret
SVC_END
SVC_BEGIN svcUnmapPhysicalMemoryUnsafe
svc 0x49
ret
SVC_END
SVC_BEGIN svcSetUnsafeLimit
svc 0x4A
ret
SVC_END
SVC_BEGIN svcCreateCodeMemory
str x0, [sp, #-16]!
svc 0x4B
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcControlCodeMemory
svc 0x4C
ret
SVC_END
SVC_BEGIN svcReadWriteRegister
str x0, [sp, #-16]!
svc 0x4E
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcCreateSharedMemory
str x0, [sp, #-16]!
svc 0x50
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcMapTransferMemory
svc 0x51
ret
SVC_END
SVC_BEGIN svcUnmapTransferMemory
svc 0x52
ret
SVC_END
SVC_BEGIN svcCreateInterruptEvent
str x0, [sp, #-16]!
svc 0x53
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcQueryPhysicalAddress
str x0, [sp, #-16]!
svc 0x54
ldr x4, [sp], #16
stp x1, x2, [x4]
str x3, [x4, #16]
ret
SVC_END
SVC_BEGIN svcQueryIoMapping
str x0, [sp, #-16]!
svc 0x55
ldr x2, [sp], #16
str x1, [x2]
ret
SVC_END
SVC_BEGIN svcCreateDeviceAddressSpace
str x0, [sp, #-16]!
svc 0x56
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcAttachDeviceAddressSpace
svc 0x57
ret
SVC_END
SVC_BEGIN svcDetachDeviceAddressSpace
svc 0x58
ret
SVC_END
SVC_BEGIN svcMapDeviceAddressSpaceByForce
svc 0x59
ret
SVC_END
SVC_BEGIN svcMapDeviceAddressSpaceAligned
svc 0x5A
ret
SVC_END
SVC_BEGIN svcUnmapDeviceAddressSpace
svc 0x5C
ret
SVC_END
SVC_BEGIN svcDebugActiveProcess
str x0, [sp, #-16]!
svc 0x60
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcBreakDebugProcess
svc 0x61
ret
SVC_END
SVC_BEGIN svcTerminateDebugProcess
svc 0x62
ret
SVC_END
SVC_BEGIN svcGetDebugEvent
svc 0x63
ret
SVC_END
SVC_BEGIN svcLegacyContinueDebugEvent
svc 0x64
ret
SVC_END
SVC_BEGIN svcContinueDebugEvent
svc 0x64
ret
SVC_END
SVC_BEGIN svcGetProcessList
str x0, [sp, #-16]!
svc 0x65
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcGetThreadList
str x0, [sp, #-16]!
svc 0x66
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcGetDebugThreadContext
svc 0x67
ret
SVC_END
SVC_BEGIN svcSetDebugThreadContext
svc 0x68
ret
SVC_END
SVC_BEGIN svcQueryDebugProcessMemory
str x1, [sp, #-16]!
svc 0x69
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcReadDebugProcessMemory
svc 0x6A
ret
SVC_END
SVC_BEGIN svcWriteDebugProcessMemory
svc 0x6B
ret
SVC_END
SVC_BEGIN svcGetDebugThreadParam
stp x0, x1, [sp, #-16]!
svc 0x6D
ldp x3, x4, [sp], #16
str x1, [x3]
str w2, [x4]
ret
SVC_END
SVC_BEGIN svcGetSystemInfo
str x0, [sp, #-16]!
svc 0x6F
ldr x2, [sp], #16
str x1, [x2]
ret
SVC_END
SVC_BEGIN svcCreatePort
stp x0, x1, [sp, #-16]!
svc 0x70
ldp x3, x4, [sp], #16
str w1, [x3]
str w2, [x4]
ret
SVC_END
SVC_BEGIN svcManageNamedPort
str x0, [sp, #-16]!
svc 0x71
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcConnectToPort
str x0, [sp, #-16]!
svc 0x72
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcSetProcessMemoryPermission
svc 0x73
ret
SVC_END
SVC_BEGIN svcMapProcessMemory
svc 0x74
ret
SVC_END
SVC_BEGIN svcUnmapProcessMemory
svc 0x75
ret
SVC_END
SVC_BEGIN svcMapProcessCodeMemory
svc 0x77
ret
SVC_END
SVC_BEGIN svcUnmapProcessCodeMemory
svc 0x78
ret
SVC_END
SVC_BEGIN svcCreateProcess
str x0, [sp, #-16]!
svc 0x79
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcStartProcess
svc 0x7A
ret
SVC_END
SVC_BEGIN svcTerminateProcess
svc 0x7B
ret
SVC_END
SVC_BEGIN svcGetProcessInfo
str x0, [sp, #-16]!
svc 0x7C
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcCreateResourceLimit
str x0, [sp, #-16]!
svc 0x7D
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcSetResourceLimitLimitValue
svc 0x7E
ret
SVC_END
SVC_BEGIN svcCallSecureMonitor
str x0, [sp, #-16]!
mov x8, x0
ldp x0, x1, [x8]
ldp x2, x3, [x8, #0x10]
ldp x4, x5, [x8, #0x20]
ldp x6, x7, [x8, #0x30]
svc 0x7F
ldr x8, [sp], #16
stp x0, x1, [x8]
stp x2, x3, [x8, #0x10]
stp x4, x5, [x8, #0x20]
stp x6, x7, [x8, #0x30]
ret
SVC_END
|
Project-Gamblitz/Project-Gamblitz-Starlight | 4,349 | include/libnx/nx/source/runtime/exception.s | .macro CODE_BEGIN name
.section .text.\name, "ax", %progbits
.global \name
.type \name, %function
.align 2
.cfi_startproc
\name:
.endm
.macro CODE_END
.cfi_endproc
.endm
// Called by crt0 when the args at the time of entry indicate an exception occured.
.weak __libnx_exception_handler
.weak __libnx_exception_entry
CODE_BEGIN __libnx_exception_entry
cmp x1, #0
beq __libnx_exception_entry_abort
// Abort exception handling when __libnx_exception_handler is not defined.
adrp x5, :got:__libnx_exception_handler
ldr x5, [x5, #:got_lo12:__libnx_exception_handler]
cmp x5, #0
beq __libnx_exception_entry_abort
// Load IsCurrentProcessBeingDebugged.
stp x9, x10, [sp, #-16]!
stp x11, x12, [sp, #-16]!
stp x13, x14, [sp, #-16]!
stp x15, x16, [sp, #-16]!
stp x17, x18, [sp, #-16]!
stp x19, x20, [sp, #-16]!
str x21, [sp, #-16]!
stp x0, x1, [sp, #-16]!
sub sp, sp, #16
mov x0, sp
mov x1, #8
mov w2, wzr
mov x3, #0
bl svcGetInfo
mov w6, w0
ldr x7, [sp], #16
ldp x0, x1, [sp], #16
ldr x21, [sp], #16
ldp x19, x20, [sp], #16
ldp x17, x18, [sp], #16
ldp x15, x16, [sp], #16
ldp x13, x14, [sp], #16
ldp x11, x12, [sp], #16
ldp x9, x10, [sp], #16
// Abort when svcGetInfo failed.
cbnz w6, __libnx_exception_entry_abort
// Abort when IsCurrentProcessBeingDebugged is set where __nx_exception_ignoredebug==0.
adrp x6, __nx_exception_ignoredebug
ldr w5, [x6, #:lo12:__nx_exception_ignoredebug]
cbnz w5, __libnx_exception_entry_start
cbnz x7, __libnx_exception_entry_abort
__libnx_exception_entry_start:
adrp x2, __nx_exceptiondump
add x2, x2, #:lo12:__nx_exceptiondump
mov x5, x2
// error_desc
str w0, [x2], #4
// pad
str wzr, [x2], #4
str wzr, [x2], #4
str wzr, [x2], #4
// GPRs 0..8
ldp x3, x4, [x1]
str x5, [x1], #16 // x0 = __nx_exceptiondump
stp x3, x4, [x2], #16
ldp x3, x4, [x1], #16
stp x3, x4, [x2], #16
ldp x3, x4, [x1], #16
stp x3, x4, [x2], #16
ldp x3, x4, [x1], #16
stp x3, x4, [x2], #16
ldr x3, [x1], #8
str x3, [x2], #8
// GPRs 9..28
str x9, [x2], #8
stp x10, x11, [x2], #16
stp x12, x13, [x2], #16
stp x14, x15, [x2], #16
stp x16, x17, [x2], #16
stp x18, x19, [x2], #16
stp x20, x21, [x2], #16
stp x22, x23, [x2], #16
stp x24, x25, [x2], #16
stp x26, x27, [x2], #16
str x28, [x2], #8
// fp
str x29, [x2], #8
// lr
ldr x3, [x1], #8
str x3, [x2], #8
// sp
adrp x4, __nx_exception_stack
add x4, x4, #:lo12:__nx_exception_stack
adrp x5, __nx_exception_stack_size
ldr x5, [x5, #:lo12:__nx_exception_stack_size]
add x4, x4, x5
ldr x3, [x1]
str x4, [x1], #8 // sp = __nx_exception_stack + __nx_exception_stack_size
str x3, [x2], #8
// elr_el1 (pc)
adrp x4, __libnx_exception_returnentry
add x4, x4, #:lo12:__libnx_exception_returnentry
ldr x3, [x1]
str x4, [x1], #8 // elr_el1 = __libnx_exception_returnentry
str x3, [x2], #8
// padding
str xzr, [x2], #8
// fpu_gprs
stp q0, q1, [x2], #32
stp q2, q3, [x2], #32
stp q4, q5, [x2], #32
stp q6, q7, [x2], #32
stp q8, q9, [x2], #32
stp q10, q11, [x2], #32
stp q12, q13, [x2], #32
stp q14, q15, [x2], #32
stp q16, q17, [x2], #32
stp q18, q19, [x2], #32
stp q20, q21, [x2], #32
stp q22, q23, [x2], #32
stp q24, q25, [x2], #32
stp q26, q27, [x2], #32
stp q28, q29, [x2], #32
stp q30, q31, [x2], #32
// 4 u32s: pstate, afsr0, afsr1, and esr.
ldr w3, [x1], #4
str w3, [x2], #4
ldr w3, [x1], #4
str w3, [x2], #4
ldr w3, [x1], #4
str w3, [x2], #4
ldr w3, [x1], #4
str w3, [x2], #4
//far
ldr x3, [x1], #8
str x3, [x2], #8
mov w0, wzr
b __libnx_exception_entry_end
__libnx_exception_entry_abort:
mov w0, #0xf801
__libnx_exception_entry_end:
bl svcReturnFromException
b .
CODE_END
// Jumped to by kernel in svcReturnFromException via the overridden elr_el1, with x0 set to __nx_exceptiondump.
CODE_BEGIN __libnx_exception_returnentry
bl __libnx_exception_handler
mov w0, wzr
mov x1, #0
mov x2, #0
bl svcBreak
b .
CODE_END
|
Project-Gamblitz/Project-Gamblitz-Starlight | 2,009 | include/libnx/nx/source/runtime/switch_crt0.s | .section ".crt0","ax"
.global _start
_start:
b startup
.word __nx_mod0 - _start
.ascii "HOMEBREW"
.org _start+0x80
startup:
// save lr
mov x7, x30
// get aslr base
bl +4
sub x6, x30, #0x88
// context ptr and main thread handle
mov x5, x0
mov x4, x1
// Handle the exception if needed.
// if (ctx != NULL && main_thread != -1)__libnx_exception_entry(<inargs>);
cmp x5, #0
ccmn x4, #1, #4, ne // 4 = Z
beq bssclr_start
b __libnx_exception_entry
bssclr_start:
mov x27, x7
mov x25, x5
mov x26, x4
// clear .bss
adrp x0, __bss_start__
adrp x1, __bss_end__
add x0, x0, #:lo12:__bss_start__
add x1, x1, #:lo12:__bss_end__
sub x1, x1, x0 // calculate size
add x1, x1, #7 // round up to 8
bic x1, x1, #7
bss_loop:
str xzr, [x0], #8
subs x1, x1, #8
bne bss_loop
// store stack pointer
mov x1, sp
adrp x0, __stack_top
str x1, [x0, #:lo12:__stack_top]
// process .dynamic section
mov x0, x6
adrp x1, _DYNAMIC
add x1, x1, #:lo12:_DYNAMIC
bl __nx_dynamic
// initialize system
mov x0, x25
mov x1, x26
mov x2, x27
bl __libnx_init
// call entrypoint
adrp x0, __system_argc // argc
ldr w0, [x0, #:lo12:__system_argc]
adrp x1, __system_argv // argv
ldr x1, [x1, #:lo12:__system_argv]
adrp x30, exit
add x30, x30, #:lo12:exit
b main
.global __nx_exit
.type __nx_exit, %function
__nx_exit:
// restore stack pointer
adrp x8, __stack_top
ldr x8, [x8, #:lo12:__stack_top]
mov sp, x8
// jump back to loader
br x1
.global __nx_mod0
__nx_mod0:
.ascii "MOD0"
.word _DYNAMIC - __nx_mod0
.word __bss_start__ - __nx_mod0
.word __bss_end__ - __nx_mod0
.word __eh_frame_hdr_start - __nx_mod0
.word __eh_frame_hdr_end - __nx_mod0
.word 0 // "offset to runtime-generated module object" (??)
|
Project-Gamblitz/Project-Gamblitz-Starlight | 1,288 | include/libnx/nx/source/arm/cache.s | .macro CODE_BEGIN name
.section .text.\name, "ax", %progbits
.global \name
.type \name, %function
.align 2
.cfi_startproc
\name:
.endm
.macro CODE_END
.cfi_endproc
.endm
CODE_BEGIN armDCacheFlush
add x1, x1, x0
mrs x8, CTR_EL0
lsr x8, x8, #16
and x8, x8, #0xf
mov x9, #4
lsl x9, x9, x8
sub x10, x9, #1
bic x8, x0, x10
mov x10, x1
armDCacheFlush_L0:
dc civac, x8
add x8, x8, x9
cmp x8, x10
bcc armDCacheFlush_L0
dsb sy
ret
CODE_END
CODE_BEGIN armDCacheClean
add x1, x1, x0
mrs x8, CTR_EL0
lsr x8, x8, #16
and x8, x8, #0xf
mov x9, #4
lsl x9, x9, x8
sub x10, x9, #1
bic x8, x0, x10
mov x10, x1
armDCacheClean_L0:
dc cvac, x8
add x8, x8, x9
cmp x8, x10
bcc armDCacheClean_L0
dsb sy
ret
CODE_END
CODE_BEGIN armICacheInvalidate
add x1, x1, x0
mrs x8, CTR_EL0
and x8, x8, #0xf
mov x9, #4
lsl x9, x9, x8
sub x10, x9, #1
bic x8, x0, x10
mov x10, x1
armICacheInvalidate_L0:
ic ivau, x8
add x8, x8, x9
cmp x8, x10
bcc armICacheInvalidate_L0
dsb sy
ret
CODE_END
CODE_BEGIN armDCacheZero
add x1, x1, x0
mrs x8, CTR_EL0
lsr x8, x8, #16
and x8, x8, #0xf
mov x9, #4
lsl x9, x9, x8
sub x10, x9, #1
bic x8, x0, x10
mov x10, x1
armDCacheZero_L0:
dc zva, x8
add x8, x8, x9
cmp x8, x10
bcc armDCacheZero_L0
dsb sy
ret
CODE_END
|
shilei-massclouds/arch_boot | 1,730 | arch_boot/linker.lds.S | OUTPUT_ARCH(%ARCH%)
BASE_ADDRESS = %KERNEL_BASE%;
ENTRY(_start)
SECTIONS
{
. = BASE_ADDRESS;
_skernel = .;
.text : ALIGN(4K) {
_stext = .;
*(.text.boot)
*(.text .text.*)
*(.fixup)
. = ALIGN(4K);
_etext = .;
}
.rodata : ALIGN(4K) {
_srodata = .;
*(.rodata .rodata.*)
*(.srodata .srodata.*)
*(.sdata2 .sdata2.*)
. = ALIGN(16);
__start___ex_table = .;
KEEP(*(__ex_table))
__stop___ex_table = .;
. = ALIGN(4K);
_erodata = .;
}
.data : ALIGN(4K) {
_sdata = .;
*(.data.boot_page_table)
. = ALIGN(4K);
*(.data .data.*)
*(.sdata .sdata.*)
*(.got .got.*)
}
.tdata : ALIGN(0x10) {
_stdata = .;
*(.tdata .tdata.*)
_etdata = .;
}
.tbss : ALIGN(0x10) {
_stbss = .;
*(.tbss .tbss.*)
*(.tcommon)
_etbss = .;
}
. = ALIGN(4K);
_percpu_start = .;
.percpu 0x0 : AT(_percpu_start) {
_percpu_load_start = .;
*(.percpu .percpu.*)
_percpu_load_end = .;
. = ALIGN(64);
_percpu_size_aligned = .;
. = _percpu_load_start + _percpu_size_aligned * %SMP%;
}
. = _percpu_start + SIZEOF(.percpu);
_percpu_end = .;
. = ALIGN(4K);
_edata = .;
.bss : ALIGN(4K) {
boot_stack = .;
*(.bss.stack)
. = ALIGN(4K);
boot_stack_top = .;
_sbss = .;
*(.bss .bss.*)
*(.sbss .sbss.*)
*(COMMON)
. = ALIGN(4K);
_ebss = .;
}
_ekernel = .;
/DISCARD/ : {
*(.comment) *(.gnu*) *(.note*) *(.eh_frame*)
}
}
|
shilei-massclouds/arch_boot | 3,882 | arch_boot/src/platform/x86_pc/multiboot.S | # Bootstrapping from 32-bit with the Multiboot specification.
# See https://www.gnu.org/software/grub/manual/multiboot/multiboot.html
.section .text.boot
.code32
.global _start
_start:
mov edi, eax # arg1: magic: 0x2BADB002
mov esi, ebx # arg2: multiboot info
jmp bsp_entry32
.balign 4
.type multiboot_header, STT_OBJECT
multiboot_header:
.int {mb_hdr_magic} # magic: 0x1BADB002
.int {mb_hdr_flags} # flags
.int -({mb_hdr_magic} + {mb_hdr_flags}) # checksum
.int multiboot_header - {offset} # header_addr
.int _skernel - {offset} # load_addr
.int _edata - {offset} # load_end
.int _ebss - {offset} # bss_end_addr
.int _start - {offset} # entry_addr
# Common code in 32-bit, prepare states to enter 64-bit.
.macro ENTRY32_COMMON
# set data segment selectors
mov ax, 0x18
mov ss, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
# set PAE, PGE bit in CR4
mov eax, {cr4}
mov cr4, eax
# load the temporary page table
lea eax, [.Ltmp_pml4 - {offset}]
mov cr3, eax
# set LME, NXE bit in IA32_EFER
mov ecx, {efer_msr}
mov edx, 0
mov eax, {efer}
wrmsr
# set protected mode, write protect, paging bit in CR0
mov eax, {cr0}
mov cr0, eax
.endm
# Common code in 64-bit
.macro ENTRY64_COMMON
# clear segment selectors
xor ax, ax
mov ss, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
.endm
.code32
bsp_entry32:
lgdt [.Ltmp_gdt_desc - {offset}] # load the temporary GDT
ENTRY32_COMMON
ljmp 0x10, offset bsp_entry64 - {offset} # 0x10 is code64 segment
.code64
bsp_entry64:
ENTRY64_COMMON
# set RSP to boot stack
movabs rsp, offset {boot_stack}
add rsp, {boot_stack_size}
# call rust_entry(magic, mbi)
movabs rax, offset {entry}
call rax
jmp .Lhlt
.Lhlt:
hlt
jmp .Lhlt
.section .rodata
.balign 8
.Ltmp_gdt_desc:
.short .Ltmp_gdt_end - .Ltmp_gdt - 1 # limit
.long .Ltmp_gdt - {offset} # base
.section .data
.balign 16
.Ltmp_gdt:
.quad 0x0000000000000000 # 0x00: null
.quad 0x00cf9b000000ffff # 0x08: code segment (base=0, limit=0xfffff, type=32bit code exec/read, DPL=0, 4k)
.quad 0x00af9b000000ffff # 0x10: code segment (base=0, limit=0xfffff, type=64bit code exec/read, DPL=0, 4k)
.quad 0x00cf93000000ffff # 0x18: data segment (base=0, limit=0xfffff, type=32bit data read/write, DPL=0, 4k)
.Ltmp_gdt_end:
.balign 4096
.Ltmp_pml4:
# 0x0000_0000 ~ 0xffff_ffff
.quad .Ltmp_pdpt_low - {offset} + 0x3 # PRESENT | WRITABLE | paddr(tmp_pdpt)
.zero 8 * 510
# 0xffff_ff80_0000_0000 ~ 0xffff_ff80_ffff_ffff
.quad .Ltmp_pdpt_high - {offset} + 0x3 # PRESENT | WRITABLE | paddr(tmp_pdpt)
# FIXME: may not work on macOS using hvf as the CPU does not support 1GB page (pdpe1gb)
.Ltmp_pdpt_low:
.quad 0x0000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x0)
.quad 0x40000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x4000_0000)
.quad 0x80000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x8000_0000)
.quad 0xc0000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0xc000_0000)
.zero 8 * 508
.Ltmp_pdpt_high:
.quad 0x0000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x0)
.quad 0x40000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x4000_0000)
.quad 0x80000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x8000_0000)
.quad 0xc0000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0xc000_0000)
.zero 8 * 508
|
shilei-massclouds/lkmodel | 1,505 | axtrap/axtrap/src/arch/x86_64/trap.S | .equ NUM_INT, 256
.altmacro
.macro DEF_HANDLER, i
.Ltrap_handler_\i:
.if \i == 8 || (\i >= 10 && \i <= 14) || \i == 17
# error code pushed by CPU
push \i # interrupt vector
jmp .Ltrap_common
.else
push 0 # fill in error code in TrapFrame
push \i # interrupt vector
jmp .Ltrap_common
.endif
.endm
.macro DEF_TABLE_ENTRY, i
.quad .Ltrap_handler_\i
.endm
.section .text
.code64
_trap_handlers:
.set i, 0
.rept NUM_INT
DEF_HANDLER %i
.set i, i + 1
.endr
.Ltrap_common:
test byte ptr [rsp + 3 * 8], 3 # swap GS if it comes from user space
jz 1f
swapgs
1:
push r15
push r14
push r13
push r12
push r11
push r10
push r9
push r8
push rdi
push rsi
push rbp
push rbx
push rdx
push rcx
push rax
mov rdi, rsp
call x86_trap_handler
pop rax
pop rcx
pop rdx
pop rbx
pop rbp
pop rsi
pop rdi
pop r8
pop r9
pop r10
pop r11
pop r12
pop r13
pop r14
pop r15
test byte ptr [rsp + 3 * 8], 3 # swap GS back if return to user space
jz 2f
swapgs
2:
add rsp, 16 # pop vector, error_code
iretq
.section .rodata
.global trap_handler_table
trap_handler_table:
.set i, 0
.rept NUM_INT
DEF_TABLE_ENTRY %i
.set i, i + 1
.endr
|
shilei-massclouds/lkmodel | 1,201 | axtrap/axtrap/src/arch/x86_64/syscall.S | .section .text
syscall_entry:
swapgs
# The user rsp and kernel rsp are defined in axhal
mov gs:[offset __PERCPU_USER_RSP_OFFSET], rsp
mov rsp, gs:[offset __PERCPU_KERNEL_RSP_OFFSET]
sub rsp, 8 // skip user_ss
push gs:[offset __PERCPU_USER_RSP_OFFSET] // user_rsp
push r11 // rflags
mov [rsp - 2 * 8], rcx // rip
sub rsp, 4 * 8 // skip until general registers
push r15
push r14
push r13
push r12
push r11
push r10
push r9
push r8
push rdi
push rsi
push rbp
push rbx
push rdx
push rcx
push rax
mov rdi, rsp
call x86_syscall_handler
pop rax
pop rcx
pop rdx
pop rbx
pop rbp
pop rsi
pop rdi
pop r8
pop r9
pop r10
pop r11
pop r12
pop r13
pop r14
pop r15
add rsp, 7 * 8
mov rcx, [rsp - 5 * 8] // rip
mov r11, [rsp - 3 * 8] // rflags
mov rsp, [rsp - 2 * 8] // user_rsp
swapgs
sysretq |
shilei-massclouds/lkmodel | 1,730 | arch_boot/arch_boot/linker.lds.S | OUTPUT_ARCH(%ARCH%)
BASE_ADDRESS = %KERNEL_BASE%;
ENTRY(_start)
SECTIONS
{
. = BASE_ADDRESS;
_skernel = .;
.text : ALIGN(4K) {
_stext = .;
*(.text.boot)
*(.text .text.*)
*(.fixup)
. = ALIGN(4K);
_etext = .;
}
.rodata : ALIGN(4K) {
_srodata = .;
*(.rodata .rodata.*)
*(.srodata .srodata.*)
*(.sdata2 .sdata2.*)
. = ALIGN(16);
__start___ex_table = .;
KEEP(*(__ex_table))
__stop___ex_table = .;
. = ALIGN(4K);
_erodata = .;
}
.data : ALIGN(4K) {
_sdata = .;
*(.data.boot_page_table)
. = ALIGN(4K);
*(.data .data.*)
*(.sdata .sdata.*)
*(.got .got.*)
}
.tdata : ALIGN(0x10) {
_stdata = .;
*(.tdata .tdata.*)
_etdata = .;
}
.tbss : ALIGN(0x10) {
_stbss = .;
*(.tbss .tbss.*)
*(.tcommon)
_etbss = .;
}
. = ALIGN(4K);
_percpu_start = .;
.percpu 0x0 : AT(_percpu_start) {
_percpu_load_start = .;
*(.percpu .percpu.*)
_percpu_load_end = .;
. = ALIGN(64);
_percpu_size_aligned = .;
. = _percpu_load_start + _percpu_size_aligned * %SMP%;
}
. = _percpu_start + SIZEOF(.percpu);
_percpu_end = .;
. = ALIGN(4K);
_edata = .;
.bss : ALIGN(4K) {
boot_stack = .;
*(.bss.stack)
. = ALIGN(4K);
boot_stack_top = .;
_sbss = .;
*(.bss .bss.*)
*(.sbss .sbss.*)
*(COMMON)
. = ALIGN(4K);
_ebss = .;
}
_ekernel = .;
/DISCARD/ : {
*(.comment) *(.gnu*) *(.note*) *(.eh_frame*)
}
}
|
shilei-massclouds/lkmodel | 3,882 | arch_boot/arch_boot/src/platform/x86_pc/multiboot.S | # Bootstrapping from 32-bit with the Multiboot specification.
# See https://www.gnu.org/software/grub/manual/multiboot/multiboot.html
.section .text.boot
.code32
.global _start
_start:
mov edi, eax # arg1: magic: 0x2BADB002
mov esi, ebx # arg2: multiboot info
jmp bsp_entry32
.balign 4
.type multiboot_header, STT_OBJECT
multiboot_header:
.int {mb_hdr_magic} # magic: 0x1BADB002
.int {mb_hdr_flags} # flags
.int -({mb_hdr_magic} + {mb_hdr_flags}) # checksum
.int multiboot_header - {offset} # header_addr
.int _skernel - {offset} # load_addr
.int _edata - {offset} # load_end
.int _ebss - {offset} # bss_end_addr
.int _start - {offset} # entry_addr
# Common code in 32-bit, prepare states to enter 64-bit.
.macro ENTRY32_COMMON
# set data segment selectors
mov ax, 0x18
mov ss, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
# set PAE, PGE bit in CR4
mov eax, {cr4}
mov cr4, eax
# load the temporary page table
lea eax, [.Ltmp_pml4 - {offset}]
mov cr3, eax
# set LME, NXE bit in IA32_EFER
mov ecx, {efer_msr}
mov edx, 0
mov eax, {efer}
wrmsr
# set protected mode, write protect, paging bit in CR0
mov eax, {cr0}
mov cr0, eax
.endm
# Common code in 64-bit
.macro ENTRY64_COMMON
# clear segment selectors
xor ax, ax
mov ss, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
.endm
.code32
bsp_entry32:
lgdt [.Ltmp_gdt_desc - {offset}] # load the temporary GDT
ENTRY32_COMMON
ljmp 0x10, offset bsp_entry64 - {offset} # 0x10 is code64 segment
.code64
bsp_entry64:
ENTRY64_COMMON
# set RSP to boot stack
movabs rsp, offset {boot_stack}
add rsp, {boot_stack_size}
# call rust_entry(magic, mbi)
movabs rax, offset {entry}
call rax
jmp .Lhlt
.Lhlt:
hlt
jmp .Lhlt
.section .rodata
.balign 8
.Ltmp_gdt_desc:
.short .Ltmp_gdt_end - .Ltmp_gdt - 1 # limit
.long .Ltmp_gdt - {offset} # base
.section .data
.balign 16
.Ltmp_gdt:
.quad 0x0000000000000000 # 0x00: null
.quad 0x00cf9b000000ffff # 0x08: code segment (base=0, limit=0xfffff, type=32bit code exec/read, DPL=0, 4k)
.quad 0x00af9b000000ffff # 0x10: code segment (base=0, limit=0xfffff, type=64bit code exec/read, DPL=0, 4k)
.quad 0x00cf93000000ffff # 0x18: data segment (base=0, limit=0xfffff, type=32bit data read/write, DPL=0, 4k)
.Ltmp_gdt_end:
.balign 4096
.Ltmp_pml4:
# 0x0000_0000 ~ 0xffff_ffff
.quad .Ltmp_pdpt_low - {offset} + 0x3 # PRESENT | WRITABLE | paddr(tmp_pdpt)
.zero 8 * 510
# 0xffff_ff80_0000_0000 ~ 0xffff_ff80_ffff_ffff
.quad .Ltmp_pdpt_high - {offset} + 0x3 # PRESENT | WRITABLE | paddr(tmp_pdpt)
# FIXME: may not work on macOS using hvf as the CPU does not support 1GB page (pdpe1gb)
.Ltmp_pdpt_low:
.quad 0x0000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x0)
.quad 0x40000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x4000_0000)
.quad 0x80000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x8000_0000)
.quad 0xc0000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0xc000_0000)
.zero 8 * 508
.Ltmp_pdpt_high:
.quad 0x0000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x0)
.quad 0x40000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x4000_0000)
.quad 0x80000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x8000_0000)
.quad 0xc0000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0xc000_0000)
.zero 8 * 508
|
shilei-massclouds/lkmodel | 1,746 | axhal/axhal/linker.lds.S | OUTPUT_ARCH(%ARCH%)
BASE_ADDRESS = %KERNEL_BASE%;
ENTRY(_start)
SECTIONS
{
. = BASE_ADDRESS;
_skernel = .;
.text : ALIGN(4K) {
_stext = .;
*(.text.boot)
*(.text .text.*)
*(.fixup)
. = ALIGN(4K);
_etext = .;
}
.rodata : ALIGN(4K) {
_srodata = .;
_srodata = .;
*(.rodata .rodata.*)
*(.srodata .srodata.*)
*(.sdata2 .sdata2.*)
. = ALIGN(16);
__start___ex_table = .;
*(__ex_table)
__stop___ex_table = .;
. = ALIGN(4K);
_erodata = .;
}
.data : ALIGN(4K) {
_sdata = .;
*(.data.boot_page_table)
. = ALIGN(4K);
*(.data .data.*)
*(.sdata .sdata.*)
*(.got .got.*)
}
.tdata : ALIGN(0x10) {
_stdata = .;
*(.tdata .tdata.*)
_etdata = .;
}
.tbss : ALIGN(0x10) {
_stbss = .;
*(.tbss .tbss.*)
*(.tcommon)
_etbss = .;
}
. = ALIGN(4K);
_percpu_start = .;
.percpu 0x0 : AT(_percpu_start) {
_percpu_load_start = .;
*(.percpu .percpu.*)
_percpu_load_end = .;
. = ALIGN(64);
_percpu_size_aligned = .;
. = _percpu_load_start + _percpu_size_aligned * %SMP%;
}
. = _percpu_start + SIZEOF(.percpu);
_percpu_end = .;
. = ALIGN(4K);
_edata = .;
.bss : ALIGN(4K) {
boot_stack = .;
*(.bss.stack)
. = ALIGN(4K);
boot_stack_top = .;
_sbss = .;
*(.bss .bss.*)
*(.sbss .sbss.*)
*(COMMON)
. = ALIGN(4K);
_ebss = .;
}
_ekernel = .;
/DISCARD/ : {
*(.comment) *(.gnu*) *(.note*) *(.eh_frame*)
}
}
|
shilei-massclouds/lkmodel | 1,965 | axhal/axhal/src/platform/x86_pc/ap_start.S | # Boot application processors into the protected mode.
# Each non-boot CPU ("AP") is started up in response to a STARTUP
# IPI from the boot CPU. Section B.4.2 of the Multi-Processor
# Specification says that the AP will start in real mode with CS:IP
# set to XY00:0000, where XY is an 8-bit value sent with the
# STARTUP. Thus this code must start at a 4096-byte boundary.
#
# Because this code sets DS to zero, it must sit
# at an address in the low 2^16 bytes.
.equ pa_ap_start32, ap_start32 - ap_start + {start_page_paddr}
.equ pa_ap_gdt, .Lap_tmp_gdt - ap_start + {start_page_paddr}
.equ pa_ap_gdt_desc, .Lap_tmp_gdt_desc - ap_start + {start_page_paddr}
.equ stack_ptr, {start_page_paddr} + 0xff0
.equ entry_ptr, {start_page_paddr} + 0xff8
# 0x6000
.section .text
.code16
.p2align 12
.global ap_start
ap_start:
cli
wbinvd
xor ax, ax
mov ds, ax
mov es, ax
mov ss, ax
mov fs, ax
mov gs, ax
# load the 64-bit GDT
lgdt [pa_ap_gdt_desc]
# switch to protected-mode
mov eax, cr0
or eax, (1 << 0)
mov cr0, eax
# far jump to 32-bit code. 0x8 is code32 segment selector
ljmp 0x8, offset pa_ap_start32
.code32
ap_start32:
mov esp, [stack_ptr]
mov eax, [entry_ptr]
jmp eax
.balign 8
# .type multiboot_header, STT_OBJECT
.Lap_tmp_gdt_desc:
.short .Lap_tmp_gdt_end - .Lap_tmp_gdt - 1 # limit
.long pa_ap_gdt # base
.balign 16
.Lap_tmp_gdt:
.quad 0x0000000000000000 # 0x00: null
.quad 0x00cf9b000000ffff # 0x08: code segment (base=0, limit=0xfffff, type=32bit code exec/read, DPL=0, 4k)
.quad 0x00af9b000000ffff # 0x10: code segment (base=0, limit=0xfffff, type=64bit code exec/read, DPL=0, 4k)
.quad 0x00cf93000000ffff # 0x18: data segment (base=0, limit=0xfffff, type=32bit data read/write, DPL=0, 4k)
.Lap_tmp_gdt_end:
# 0x7000
.p2align 12
.global ap_end
ap_end:
|
shilei-massclouds/lkmodel | 2,519 | axhal/axhal/src/arch/aarch64/trap.S | .macro SAVE_REGS
sub sp, sp, 34 * 8
stp x0, x1, [sp]
stp x2, x3, [sp, 2 * 8]
stp x4, x5, [sp, 4 * 8]
stp x6, x7, [sp, 6 * 8]
stp x8, x9, [sp, 8 * 8]
stp x10, x11, [sp, 10 * 8]
stp x12, x13, [sp, 12 * 8]
stp x14, x15, [sp, 14 * 8]
stp x16, x17, [sp, 16 * 8]
stp x18, x19, [sp, 18 * 8]
stp x20, x21, [sp, 20 * 8]
stp x22, x23, [sp, 22 * 8]
stp x24, x25, [sp, 24 * 8]
stp x26, x27, [sp, 26 * 8]
stp x28, x29, [sp, 28 * 8]
mrs x9, sp_el0
mrs x10, elr_el1
mrs x11, spsr_el1
stp x30, x9, [sp, 30 * 8]
stp x10, x11, [sp, 32 * 8]
.endm
.macro RESTORE_REGS
ldp x10, x11, [sp, 32 * 8]
ldp x30, x9, [sp, 30 * 8]
msr sp_el0, x9
msr elr_el1, x10
msr spsr_el1, x11
ldp x28, x29, [sp, 28 * 8]
ldp x26, x27, [sp, 26 * 8]
ldp x24, x25, [sp, 24 * 8]
ldp x22, x23, [sp, 22 * 8]
ldp x20, x21, [sp, 20 * 8]
ldp x18, x19, [sp, 18 * 8]
ldp x16, x17, [sp, 16 * 8]
ldp x14, x15, [sp, 14 * 8]
ldp x12, x13, [sp, 12 * 8]
ldp x10, x11, [sp, 10 * 8]
ldp x8, x9, [sp, 8 * 8]
ldp x6, x7, [sp, 6 * 8]
ldp x4, x5, [sp, 4 * 8]
ldp x2, x3, [sp, 2 * 8]
ldp x0, x1, [sp]
add sp, sp, 34 * 8
.endm
.macro INVALID_EXCP, kind, source
.p2align 7
SAVE_REGS
mov x0, sp
mov x1, \kind
mov x2, \source
bl invalid_exception
b .Lexception_return
.endm
.macro HANDLE_SYNC
.p2align 7
SAVE_REGS
mov x0, sp
bl handle_sync_exception
b .Lexception_return
.endm
.macro HANDLE_IRQ
.p2align 7
SAVE_REGS
mov x0, sp
bl handle_irq_exception
b .Lexception_return
.endm
.section .text
.p2align 11
.global exception_vector_base
exception_vector_base:
// current EL, with SP_EL0
INVALID_EXCP 0 0
INVALID_EXCP 1 0
INVALID_EXCP 2 0
INVALID_EXCP 3 0
// current EL, with SP_ELx
HANDLE_SYNC
HANDLE_IRQ
INVALID_EXCP 2 1
INVALID_EXCP 3 1
// lower EL, aarch64
HANDLE_SYNC
HANDLE_IRQ
INVALID_EXCP 2 2
INVALID_EXCP 3 2
// lower EL, aarch32
INVALID_EXCP 0 3
INVALID_EXCP 1 3
INVALID_EXCP 2 3
INVALID_EXCP 3 3
.Lexception_return:
RESTORE_REGS
eret
.section .text
.balign 4
.global ret_from_fork
ret_from_fork:
mov sp, x0
RESTORE_REGS
eret
|
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 6,611 | sdk/appsrc/fsbl/src/fsbl_handoff.S | #ifdef __GNUC__
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file handoff.S
*
* Contains the code that does the handoff to the loaded application. This
* code lives high in the ROM.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date.word Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 03/01/10 Initial release
* 7.00a kc 10/23/13 Added support for armcc compiler
* </pre>
*
* @note
* Assumes that the starting address of the FSBL is provided by the calling routine
* in R0.
*
******************************************************************************/
.globl FsblHandoffJtagExit
.globl FsblHandoffExit
.section .handoff,"axS"
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
FsblHandoffJtagExit:
mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
dsb
isb /* make sure it completes */
ldr r4, =0
mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
isb /* make sure it completes */
Loop:
wfe
b Loop
FsblHandoffExit:
mov lr, r0 /* move the destination address into link register */
mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
dsb
isb /* make sure it completes */
ldr r4, =0
mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
isb /* make sure it completes */
bx lr /* force the switch, destination should have been in r0 */
.Ldone: b .Ldone /* Paranoia: we should never get here */
.end
#elif defined (__IASMARM__)
PUBLIC FsblHandoffJtagExit
PUBLIC FsblHandoffExit
SECTION .handoff:CODE:NOROOT(2)
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
FsblHandoffJtagExit
mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
dsb
isb ;/* make sure it completes */
ldr r4, =0
mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
isb ;/* make sure it completes */
Loop
wfe
b Loop
FsblHandoffExit
mov lr, r0 ;/* move the destination address into link register */
mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
dsb
isb ;/* make sure it completes */
ldr r4, =0
mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
isb ;/* make sure it completes */
bx lr ;/* force the switch, destination should have been in r0 */
.Ldone
b .Ldone ;/* Paranoia: we should never get here */
END
#else
EXPORT FsblHandoffJtagExit
EXPORT FsblHandoffExit
AREA |.handoff|,CODE
;/***************************** Include Files *********************************/
;/************************** Constant Definitions *****************************/
;/**************************** Type Definitions *******************************/
;/***************** Macros (Inline Functions) Definitions *********************/
;/************************** Function Prototypes ******************************/
;/************************** Variable Definitions *****************************/
FsblHandoffJtagExit
mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
dsb
isb ;/* make sure it completes */
ldr r4, =0
mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
isb ;/* make sure it completes */
Loop
wfe
b Loop
FsblHandoffExit
mov lr, r0 ;/* move the destination address into link register */
mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
dsb
isb ;/* make sure it completes */
ldr r4, =0
mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
isb ;/* make sure it completes */
bx lr ;/* force the switch, destination should have been in r0 */
Ldone b Ldone ;/* Paranoia: we should never get here */
END
#endif
|
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 4,428 | sdk/appsrc/fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil-crt0.S | /******************************************************************************
*
* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xil-crt0.S
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a ecm 10/20/09 Initial version
* 3.05a sdm 02/02/12 Added code for profiling
* 3.06a sgd 05/16/12 Added global constructors and cleanup code
* Uart initialization based on compiler flag
* 3.07a sgd 07/05/12 Updated with reset and start Global Timer
* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
* 4.2 pkp 08/04/14 Removed PEEP board related code which contained
* initialization of uart smc nor and sram
* 5.3 pkp 10/07/15 Added support for OpenAMP by not initializing global
* timer when USE_AMP flag is defined
* 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API.
* Now the TTC instance as specified by the user will be
* started.
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#include "bspconfig.h"
.file "xil-crt0.S"
.section ".got2","aw"
.align 2
.text
.Lsbss_start:
.long __sbss_start
.Lsbss_end:
.long __sbss_end
.Lbss_start:
.long __bss_start
.Lbss_end:
.long __bss_end
.Lstack:
.long __stack
.globl _start
_start:
bl __cpu_init /* Initialize the CPU first (BSP provides this) */
mov r0, #0
/* clear sbss */
ldr r1,.Lsbss_start /* calculate beginning of the SBSS */
ldr r2,.Lsbss_end /* calculate end of the SBSS */
.Lloop_sbss:
cmp r1,r2
bge .Lenclsbss /* If no SBSS, no clearing required */
str r0, [r1], #4
b .Lloop_sbss
.Lenclsbss:
/* clear bss */
ldr r1,.Lbss_start /* calculate beginning of the BSS */
ldr r2,.Lbss_end /* calculate end of the BSS */
.Lloop_bss:
cmp r1,r2
bge .Lenclbss /* If no BSS, no clearing required */
str r0, [r1], #4
b .Lloop_bss
.Lenclbss:
/* set stack pointer */
ldr r13,.Lstack /* stack address */
/* Reset and start Global Timer */
mov r0, #0x0
mov r1, #0x0
/* Reset and start Triple Timer Counter */
#if defined SLEEP_TIMER_BASEADDR
bl XTime_StartTTCTimer
#endif
#if USE_AMP != 1
bl XTime_SetTime
#endif
#ifdef PROFILING /* defined in Makefile */
/* Setup profiling stuff */
bl _profile_init
#endif /* PROFILING */
/* run global constructors */
bl __libc_init_array
/* make sure argc and argv are valid */
mov r0, #0
mov r1, #0
/* Let her rip */
bl main
/* Cleanup global constructors */
bl __libc_fini_array
#ifdef PROFILING
/* Cleanup profiling stuff */
bl _profile_clean
#endif /* PROFILING */
/* All done */
bl exit
.Lexit: /* should never get here */
b .Lexit
.Lstart:
.size _start,.Lstart-_start
|
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 9,105 | sdk/appsrc/fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/translation_table.S | /******************************************************************************
*
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file translation_table.s
*
* @addtogroup a9_boot_code
* @{
* <h2> translation_table.S </h2>
* translation_table.S contains a static page table required by MMU for
* cortex-A9. This translation table is flat mapped (input address = output
* address) with default memory attributes defined for zynq architecture. It
* utilizes short descriptor translation table format with each section defining
* 1MB of memory.
*
* The overview of translation table memory attributes is described below.
*
*| | Memory Range | Definition in Translation Table |
*|-----------------------|-------------------------|-----------------------------------|
*| DDR | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable |
*| PL | 0x40000000 - 0xBFFFFFFF | Strongly Ordered |
*| Reserved | 0xC0000000 - 0xDFFFFFFF | Unassigned |
*| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory |
*| Reserved | 0xE0300000 - 0xE0FFFFFF | Unassigned |
*| NAND, NOR | 0xE1000000 - 0xE3FFFFFF | Device memory |
*| SRAM | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable |
*| Reserved | 0xE6000000 - 0xF7FFFFFF | Unassigned |
*| AMBA APB Peripherals | 0xF8000000 - 0xF8FFFFFF | Device Memory |
*| Reserved | 0xF9000000 - 0xFBFFFFFF | Unassigned |
*| Linear QSPI - XIP | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable |
*| Reserved | 0xFE000000 - 0xFFEFFFFF | Unassigned |
*| OCM | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable |
*
* @note
*
* For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1GB,
* region after DDR and before PL is marked as undefined/reserved in translation
* table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 -
* 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved but due to granual size
* of 1MB, it is not possible to define separate regions for them. For region
* 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB
* granual size, it is not possible to define separate region for it
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a ecm 10/20/09 Initial version
* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
* 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device
* instead of strongly-ordered.
* 3.07a asa 07/17/2012 Changed the property of the ".mmu_tbl" section.
* 4.2 pkp 09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved
* and 0xe0000000 - 0xe1ffffff is broken down into
* 0xe0000000 - 0xe02fffff (memory mapped devides)
* 0xe0300000 - 0xe0ffffff (reserved) and
* 0xe1000000 - 0xe1ffffff (NAND)
* 5.2 pkp 06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm
* if DDR is present or not and accordingly generate the
* translation table
* 6.1 pkp 07/11/2016 Corrected comments for memory attributes
* </pre>
*
*
******************************************************************************/
#include "xparameters.h"
.globl MMUTable
.section .mmu_tbl,"a"
MMUTable:
/* Each table entry occupies one 32-bit word and there are
* 4096 entries, so the entire table takes up 16KB.
* Each entry covers a 1MB section.
*/
.set SECT, 0
#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
.set DDR_START, XPAR_PS7_DDR_0_S_AXI_BASEADDR
.set DDR_END, XPAR_PS7_DDR_0_S_AXI_HIGHADDR
.set DDR_SIZE, (DDR_END - DDR_START)+1
.set DDR_REG, DDR_SIZE/0x100000
#else
.set DDR_REG, 0
#endif
.set UNDEF_REG, 0x3FF - DDR_REG
/*0x00000000 - 0x00100000 (cacheable )*/
.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
.set SECT, SECT+0x100000
.rept DDR_REG /* (DDR Cacheable) */
.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept UNDEF_REG /* (unassigned/reserved).
* Generates a translation fault if accessed */
.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
.rept 0x0400 /* 0x40000000 - 0x7fffffff (FPGA slave0) */
.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
.rept 0x0400 /* 0x80000000 - 0xbfffffff (FPGA slave1) */
.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
.rept 0x0200 /* 0xc0000000 - 0xdfffffff (unassigned/reserved).
* Generates a translation fault if accessed */
.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
.rept 0x003 /* 0xe0000000 - 0xe02fffff (Memory mapped devices)
* UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */
.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x0D /* 0xe0300000 - 0xe0ffffff (unassigned/reserved).
* Generates a translation fault if accessed */
.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
.rept 0x0010 /* 0xe1000000 - 0xe1ffffff (NAND) */
.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x0020 /* 0xe2000000 - 0xe3ffffff (NOR) */
.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x0020 /* 0xe4000000 - 0xe5ffffff (SRAM) */
.word SECT + 0xc0e /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x0120 /* 0xe6000000 - 0xf7ffffff (unassigned/reserved).
* Generates a translation fault if accessed */
.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
/* 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and
0xf8f03000 to 0xf8ffffff are reserved but due to granual size of
1MB, it is not possible to define separate regions for them */
.rept 0x0010 /* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */
.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x0030 /* 0xf9000000 - 0xfbffffff (unassigned/reserved).
* Generates a translation fault if accessed */
.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
.rept 0x0020 /* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */
.word SECT + 0xc0a /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b0 */
.set SECT, SECT+0x100000
.endr
.rept 0x001F /* 0xfe000000 - 0xffefffff (unassigned/reserved).
* Generates a translation fault if accessed */
.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
/* 0xfff00000 to 0xfffb0000 is reserved but due to granual size of
1MB, it is not possible to define separate region for it
0xfff00000 - 0xffffffff
256K OCM when mapped to high address space
inner-cacheable */
.word SECT + 0x4c0e /* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */
.set SECT, SECT+0x100000
.end
/**
* @} End of "addtogroup a9_boot_code".
*/ |
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 5,947 | sdk/appsrc/fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/asm_vectors.S | /******************************************************************************
*
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file asm_vectors.s
*
* This file contains the initial vector table for the Cortex A9 processor
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 1.00a ecm/sdm 10/20/09 Initial version
* 3.05a sdm 02/02/12 Save lr when profiling is enabled
* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
* 'xil_errata.h' for errata description
* 4.00a pkp 22/01/14 Modified return addresses for interrupt
* handlers (DataAbortHandler and SVCHandler)
* to fix CR#767251
* 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
* abort and prefetch abort into DataAbortAddr and
* PrefetchAbortAddr for further use to fix CR#854523
* 5.4 pkp 12/03/15 Added handler for undefined exception
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#include "xil_errata.h"
#define __ARM_NEON__ 1
.org 0
.text
.globl _vector_table
.section .vectors
_vector_table:
B _boot
B Undefined
B SVCHandler
B PrefetchAbortHandler
B DataAbortHandler
NOP /* Placeholder for address exception vector*/
B IRQHandler
B FIQHandler
IRQHandler: /* IRQ vector handler */
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/
#ifdef __ARM_NEON__
vpush {d0-d7}
vpush {d16-d31}
vmrs r1, FPSCR
push {r1}
vmrs r1, FPEXC
push {r1}
#endif
#ifdef PROFILING
ldr r2, =prof_pc
subs r3, lr, #0
str r3, [r2]
#endif
bl IRQInterrupt /* IRQ vector */
#ifdef __ARM_NEON__
pop {r1}
vmsr FPEXC, r1
pop {r1}
vmsr FPSCR, r1
vpop {d16-d31}
vpop {d0-d7}
#endif
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #4 /* adjust return */
FIQHandler: /* FIQ vector handler */
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
#ifdef __ARM_NEON__
vpush {d0-d7}
vpush {d16-d31}
vmrs r1, FPSCR
push {r1}
vmrs r1, FPEXC
push {r1}
#endif
FIQLoop:
bl FIQInterrupt /* FIQ vector */
#ifdef __ARM_NEON__
pop {r1}
vmsr FPEXC, r1
pop {r1}
vmsr FPSCR, r1
vpop {d16-d31}
vpop {d0-d7}
#endif
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #4 /* adjust return */
Undefined: /* Undefined handler */
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
ldr r0, =UndefinedExceptionAddr
sub r1, lr, #4
str r1, [r0] /* Store address of instruction causing undefined exception */
bl UndefinedException /* UndefinedException: call C function here */
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
movs pc, lr
SVCHandler: /* SWI handler */
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
tst r0, #0x20 /* check the T bit */
ldrneh r0, [lr,#-2] /* Thumb mode */
bicne r0, r0, #0xff00 /* Thumb mode */
ldreq r0, [lr,#-4] /* ARM mode */
biceq r0, r0, #0xff000000 /* ARM mode */
bl SWInterrupt /* SWInterrupt: call C function here */
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
movs pc, lr /*return to the next instruction after the SWI instruction */
DataAbortHandler: /* Data Abort handler */
#ifdef CONFIG_ARM_ERRATA_775420
dsb
#endif
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
ldr r0, =DataAbortAddr
sub r1, lr, #8
str r1, [r0] /* Stores instruction causing data abort */
bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #8 /* points to the instruction that caused the Data Abort exception */
PrefetchAbortHandler: /* Prefetch Abort handler */
#ifdef CONFIG_ARM_ERRATA_775420
dsb
#endif
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
ldr r0, =PrefetchAbortAddr
sub r1, lr, #4
str r1, [r0] /* Stores instruction causing prefetch abort */
bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #4 /* points to the instruction that caused the Prefetch Abort exception */
.end
|
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 2,950 | sdk/appsrc/fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/cpu_init.S | /******************************************************************************
*
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file cpu_init.s
*
* This file contains CPU specific initialization. Invoked from main CRT
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 1.00a ecm/sdm 10/20/09 Initial version
* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
* 5.0 pkp 12/16/14 removed incorrect initialization of TLB lockdown
* register to fix CR#830580
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
.text
.global __cpu_init
.align 2
__cpu_init:
/* Clear cp15 regs with unknown reset values */
mov r0, #0x0
mcr p15, 0, r0, c5, c0, 0 /* DFSR */
mcr p15, 0, r0, c5, c0, 1 /* IFSR */
mcr p15, 0, r0, c6, c0, 0 /* DFAR */
mcr p15, 0, r0, c6, c0, 2 /* IFAR */
mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */
mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */
mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */
/* Reset and start Cycle Counter */
mov r2, #0x80000000 /* clear overflow */
mcr p15, 0, r2, c9, c12, 3
mov r2, #0xd /* D, C, E */
mcr p15, 0, r2, c9, c12, 0
mov r2, #0x80000000 /* enable cycle counter */
mcr p15, 0, r2, c9, c12, 1
bx lr
.end
|
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 18,784 | sdk/appsrc/fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/boot.S | /******************************************************************************
*
* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file boot.S
*
* @addtogroup a9_boot_code Cortex A9 Processor Boot Code
* @{
* <h2> boot.S </h2>
* The boot code performs minimum configuration which is required for an
* application to run starting from processor's reset state. Below is a
* sequence illustrating what all configuration is performed before control
* reaches to main function.
*
* 1. Program vector table base for exception handling
* 2. Invalidate instruction cache, data cache and TLBs
* 3. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine,
* abort, system)
* 4. Configure MMU with short descriptor translation table format and program
* base address of translation table
* 5. Enable data cache, instruction cache and MMU
* 6. Enable Floating point unit
* 7. Transfer control to _start which clears BSS sections, initializes
* global timer and runs global constructor before jumping to main
* application
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 1.00a ecm/sdm 10/20/09 Initial version
* 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
* register settings.
* 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
* register settings.
* 3.07a asa 07/16/12 Modified the L2 Cache controller settings to improve
* performance. Changed the property of the ".boot"
* section.
* 3.07a sgd 08/21/12 Modified the L2 Cache controller and cp15 Aux Control
* Register settings
* 3.09a sgd 02/06/13 Updated SLCR l2c Ram Control register to a
* value of 0x00020202. Fix for CR 697094 (SI#687034).
* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
* 'xil_errata.h' for errata description
* 4.2 pkp 06/19/14 Enabled asynchronous abort exception
* 5.0 pkp 16/15/14 Modified initialization code to enable scu after
* MMU is enabled
* 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
* caches and TLB, enable MMU and caches, then enable SMP
* bit in ACTLR. L2Cache invalidation and enabling of L2Cache
* is done later.
* 5.4 asa 12/6/15 Added code to initialize SPSR for all relevant modes.
* 6.0 mus 08/04/16 Added code to detect zynq-7000 base silicon configuration and
* attempt to enable dual core behavior on single cpu zynq-7000s
* devices is prevented from corrupting system behavior.
* 6.0 mus 08/24/16 Check CPU core before putting cpu1 to reset for single core
* zynq-7000s devices
*
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#include "xparameters.h"
#include "xil_errata.h"
.globl MMUTable
.global _prestart
.global _boot
.global __stack
.global __irq_stack
.global __supervisor_stack
.global __abort_stack
.global __fiq_stack
.global __undef_stack
.global _vector_table
.set PSS_L2CC_BASE_ADDR, 0xF8F02000
.set PSS_SLCR_BASE_ADDR, 0xF8000000
.set RESERVED, 0x0fffff00
.set TblBase , MMUTable
.set LRemap, 0xFE00000F /* set the base address of the peripheral block as not shared */
.set L2CCWay, (PSS_L2CC_BASE_ADDR + 0x077C) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/
.set L2CCSync, (PSS_L2CC_BASE_ADDR + 0x0730) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/
.set L2CCCrtl, (PSS_L2CC_BASE_ADDR + 0x0100) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/
.set L2CCAuxCrtl, (PSS_L2CC_BASE_ADDR + 0x0104) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/
.set L2CCTAGLatReg, (PSS_L2CC_BASE_ADDR + 0x0108) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/
.set L2CCDataLatReg, (PSS_L2CC_BASE_ADDR + 0x010C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/
.set L2CCIntClear, (PSS_L2CC_BASE_ADDR + 0x0220) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/
.set L2CCIntRaw, (PSS_L2CC_BASE_ADDR + 0x021C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/
.set SLCRlockReg, (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
.set SLCRUnlockReg, (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
.set SLCRL2cRamReg, (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
.set SLCRCPURSTReg, (0xF8000000 + 0x244) /*(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)*/
.set EFUSEStaus, (0xF800D000 + 0x10) /*(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)*/
/* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */
.if SIM_MODE == 1
.set CRValMmuCac, 0b00000000000000 /* Disable IDC, and MMU */
.else
.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */
.endif
.set CRValHiVectorAddr, 0b10000000000000 /* Set the Vector address to high, 0xFFFF0000 */
.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable,
Event monitor bus enable and Way Size (64 KB) */
.set L2CCControl, 0x01 /* Enable L2CC */
.set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */
.set L2CCDataLatency, 0x0121 /* latency for DATA RAM */
.set SLCRlockKey, 0x767B /* SLCR lock key */
.set SLCRUnlockKey, 0xDF0D /* SLCR unlock key */
.set SLCRL2cRamConfig, 0x00020202 /* SLCR L2C ram configuration */
/* Stack Pointer locations for boot code */
.set Undef_stack, __undef_stack
.set FIQ_stack, __fiq_stack
.set Abort_stack, __abort_stack
.set SPV_stack, __supervisor_stack
.set IRQ_stack, __irq_stack
.set SYS_stack, __stack
.set vector_base, _vector_table
.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */
.section .boot,"ax"
/* this initializes the various processor modes */
_prestart:
_boot:
#if XPAR_CPU_ID==0
/* only allow cpu0 through */
mrc p15,0,r1,c0,c0,5
and r1, r1, #0xf
cmp r1, #0
beq CheckEFUSE
EndlessLoop0:
wfe
b EndlessLoop0
CheckEFUSE:
ldr r0,=EFUSEStaus
ldr r1,[r0] /* Read eFuse setting */
ands r1,r1,#0x80 /* Check whether device is having single core */
beq OKToRun
/* single core device, reset cpu1 */
ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
ldr r1,=SLCRUnlockKey /* set unlock key */
str r1, [r0] /* Unlock SLCR */
ldr r0,=SLCRCPURSTReg
ldr r1,[r0] /* Read CPU Software Reset Control register */
orr r1,r1,#0x22
str r1,[r0] /* Reset CPU1 */
ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
ldr r1,=SLCRlockKey /* set lock key */
str r1, [r0] /* lock SLCR */
#elif XPAR_CPU_ID==1
/* only allow cpu1 through */
mrc p15,0,r1,c0,c0,5
and r1, r1, #0xf
cmp r1, #1
beq CheckEFUSE1
b EndlessLoop1
CheckEFUSE1:
ldr r0,=EFUSEStaus
ldr r1,[r0] /* Read eFuse setting */
ands r1,r1,#0x80 /* Check whether device is having single core */
beq OKToRun
EndlessLoop1:
wfe
b EndlessLoop1
#endif
OKToRun:
mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
and r5, r0, #0x00f00000
and r6, r0, #0x0000000f
orr r6, r6, r5, lsr #20-4
#ifdef CONFIG_ARM_ERRATA_742230
cmp r6, #0x22 /* only present up to r2p2 */
mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */
orrle r10, r10, #1 << 4 /* set bit #4 */
mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */
#endif
#ifdef CONFIG_ARM_ERRATA_743622
teq r5, #0x00200000 /* only present in r2p* */
mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */
orreq r10, r10, #1 << 6 /* set bit #6 */
mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */
#endif
/* set VBAR to the _vector_table address in linker script */
ldr r0, =vector_base
mcr p15, 0, r0, c12, c0, 0
/*invalidate scu*/
ldr r7, =0xf8f0000c
ldr r6, =0xffff
str r6, [r7]
/* Invalidate caches and TLBs */
mov r0,#0 /* r0 = 0 */
mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */
bl invalidate_dcache /* invalidate dcache */
/* Disable MMU, if enabled */
mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */
bic r0, r0, #0x1 /* clear bit 0 */
mcr p15, 0, r0, c1, c0, 0 /* write value back */
#ifdef SHAREABLE_DDR
/* Mark the entire DDR memory as shareable */
ldr r3, =0x3ff /* 1024 entries to cover 1G DDR */
ldr r0, =TblBase /* MMU Table address in memory */
ldr r2, =0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
shareable_loop:
str r2, [r0] /* write the entry to MMU table */
add r0, r0, #0x4 /* next entry in the table */
add r2, r2, #0x100000 /* next section */
subs r3, r3, #1
bge shareable_loop /* loop till 1G is covered */
#endif
mrs r0, cpsr /* get the current PSR */
mvn r1, #0x1f /* set up the irq stack pointer */
and r2, r1, r0
orr r2, r2, #0x12 /* IRQ mode */
msr cpsr, r2
ldr r13,=IRQ_stack /* IRQ stack pointer */
bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
msr spsr_fsxc,r2
mrs r0, cpsr /* get the current PSR */
mvn r1, #0x1f /* set up the supervisor stack pointer */
and r2, r1, r0
orr r2, r2, #0x13 /* supervisor mode */
msr cpsr, r2
ldr r13,=SPV_stack /* Supervisor stack pointer */
bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
msr spsr_fsxc,r2
mrs r0, cpsr /* get the current PSR */
mvn r1, #0x1f /* set up the Abort stack pointer */
and r2, r1, r0
orr r2, r2, #0x17 /* Abort mode */
msr cpsr, r2
ldr r13,=Abort_stack /* Abort stack pointer */
bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
msr spsr_fsxc,r2
mrs r0, cpsr /* get the current PSR */
mvn r1, #0x1f /* set up the FIQ stack pointer */
and r2, r1, r0
orr r2, r2, #0x11 /* FIQ mode */
msr cpsr, r2
ldr r13,=FIQ_stack /* FIQ stack pointer */
bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
msr spsr_fsxc,r2
mrs r0, cpsr /* get the current PSR */
mvn r1, #0x1f /* set up the Undefine stack pointer */
and r2, r1, r0
orr r2, r2, #0x1b /* Undefine mode */
msr cpsr, r2
ldr r13,=Undef_stack /* Undefine stack pointer */
bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
msr spsr_fsxc,r2
mrs r0, cpsr /* get the current PSR */
mvn r1, #0x1f /* set up the system stack pointer */
and r2, r1, r0
orr r2, r2, #0x1F /* SYS mode */
msr cpsr, r2
ldr r13,=SYS_stack /* SYS stack pointer */
/*set scu enable bit in scu*/
ldr r7, =0xf8f00000
ldr r0, [r7]
orr r0, r0, #0x1
str r0, [r7]
/* enable MMU and cache */
ldr r0,=TblBase /* Load MMU translation table base */
orr r0, r0, #0x5B /* Outer-cacheable, WB */
mcr 15, 0, r0, c2, c0, 0 /* TTB0 */
mvn r0,#0 /* Load MMU domains -- all ones=manager */
mcr p15,0,r0,c3,c0,0
/* Enable mmu, icahce and dcache */
ldr r0,=CRValMmuCac
mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */
dsb /* dsb allow the MMU to start up */
isb /* isb flush prefetch buffer */
/* Write to ACTLR */
mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
orr r0, r0, #(0x01 << 6) /* set SMP bit */
orr r0, r0, #(0x01 ) /* Cache/TLB maintenance broadcast */
mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
/* Invalidate L2 Cache and enable L2 Cache*/
/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */
#if USE_AMP!=1
ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
mov r1, #0 /* force the disable bit */
str r1, [r0] /* disable the L2 Caches */
ldr r0,=L2CCAuxCrtl /* Load L2CC base address base + Aux control register */
ldr r1,[r0] /* read the register */
ldr r2,=L2CCAuxControl /* set the default bits */
orr r1,r1,r2
str r1, [r0] /* store the Aux Control Register */
ldr r0,=L2CCTAGLatReg /* Load L2CC base address base + TAG Latency address */
ldr r1,=L2CCTAGLatency /* set the latencies for the TAG*/
str r1, [r0] /* store the TAG Latency register Register */
ldr r0,=L2CCDataLatReg /* Load L2CC base address base + Data Latency address */
ldr r1,=L2CCDataLatency /* set the latencies for the Data*/
str r1, [r0] /* store the Data Latency register Register */
ldr r0,=L2CCWay /* Load L2CC base address base + way register*/
ldr r2, =0xFFFF
str r2, [r0] /* force invalidate */
ldr r0,=L2CCSync /* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */
/* Load L2CC base address base + sync register*/
/* poll for completion */
Sync: ldr r1, [r0]
cmp r1, #0
bne Sync
ldr r0,=L2CCIntRaw /* clear pending interrupts */
ldr r1,[r0]
ldr r0,=L2CCIntClear
str r1,[r0]
ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
ldr r1,=SLCRUnlockKey /* set unlock key */
str r1, [r0] /* Unlock SLCR */
ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */
ldr r1,=SLCRL2cRamConfig /* set the configuration value */
str r1, [r0] /* store the L2c Ram Control Register */
ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
ldr r1,=SLCRlockKey /* set lock key */
str r1, [r0] /* lock SLCR */
ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
ldr r1,[r0] /* read the register */
mov r2, #L2CCControl /* set the enable bit */
orr r1,r1,r2
str r1, [r0] /* enable the L2 Caches */
#endif
mov r0, r0
mrc p15, 0, r1, c1, c0, 2 /* read cp access control register (CACR) into r1 */
orr r1, r1, #(0xf << 20) /* enable full access for p10 & p11 */
mcr p15, 0, r1, c1, c0, 2 /* write back into CACR */
/* enable vfp */
fmrx r1, FPEXC /* read the exception register */
orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */
fmxr FPEXC, r1 /* write back the exception register */
mrc p15,0,r0,c1,c0,0 /* flow prediction enable */
orr r0, r0, #(0x01 << 11) /* #0x8000 */
mcr p15,0,r0,c1,c0,0
mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */
orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */
orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */
mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */
mrs r0, cpsr /* get the current PSR */
bic r0, r0, #0x100 /* enable asynchronous abort exception */
msr cpsr_xsf, r0
b _start /* jump to C startup code */
and r0, r0, r0 /* no op */
.Ldone: b .Ldone /* Paranoia: we should never get here */
/*
*************************************************************************
*
* invalidate_dcache - invalidate the entire d-cache by set/way
*
* Note: for Cortex-A9, there is no cp instruction for invalidating
* the whole D-cache. Need to invalidate each line.
*
*************************************************************************
*/
invalidate_dcache:
mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */
ands r3, r0, #0x7000000
mov r3, r3, lsr #23 /* cache level value (naturally aligned) */
beq finished
mov r10, #0 /* start with level 0 */
loop1:
add r2, r10, r10, lsr #1 /* work out 3xcachelevel */
mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */
and r1, r1, #7 /* get those 3 bits alone */
cmp r1, #2
blt skip /* no cache or only instruction cache at this level */
mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */
isb /* isb to sync the change to the CacheSizeID reg */
mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */
and r2, r1, #7 /* extract the line length field */
add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */
ldr r4, =0x3ff
ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */
clz r5, r4 /* r5 is the bit position of the way size increment */
ldr r7, =0x7fff
ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */
loop2:
mov r9, r4 /* r9 working copy of the max way size (right aligned) */
loop3:
orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */
orr r11, r11, r7, lsl r2 /* factor in the index number */
mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
subs r9, r9, #1 /* decrement the way number */
bge loop3
subs r7, r7, #1 /* decrement the index */
bge loop2
skip:
add r10, r10, #2 /* increment the cache number */
cmp r3, r10
bgt loop1
finished:
mov r10, #0 /* swith back to cache level 0 */
mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
dsb
isb
bx lr
.end
/**
* @} End of "addtogroup a9_boot_code".
*/ |
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 1,956 | sdk/appsrc/fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/dummy.S | /******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
.globl dummy_f
#ifdef PROC_MICROBLAZE
.text
.align 2
.ent dummy_f
dummy_f:
nop
.end dummy_f
#endif
#ifdef PROC_PPC
.section .text
.align 2
.type dummy_f@function
dummy_f:
b dummy_f
#endif
#ifdef PROC_CORTEXA9
.section .text
.align 2
.type dummy_f, %function
dummy_f:
b dummy_f
#endif
|
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 2,045 | sdk/appsrc/fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_arm.S | /******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
// based on "ARM Profiling Implementation" from Sourcery G++ Lite for ARM EABI
.globl __gnu_mcount_nc
.type __gnu_mcount_nc, %function
__gnu_mcount_nc:
push {r0, r1, r2, r3, lr}
subs r1, lr, #0 /* callee - current lr */
ldr r0, [sp, #20] /* caller - at the top of the stack */
bl mcount /* when __gnu_mcount_nc is called */
pop {r0, r1, r2, r3, ip, lr}
bx ip
.end __gnu_mcount_nc
|
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 2,255 | sdk/appsrc/fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_ppc.S | /******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
.globl _mcount
#define _MCOUNT_STACK_FRAME 48
.section .text
.align 2
.type _mcount@function
_mcount:
stwu 1, -_MCOUNT_STACK_FRAME(1)
stw 3, 8(1)
stw 4, 12(1)
stw 5, 16(1)
stw 6, 20(1)
stw 7, 24(1)
stw 8, 28(1)
stw 9, 32(1)
stw 10, 36(1)
stw 11, 40(1)
stw 12, 44(1)
mflr 4
stw 4, (_MCOUNT_STACK_FRAME+4)(1)
lwz 3, (_MCOUNT_STACK_FRAME)(1)
lwz 3, 4(3)
bl mcount
lwz 4, (_MCOUNT_STACK_FRAME+4)(1)
mtlr 4
lwz 12, 44(1)
lwz 11, 40(1)
lwz 10, 36(1)
lwz 9, 32(1)
lwz 8, 28(1)
lwz 7, 24(1)
lwz 6, 20(1)
lwz 5, 16(1)
lwz 4, 12(1)
lwz 3, 8(1)
addi 1,1, _MCOUNT_STACK_FRAME
blr
|
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 2,178 | sdk/appsrc/fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_mb.S | /******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
.globl _mcount
.text
.align 2
.ent _mcount
#ifndef PROFILE_NO_GRAPH
_mcount:
addi r1, r1, -48
swi r11, r1, 44
swi r12, r1, 40
swi r5, r1, 36
swi r6, r1, 32
swi r7, r1, 28
swi r8, r1, 24
swi r9, r1, 20
swi r10, r1, 16
swi r15, r1, 12
add r5, r0, r15
brlid r15, mcount
add r6, r0, r16
lwi r11, r1, 44
lwi r12, r1, 40
lwi r5, r1, 36
lwi r6, r1, 32
lwi r7, r1, 28
lwi r8, r1, 24
lwi r9, r1, 20
lwi r10, r1, 16
lwi r15, r1, 12
rtsd r15, 4
addi r1, r1, 48
#endif /* PROFILE_NO_GRAPH */
.end _mcount
|
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 4,428 | sdk/appsrc/game_demo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil-crt0.S | /******************************************************************************
*
* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xil-crt0.S
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a ecm 10/20/09 Initial version
* 3.05a sdm 02/02/12 Added code for profiling
* 3.06a sgd 05/16/12 Added global constructors and cleanup code
* Uart initialization based on compiler flag
* 3.07a sgd 07/05/12 Updated with reset and start Global Timer
* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
* 4.2 pkp 08/04/14 Removed PEEP board related code which contained
* initialization of uart smc nor and sram
* 5.3 pkp 10/07/15 Added support for OpenAMP by not initializing global
* timer when USE_AMP flag is defined
* 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API.
* Now the TTC instance as specified by the user will be
* started.
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#include "bspconfig.h"
.file "xil-crt0.S"
.section ".got2","aw"
.align 2
.text
.Lsbss_start:
.long __sbss_start
.Lsbss_end:
.long __sbss_end
.Lbss_start:
.long __bss_start
.Lbss_end:
.long __bss_end
.Lstack:
.long __stack
.globl _start
_start:
bl __cpu_init /* Initialize the CPU first (BSP provides this) */
mov r0, #0
/* clear sbss */
ldr r1,.Lsbss_start /* calculate beginning of the SBSS */
ldr r2,.Lsbss_end /* calculate end of the SBSS */
.Lloop_sbss:
cmp r1,r2
bge .Lenclsbss /* If no SBSS, no clearing required */
str r0, [r1], #4
b .Lloop_sbss
.Lenclsbss:
/* clear bss */
ldr r1,.Lbss_start /* calculate beginning of the BSS */
ldr r2,.Lbss_end /* calculate end of the BSS */
.Lloop_bss:
cmp r1,r2
bge .Lenclbss /* If no BSS, no clearing required */
str r0, [r1], #4
b .Lloop_bss
.Lenclbss:
/* set stack pointer */
ldr r13,.Lstack /* stack address */
/* Reset and start Global Timer */
mov r0, #0x0
mov r1, #0x0
/* Reset and start Triple Timer Counter */
#if defined SLEEP_TIMER_BASEADDR
bl XTime_StartTTCTimer
#endif
#if USE_AMP != 1
bl XTime_SetTime
#endif
#ifdef PROFILING /* defined in Makefile */
/* Setup profiling stuff */
bl _profile_init
#endif /* PROFILING */
/* run global constructors */
bl __libc_init_array
/* make sure argc and argv are valid */
mov r0, #0
mov r1, #0
/* Let her rip */
bl main
/* Cleanup global constructors */
bl __libc_fini_array
#ifdef PROFILING
/* Cleanup profiling stuff */
bl _profile_clean
#endif /* PROFILING */
/* All done */
bl exit
.Lexit: /* should never get here */
b .Lexit
.Lstart:
.size _start,.Lstart-_start
|
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 9,105 | sdk/appsrc/game_demo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/translation_table.S | /******************************************************************************
*
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file translation_table.s
*
* @addtogroup a9_boot_code
* @{
* <h2> translation_table.S </h2>
* translation_table.S contains a static page table required by MMU for
* cortex-A9. This translation table is flat mapped (input address = output
* address) with default memory attributes defined for zynq architecture. It
* utilizes short descriptor translation table format with each section defining
* 1MB of memory.
*
* The overview of translation table memory attributes is described below.
*
*| | Memory Range | Definition in Translation Table |
*|-----------------------|-------------------------|-----------------------------------|
*| DDR | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable |
*| PL | 0x40000000 - 0xBFFFFFFF | Strongly Ordered |
*| Reserved | 0xC0000000 - 0xDFFFFFFF | Unassigned |
*| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory |
*| Reserved | 0xE0300000 - 0xE0FFFFFF | Unassigned |
*| NAND, NOR | 0xE1000000 - 0xE3FFFFFF | Device memory |
*| SRAM | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable |
*| Reserved | 0xE6000000 - 0xF7FFFFFF | Unassigned |
*| AMBA APB Peripherals | 0xF8000000 - 0xF8FFFFFF | Device Memory |
*| Reserved | 0xF9000000 - 0xFBFFFFFF | Unassigned |
*| Linear QSPI - XIP | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable |
*| Reserved | 0xFE000000 - 0xFFEFFFFF | Unassigned |
*| OCM | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable |
*
* @note
*
* For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1GB,
* region after DDR and before PL is marked as undefined/reserved in translation
* table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 -
* 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved but due to granual size
* of 1MB, it is not possible to define separate regions for them. For region
* 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB
* granual size, it is not possible to define separate region for it
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a ecm 10/20/09 Initial version
* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
* 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device
* instead of strongly-ordered.
* 3.07a asa 07/17/2012 Changed the property of the ".mmu_tbl" section.
* 4.2 pkp 09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved
* and 0xe0000000 - 0xe1ffffff is broken down into
* 0xe0000000 - 0xe02fffff (memory mapped devides)
* 0xe0300000 - 0xe0ffffff (reserved) and
* 0xe1000000 - 0xe1ffffff (NAND)
* 5.2 pkp 06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm
* if DDR is present or not and accordingly generate the
* translation table
* 6.1 pkp 07/11/2016 Corrected comments for memory attributes
* </pre>
*
*
******************************************************************************/
#include "xparameters.h"
.globl MMUTable
.section .mmu_tbl,"a"
MMUTable:
/* Each table entry occupies one 32-bit word and there are
* 4096 entries, so the entire table takes up 16KB.
* Each entry covers a 1MB section.
*/
.set SECT, 0
#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
.set DDR_START, XPAR_PS7_DDR_0_S_AXI_BASEADDR
.set DDR_END, XPAR_PS7_DDR_0_S_AXI_HIGHADDR
.set DDR_SIZE, (DDR_END - DDR_START)+1
.set DDR_REG, DDR_SIZE/0x100000
#else
.set DDR_REG, 0
#endif
.set UNDEF_REG, 0x3FF - DDR_REG
/*0x00000000 - 0x00100000 (cacheable )*/
.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
.set SECT, SECT+0x100000
.rept DDR_REG /* (DDR Cacheable) */
.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept UNDEF_REG /* (unassigned/reserved).
* Generates a translation fault if accessed */
.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
.rept 0x0400 /* 0x40000000 - 0x7fffffff (FPGA slave0) */
.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
.rept 0x0400 /* 0x80000000 - 0xbfffffff (FPGA slave1) */
.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
.rept 0x0200 /* 0xc0000000 - 0xdfffffff (unassigned/reserved).
* Generates a translation fault if accessed */
.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
.rept 0x003 /* 0xe0000000 - 0xe02fffff (Memory mapped devices)
* UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */
.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x0D /* 0xe0300000 - 0xe0ffffff (unassigned/reserved).
* Generates a translation fault if accessed */
.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
.rept 0x0010 /* 0xe1000000 - 0xe1ffffff (NAND) */
.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x0020 /* 0xe2000000 - 0xe3ffffff (NOR) */
.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x0020 /* 0xe4000000 - 0xe5ffffff (SRAM) */
.word SECT + 0xc0e /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x0120 /* 0xe6000000 - 0xf7ffffff (unassigned/reserved).
* Generates a translation fault if accessed */
.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
/* 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and
0xf8f03000 to 0xf8ffffff are reserved but due to granual size of
1MB, it is not possible to define separate regions for them */
.rept 0x0010 /* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */
.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x0030 /* 0xf9000000 - 0xfbffffff (unassigned/reserved).
* Generates a translation fault if accessed */
.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
.rept 0x0020 /* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */
.word SECT + 0xc0a /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b0 */
.set SECT, SECT+0x100000
.endr
.rept 0x001F /* 0xfe000000 - 0xffefffff (unassigned/reserved).
* Generates a translation fault if accessed */
.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
/* 0xfff00000 to 0xfffb0000 is reserved but due to granual size of
1MB, it is not possible to define separate region for it
0xfff00000 - 0xffffffff
256K OCM when mapped to high address space
inner-cacheable */
.word SECT + 0x4c0e /* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */
.set SECT, SECT+0x100000
.end
/**
* @} End of "addtogroup a9_boot_code".
*/ |
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 5,947 | sdk/appsrc/game_demo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/asm_vectors.S | /******************************************************************************
*
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file asm_vectors.s
*
* This file contains the initial vector table for the Cortex A9 processor
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 1.00a ecm/sdm 10/20/09 Initial version
* 3.05a sdm 02/02/12 Save lr when profiling is enabled
* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
* 'xil_errata.h' for errata description
* 4.00a pkp 22/01/14 Modified return addresses for interrupt
* handlers (DataAbortHandler and SVCHandler)
* to fix CR#767251
* 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
* abort and prefetch abort into DataAbortAddr and
* PrefetchAbortAddr for further use to fix CR#854523
* 5.4 pkp 12/03/15 Added handler for undefined exception
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#include "xil_errata.h"
#define __ARM_NEON__ 1
.org 0
.text
.globl _vector_table
.section .vectors
_vector_table:
B _boot
B Undefined
B SVCHandler
B PrefetchAbortHandler
B DataAbortHandler
NOP /* Placeholder for address exception vector*/
B IRQHandler
B FIQHandler
IRQHandler: /* IRQ vector handler */
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/
#ifdef __ARM_NEON__
vpush {d0-d7}
vpush {d16-d31}
vmrs r1, FPSCR
push {r1}
vmrs r1, FPEXC
push {r1}
#endif
#ifdef PROFILING
ldr r2, =prof_pc
subs r3, lr, #0
str r3, [r2]
#endif
bl IRQInterrupt /* IRQ vector */
#ifdef __ARM_NEON__
pop {r1}
vmsr FPEXC, r1
pop {r1}
vmsr FPSCR, r1
vpop {d16-d31}
vpop {d0-d7}
#endif
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #4 /* adjust return */
FIQHandler: /* FIQ vector handler */
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
#ifdef __ARM_NEON__
vpush {d0-d7}
vpush {d16-d31}
vmrs r1, FPSCR
push {r1}
vmrs r1, FPEXC
push {r1}
#endif
FIQLoop:
bl FIQInterrupt /* FIQ vector */
#ifdef __ARM_NEON__
pop {r1}
vmsr FPEXC, r1
pop {r1}
vmsr FPSCR, r1
vpop {d16-d31}
vpop {d0-d7}
#endif
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #4 /* adjust return */
Undefined: /* Undefined handler */
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
ldr r0, =UndefinedExceptionAddr
sub r1, lr, #4
str r1, [r0] /* Store address of instruction causing undefined exception */
bl UndefinedException /* UndefinedException: call C function here */
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
movs pc, lr
SVCHandler: /* SWI handler */
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
tst r0, #0x20 /* check the T bit */
ldrneh r0, [lr,#-2] /* Thumb mode */
bicne r0, r0, #0xff00 /* Thumb mode */
ldreq r0, [lr,#-4] /* ARM mode */
biceq r0, r0, #0xff000000 /* ARM mode */
bl SWInterrupt /* SWInterrupt: call C function here */
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
movs pc, lr /*return to the next instruction after the SWI instruction */
DataAbortHandler: /* Data Abort handler */
#ifdef CONFIG_ARM_ERRATA_775420
dsb
#endif
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
ldr r0, =DataAbortAddr
sub r1, lr, #8
str r1, [r0] /* Stores instruction causing data abort */
bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #8 /* points to the instruction that caused the Data Abort exception */
PrefetchAbortHandler: /* Prefetch Abort handler */
#ifdef CONFIG_ARM_ERRATA_775420
dsb
#endif
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
ldr r0, =PrefetchAbortAddr
sub r1, lr, #4
str r1, [r0] /* Stores instruction causing prefetch abort */
bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #4 /* points to the instruction that caused the Prefetch Abort exception */
.end
|
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 2,950 | sdk/appsrc/game_demo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/cpu_init.S | /******************************************************************************
*
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file cpu_init.s
*
* This file contains CPU specific initialization. Invoked from main CRT
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 1.00a ecm/sdm 10/20/09 Initial version
* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
* 5.0 pkp 12/16/14 removed incorrect initialization of TLB lockdown
* register to fix CR#830580
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
.text
.global __cpu_init
.align 2
__cpu_init:
/* Clear cp15 regs with unknown reset values */
mov r0, #0x0
mcr p15, 0, r0, c5, c0, 0 /* DFSR */
mcr p15, 0, r0, c5, c0, 1 /* IFSR */
mcr p15, 0, r0, c6, c0, 0 /* DFAR */
mcr p15, 0, r0, c6, c0, 2 /* IFAR */
mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */
mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */
mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */
/* Reset and start Cycle Counter */
mov r2, #0x80000000 /* clear overflow */
mcr p15, 0, r2, c9, c12, 3
mov r2, #0xd /* D, C, E */
mcr p15, 0, r2, c9, c12, 0
mov r2, #0x80000000 /* enable cycle counter */
mcr p15, 0, r2, c9, c12, 1
bx lr
.end
|
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 18,784 | sdk/appsrc/game_demo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/boot.S | /******************************************************************************
*
* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file boot.S
*
* @addtogroup a9_boot_code Cortex A9 Processor Boot Code
* @{
* <h2> boot.S </h2>
* The boot code performs minimum configuration which is required for an
* application to run starting from processor's reset state. Below is a
* sequence illustrating what all configuration is performed before control
* reaches to main function.
*
* 1. Program vector table base for exception handling
* 2. Invalidate instruction cache, data cache and TLBs
* 3. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine,
* abort, system)
* 4. Configure MMU with short descriptor translation table format and program
* base address of translation table
* 5. Enable data cache, instruction cache and MMU
* 6. Enable Floating point unit
* 7. Transfer control to _start which clears BSS sections, initializes
* global timer and runs global constructor before jumping to main
* application
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 1.00a ecm/sdm 10/20/09 Initial version
* 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
* register settings.
* 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
* register settings.
* 3.07a asa 07/16/12 Modified the L2 Cache controller settings to improve
* performance. Changed the property of the ".boot"
* section.
* 3.07a sgd 08/21/12 Modified the L2 Cache controller and cp15 Aux Control
* Register settings
* 3.09a sgd 02/06/13 Updated SLCR l2c Ram Control register to a
* value of 0x00020202. Fix for CR 697094 (SI#687034).
* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
* 'xil_errata.h' for errata description
* 4.2 pkp 06/19/14 Enabled asynchronous abort exception
* 5.0 pkp 16/15/14 Modified initialization code to enable scu after
* MMU is enabled
* 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
* caches and TLB, enable MMU and caches, then enable SMP
* bit in ACTLR. L2Cache invalidation and enabling of L2Cache
* is done later.
* 5.4 asa 12/6/15 Added code to initialize SPSR for all relevant modes.
* 6.0 mus 08/04/16 Added code to detect zynq-7000 base silicon configuration and
* attempt to enable dual core behavior on single cpu zynq-7000s
* devices is prevented from corrupting system behavior.
* 6.0 mus 08/24/16 Check CPU core before putting cpu1 to reset for single core
* zynq-7000s devices
*
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#include "xparameters.h"
#include "xil_errata.h"
.globl MMUTable
.global _prestart
.global _boot
.global __stack
.global __irq_stack
.global __supervisor_stack
.global __abort_stack
.global __fiq_stack
.global __undef_stack
.global _vector_table
.set PSS_L2CC_BASE_ADDR, 0xF8F02000
.set PSS_SLCR_BASE_ADDR, 0xF8000000
.set RESERVED, 0x0fffff00
.set TblBase , MMUTable
.set LRemap, 0xFE00000F /* set the base address of the peripheral block as not shared */
.set L2CCWay, (PSS_L2CC_BASE_ADDR + 0x077C) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/
.set L2CCSync, (PSS_L2CC_BASE_ADDR + 0x0730) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/
.set L2CCCrtl, (PSS_L2CC_BASE_ADDR + 0x0100) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/
.set L2CCAuxCrtl, (PSS_L2CC_BASE_ADDR + 0x0104) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/
.set L2CCTAGLatReg, (PSS_L2CC_BASE_ADDR + 0x0108) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/
.set L2CCDataLatReg, (PSS_L2CC_BASE_ADDR + 0x010C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/
.set L2CCIntClear, (PSS_L2CC_BASE_ADDR + 0x0220) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/
.set L2CCIntRaw, (PSS_L2CC_BASE_ADDR + 0x021C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/
.set SLCRlockReg, (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
.set SLCRUnlockReg, (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
.set SLCRL2cRamReg, (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
.set SLCRCPURSTReg, (0xF8000000 + 0x244) /*(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)*/
.set EFUSEStaus, (0xF800D000 + 0x10) /*(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)*/
/* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */
.if SIM_MODE == 1
.set CRValMmuCac, 0b00000000000000 /* Disable IDC, and MMU */
.else
.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */
.endif
.set CRValHiVectorAddr, 0b10000000000000 /* Set the Vector address to high, 0xFFFF0000 */
.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable,
Event monitor bus enable and Way Size (64 KB) */
.set L2CCControl, 0x01 /* Enable L2CC */
.set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */
.set L2CCDataLatency, 0x0121 /* latency for DATA RAM */
.set SLCRlockKey, 0x767B /* SLCR lock key */
.set SLCRUnlockKey, 0xDF0D /* SLCR unlock key */
.set SLCRL2cRamConfig, 0x00020202 /* SLCR L2C ram configuration */
/* Stack Pointer locations for boot code */
.set Undef_stack, __undef_stack
.set FIQ_stack, __fiq_stack
.set Abort_stack, __abort_stack
.set SPV_stack, __supervisor_stack
.set IRQ_stack, __irq_stack
.set SYS_stack, __stack
.set vector_base, _vector_table
.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */
.section .boot,"ax"
/* this initializes the various processor modes */
_prestart:
_boot:
#if XPAR_CPU_ID==0
/* only allow cpu0 through */
mrc p15,0,r1,c0,c0,5
and r1, r1, #0xf
cmp r1, #0
beq CheckEFUSE
EndlessLoop0:
wfe
b EndlessLoop0
CheckEFUSE:
ldr r0,=EFUSEStaus
ldr r1,[r0] /* Read eFuse setting */
ands r1,r1,#0x80 /* Check whether device is having single core */
beq OKToRun
/* single core device, reset cpu1 */
ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
ldr r1,=SLCRUnlockKey /* set unlock key */
str r1, [r0] /* Unlock SLCR */
ldr r0,=SLCRCPURSTReg
ldr r1,[r0] /* Read CPU Software Reset Control register */
orr r1,r1,#0x22
str r1,[r0] /* Reset CPU1 */
ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
ldr r1,=SLCRlockKey /* set lock key */
str r1, [r0] /* lock SLCR */
#elif XPAR_CPU_ID==1
/* only allow cpu1 through */
mrc p15,0,r1,c0,c0,5
and r1, r1, #0xf
cmp r1, #1
beq CheckEFUSE1
b EndlessLoop1
CheckEFUSE1:
ldr r0,=EFUSEStaus
ldr r1,[r0] /* Read eFuse setting */
ands r1,r1,#0x80 /* Check whether device is having single core */
beq OKToRun
EndlessLoop1:
wfe
b EndlessLoop1
#endif
OKToRun:
mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
and r5, r0, #0x00f00000
and r6, r0, #0x0000000f
orr r6, r6, r5, lsr #20-4
#ifdef CONFIG_ARM_ERRATA_742230
cmp r6, #0x22 /* only present up to r2p2 */
mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */
orrle r10, r10, #1 << 4 /* set bit #4 */
mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */
#endif
#ifdef CONFIG_ARM_ERRATA_743622
teq r5, #0x00200000 /* only present in r2p* */
mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */
orreq r10, r10, #1 << 6 /* set bit #6 */
mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */
#endif
/* set VBAR to the _vector_table address in linker script */
ldr r0, =vector_base
mcr p15, 0, r0, c12, c0, 0
/*invalidate scu*/
ldr r7, =0xf8f0000c
ldr r6, =0xffff
str r6, [r7]
/* Invalidate caches and TLBs */
mov r0,#0 /* r0 = 0 */
mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */
bl invalidate_dcache /* invalidate dcache */
/* Disable MMU, if enabled */
mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */
bic r0, r0, #0x1 /* clear bit 0 */
mcr p15, 0, r0, c1, c0, 0 /* write value back */
#ifdef SHAREABLE_DDR
/* Mark the entire DDR memory as shareable */
ldr r3, =0x3ff /* 1024 entries to cover 1G DDR */
ldr r0, =TblBase /* MMU Table address in memory */
ldr r2, =0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
shareable_loop:
str r2, [r0] /* write the entry to MMU table */
add r0, r0, #0x4 /* next entry in the table */
add r2, r2, #0x100000 /* next section */
subs r3, r3, #1
bge shareable_loop /* loop till 1G is covered */
#endif
mrs r0, cpsr /* get the current PSR */
mvn r1, #0x1f /* set up the irq stack pointer */
and r2, r1, r0
orr r2, r2, #0x12 /* IRQ mode */
msr cpsr, r2
ldr r13,=IRQ_stack /* IRQ stack pointer */
bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
msr spsr_fsxc,r2
mrs r0, cpsr /* get the current PSR */
mvn r1, #0x1f /* set up the supervisor stack pointer */
and r2, r1, r0
orr r2, r2, #0x13 /* supervisor mode */
msr cpsr, r2
ldr r13,=SPV_stack /* Supervisor stack pointer */
bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
msr spsr_fsxc,r2
mrs r0, cpsr /* get the current PSR */
mvn r1, #0x1f /* set up the Abort stack pointer */
and r2, r1, r0
orr r2, r2, #0x17 /* Abort mode */
msr cpsr, r2
ldr r13,=Abort_stack /* Abort stack pointer */
bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
msr spsr_fsxc,r2
mrs r0, cpsr /* get the current PSR */
mvn r1, #0x1f /* set up the FIQ stack pointer */
and r2, r1, r0
orr r2, r2, #0x11 /* FIQ mode */
msr cpsr, r2
ldr r13,=FIQ_stack /* FIQ stack pointer */
bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
msr spsr_fsxc,r2
mrs r0, cpsr /* get the current PSR */
mvn r1, #0x1f /* set up the Undefine stack pointer */
and r2, r1, r0
orr r2, r2, #0x1b /* Undefine mode */
msr cpsr, r2
ldr r13,=Undef_stack /* Undefine stack pointer */
bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
msr spsr_fsxc,r2
mrs r0, cpsr /* get the current PSR */
mvn r1, #0x1f /* set up the system stack pointer */
and r2, r1, r0
orr r2, r2, #0x1F /* SYS mode */
msr cpsr, r2
ldr r13,=SYS_stack /* SYS stack pointer */
/*set scu enable bit in scu*/
ldr r7, =0xf8f00000
ldr r0, [r7]
orr r0, r0, #0x1
str r0, [r7]
/* enable MMU and cache */
ldr r0,=TblBase /* Load MMU translation table base */
orr r0, r0, #0x5B /* Outer-cacheable, WB */
mcr 15, 0, r0, c2, c0, 0 /* TTB0 */
mvn r0,#0 /* Load MMU domains -- all ones=manager */
mcr p15,0,r0,c3,c0,0
/* Enable mmu, icahce and dcache */
ldr r0,=CRValMmuCac
mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */
dsb /* dsb allow the MMU to start up */
isb /* isb flush prefetch buffer */
/* Write to ACTLR */
mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
orr r0, r0, #(0x01 << 6) /* set SMP bit */
orr r0, r0, #(0x01 ) /* Cache/TLB maintenance broadcast */
mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
/* Invalidate L2 Cache and enable L2 Cache*/
/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */
#if USE_AMP!=1
ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
mov r1, #0 /* force the disable bit */
str r1, [r0] /* disable the L2 Caches */
ldr r0,=L2CCAuxCrtl /* Load L2CC base address base + Aux control register */
ldr r1,[r0] /* read the register */
ldr r2,=L2CCAuxControl /* set the default bits */
orr r1,r1,r2
str r1, [r0] /* store the Aux Control Register */
ldr r0,=L2CCTAGLatReg /* Load L2CC base address base + TAG Latency address */
ldr r1,=L2CCTAGLatency /* set the latencies for the TAG*/
str r1, [r0] /* store the TAG Latency register Register */
ldr r0,=L2CCDataLatReg /* Load L2CC base address base + Data Latency address */
ldr r1,=L2CCDataLatency /* set the latencies for the Data*/
str r1, [r0] /* store the Data Latency register Register */
ldr r0,=L2CCWay /* Load L2CC base address base + way register*/
ldr r2, =0xFFFF
str r2, [r0] /* force invalidate */
ldr r0,=L2CCSync /* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */
/* Load L2CC base address base + sync register*/
/* poll for completion */
Sync: ldr r1, [r0]
cmp r1, #0
bne Sync
ldr r0,=L2CCIntRaw /* clear pending interrupts */
ldr r1,[r0]
ldr r0,=L2CCIntClear
str r1,[r0]
ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
ldr r1,=SLCRUnlockKey /* set unlock key */
str r1, [r0] /* Unlock SLCR */
ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */
ldr r1,=SLCRL2cRamConfig /* set the configuration value */
str r1, [r0] /* store the L2c Ram Control Register */
ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
ldr r1,=SLCRlockKey /* set lock key */
str r1, [r0] /* lock SLCR */
ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
ldr r1,[r0] /* read the register */
mov r2, #L2CCControl /* set the enable bit */
orr r1,r1,r2
str r1, [r0] /* enable the L2 Caches */
#endif
mov r0, r0
mrc p15, 0, r1, c1, c0, 2 /* read cp access control register (CACR) into r1 */
orr r1, r1, #(0xf << 20) /* enable full access for p10 & p11 */
mcr p15, 0, r1, c1, c0, 2 /* write back into CACR */
/* enable vfp */
fmrx r1, FPEXC /* read the exception register */
orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */
fmxr FPEXC, r1 /* write back the exception register */
mrc p15,0,r0,c1,c0,0 /* flow prediction enable */
orr r0, r0, #(0x01 << 11) /* #0x8000 */
mcr p15,0,r0,c1,c0,0
mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */
orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */
orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */
mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */
mrs r0, cpsr /* get the current PSR */
bic r0, r0, #0x100 /* enable asynchronous abort exception */
msr cpsr_xsf, r0
b _start /* jump to C startup code */
and r0, r0, r0 /* no op */
.Ldone: b .Ldone /* Paranoia: we should never get here */
/*
*************************************************************************
*
* invalidate_dcache - invalidate the entire d-cache by set/way
*
* Note: for Cortex-A9, there is no cp instruction for invalidating
* the whole D-cache. Need to invalidate each line.
*
*************************************************************************
*/
invalidate_dcache:
mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */
ands r3, r0, #0x7000000
mov r3, r3, lsr #23 /* cache level value (naturally aligned) */
beq finished
mov r10, #0 /* start with level 0 */
loop1:
add r2, r10, r10, lsr #1 /* work out 3xcachelevel */
mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */
and r1, r1, #7 /* get those 3 bits alone */
cmp r1, #2
blt skip /* no cache or only instruction cache at this level */
mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */
isb /* isb to sync the change to the CacheSizeID reg */
mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */
and r2, r1, #7 /* extract the line length field */
add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */
ldr r4, =0x3ff
ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */
clz r5, r4 /* r5 is the bit position of the way size increment */
ldr r7, =0x7fff
ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */
loop2:
mov r9, r4 /* r9 working copy of the max way size (right aligned) */
loop3:
orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */
orr r11, r11, r7, lsl r2 /* factor in the index number */
mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
subs r9, r9, #1 /* decrement the way number */
bge loop3
subs r7, r7, #1 /* decrement the index */
bge loop2
skip:
add r10, r10, #2 /* increment the cache number */
cmp r3, r10
bgt loop1
finished:
mov r10, #0 /* swith back to cache level 0 */
mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
dsb
isb
bx lr
.end
/**
* @} End of "addtogroup a9_boot_code".
*/ |
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 1,956 | sdk/appsrc/game_demo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/dummy.S | /******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
.globl dummy_f
#ifdef PROC_MICROBLAZE
.text
.align 2
.ent dummy_f
dummy_f:
nop
.end dummy_f
#endif
#ifdef PROC_PPC
.section .text
.align 2
.type dummy_f@function
dummy_f:
b dummy_f
#endif
#ifdef PROC_CORTEXA9
.section .text
.align 2
.type dummy_f, %function
dummy_f:
b dummy_f
#endif
|
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 2,045 | sdk/appsrc/game_demo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_arm.S | /******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
// based on "ARM Profiling Implementation" from Sourcery G++ Lite for ARM EABI
.globl __gnu_mcount_nc
.type __gnu_mcount_nc, %function
__gnu_mcount_nc:
push {r0, r1, r2, r3, lr}
subs r1, lr, #0 /* callee - current lr */
ldr r0, [sp, #20] /* caller - at the top of the stack */
bl mcount /* when __gnu_mcount_nc is called */
pop {r0, r1, r2, r3, ip, lr}
bx ip
.end __gnu_mcount_nc
|
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 2,255 | sdk/appsrc/game_demo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_ppc.S | /******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
.globl _mcount
#define _MCOUNT_STACK_FRAME 48
.section .text
.align 2
.type _mcount@function
_mcount:
stwu 1, -_MCOUNT_STACK_FRAME(1)
stw 3, 8(1)
stw 4, 12(1)
stw 5, 16(1)
stw 6, 20(1)
stw 7, 24(1)
stw 8, 28(1)
stw 9, 32(1)
stw 10, 36(1)
stw 11, 40(1)
stw 12, 44(1)
mflr 4
stw 4, (_MCOUNT_STACK_FRAME+4)(1)
lwz 3, (_MCOUNT_STACK_FRAME)(1)
lwz 3, 4(3)
bl mcount
lwz 4, (_MCOUNT_STACK_FRAME+4)(1)
mtlr 4
lwz 12, 44(1)
lwz 11, 40(1)
lwz 10, 36(1)
lwz 9, 32(1)
lwz 8, 28(1)
lwz 7, 24(1)
lwz 6, 20(1)
lwz 5, 16(1)
lwz 4, 12(1)
lwz 3, 8(1)
addi 1,1, _MCOUNT_STACK_FRAME
blr
|
Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang | 2,178 | sdk/appsrc/game_demo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_mcount_mb.S | /******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
.globl _mcount
.text
.align 2
.ent _mcount
#ifndef PROFILE_NO_GRAPH
_mcount:
addi r1, r1, -48
swi r11, r1, 44
swi r12, r1, 40
swi r5, r1, 36
swi r6, r1, 32
swi r7, r1, 28
swi r8, r1, 24
swi r9, r1, 20
swi r10, r1, 16
swi r15, r1, 12
add r5, r0, r15
brlid r15, mcount
add r6, r0, r16
lwi r11, r1, 44
lwi r12, r1, 40
lwi r5, r1, 36
lwi r6, r1, 32
lwi r7, r1, 28
lwi r8, r1, 24
lwi r9, r1, 20
lwi r10, r1, 16
lwi r15, r1, 12
rtsd r15, 4
addi r1, r1, 48
#endif /* PROFILE_NO_GRAPH */
.end _mcount
|
Starrynightzyq/Nexys4DDR-ARM-M3-Plate-Recognition | 17,214 | vivado/Arm_sw_repository/CortexM/bsp/standalone_v6_7/src/arm/cortexm3/armcc/boot.S | ;******************************************************************************
;
; Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
;
; Permission is hereby granted, free of charge, to any person obtaining a copy
; of this software and associated documentation files (the "Software"), to deal
; in the Software without restriction, including without limitation the rights
; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
; copies of the Software, and to permit persons to whom the Software is
; furnished to do so, subject to the following conditions:
;
; The above copyright notice and this permission notice shall be included in
; all copies or substantial portions of the Software.
;
; Use of the Software is limited solely to applications:
; (a) running on a Xilinx device, or
; (b) that interact with a Xilinx device through a bus or interconnect.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
; XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
; WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
; OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
; SOFTWARE.
;
; Except as contained in this notice, the name of the Xilinx shall not be used
; in advertising or otherwise to promote the sale, use or other dealings in
; this Software without prior written authorization from Xilinx.
;
;*****************************************************************************
;****************************************************************************
;**
; @file boot.S
;
; This file contains the initial startup code for the Cortex A9 processor
;
; <pre>
; MODIFICATION HISTORY:
;
; Ver Who Date Changes
; ----- ------- -------- ---------------------------------------------------
; 1.00a ecm/sdm 10/20/09 Initial version
; 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
; 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
; register settings.
; 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
; register settings.
; 3.07a sgd 07/05/12 Updated with reset and start Global Timer
; 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
; 4.2 pkp 06/19/14 Enabled asynchronous abort exception
; 4.2 pkp 08/04/14 Removed PEEP board related code which contained
; initialization of uart smc nor and sram
; 5.0 pkp 16/12/14 Modified initialization code to enable scu after
; MMU is enabled and removed incorrect initialization
; of TLB lockdown register to fix CR#830580
; 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
; caches and TLB, enable MMU and caches, then enable SMP
; bit in ACTLR. L2Cache invalidation and enabling of L2Cache
; is done later.
; 5.4 asa 12/06/15 Added code to initialize SPSR for all relevant modes.
; 6.0 mus 04/08/16 Added code to detect zynq-7000 base silicon configuration and
; attempt to enable dual core behavior on single cpu zynq-7000s devices
; is prevented from corrupting system behavior.
; 6.0 mus 24/08/16 Check CPU core before putting cpu1 to reset for single core
; zynq-7000s devices
; 6.6 srm 10/25/17 Added timer configuration using XTime_StartTTCTimer API.
* Now the TTC instance as specified by the user will be
* started.
; </pre>
;
; @note
;
; None.
;
;****************************************************************************
#include "xparameters.h"
#include "xil_errata.h"
#define UART_BAUDRATE 115200
EXPORT _prestart
EXPORT _boot
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
IMPORT |Image$$IRQ_STACK$$ZI$$Limit|
IMPORT |Image$$SPV_STACK$$ZI$$Limit|
IMPORT |Image$$ABORT_STACK$$ZI$$Limit|
IMPORT MMUTable
IMPORT _vector_table
IMPORT __main
IMPORT Xil_ExceptionInit
IMPORT XTime_SetTime
#if defined SLEEP_TIMER_BASEADDR
IMPORT XTime_StartTTCTimer
#endif
PSS_L2CC_BASE_ADDR EQU 0xF8F02000
PSS_SLCR_BASE_ADDR EQU 0xF8000000
L2CCWay EQU (PSS_L2CC_BASE_ADDR + 0x077C) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)
L2CCSync EQU (PSS_L2CC_BASE_ADDR + 0x0730) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)
L2CCCrtl EQU (PSS_L2CC_BASE_ADDR + 0x0100) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)
L2CCAuxCrtl EQU (PSS_L2CC_BASE_ADDR + 0x0104) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)
L2CCTAGLatReg EQU (PSS_L2CC_BASE_ADDR + 0x0108) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)
L2CCDataLatReg EQU (PSS_L2CC_BASE_ADDR + 0x010C) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)
L2CCIntClear EQU (PSS_L2CC_BASE_ADDR + 0x0220) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)
L2CCIntRaw EQU (PSS_L2CC_BASE_ADDR + 0x021C) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)
SLCRlockReg EQU (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
SLCRUnlockReg EQU (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
SLCRL2cRamReg EQU (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
SLCRCPURSTReg EQU (0xF8000000 + 0x244) ;(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)
EFUSEStaus EQU (0xF800D000 + 0x10) ;(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)
SLCRlockKey EQU 0x767B /* SLCR lock key */
SLCRUnlockKey EQU 0xDF0D /* SLCR unlock key */
SLCRL2cRamConfig EQU 0x00020202 /* SLCR L2C ram configuration */
CRValMmuCac EQU 2_01000000000101 ; Enable IDC, and MMU
CRValHiVectorAddr EQU 2_10000000000000 ; Set the Vector address to high, 0xFFFF0000
L2CCAuxControl EQU 0x72360000 ; Enable all prefetching, Way Size (16 KB) and High Priority for SO and Dev Reads Enable
L2CCControl EQU 0x01 ; Enable L2CC
L2CCTAGLatency EQU 0x0111 ; 7 Cycles of latency for TAG RAM
L2CCDataLatency EQU 0x0121 ; 7 Cycles of latency for DATA RAM
FPEXC_EN EQU 0x40000000 ; FPU enable bit, (1 << 30)
AREA |.boot|, CODE
PRESERVE8
; this initializes the various processor modes
_prestart
_boot
#if XPAR_CPU_ID==0
; only allow cp0 through
mrc p15,0,r1,c0,c0,5
and r1, r1, #0xf
cmp r1, #0
beq CheckEFUSE
EndlessLoop0
wfe
b EndlessLoop0
CheckEFUSE
ldr r0,=EFUSEStaus
ldr r1,[r0] ; Read eFuse setting
ands r1,r1,#0x80 ; Check whether device is having single core
beq OKToRun
; Single core device, reset CPU1
ldr r0,=SLCRUnlockReg ; Load SLCR base address base + unlock register
ldr r1,=SLCRUnlockKey ; set unlock key
str r1, [r0] ; Unlock SLCR
ldr r0,=SLCRCPURSTReg
ldr r1,[r0] ; Read CPU Software Reset Control register
orr r1,r1,#0x22
str r1,[r0] ; Reset CPU1
ldr r0,=SLCRlockReg ; Load SLCR base address base + lock register
ldr r1,=SLCRlockKey ; set lock key
str r1, [r0] ; lock SLCR
#elif XPAR_CPU_ID==1
; only allow cpu1 through
mrc p15,0,r1,c0,c0,5
and r1, r1, #0xf
cmp r1, #1
beq CheckEFUSE1
b EndlessLoop1
CheckEFUSE1
ldr r0,=EFUSEStaus
ldr r1,[r0] ; Read eFuse setting
ands r1,r1,#0x80 ; Check whether device is having single core
beq OKToRun
EndlessLoop1
wfe
b EndlessLoop1
#endif
OKToRun
mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
and r5, r0, #0x00f00000
and r6, r0, #0x0000000f
orr r6, r6, r5, lsr #20-4
#ifdef CONFIG_ARM_ERRATA_742230
cmp r6, #0x22 /* only present up to r2p2 */
mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */
orrle r10, r10, #1 << 4 /* set bit #4 */
mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */
#endif
#ifdef CONFIG_ARM_ERRATA_743622
teq r5, #0x00200000 /* only present in r2p* */
mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */
orreq r10, r10, #1 << 6 /* set bit #6 */
mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */
#endif
/* set VBAR to the _vector_table address in scatter file */
ldr r0, =_vector_table
mcr p15, 0, r0, c12, c0, 0
;invalidate scu
ldr r7, =0xf8f0000c
ldr r6, =0xffff
str r6, [r7]
;Invalidate caches and TLBs
mov r0,#0 ; r0 = 0
mcr p15, 0, r0, c8, c7, 0 ; invalidate TLBs
mcr p15, 0, r0, c7, c5, 0 ; invalidate icache
mcr p15, 0, r0, c7, c5, 6 ; Invalidate branch predictor array
bl invalidate_dcache ; invalidate dcache
; Disable MMU, if enabled
mrc p15, 0, r0, c1, c0, 0 ; read CP15 register 1
bic r0, r0, #0x1 ; clear bit 0
mcr p15, 0, r0, c1, c0, 0 ; write value back
#ifdef SHAREABLE_DDR
; Mark the entire DDR memory as shareable
ldr r3, =0x3ff ; 1024 entries to cover 1G DDR
ldr r0, =TblBase ; MMU Table address in memory
ldr r2, =0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1
shareable_loop:
str r2, [r0] ; write the entry to MMU table
add r0, r0, #0x4 ; next entry in the table
add r2, r2, #0x100000 ; next section
subs r3, r3, #1
bge shareable_loop ; loop till 1G is covered
#endif
mrs r0, cpsr ; get the current PSR
mvn r1, #0x1f ; set up the irq stack pointer
and r2, r1, r0
orr r2, r2, #0x12 ; IRQ mode
msr apsr, r2 ; was cpsr, apsr is considered synonym
ldr r13,=|Image$$IRQ_STACK$$ZI$$Limit| ; IRQ stack pointer
bic r2, r2, #(0x1 << 9) ; Set EE bit to little-endian
msr spsr_fsxc,r2
mrs r0, cpsr ; get the current PSR
mvn r1, #0x1f ; set up the supervisor stack pointer
and r2, r1, r0
orr r2, r2, #0x13 ; supervisor mode
msr apsr, r2 ; was cpsr, apsr is considered synonym
ldr r13,=|Image$$SPV_STACK$$ZI$$Limit| ; Supervisor stack pointer
bic r2, r2, #(0x1 << 9) ; Set EE bit to little-endian
msr spsr_fsxc,r2
mrs r0, cpsr ; get the current PSR
mvn r1, #0x1f ; set up the Abort stack pointer
and r2, r1, r0
orr r2, r2, #0x17 ; Abort mode
msr apsr, r2 ; was cpsr, apsr is considered synonym
ldr r13,=|Image$$ABORT_STACK$$ZI$$Limit| ; Abort stack pointer
bic r2, r2, #(0x1 << 9) ; Set EE bit to little-endian
msr spsr_fsxc,r2
mrs r0, cpsr ; get the current PSR
mvn r1, #0x1f ; set up the system stack pointer
and r2, r1, r0
orr r2, r2, #0x1f ; SYS mode
msr apsr, r2 ; was cpsr, apsr is considered synonym
ldr r13,=|Image$$ARM_LIB_STACK$$ZI$$Limit| ; SYS stack pointer
;set scu enable bit in scu
ldr r7, =0xf8f00000
ldr r0, [r7]
orr r0, r0, #0x1
str r0, [r7]
; enable MMU and cache
ldr r0,=MMUTable ; Load MMU translation table base
orr r0, r0, #0x5B ; Outer-cacheable, WB
mcr p15, 0, r0, c2, c0, 0 ; TTB0
mvn r0,#0
mcr p15,0,r0,c3,c0,0
; Enable mmu, icahce and dcache
ldr r0,=CRValMmuCac
mcr p15,0,r0,c1,c0,0 ; Enable cache and MMU
dsb ; dsb allow the MMU to start up
isb ; isb flush prefetch buffer
; Write to ACTLR
mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR
orr r0, r0, #(0x01 << 6) ; SMP bit
orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast
mcr p15, 0,r0, c1, c0, 1 ; Write ACTLR
; Invalidate L2 Cache and initialize L2 Cache
; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux)
#if USE_AMP!=1
ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
mov r1, #0 ; force the disable bit
str r1, [r0] ; disable the L2 Caches
ldr r0,=L2CCAuxCrtl ; Load L2CC base address base + Aux control register
ldr r1,[r0] ; read the register
ldr r2,=L2CCAuxControl ; set the default bits
orr r1,r1,r2
str r1, [r0] ; store the Aux Control Register
ldr r0,=L2CCTAGLatReg ; Load L2CC base address base + TAG Latency address
ldr r1,=L2CCTAGLatency ; set the latencies for the TAG
str r1, [r0] ; store the TAG Latency register Register
ldr r0,=L2CCDataLatReg ; Load L2CC base address base + Data Latency address
ldr r1,=L2CCDataLatency ; set the latencies for the Data
str r1, [r0] ; store the Data Latency register Register
ldr r0,=L2CCWay ; Load L2CC base address base + way register
ldr r2, =0xFFFF
str r2, [r0] ; force invalidate
ldr r0,=L2CCSync ; need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET
; Load L2CC base address base + sync register
; poll for completion
Sync
ldr r1, [r0]
cmp r1, #0
bne Sync
ldr r0,=L2CCIntRaw ; clear pending interrupts
ldr r1,[r0]
ldr r0,=L2CCIntClear
str r1,[r0]
ldr r0,=SLCRUnlockReg ;Load SLCR base address base + unlock register
ldr r1,=SLCRUnlockKey ;set unlock key
str r1, [r0] ;Unlock SLCR
ldr r0,=SLCRL2cRamReg ;Load SLCR base address base + l2c Ram Control register
ldr r1,=SLCRL2cRamConfig ;set the configuration value
str r1, [r0] ;store the L2c Ram Control Register
ldr r0,=SLCRlockReg ;Load SLCR base address base + lock register
ldr r1,=SLCRlockKey ;set lock key
str r1, [r0] ;lock SLCR
ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
ldr r1,[r0] ; read the register
mov r2, #L2CCControl ; set the enable bit
orr r1,r1,r2
str r1, [r0] ; enable the L2 Caches
#endif
mov r0, r0
mrc p15, 0, r1, c1, c0, 2 ; read cp access control register (CACR) into r1
orr r1, r1, #(0xf << 20) ; enable full access for p10 & p11
mcr p15, 0, r1, c1, c0, 2 ; write back into CACR
; enable vfp
fmrx r1, FPEXC ; read the exception register
orr r1,r1, #FPEXC_EN ; set VFP enable bit, leave the others in orig state
fmxr FPEXC, r1 ; write back the exception register
mrc p15, 0, r0, c1, c0, 0 ; flow prediction enable
orr r0, r0, #(0x01 << 11) ; #0x8000
mcr p15,0,r0,c1,c0,0
mrc p15, 0, r0, c1, c0, 1 ; read Auxiliary Control Register
orr r0, r0, #(0x1 << 2) ; enable Dside prefetch
orr r0, r0, #(0x1 << 1) ; enable L2 prefetch
mcr p15, 0, r0, c1, c0, 1 ; write Auxiliary Control Register
mrs r0, cpsr /* get the current PSR */
bic r0, r0, #0x100 /* enable asynchronous abort exception */
msr cpsr_xsf, r0
; Clear cp15 regs with unknown reset values
mov r0, #0x0
mcr p15, 0, r0, c5, c0, 0 ; DFSR
mcr p15, 0, r0, c5, c0, 1 ; IFSR
mcr p15, 0, r0, c6, c0, 0 ; DFAR
mcr p15, 0, r0, c6, c0, 2 ; IFAR
mcr p15, 0, r0, c9, c13, 2 ; PMXEVCNTR
mcr p15, 0, r0, c13, c0, 2 ; TPIDRURW
mcr p15, 0, r0, c13, c0, 3 ; TPIDRURO
; Reset and start Cycle Counter
mov r2, #0x80000000 ; clear overflow
mcr p15, 0, r2, c9, c12, 3
mov r2, #0xd ; D, C, E
mcr p15, 0, r2, c9, c12, 0
mov r2, #0x80000000 ; enable cycle counter
mcr p15, 0, r2, c9, c12, 1
; Reset and start Global Timer
mov r0, #0x0
mov r1, #0x0
bl XTime_SetTime
; Reset and start Triple Timer counter
#if defined SLEEP_TIMER_BASEADDR
bl XTime_StartTTCTimer
#endif
#ifdef PROFILING /* defined in Makefile */
/* Setup profiling stuff */
bl _profile_init
#endif /* PROFILING */
; make sure argc and argv are valid
mov r0, #0
mov r1, #0
b __main ; jump to C startup code
and r0, r0, r0 ; no op
Ldone b Ldone ; Paranoia: we should never get here
; *************************************************************************
; *
; * invalidate_dcache - invalidate the entire d-cache by set/way
; *
; * Note: for Cortex-A9, there is no cp instruction for invalidating
; * the whole D-cache. Need to invalidate each line.
; *
; *************************************************************************
invalidate_dcache
mrc p15, 1, r0, c0, c0, 1 ; read CLIDR
ands r3, r0, #0x7000000
mov r3, r3, lsr #23 ; cache level value (naturally aligned)
beq finished
mov r10, #0 ; start with level 0
loop1
add r2, r10, r10, lsr #1 ; work out 3xcachelevel
mov r1, r0, lsr r2 ; bottom 3 bits are the Cache type for this level
and r1, r1, #7 ; get those 3 bits alone
cmp r1, #2
blt skip ; no cache or only instruction cache at this level
mcr p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
isb ; isb to sync the change to the CacheSizeID reg
mrc p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register
and r2, r1, #7 ; extract the line length field
add r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
ldr r4, =0x3ff
ands r4, r4, r1, lsr #3 ; r4 is the max number on the way size (right aligned)
clz r5, r4 ; r5 is the bit position of the way size increment
ldr r7, =0x7fff
ands r7, r7, r1, lsr #13 ; r7 is the max number of the index size (right aligned)
loop2
mov r9, r4 ; r9 working copy of the max way size (right aligned)
loop3
orr r11, r10, r9, lsl r5 ; factor in the way number and cache number into r11
orr r11, r11, r7, lsl r2 ; factor in the index number
mcr p15, 0, r11, c7, c6, 2 ; invalidate by set/way
subs r9, r9, #1 ; decrement the way number
bge loop3
subs r7, r7, #1 ; decrement the index
bge loop2
skip
add r10, r10, #2 ; increment the cache number
cmp r3, r10
bgt loop1
finished
mov r10, #0 ; swith back to cache level 0
mcr p15, 2, r10, c0, c0, 0 ; select current cache level in cssr
isb
bx lr
END
|
Starrynightzyq/Nexys4DDR-ARM-M3-Plate-Recognition | 17,214 | vivado/Arm_sw_repository/CortexM/bsp/standalone_v6_7/src/arm/cortexm1/armcc/boot.S | ;******************************************************************************
;
; Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
;
; Permission is hereby granted, free of charge, to any person obtaining a copy
; of this software and associated documentation files (the "Software"), to deal
; in the Software without restriction, including without limitation the rights
; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
; copies of the Software, and to permit persons to whom the Software is
; furnished to do so, subject to the following conditions:
;
; The above copyright notice and this permission notice shall be included in
; all copies or substantial portions of the Software.
;
; Use of the Software is limited solely to applications:
; (a) running on a Xilinx device, or
; (b) that interact with a Xilinx device through a bus or interconnect.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
; XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
; WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
; OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
; SOFTWARE.
;
; Except as contained in this notice, the name of the Xilinx shall not be used
; in advertising or otherwise to promote the sale, use or other dealings in
; this Software without prior written authorization from Xilinx.
;
;*****************************************************************************
;****************************************************************************
;**
; @file boot.S
;
; This file contains the initial startup code for the Cortex A9 processor
;
; <pre>
; MODIFICATION HISTORY:
;
; Ver Who Date Changes
; ----- ------- -------- ---------------------------------------------------
; 1.00a ecm/sdm 10/20/09 Initial version
; 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
; 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
; register settings.
; 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
; register settings.
; 3.07a sgd 07/05/12 Updated with reset and start Global Timer
; 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
; 4.2 pkp 06/19/14 Enabled asynchronous abort exception
; 4.2 pkp 08/04/14 Removed PEEP board related code which contained
; initialization of uart smc nor and sram
; 5.0 pkp 16/12/14 Modified initialization code to enable scu after
; MMU is enabled and removed incorrect initialization
; of TLB lockdown register to fix CR#830580
; 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
; caches and TLB, enable MMU and caches, then enable SMP
; bit in ACTLR. L2Cache invalidation and enabling of L2Cache
; is done later.
; 5.4 asa 12/06/15 Added code to initialize SPSR for all relevant modes.
; 6.0 mus 04/08/16 Added code to detect zynq-7000 base silicon configuration and
; attempt to enable dual core behavior on single cpu zynq-7000s devices
; is prevented from corrupting system behavior.
; 6.0 mus 24/08/16 Check CPU core before putting cpu1 to reset for single core
; zynq-7000s devices
; 6.6 srm 10/25/17 Added timer configuration using XTime_StartTTCTimer API.
* Now the TTC instance as specified by the user will be
* started.
; </pre>
;
; @note
;
; None.
;
;****************************************************************************
#include "xparameters.h"
#include "xil_errata.h"
#define UART_BAUDRATE 115200
EXPORT _prestart
EXPORT _boot
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
IMPORT |Image$$IRQ_STACK$$ZI$$Limit|
IMPORT |Image$$SPV_STACK$$ZI$$Limit|
IMPORT |Image$$ABORT_STACK$$ZI$$Limit|
IMPORT MMUTable
IMPORT _vector_table
IMPORT __main
IMPORT Xil_ExceptionInit
IMPORT XTime_SetTime
#if defined SLEEP_TIMER_BASEADDR
IMPORT XTime_StartTTCTimer
#endif
PSS_L2CC_BASE_ADDR EQU 0xF8F02000
PSS_SLCR_BASE_ADDR EQU 0xF8000000
L2CCWay EQU (PSS_L2CC_BASE_ADDR + 0x077C) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)
L2CCSync EQU (PSS_L2CC_BASE_ADDR + 0x0730) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)
L2CCCrtl EQU (PSS_L2CC_BASE_ADDR + 0x0100) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)
L2CCAuxCrtl EQU (PSS_L2CC_BASE_ADDR + 0x0104) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)
L2CCTAGLatReg EQU (PSS_L2CC_BASE_ADDR + 0x0108) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)
L2CCDataLatReg EQU (PSS_L2CC_BASE_ADDR + 0x010C) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)
L2CCIntClear EQU (PSS_L2CC_BASE_ADDR + 0x0220) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)
L2CCIntRaw EQU (PSS_L2CC_BASE_ADDR + 0x021C) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)
SLCRlockReg EQU (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
SLCRUnlockReg EQU (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
SLCRL2cRamReg EQU (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
SLCRCPURSTReg EQU (0xF8000000 + 0x244) ;(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)
EFUSEStaus EQU (0xF800D000 + 0x10) ;(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)
SLCRlockKey EQU 0x767B /* SLCR lock key */
SLCRUnlockKey EQU 0xDF0D /* SLCR unlock key */
SLCRL2cRamConfig EQU 0x00020202 /* SLCR L2C ram configuration */
CRValMmuCac EQU 2_01000000000101 ; Enable IDC, and MMU
CRValHiVectorAddr EQU 2_10000000000000 ; Set the Vector address to high, 0xFFFF0000
L2CCAuxControl EQU 0x72360000 ; Enable all prefetching, Way Size (16 KB) and High Priority for SO and Dev Reads Enable
L2CCControl EQU 0x01 ; Enable L2CC
L2CCTAGLatency EQU 0x0111 ; 7 Cycles of latency for TAG RAM
L2CCDataLatency EQU 0x0121 ; 7 Cycles of latency for DATA RAM
FPEXC_EN EQU 0x40000000 ; FPU enable bit, (1 << 30)
AREA |.boot|, CODE
PRESERVE8
; this initializes the various processor modes
_prestart
_boot
#if XPAR_CPU_ID==0
; only allow cp0 through
mrc p15,0,r1,c0,c0,5
and r1, r1, #0xf
cmp r1, #0
beq CheckEFUSE
EndlessLoop0
wfe
b EndlessLoop0
CheckEFUSE
ldr r0,=EFUSEStaus
ldr r1,[r0] ; Read eFuse setting
ands r1,r1,#0x80 ; Check whether device is having single core
beq OKToRun
; Single core device, reset CPU1
ldr r0,=SLCRUnlockReg ; Load SLCR base address base + unlock register
ldr r1,=SLCRUnlockKey ; set unlock key
str r1, [r0] ; Unlock SLCR
ldr r0,=SLCRCPURSTReg
ldr r1,[r0] ; Read CPU Software Reset Control register
orr r1,r1,#0x22
str r1,[r0] ; Reset CPU1
ldr r0,=SLCRlockReg ; Load SLCR base address base + lock register
ldr r1,=SLCRlockKey ; set lock key
str r1, [r0] ; lock SLCR
#elif XPAR_CPU_ID==1
; only allow cpu1 through
mrc p15,0,r1,c0,c0,5
and r1, r1, #0xf
cmp r1, #1
beq CheckEFUSE1
b EndlessLoop1
CheckEFUSE1
ldr r0,=EFUSEStaus
ldr r1,[r0] ; Read eFuse setting
ands r1,r1,#0x80 ; Check whether device is having single core
beq OKToRun
EndlessLoop1
wfe
b EndlessLoop1
#endif
OKToRun
mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
and r5, r0, #0x00f00000
and r6, r0, #0x0000000f
orr r6, r6, r5, lsr #20-4
#ifdef CONFIG_ARM_ERRATA_742230
cmp r6, #0x22 /* only present up to r2p2 */
mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */
orrle r10, r10, #1 << 4 /* set bit #4 */
mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */
#endif
#ifdef CONFIG_ARM_ERRATA_743622
teq r5, #0x00200000 /* only present in r2p* */
mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */
orreq r10, r10, #1 << 6 /* set bit #6 */
mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */
#endif
/* set VBAR to the _vector_table address in scatter file */
ldr r0, =_vector_table
mcr p15, 0, r0, c12, c0, 0
;invalidate scu
ldr r7, =0xf8f0000c
ldr r6, =0xffff
str r6, [r7]
;Invalidate caches and TLBs
mov r0,#0 ; r0 = 0
mcr p15, 0, r0, c8, c7, 0 ; invalidate TLBs
mcr p15, 0, r0, c7, c5, 0 ; invalidate icache
mcr p15, 0, r0, c7, c5, 6 ; Invalidate branch predictor array
bl invalidate_dcache ; invalidate dcache
; Disable MMU, if enabled
mrc p15, 0, r0, c1, c0, 0 ; read CP15 register 1
bic r0, r0, #0x1 ; clear bit 0
mcr p15, 0, r0, c1, c0, 0 ; write value back
#ifdef SHAREABLE_DDR
; Mark the entire DDR memory as shareable
ldr r3, =0x3ff ; 1024 entries to cover 1G DDR
ldr r0, =TblBase ; MMU Table address in memory
ldr r2, =0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1
shareable_loop:
str r2, [r0] ; write the entry to MMU table
add r0, r0, #0x4 ; next entry in the table
add r2, r2, #0x100000 ; next section
subs r3, r3, #1
bge shareable_loop ; loop till 1G is covered
#endif
mrs r0, cpsr ; get the current PSR
mvn r1, #0x1f ; set up the irq stack pointer
and r2, r1, r0
orr r2, r2, #0x12 ; IRQ mode
msr apsr, r2 ; was cpsr, apsr is considered synonym
ldr r13,=|Image$$IRQ_STACK$$ZI$$Limit| ; IRQ stack pointer
bic r2, r2, #(0x1 << 9) ; Set EE bit to little-endian
msr spsr_fsxc,r2
mrs r0, cpsr ; get the current PSR
mvn r1, #0x1f ; set up the supervisor stack pointer
and r2, r1, r0
orr r2, r2, #0x13 ; supervisor mode
msr apsr, r2 ; was cpsr, apsr is considered synonym
ldr r13,=|Image$$SPV_STACK$$ZI$$Limit| ; Supervisor stack pointer
bic r2, r2, #(0x1 << 9) ; Set EE bit to little-endian
msr spsr_fsxc,r2
mrs r0, cpsr ; get the current PSR
mvn r1, #0x1f ; set up the Abort stack pointer
and r2, r1, r0
orr r2, r2, #0x17 ; Abort mode
msr apsr, r2 ; was cpsr, apsr is considered synonym
ldr r13,=|Image$$ABORT_STACK$$ZI$$Limit| ; Abort stack pointer
bic r2, r2, #(0x1 << 9) ; Set EE bit to little-endian
msr spsr_fsxc,r2
mrs r0, cpsr ; get the current PSR
mvn r1, #0x1f ; set up the system stack pointer
and r2, r1, r0
orr r2, r2, #0x1f ; SYS mode
msr apsr, r2 ; was cpsr, apsr is considered synonym
ldr r13,=|Image$$ARM_LIB_STACK$$ZI$$Limit| ; SYS stack pointer
;set scu enable bit in scu
ldr r7, =0xf8f00000
ldr r0, [r7]
orr r0, r0, #0x1
str r0, [r7]
; enable MMU and cache
ldr r0,=MMUTable ; Load MMU translation table base
orr r0, r0, #0x5B ; Outer-cacheable, WB
mcr p15, 0, r0, c2, c0, 0 ; TTB0
mvn r0,#0
mcr p15,0,r0,c3,c0,0
; Enable mmu, icahce and dcache
ldr r0,=CRValMmuCac
mcr p15,0,r0,c1,c0,0 ; Enable cache and MMU
dsb ; dsb allow the MMU to start up
isb ; isb flush prefetch buffer
; Write to ACTLR
mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR
orr r0, r0, #(0x01 << 6) ; SMP bit
orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast
mcr p15, 0,r0, c1, c0, 1 ; Write ACTLR
; Invalidate L2 Cache and initialize L2 Cache
; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux)
#if USE_AMP!=1
ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
mov r1, #0 ; force the disable bit
str r1, [r0] ; disable the L2 Caches
ldr r0,=L2CCAuxCrtl ; Load L2CC base address base + Aux control register
ldr r1,[r0] ; read the register
ldr r2,=L2CCAuxControl ; set the default bits
orr r1,r1,r2
str r1, [r0] ; store the Aux Control Register
ldr r0,=L2CCTAGLatReg ; Load L2CC base address base + TAG Latency address
ldr r1,=L2CCTAGLatency ; set the latencies for the TAG
str r1, [r0] ; store the TAG Latency register Register
ldr r0,=L2CCDataLatReg ; Load L2CC base address base + Data Latency address
ldr r1,=L2CCDataLatency ; set the latencies for the Data
str r1, [r0] ; store the Data Latency register Register
ldr r0,=L2CCWay ; Load L2CC base address base + way register
ldr r2, =0xFFFF
str r2, [r0] ; force invalidate
ldr r0,=L2CCSync ; need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET
; Load L2CC base address base + sync register
; poll for completion
Sync
ldr r1, [r0]
cmp r1, #0
bne Sync
ldr r0,=L2CCIntRaw ; clear pending interrupts
ldr r1,[r0]
ldr r0,=L2CCIntClear
str r1,[r0]
ldr r0,=SLCRUnlockReg ;Load SLCR base address base + unlock register
ldr r1,=SLCRUnlockKey ;set unlock key
str r1, [r0] ;Unlock SLCR
ldr r0,=SLCRL2cRamReg ;Load SLCR base address base + l2c Ram Control register
ldr r1,=SLCRL2cRamConfig ;set the configuration value
str r1, [r0] ;store the L2c Ram Control Register
ldr r0,=SLCRlockReg ;Load SLCR base address base + lock register
ldr r1,=SLCRlockKey ;set lock key
str r1, [r0] ;lock SLCR
ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
ldr r1,[r0] ; read the register
mov r2, #L2CCControl ; set the enable bit
orr r1,r1,r2
str r1, [r0] ; enable the L2 Caches
#endif
mov r0, r0
mrc p15, 0, r1, c1, c0, 2 ; read cp access control register (CACR) into r1
orr r1, r1, #(0xf << 20) ; enable full access for p10 & p11
mcr p15, 0, r1, c1, c0, 2 ; write back into CACR
; enable vfp
fmrx r1, FPEXC ; read the exception register
orr r1,r1, #FPEXC_EN ; set VFP enable bit, leave the others in orig state
fmxr FPEXC, r1 ; write back the exception register
mrc p15, 0, r0, c1, c0, 0 ; flow prediction enable
orr r0, r0, #(0x01 << 11) ; #0x8000
mcr p15,0,r0,c1,c0,0
mrc p15, 0, r0, c1, c0, 1 ; read Auxiliary Control Register
orr r0, r0, #(0x1 << 2) ; enable Dside prefetch
orr r0, r0, #(0x1 << 1) ; enable L2 prefetch
mcr p15, 0, r0, c1, c0, 1 ; write Auxiliary Control Register
mrs r0, cpsr /* get the current PSR */
bic r0, r0, #0x100 /* enable asynchronous abort exception */
msr cpsr_xsf, r0
; Clear cp15 regs with unknown reset values
mov r0, #0x0
mcr p15, 0, r0, c5, c0, 0 ; DFSR
mcr p15, 0, r0, c5, c0, 1 ; IFSR
mcr p15, 0, r0, c6, c0, 0 ; DFAR
mcr p15, 0, r0, c6, c0, 2 ; IFAR
mcr p15, 0, r0, c9, c13, 2 ; PMXEVCNTR
mcr p15, 0, r0, c13, c0, 2 ; TPIDRURW
mcr p15, 0, r0, c13, c0, 3 ; TPIDRURO
; Reset and start Cycle Counter
mov r2, #0x80000000 ; clear overflow
mcr p15, 0, r2, c9, c12, 3
mov r2, #0xd ; D, C, E
mcr p15, 0, r2, c9, c12, 0
mov r2, #0x80000000 ; enable cycle counter
mcr p15, 0, r2, c9, c12, 1
; Reset and start Global Timer
mov r0, #0x0
mov r1, #0x0
bl XTime_SetTime
; Reset and start Triple Timer counter
#if defined SLEEP_TIMER_BASEADDR
bl XTime_StartTTCTimer
#endif
#ifdef PROFILING /* defined in Makefile */
/* Setup profiling stuff */
bl _profile_init
#endif /* PROFILING */
; make sure argc and argv are valid
mov r0, #0
mov r1, #0
b __main ; jump to C startup code
and r0, r0, r0 ; no op
Ldone b Ldone ; Paranoia: we should never get here
; *************************************************************************
; *
; * invalidate_dcache - invalidate the entire d-cache by set/way
; *
; * Note: for Cortex-A9, there is no cp instruction for invalidating
; * the whole D-cache. Need to invalidate each line.
; *
; *************************************************************************
invalidate_dcache
mrc p15, 1, r0, c0, c0, 1 ; read CLIDR
ands r3, r0, #0x7000000
mov r3, r3, lsr #23 ; cache level value (naturally aligned)
beq finished
mov r10, #0 ; start with level 0
loop1
add r2, r10, r10, lsr #1 ; work out 3xcachelevel
mov r1, r0, lsr r2 ; bottom 3 bits are the Cache type for this level
and r1, r1, #7 ; get those 3 bits alone
cmp r1, #2
blt skip ; no cache or only instruction cache at this level
mcr p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
isb ; isb to sync the change to the CacheSizeID reg
mrc p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register
and r2, r1, #7 ; extract the line length field
add r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
ldr r4, =0x3ff
ands r4, r4, r1, lsr #3 ; r4 is the max number on the way size (right aligned)
clz r5, r4 ; r5 is the bit position of the way size increment
ldr r7, =0x7fff
ands r7, r7, r1, lsr #13 ; r7 is the max number of the index size (right aligned)
loop2
mov r9, r4 ; r9 working copy of the max way size (right aligned)
loop3
orr r11, r10, r9, lsl r5 ; factor in the way number and cache number into r11
orr r11, r11, r7, lsl r2 ; factor in the index number
mcr p15, 0, r11, c7, c6, 2 ; invalidate by set/way
subs r9, r9, #1 ; decrement the way number
bge loop3
subs r7, r7, #1 ; decrement the index
bge loop2
skip
add r10, r10, #2 ; increment the cache number
cmp r3, r10
bgt loop1
finished
mov r10, #0 ; swith back to cache level 0
mcr p15, 2, r10, c0, c0, 0 ; select current cache level in cssr
isb
bx lr
END
|
Starrynightzyq/Nexys4DDR-ARM-M3-Plate-Recognition | 29,171 | docs/参考文献/ATK-OV5640摄像头模块/2，程序源码/（库函数版本，适合探索者STM32F4开发板）扩展实验15B OV5640照相机实验/CORE/startup_stm32f40_41xxx.s | ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.4.0
;* @date : 04-August-2014
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
sysprog21/classify-rv32i | 1,326 | coverage-src/initialize_zero.s | .globl initialize_zero
.text
# =======================================================
# FUNCTION: Initialize a zero array with the given length
# Arguments:
# a0 (int) size of the array
# Returns:
# a0 (int*) is the pointer to the zero array
# Exceptions:
# - If the length of the array is less than 1,
# this function terminates the program with error code 36.
# - If malloc fails, this function terminats the program with exit code 26.
# =======================================================
initialize_zero:
# Checking to see if the stride and length is greater than 0.
li t0 1
blt a0 t0 exit_bad_len
addi sp sp -8
sw a0 0(sp)
sw ra 4(sp)
slli a0 a0 2 # get how many bytes to allocate
jal malloc
beqz a0 error_malloc # exit if malloc failed
lw a1 0(sp) # load back a0
li t0 0 # t0 is the loop index "i"
loop_start:
# Check loop end condition
beq t0 a1 loop_end
# Get addresses of "i"th element of both arrays
slli t2 t0 2 # t2 = index * sizeof(int)
add t3 t2 a0
# Save 0 to the "i"th element of both arrays
sw x0 0(t3)
# Increment loop index and array pointers
addi t0 t0 1
j loop_start
loop_end:
lw ra 4(sp)
addi sp sp 8
jr ra
exit_bad_len:
li a0 36
j exit
error_malloc:
li a0 26
j exit
|
sysprog21/classify-rv32i | 1,578 | coverage-src/abs_loss.s | .globl abs_loss
.text
# =======================================================
# FUNCTION: Get the absolute difference of 2 int arrays,
# store in a third array and compute the sum
# Arguments:
# a0 (int*) is the pointer to the start of arr0
# a1 (int*) is the pointer to the start of arr1
# a2 (int) is the length of the arrays
# a3 (int*) is the pointer to the start of the loss array
# Returns:
# a0 (int) is the sum of the absolute loss
# Exceptions:
# - If the length of the array is less than 1,
# this function terminates the program with error code 36.
# =======================================================
abs_loss:
# Checking to see if the stride and length is greater than 0.
li t0 1
blt a2 t0 exit_bad_len
li t0 0 # t0 is the loop index "i"
li t1 0 # t1 is the running total loss
loop_start:
# Check loop end condition
beq t0 a2 loop_end
# Get addresses of "i"th element of both arrays
slli t2 t0 2 # t2 = index * sizeof(int)
add t3 t2 a0
add t4 t2 a1
# Load "i"th element of both arrays
lw t5 0(t3)
lw t6 0(t4)
bge t6 t5 sub2
sub1:
sub t2 t5 t6
j loop_cont
sub2:
sub t2 t6 t5
loop_cont:
# Adding the loss to the running total
add t1 t1 t2
# Storing the absolute difference into a3
slli t3 t0 2 # t2 = index * sizeof(int)
add t3 t3 a3
sw t2 0(t3)
# Increment loop index and array pointers
addi t0 t0 1
j loop_start
loop_end:
# Move result into a0 and return
mv a0 t1
jr ra
exit_bad_len:
li a0 36
j exit
|
sysprog21/classify-rv32i | 1,398 | coverage-src/zero_one_loss.s | .globl zero_one_loss
.text
# =======================================================
# FUNCTION: Return a 0-1 classifer array
# Arguments:
# a0 (int*) is the pointer to the start of arr0
# a1 (int*) is the pointer to the start of arr1
# a2 (int) is the length of the arrays
# a3 (int*) is the pointer to the start of the result (loss) array
# Returns:
# NONE
# Exceptions:
# - If the length of the array is less than 1,
# this function terminates the program with error code 36.
# =======================================================
zero_one_loss:
# Checking to see if the stride and length is greater than 0.
li t0 1
blt a2 t0 exit_bad_len
li t0 0 # t0 is the loop index "i"
li t1 0 # t1 is the running total loss
loop_start:
# Check loop end condition
beq t0 a2 loop_end
# Get addresses of "i"th element of both arrays
slli t2 t0 2 # t2 = index * sizeof(int)
add t3 t2 a0
add t4 t2 a1
# Load "i"th element of both arrays
lw t5 0(t3)
lw t6 0(t4)
# Get address of "i"th element of the result array
add t3 t2 a3
beq t5 t6 load1
load0:
sw x0 0(t3)
j loop_cont
load1:
li t2 1
sw t2 0(t3)
loop_cont:
# Increment loop index and array pointers
addi t0 t0 1
j loop_start
loop_end:
# Move result into a0 and return
mv a0 t1
jr ra
exit_bad_len:
li a0 36
j exit
|
sysprog21/classify-rv32i | 1,537 | coverage-src/squared_loss.s | .globl squared_loss
.text
# =======================================================
# FUNCTION: Get the squared difference of 2 int arrays,
# store in a third array and compute the sum
# Arguments:
# a0 (int*) is the pointer to the start of arr0
# a1 (int*) is the pointer to the start of arr1
# a2 (int) is the length of the arrays
# a3 (int*) is the pointer to the start of the loss array
# Returns:
# a0 (int) is the sum of the squared loss
# Exceptions:
# - If the length of the array is less than 1,
# this function terminates the program with error code 36.
# =======================================================
squared_loss:
# Checking to see if the stride and length is greater than 0.
li t0 1
blt a2 t0 exit_bad_len
li t0 0 # t0 is the loop index "i"
li t1 0 # t1 is the running total loss
loop_start:
# Check loop end condition
beq t0 a2 loop_end
# Get addresses of "i"th element of both arrays
slli t2 t0 2 # t2 = index * sizeof(int)
add t3 t2 a0
add t4 t2 a1
# Load "i"th element of both arrays
lw t5 0(t3)
lw t6 0(t4)
# Getting the difference of the elements and squaring
sub t2 t5 t6
mul t2 t2 t2
add t1 t1 t2
# Storing the squared difference into a3
slli t3 t0 2 # t2 = index * sizeof(int)
add t3 t3 a3
sw t2 0(t3)
# Increment loop index and array pointers
addi t0 t0 1
j loop_start
loop_end:
# Move result into a0 and return
mv a0 t1
jr ra
exit_bad_len:
li a0 36
j exit
|
sysprog21/classify-rv32i | 3,153 | src/matmul.s | .globl matmul
.text
# =======================================================
# FUNCTION: Matrix Multiplication Implementation
#
# Performs operation: D = M0 × M1
# Where:
# - M0 is a (rows0 × cols0) matrix
# - M1 is a (rows1 × cols1) matrix
# - D is a (rows0 × cols1) result matrix
#
# Arguments:
# First Matrix (M0):
# a0: Memory address of first element
# a1: Row count
# a2: Column count
#
# Second Matrix (M1):
# a3: Memory address of first element
# a4: Row count
# a5: Column count
#
# Output Matrix (D):
# a6: Memory address for result storage
#
# Validation (in sequence):
# 1. Validates M0: Ensures positive dimensions
# 2. Validates M1: Ensures positive dimensions
# 3. Validates multiplication compatibility: M0_cols = M1_rows
# All failures trigger program exit with code 38
#
# Output:
# None explicit - Result matrix D populated in-place
# =======================================================
matmul:
# Error checks
li t0 1
blt a1, t0, error
blt a2, t0, error
blt a4, t0, error
blt a5, t0, error
bne a2, a4, error
# Prologue
addi sp, sp, -28
sw ra, 0(sp)
sw s0, 4(sp)
sw s1, 8(sp)
sw s2, 12(sp)
sw s3, 16(sp)
sw s4, 20(sp)
sw s5, 24(sp)
li s0, 0 # outer loop counter
li s1, 0 # inner loop counter
mv s2, a6 # incrementing result matrix pointer
mv s3, a0 # incrementing matrix A pointer, increments durring outer loop
mv s4, a3 # incrementing matrix B pointer, increments during inner loop
outer_loop_start:
#s0 is going to be the loop counter for the rows in A
li s1, 0
mv s4, a3
blt s0, a1, inner_loop_start
j outer_loop_end
inner_loop_start:
# HELPER FUNCTION: Dot product of 2 int arrays
# Arguments:
# a0 (int*) is the pointer to the start of arr0
# a1 (int*) is the pointer to the start of arr1
# a2 (int) is the number of elements to use = number of columns of A, or number of rows of B
# a3 (int) is the stride of arr0 = for A, stride = 1
# a4 (int) is the stride of arr1 = for B, stride = len(rows) - 1
# Returns:
# a0 (int) is the dot product of arr0 and arr1
beq s1, a5, inner_loop_end
addi sp, sp, -24
sw a0, 0(sp)
sw a1, 4(sp)
sw a2, 8(sp)
sw a3, 12(sp)
sw a4, 16(sp)
sw a5, 20(sp)
mv a0, s3 # setting pointer for matrix A into the correct argument value
mv a1, s4 # setting pointer for Matrix B into the correct argument value
mv a2, a2 # setting the number of elements to use to the columns of A
li a3, 1 # stride for matrix A
mv a4, a5 # stride for matrix B
jal dot
mv t0, a0 # storing result of the dot product into t0
lw a0, 0(sp)
lw a1, 4(sp)
lw a2, 8(sp)
lw a3, 12(sp)
lw a4, 16(sp)
lw a5, 20(sp)
addi sp, sp, 24
sw t0, 0(s2)
addi s2, s2, 4 # Incrememtning pointer for result matrix
li t1, 4
add s4, s4, t1 # incrememtning the column on Matrix B
addi s1, s1, 1
j inner_loop_start
inner_loop_end:
# TODO: Add your own implementation
error:
li a0, 38
j exit
|
sysprog21/classify-rv32i | 2,841 | src/read_matrix.s | .globl read_matrix
.text
# ==============================================================================
# FUNCTION: Binary Matrix File Reader
#
# Loads matrix data from a binary file into dynamically allocated memory.
# Matrix dimensions are read from file header and stored at provided addresses.
#
# Binary File Format:
# Header (8 bytes):
# - Bytes 0-3: Number of rows (int32)
# - Bytes 4-7: Number of columns (int32)
# Data:
# - Subsequent 4-byte blocks: Matrix elements
# - Stored in row-major order: [row0|row1|row2|...]
#
# Arguments:
# Input:
# a0: Pointer to filename string
# a1: Address to write row count
# a2: Address to write column count
#
# Output:
# a0: Base address of loaded matrix
#
# Error Handling:
# Program terminates with:
# - Code 26: Dynamic memory allocation failed
# - Code 27: File access error (open/EOF)
# - Code 28: File closure error
# - Code 29: Data read error
#
# Memory Note:
# Caller is responsible for freeing returned matrix pointer
# ==============================================================================
read_matrix:
# Prologue
addi sp, sp, -40
sw ra, 0(sp)
sw s0, 4(sp)
sw s1, 8(sp)
sw s2, 12(sp)
sw s3, 16(sp)
sw s4, 20(sp)
mv s3, a1 # save and copy rows
mv s4, a2 # save and copy cols
li a1, 0
jal fopen
li t0, -1
beq a0, t0, fopen_error # fopen didn't work
mv s0, a0 # file
# read rows n columns
mv a0, s0
addi a1, sp, 28 # a1 is a buffer
li a2, 8 # look at 2 numbers
jal fread
li t0, 8
bne a0, t0, fread_error
lw t1, 28(sp) # opening to save num rows
lw t2, 32(sp) # opening to save num cols
sw t1, 0(s3) # saves num rows
sw t2, 0(s4) # saves num cols
# mul s1, t1, t2 # s1 is number of elements
# FIXME: Replace 'mul' with your own implementation
slli t3, s1, 2
sw t3, 24(sp) # size in bytes
lw a0, 24(sp) # a0 = size in bytes
jal malloc
beq a0, x0, malloc_error
# set up file, buffer and bytes to read
mv s2, a0 # matrix
mv a0, s0
mv a1, s2
lw a2, 24(sp)
jal fread
lw t3, 24(sp)
bne a0, t3, fread_error
mv a0, s0
jal fclose
li t0, -1
beq a0, t0, fclose_error
mv a0, s2
# Epilogue
lw ra, 0(sp)
lw s0, 4(sp)
lw s1, 8(sp)
lw s2, 12(sp)
lw s3, 16(sp)
lw s4, 20(sp)
addi sp, sp, 40
jr ra
malloc_error:
li a0, 26
j error_exit
fopen_error:
li a0, 27
j error_exit
fread_error:
li a0, 29
j error_exit
fclose_error:
li a0, 28
j error_exit
error_exit:
lw ra, 0(sp)
lw s0, 4(sp)
lw s1, 8(sp)
lw s2, 12(sp)
lw s3, 16(sp)
lw s4, 20(sp)
addi sp, sp, 40
j exit
|
sysprog21/classify-rv32i | 2,600 | src/write_matrix.s | .globl write_matrix
.text
# ==============================================================================
# FUNCTION: Write a matrix of integers to a binary file
# FILE FORMAT:
# - The first 8 bytes store two 4-byte integers representing the number of
# rows and columns, respectively.
# - Each subsequent 4-byte segment represents a matrix element, stored in
# row-major order.
#
# Arguments:
# a0 (char *) - Pointer to a string representing the filename.
# a1 (int *) - Pointer to the matrix's starting location in memory.
# a2 (int) - Number of rows in the matrix.
# a3 (int) - Number of columns in the matrix.
#
# Returns:
# None
#
# Exceptions:
# - Terminates with error code 27 on `fopen` error or end-of-file (EOF).
# - Terminates with error code 28 on `fclose` error or EOF.
# - Terminates with error code 30 on `fwrite` error or EOF.
# ==============================================================================
write_matrix:
# Prologue
addi sp, sp, -44
sw ra, 0(sp)
sw s0, 4(sp)
sw s1, 8(sp)
sw s2, 12(sp)
sw s3, 16(sp)
sw s4, 20(sp)
# save arguments
mv s1, a1 # s1 = matrix pointer
mv s2, a2 # s2 = number of rows
mv s3, a3 # s3 = number of columns
li a1, 1
jal fopen
li t0, -1
beq a0, t0, fopen_error # fopen didn't work
mv s0, a0 # file descriptor
# Write number of rows and columns to file
sw s2, 24(sp) # number of rows
sw s3, 28(sp) # number of columns
mv a0, s0
addi a1, sp, 24 # buffer with rows and columns
li a2, 2 # number of elements to write
li a3, 4 # size of each element
jal fwrite
li t0, 2
bne a0, t0, fwrite_error
# mul s4, s2, s3 # s4 = total elements
# FIXME: Replace 'mul' with your own implementation
# write matrix data to file
mv a0, s0
mv a1, s1 # matrix data pointer
mv a2, s4 # number of elements to write
li a3, 4 # size of each element
jal fwrite
bne a0, s4, fwrite_error
mv a0, s0
jal fclose
li t0, -1
beq a0, t0, fclose_error
# Epilogue
lw ra, 0(sp)
lw s0, 4(sp)
lw s1, 8(sp)
lw s2, 12(sp)
lw s3, 16(sp)
lw s4, 20(sp)
addi sp, sp, 44
jr ra
fopen_error:
li a0, 27
j error_exit
fwrite_error:
li a0, 30
j error_exit
fclose_error:
li a0, 28
j error_exit
error_exit:
lw ra, 0(sp)
lw s0, 4(sp)
lw s1, 8(sp)
lw s2, 12(sp)
lw s3, 16(sp)
lw s4, 20(sp)
addi sp, sp, 44
j exit
|
sysprog21/classify-rv32i | 14,595 | src/utils.s | ##############################################################
# Do not modify! (But feel free to use the functions provided)
##############################################################
#define c_print_int 1
#define c_print_str 4
#define c_atoi 5
#define c_sbrk 9
#define c_print_char 11
#define c_openFile 13
#define c_readFile 14
#define c_writeFile 15
#define c_closeFile 16
#define c_exit2 17
#define c_fflush 18
#define c_feof 19
#define c_ferror 20
#define c_printHex 34
# ecall wrappers
.globl print_int, print_str, atoi, sbrk, exit, print_char, fopen, fread, fwrite, fclose, fflush, ferror, print_hex
# helper functions
.globl file_error, print_int_array, malloc, free, print_num_alloc_blocks, num_alloc_blocks
# unittest helper functions
.globl compare_int_array
# Calling Convention Functions
.globl randomizeCallerSavedRegs, randomizeCallerSavedRegsBesidesA0, randomizeCalleeSavedRegs, checkCalleeSavedRegs, randomizeCalleeSavedRegs2, checkCalleeSavedRegs2
.data
static_space_for_sp: .word 0 0 0
error_string: .string "This library file should not be directly called!"
static_space_for_sp2: .word 0 0 0
error_string2: .string "This library file should not be directly called!"
.text
# Exits if you run this file
main:
la a0 error_string
jal print_str
li a0 1
jal exit
# End main
#================================================================
# void print_int(int a0)
# Prints the integer in a0.
# args:
# a0 = integer to print
# return:
# void
#================================================================
print_int:
mv a1 a0
li a0 c_print_int
ecall
jr ra
#================================================================
# void print_str(char *a0)
# Prints the null-terminated string at address a0.
# args:
# a0 = address of the string you want printed.
# return:
# void
#================================================================
print_str:
mv a1 a0
li a0 c_print_str
ecall
jr ra
#================================================================
# int atoi(char* a0)
# Returns the integer version of the string at address a0.
# args:
# a0 = address of the string you want to turn into an integer.
# return:
# a0 = Integer representation of string
#================================================================
atoi:
mv a1 a0
li a0 c_atoi
ecall
jr ra
#================================================================
# void *sbrk(int a0)
# Allocates a0 bytes onto the heap.
# args:
# a0 = Number of bytes you want to allocate.
# return:
# a0 = Pointer to the start of the allocated memory
#================================================================
sbrk:
mv a1 a0
li a0 c_sbrk
ecall
jr ra
#================================================================
# void noreturn exit(int a0)
# Exits the program with error code a0.
# args:
# a0 = Exit code.
# return:
# This program does not return.
#================================================================
exit:
mv a1 a0
li a0 c_exit2
ecall
#================================================================
# void print_char(char a0)
# Prints the ASCII character in a0 to the console.
# args:
# a0 = character to print
# return:
# void
#================================================================
print_char:
mv a1 a0
li a0 c_print_char
ecall
jr ra
#================================================================
# int fopen(char *a0, int a1)
# Opens file with name a0 with permissions a1.
# args:
# a0 = filepath
# a1 = permissions (0, 1, 2, 3, 4, 5 = r, w, a, r+, w+, a+)
# return:
# a0 = file descriptor
#================================================================
fopen:
mv a2 a1
mv a1 a0
li a0 c_openFile
ecall
#FOPEN_RETURN_HOOK
jr ra
#================================================================
# int fread(int a0, void *a1, size_t a2)
# Reads a2 bytes of the file into the buffer a1.
# args:
# a0 = file descriptor
# a1 = pointer to the buffer you want to write the read bytes to.
# a2 = Number of bytes to be read.
# return:
# a0 = Number of bytes actually read.
#================================================================
fread:
mv a3 a2
mv a2 a1
mv a1 a0
li a0 c_readFile
ecall
#FREAD_RETURN_HOOK
jr ra
#================================================================
# int fwrite(int a0, void *a1, size_t a2, size_t a3)
# Writes a2 * a3 bytes from the buffer in a1 to the file descriptor a0.
# args:
# a0 = file descriptor
# a1 = Buffer to read from
# a2 = Number of items to read from the buffer.
# a3 = Size of each item in the buffer.
# return:
# a0 = Number of elements writen. If this is less than a2,
# it is either an error or EOF. You will also need to still flush the fd.
#================================================================
fwrite:
mv a4 a3
mv a3 a2
mv a2 a1
mv a1 a0
li a0 c_writeFile
ecall
#FWRITE_RETURN_HOOK
jr ra
#================================================================
# int fclose(int a0)
# Closes the file descriptor a0.
# args:
# a0 = file descriptor
# return:
# a0 = 0 on success, and EOF (-1) otherwise.
#================================================================
fclose:
mv a1 a0
li a0 c_closeFile
ecall
#FCLOSE_RETURN_HOOK
jr ra
#================================================================
# int fflush(int a0)
# Flushes the data to the filesystem.
# args:
# a0 = file descriptor
# return:
# a0 = 0 on success, and EOF (-1) otherwise.
#================================================================
fflush:
mv a1 a0
li a0 c_fflush
ecall
jr ra
#================================================================
# int ferror(int a0)
# Returns a nonzero value if the file stream has errors, otherwise it returns 0.
# args:
# a0 = file descriptor
# return:
# a0 = Nonzero falue if the end of file is reached. 0 Otherwise.
#================================================================
ferror:
mv a1 a0
li a0 c_ferror
ecall
jr ra
#================================================================
# void print_hex(int a0)
#
# args:
# a0 = The word which will be printed as a hex value.
# return:
# void
#================================================================
print_hex:
mv a1 a0
li a0 c_printHex
ecall
jr ra
#================================================================
# void* malloc(int a0)
# Allocates heap memory and return a pointer to it
# args:
# a0 is the # of bytes to allocate heap memory for
# return:
# a0 is the pointer to the allocated heap memory
#================================================================
malloc:
# Call to sbrk
mv a1 a0
li a0 0x3CC
addi a6 x0 1
ecall
#MALLOC_RETURN_HOOK
jr ra
#================================================================
# void free(int a0)
# Frees heap memory referenced by pointer
# args:
# a0 is the pointer to heap memory to free
# return:
# void
#================================================================
free:
mv a1 a0
li a0 0x3CC
addi a6 x0 4
ecall
jr ra
#================================================================
# void num_alloc_blocks(int a0)
# Returns the number of currently allocated blocks
# args:
# void
# return:
# a0 is the # of allocated blocks
#================================================================
num_alloc_blocks:
li a0, 0x3CC
li a6, 5
ecall
jr ra
print_num_alloc_blocks:
addi sp, sp -4
sw ra 0(sp)
jal num_alloc_blocks
mv a0 a0
jal print_int
li a0 '\n'
jal print_char
lw ra 0(sp)
addi sp, sp 4
jr ra
#================================================================
# void print_int_array(int* a0, int a1, int a2)
# Prints an integer array, with spaces between the elements
# args:
# a0 is the pointer to the start of the array
# a1 is the # of rows in the array
# a2 is the # of columns in the array
# return:
# void
#================================================================
print_int_array:
# Prologue
addi sp sp -24
sw s0 0(sp)
sw s1 4(sp)
sw s2 8(sp)
sw s3 12(sp)
sw s4 16(sp)
sw ra 20(sp)
# Save arguments
mv s0 a0
mv s1 a1
mv s2 a2
# Set outer loop index
li s3 0
outer_loop_start:
# Check outer loop condition
beq s3 s1 outer_loop_end
# Set inner loop index
li s4 0
inner_loop_start:
# Check inner loop condition
beq s4 s2 inner_loop_end
# t0 = row index * len(row) + column index
mul t0 s2 s3
add t0 t0 s4
slli t0 t0 2
# Load matrix element
add t0 t0 s0
lw t1 0(t0)
# Print matrix element
mv a0 t1
jal print_int
# Print whitespace
li a0 ' '
jal print_char
addi s4 s4 1
j inner_loop_start
inner_loop_end:
# Print newline
li a0 '\n'
jal print_char
addi s3 s3 1
j outer_loop_start
outer_loop_end:
# Epilogue
lw s0 0(sp)
lw s1 4(sp)
lw s2 8(sp)
lw s3 12(sp)
lw s4 16(sp)
lw ra 20(sp)
addi sp sp 24
jr ra
#================================================================
# void compare_int_array(int a0, int* a0, int* a1, int a2)
# Prints an integer array, with spaces between the elements
# args:
# a0 is the base exit code that will be used if an unequal element is found
# a1 is the pointer to the expected data
# a2 is the pointer to the actual data
# a3 is the number of elements in each array
# a4 is the error message
# return:
# void
#================================================================
compare_int_array:
# Prologue
addi sp sp -24
sw s0 0(sp)
sw s1 4(sp)
sw s2 8(sp)
sw s3 12(sp)
sw s4 16(sp)
sw ra 20(sp)
# save pointer to original array in s1
mv s1, a2
# t0: current element
mv t0 zero
loop_start:
# we are done once t0 >= a3
bge t0, a3, end
# t1 := *a1
lw t1, 0(a1)
# t2 := *a2
lw t2, 0(a2)
# if the values are different -> fail
bne t1, t2, fail
# go to next value
addi t0, t0, 1
addi a1, a1, 4
addi a2, a2, 4
j loop_start
fail:
# exit code: a0
mv s0, a0
# remember length
mv s2, a3
# print user supplied error message
mv a0, a4
jal print_str
# print actual data
mv a0, s1
li a1, 1
mv a2, s2
jal print_int_array
# exit with user defined error code
mv a0, s0
jal exit
end:
# Epilogue
lw s0 0(sp)
lw s1 4(sp)
lw s2 8(sp)
lw s3 12(sp)
lw s4 16(sp)
lw ra 20(sp)
addi sp sp 24
jr ra
# Shuffling registers to test calling convention
randomizeCallerSavedRegs:
li t0 0x61C0061C
li t1 0x61C1161C
li t2 0x61C2261C
li t3 0x61C3361C
li t4 0x61C4461C
li t5 0x61C5561C
li t6 0x61C6661C
li a0 0x61C8861C
li a1 0x61C9961C
li a2 0x61Caa61C
li a3 0x61Cbb61C
li a4 0x61Ccc61C
li a5 0x61Cdd61C
li a6 0x61Cee61C
li a7 0x61Cff61C
jr ra
randomizeCallerSavedRegsBesidesA0:
li t0 0x61C0061C
li t1 0x61C1161C
li t2 0x61C2261C
li t3 0x61C3361C
li t4 0x61C4461C
li t5 0x61C5561C
li t6 0x61C6661C
li a1 0x61C9961C
li a2 0x61Caa61C
li a3 0x61Cbb61C
li a4 0x61Ccc61C
li a5 0x61Cdd61C
li a6 0x61Cee61C
li a7 0x61Cff61C
jr ra
randomizeCalleeSavedRegs:
addi sp sp -48
sw s0 0(sp)
sw s1 4(sp)
sw s2 8(sp)
sw s3 12(sp)
sw s4 16(sp)
sw s5 20(sp)
sw s6 24(sp)
sw s7 28(sp)
sw s8 32(sp)
sw s9 36(sp)
sw s10 40(sp)
sw s11 44(sp)
la t0 static_space_for_sp
sw sp 0(t0)
li s0, 0x61D0061D
li s1, 0x61D1161D
li s2, 0x61D2261D
li s3, 0x61D3361D
li s4, 0x61D4461D
li s5, 0x61D5561D
li s6, 0x61D6661D
li s7, 0x61D7761D
li s8, 0x61D8861D
li s9, 0x61D9961D
li s10, 0x61Daa61D
li s11, 0x61Dbb61D
jr ra
checkCalleeSavedRegs:
li t0, 0x61D0061D
bne s0, t0, savereg_error
li t0, 0x61D1161D
bne s1, t0, savereg_error
li t0, 0x61D2261D
bne s2, t0, savereg_error
li t0, 0x61D3361D
bne s3, t0, savereg_error
li t0, 0x61D4461D
bne s4, t0, savereg_error
li t0, 0x61D5561D
bne s5, t0, savereg_error
li t0, 0x61D6661D
bne s6, t0, savereg_error
li t0, 0x61D7761D
bne s7, t0, savereg_error
li t0, 0x61D8861D
bne s8, t0, savereg_error
li t0, 0x61D9961D
bne s9, t0, savereg_error
li t0, 0x61Daa61D
bne s10, t0, savereg_error
li t0, 0x61Dbb61D
bne s11, t0, savereg_error
la t0 static_space_for_sp
lw t0 0(t0)
bne sp t0 savereg_error
lw s0 0(sp)
lw s1 4(sp)
lw s2 8(sp)
lw s3 12(sp)
lw s4 16(sp)
lw s5 20(sp)
lw s6 24(sp)
lw s7 28(sp)
lw s8 32(sp)
lw s9 36(sp)
lw s10 40(sp)
lw s11 44(sp)
addi sp sp 48
jr ra
randomizeCalleeSavedRegs2:
addi sp sp -48
sw s0 0(sp)
sw s1 4(sp)
sw s2 8(sp)
sw s3 12(sp)
sw s4 16(sp)
sw s5 20(sp)
sw s6 24(sp)
sw s7 28(sp)
sw s8 32(sp)
sw s9 36(sp)
sw s10 40(sp)
sw s11 44(sp)
la t0 static_space_for_sp2
sw sp 0(t0)
li s0, 0x61E0061E
li s1, 0x61E1161E
li s2, 0x61E2261E
li s3, 0x61E3361E
li s4, 0x61E4461E
li s5, 0x61E5561E
li s6, 0x61E6661E
li s7, 0x61E7761E
li s8, 0x61E8861E
li s9, 0x61E9961E
li s10, 0x61Eaa61E
li s11, 0x61Ebb61E
jr ra
checkCalleeSavedRegs2:
li t0, 0x61D0061D
bne s0, t0, savereg_error
li t0, 0x61D1161D
bne s1, t0, savereg_error
li t0, 0x61D2261D
bne s2, t0, savereg_error
li t0, 0x61D3361D
bne s3, t0, savereg_error
li t0, 0x61D4461D
bne s4, t0, savereg_error
li t0, 0x61D5561D
bne s5, t0, savereg_error
li t0, 0x61D6661D
bne s6, t0, savereg_error
li t0, 0x61D7761D
bne s7, t0, savereg_error
li t0, 0x61D8861D
bne s8, t0, savereg_error
li t0, 0x61D9961D
bne s9, t0, savereg_error
li t0, 0x61Daa61D
bne s10, t0, savereg_error
li t0, 0x61Dbb61D
bne s11, t0, savereg_error
la t0 static_space_for_sp2
lw t0 0(t0)
bne sp t0 savereg_error
lw s0 0(sp)
lw s1 4(sp)
lw s2 8(sp)
lw s3 12(sp)
lw s4 16(sp)
lw s5 20(sp)
lw s6 24(sp)
lw s7 28(sp)
lw s8 32(sp)
lw s9 36(sp)
lw s10 40(sp)
lw s11 44(sp)
addi sp sp 48
jr ra
savereg_error:
li a0 100
jal exit
|
sysprog21/classify-rv32i | 8,059 | src/classify.s | .globl classify
.text
# =====================================
# NEURAL NETWORK CLASSIFIER
# =====================================
# Description:
# Command line program for matrix-based classification
#
# Command Line Arguments:
# 1. M0_PATH - First matrix file location
# 2. M1_PATH - Second matrix file location
# 3. INPUT_PATH - Input matrix file location
# 4. OUTPUT_PATH - Output file destination
#
# Register Usage:
# a0 (int) - Input: Argument count
# - Output: Classification result
# a1 (char **) - Input: Argument vector
# a2 (int) - Input: Silent mode flag
# (0 = verbose, 1 = silent)
#
# Error Codes:
# 31 - Invalid argument count
# 26 - Memory allocation failure
#
# Usage Example:
# main.s <M0_PATH> <M1_PATH> <INPUT_PATH> <OUTPUT_PATH>
# =====================================
classify:
# Error handling
li t0, 5
blt a0, t0, error_args
# Prolouge
addi sp, sp, -48
sw ra, 0(sp)
sw s0, 4(sp) # m0 matrix
sw s1, 8(sp) # m1 matrix
sw s2, 12(sp) # input matrix
sw s3, 16(sp) # m0 matrix rows
sw s4, 20(sp) # m0 matrix cols
sw s5, 24(sp) # m1 matrix rows
sw s6, 28(sp) # m1 matrix cols
sw s7, 32(sp) # input matrix rows
sw s8, 36(sp) # input matrix cols
sw s9, 40(sp) # h
sw s10, 44(sp) # o
# Read pretrained m0
addi sp, sp, -12
sw a0, 0(sp)
sw a1, 4(sp)
sw a2, 8(sp)
li a0, 4
jal malloc # malloc 4 bytes for an integer, rows
beq a0, x0, error_malloc
mv s3, a0 # save m0 rows pointer for later
li a0, 4
jal malloc # malloc 4 bytes for an integer, cols
beq a0, x0, error_malloc
mv s4, a0 # save m0 cols pointer for later
lw a1, 4(sp) # restores the argument pointer
lw a0, 4(a1) # set argument 1 for the read_matrix function
mv a1, s3 # set argument 2 for the read_matrix function
mv a2, s4 # set argument 3 for the read_matrix function
jal read_matrix
mv s0, a0 # setting s0 to the m0, aka the return value of read_matrix
lw a0, 0(sp)
lw a1, 4(sp)
lw a2, 8(sp)
addi sp, sp, 12
# Read pretrained m1
addi sp, sp, -12
sw a0, 0(sp)
sw a1, 4(sp)
sw a2, 8(sp)
li a0, 4
jal malloc # malloc 4 bytes for an integer, rows
beq a0, x0, error_malloc
mv s5, a0 # save m1 rows pointer for later
li a0, 4
jal malloc # malloc 4 bytes for an integer, cols
beq a0, x0, error_malloc
mv s6, a0 # save m1 cols pointer for later
lw a1, 4(sp) # restores the argument pointer
lw a0, 8(a1) # set argument 1 for the read_matrix function
mv a1, s5 # set argument 2 for the read_matrix function
mv a2, s6 # set argument 3 for the read_matrix function
jal read_matrix
mv s1, a0 # setting s1 to the m1, aka the return value of read_matrix
lw a0, 0(sp)
lw a1, 4(sp)
lw a2, 8(sp)
addi sp, sp, 12
# Read input matrix
addi sp, sp, -12
sw a0, 0(sp)
sw a1, 4(sp)
sw a2, 8(sp)
li a0, 4
jal malloc # malloc 4 bytes for an integer, rows
beq a0, x0, error_malloc
mv s7, a0 # save input rows pointer for later
li a0, 4
jal malloc # malloc 4 bytes for an integer, cols
beq a0, x0, error_malloc
mv s8, a0 # save input cols pointer for later
lw a1, 4(sp) # restores the argument pointer
lw a0, 12(a1) # set argument 1 for the read_matrix function
mv a1, s7 # set argument 2 for the read_matrix function
mv a2, s8 # set argument 3 for the read_matrix function
jal read_matrix
mv s2, a0 # setting s2 to the input matrix, aka the return value of read_matrix
lw a0, 0(sp)
lw a1, 4(sp)
lw a2, 8(sp)
addi sp, sp, 12
# Compute h = matmul(m0, input)
addi sp, sp, -28
sw a0, 0(sp)
sw a1, 4(sp)
sw a2, 8(sp)
sw a3, 12(sp)
sw a4, 16(sp)
sw a5, 20(sp)
sw a6, 24(sp)
lw t0, 0(s3)
lw t1, 0(s8)
# mul a0, t0, t1 # FIXME: Replace 'mul' with your own implementation
slli a0, a0, 2
jal malloc
beq a0, x0, error_malloc
mv s9, a0 # move h to s9
mv a6, a0 # h
mv a0, s0 # move m0 array to first arg
lw a1, 0(s3) # move m0 rows to second arg
lw a2, 0(s4) # move m0 cols to third arg
mv a3, s2 # move input array to fourth arg
lw a4, 0(s7) # move input rows to fifth arg
lw a5, 0(s8) # move input cols to sixth arg
jal matmul
lw a0, 0(sp)
lw a1, 4(sp)
lw a2, 8(sp)
lw a3, 12(sp)
lw a4, 16(sp)
lw a5, 20(sp)
lw a6, 24(sp)
addi sp, sp, 28
# Compute h = relu(h)
addi sp, sp, -8
sw a0, 0(sp)
sw a1, 4(sp)
mv a0, s9 # move h to the first argument
lw t0, 0(s3)
lw t1, 0(s8)
# mul a1, t0, t1 # length of h array and set it as second argument
# FIXME: Replace 'mul' with your own implementation
jal relu
lw a0, 0(sp)
lw a1, 4(sp)
addi sp, sp, 8
# Compute o = matmul(m1, h)
addi sp, sp, -28
sw a0, 0(sp)
sw a1, 4(sp)
sw a2, 8(sp)
sw a3, 12(sp)
sw a4, 16(sp)
sw a5, 20(sp)
sw a6, 24(sp)
lw t0, 0(s3)
lw t1, 0(s6)
# mul a0, t0, t1 # FIXME: Replace 'mul' with your own implementation
slli a0, a0, 2
jal malloc
beq a0, x0, error_malloc
mv s10, a0 # move o to s10
mv a6, a0 # o
mv a0, s1 # move m1 array to first arg
lw a1, 0(s5) # move m1 rows to second arg
lw a2, 0(s6) # move m1 cols to third arg
mv a3, s9 # move h array to fourth arg
lw a4, 0(s3) # move h rows to fifth arg
lw a5, 0(s8) # move h cols to sixth arg
jal matmul
lw a0, 0(sp)
lw a1, 4(sp)
lw a2, 8(sp)
lw a3, 12(sp)
lw a4, 16(sp)
lw a5, 20(sp)
lw a6, 24(sp)
addi sp, sp, 28
# Write output matrix o
addi sp, sp, -16
sw a0, 0(sp)
sw a1, 4(sp)
sw a2, 8(sp)
sw a3, 12(sp)
lw a0, 16(a1) # load filename string into first arg
mv a1, s10 # load array into second arg
lw a2, 0(s5) # load number of rows into fourth arg
lw a3, 0(s8) # load number of cols into third arg
jal write_matrix
lw a0, 0(sp)
lw a1, 4(sp)
lw a2, 8(sp)
lw a3, 12(sp)
addi sp, sp, 16
# Compute and return argmax(o)
addi sp, sp, -12
sw a0, 0(sp)
sw a1, 4(sp)
sw a2, 8(sp)
mv a0, s10 # load o array into first arg
lw t0, 0(s3)
lw t1, 0(s6)
mul a1, t0, t1 # load length of array into second arg
# FIXME: Replace 'mul' with your own implementation
jal argmax
mv t0, a0 # move return value of argmax into t0
lw a0, 0(sp)
lw a1, 4(sp)
lw a2, 8(sp)
addi sp, sp 12
mv a0, t0
# If enabled, print argmax(o) and newline
bne a2, x0, epilouge
addi sp, sp, -4
sw a0, 0(sp)
jal print_int
li a0, '\n'
jal print_char
lw a0, 0(sp)
addi sp, sp, 4
# Epilouge
epilouge:
addi sp, sp, -4
sw a0, 0(sp)
mv a0, s0
jal free
mv a0, s1
jal free
mv a0, s2
jal free
mv a0, s3
jal free
mv a0, s4
jal free
mv a0, s5
jal free
mv a0, s6
jal free
mv a0, s7
jal free
mv a0, s8
jal free
mv a0, s9
jal free
mv a0, s10
jal free
lw a0, 0(sp)
addi sp, sp, 4
lw ra, 0(sp)
lw s0, 4(sp) # m0 matrix
lw s1, 8(sp) # m1 matrix
lw s2, 12(sp) # input matrix
lw s3, 16(sp)
lw s4, 20(sp)
lw s5, 24(sp)
lw s6, 28(sp)
lw s7, 32(sp)
lw s8, 36(sp)
lw s9, 40(sp) # h
lw s10, 44(sp) # o
addi sp, sp, 48
jr ra
error_args:
li a0, 31
j exit
error_malloc:
li a0, 26
j exit
|
sysprog21/classify-rv32i | 1,186 | src/dot.s | .globl dot
.text
# =======================================================
# FUNCTION: Strided Dot Product Calculator
#
# Calculates sum(arr0[i * stride0] * arr1[i * stride1])
# where i ranges from 0 to (element_count - 1)
#
# Args:
# a0 (int *): Pointer to first input array
# a1 (int *): Pointer to second input array
# a2 (int): Number of elements to process
# a3 (int): Skip distance in first array
# a4 (int): Skip distance in second array
#
# Returns:
# a0 (int): Resulting dot product value
#
# Preconditions:
# - Element count must be positive (>= 1)
# - Both strides must be positive (>= 1)
#
# Error Handling:
# - Exits with code 36 if element count < 1
# - Exits with code 37 if any stride < 1
# =======================================================
dot:
li t0, 1
blt a2, t0, error_terminate
blt a3, t0, error_terminate
blt a4, t0, error_terminate
li t0, 0
li t1, 0
loop_start:
bge t1, a2, loop_end
# TODO: Add your own implementation
loop_end:
mv a0, t0
jr ra
error_terminate:
blt a2, t0, set_error_36
li a0, 37
j exit
set_error_36:
li a0, 36
j exit
|
sysprog21/classify-rv32i | 4,838 | tests/chain-1/chain.s | .import ../../src/read_matrix.s
.import ../../src/write_matrix.s
.import ../../src/matmul.s
.import ../../src/dot.s
.import ../../src/relu.s
.import ../../src/argmax.s
.import ../../src/utils.s
.import ../../src/classify.s
.globl main
# This is a dummy main function which imports and calls the classify function.
# While it just exits right after, it could always call classify again.
.data
print_msg: .string "Two classifications:\n"
fname: .string "main_chain.s"
simple0_m0: .string "../tests/chain-1/batch0-m0.bin"
simple0_m1: .string "../tests/chain-1/batch0-m1.bin"
simple0_input: .string "../tests/chain-1/batch0-input.bin"
simple0_output: .string "../tests/chain-1/batch0-output.bin"
larger0_m0: .string "../tests/chain-1/batch1-m0.bin"
larger0_m1: .string "../tests/chain-1/batch1-m1.bin"
larger0_input: .string "../tests/chain-1/batch1-input.bin"
larger0_output: .string "../tests/chain-1/batch1-output.bin"
.text
main:
# BEGIN MAIN CHAIN
# allocate spaces for 5 pointers on the stack
addi sp, sp, -20
# load first argument on the stack
la t0, fname
sw t0, 0(sp)
# load filepath for m0 on the stack
la t0, simple0_m0
sw t0, 4(sp)
# load filepath for m1 on the stack
la t0, simple0_m1
sw t0, 8(sp)
# load filepath for input on the stack
la t0, simple0_input
sw t0, 12(sp)
# load filepath for output on the stack
la t0, simple0_output
sw t0, 16(sp)
# load a0, a1, and a2 as arguments, preparing to call classify
li a0 5
mv a1 sp
li a2 1
# call the `classify` function
jal classify
# load back the stack
addi sp, sp 16
# save output of first classify on the stack
sw a0, 0(sp)
# allocate space and load filepath on the stack
addi sp, sp, -20
la t0, fname
sw t0, 0(sp)
la t0, simple0_m0
sw t0, 4(sp)
la t0, simple0_m1
sw t0, 8(sp)
la t0, simple0_input
sw t0, 12(sp)
la t0, simple0_output
sw t0, 16(sp)
# load arguments and call classify
li a0 5
mv a1 sp
li a2 1
jal classify
# save output of second classify
mv s1 a0
# load back the stack pointer for the second classify call
addi sp, sp, 20
# load the result of the first classify call
lw s0 0(sp)
# restore the stack pointer to before the first classify call
addi sp, sp, 4
# print message
la a0 print_msg
jal print_str
# print result of first classify
mv a0 s0
jal print_int
li a0 '\n'
jal print_char
# print result of second classify
mv a0 s1
jal print_int
li a0 '\n'
jal print_char
# END MAIN CHAIN
# BEGIN MAIN CHAIN
# load filepath on the stack
addi sp, sp, -20
la t0, fname
sw t0, 0(sp)
la t0, simple0_m0
sw t0, 4(sp)
la t0, simple0_m1
sw t0, 8(sp)
la t0, simple0_input
sw t0, 12(sp)
la t0, simple0_output
sw t0, 16(sp)
# load arguments and call classify
li a0 5
mv a1 sp
li a2 1
jal classify
addi sp, sp 16
# save output of first classify
sw a0, 0(sp)
# load filepath for second classify
addi sp, sp, -20
la t0, fname
sw t0, 0(sp)
la t0, larger0_m0
sw t0, 4(sp)
la t0, larger0_m1
sw t0, 8(sp)
la t0, larger0_input
sw t0, 12(sp)
la t0, larger0_output
sw t0, 16(sp)
# load arguments and call classify
li a0 5
mv a1 sp
li a2 1
jal classify
# save output of second classify
mv s1 a0
# load back output of first classify, restore sp
addi sp, sp, 20
lw s0 0(sp)
addi sp, sp, 4
# print message
la a0 print_msg
jal print_str
# print first classify output
mv a0 s0
jal print_int
li a0 '\n'
jal print_char
# print second classify output
mv a0 s1
jal print_int
li a0 '\n'
jal print_char
# END MAIN CHAIN
# BEGIN MAIN CHAIN
# Repeat the same process as the last two
addi sp, sp, -20
la t0, fname
sw t0, 0(sp)
la t0, larger0_m0
sw t0, 4(sp)
la t0, larger0_m1
sw t0, 8(sp)
la t0, larger0_input
sw t0, 12(sp)
la t0, larger0_output
sw t0, 16(sp)
li a0 5
mv a1 sp
li a2 1
jal classify
addi sp, sp 16
sw a0, 0(sp)
addi sp, sp, -20
la t0, fname
sw t0, 0(sp)
la t0, larger0_m0
sw t0, 4(sp)
la t0, larger0_m1
sw t0, 8(sp)
la t0, larger0_input
sw t0, 12(sp)
la t0, larger0_output
sw t0, 16(sp)
li a0 5
mv a1 sp
li a2 1
jal classify
mv s1 a0
addi sp, sp, 20
lw s0 0(sp)
addi sp, sp, 4
la a0 print_msg
jal print_str
mv a0 s0
jal print_int
li a0 '\n'
jal print_char
mv a0 s1
jal print_int
li a0 '\n'
jal print_char
# END MAIN CHAIN
li a0 0
jal exit
|
yigao/NFShmXFrame | 42,842 | thirdparty/zlib/contrib/inflate86/inffast.S | /*
* inffast.S is a hand tuned assembler version of:
*
* inffast.c -- fast decoding
* Copyright (C) 1995-2003 Mark Adler
* For conditions of distribution and use, see copyright notice in zlib.h
*
* Copyright (C) 2003 Chris Anderson <christop@charm.net>
* Please use the copyright conditions above.
*
* This version (Jan-23-2003) of inflate_fast was coded and tested under
* GNU/Linux on a pentium 3, using the gcc-3.2 compiler distribution. On that
* machine, I found that gzip style archives decompressed about 20% faster than
* the gcc-3.2 -O3 -fomit-frame-pointer compiled version. Your results will
* depend on how large of a buffer is used for z_stream.next_in & next_out
* (8K-32K worked best for my 256K cpu cache) and how much overhead there is in
* stream processing I/O and crc32/addler32. In my case, this routine used
* 70% of the cpu time and crc32 used 20%.
*
* I am confident that this version will work in the general case, but I have
* not tested a wide variety of datasets or a wide variety of platforms.
*
* Jan-24-2003 -- Added -DUSE_MMX define for slightly faster inflating.
* It should be a runtime flag instead of compile time flag...
*
* Jan-26-2003 -- Added runtime check for MMX support with cpuid instruction.
* With -DUSE_MMX, only MMX code is compiled. With -DNO_MMX, only non-MMX code
* is compiled. Without either option, runtime detection is enabled. Runtime
* detection should work on all modern cpus and the recomended algorithm (flip
* ID bit on eflags and then use the cpuid instruction) is used in many
* multimedia applications. Tested under win2k with gcc-2.95 and gas-2.12
* distributed with cygwin3. Compiling with gcc-2.95 -c inffast.S -o
* inffast.obj generates a COFF object which can then be linked with MSVC++
* compiled code. Tested under FreeBSD 4.7 with gcc-2.95.
*
* Jan-28-2003 -- Tested Athlon XP... MMX mode is slower than no MMX (and
* slower than compiler generated code). Adjusted cpuid check to use the MMX
* code only for Pentiums < P4 until I have more data on the P4. Speed
* improvment is only about 15% on the Athlon when compared with code generated
* with MSVC++. Not sure yet, but I think the P4 will also be slower using the
* MMX mode because many of it's x86 ALU instructions execute in .5 cycles and
* have less latency than MMX ops. Added code to buffer the last 11 bytes of
* the input stream since the MMX code grabs bits in chunks of 32, which
* differs from the inffast.c algorithm. I don't think there would have been
* read overruns where a page boundary was crossed (a segfault), but there
* could have been overruns when next_in ends on unaligned memory (unintialized
* memory read).
*
* Mar-13-2003 -- P4 MMX is slightly slower than P4 NO_MMX. I created a C
* version of the non-MMX code so that it doesn't depend on zstrm and zstate
* structure offsets which are hard coded in this file. This was last tested
* with zlib-1.2.0 which is currently in beta testing, newer versions of this
* and inffas86.c can be found at http://www.eetbeetee.com/zlib/ and
* http://www.charm.net/~christop/zlib/
*/
/*
* if you have underscore linking problems (_inflate_fast undefined), try
* using -DGAS_COFF
*/
#if ! defined( GAS_COFF ) && ! defined( GAS_ELF )
#if defined( WIN32 ) || defined( __CYGWIN__ )
#define GAS_COFF /* windows object format */
#else
#define GAS_ELF
#endif
#endif /* ! GAS_COFF && ! GAS_ELF */
#if defined( GAS_COFF )
/* coff externals have underscores */
#define inflate_fast _inflate_fast
#define inflate_fast_use_mmx _inflate_fast_use_mmx
#endif /* GAS_COFF */
.file "inffast.S"
.globl inflate_fast
.text
.align 4,0
.L_invalid_literal_length_code_msg:
.string "invalid literal/length code"
.align 4,0
.L_invalid_distance_code_msg:
.string "invalid distance code"
.align 4,0
.L_invalid_distance_too_far_msg:
.string "invalid distance too far back"
#if ! defined( NO_MMX )
.align 4,0
.L_mask: /* mask[N] = ( 1 << N ) - 1 */
.long 0
.long 1
.long 3
.long 7
.long 15
.long 31
.long 63
.long 127
.long 255
.long 511
.long 1023
.long 2047
.long 4095
.long 8191
.long 16383
.long 32767
.long 65535
.long 131071
.long 262143
.long 524287
.long 1048575
.long 2097151
.long 4194303
.long 8388607
.long 16777215
.long 33554431
.long 67108863
.long 134217727
.long 268435455
.long 536870911
.long 1073741823
.long 2147483647
.long 4294967295
#endif /* NO_MMX */
.text
/*
* struct z_stream offsets, in zlib.h
*/
#define next_in_strm 0 /* strm->next_in */
#define avail_in_strm 4 /* strm->avail_in */
#define next_out_strm 12 /* strm->next_out */
#define avail_out_strm 16 /* strm->avail_out */
#define msg_strm 24 /* strm->msg */
#define state_strm 28 /* strm->state */
/*
* struct inflate_state offsets, in inflate.h
*/
#define mode_state 0 /* state->mode */
#define wsize_state 32 /* state->wsize */
#define write_state 40 /* state->write */
#define window_state 44 /* state->window */
#define hold_state 48 /* state->hold */
#define bits_state 52 /* state->bits */
#define lencode_state 68 /* state->lencode */
#define distcode_state 72 /* state->distcode */
#define lenbits_state 76 /* state->lenbits */
#define distbits_state 80 /* state->distbits */
/*
* inflate_fast's activation record
*/
#define local_var_size 64 /* how much local space for vars */
#define strm_sp 88 /* first arg: z_stream * (local_var_size + 24) */
#define start_sp 92 /* second arg: unsigned int (local_var_size + 28) */
/*
* offsets for local vars on stack
*/
#define out 60 /* unsigned char* */
#define window 56 /* unsigned char* */
#define wsize 52 /* unsigned int */
#define write 48 /* unsigned int */
#define in 44 /* unsigned char* */
#define beg 40 /* unsigned char* */
#define buf 28 /* char[ 12 ] */
#define len 24 /* unsigned int */
#define last 20 /* unsigned char* */
#define end 16 /* unsigned char* */
#define dcode 12 /* code* */
#define lcode 8 /* code* */
#define dmask 4 /* unsigned int */
#define lmask 0 /* unsigned int */
/*
* typedef enum inflate_mode consts, in inflate.h
*/
#define INFLATE_MODE_TYPE 11 /* state->mode flags enum-ed in inflate.h */
#define INFLATE_MODE_BAD 26
#if ! defined( USE_MMX ) && ! defined( NO_MMX )
#define RUN_TIME_MMX
#define CHECK_MMX 1
#define DO_USE_MMX 2
#define DONT_USE_MMX 3
.globl inflate_fast_use_mmx
.data
.align 4,0
inflate_fast_use_mmx: /* integer flag for run time control 1=check,2=mmx,3=no */
.long CHECK_MMX
#if defined( GAS_ELF )
/* elf info */
.type inflate_fast_use_mmx,@object
.size inflate_fast_use_mmx,4
#endif
#endif /* RUN_TIME_MMX */
#if defined( GAS_COFF )
/* coff info: scl 2 = extern, type 32 = function */
.def inflate_fast; .scl 2; .type 32; .endef
#endif
.text
.align 32,0x90
inflate_fast:
pushl %edi
pushl %esi
pushl %ebp
pushl %ebx
pushf /* save eflags (strm_sp, state_sp assumes this is 32 bits) */
subl $local_var_size, %esp
cld
#define strm_r %esi
#define state_r %edi
movl strm_sp(%esp), strm_r
movl state_strm(strm_r), state_r
/* in = strm->next_in;
* out = strm->next_out;
* last = in + strm->avail_in - 11;
* beg = out - (start - strm->avail_out);
* end = out + (strm->avail_out - 257);
*/
movl avail_in_strm(strm_r), %edx
movl next_in_strm(strm_r), %eax
addl %eax, %edx /* avail_in += next_in */
subl $11, %edx /* avail_in -= 11 */
movl %eax, in(%esp)
movl %edx, last(%esp)
movl start_sp(%esp), %ebp
movl avail_out_strm(strm_r), %ecx
movl next_out_strm(strm_r), %ebx
subl %ecx, %ebp /* start -= avail_out */
negl %ebp /* start = -start */
addl %ebx, %ebp /* start += next_out */
subl $257, %ecx /* avail_out -= 257 */
addl %ebx, %ecx /* avail_out += out */
movl %ebx, out(%esp)
movl %ebp, beg(%esp)
movl %ecx, end(%esp)
/* wsize = state->wsize;
* write = state->write;
* window = state->window;
* hold = state->hold;
* bits = state->bits;
* lcode = state->lencode;
* dcode = state->distcode;
* lmask = ( 1 << state->lenbits ) - 1;
* dmask = ( 1 << state->distbits ) - 1;
*/
movl lencode_state(state_r), %eax
movl distcode_state(state_r), %ecx
movl %eax, lcode(%esp)
movl %ecx, dcode(%esp)
movl $1, %eax
movl lenbits_state(state_r), %ecx
shll %cl, %eax
decl %eax
movl %eax, lmask(%esp)
movl $1, %eax
movl distbits_state(state_r), %ecx
shll %cl, %eax
decl %eax
movl %eax, dmask(%esp)
movl wsize_state(state_r), %eax
movl write_state(state_r), %ecx
movl window_state(state_r), %edx
movl %eax, wsize(%esp)
movl %ecx, write(%esp)
movl %edx, window(%esp)
movl hold_state(state_r), %ebp
movl bits_state(state_r), %ebx
#undef strm_r
#undef state_r
#define in_r %esi
#define from_r %esi
#define out_r %edi
movl in(%esp), in_r
movl last(%esp), %ecx
cmpl in_r, %ecx
ja .L_align_long /* if in < last */
addl $11, %ecx /* ecx = &in[ avail_in ] */
subl in_r, %ecx /* ecx = avail_in */
movl $12, %eax
subl %ecx, %eax /* eax = 12 - avail_in */
leal buf(%esp), %edi
rep movsb /* memcpy( buf, in, avail_in ) */
movl %eax, %ecx
xorl %eax, %eax
rep stosb /* memset( &buf[ avail_in ], 0, 12 - avail_in ) */
leal buf(%esp), in_r /* in = buf */
movl in_r, last(%esp) /* last = in, do just one iteration */
jmp .L_is_aligned
/* align in_r on long boundary */
.L_align_long:
testl $3, in_r
jz .L_is_aligned
xorl %eax, %eax
movb (in_r), %al
incl in_r
movl %ebx, %ecx
addl $8, %ebx
shll %cl, %eax
orl %eax, %ebp
jmp .L_align_long
.L_is_aligned:
movl out(%esp), out_r
#if defined( NO_MMX )
jmp .L_do_loop
#endif
#if defined( USE_MMX )
jmp .L_init_mmx
#endif
/*** Runtime MMX check ***/
#if defined( RUN_TIME_MMX )
.L_check_mmx:
cmpl $DO_USE_MMX, inflate_fast_use_mmx
je .L_init_mmx
ja .L_do_loop /* > 2 */
pushl %eax
pushl %ebx
pushl %ecx
pushl %edx
pushf
movl (%esp), %eax /* copy eflags to eax */
xorl $0x200000, (%esp) /* try toggling ID bit of eflags (bit 21)
* to see if cpu supports cpuid...
* ID bit method not supported by NexGen but
* bios may load a cpuid instruction and
* cpuid may be disabled on Cyrix 5-6x86 */
popf
pushf
popl %edx /* copy new eflags to edx */
xorl %eax, %edx /* test if ID bit is flipped */
jz .L_dont_use_mmx /* not flipped if zero */
xorl %eax, %eax
cpuid
cmpl $0x756e6547, %ebx /* check for GenuineIntel in ebx,ecx,edx */
jne .L_dont_use_mmx
cmpl $0x6c65746e, %ecx
jne .L_dont_use_mmx
cmpl $0x49656e69, %edx
jne .L_dont_use_mmx
movl $1, %eax
cpuid /* get cpu features */
shrl $8, %eax
andl $15, %eax
cmpl $6, %eax /* check for Pentium family, is 0xf for P4 */
jne .L_dont_use_mmx
testl $0x800000, %edx /* test if MMX feature is set (bit 23) */
jnz .L_use_mmx
jmp .L_dont_use_mmx
.L_use_mmx:
movl $DO_USE_MMX, inflate_fast_use_mmx
jmp .L_check_mmx_pop
.L_dont_use_mmx:
movl $DONT_USE_MMX, inflate_fast_use_mmx
.L_check_mmx_pop:
popl %edx
popl %ecx
popl %ebx
popl %eax
jmp .L_check_mmx
#endif
/*** Non-MMX code ***/
#if defined ( NO_MMX ) || defined( RUN_TIME_MMX )
#define hold_r %ebp
#define bits_r %bl
#define bitslong_r %ebx
.align 32,0x90
.L_while_test:
/* while (in < last && out < end)
*/
cmpl out_r, end(%esp)
jbe .L_break_loop /* if (out >= end) */
cmpl in_r, last(%esp)
jbe .L_break_loop
.L_do_loop:
/* regs: %esi = in, %ebp = hold, %bl = bits, %edi = out
*
* do {
* if (bits < 15) {
* hold |= *((unsigned short *)in)++ << bits;
* bits += 16
* }
* this = lcode[hold & lmask]
*/
cmpb $15, bits_r
ja .L_get_length_code /* if (15 < bits) */
xorl %eax, %eax
lodsw /* al = *(ushort *)in++ */
movb bits_r, %cl /* cl = bits, needs it for shifting */
addb $16, bits_r /* bits += 16 */
shll %cl, %eax
orl %eax, hold_r /* hold |= *((ushort *)in)++ << bits */
.L_get_length_code:
movl lmask(%esp), %edx /* edx = lmask */
movl lcode(%esp), %ecx /* ecx = lcode */
andl hold_r, %edx /* edx &= hold */
movl (%ecx,%edx,4), %eax /* eax = lcode[hold & lmask] */
.L_dolen:
/* regs: %esi = in, %ebp = hold, %bl = bits, %edi = out
*
* dolen:
* bits -= this.bits;
* hold >>= this.bits
*/
movb %ah, %cl /* cl = this.bits */
subb %ah, bits_r /* bits -= this.bits */
shrl %cl, hold_r /* hold >>= this.bits */
/* check if op is a literal
* if (op == 0) {
* PUP(out) = this.val;
* }
*/
testb %al, %al
jnz .L_test_for_length_base /* if (op != 0) 45.7% */
shrl $16, %eax /* output this.val char */
stosb
jmp .L_while_test
.L_test_for_length_base:
/* regs: %esi = in, %ebp = hold, %bl = bits, %edi = out, %edx = len
*
* else if (op & 16) {
* len = this.val
* op &= 15
* if (op) {
* if (op > bits) {
* hold |= *((unsigned short *)in)++ << bits;
* bits += 16
* }
* len += hold & mask[op];
* bits -= op;
* hold >>= op;
* }
*/
#define len_r %edx
movl %eax, len_r /* len = this */
shrl $16, len_r /* len = this.val */
movb %al, %cl
testb $16, %al
jz .L_test_for_second_level_length /* if ((op & 16) == 0) 8% */
andb $15, %cl /* op &= 15 */
jz .L_save_len /* if (!op) */
cmpb %cl, bits_r
jae .L_add_bits_to_len /* if (op <= bits) */
movb %cl, %ch /* stash op in ch, freeing cl */
xorl %eax, %eax
lodsw /* al = *(ushort *)in++ */
movb bits_r, %cl /* cl = bits, needs it for shifting */
addb $16, bits_r /* bits += 16 */
shll %cl, %eax
orl %eax, hold_r /* hold |= *((ushort *)in)++ << bits */
movb %ch, %cl /* move op back to ecx */
.L_add_bits_to_len:
movl $1, %eax
shll %cl, %eax
decl %eax
subb %cl, bits_r
andl hold_r, %eax /* eax &= hold */
shrl %cl, hold_r
addl %eax, len_r /* len += hold & mask[op] */
.L_save_len:
movl len_r, len(%esp) /* save len */
#undef len_r
.L_decode_distance:
/* regs: %esi = in, %ebp = hold, %bl = bits, %edi = out, %edx = dist
*
* if (bits < 15) {
* hold |= *((unsigned short *)in)++ << bits;
* bits += 16
* }
* this = dcode[hold & dmask];
* dodist:
* bits -= this.bits;
* hold >>= this.bits;
* op = this.op;
*/
cmpb $15, bits_r
ja .L_get_distance_code /* if (15 < bits) */
xorl %eax, %eax
lodsw /* al = *(ushort *)in++ */
movb bits_r, %cl /* cl = bits, needs it for shifting */
addb $16, bits_r /* bits += 16 */
shll %cl, %eax
orl %eax, hold_r /* hold |= *((ushort *)in)++ << bits */
.L_get_distance_code:
movl dmask(%esp), %edx /* edx = dmask */
movl dcode(%esp), %ecx /* ecx = dcode */
andl hold_r, %edx /* edx &= hold */
movl (%ecx,%edx,4), %eax /* eax = dcode[hold & dmask] */
#define dist_r %edx
.L_dodist:
movl %eax, dist_r /* dist = this */
shrl $16, dist_r /* dist = this.val */
movb %ah, %cl
subb %ah, bits_r /* bits -= this.bits */
shrl %cl, hold_r /* hold >>= this.bits */
/* if (op & 16) {
* dist = this.val
* op &= 15
* if (op > bits) {
* hold |= *((unsigned short *)in)++ << bits;
* bits += 16
* }
* dist += hold & mask[op];
* bits -= op;
* hold >>= op;
*/
movb %al, %cl /* cl = this.op */
testb $16, %al /* if ((op & 16) == 0) */
jz .L_test_for_second_level_dist
andb $15, %cl /* op &= 15 */
jz .L_check_dist_one
cmpb %cl, bits_r
jae .L_add_bits_to_dist /* if (op <= bits) 97.6% */
movb %cl, %ch /* stash op in ch, freeing cl */
xorl %eax, %eax
lodsw /* al = *(ushort *)in++ */
movb bits_r, %cl /* cl = bits, needs it for shifting */
addb $16, bits_r /* bits += 16 */
shll %cl, %eax
orl %eax, hold_r /* hold |= *((ushort *)in)++ << bits */
movb %ch, %cl /* move op back to ecx */
.L_add_bits_to_dist:
movl $1, %eax
shll %cl, %eax
decl %eax /* (1 << op) - 1 */
subb %cl, bits_r
andl hold_r, %eax /* eax &= hold */
shrl %cl, hold_r
addl %eax, dist_r /* dist += hold & ((1 << op) - 1) */
jmp .L_check_window
.L_check_window:
/* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist
* %ecx = nbytes
*
* nbytes = out - beg;
* if (dist <= nbytes) {
* from = out - dist;
* do {
* PUP(out) = PUP(from);
* } while (--len > 0) {
* }
*/
movl in_r, in(%esp) /* save in so from can use it's reg */
movl out_r, %eax
subl beg(%esp), %eax /* nbytes = out - beg */
cmpl dist_r, %eax
jb .L_clip_window /* if (dist > nbytes) 4.2% */
movl len(%esp), %ecx
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
subl $3, %ecx
movb (from_r), %al
movb %al, (out_r)
movb 1(from_r), %al
movb 2(from_r), %dl
addl $3, from_r
movb %al, 1(out_r)
movb %dl, 2(out_r)
addl $3, out_r
rep movsb
movl in(%esp), in_r /* move in back to %esi, toss from */
jmp .L_while_test
.align 16,0x90
.L_check_dist_one:
cmpl $1, dist_r
jne .L_check_window
cmpl out_r, beg(%esp)
je .L_check_window
decl out_r
movl len(%esp), %ecx
movb (out_r), %al
subl $3, %ecx
movb %al, 1(out_r)
movb %al, 2(out_r)
movb %al, 3(out_r)
addl $4, out_r
rep stosb
jmp .L_while_test
.align 16,0x90
.L_test_for_second_level_length:
/* else if ((op & 64) == 0) {
* this = lcode[this.val + (hold & mask[op])];
* }
*/
testb $64, %al
jnz .L_test_for_end_of_block /* if ((op & 64) != 0) */
movl $1, %eax
shll %cl, %eax
decl %eax
andl hold_r, %eax /* eax &= hold */
addl %edx, %eax /* eax += this.val */
movl lcode(%esp), %edx /* edx = lcode */
movl (%edx,%eax,4), %eax /* eax = lcode[val + (hold&mask[op])] */
jmp .L_dolen
.align 16,0x90
.L_test_for_second_level_dist:
/* else if ((op & 64) == 0) {
* this = dcode[this.val + (hold & mask[op])];
* }
*/
testb $64, %al
jnz .L_invalid_distance_code /* if ((op & 64) != 0) */
movl $1, %eax
shll %cl, %eax
decl %eax
andl hold_r, %eax /* eax &= hold */
addl %edx, %eax /* eax += this.val */
movl dcode(%esp), %edx /* edx = dcode */
movl (%edx,%eax,4), %eax /* eax = dcode[val + (hold&mask[op])] */
jmp .L_dodist
.align 16,0x90
.L_clip_window:
/* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist
* %ecx = nbytes
*
* else {
* if (dist > wsize) {
* invalid distance
* }
* from = window;
* nbytes = dist - nbytes;
* if (write == 0) {
* from += wsize - nbytes;
*/
#define nbytes_r %ecx
movl %eax, nbytes_r
movl wsize(%esp), %eax /* prepare for dist compare */
negl nbytes_r /* nbytes = -nbytes */
movl window(%esp), from_r /* from = window */
cmpl dist_r, %eax
jb .L_invalid_distance_too_far /* if (dist > wsize) */
addl dist_r, nbytes_r /* nbytes = dist - nbytes */
cmpl $0, write(%esp)
jne .L_wrap_around_window /* if (write != 0) */
subl nbytes_r, %eax
addl %eax, from_r /* from += wsize - nbytes */
/* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist
* %ecx = nbytes, %eax = len
*
* if (nbytes < len) {
* len -= nbytes;
* do {
* PUP(out) = PUP(from);
* } while (--nbytes);
* from = out - dist;
* }
* }
*/
#define len_r %eax
movl len(%esp), len_r
cmpl nbytes_r, len_r
jbe .L_do_copy1 /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1
cmpl nbytes_r, len_r
jbe .L_do_copy1 /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1
.L_wrap_around_window:
/* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist
* %ecx = nbytes, %eax = write, %eax = len
*
* else if (write < nbytes) {
* from += wsize + write - nbytes;
* nbytes -= write;
* if (nbytes < len) {
* len -= nbytes;
* do {
* PUP(out) = PUP(from);
* } while (--nbytes);
* from = window;
* nbytes = write;
* if (nbytes < len) {
* len -= nbytes;
* do {
* PUP(out) = PUP(from);
* } while(--nbytes);
* from = out - dist;
* }
* }
* }
*/
#define write_r %eax
movl write(%esp), write_r
cmpl write_r, nbytes_r
jbe .L_contiguous_in_window /* if (write >= nbytes) */
addl wsize(%esp), from_r
addl write_r, from_r
subl nbytes_r, from_r /* from += wsize + write - nbytes */
subl write_r, nbytes_r /* nbytes -= write */
#undef write_r
movl len(%esp), len_r
cmpl nbytes_r, len_r
jbe .L_do_copy1 /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl window(%esp), from_r /* from = window */
movl write(%esp), nbytes_r /* nbytes = write */
cmpl nbytes_r, len_r
jbe .L_do_copy1 /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1
.L_contiguous_in_window:
/* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist
* %ecx = nbytes, %eax = write, %eax = len
*
* else {
* from += write - nbytes;
* if (nbytes < len) {
* len -= nbytes;
* do {
* PUP(out) = PUP(from);
* } while (--nbytes);
* from = out - dist;
* }
* }
*/
#define write_r %eax
addl write_r, from_r
subl nbytes_r, from_r /* from += write - nbytes */
#undef write_r
movl len(%esp), len_r
cmpl nbytes_r, len_r
jbe .L_do_copy1 /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
.L_do_copy1:
/* regs: %esi = from, %esi = in, %ebp = hold, %bl = bits, %edi = out
* %eax = len
*
* while (len > 0) {
* PUP(out) = PUP(from);
* len--;
* }
* }
* } while (in < last && out < end);
*/
#undef nbytes_r
#define in_r %esi
movl len_r, %ecx
rep movsb
movl in(%esp), in_r /* move in back to %esi, toss from */
jmp .L_while_test
#undef len_r
#undef dist_r
#endif /* NO_MMX || RUN_TIME_MMX */
/*** MMX code ***/
#if defined( USE_MMX ) || defined( RUN_TIME_MMX )
.align 32,0x90
.L_init_mmx:
emms
#undef bits_r
#undef bitslong_r
#define bitslong_r %ebp
#define hold_mm %mm0
movd %ebp, hold_mm
movl %ebx, bitslong_r
#define used_mm %mm1
#define dmask2_mm %mm2
#define lmask2_mm %mm3
#define lmask_mm %mm4
#define dmask_mm %mm5
#define tmp_mm %mm6
movd lmask(%esp), lmask_mm
movq lmask_mm, lmask2_mm
movd dmask(%esp), dmask_mm
movq dmask_mm, dmask2_mm
pxor used_mm, used_mm
movl lcode(%esp), %ebx /* ebx = lcode */
jmp .L_do_loop_mmx
.align 32,0x90
.L_while_test_mmx:
/* while (in < last && out < end)
*/
cmpl out_r, end(%esp)
jbe .L_break_loop /* if (out >= end) */
cmpl in_r, last(%esp)
jbe .L_break_loop
.L_do_loop_mmx:
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
cmpl $32, bitslong_r
ja .L_get_length_code_mmx /* if (32 < bits) */
movd bitslong_r, tmp_mm
movd (in_r), %mm7
addl $4, in_r
psllq tmp_mm, %mm7
addl $32, bitslong_r
por %mm7, hold_mm /* hold_mm |= *((uint *)in)++ << bits */
.L_get_length_code_mmx:
pand hold_mm, lmask_mm
movd lmask_mm, %eax
movq lmask2_mm, lmask_mm
movl (%ebx,%eax,4), %eax /* eax = lcode[hold & lmask] */
.L_dolen_mmx:
movzbl %ah, %ecx /* ecx = this.bits */
movd %ecx, used_mm
subl %ecx, bitslong_r /* bits -= this.bits */
testb %al, %al
jnz .L_test_for_length_base_mmx /* if (op != 0) 45.7% */
shrl $16, %eax /* output this.val char */
stosb
jmp .L_while_test_mmx
.L_test_for_length_base_mmx:
#define len_r %edx
movl %eax, len_r /* len = this */
shrl $16, len_r /* len = this.val */
testb $16, %al
jz .L_test_for_second_level_length_mmx /* if ((op & 16) == 0) 8% */
andl $15, %eax /* op &= 15 */
jz .L_decode_distance_mmx /* if (!op) */
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
movd %eax, used_mm
movd hold_mm, %ecx
subl %eax, bitslong_r
andl .L_mask(,%eax,4), %ecx
addl %ecx, len_r /* len += hold & mask[op] */
.L_decode_distance_mmx:
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
cmpl $32, bitslong_r
ja .L_get_dist_code_mmx /* if (32 < bits) */
movd bitslong_r, tmp_mm
movd (in_r), %mm7
addl $4, in_r
psllq tmp_mm, %mm7
addl $32, bitslong_r
por %mm7, hold_mm /* hold_mm |= *((uint *)in)++ << bits */
.L_get_dist_code_mmx:
movl dcode(%esp), %ebx /* ebx = dcode */
pand hold_mm, dmask_mm
movd dmask_mm, %eax
movq dmask2_mm, dmask_mm
movl (%ebx,%eax,4), %eax /* eax = dcode[hold & lmask] */
.L_dodist_mmx:
#define dist_r %ebx
movzbl %ah, %ecx /* ecx = this.bits */
movl %eax, dist_r
shrl $16, dist_r /* dist = this.val */
subl %ecx, bitslong_r /* bits -= this.bits */
movd %ecx, used_mm
testb $16, %al /* if ((op & 16) == 0) */
jz .L_test_for_second_level_dist_mmx
andl $15, %eax /* op &= 15 */
jz .L_check_dist_one_mmx
.L_add_bits_to_dist_mmx:
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
movd %eax, used_mm /* save bit length of current op */
movd hold_mm, %ecx /* get the next bits on input stream */
subl %eax, bitslong_r /* bits -= op bits */
andl .L_mask(,%eax,4), %ecx /* ecx = hold & mask[op] */
addl %ecx, dist_r /* dist += hold & mask[op] */
.L_check_window_mmx:
movl in_r, in(%esp) /* save in so from can use it's reg */
movl out_r, %eax
subl beg(%esp), %eax /* nbytes = out - beg */
cmpl dist_r, %eax
jb .L_clip_window_mmx /* if (dist > nbytes) 4.2% */
movl len_r, %ecx
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
subl $3, %ecx
movb (from_r), %al
movb %al, (out_r)
movb 1(from_r), %al
movb 2(from_r), %dl
addl $3, from_r
movb %al, 1(out_r)
movb %dl, 2(out_r)
addl $3, out_r
rep movsb
movl in(%esp), in_r /* move in back to %esi, toss from */
movl lcode(%esp), %ebx /* move lcode back to %ebx, toss dist */
jmp .L_while_test_mmx
.align 16,0x90
.L_check_dist_one_mmx:
cmpl $1, dist_r
jne .L_check_window_mmx
cmpl out_r, beg(%esp)
je .L_check_window_mmx
decl out_r
movl len_r, %ecx
movb (out_r), %al
subl $3, %ecx
movb %al, 1(out_r)
movb %al, 2(out_r)
movb %al, 3(out_r)
addl $4, out_r
rep stosb
movl lcode(%esp), %ebx /* move lcode back to %ebx, toss dist */
jmp .L_while_test_mmx
.align 16,0x90
.L_test_for_second_level_length_mmx:
testb $64, %al
jnz .L_test_for_end_of_block /* if ((op & 64) != 0) */
andl $15, %eax
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
movd hold_mm, %ecx
andl .L_mask(,%eax,4), %ecx
addl len_r, %ecx
movl (%ebx,%ecx,4), %eax /* eax = lcode[hold & lmask] */
jmp .L_dolen_mmx
.align 16,0x90
.L_test_for_second_level_dist_mmx:
testb $64, %al
jnz .L_invalid_distance_code /* if ((op & 64) != 0) */
andl $15, %eax
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
movd hold_mm, %ecx
andl .L_mask(,%eax,4), %ecx
movl dcode(%esp), %eax /* ecx = dcode */
addl dist_r, %ecx
movl (%eax,%ecx,4), %eax /* eax = lcode[hold & lmask] */
jmp .L_dodist_mmx
.align 16,0x90
.L_clip_window_mmx:
#define nbytes_r %ecx
movl %eax, nbytes_r
movl wsize(%esp), %eax /* prepare for dist compare */
negl nbytes_r /* nbytes = -nbytes */
movl window(%esp), from_r /* from = window */
cmpl dist_r, %eax
jb .L_invalid_distance_too_far /* if (dist > wsize) */
addl dist_r, nbytes_r /* nbytes = dist - nbytes */
cmpl $0, write(%esp)
jne .L_wrap_around_window_mmx /* if (write != 0) */
subl nbytes_r, %eax
addl %eax, from_r /* from += wsize - nbytes */
cmpl nbytes_r, len_r
jbe .L_do_copy1_mmx /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1_mmx
cmpl nbytes_r, len_r
jbe .L_do_copy1_mmx /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1_mmx
.L_wrap_around_window_mmx:
#define write_r %eax
movl write(%esp), write_r
cmpl write_r, nbytes_r
jbe .L_contiguous_in_window_mmx /* if (write >= nbytes) */
addl wsize(%esp), from_r
addl write_r, from_r
subl nbytes_r, from_r /* from += wsize + write - nbytes */
subl write_r, nbytes_r /* nbytes -= write */
#undef write_r
cmpl nbytes_r, len_r
jbe .L_do_copy1_mmx /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl window(%esp), from_r /* from = window */
movl write(%esp), nbytes_r /* nbytes = write */
cmpl nbytes_r, len_r
jbe .L_do_copy1_mmx /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1_mmx
.L_contiguous_in_window_mmx:
#define write_r %eax
addl write_r, from_r
subl nbytes_r, from_r /* from += write - nbytes */
#undef write_r
cmpl nbytes_r, len_r
jbe .L_do_copy1_mmx /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
.L_do_copy1_mmx:
#undef nbytes_r
#define in_r %esi
movl len_r, %ecx
rep movsb
movl in(%esp), in_r /* move in back to %esi, toss from */
movl lcode(%esp), %ebx /* move lcode back to %ebx, toss dist */
jmp .L_while_test_mmx
#undef hold_r
#undef bitslong_r
#endif /* USE_MMX || RUN_TIME_MMX */
/*** USE_MMX, NO_MMX, and RUNTIME_MMX from here on ***/
.L_invalid_distance_code:
/* else {
* strm->msg = "invalid distance code";
* state->mode = BAD;
* }
*/
movl $.L_invalid_distance_code_msg, %ecx
movl $INFLATE_MODE_BAD, %edx
jmp .L_update_stream_state
.L_test_for_end_of_block:
/* else if (op & 32) {
* state->mode = TYPE;
* break;
* }
*/
testb $32, %al
jz .L_invalid_literal_length_code /* if ((op & 32) == 0) */
movl $0, %ecx
movl $INFLATE_MODE_TYPE, %edx
jmp .L_update_stream_state
.L_invalid_literal_length_code:
/* else {
* strm->msg = "invalid literal/length code";
* state->mode = BAD;
* }
*/
movl $.L_invalid_literal_length_code_msg, %ecx
movl $INFLATE_MODE_BAD, %edx
jmp .L_update_stream_state
.L_invalid_distance_too_far:
/* strm->msg = "invalid distance too far back";
* state->mode = BAD;
*/
movl in(%esp), in_r /* from_r has in's reg, put in back */
movl $.L_invalid_distance_too_far_msg, %ecx
movl $INFLATE_MODE_BAD, %edx
jmp .L_update_stream_state
.L_update_stream_state:
/* set strm->msg = %ecx, strm->state->mode = %edx */
movl strm_sp(%esp), %eax
testl %ecx, %ecx /* if (msg != NULL) */
jz .L_skip_msg
movl %ecx, msg_strm(%eax) /* strm->msg = msg */
.L_skip_msg:
movl state_strm(%eax), %eax /* state = strm->state */
movl %edx, mode_state(%eax) /* state->mode = edx (BAD | TYPE) */
jmp .L_break_loop
.align 32,0x90
.L_break_loop:
/*
* Regs:
*
* bits = %ebp when mmx, and in %ebx when non-mmx
* hold = %hold_mm when mmx, and in %ebp when non-mmx
* in = %esi
* out = %edi
*/
#if defined( USE_MMX ) || defined( RUN_TIME_MMX )
#if defined( RUN_TIME_MMX )
cmpl $DO_USE_MMX, inflate_fast_use_mmx
jne .L_update_next_in
#endif /* RUN_TIME_MMX */
movl %ebp, %ebx
.L_update_next_in:
#endif
#define strm_r %eax
#define state_r %edx
/* len = bits >> 3;
* in -= len;
* bits -= len << 3;
* hold &= (1U << bits) - 1;
* state->hold = hold;
* state->bits = bits;
* strm->next_in = in;
* strm->next_out = out;
*/
movl strm_sp(%esp), strm_r
movl %ebx, %ecx
movl state_strm(strm_r), state_r
shrl $3, %ecx
subl %ecx, in_r
shll $3, %ecx
subl %ecx, %ebx
movl out_r, next_out_strm(strm_r)
movl %ebx, bits_state(state_r)
movl %ebx, %ecx
leal buf(%esp), %ebx
cmpl %ebx, last(%esp)
jne .L_buf_not_used /* if buf != last */
subl %ebx, in_r /* in -= buf */
movl next_in_strm(strm_r), %ebx
movl %ebx, last(%esp) /* last = strm->next_in */
addl %ebx, in_r /* in += strm->next_in */
movl avail_in_strm(strm_r), %ebx
subl $11, %ebx
addl %ebx, last(%esp) /* last = &strm->next_in[ avail_in - 11 ] */
.L_buf_not_used:
movl in_r, next_in_strm(strm_r)
movl $1, %ebx
shll %cl, %ebx
decl %ebx
#if defined( USE_MMX ) || defined( RUN_TIME_MMX )
#if defined( RUN_TIME_MMX )
cmpl $DO_USE_MMX, inflate_fast_use_mmx
jne .L_update_hold
#endif /* RUN_TIME_MMX */
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
movd hold_mm, %ebp
emms
.L_update_hold:
#endif /* USE_MMX || RUN_TIME_MMX */
andl %ebx, %ebp
movl %ebp, hold_state(state_r)
#define last_r %ebx
/* strm->avail_in = in < last ? 11 + (last - in) : 11 - (in - last) */
movl last(%esp), last_r
cmpl in_r, last_r
jbe .L_last_is_smaller /* if (in >= last) */
subl in_r, last_r /* last -= in */
addl $11, last_r /* last += 11 */
movl last_r, avail_in_strm(strm_r)
jmp .L_fixup_out
.L_last_is_smaller:
subl last_r, in_r /* in -= last */
negl in_r /* in = -in */
addl $11, in_r /* in += 11 */
movl in_r, avail_in_strm(strm_r)
#undef last_r
#define end_r %ebx
.L_fixup_out:
/* strm->avail_out = out < end ? 257 + (end - out) : 257 - (out - end)*/
movl end(%esp), end_r
cmpl out_r, end_r
jbe .L_end_is_smaller /* if (out >= end) */
subl out_r, end_r /* end -= out */
addl $257, end_r /* end += 257 */
movl end_r, avail_out_strm(strm_r)
jmp .L_done
.L_end_is_smaller:
subl end_r, out_r /* out -= end */
negl out_r /* out = -out */
addl $257, out_r /* out += 257 */
movl out_r, avail_out_strm(strm_r)
#undef end_r
#undef strm_r
#undef state_r
.L_done:
addl $local_var_size, %esp
popf
popl %ebx
popl %ebp
popl %esi
popl %edi
ret
#if defined( GAS_ELF )
/* elf info */
.type inflate_fast,@function
.size inflate_fast,.-inflate_fast
#endif
|
yigao/NFShmXFrame | 10,365 | thirdparty/zlib/contrib/asm686/match.S | /* match.S -- x86 assembly version of the zlib longest_match() function.
* Optimized for the Intel 686 chips (PPro and later).
*
* Copyright (C) 1998, 2007 Brian Raiter <breadbox@muppetlabs.com>
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the author be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*/
#ifndef NO_UNDERLINE
#define match_init _match_init
#define longest_match _longest_match
#endif
#define MAX_MATCH (258)
#define MIN_MATCH (3)
#define MIN_LOOKAHEAD (MAX_MATCH + MIN_MATCH + 1)
#define MAX_MATCH_8 ((MAX_MATCH + 7) & ~7)
/* stack frame offsets */
#define chainlenwmask 0 /* high word: current chain len */
/* low word: s->wmask */
#define window 4 /* local copy of s->window */
#define windowbestlen 8 /* s->window + bestlen */
#define scanstart 16 /* first two bytes of string */
#define scanend 12 /* last two bytes of string */
#define scanalign 20 /* dword-misalignment of string */
#define nicematch 24 /* a good enough match size */
#define bestlen 28 /* size of best match so far */
#define scan 32 /* ptr to string wanting match */
#define LocalVarsSize (36)
/* saved ebx 36 */
/* saved edi 40 */
/* saved esi 44 */
/* saved ebp 48 */
/* return address 52 */
#define deflatestate 56 /* the function arguments */
#define curmatch 60
/* All the +zlib1222add offsets are due to the addition of fields
* in zlib in the deflate_state structure since the asm code was first written
* (if you compile with zlib 1.0.4 or older, use "zlib1222add equ (-4)").
* (if you compile with zlib between 1.0.5 and 1.2.2.1, use "zlib1222add equ 0").
* if you compile with zlib 1.2.2.2 or later , use "zlib1222add equ 8").
*/
#define zlib1222add (8)
#define dsWSize (36+zlib1222add)
#define dsWMask (44+zlib1222add)
#define dsWindow (48+zlib1222add)
#define dsPrev (56+zlib1222add)
#define dsMatchLen (88+zlib1222add)
#define dsPrevMatch (92+zlib1222add)
#define dsStrStart (100+zlib1222add)
#define dsMatchStart (104+zlib1222add)
#define dsLookahead (108+zlib1222add)
#define dsPrevLen (112+zlib1222add)
#define dsMaxChainLen (116+zlib1222add)
#define dsGoodMatch (132+zlib1222add)
#define dsNiceMatch (136+zlib1222add)
.file "match.S"
.globl match_init, longest_match
.text
/* uInt longest_match(deflate_state *deflatestate, IPos curmatch) */
.cfi_sections .debug_frame
longest_match:
.cfi_startproc
/* Save registers that the compiler may be using, and adjust %esp to */
/* make room for our stack frame. */
pushl %ebp
.cfi_def_cfa_offset 8
.cfi_offset ebp, -8
pushl %edi
.cfi_def_cfa_offset 12
pushl %esi
.cfi_def_cfa_offset 16
pushl %ebx
.cfi_def_cfa_offset 20
subl $LocalVarsSize, %esp
.cfi_def_cfa_offset LocalVarsSize+20
/* Retrieve the function arguments. %ecx will hold cur_match */
/* throughout the entire function. %edx will hold the pointer to the */
/* deflate_state structure during the function's setup (before */
/* entering the main loop). */
movl deflatestate(%esp), %edx
movl curmatch(%esp), %ecx
/* uInt wmask = s->w_mask; */
/* unsigned chain_length = s->max_chain_length; */
/* if (s->prev_length >= s->good_match) { */
/* chain_length >>= 2; */
/* } */
movl dsPrevLen(%edx), %eax
movl dsGoodMatch(%edx), %ebx
cmpl %ebx, %eax
movl dsWMask(%edx), %eax
movl dsMaxChainLen(%edx), %ebx
jl LastMatchGood
shrl $2, %ebx
LastMatchGood:
/* chainlen is decremented once beforehand so that the function can */
/* use the sign flag instead of the zero flag for the exit test. */
/* It is then shifted into the high word, to make room for the wmask */
/* value, which it will always accompany. */
decl %ebx
shll $16, %ebx
orl %eax, %ebx
movl %ebx, chainlenwmask(%esp)
/* if ((uInt)nice_match > s->lookahead) nice_match = s->lookahead; */
movl dsNiceMatch(%edx), %eax
movl dsLookahead(%edx), %ebx
cmpl %eax, %ebx
jl LookaheadLess
movl %eax, %ebx
LookaheadLess: movl %ebx, nicematch(%esp)
/* register Bytef *scan = s->window + s->strstart; */
movl dsWindow(%edx), %esi
movl %esi, window(%esp)
movl dsStrStart(%edx), %ebp
lea (%esi,%ebp), %edi
movl %edi, scan(%esp)
/* Determine how many bytes the scan ptr is off from being */
/* dword-aligned. */
movl %edi, %eax
negl %eax
andl $3, %eax
movl %eax, scanalign(%esp)
/* IPos limit = s->strstart > (IPos)MAX_DIST(s) ? */
/* s->strstart - (IPos)MAX_DIST(s) : NIL; */
movl dsWSize(%edx), %eax
subl $MIN_LOOKAHEAD, %eax
subl %eax, %ebp
jg LimitPositive
xorl %ebp, %ebp
LimitPositive:
/* int best_len = s->prev_length; */
movl dsPrevLen(%edx), %eax
movl %eax, bestlen(%esp)
/* Store the sum of s->window + best_len in %esi locally, and in %esi. */
addl %eax, %esi
movl %esi, windowbestlen(%esp)
/* register ush scan_start = *(ushf*)scan; */
/* register ush scan_end = *(ushf*)(scan+best_len-1); */
/* Posf *prev = s->prev; */
movzwl (%edi), %ebx
movl %ebx, scanstart(%esp)
movzwl -1(%edi,%eax), %ebx
movl %ebx, scanend(%esp)
movl dsPrev(%edx), %edi
/* Jump into the main loop. */
movl chainlenwmask(%esp), %edx
jmp LoopEntry
.balign 16
/* do {
* match = s->window + cur_match;
* if (*(ushf*)(match+best_len-1) != scan_end ||
* *(ushf*)match != scan_start) continue;
* [...]
* } while ((cur_match = prev[cur_match & wmask]) > limit
* && --chain_length != 0);
*
* Here is the inner loop of the function. The function will spend the
* majority of its time in this loop, and majority of that time will
* be spent in the first ten instructions.
*
* Within this loop:
* %ebx = scanend
* %ecx = curmatch
* %edx = chainlenwmask - i.e., ((chainlen << 16) | wmask)
* %esi = windowbestlen - i.e., (window + bestlen)
* %edi = prev
* %ebp = limit
*/
LookupLoop:
andl %edx, %ecx
movzwl (%edi,%ecx,2), %ecx
cmpl %ebp, %ecx
jbe LeaveNow
subl $0x00010000, %edx
js LeaveNow
LoopEntry: movzwl -1(%esi,%ecx), %eax
cmpl %ebx, %eax
jnz LookupLoop
movl window(%esp), %eax
movzwl (%eax,%ecx), %eax
cmpl scanstart(%esp), %eax
jnz LookupLoop
/* Store the current value of chainlen. */
movl %edx, chainlenwmask(%esp)
/* Point %edi to the string under scrutiny, and %esi to the string we */
/* are hoping to match it up with. In actuality, %esi and %edi are */
/* both pointed (MAX_MATCH_8 - scanalign) bytes ahead, and %edx is */
/* initialized to -(MAX_MATCH_8 - scanalign). */
movl window(%esp), %esi
movl scan(%esp), %edi
addl %ecx, %esi
movl scanalign(%esp), %eax
movl $(-MAX_MATCH_8), %edx
lea MAX_MATCH_8(%edi,%eax), %edi
lea MAX_MATCH_8(%esi,%eax), %esi
/* Test the strings for equality, 8 bytes at a time. At the end,
* adjust %edx so that it is offset to the exact byte that mismatched.
*
* We already know at this point that the first three bytes of the
* strings match each other, and they can be safely passed over before
* starting the compare loop. So what this code does is skip over 0-3
* bytes, as much as necessary in order to dword-align the %edi
* pointer. (%esi will still be misaligned three times out of four.)
*
* It should be confessed that this loop usually does not represent
* much of the total running time. Replacing it with a more
* straightforward "rep cmpsb" would not drastically degrade
* performance.
*/
LoopCmps:
movl (%esi,%edx), %eax
xorl (%edi,%edx), %eax
jnz LeaveLoopCmps
movl 4(%esi,%edx), %eax
xorl 4(%edi,%edx), %eax
jnz LeaveLoopCmps4
addl $8, %edx
jnz LoopCmps
jmp LenMaximum
LeaveLoopCmps4: addl $4, %edx
LeaveLoopCmps: testl $0x0000FFFF, %eax
jnz LenLower
addl $2, %edx
shrl $16, %eax
LenLower: subb $1, %al
adcl $0, %edx
/* Calculate the length of the match. If it is longer than MAX_MATCH, */
/* then automatically accept it as the best possible match and leave. */
lea (%edi,%edx), %eax
movl scan(%esp), %edi
subl %edi, %eax
cmpl $MAX_MATCH, %eax
jge LenMaximum
/* If the length of the match is not longer than the best match we */
/* have so far, then forget it and return to the lookup loop. */
movl deflatestate(%esp), %edx
movl bestlen(%esp), %ebx
cmpl %ebx, %eax
jg LongerMatch
movl windowbestlen(%esp), %esi
movl dsPrev(%edx), %edi
movl scanend(%esp), %ebx
movl chainlenwmask(%esp), %edx
jmp LookupLoop
/* s->match_start = cur_match; */
/* best_len = len; */
/* if (len >= nice_match) break; */
/* scan_end = *(ushf*)(scan+best_len-1); */
LongerMatch: movl nicematch(%esp), %ebx
movl %eax, bestlen(%esp)
movl %ecx, dsMatchStart(%edx)
cmpl %ebx, %eax
jge LeaveNow
movl window(%esp), %esi
addl %eax, %esi
movl %esi, windowbestlen(%esp)
movzwl -1(%edi,%eax), %ebx
movl dsPrev(%edx), %edi
movl %ebx, scanend(%esp)
movl chainlenwmask(%esp), %edx
jmp LookupLoop
/* Accept the current string, with the maximum possible length. */
LenMaximum: movl deflatestate(%esp), %edx
movl $MAX_MATCH, bestlen(%esp)
movl %ecx, dsMatchStart(%edx)
/* if ((uInt)best_len <= s->lookahead) return (uInt)best_len; */
/* return s->lookahead; */
LeaveNow:
movl deflatestate(%esp), %edx
movl bestlen(%esp), %ebx
movl dsLookahead(%edx), %eax
cmpl %eax, %ebx
jg LookaheadRet
movl %ebx, %eax
LookaheadRet:
/* Restore the stack and return from whence we came. */
addl $LocalVarsSize, %esp
.cfi_def_cfa_offset 20
popl %ebx
.cfi_def_cfa_offset 16
popl %esi
.cfi_def_cfa_offset 12
popl %edi
.cfi_def_cfa_offset 8
popl %ebp
.cfi_def_cfa_offset 4
.cfi_endproc
match_init: ret
|
yigao/NFShmXFrame | 15,839 | thirdparty/zlib/contrib/gcc_gvmat64/gvmat64.S | /*
;uInt longest_match_x64(
; deflate_state *s,
; IPos cur_match); // current match
; gvmat64.S -- Asm portion of the optimized longest_match for 32 bits x86_64
; (AMD64 on Athlon 64, Opteron, Phenom
; and Intel EM64T on Pentium 4 with EM64T, Pentium D, Core 2 Duo, Core I5/I7)
; this file is translation from gvmat64.asm to GCC 4.x (for Linux, Mac XCode)
; Copyright (C) 1995-2010 Jean-loup Gailly, Brian Raiter and Gilles Vollant.
;
; File written by Gilles Vollant, by converting to assembly the longest_match
; from Jean-loup Gailly in deflate.c of zLib and infoZip zip.
; and by taking inspiration on asm686 with masm, optimised assembly code
; from Brian Raiter, written 1998
;
; This software is provided 'as-is', without any express or implied
; warranty. In no event will the authors be held liable for any damages
; arising from the use of this software.
;
; Permission is granted to anyone to use this software for any purpose,
; including commercial applications, and to alter it and redistribute it
; freely, subject to the following restrictions:
;
; 1. The origin of this software must not be misrepresented; you must not
; claim that you wrote the original software. If you use this software
; in a product, an acknowledgment in the product documentation would be
; appreciated but is not required.
; 2. Altered source versions must be plainly marked as such, and must not be
; misrepresented as being the original software
; 3. This notice may not be removed or altered from any source distribution.
;
; http://www.zlib.net
; http://www.winimage.com/zLibDll
; http://www.muppetlabs.com/~breadbox/software/assembly.html
;
; to compile this file for zLib, I use option:
; gcc -c -arch x86_64 gvmat64.S
;uInt longest_match(s, cur_match)
; deflate_state *s;
; IPos cur_match; // current match /
;
; with XCode for Mac, I had strange error with some jump on intel syntax
; this is why BEFORE_JMP and AFTER_JMP are used
*/
#define BEFORE_JMP .att_syntax
#define AFTER_JMP .intel_syntax noprefix
#ifndef NO_UNDERLINE
# define match_init _match_init
# define longest_match _longest_match
#endif
.intel_syntax noprefix
.globl match_init, longest_match
.text
longest_match:
#define LocalVarsSize 96
/*
; register used : rax,rbx,rcx,rdx,rsi,rdi,r8,r9,r10,r11,r12
; free register : r14,r15
; register can be saved : rsp
*/
#define chainlenwmask (rsp + 8 - LocalVarsSize)
#define nicematch (rsp + 16 - LocalVarsSize)
#define save_rdi (rsp + 24 - LocalVarsSize)
#define save_rsi (rsp + 32 - LocalVarsSize)
#define save_rbx (rsp + 40 - LocalVarsSize)
#define save_rbp (rsp + 48 - LocalVarsSize)
#define save_r12 (rsp + 56 - LocalVarsSize)
#define save_r13 (rsp + 64 - LocalVarsSize)
#define save_r14 (rsp + 72 - LocalVarsSize)
#define save_r15 (rsp + 80 - LocalVarsSize)
/*
; all the +4 offsets are due to the addition of pending_buf_size (in zlib
; in the deflate_state structure since the asm code was first written
; (if you compile with zlib 1.0.4 or older, remove the +4).
; Note : these value are good with a 8 bytes boundary pack structure
*/
#define MAX_MATCH 258
#define MIN_MATCH 3
#define MIN_LOOKAHEAD (MAX_MATCH+MIN_MATCH+1)
/*
;;; Offsets for fields in the deflate_state structure. These numbers
;;; are calculated from the definition of deflate_state, with the
;;; assumption that the compiler will dword-align the fields. (Thus,
;;; changing the definition of deflate_state could easily cause this
;;; program to crash horribly, without so much as a warning at
;;; compile time. Sigh.)
; all the +zlib1222add offsets are due to the addition of fields
; in zlib in the deflate_state structure since the asm code was first written
; (if you compile with zlib 1.0.4 or older, use "zlib1222add equ (-4)").
; (if you compile with zlib between 1.0.5 and 1.2.2.1, use "zlib1222add equ 0").
; if you compile with zlib 1.2.2.2 or later , use "zlib1222add equ 8").
*/
/* you can check the structure offset by running
#include <stdlib.h>
#include <stdio.h>
#include "deflate.h"
void print_depl()
{
deflate_state ds;
deflate_state *s=&ds;
printf("size pointer=%u\n",(int)sizeof(void*));
printf("#define dsWSize %u\n",(int)(((char*)&(s->w_size))-((char*)s)));
printf("#define dsWMask %u\n",(int)(((char*)&(s->w_mask))-((char*)s)));
printf("#define dsWindow %u\n",(int)(((char*)&(s->window))-((char*)s)));
printf("#define dsPrev %u\n",(int)(((char*)&(s->prev))-((char*)s)));
printf("#define dsMatchLen %u\n",(int)(((char*)&(s->match_length))-((char*)s)));
printf("#define dsPrevMatch %u\n",(int)(((char*)&(s->prev_match))-((char*)s)));
printf("#define dsStrStart %u\n",(int)(((char*)&(s->strstart))-((char*)s)));
printf("#define dsMatchStart %u\n",(int)(((char*)&(s->match_start))-((char*)s)));
printf("#define dsLookahead %u\n",(int)(((char*)&(s->lookahead))-((char*)s)));
printf("#define dsPrevLen %u\n",(int)(((char*)&(s->prev_length))-((char*)s)));
printf("#define dsMaxChainLen %u\n",(int)(((char*)&(s->max_chain_length))-((char*)s)));
printf("#define dsGoodMatch %u\n",(int)(((char*)&(s->good_match))-((char*)s)));
printf("#define dsNiceMatch %u\n",(int)(((char*)&(s->nice_match))-((char*)s)));
}
*/
#define dsWSize 68
#define dsWMask 76
#define dsWindow 80
#define dsPrev 96
#define dsMatchLen 144
#define dsPrevMatch 148
#define dsStrStart 156
#define dsMatchStart 160
#define dsLookahead 164
#define dsPrevLen 168
#define dsMaxChainLen 172
#define dsGoodMatch 188
#define dsNiceMatch 192
#define window_size [ rcx + dsWSize]
#define WMask [ rcx + dsWMask]
#define window_ad [ rcx + dsWindow]
#define prev_ad [ rcx + dsPrev]
#define strstart [ rcx + dsStrStart]
#define match_start [ rcx + dsMatchStart]
#define Lookahead [ rcx + dsLookahead] //; 0ffffffffh on infozip
#define prev_length [ rcx + dsPrevLen]
#define max_chain_length [ rcx + dsMaxChainLen]
#define good_match [ rcx + dsGoodMatch]
#define nice_match [ rcx + dsNiceMatch]
/*
; windows:
; parameter 1 in rcx(deflate state s), param 2 in rdx (cur match)
; see http://weblogs.asp.net/oldnewthing/archive/2004/01/14/58579.aspx and
; http://msdn.microsoft.com/library/en-us/kmarch/hh/kmarch/64bitAMD_8e951dd2-ee77-4728-8702-55ce4b5dd24a.xml.asp
;
; All registers must be preserved across the call, except for
; rax, rcx, rdx, r8, r9, r10, and r11, which are scratch.
;
; gcc on macosx-linux:
; see http://www.x86-64.org/documentation/abi-0.99.pdf
; param 1 in rdi, param 2 in rsi
; rbx, rsp, rbp, r12 to r15 must be preserved
;;; Save registers that the compiler may be using, and adjust esp to
;;; make room for our stack frame.
;;; Retrieve the function arguments. r8d will hold cur_match
;;; throughout the entire function. edx will hold the pointer to the
;;; deflate_state structure during the function's setup (before
;;; entering the main loop.
; ms: parameter 1 in rcx (deflate_state* s), param 2 in edx -> r8 (cur match)
; mac: param 1 in rdi, param 2 rsi
; this clear high 32 bits of r8, which can be garbage in both r8 and rdx
*/
mov [save_rbx],rbx
mov [save_rbp],rbp
mov rcx,rdi
mov r8d,esi
mov [save_r12],r12
mov [save_r13],r13
mov [save_r14],r14
mov [save_r15],r15
//;;; uInt wmask = s->w_mask;
//;;; unsigned chain_length = s->max_chain_length;
//;;; if (s->prev_length >= s->good_match) {
//;;; chain_length >>= 2;
//;;; }
mov edi, prev_length
mov esi, good_match
mov eax, WMask
mov ebx, max_chain_length
cmp edi, esi
jl LastMatchGood
shr ebx, 2
LastMatchGood:
//;;; chainlen is decremented once beforehand so that the function can
//;;; use the sign flag instead of the zero flag for the exit test.
//;;; It is then shifted into the high word, to make room for the wmask
//;;; value, which it will always accompany.
dec ebx
shl ebx, 16
or ebx, eax
//;;; on zlib only
//;;; if ((uInt)nice_match > s->lookahead) nice_match = s->lookahead;
mov eax, nice_match
mov [chainlenwmask], ebx
mov r10d, Lookahead
cmp r10d, eax
cmovnl r10d, eax
mov [nicematch],r10d
//;;; register Bytef *scan = s->window + s->strstart;
mov r10, window_ad
mov ebp, strstart
lea r13, [r10 + rbp]
//;;; Determine how many bytes the scan ptr is off from being
//;;; dword-aligned.
mov r9,r13
neg r13
and r13,3
//;;; IPos limit = s->strstart > (IPos)MAX_DIST(s) ?
//;;; s->strstart - (IPos)MAX_DIST(s) : NIL;
mov eax, window_size
sub eax, MIN_LOOKAHEAD
xor edi,edi
sub ebp, eax
mov r11d, prev_length
cmovng ebp,edi
//;;; int best_len = s->prev_length;
//;;; Store the sum of s->window + best_len in esi locally, and in esi.
lea rsi,[r10+r11]
//;;; register ush scan_start = *(ushf*)scan;
//;;; register ush scan_end = *(ushf*)(scan+best_len-1);
//;;; Posf *prev = s->prev;
movzx r12d,word ptr [r9]
movzx ebx, word ptr [r9 + r11 - 1]
mov rdi, prev_ad
//;;; Jump into the main loop.
mov edx, [chainlenwmask]
cmp bx,word ptr [rsi + r8 - 1]
jz LookupLoopIsZero
LookupLoop1:
and r8d, edx
movzx r8d, word ptr [rdi + r8*2]
cmp r8d, ebp
jbe LeaveNow
sub edx, 0x00010000
BEFORE_JMP
js LeaveNow
AFTER_JMP
LoopEntry1:
cmp bx,word ptr [rsi + r8 - 1]
BEFORE_JMP
jz LookupLoopIsZero
AFTER_JMP
LookupLoop2:
and r8d, edx
movzx r8d, word ptr [rdi + r8*2]
cmp r8d, ebp
BEFORE_JMP
jbe LeaveNow
AFTER_JMP
sub edx, 0x00010000
BEFORE_JMP
js LeaveNow
AFTER_JMP
LoopEntry2:
cmp bx,word ptr [rsi + r8 - 1]
BEFORE_JMP
jz LookupLoopIsZero
AFTER_JMP
LookupLoop4:
and r8d, edx
movzx r8d, word ptr [rdi + r8*2]
cmp r8d, ebp
BEFORE_JMP
jbe LeaveNow
AFTER_JMP
sub edx, 0x00010000
BEFORE_JMP
js LeaveNow
AFTER_JMP
LoopEntry4:
cmp bx,word ptr [rsi + r8 - 1]
BEFORE_JMP
jnz LookupLoop1
jmp LookupLoopIsZero
AFTER_JMP
/*
;;; do {
;;; match = s->window + cur_match;
;;; if (*(ushf*)(match+best_len-1) != scan_end ||
;;; *(ushf*)match != scan_start) continue;
;;; [...]
;;; } while ((cur_match = prev[cur_match & wmask]) > limit
;;; && --chain_length != 0);
;;;
;;; Here is the inner loop of the function. The function will spend the
;;; majority of its time in this loop, and majority of that time will
;;; be spent in the first ten instructions.
;;;
;;; Within this loop:
;;; ebx = scanend
;;; r8d = curmatch
;;; edx = chainlenwmask - i.e., ((chainlen << 16) | wmask)
;;; esi = windowbestlen - i.e., (window + bestlen)
;;; edi = prev
;;; ebp = limit
*/
.balign 16
LookupLoop:
and r8d, edx
movzx r8d, word ptr [rdi + r8*2]
cmp r8d, ebp
BEFORE_JMP
jbe LeaveNow
AFTER_JMP
sub edx, 0x00010000
BEFORE_JMP
js LeaveNow
AFTER_JMP
LoopEntry:
cmp bx,word ptr [rsi + r8 - 1]
BEFORE_JMP
jnz LookupLoop1
AFTER_JMP
LookupLoopIsZero:
cmp r12w, word ptr [r10 + r8]
BEFORE_JMP
jnz LookupLoop1
AFTER_JMP
//;;; Store the current value of chainlen.
mov [chainlenwmask], edx
/*
;;; Point edi to the string under scrutiny, and esi to the string we
;;; are hoping to match it up with. In actuality, esi and edi are
;;; both pointed (MAX_MATCH_8 - scanalign) bytes ahead, and edx is
;;; initialized to -(MAX_MATCH_8 - scanalign).
*/
lea rsi,[r8+r10]
mov rdx, 0xfffffffffffffef8 //; -(MAX_MATCH_8)
lea rsi, [rsi + r13 + 0x0108] //;MAX_MATCH_8]
lea rdi, [r9 + r13 + 0x0108] //;MAX_MATCH_8]
prefetcht1 [rsi+rdx]
prefetcht1 [rdi+rdx]
/*
;;; Test the strings for equality, 8 bytes at a time. At the end,
;;; adjust rdx so that it is offset to the exact byte that mismatched.
;;;
;;; We already know at this point that the first three bytes of the
;;; strings match each other, and they can be safely passed over before
;;; starting the compare loop. So what this code does is skip over 0-3
;;; bytes, as much as necessary in order to dword-align the edi
;;; pointer. (rsi will still be misaligned three times out of four.)
;;;
;;; It should be confessed that this loop usually does not represent
;;; much of the total running time. Replacing it with a more
;;; straightforward "rep cmpsb" would not drastically degrade
;;; performance.
*/
LoopCmps:
mov rax, [rsi + rdx]
xor rax, [rdi + rdx]
jnz LeaveLoopCmps
mov rax, [rsi + rdx + 8]
xor rax, [rdi + rdx + 8]
jnz LeaveLoopCmps8
mov rax, [rsi + rdx + 8+8]
xor rax, [rdi + rdx + 8+8]
jnz LeaveLoopCmps16
add rdx,8+8+8
BEFORE_JMP
jnz LoopCmps
jmp LenMaximum
AFTER_JMP
LeaveLoopCmps16: add rdx,8
LeaveLoopCmps8: add rdx,8
LeaveLoopCmps:
test eax, 0x0000FFFF
jnz LenLower
test eax,0xffffffff
jnz LenLower32
add rdx,4
shr rax,32
or ax,ax
BEFORE_JMP
jnz LenLower
AFTER_JMP
LenLower32:
shr eax,16
add rdx,2
LenLower:
sub al, 1
adc rdx, 0
//;;; Calculate the length of the match. If it is longer than MAX_MATCH,
//;;; then automatically accept it as the best possible match and leave.
lea rax, [rdi + rdx]
sub rax, r9
cmp eax, MAX_MATCH
BEFORE_JMP
jge LenMaximum
AFTER_JMP
/*
;;; If the length of the match is not longer than the best match we
;;; have so far, then forget it and return to the lookup loop.
;///////////////////////////////////
*/
cmp eax, r11d
jg LongerMatch
lea rsi,[r10+r11]
mov rdi, prev_ad
mov edx, [chainlenwmask]
BEFORE_JMP
jmp LookupLoop
AFTER_JMP
/*
;;; s->match_start = cur_match;
;;; best_len = len;
;;; if (len >= nice_match) break;
;;; scan_end = *(ushf*)(scan+best_len-1);
*/
LongerMatch:
mov r11d, eax
mov match_start, r8d
cmp eax, [nicematch]
BEFORE_JMP
jge LeaveNow
AFTER_JMP
lea rsi,[r10+rax]
movzx ebx, word ptr [r9 + rax - 1]
mov rdi, prev_ad
mov edx, [chainlenwmask]
BEFORE_JMP
jmp LookupLoop
AFTER_JMP
//;;; Accept the current string, with the maximum possible length.
LenMaximum:
mov r11d,MAX_MATCH
mov match_start, r8d
//;;; if ((uInt)best_len <= s->lookahead) return (uInt)best_len;
//;;; return s->lookahead;
LeaveNow:
mov eax, Lookahead
cmp r11d, eax
cmovng eax, r11d
//;;; Restore the stack and return from whence we came.
// mov rsi,[save_rsi]
// mov rdi,[save_rdi]
mov rbx,[save_rbx]
mov rbp,[save_rbp]
mov r12,[save_r12]
mov r13,[save_r13]
mov r14,[save_r14]
mov r15,[save_r15]
ret 0
//; please don't remove this string !
//; Your can freely use gvmat64 in any free or commercial app
//; but it is far better don't remove the string in the binary!
// db 0dh,0ah,"asm686 with masm, optimised assembly code from Brian Raiter, written 1998, converted to amd 64 by Gilles Vollant 2005",0dh,0ah,0
match_init:
ret 0
|
yigao/NFShmXFrame | 12,418 | thirdparty/zlib/contrib/amd64/amd64-match.S | /*
* match.S -- optimized version of longest_match()
* based on the similar work by Gilles Vollant, and Brian Raiter, written 1998
*
* This is free software; you can redistribute it and/or modify it
* under the terms of the BSD License. Use by owners of Che Guevarra
* parafernalia is prohibited, where possible, and highly discouraged
* elsewhere.
*/
#ifndef NO_UNDERLINE
# define match_init _match_init
# define longest_match _longest_match
#endif
#define scanend ebx
#define scanendw bx
#define chainlenwmask edx /* high word: current chain len low word: s->wmask */
#define curmatch rsi
#define curmatchd esi
#define windowbestlen r8
#define scanalign r9
#define scanalignd r9d
#define window r10
#define bestlen r11
#define bestlend r11d
#define scanstart r12d
#define scanstartw r12w
#define scan r13
#define nicematch r14d
#define limit r15
#define limitd r15d
#define prev rcx
/*
* The 258 is a "magic number, not a parameter -- changing it
* breaks the hell loose
*/
#define MAX_MATCH (258)
#define MIN_MATCH (3)
#define MIN_LOOKAHEAD (MAX_MATCH + MIN_MATCH + 1)
#define MAX_MATCH_8 ((MAX_MATCH + 7) & ~7)
/* stack frame offsets */
#define LocalVarsSize (112)
#define _chainlenwmask ( 8-LocalVarsSize)(%rsp)
#define _windowbestlen (16-LocalVarsSize)(%rsp)
#define save_r14 (24-LocalVarsSize)(%rsp)
#define save_rsi (32-LocalVarsSize)(%rsp)
#define save_rbx (40-LocalVarsSize)(%rsp)
#define save_r12 (56-LocalVarsSize)(%rsp)
#define save_r13 (64-LocalVarsSize)(%rsp)
#define save_r15 (80-LocalVarsSize)(%rsp)
.globl match_init, longest_match
/*
* On AMD64 the first argument of a function (in our case -- the pointer to
* deflate_state structure) is passed in %rdi, hence our offsets below are
* all off of that.
*/
/* you can check the structure offset by running
#include <stdlib.h>
#include <stdio.h>
#include "deflate.h"
void print_depl()
{
deflate_state ds;
deflate_state *s=&ds;
printf("size pointer=%u\n",(int)sizeof(void*));
printf("#define dsWSize (%3u)(%%rdi)\n",(int)(((char*)&(s->w_size))-((char*)s)));
printf("#define dsWMask (%3u)(%%rdi)\n",(int)(((char*)&(s->w_mask))-((char*)s)));
printf("#define dsWindow (%3u)(%%rdi)\n",(int)(((char*)&(s->window))-((char*)s)));
printf("#define dsPrev (%3u)(%%rdi)\n",(int)(((char*)&(s->prev))-((char*)s)));
printf("#define dsMatchLen (%3u)(%%rdi)\n",(int)(((char*)&(s->match_length))-((char*)s)));
printf("#define dsPrevMatch (%3u)(%%rdi)\n",(int)(((char*)&(s->prev_match))-((char*)s)));
printf("#define dsStrStart (%3u)(%%rdi)\n",(int)(((char*)&(s->strstart))-((char*)s)));
printf("#define dsMatchStart (%3u)(%%rdi)\n",(int)(((char*)&(s->match_start))-((char*)s)));
printf("#define dsLookahead (%3u)(%%rdi)\n",(int)(((char*)&(s->lookahead))-((char*)s)));
printf("#define dsPrevLen (%3u)(%%rdi)\n",(int)(((char*)&(s->prev_length))-((char*)s)));
printf("#define dsMaxChainLen (%3u)(%%rdi)\n",(int)(((char*)&(s->max_chain_length))-((char*)s)));
printf("#define dsGoodMatch (%3u)(%%rdi)\n",(int)(((char*)&(s->good_match))-((char*)s)));
printf("#define dsNiceMatch (%3u)(%%rdi)\n",(int)(((char*)&(s->nice_match))-((char*)s)));
}
*/
/*
to compile for XCode 3.2 on MacOSX x86_64
- run "gcc -g -c -DXCODE_MAC_X64_STRUCTURE amd64-match.S"
*/
#ifndef CURRENT_LINX_XCODE_MAC_X64_STRUCTURE
#define dsWSize ( 68)(%rdi)
#define dsWMask ( 76)(%rdi)
#define dsWindow ( 80)(%rdi)
#define dsPrev ( 96)(%rdi)
#define dsMatchLen (144)(%rdi)
#define dsPrevMatch (148)(%rdi)
#define dsStrStart (156)(%rdi)
#define dsMatchStart (160)(%rdi)
#define dsLookahead (164)(%rdi)
#define dsPrevLen (168)(%rdi)
#define dsMaxChainLen (172)(%rdi)
#define dsGoodMatch (188)(%rdi)
#define dsNiceMatch (192)(%rdi)
#else
#ifndef STRUCT_OFFSET
# define STRUCT_OFFSET (0)
#endif
#define dsWSize ( 56 + STRUCT_OFFSET)(%rdi)
#define dsWMask ( 64 + STRUCT_OFFSET)(%rdi)
#define dsWindow ( 72 + STRUCT_OFFSET)(%rdi)
#define dsPrev ( 88 + STRUCT_OFFSET)(%rdi)
#define dsMatchLen (136 + STRUCT_OFFSET)(%rdi)
#define dsPrevMatch (140 + STRUCT_OFFSET)(%rdi)
#define dsStrStart (148 + STRUCT_OFFSET)(%rdi)
#define dsMatchStart (152 + STRUCT_OFFSET)(%rdi)
#define dsLookahead (156 + STRUCT_OFFSET)(%rdi)
#define dsPrevLen (160 + STRUCT_OFFSET)(%rdi)
#define dsMaxChainLen (164 + STRUCT_OFFSET)(%rdi)
#define dsGoodMatch (180 + STRUCT_OFFSET)(%rdi)
#define dsNiceMatch (184 + STRUCT_OFFSET)(%rdi)
#endif
.text
/* uInt longest_match(deflate_state *deflatestate, IPos curmatch) */
longest_match:
/*
* Retrieve the function arguments. %curmatch will hold cur_match
* throughout the entire function (passed via rsi on amd64).
* rdi will hold the pointer to the deflate_state (first arg on amd64)
*/
mov %rsi, save_rsi
mov %rbx, save_rbx
mov %r12, save_r12
mov %r13, save_r13
mov %r14, save_r14
mov %r15, save_r15
/* uInt wmask = s->w_mask; */
/* unsigned chain_length = s->max_chain_length; */
/* if (s->prev_length >= s->good_match) { */
/* chain_length >>= 2; */
/* } */
movl dsPrevLen, %eax
movl dsGoodMatch, %ebx
cmpl %ebx, %eax
movl dsWMask, %eax
movl dsMaxChainLen, %chainlenwmask
jl LastMatchGood
shrl $2, %chainlenwmask
LastMatchGood:
/* chainlen is decremented once beforehand so that the function can */
/* use the sign flag instead of the zero flag for the exit test. */
/* It is then shifted into the high word, to make room for the wmask */
/* value, which it will always accompany. */
decl %chainlenwmask
shll $16, %chainlenwmask
orl %eax, %chainlenwmask
/* if ((uInt)nice_match > s->lookahead) nice_match = s->lookahead; */
movl dsNiceMatch, %eax
movl dsLookahead, %ebx
cmpl %eax, %ebx
jl LookaheadLess
movl %eax, %ebx
LookaheadLess: movl %ebx, %nicematch
/* register Bytef *scan = s->window + s->strstart; */
mov dsWindow, %window
movl dsStrStart, %limitd
lea (%limit, %window), %scan
/* Determine how many bytes the scan ptr is off from being */
/* dword-aligned. */
mov %scan, %scanalign
negl %scanalignd
andl $3, %scanalignd
/* IPos limit = s->strstart > (IPos)MAX_DIST(s) ? */
/* s->strstart - (IPos)MAX_DIST(s) : NIL; */
movl dsWSize, %eax
subl $MIN_LOOKAHEAD, %eax
xorl %ecx, %ecx
subl %eax, %limitd
cmovng %ecx, %limitd
/* int best_len = s->prev_length; */
movl dsPrevLen, %bestlend
/* Store the sum of s->window + best_len in %windowbestlen locally, and in memory. */
lea (%window, %bestlen), %windowbestlen
mov %windowbestlen, _windowbestlen
/* register ush scan_start = *(ushf*)scan; */
/* register ush scan_end = *(ushf*)(scan+best_len-1); */
/* Posf *prev = s->prev; */
movzwl (%scan), %scanstart
movzwl -1(%scan, %bestlen), %scanend
mov dsPrev, %prev
/* Jump into the main loop. */
movl %chainlenwmask, _chainlenwmask
jmp LoopEntry
.balign 16
/* do {
* match = s->window + cur_match;
* if (*(ushf*)(match+best_len-1) != scan_end ||
* *(ushf*)match != scan_start) continue;
* [...]
* } while ((cur_match = prev[cur_match & wmask]) > limit
* && --chain_length != 0);
*
* Here is the inner loop of the function. The function will spend the
* majority of its time in this loop, and majority of that time will
* be spent in the first ten instructions.
*/
LookupLoop:
andl %chainlenwmask, %curmatchd
movzwl (%prev, %curmatch, 2), %curmatchd
cmpl %limitd, %curmatchd
jbe LeaveNow
subl $0x00010000, %chainlenwmask
js LeaveNow
LoopEntry: cmpw -1(%windowbestlen, %curmatch), %scanendw
jne LookupLoop
cmpw %scanstartw, (%window, %curmatch)
jne LookupLoop
/* Store the current value of chainlen. */
movl %chainlenwmask, _chainlenwmask
/* %scan is the string under scrutiny, and %prev to the string we */
/* are hoping to match it up with. In actuality, %esi and %edi are */
/* both pointed (MAX_MATCH_8 - scanalign) bytes ahead, and %edx is */
/* initialized to -(MAX_MATCH_8 - scanalign). */
mov $(-MAX_MATCH_8), %rdx
lea (%curmatch, %window), %windowbestlen
lea MAX_MATCH_8(%windowbestlen, %scanalign), %windowbestlen
lea MAX_MATCH_8(%scan, %scanalign), %prev
/* the prefetching below makes very little difference... */
prefetcht1 (%windowbestlen, %rdx)
prefetcht1 (%prev, %rdx)
/*
* Test the strings for equality, 8 bytes at a time. At the end,
* adjust %rdx so that it is offset to the exact byte that mismatched.
*
* It should be confessed that this loop usually does not represent
* much of the total running time. Replacing it with a more
* straightforward "rep cmpsb" would not drastically degrade
* performance -- unrolling it, for example, makes no difference.
*/
#undef USE_SSE /* works, but is 6-7% slower, than non-SSE... */
LoopCmps:
#ifdef USE_SSE
/* Preload the SSE registers */
movdqu (%windowbestlen, %rdx), %xmm1
movdqu (%prev, %rdx), %xmm2
pcmpeqb %xmm2, %xmm1
movdqu 16(%windowbestlen, %rdx), %xmm3
movdqu 16(%prev, %rdx), %xmm4
pcmpeqb %xmm4, %xmm3
movdqu 32(%windowbestlen, %rdx), %xmm5
movdqu 32(%prev, %rdx), %xmm6
pcmpeqb %xmm6, %xmm5
movdqu 48(%windowbestlen, %rdx), %xmm7
movdqu 48(%prev, %rdx), %xmm8
pcmpeqb %xmm8, %xmm7
/* Check the comparisions' results */
pmovmskb %xmm1, %rax
notw %ax
bsfw %ax, %ax
jnz LeaveLoopCmps
/* this is the only iteration of the loop with a possibility of having
incremented rdx by 0x108 (each loop iteration add 16*4 = 0x40
and (0x40*4)+8=0x108 */
add $8, %rdx
jz LenMaximum
add $8, %rdx
pmovmskb %xmm3, %rax
notw %ax
bsfw %ax, %ax
jnz LeaveLoopCmps
add $16, %rdx
pmovmskb %xmm5, %rax
notw %ax
bsfw %ax, %ax
jnz LeaveLoopCmps
add $16, %rdx
pmovmskb %xmm7, %rax
notw %ax
bsfw %ax, %ax
jnz LeaveLoopCmps
add $16, %rdx
jmp LoopCmps
LeaveLoopCmps: add %rax, %rdx
#else
mov (%windowbestlen, %rdx), %rax
xor (%prev, %rdx), %rax
jnz LeaveLoopCmps
mov 8(%windowbestlen, %rdx), %rax
xor 8(%prev, %rdx), %rax
jnz LeaveLoopCmps8
mov 16(%windowbestlen, %rdx), %rax
xor 16(%prev, %rdx), %rax
jnz LeaveLoopCmps16
add $24, %rdx
jnz LoopCmps
jmp LenMaximum
# if 0
/*
* This three-liner is tantalizingly simple, but bsf is a slow instruction,
* and the complicated alternative down below is quite a bit faster. Sad...
*/
LeaveLoopCmps: bsf %rax, %rax /* find the first non-zero bit */
shrl $3, %eax /* divide by 8 to get the byte */
add %rax, %rdx
# else
LeaveLoopCmps16:
add $8, %rdx
LeaveLoopCmps8:
add $8, %rdx
LeaveLoopCmps: testl $0xFFFFFFFF, %eax /* Check the first 4 bytes */
jnz Check16
add $4, %rdx
shr $32, %rax
Check16: testw $0xFFFF, %ax
jnz LenLower
add $2, %rdx
shrl $16, %eax
LenLower: subb $1, %al
adc $0, %rdx
# endif
#endif
/* Calculate the length of the match. If it is longer than MAX_MATCH, */
/* then automatically accept it as the best possible match and leave. */
lea (%prev, %rdx), %rax
sub %scan, %rax
cmpl $MAX_MATCH, %eax
jge LenMaximum
/* If the length of the match is not longer than the best match we */
/* have so far, then forget it and return to the lookup loop. */
cmpl %bestlend, %eax
jg LongerMatch
mov _windowbestlen, %windowbestlen
mov dsPrev, %prev
movl _chainlenwmask, %edx
jmp LookupLoop
/* s->match_start = cur_match; */
/* best_len = len; */
/* if (len >= nice_match) break; */
/* scan_end = *(ushf*)(scan+best_len-1); */
LongerMatch:
movl %eax, %bestlend
movl %curmatchd, dsMatchStart
cmpl %nicematch, %eax
jge LeaveNow
lea (%window, %bestlen), %windowbestlen
mov %windowbestlen, _windowbestlen
movzwl -1(%scan, %rax), %scanend
mov dsPrev, %prev
movl _chainlenwmask, %chainlenwmask
jmp LookupLoop
/* Accept the current string, with the maximum possible length. */
LenMaximum:
movl $MAX_MATCH, %bestlend
movl %curmatchd, dsMatchStart
/* if ((uInt)best_len <= s->lookahead) return (uInt)best_len; */
/* return s->lookahead; */
LeaveNow:
movl dsLookahead, %eax
cmpl %eax, %bestlend
cmovngl %bestlend, %eax
LookaheadRet:
/* Restore the registers and return from whence we came. */
mov save_rsi, %rsi
mov save_rbx, %rbx
mov save_r12, %r12
mov save_r13, %r13
mov save_r14, %r14
mov save_r15, %r15
ret
match_init: ret
|
0verflowme/kvm_play | 86 | guest.S | .globl _start
.code16
_start:
xorw %ax, %ax
loop:
out %ax, $0x10
inc %ax
jmp loop |
01nstagram/Meus-projetos | 933 | go/pkg/mod/golang.org/x/sys@v0.32.0/cpu/cpu_arm64.s | // Copyright 2019 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
//go:build gc
#include "textflag.h"
// func getisar0() uint64
TEXT ·getisar0(SB),NOSPLIT,$0-8
// get Instruction Set Attributes 0 into x0
// mrs x0, ID_AA64ISAR0_EL1 = d5380600
WORD $0xd5380600
MOVD R0, ret+0(FP)
RET
// func getisar1() uint64
TEXT ·getisar1(SB),NOSPLIT,$0-8
// get Instruction Set Attributes 1 into x0
// mrs x0, ID_AA64ISAR1_EL1 = d5380620
WORD $0xd5380620
MOVD R0, ret+0(FP)
RET
// func getpfr0() uint64
TEXT ·getpfr0(SB),NOSPLIT,$0-8
// get Processor Feature Register 0 into x0
// mrs x0, ID_AA64PFR0_EL1 = d5380400
WORD $0xd5380400
MOVD R0, ret+0(FP)
RET
// func getzfr0() uint64
TEXT ·getzfr0(SB),NOSPLIT,$0-8
// get SVE Feature Register 0 into x0
// mrs x0, ID_AA64ZFR0_EL1 = d5380480
WORD $0xd5380480
MOVD R0, ret+0(FP)
RET
|
01nstagram/Meus-projetos | 628 | go/pkg/mod/golang.org/x/sys@v0.32.0/cpu/asm_darwin_x86_gc.s | // Copyright 2024 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
//go:build darwin && amd64 && gc
#include "textflag.h"
TEXT libc_sysctl_trampoline<>(SB),NOSPLIT,$0-0
JMP libc_sysctl(SB)
GLOBL ·libc_sysctl_trampoline_addr(SB), RODATA, $8
DATA ·libc_sysctl_trampoline_addr(SB)/8, $libc_sysctl_trampoline<>(SB)
TEXT libc_sysctlbyname_trampoline<>(SB),NOSPLIT,$0-0
JMP libc_sysctlbyname(SB)
GLOBL ·libc_sysctlbyname_trampoline_addr(SB), RODATA, $8
DATA ·libc_sysctlbyname_trampoline_addr(SB)/8, $libc_sysctlbyname_trampoline<>(SB)
|
01nstagram/Meus-projetos | 2,000 | go/pkg/mod/golang.org/x/sys@v0.32.0/cpu/cpu_s390x.s | // Copyright 2019 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
//go:build gc
#include "textflag.h"
// func stfle() facilityList
TEXT ·stfle(SB), NOSPLIT|NOFRAME, $0-32
MOVD $ret+0(FP), R1
MOVD $3, R0 // last doubleword index to store
XC $32, (R1), (R1) // clear 4 doublewords (32 bytes)
WORD $0xb2b01000 // store facility list extended (STFLE)
RET
// func kmQuery() queryResult
TEXT ·kmQuery(SB), NOSPLIT|NOFRAME, $0-16
MOVD $0, R0 // set function code to 0 (KM-Query)
MOVD $ret+0(FP), R1 // address of 16-byte return value
WORD $0xB92E0024 // cipher message (KM)
RET
// func kmcQuery() queryResult
TEXT ·kmcQuery(SB), NOSPLIT|NOFRAME, $0-16
MOVD $0, R0 // set function code to 0 (KMC-Query)
MOVD $ret+0(FP), R1 // address of 16-byte return value
WORD $0xB92F0024 // cipher message with chaining (KMC)
RET
// func kmctrQuery() queryResult
TEXT ·kmctrQuery(SB), NOSPLIT|NOFRAME, $0-16
MOVD $0, R0 // set function code to 0 (KMCTR-Query)
MOVD $ret+0(FP), R1 // address of 16-byte return value
WORD $0xB92D4024 // cipher message with counter (KMCTR)
RET
// func kmaQuery() queryResult
TEXT ·kmaQuery(SB), NOSPLIT|NOFRAME, $0-16
MOVD $0, R0 // set function code to 0 (KMA-Query)
MOVD $ret+0(FP), R1 // address of 16-byte return value
WORD $0xb9296024 // cipher message with authentication (KMA)
RET
// func kimdQuery() queryResult
TEXT ·kimdQuery(SB), NOSPLIT|NOFRAME, $0-16
MOVD $0, R0 // set function code to 0 (KIMD-Query)
MOVD $ret+0(FP), R1 // address of 16-byte return value
WORD $0xB93E0024 // compute intermediate message digest (KIMD)
RET
// func klmdQuery() queryResult
TEXT ·klmdQuery(SB), NOSPLIT|NOFRAME, $0-16
MOVD $0, R0 // set function code to 0 (KLMD-Query)
MOVD $ret+0(FP), R1 // address of 16-byte return value
WORD $0xB93F0024 // compute last message digest (KLMD)
RET
|
01nstagram/Meus-projetos | 403 | go/pkg/mod/golang.org/x/sys@v0.32.0/cpu/asm_aix_ppc64.s | // Copyright 2018 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
//go:build gc
#include "textflag.h"
//
// System calls for ppc64, AIX are implemented in runtime/syscall_aix.go
//
TEXT ·syscall6(SB),NOSPLIT,$0-88
JMP syscall·syscall6(SB)
TEXT ·rawSyscall6(SB),NOSPLIT,$0-88
JMP syscall·rawSyscall6(SB)
|
01nstagram/Meus-projetos | 600 | go/pkg/mod/golang.org/x/sys@v0.32.0/cpu/cpu_gc_x86.s | // Copyright 2018 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
//go:build (386 || amd64 || amd64p32) && gc
#include "textflag.h"
// func cpuid(eaxArg, ecxArg uint32) (eax, ebx, ecx, edx uint32)
TEXT ·cpuid(SB), NOSPLIT, $0-24
MOVL eaxArg+0(FP), AX
MOVL ecxArg+4(FP), CX
CPUID
MOVL AX, eax+8(FP)
MOVL BX, ebx+12(FP)
MOVL CX, ecx+16(FP)
MOVL DX, edx+20(FP)
RET
// func xgetbv() (eax, edx uint32)
TEXT ·xgetbv(SB), NOSPLIT, $0-8
MOVL $0, CX
XGETBV
MOVL AX, eax+0(FP)
MOVL DX, edx+4(FP)
RET
|
01nstagram/Meus-projetos | 357 | go/pkg/mod/golang.org/x/sys@v0.32.0/cpu/cpu_loong64.s | // Copyright 2025 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
#include "textflag.h"
// func get_cpucfg(reg uint32) uint32
TEXT ·get_cpucfg(SB), NOSPLIT|NOFRAME, $0
MOVW reg+0(FP), R5
// CPUCFG R5, R4 = 0x00006ca4
WORD $0x00006ca4
MOVW R4, ret+8(FP)
RET
|
01nstagram/Meus-projetos | 374 | go/pkg/mod/golang.org/x/sys@v0.32.0/cpu/cpu_openbsd_arm64.s | // Copyright 2022 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
#include "textflag.h"
TEXT libc_sysctl_trampoline<>(SB),NOSPLIT,$0-0
JMP libc_sysctl(SB)
GLOBL ·libc_sysctl_trampoline_addr(SB), RODATA, $8
DATA ·libc_sysctl_trampoline_addr(SB)/8, $libc_sysctl_trampoline<>(SB)
|
01nstagram/Meus-projetos | 1,029 | go/pkg/mod/golang.org/x/sys@v0.32.0/unix/asm_linux_riscv64.s | // Copyright 2019 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
//go:build riscv64 && gc
#include "textflag.h"
//
// System calls for linux/riscv64.
//
// Where available, just jump to package syscall's implementation of
// these functions.
TEXT ·Syscall(SB),NOSPLIT,$0-56
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
JMP syscall·Syscall6(SB)
TEXT ·SyscallNoError(SB),NOSPLIT,$0-48
CALL runtime·entersyscall(SB)
MOV a1+8(FP), A0
MOV a2+16(FP), A1
MOV a3+24(FP), A2
MOV trap+0(FP), A7 // syscall entry
ECALL
MOV A0, r1+32(FP) // r1
MOV A1, r2+40(FP) // r2
CALL runtime·exitsyscall(SB)
RET
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
JMP syscall·RawSyscall6(SB)
TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-48
MOV a1+8(FP), A0
MOV a2+16(FP), A1
MOV a3+24(FP), A2
MOV trap+0(FP), A7 // syscall entry
ECALL
MOV A0, r1+32(FP)
MOV A1, r2+40(FP)
RET
|
01nstagram/Meus-projetos | 686 | go/pkg/mod/golang.org/x/sys@v0.32.0/unix/asm_bsd_386.s | // Copyright 2021 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
//go:build (freebsd || netbsd || openbsd) && gc
#include "textflag.h"
// System call support for 386 BSD
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-28
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-40
JMP syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-52
JMP syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-28
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-40
JMP syscall·RawSyscall6(SB)
|
01nstagram/Meus-projetos | 905 | go/pkg/mod/golang.org/x/sys@v0.32.0/unix/asm_linux_ppc64x.s | // Copyright 2014 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
//go:build linux && (ppc64 || ppc64le) && gc
#include "textflag.h"
//
// System calls for ppc64, Linux
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·SyscallNoError(SB),NOSPLIT,$0-48
BL runtime·entersyscall(SB)
MOVD a1+8(FP), R3
MOVD a2+16(FP), R4
MOVD a3+24(FP), R5
MOVD R0, R6
MOVD R0, R7
MOVD R0, R8
MOVD trap+0(FP), R9 // syscall entry
SYSCALL R9
MOVD R3, r1+32(FP)
MOVD R4, r2+40(FP)
BL runtime·exitsyscall(SB)
RET
TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-48
MOVD a1+8(FP), R3
MOVD a2+16(FP), R4
MOVD a3+24(FP), R5
MOVD R0, R6
MOVD R0, R7
MOVD R0, R8
MOVD trap+0(FP), R9 // syscall entry
SYSCALL R9
MOVD R3, r1+32(FP)
MOVD R4, r2+40(FP)
RET
|
01nstagram/Meus-projetos | 1,171 | go/pkg/mod/golang.org/x/sys@v0.32.0/unix/asm_linux_loong64.s | // Copyright 2022 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
//go:build linux && loong64 && gc
#include "textflag.h"
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
JMP syscall·Syscall6(SB)
TEXT ·SyscallNoError(SB),NOSPLIT,$0-48
JAL runtime·entersyscall(SB)
MOVV a1+8(FP), R4
MOVV a2+16(FP), R5
MOVV a3+24(FP), R6
MOVV R0, R7
MOVV R0, R8
MOVV R0, R9
MOVV trap+0(FP), R11 // syscall entry
SYSCALL
MOVV R4, r1+32(FP)
MOVV R0, r2+40(FP) // r2 is not used. Always set to 0
JAL runtime·exitsyscall(SB)
RET
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
JMP syscall·RawSyscall6(SB)
TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-48
MOVV a1+8(FP), R4
MOVV a2+16(FP), R5
MOVV a3+24(FP), R6
MOVV R0, R7
MOVV R0, R8
MOVV R0, R9
MOVV trap+0(FP), R11 // syscall entry
SYSCALL
MOVV R4, r1+32(FP)
MOVV R0, r2+40(FP) // r2 is not used. Always set to 0
RET
|
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