repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
LucaWilliams4831/vSdk | 28,453 | crypto/keys/secp256k1/internal/secp256k1/libsecp256k1/src/asm/field_10x26_arm.s | @ vim: set tabstop=8 softtabstop=8 shiftwidth=8 noexpandtab syntax=armasm:
/**********************************************************************
* Copyright (c) 2014 Wladimir J. van der Laan *
* Distributed under the MIT software license, see the accompanying *
* file COPYING or http://www.opensource.org/licenses/mit-license.php.*
**********************************************************************/
/*
ARM implementation of field_10x26 inner loops.
Note:
- To avoid unnecessary loads and make use of available registers, two
'passes' have every time been interleaved, with the odd passes accumulating c' and d'
which will be added to c and d respectively in the even passes
*/
.syntax unified
.arch armv7-a
@ eabi attributes - see readelf -A
.eabi_attribute 8, 1 @ Tag_ARM_ISA_use = yes
.eabi_attribute 9, 0 @ Tag_Thumb_ISA_use = no
.eabi_attribute 10, 0 @ Tag_FP_arch = none
.eabi_attribute 24, 1 @ Tag_ABI_align_needed = 8-byte
.eabi_attribute 25, 1 @ Tag_ABI_align_preserved = 8-byte, except leaf SP
.eabi_attribute 30, 2 @ Tag_ABI_optimization_goals = Aggressive Speed
.eabi_attribute 34, 1 @ Tag_CPU_unaligned_access = v6
.text
@ Field constants
.set field_R0, 0x3d10
.set field_R1, 0x400
.set field_not_M, 0xfc000000 @ ~M = ~0x3ffffff
.align 2
.global secp256k1_fe_mul_inner
.type secp256k1_fe_mul_inner, %function
@ Arguments:
@ r0 r Restrict: can overlap with a, not with b
@ r1 a
@ r2 b
@ Stack (total 4+10*4 = 44)
@ sp + #0 saved 'r' pointer
@ sp + #4 + 4*X t0,t1,t2,t3,t4,t5,t6,t7,u8,t9
secp256k1_fe_mul_inner:
stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, r14}
sub sp, sp, #48 @ frame=44 + alignment
str r0, [sp, #0] @ save result address, we need it only at the end
/******************************************
* Main computation code.
******************************************
Allocation:
r0,r14,r7,r8 scratch
r1 a (pointer)
r2 b (pointer)
r3:r4 c
r5:r6 d
r11:r12 c'
r9:r10 d'
Note: do not write to r[] here, it may overlap with a[]
*/
/* A - interleaved with B */
ldr r7, [r1, #0*4] @ a[0]
ldr r8, [r2, #9*4] @ b[9]
ldr r0, [r1, #1*4] @ a[1]
umull r5, r6, r7, r8 @ d = a[0] * b[9]
ldr r14, [r2, #8*4] @ b[8]
umull r9, r10, r0, r8 @ d' = a[1] * b[9]
ldr r7, [r1, #2*4] @ a[2]
umlal r5, r6, r0, r14 @ d += a[1] * b[8]
ldr r8, [r2, #7*4] @ b[7]
umlal r9, r10, r7, r14 @ d' += a[2] * b[8]
ldr r0, [r1, #3*4] @ a[3]
umlal r5, r6, r7, r8 @ d += a[2] * b[7]
ldr r14, [r2, #6*4] @ b[6]
umlal r9, r10, r0, r8 @ d' += a[3] * b[7]
ldr r7, [r1, #4*4] @ a[4]
umlal r5, r6, r0, r14 @ d += a[3] * b[6]
ldr r8, [r2, #5*4] @ b[5]
umlal r9, r10, r7, r14 @ d' += a[4] * b[6]
ldr r0, [r1, #5*4] @ a[5]
umlal r5, r6, r7, r8 @ d += a[4] * b[5]
ldr r14, [r2, #4*4] @ b[4]
umlal r9, r10, r0, r8 @ d' += a[5] * b[5]
ldr r7, [r1, #6*4] @ a[6]
umlal r5, r6, r0, r14 @ d += a[5] * b[4]
ldr r8, [r2, #3*4] @ b[3]
umlal r9, r10, r7, r14 @ d' += a[6] * b[4]
ldr r0, [r1, #7*4] @ a[7]
umlal r5, r6, r7, r8 @ d += a[6] * b[3]
ldr r14, [r2, #2*4] @ b[2]
umlal r9, r10, r0, r8 @ d' += a[7] * b[3]
ldr r7, [r1, #8*4] @ a[8]
umlal r5, r6, r0, r14 @ d += a[7] * b[2]
ldr r8, [r2, #1*4] @ b[1]
umlal r9, r10, r7, r14 @ d' += a[8] * b[2]
ldr r0, [r1, #9*4] @ a[9]
umlal r5, r6, r7, r8 @ d += a[8] * b[1]
ldr r14, [r2, #0*4] @ b[0]
umlal r9, r10, r0, r8 @ d' += a[9] * b[1]
ldr r7, [r1, #0*4] @ a[0]
umlal r5, r6, r0, r14 @ d += a[9] * b[0]
@ r7,r14 used in B
bic r0, r5, field_not_M @ t9 = d & M
str r0, [sp, #4 + 4*9]
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
/* B */
umull r3, r4, r7, r14 @ c = a[0] * b[0]
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u0 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u0 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t0 = c & M
str r14, [sp, #4 + 0*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u0 * R1
umlal r3, r4, r0, r14
/* C - interleaved with D */
ldr r7, [r1, #0*4] @ a[0]
ldr r8, [r2, #2*4] @ b[2]
ldr r14, [r2, #1*4] @ b[1]
umull r11, r12, r7, r8 @ c' = a[0] * b[2]
ldr r0, [r1, #1*4] @ a[1]
umlal r3, r4, r7, r14 @ c += a[0] * b[1]
ldr r8, [r2, #0*4] @ b[0]
umlal r11, r12, r0, r14 @ c' += a[1] * b[1]
ldr r7, [r1, #2*4] @ a[2]
umlal r3, r4, r0, r8 @ c += a[1] * b[0]
ldr r14, [r2, #9*4] @ b[9]
umlal r11, r12, r7, r8 @ c' += a[2] * b[0]
ldr r0, [r1, #3*4] @ a[3]
umlal r5, r6, r7, r14 @ d += a[2] * b[9]
ldr r8, [r2, #8*4] @ b[8]
umull r9, r10, r0, r14 @ d' = a[3] * b[9]
ldr r7, [r1, #4*4] @ a[4]
umlal r5, r6, r0, r8 @ d += a[3] * b[8]
ldr r14, [r2, #7*4] @ b[7]
umlal r9, r10, r7, r8 @ d' += a[4] * b[8]
ldr r0, [r1, #5*4] @ a[5]
umlal r5, r6, r7, r14 @ d += a[4] * b[7]
ldr r8, [r2, #6*4] @ b[6]
umlal r9, r10, r0, r14 @ d' += a[5] * b[7]
ldr r7, [r1, #6*4] @ a[6]
umlal r5, r6, r0, r8 @ d += a[5] * b[6]
ldr r14, [r2, #5*4] @ b[5]
umlal r9, r10, r7, r8 @ d' += a[6] * b[6]
ldr r0, [r1, #7*4] @ a[7]
umlal r5, r6, r7, r14 @ d += a[6] * b[5]
ldr r8, [r2, #4*4] @ b[4]
umlal r9, r10, r0, r14 @ d' += a[7] * b[5]
ldr r7, [r1, #8*4] @ a[8]
umlal r5, r6, r0, r8 @ d += a[7] * b[4]
ldr r14, [r2, #3*4] @ b[3]
umlal r9, r10, r7, r8 @ d' += a[8] * b[4]
ldr r0, [r1, #9*4] @ a[9]
umlal r5, r6, r7, r14 @ d += a[8] * b[3]
ldr r8, [r2, #2*4] @ b[2]
umlal r9, r10, r0, r14 @ d' += a[9] * b[3]
umlal r5, r6, r0, r8 @ d += a[9] * b[2]
bic r0, r5, field_not_M @ u1 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u1 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t1 = c & M
str r14, [sp, #4 + 1*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u1 * R1
umlal r3, r4, r0, r14
/* D */
adds r3, r3, r11 @ c += c'
adc r4, r4, r12
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u2 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u2 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t2 = c & M
str r14, [sp, #4 + 2*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u2 * R1
umlal r3, r4, r0, r14
/* E - interleaved with F */
ldr r7, [r1, #0*4] @ a[0]
ldr r8, [r2, #4*4] @ b[4]
umull r11, r12, r7, r8 @ c' = a[0] * b[4]
ldr r8, [r2, #3*4] @ b[3]
umlal r3, r4, r7, r8 @ c += a[0] * b[3]
ldr r7, [r1, #1*4] @ a[1]
umlal r11, r12, r7, r8 @ c' += a[1] * b[3]
ldr r8, [r2, #2*4] @ b[2]
umlal r3, r4, r7, r8 @ c += a[1] * b[2]
ldr r7, [r1, #2*4] @ a[2]
umlal r11, r12, r7, r8 @ c' += a[2] * b[2]
ldr r8, [r2, #1*4] @ b[1]
umlal r3, r4, r7, r8 @ c += a[2] * b[1]
ldr r7, [r1, #3*4] @ a[3]
umlal r11, r12, r7, r8 @ c' += a[3] * b[1]
ldr r8, [r2, #0*4] @ b[0]
umlal r3, r4, r7, r8 @ c += a[3] * b[0]
ldr r7, [r1, #4*4] @ a[4]
umlal r11, r12, r7, r8 @ c' += a[4] * b[0]
ldr r8, [r2, #9*4] @ b[9]
umlal r5, r6, r7, r8 @ d += a[4] * b[9]
ldr r7, [r1, #5*4] @ a[5]
umull r9, r10, r7, r8 @ d' = a[5] * b[9]
ldr r8, [r2, #8*4] @ b[8]
umlal r5, r6, r7, r8 @ d += a[5] * b[8]
ldr r7, [r1, #6*4] @ a[6]
umlal r9, r10, r7, r8 @ d' += a[6] * b[8]
ldr r8, [r2, #7*4] @ b[7]
umlal r5, r6, r7, r8 @ d += a[6] * b[7]
ldr r7, [r1, #7*4] @ a[7]
umlal r9, r10, r7, r8 @ d' += a[7] * b[7]
ldr r8, [r2, #6*4] @ b[6]
umlal r5, r6, r7, r8 @ d += a[7] * b[6]
ldr r7, [r1, #8*4] @ a[8]
umlal r9, r10, r7, r8 @ d' += a[8] * b[6]
ldr r8, [r2, #5*4] @ b[5]
umlal r5, r6, r7, r8 @ d += a[8] * b[5]
ldr r7, [r1, #9*4] @ a[9]
umlal r9, r10, r7, r8 @ d' += a[9] * b[5]
ldr r8, [r2, #4*4] @ b[4]
umlal r5, r6, r7, r8 @ d += a[9] * b[4]
bic r0, r5, field_not_M @ u3 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u3 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t3 = c & M
str r14, [sp, #4 + 3*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u3 * R1
umlal r3, r4, r0, r14
/* F */
adds r3, r3, r11 @ c += c'
adc r4, r4, r12
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u4 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u4 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t4 = c & M
str r14, [sp, #4 + 4*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u4 * R1
umlal r3, r4, r0, r14
/* G - interleaved with H */
ldr r7, [r1, #0*4] @ a[0]
ldr r8, [r2, #6*4] @ b[6]
ldr r14, [r2, #5*4] @ b[5]
umull r11, r12, r7, r8 @ c' = a[0] * b[6]
ldr r0, [r1, #1*4] @ a[1]
umlal r3, r4, r7, r14 @ c += a[0] * b[5]
ldr r8, [r2, #4*4] @ b[4]
umlal r11, r12, r0, r14 @ c' += a[1] * b[5]
ldr r7, [r1, #2*4] @ a[2]
umlal r3, r4, r0, r8 @ c += a[1] * b[4]
ldr r14, [r2, #3*4] @ b[3]
umlal r11, r12, r7, r8 @ c' += a[2] * b[4]
ldr r0, [r1, #3*4] @ a[3]
umlal r3, r4, r7, r14 @ c += a[2] * b[3]
ldr r8, [r2, #2*4] @ b[2]
umlal r11, r12, r0, r14 @ c' += a[3] * b[3]
ldr r7, [r1, #4*4] @ a[4]
umlal r3, r4, r0, r8 @ c += a[3] * b[2]
ldr r14, [r2, #1*4] @ b[1]
umlal r11, r12, r7, r8 @ c' += a[4] * b[2]
ldr r0, [r1, #5*4] @ a[5]
umlal r3, r4, r7, r14 @ c += a[4] * b[1]
ldr r8, [r2, #0*4] @ b[0]
umlal r11, r12, r0, r14 @ c' += a[5] * b[1]
ldr r7, [r1, #6*4] @ a[6]
umlal r3, r4, r0, r8 @ c += a[5] * b[0]
ldr r14, [r2, #9*4] @ b[9]
umlal r11, r12, r7, r8 @ c' += a[6] * b[0]
ldr r0, [r1, #7*4] @ a[7]
umlal r5, r6, r7, r14 @ d += a[6] * b[9]
ldr r8, [r2, #8*4] @ b[8]
umull r9, r10, r0, r14 @ d' = a[7] * b[9]
ldr r7, [r1, #8*4] @ a[8]
umlal r5, r6, r0, r8 @ d += a[7] * b[8]
ldr r14, [r2, #7*4] @ b[7]
umlal r9, r10, r7, r8 @ d' += a[8] * b[8]
ldr r0, [r1, #9*4] @ a[9]
umlal r5, r6, r7, r14 @ d += a[8] * b[7]
ldr r8, [r2, #6*4] @ b[6]
umlal r9, r10, r0, r14 @ d' += a[9] * b[7]
umlal r5, r6, r0, r8 @ d += a[9] * b[6]
bic r0, r5, field_not_M @ u5 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u5 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t5 = c & M
str r14, [sp, #4 + 5*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u5 * R1
umlal r3, r4, r0, r14
/* H */
adds r3, r3, r11 @ c += c'
adc r4, r4, r12
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u6 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u6 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t6 = c & M
str r14, [sp, #4 + 6*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u6 * R1
umlal r3, r4, r0, r14
/* I - interleaved with J */
ldr r8, [r2, #8*4] @ b[8]
ldr r7, [r1, #0*4] @ a[0]
ldr r14, [r2, #7*4] @ b[7]
umull r11, r12, r7, r8 @ c' = a[0] * b[8]
ldr r0, [r1, #1*4] @ a[1]
umlal r3, r4, r7, r14 @ c += a[0] * b[7]
ldr r8, [r2, #6*4] @ b[6]
umlal r11, r12, r0, r14 @ c' += a[1] * b[7]
ldr r7, [r1, #2*4] @ a[2]
umlal r3, r4, r0, r8 @ c += a[1] * b[6]
ldr r14, [r2, #5*4] @ b[5]
umlal r11, r12, r7, r8 @ c' += a[2] * b[6]
ldr r0, [r1, #3*4] @ a[3]
umlal r3, r4, r7, r14 @ c += a[2] * b[5]
ldr r8, [r2, #4*4] @ b[4]
umlal r11, r12, r0, r14 @ c' += a[3] * b[5]
ldr r7, [r1, #4*4] @ a[4]
umlal r3, r4, r0, r8 @ c += a[3] * b[4]
ldr r14, [r2, #3*4] @ b[3]
umlal r11, r12, r7, r8 @ c' += a[4] * b[4]
ldr r0, [r1, #5*4] @ a[5]
umlal r3, r4, r7, r14 @ c += a[4] * b[3]
ldr r8, [r2, #2*4] @ b[2]
umlal r11, r12, r0, r14 @ c' += a[5] * b[3]
ldr r7, [r1, #6*4] @ a[6]
umlal r3, r4, r0, r8 @ c += a[5] * b[2]
ldr r14, [r2, #1*4] @ b[1]
umlal r11, r12, r7, r8 @ c' += a[6] * b[2]
ldr r0, [r1, #7*4] @ a[7]
umlal r3, r4, r7, r14 @ c += a[6] * b[1]
ldr r8, [r2, #0*4] @ b[0]
umlal r11, r12, r0, r14 @ c' += a[7] * b[1]
ldr r7, [r1, #8*4] @ a[8]
umlal r3, r4, r0, r8 @ c += a[7] * b[0]
ldr r14, [r2, #9*4] @ b[9]
umlal r11, r12, r7, r8 @ c' += a[8] * b[0]
ldr r0, [r1, #9*4] @ a[9]
umlal r5, r6, r7, r14 @ d += a[8] * b[9]
ldr r8, [r2, #8*4] @ b[8]
umull r9, r10, r0, r14 @ d' = a[9] * b[9]
umlal r5, r6, r0, r8 @ d += a[9] * b[8]
bic r0, r5, field_not_M @ u7 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u7 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t7 = c & M
str r14, [sp, #4 + 7*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u7 * R1
umlal r3, r4, r0, r14
/* J */
adds r3, r3, r11 @ c += c'
adc r4, r4, r12
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u8 = d & M
str r0, [sp, #4 + 8*4]
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u8 * R0
umlal r3, r4, r0, r14
/******************************************
* compute and write back result
******************************************
Allocation:
r0 r
r3:r4 c
r5:r6 d
r7 t0
r8 t1
r9 t2
r11 u8
r12 t9
r1,r2,r10,r14 scratch
Note: do not read from a[] after here, it may overlap with r[]
*/
ldr r0, [sp, #0]
add r1, sp, #4 + 3*4 @ r[3..7] = t3..7, r11=u8, r12=t9
ldmia r1, {r2,r7,r8,r9,r10,r11,r12}
add r1, r0, #3*4
stmia r1, {r2,r7,r8,r9,r10}
bic r2, r3, field_not_M @ r[8] = c & M
str r2, [r0, #8*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u8 * R1
umlal r3, r4, r11, r14
movw r14, field_R0 @ c += d * R0
umlal r3, r4, r5, r14
adds r3, r3, r12 @ c += t9
adc r4, r4, #0
add r1, sp, #4 + 0*4 @ r7,r8,r9 = t0,t1,t2
ldmia r1, {r7,r8,r9}
ubfx r2, r3, #0, #22 @ r[9] = c & (M >> 4)
str r2, [r0, #9*4]
mov r3, r3, lsr #22 @ c >>= 22
orr r3, r3, r4, asl #10
mov r4, r4, lsr #22
movw r14, field_R1 << 4 @ c += d * (R1 << 4)
umlal r3, r4, r5, r14
movw r14, field_R0 >> 4 @ d = c * (R0 >> 4) + t0 (64x64 multiply+add)
umull r5, r6, r3, r14 @ d = c.lo * (R0 >> 4)
adds r5, r5, r7 @ d.lo += t0
mla r6, r14, r4, r6 @ d.hi += c.hi * (R0 >> 4)
adc r6, r6, 0 @ d.hi += carry
bic r2, r5, field_not_M @ r[0] = d & M
str r2, [r0, #0*4]
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R1 >> 4 @ d += c * (R1 >> 4) + t1 (64x64 multiply+add)
umull r1, r2, r3, r14 @ tmp = c.lo * (R1 >> 4)
adds r5, r5, r8 @ d.lo += t1
adc r6, r6, #0 @ d.hi += carry
adds r5, r5, r1 @ d.lo += tmp.lo
mla r2, r14, r4, r2 @ tmp.hi += c.hi * (R1 >> 4)
adc r6, r6, r2 @ d.hi += carry + tmp.hi
bic r2, r5, field_not_M @ r[1] = d & M
str r2, [r0, #1*4]
mov r5, r5, lsr #26 @ d >>= 26 (ignore hi)
orr r5, r5, r6, asl #6
add r5, r5, r9 @ d += t2
str r5, [r0, #2*4] @ r[2] = d
add sp, sp, #48
ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc}
.size secp256k1_fe_mul_inner, .-secp256k1_fe_mul_inner
.align 2
.global secp256k1_fe_sqr_inner
.type secp256k1_fe_sqr_inner, %function
@ Arguments:
@ r0 r Can overlap with a
@ r1 a
@ Stack (total 4+10*4 = 44)
@ sp + #0 saved 'r' pointer
@ sp + #4 + 4*X t0,t1,t2,t3,t4,t5,t6,t7,u8,t9
secp256k1_fe_sqr_inner:
stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, r14}
sub sp, sp, #48 @ frame=44 + alignment
str r0, [sp, #0] @ save result address, we need it only at the end
/******************************************
* Main computation code.
******************************************
Allocation:
r0,r14,r2,r7,r8 scratch
r1 a (pointer)
r3:r4 c
r5:r6 d
r11:r12 c'
r9:r10 d'
Note: do not write to r[] here, it may overlap with a[]
*/
/* A interleaved with B */
ldr r0, [r1, #1*4] @ a[1]*2
ldr r7, [r1, #0*4] @ a[0]
mov r0, r0, asl #1
ldr r14, [r1, #9*4] @ a[9]
umull r3, r4, r7, r7 @ c = a[0] * a[0]
ldr r8, [r1, #8*4] @ a[8]
mov r7, r7, asl #1
umull r5, r6, r7, r14 @ d = a[0]*2 * a[9]
ldr r7, [r1, #2*4] @ a[2]*2
umull r9, r10, r0, r14 @ d' = a[1]*2 * a[9]
ldr r14, [r1, #7*4] @ a[7]
umlal r5, r6, r0, r8 @ d += a[1]*2 * a[8]
mov r7, r7, asl #1
ldr r0, [r1, #3*4] @ a[3]*2
umlal r9, r10, r7, r8 @ d' += a[2]*2 * a[8]
ldr r8, [r1, #6*4] @ a[6]
umlal r5, r6, r7, r14 @ d += a[2]*2 * a[7]
mov r0, r0, asl #1
ldr r7, [r1, #4*4] @ a[4]*2
umlal r9, r10, r0, r14 @ d' += a[3]*2 * a[7]
ldr r14, [r1, #5*4] @ a[5]
mov r7, r7, asl #1
umlal r5, r6, r0, r8 @ d += a[3]*2 * a[6]
umlal r9, r10, r7, r8 @ d' += a[4]*2 * a[6]
umlal r5, r6, r7, r14 @ d += a[4]*2 * a[5]
umlal r9, r10, r14, r14 @ d' += a[5] * a[5]
bic r0, r5, field_not_M @ t9 = d & M
str r0, [sp, #4 + 9*4]
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
/* B */
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u0 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u0 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t0 = c & M
str r14, [sp, #4 + 0*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u0 * R1
umlal r3, r4, r0, r14
/* C interleaved with D */
ldr r0, [r1, #0*4] @ a[0]*2
ldr r14, [r1, #1*4] @ a[1]
mov r0, r0, asl #1
ldr r8, [r1, #2*4] @ a[2]
umlal r3, r4, r0, r14 @ c += a[0]*2 * a[1]
mov r7, r8, asl #1 @ a[2]*2
umull r11, r12, r14, r14 @ c' = a[1] * a[1]
ldr r14, [r1, #9*4] @ a[9]
umlal r11, r12, r0, r8 @ c' += a[0]*2 * a[2]
ldr r0, [r1, #3*4] @ a[3]*2
ldr r8, [r1, #8*4] @ a[8]
umlal r5, r6, r7, r14 @ d += a[2]*2 * a[9]
mov r0, r0, asl #1
ldr r7, [r1, #4*4] @ a[4]*2
umull r9, r10, r0, r14 @ d' = a[3]*2 * a[9]
ldr r14, [r1, #7*4] @ a[7]
umlal r5, r6, r0, r8 @ d += a[3]*2 * a[8]
mov r7, r7, asl #1
ldr r0, [r1, #5*4] @ a[5]*2
umlal r9, r10, r7, r8 @ d' += a[4]*2 * a[8]
ldr r8, [r1, #6*4] @ a[6]
mov r0, r0, asl #1
umlal r5, r6, r7, r14 @ d += a[4]*2 * a[7]
umlal r9, r10, r0, r14 @ d' += a[5]*2 * a[7]
umlal r5, r6, r0, r8 @ d += a[5]*2 * a[6]
umlal r9, r10, r8, r8 @ d' += a[6] * a[6]
bic r0, r5, field_not_M @ u1 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u1 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t1 = c & M
str r14, [sp, #4 + 1*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u1 * R1
umlal r3, r4, r0, r14
/* D */
adds r3, r3, r11 @ c += c'
adc r4, r4, r12
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u2 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u2 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t2 = c & M
str r14, [sp, #4 + 2*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u2 * R1
umlal r3, r4, r0, r14
/* E interleaved with F */
ldr r7, [r1, #0*4] @ a[0]*2
ldr r0, [r1, #1*4] @ a[1]*2
ldr r14, [r1, #2*4] @ a[2]
mov r7, r7, asl #1
ldr r8, [r1, #3*4] @ a[3]
ldr r2, [r1, #4*4]
umlal r3, r4, r7, r8 @ c += a[0]*2 * a[3]
mov r0, r0, asl #1
umull r11, r12, r7, r2 @ c' = a[0]*2 * a[4]
mov r2, r2, asl #1 @ a[4]*2
umlal r11, r12, r0, r8 @ c' += a[1]*2 * a[3]
ldr r8, [r1, #9*4] @ a[9]
umlal r3, r4, r0, r14 @ c += a[1]*2 * a[2]
ldr r0, [r1, #5*4] @ a[5]*2
umlal r11, r12, r14, r14 @ c' += a[2] * a[2]
ldr r14, [r1, #8*4] @ a[8]
mov r0, r0, asl #1
umlal r5, r6, r2, r8 @ d += a[4]*2 * a[9]
ldr r7, [r1, #6*4] @ a[6]*2
umull r9, r10, r0, r8 @ d' = a[5]*2 * a[9]
mov r7, r7, asl #1
ldr r8, [r1, #7*4] @ a[7]
umlal r5, r6, r0, r14 @ d += a[5]*2 * a[8]
umlal r9, r10, r7, r14 @ d' += a[6]*2 * a[8]
umlal r5, r6, r7, r8 @ d += a[6]*2 * a[7]
umlal r9, r10, r8, r8 @ d' += a[7] * a[7]
bic r0, r5, field_not_M @ u3 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u3 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t3 = c & M
str r14, [sp, #4 + 3*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u3 * R1
umlal r3, r4, r0, r14
/* F */
adds r3, r3, r11 @ c += c'
adc r4, r4, r12
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u4 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u4 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t4 = c & M
str r14, [sp, #4 + 4*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u4 * R1
umlal r3, r4, r0, r14
/* G interleaved with H */
ldr r7, [r1, #0*4] @ a[0]*2
ldr r0, [r1, #1*4] @ a[1]*2
mov r7, r7, asl #1
ldr r8, [r1, #5*4] @ a[5]
ldr r2, [r1, #6*4] @ a[6]
umlal r3, r4, r7, r8 @ c += a[0]*2 * a[5]
ldr r14, [r1, #4*4] @ a[4]
mov r0, r0, asl #1
umull r11, r12, r7, r2 @ c' = a[0]*2 * a[6]
ldr r7, [r1, #2*4] @ a[2]*2
umlal r11, r12, r0, r8 @ c' += a[1]*2 * a[5]
mov r7, r7, asl #1
ldr r8, [r1, #3*4] @ a[3]
umlal r3, r4, r0, r14 @ c += a[1]*2 * a[4]
mov r0, r2, asl #1 @ a[6]*2
umlal r11, r12, r7, r14 @ c' += a[2]*2 * a[4]
ldr r14, [r1, #9*4] @ a[9]
umlal r3, r4, r7, r8 @ c += a[2]*2 * a[3]
ldr r7, [r1, #7*4] @ a[7]*2
umlal r11, r12, r8, r8 @ c' += a[3] * a[3]
mov r7, r7, asl #1
ldr r8, [r1, #8*4] @ a[8]
umlal r5, r6, r0, r14 @ d += a[6]*2 * a[9]
umull r9, r10, r7, r14 @ d' = a[7]*2 * a[9]
umlal r5, r6, r7, r8 @ d += a[7]*2 * a[8]
umlal r9, r10, r8, r8 @ d' += a[8] * a[8]
bic r0, r5, field_not_M @ u5 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u5 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t5 = c & M
str r14, [sp, #4 + 5*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u5 * R1
umlal r3, r4, r0, r14
/* H */
adds r3, r3, r11 @ c += c'
adc r4, r4, r12
adds r5, r5, r9 @ d += d'
adc r6, r6, r10
bic r0, r5, field_not_M @ u6 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u6 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t6 = c & M
str r14, [sp, #4 + 6*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u6 * R1
umlal r3, r4, r0, r14
/* I interleaved with J */
ldr r7, [r1, #0*4] @ a[0]*2
ldr r0, [r1, #1*4] @ a[1]*2
mov r7, r7, asl #1
ldr r8, [r1, #7*4] @ a[7]
ldr r2, [r1, #8*4] @ a[8]
umlal r3, r4, r7, r8 @ c += a[0]*2 * a[7]
ldr r14, [r1, #6*4] @ a[6]
mov r0, r0, asl #1
umull r11, r12, r7, r2 @ c' = a[0]*2 * a[8]
ldr r7, [r1, #2*4] @ a[2]*2
umlal r11, r12, r0, r8 @ c' += a[1]*2 * a[7]
ldr r8, [r1, #5*4] @ a[5]
umlal r3, r4, r0, r14 @ c += a[1]*2 * a[6]
ldr r0, [r1, #3*4] @ a[3]*2
mov r7, r7, asl #1
umlal r11, r12, r7, r14 @ c' += a[2]*2 * a[6]
ldr r14, [r1, #4*4] @ a[4]
mov r0, r0, asl #1
umlal r3, r4, r7, r8 @ c += a[2]*2 * a[5]
mov r2, r2, asl #1 @ a[8]*2
umlal r11, r12, r0, r8 @ c' += a[3]*2 * a[5]
umlal r3, r4, r0, r14 @ c += a[3]*2 * a[4]
umlal r11, r12, r14, r14 @ c' += a[4] * a[4]
ldr r8, [r1, #9*4] @ a[9]
umlal r5, r6, r2, r8 @ d += a[8]*2 * a[9]
@ r8 will be used in J
bic r0, r5, field_not_M @ u7 = d & M
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u7 * R0
umlal r3, r4, r0, r14
bic r14, r3, field_not_M @ t7 = c & M
str r14, [sp, #4 + 7*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u7 * R1
umlal r3, r4, r0, r14
/* J */
adds r3, r3, r11 @ c += c'
adc r4, r4, r12
umlal r5, r6, r8, r8 @ d += a[9] * a[9]
bic r0, r5, field_not_M @ u8 = d & M
str r0, [sp, #4 + 8*4]
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R0 @ c += u8 * R0
umlal r3, r4, r0, r14
/******************************************
* compute and write back result
******************************************
Allocation:
r0 r
r3:r4 c
r5:r6 d
r7 t0
r8 t1
r9 t2
r11 u8
r12 t9
r1,r2,r10,r14 scratch
Note: do not read from a[] after here, it may overlap with r[]
*/
ldr r0, [sp, #0]
add r1, sp, #4 + 3*4 @ r[3..7] = t3..7, r11=u8, r12=t9
ldmia r1, {r2,r7,r8,r9,r10,r11,r12}
add r1, r0, #3*4
stmia r1, {r2,r7,r8,r9,r10}
bic r2, r3, field_not_M @ r[8] = c & M
str r2, [r0, #8*4]
mov r3, r3, lsr #26 @ c >>= 26
orr r3, r3, r4, asl #6
mov r4, r4, lsr #26
mov r14, field_R1 @ c += u8 * R1
umlal r3, r4, r11, r14
movw r14, field_R0 @ c += d * R0
umlal r3, r4, r5, r14
adds r3, r3, r12 @ c += t9
adc r4, r4, #0
add r1, sp, #4 + 0*4 @ r7,r8,r9 = t0,t1,t2
ldmia r1, {r7,r8,r9}
ubfx r2, r3, #0, #22 @ r[9] = c & (M >> 4)
str r2, [r0, #9*4]
mov r3, r3, lsr #22 @ c >>= 22
orr r3, r3, r4, asl #10
mov r4, r4, lsr #22
movw r14, field_R1 << 4 @ c += d * (R1 << 4)
umlal r3, r4, r5, r14
movw r14, field_R0 >> 4 @ d = c * (R0 >> 4) + t0 (64x64 multiply+add)
umull r5, r6, r3, r14 @ d = c.lo * (R0 >> 4)
adds r5, r5, r7 @ d.lo += t0
mla r6, r14, r4, r6 @ d.hi += c.hi * (R0 >> 4)
adc r6, r6, 0 @ d.hi += carry
bic r2, r5, field_not_M @ r[0] = d & M
str r2, [r0, #0*4]
mov r5, r5, lsr #26 @ d >>= 26
orr r5, r5, r6, asl #6
mov r6, r6, lsr #26
movw r14, field_R1 >> 4 @ d += c * (R1 >> 4) + t1 (64x64 multiply+add)
umull r1, r2, r3, r14 @ tmp = c.lo * (R1 >> 4)
adds r5, r5, r8 @ d.lo += t1
adc r6, r6, #0 @ d.hi += carry
adds r5, r5, r1 @ d.lo += tmp.lo
mla r2, r14, r4, r2 @ tmp.hi += c.hi * (R1 >> 4)
adc r6, r6, r2 @ d.hi += carry + tmp.hi
bic r2, r5, field_not_M @ r[1] = d & M
str r2, [r0, #1*4]
mov r5, r5, lsr #26 @ d >>= 26 (ignore hi)
orr r5, r5, r6, asl #6
add r5, r5, r9 @ d += t2
str r5, [r0, #2*4] @ r[2] = d
add sp, sp, #48
ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc}
.size secp256k1_fe_sqr_inner, .-secp256k1_fe_sqr_inner
|
luliyucoordinate/myos | 2,143 | src/hardwarecommunication/interruptstubs.s | .set IRQ_BASE, 0x20
.section .text
.extern __ZN4myos21hardwarecommunication16InterruptManager15HandleInterruptEhj
.macro HandleInterruptRequest num
.global __ZN4myos21hardwarecommunication16InterruptManager26HandleInterruptRequest\num\()Ev
__ZN4myos21hardwarecommunication16InterruptManager26HandleInterruptRequest\num\()Ev:
movb $\num + IRQ_BASE, (interruptnumber)
pushl $0
jmp int_bottom
.endm
.macro HandleException num
.global __ZN4myos21hardwarecommunication16InterruptManager19HandleException\num\()Ev
__ZN4myos21hardwarecommunication16InterruptManager19HandleException\num\()Ev:
movb $\num, (interruptnumber)
jmp int_bottom
.endm
HandleInterruptRequest 0x00
HandleInterruptRequest 0x01
HandleInterruptRequest 0x02
HandleInterruptRequest 0x03
HandleInterruptRequest 0x04
HandleInterruptRequest 0x05
HandleInterruptRequest 0x06
HandleInterruptRequest 0x07
HandleInterruptRequest 0x08
HandleInterruptRequest 0x09
HandleInterruptRequest 0x0A
HandleInterruptRequest 0x0B
HandleInterruptRequest 0x0C
HandleInterruptRequest 0x0D
HandleInterruptRequest 0x0E
HandleInterruptRequest 0x0F
HandleInterruptRequest 0x31
HandleException 0x00
HandleException 0x01
HandleException 0x02
HandleException 0x03
HandleException 0x04
HandleException 0x05
HandleException 0x06
HandleException 0x07
HandleException 0x08
HandleException 0x09
HandleException 0x0A
HandleException 0x0B
HandleException 0x0C
HandleException 0x0D
HandleException 0x0E
HandleException 0x0F
HandleException 0x10
HandleException 0x11
HandleException 0x12
HandleException 0x13
int_bottom:
pushl %ebp
pushl %edi
pushl %esi
pushl %edx
pushl %ecx
pushl %ebx
pushl %eax
pushl %esp
push (interruptnumber)
call __ZN4myos21hardwarecommunication16InterruptManager15HandleInterruptEhj
movl %eax, %esp
popl %eax
popl %ebx
popl %ecx
popl %edx
popl %esi
popl %edi
popl %ebp
add $4, %esp
.global __ZN4myos21hardwarecommunication16InterruptManager15InterruptIgnoreEv
__ZN4myos21hardwarecommunication16InterruptManager15InterruptIgnoreEv:
iret
.data
interruptnumber: .byte 0
|
lvgl/lv_port_riverdi_101-stm32h7 | 29,796 | STM32CubeIDE/CM7/Application/User/Startup/startup_stm32h747xihx.s | /**
******************************************************************************
* @file startup_stm32h747xx.s
* @author MCD Application Team
* @brief STM32H747xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
; ldr sp, =_estack /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word 0 /* Reserved */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
.word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
.word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* Reserved */
.word RNG_IRQHandler /* Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
.word SAI3_IRQHandler /* SAI3 global Interrupt */
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
.word TIM15_IRQHandler /* TIM15 global Interrupt */
.word TIM16_IRQHandler /* TIM16 global Interrupt */
.word TIM17_IRQHandler /* TIM17 global Interrupt */
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
.word JPEG_IRQHandler /* JPEG global Interrupt */
.word MDMA_IRQHandler /* MDMA global Interrupt */
.word DSI_IRQHandler /* DSI global Interrupt */
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
.word HSEM2_IRQHandler /* HSEM1 global Interrupt */
.word ADC3_IRQHandler /* ADC3 global Interrupt */
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
.word COMP1_IRQHandler /* COMP1 global Interrupt */
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
.word LPUART1_IRQHandler /* LP UART1 interrupt */
.word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
.word SAI4_IRQHandler /* SAI4 global interrupt */
.word 0 /* Reserved */
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak FDCAN_CAL_IRQHandler
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
.weak CM7_SEV_IRQHandler
.thumb_set CM7_SEV_IRQHandler,Default_Handler
.weak CM4_SEV_IRQHandler
.thumb_set CM4_SEV_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak OTG_FS_EP1_OUT_IRQHandler
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_FS_EP1_IN_IRQHandler
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak HRTIM1_Master_IRQHandler
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
.weak HRTIM1_TIMA_IRQHandler
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
.weak HRTIM1_TIMB_IRQHandler
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
.weak HRTIM1_TIMC_IRQHandler
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
.weak HRTIM1_TIMD_IRQHandler
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
.weak HRTIM1_TIME_IRQHandler
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
.weak HRTIM1_FLT_IRQHandler
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SAI3_IRQHandler
.thumb_set SAI3_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak MDIOS_WKUP_IRQHandler
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
.weak JPEG_IRQHandler
.thumb_set JPEG_IRQHandler,Default_Handler
.weak MDMA_IRQHandler
.thumb_set MDMA_IRQHandler,Default_Handler
.weak DSI_IRQHandler
.thumb_set DSI_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak HSEM1_IRQHandler
.thumb_set HSEM1_IRQHandler,Default_Handler
.weak HSEM2_IRQHandler
.thumb_set HSEM2_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak DMAMUX2_OVR_IRQHandler
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
.weak BDMA_Channel0_IRQHandler
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
.weak BDMA_Channel1_IRQHandler
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
.weak BDMA_Channel2_IRQHandler
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
.weak BDMA_Channel3_IRQHandler
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
.weak BDMA_Channel4_IRQHandler
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
.weak BDMA_Channel5_IRQHandler
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
.weak BDMA_Channel6_IRQHandler
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
.weak BDMA_Channel7_IRQHandler
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
.weak COMP1_IRQHandler
.thumb_set COMP1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak LPTIM4_IRQHandler
.thumb_set LPTIM4_IRQHandler,Default_Handler
.weak LPTIM5_IRQHandler
.thumb_set LPTIM5_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak WWDG_RST_IRQHandler
.thumb_set WWDG_RST_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak ECC_IRQHandler
.thumb_set ECC_IRQHandler,Default_Handler
.weak SAI4_IRQHandler
.thumb_set SAI4_IRQHandler,Default_Handler
.weak HOLD_CORE_IRQHandler
.thumb_set HOLD_CORE_IRQHandler,Default_Handler
.weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
lvgl/lv_port_riverdi_101-stm32h7 | 29,795 | STM32CubeIDE/CM4/Application/User/Startup/startup_stm32h747xihx.s | /**
******************************************************************************
* @file startup_stm32h747xx.s
* @author MCD Application Team
* @brief STM32H747xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word 0 /* Reserved */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
.word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
.word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* Reserved */
.word RNG_IRQHandler /* Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
.word SAI3_IRQHandler /* SAI3 global Interrupt */
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
.word TIM15_IRQHandler /* TIM15 global Interrupt */
.word TIM16_IRQHandler /* TIM16 global Interrupt */
.word TIM17_IRQHandler /* TIM17 global Interrupt */
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
.word JPEG_IRQHandler /* JPEG global Interrupt */
.word MDMA_IRQHandler /* MDMA global Interrupt */
.word DSI_IRQHandler /* DSI global Interrupt */
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
.word HSEM2_IRQHandler /* HSEM1 global Interrupt */
.word ADC3_IRQHandler /* ADC3 global Interrupt */
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
.word COMP1_IRQHandler /* COMP1 global Interrupt */
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
.word LPUART1_IRQHandler /* LP UART1 interrupt */
.word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
.word SAI4_IRQHandler /* SAI4 global interrupt */
.word 0 /* Reserved */
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak FDCAN_CAL_IRQHandler
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
.weak CM7_SEV_IRQHandler
.thumb_set CM7_SEV_IRQHandler,Default_Handler
.weak CM4_SEV_IRQHandler
.thumb_set CM4_SEV_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak OTG_FS_EP1_OUT_IRQHandler
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_FS_EP1_IN_IRQHandler
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak HRTIM1_Master_IRQHandler
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
.weak HRTIM1_TIMA_IRQHandler
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
.weak HRTIM1_TIMB_IRQHandler
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
.weak HRTIM1_TIMC_IRQHandler
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
.weak HRTIM1_TIMD_IRQHandler
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
.weak HRTIM1_TIME_IRQHandler
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
.weak HRTIM1_FLT_IRQHandler
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SAI3_IRQHandler
.thumb_set SAI3_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak MDIOS_WKUP_IRQHandler
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
.weak JPEG_IRQHandler
.thumb_set JPEG_IRQHandler,Default_Handler
.weak MDMA_IRQHandler
.thumb_set MDMA_IRQHandler,Default_Handler
.weak DSI_IRQHandler
.thumb_set DSI_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak HSEM1_IRQHandler
.thumb_set HSEM1_IRQHandler,Default_Handler
.weak HSEM2_IRQHandler
.thumb_set HSEM2_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak DMAMUX2_OVR_IRQHandler
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
.weak BDMA_Channel0_IRQHandler
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
.weak BDMA_Channel1_IRQHandler
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
.weak BDMA_Channel2_IRQHandler
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
.weak BDMA_Channel3_IRQHandler
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
.weak BDMA_Channel4_IRQHandler
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
.weak BDMA_Channel5_IRQHandler
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
.weak BDMA_Channel6_IRQHandler
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
.weak BDMA_Channel7_IRQHandler
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
.weak COMP1_IRQHandler
.thumb_set COMP1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak LPTIM4_IRQHandler
.thumb_set LPTIM4_IRQHandler,Default_Handler
.weak LPTIM5_IRQHandler
.thumb_set LPTIM5_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak WWDG_RST_IRQHandler
.thumb_set WWDG_RST_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak ECC_IRQHandler
.thumb_set ECC_IRQHandler,Default_Handler
.weak SAI4_IRQHandler
.thumb_set SAI4_IRQHandler,Default_Handler
.weak HOLD_CORE_IRQHandler
.thumb_set HOLD_CORE_IRQHandler,Default_Handler
.weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
LvNA-system/labeled-RISC-V | 2,989 | scripts/debug_rom/debug_rom.S | // See LICENSE.SiFive for license details.
#include "spike/encoding.h"
// These are implementation-specific addresses in the Debug Module
#define HALTED 0x100
#define GOING 0x104
#define RESUMING 0x108
#define EXCEPTION 0x10C
// Region of memory where each hart has 1
// byte to read.
#define FLAGS 0x400
#define FLAG_GO 0
#define FLAG_RESUME 1
.option norvc
.global entry
.global exception
// Entry location on ebreak, Halt, or Breakpoint
// It is the same for all harts. They branch when
// their GO or RESUME bit is set.
entry:
jal zero, _entry
resume:
jal zero, _resume
exception:
jal zero, _exception
_entry:
// This fence is required because the execution may have written something
// into the Abstract Data or Program Buffer registers.
fence
csrw CSR_DSCRATCH, s0 // Save s0 to allow signaling MHARTID
// We continue to let the hart know that we are halted in order that
// a DM which was reset is still made aware that a hart is halted.
// We keep checking both whether there is something the debugger wants
// us to do, or whether we should resume.
entry_loop:
csrr s0, mhartid
sw s0, HALTED(zero)
lbu s0, FLAGS(s0) // 1 byte flag per hart. Only one hart advances here.
andi s0, s0, (1 << FLAG_GO) | (1 << FLAG_RESUME)
beqz s0, entry_loop // Loop until either GO or RESUME is set.
andi s0, s0, (1 << FLAG_GO)
beqz s0, _resume // If GO is clear at this point, RESUME must be set.
csrr s0, CSR_DSCRATCH // Restore s0 here
sw zero, GOING(zero) // When debug module sees this write, the GO flag is reset.
jalr zero, zero, %lo(whereto) // Rocket-Chip has a specific hack which is that jalr in
// Debug Mode will flush the I-Cache. We need that so that the
// remainder of the variable instructions will be what Debug Module
// intends.
_resume:
csrr s0, mhartid
sw s0, RESUMING(zero) // When Debug Module sees this write, the RESUME flag is reset.
csrr s0, CSR_DSCRATCH // Restore s0
dret
_exception:
sw zero, EXCEPTION(zero) // Let debug module know you got an exception.
ebreak
// END OF ACTUAL "ROM" CONTENTS. BELOW IS JUST FOR LINKER SCRIPT.
.section .whereto
whereto:
nop
// Variable "ROM" This is : jal x0 abstract, jal x0 program_buffer,
// or jal x0 resume, as desired.
// Debug Module state machine tracks what is 'desired'.
// We don't need/want to use jalr here because all of the
// Variable ROM contents are set by
// Debug Module before setting the OK_GO byte.
|
lvonasek/3DLiveScanner | 140,637 | third_party/libjpeg-turbo/src/simd/jsimd_mips_dspr2.S | /*
* MIPS DSPr2 optimizations for libjpeg-turbo
*
* Copyright (C) 2013-2014, MIPS Technologies, Inc., California.
* All rights reserved.
* Authors: Teodora Novkovic (teodora.novkovic@imgtec.com)
* Darko Laus (darko.laus@imgtec.com)
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*/
#include "jsimd_mips_dspr2_asm.h"
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_c_null_convert_mips_dspr2)
/*
* a0 - cinfo->image_width
* a1 - input_buf
* a2 - output_buf
* a3 - output_row
* 16(sp) - num_rows
* 20(sp) - cinfo->num_components
*
* Null conversion for compression
*/
SAVE_REGS_ON_STACK 8, s0, s1
lw t9, 24(sp) // t9 = num_rows
lw s0, 28(sp) // s0 = cinfo->num_components
andi t0, a0, 3 // t0 = cinfo->image_width & 3
beqz t0, 4f // no residual
nop
0:
addiu t9, t9, -1
bltz t9, 7f
li t1, 0
1:
sll t3, t1, 2
lwx t5, t3(a2) // t5 = outptr = output_buf[ci]
lw t2, 0(a1) // t2 = inptr = *input_buf
sll t4, a3, 2
lwx t5, t4(t5) // t5 = outptr = output_buf[ci][output_row]
addu t2, t2, t1
addu s1, t5, a0
addu t6, t5, t0
2:
lbu t3, 0(t2)
addiu t5, t5, 1
sb t3, -1(t5)
bne t6, t5, 2b
addu t2, t2, s0
3:
lbu t3, 0(t2)
addu t4, t2, s0
addu t7, t4, s0
addu t8, t7, s0
addu t2, t8, s0
lbu t4, 0(t4)
lbu t7, 0(t7)
lbu t8, 0(t8)
addiu t5, t5, 4
sb t3, -4(t5)
sb t4, -3(t5)
sb t7, -2(t5)
bne s1, t5, 3b
sb t8, -1(t5)
addiu t1, t1, 1
bne t1, s0, 1b
nop
addiu a1, a1, 4
bgez t9, 0b
addiu a3, a3, 1
b 7f
nop
4:
addiu t9, t9, -1
bltz t9, 7f
li t1, 0
5:
sll t3, t1, 2
lwx t5, t3(a2) // t5 = outptr = output_buf[ci]
lw t2, 0(a1) // t2 = inptr = *input_buf
sll t4, a3, 2
lwx t5, t4(t5) // t5 = outptr = output_buf[ci][output_row]
addu t2, t2, t1
addu s1, t5, a0
addu t6, t5, t0
6:
lbu t3, 0(t2)
addu t4, t2, s0
addu t7, t4, s0
addu t8, t7, s0
addu t2, t8, s0
lbu t4, 0(t4)
lbu t7, 0(t7)
lbu t8, 0(t8)
addiu t5, t5, 4
sb t3, -4(t5)
sb t4, -3(t5)
sb t7, -2(t5)
bne s1, t5, 6b
sb t8, -1(t5)
addiu t1, t1, 1
bne t1, s0, 5b
nop
addiu a1, a1, 4
bgez t9, 4b
addiu a3, a3, 1
7:
RESTORE_REGS_FROM_STACK 8, s0, s1
j ra
nop
END(jsimd_c_null_convert_mips_dspr2)
/*****************************************************************************/
/*
* jsimd_extrgb_ycc_convert_mips_dspr2
* jsimd_extbgr_ycc_convert_mips_dspr2
* jsimd_extrgbx_ycc_convert_mips_dspr2
* jsimd_extbgrx_ycc_convert_mips_dspr2
* jsimd_extxbgr_ycc_convert_mips_dspr2
* jsimd_extxrgb_ycc_convert_mips_dspr2
*
* Colorspace conversion RGB -> YCbCr
*/
.macro GENERATE_JSIMD_RGB_YCC_CONVERT_MIPS_DSPR2 colorid, pixel_size, r_offs, g_offs, b_offs
.macro DO_RGB_TO_YCC r, \
g, \
b, \
inptr
lbu \r, \r_offs(\inptr)
lbu \g, \g_offs(\inptr)
lbu \b, \b_offs(\inptr)
addiu \inptr, \pixel_size
.endm
LEAF_MIPS_DSPR2(jsimd_\colorid\()_ycc_convert_mips_dspr2)
/*
* a0 - cinfo->image_width
* a1 - input_buf
* a2 - output_buf
* a3 - output_row
* 16(sp) - num_rows
*/
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
lw t7, 48(sp) // t7 = num_rows
li s0, 0x4c8b // FIX(0.29900)
li s1, 0x9646 // FIX(0.58700)
li s2, 0x1d2f // FIX(0.11400)
li s3, 0xffffd4cd // -FIX(0.16874)
li s4, 0xffffab33 // -FIX(0.33126)
li s5, 0x8000 // FIX(0.50000)
li s6, 0xffff94d1 // -FIX(0.41869)
li s7, 0xffffeb2f // -FIX(0.08131)
li t8, 0x807fff // CBCR_OFFSET + ONE_HALF-1
0:
addiu t7, -1 // --num_rows
lw t6, 0(a1) // t6 = input_buf[0]
lw t0, 0(a2)
lw t1, 4(a2)
lw t2, 8(a2)
sll t3, a3, 2
lwx t0, t3(t0) // t0 = output_buf[0][output_row]
lwx t1, t3(t1) // t1 = output_buf[1][output_row]
lwx t2, t3(t2) // t2 = output_buf[2][output_row]
addu t9, t2, a0 // t9 = end address
addiu a3, 1
1:
DO_RGB_TO_YCC t3, t4, t5, t6
mtlo s5, $ac0
mtlo t8, $ac1
mtlo t8, $ac2
maddu $ac0, s2, t5
maddu $ac1, s5, t5
maddu $ac2, s5, t3
maddu $ac0, s0, t3
maddu $ac1, s3, t3
maddu $ac2, s6, t4
maddu $ac0, s1, t4
maddu $ac1, s4, t4
maddu $ac2, s7, t5
extr.w t3, $ac0, 16
extr.w t4, $ac1, 16
extr.w t5, $ac2, 16
sb t3, 0(t0)
sb t4, 0(t1)
sb t5, 0(t2)
addiu t0, 1
addiu t2, 1
bne t2, t9, 1b
addiu t1, 1
bgtz t7, 0b
addiu a1, 4
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_\colorid\()_ycc_convert_mips_dspr2)
.purgem DO_RGB_TO_YCC
.endm
/*------------------------------------------id -- pix R G B */
GENERATE_JSIMD_RGB_YCC_CONVERT_MIPS_DSPR2 extrgb, 3, 0, 1, 2
GENERATE_JSIMD_RGB_YCC_CONVERT_MIPS_DSPR2 extbgr, 3, 2, 1, 0
GENERATE_JSIMD_RGB_YCC_CONVERT_MIPS_DSPR2 extrgbx, 4, 0, 1, 2
GENERATE_JSIMD_RGB_YCC_CONVERT_MIPS_DSPR2 extbgrx, 4, 2, 1, 0
GENERATE_JSIMD_RGB_YCC_CONVERT_MIPS_DSPR2 extxbgr, 4, 3, 2, 1
GENERATE_JSIMD_RGB_YCC_CONVERT_MIPS_DSPR2 extxrgb, 4, 1, 2, 3
/*****************************************************************************/
/*
* jsimd_ycc_extrgb_convert_mips_dspr2
* jsimd_ycc_extbgr_convert_mips_dspr2
* jsimd_ycc_extrgbx_convert_mips_dspr2
* jsimd_ycc_extbgrx_convert_mips_dspr2
* jsimd_ycc_extxbgr_convert_mips_dspr2
* jsimd_ycc_extxrgb_convert_mips_dspr2
*
* Colorspace conversion YCbCr -> RGB
*/
.macro GENERATE_JSIMD_YCC_RGB_CONVERT_MIPS_DSPR2 colorid, pixel_size, r_offs, g_offs, b_offs, a_offs
.macro STORE_YCC_TO_RGB scratch0 \
scratch1 \
scratch2 \
outptr
sb \scratch0, \r_offs(\outptr)
sb \scratch1, \g_offs(\outptr)
sb \scratch2, \b_offs(\outptr)
.if (\pixel_size == 4)
li t0, 0xFF
sb t0, \a_offs(\outptr)
.endif
addiu \outptr, \pixel_size
.endm
LEAF_MIPS_DSPR2(jsimd_ycc_\colorid\()_convert_mips_dspr2)
/*
* a0 - cinfo->image_width
* a1 - input_buf
* a2 - input_row
* a3 - output_buf
* 16(sp) - num_rows
*/
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
lw s1, 48(sp)
li t3, 0x8000
li t4, 0x166e9 // FIX(1.40200)
li t5, 0x1c5a2 // FIX(1.77200)
li t6, 0xffff492e // -FIX(0.71414)
li t7, 0xffffa7e6 // -FIX(0.34414)
repl.ph t8, 128
0:
lw s0, 0(a3)
lw t0, 0(a1)
lw t1, 4(a1)
lw t2, 8(a1)
sll s5, a2, 2
addiu s1, -1
lwx s2, s5(t0)
lwx s3, s5(t1)
lwx s4, s5(t2)
addu t9, s2, a0
addiu a2, 1
1:
lbu s7, 0(s4) // cr
lbu s6, 0(s3) // cb
lbu s5, 0(s2) // y
addiu s2, 1
addiu s4, 1
addiu s7, -128
addiu s6, -128
mul t2, t7, s6
mul t0, t6, s7 // Crgtab[cr]
sll s7, 15
mulq_rs.w t1, t4, s7 // Crrtab[cr]
sll s6, 15
addu t2, t3 // Cbgtab[cb]
addu t2, t0
mulq_rs.w t0, t5, s6 // Cbbtab[cb]
sra t2, 16
addu t1, s5
addu t2, s5 // add y
ins t2, t1, 16, 16
subu.ph t2, t2, t8
addu t0, s5
shll_s.ph t2, t2, 8
subu t0, 128
shra.ph t2, t2, 8
shll_s.w t0, t0, 24
addu.ph t2, t2, t8 // clip & store
sra t0, t0, 24
sra t1, t2, 16
addiu t0, 128
STORE_YCC_TO_RGB t1, t2, t0, s0
bne s2, t9, 1b
addiu s3, 1
bgtz s1, 0b
addiu a3, 4
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_ycc_\colorid\()_convert_mips_dspr2)
.purgem STORE_YCC_TO_RGB
.endm
/*------------------------------------------id -- pix R G B A */
GENERATE_JSIMD_YCC_RGB_CONVERT_MIPS_DSPR2 extrgb, 3, 0, 1, 2, 3
GENERATE_JSIMD_YCC_RGB_CONVERT_MIPS_DSPR2 extbgr, 3, 2, 1, 0, 3
GENERATE_JSIMD_YCC_RGB_CONVERT_MIPS_DSPR2 extrgbx, 4, 0, 1, 2, 3
GENERATE_JSIMD_YCC_RGB_CONVERT_MIPS_DSPR2 extbgrx, 4, 2, 1, 0, 3
GENERATE_JSIMD_YCC_RGB_CONVERT_MIPS_DSPR2 extxbgr, 4, 3, 2, 1, 0
GENERATE_JSIMD_YCC_RGB_CONVERT_MIPS_DSPR2 extxrgb, 4, 1, 2, 3, 0
/*****************************************************************************/
/*
* jsimd_extrgb_gray_convert_mips_dspr2
* jsimd_extbgr_gray_convert_mips_dspr2
* jsimd_extrgbx_gray_convert_mips_dspr2
* jsimd_extbgrx_gray_convert_mips_dspr2
* jsimd_extxbgr_gray_convert_mips_dspr2
* jsimd_extxrgb_gray_convert_mips_dspr2
*
* Colorspace conversion RGB -> GRAY
*/
.macro GENERATE_JSIMD_RGB_GRAY_CONVERT_MIPS_DSPR2 colorid, pixel_size, r_offs, g_offs, b_offs
.macro DO_RGB_TO_GRAY r, \
g, \
b, \
inptr
lbu \r, \r_offs(\inptr)
lbu \g, \g_offs(\inptr)
lbu \b, \b_offs(\inptr)
addiu \inptr, \pixel_size
.endm
LEAF_MIPS_DSPR2(jsimd_\colorid\()_gray_convert_mips_dspr2)
/*
* a0 - cinfo->image_width
* a1 - input_buf
* a2 - output_buf
* a3 - output_row
* 16(sp) - num_rows
*/
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
li s0, 0x4c8b // s0 = FIX(0.29900)
li s1, 0x9646 // s1 = FIX(0.58700)
li s2, 0x1d2f // s2 = FIX(0.11400)
li s7, 0x8000 // s7 = FIX(0.50000)
lw s6, 48(sp)
andi t7, a0, 3
0:
addiu s6, -1 // s6 = num_rows
lw t0, 0(a1)
lw t1, 0(a2)
sll t3, a3, 2
lwx t1, t3(t1)
addiu a3, 1
addu t9, t1, a0
subu t8, t9, t7
beq t1, t8, 2f
nop
1:
DO_RGB_TO_GRAY t3, t4, t5, t0
DO_RGB_TO_GRAY s3, s4, s5, t0
mtlo s7, $ac0
maddu $ac0, s2, t5
maddu $ac0, s1, t4
maddu $ac0, s0, t3
mtlo s7, $ac1
maddu $ac1, s2, s5
maddu $ac1, s1, s4
maddu $ac1, s0, s3
extr.w t6, $ac0, 16
DO_RGB_TO_GRAY t3, t4, t5, t0
DO_RGB_TO_GRAY s3, s4, s5, t0
mtlo s7, $ac0
maddu $ac0, s2, t5
maddu $ac0, s1, t4
extr.w t2, $ac1, 16
maddu $ac0, s0, t3
mtlo s7, $ac1
maddu $ac1, s2, s5
maddu $ac1, s1, s4
maddu $ac1, s0, s3
extr.w t5, $ac0, 16
sb t6, 0(t1)
sb t2, 1(t1)
extr.w t3, $ac1, 16
addiu t1, 4
sb t5, -2(t1)
sb t3, -1(t1)
bne t1, t8, 1b
nop
2:
beqz t7, 4f
nop
3:
DO_RGB_TO_GRAY t3, t4, t5, t0
mtlo s7, $ac0
maddu $ac0, s2, t5
maddu $ac0, s1, t4
maddu $ac0, s0, t3
extr.w t6, $ac0, 16
sb t6, 0(t1)
addiu t1, 1
bne t1, t9, 3b
nop
4:
bgtz s6, 0b
addiu a1, 4
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_\colorid\()_gray_convert_mips_dspr2)
.purgem DO_RGB_TO_GRAY
.endm
/*------------------------------------------id -- pix R G B */
GENERATE_JSIMD_RGB_GRAY_CONVERT_MIPS_DSPR2 extrgb, 3, 0, 1, 2
GENERATE_JSIMD_RGB_GRAY_CONVERT_MIPS_DSPR2 extbgr, 3, 2, 1, 0
GENERATE_JSIMD_RGB_GRAY_CONVERT_MIPS_DSPR2 extrgbx, 4, 0, 1, 2
GENERATE_JSIMD_RGB_GRAY_CONVERT_MIPS_DSPR2 extbgrx, 4, 2, 1, 0
GENERATE_JSIMD_RGB_GRAY_CONVERT_MIPS_DSPR2 extxbgr, 4, 3, 2, 1
GENERATE_JSIMD_RGB_GRAY_CONVERT_MIPS_DSPR2 extxrgb, 4, 1, 2, 3
/*****************************************************************************/
/*
* jsimd_h2v2_merged_upsample_mips_dspr2
* jsimd_h2v2_extrgb_merged_upsample_mips_dspr2
* jsimd_h2v2_extrgbx_merged_upsample_mips_dspr2
* jsimd_h2v2_extbgr_merged_upsample_mips_dspr2
* jsimd_h2v2_extbgrx_merged_upsample_mips_dspr2
* jsimd_h2v2_extxbgr_merged_upsample_mips_dspr2
* jsimd_h2v2_extxrgb_merged_upsample_mips_dspr2
*
* Merged h2v2 upsample routines
*/
.macro GENERATE_H2V2_MERGED_UPSAMPLE_MIPS_DSPR2 colorid, \
pixel_size, \
r1_offs, \
g1_offs, \
b1_offs, \
a1_offs, \
r2_offs, \
g2_offs, \
b2_offs, \
a2_offs
.macro STORE_H2V2_2_PIXELS scratch0 \
scratch1 \
scratch2 \
scratch3 \
scratch4 \
scratch5 \
outptr
sb \scratch0, \r1_offs(\outptr)
sb \scratch1, \g1_offs(\outptr)
sb \scratch2, \b1_offs(\outptr)
sb \scratch3, \r2_offs(\outptr)
sb \scratch4, \g2_offs(\outptr)
sb \scratch5, \b2_offs(\outptr)
.if (\pixel_size == 8)
li \scratch0, 0xFF
sb \scratch0, \a1_offs(\outptr)
sb \scratch0, \a2_offs(\outptr)
.endif
addiu \outptr, \pixel_size
.endm
.macro STORE_H2V2_1_PIXEL scratch0 \
scratch1 \
scratch2 \
outptr
sb \scratch0, \r1_offs(\outptr)
sb \scratch1, \g1_offs(\outptr)
sb \scratch2, \b1_offs(\outptr)
.if (\pixel_size == 8)
li t0, 0xFF
sb t0, \a1_offs(\outptr)
.endif
.endm
LEAF_MIPS_DSPR2(jsimd_h2v2_\colorid\()_merged_upsample_mips_dspr2)
/*
* a0 - cinfo->output_width
* a1 - input_buf
* a2 - in_row_group_ctr
* a3 - output_buf
* 16(sp) - cinfo->sample_range_limit
*/
SAVE_REGS_ON_STACK 40, s0, s1, s2, s3, s4, s5, s6, s7, ra
lw t9, 56(sp) // cinfo->sample_range_limit
lw v0, 0(a1)
lw v1, 4(a1)
lw t0, 8(a1)
sll t1, a2, 3
addiu t2, t1, 4
sll t3, a2, 2
lw t4, 0(a3) // t4 = output_buf[0]
lwx t1, t1(v0) // t1 = input_buf[0][in_row_group_ctr*2]
lwx t2, t2(v0) // t2 = input_buf[0][in_row_group_ctr*2 + 1]
lwx t5, t3(v1) // t5 = input_buf[1][in_row_group_ctr]
lwx t6, t3(t0) // t6 = input_buf[2][in_row_group_ctr]
lw t7, 4(a3) // t7 = output_buf[1]
li s1, 0xe6ea
addiu t8, s1, 0x7fff // t8 = 0x166e9 [FIX(1.40200)]
addiu s0, t8, 0x5eb9 // s0 = 0x1c5a2 [FIX(1.77200)]
addiu s1, zero, 0xa7e6 // s4 = 0xffffa7e6 [-FIX(0.34414)]
xori s2, s1, 0xeec8 // s3 = 0xffff492e [-FIX(0.71414)]
srl t3, a0, 1
blez t3, 2f
addu t0, t5, t3 // t0 = end address
1:
lbu t3, 0(t5)
lbu s3, 0(t6)
addiu t5, t5, 1
addiu t3, t3, -128 // (cb - 128)
addiu s3, s3, -128 // (cr - 128)
mult $ac1, s1, t3
madd $ac1, s2, s3
sll s3, s3, 15
sll t3, t3, 15
mulq_rs.w s4, t8, s3 // s4 = (C1 * cr + ONE_HALF)>> SCALEBITS
extr_r.w s5, $ac1, 16
mulq_rs.w s6, s0, t3 // s6 = (C2 * cb + ONE_HALF)>> SCALEBITS
lbu v0, 0(t1)
addiu t6, t6, 1
addiu t1, t1, 2
addu t3, v0, s4 // y+cred
addu s3, v0, s5 // y+cgreen
addu v1, v0, s6 // y+cblue
addu t3, t9, t3 // y+cred
addu s3, t9, s3 // y+cgreen
addu v1, t9, v1 // y+cblue
lbu AT, 0(t3)
lbu s7, 0(s3)
lbu ra, 0(v1)
lbu v0, -1(t1)
addu t3, v0, s4 // y+cred
addu s3, v0, s5 // y+cgreen
addu v1, v0, s6 // y+cblue
addu t3, t9, t3 // y+cred
addu s3, t9, s3 // y+cgreen
addu v1, t9, v1 // y+cblue
lbu t3, 0(t3)
lbu s3, 0(s3)
lbu v1, 0(v1)
lbu v0, 0(t2)
STORE_H2V2_2_PIXELS AT, s7, ra, t3, s3, v1, t4
addu t3, v0, s4 // y+cred
addu s3, v0, s5 // y+cgreen
addu v1, v0, s6 // y+cblue
addu t3, t9, t3 // y+cred
addu s3, t9, s3 // y+cgreen
addu v1, t9, v1 // y+cblue
lbu AT, 0(t3)
lbu s7, 0(s3)
lbu ra, 0(v1)
lbu v0, 1(t2)
addiu t2, t2, 2
addu t3, v0, s4 // y+cred
addu s3, v0, s5 // y+cgreen
addu v1, v0, s6 // y+cblue
addu t3, t9, t3 // y+cred
addu s3, t9, s3 // y+cgreen
addu v1, t9, v1 // y+cblue
lbu t3, 0(t3)
lbu s3, 0(s3)
lbu v1, 0(v1)
STORE_H2V2_2_PIXELS AT, s7, ra, t3, s3, v1, t7
bne t0, t5, 1b
nop
2:
andi t0, a0, 1
beqz t0, 4f
lbu t3, 0(t5)
lbu s3, 0(t6)
addiu t3, t3, -128 // (cb - 128)
addiu s3, s3, -128 // (cr - 128)
mult $ac1, s1, t3
madd $ac1, s2, s3
sll s3, s3, 15
sll t3, t3, 15
lbu v0, 0(t1)
extr_r.w s5, $ac1, 16
mulq_rs.w s4, t8, s3 // s4 = (C1 * cr + ONE_HALF)>> SCALEBITS
mulq_rs.w s6, s0, t3 // s6 = (C2 * cb + ONE_HALF)>> SCALEBITS
addu t3, v0, s4 // y+cred
addu s3, v0, s5 // y+cgreen
addu v1, v0, s6 // y+cblue
addu t3, t9, t3 // y+cred
addu s3, t9, s3 // y+cgreen
addu v1, t9, v1 // y+cblue
lbu t3, 0(t3)
lbu s3, 0(s3)
lbu v1, 0(v1)
lbu v0, 0(t2)
STORE_H2V2_1_PIXEL t3, s3, v1, t4
addu t3, v0, s4 // y+cred
addu s3, v0, s5 // y+cgreen
addu v1, v0, s6 // y+cblue
addu t3, t9, t3 // y+cred
addu s3, t9, s3 // y+cgreen
addu v1, t9, v1 // y+cblue
lbu t3, 0(t3)
lbu s3, 0(s3)
lbu v1, 0(v1)
STORE_H2V2_1_PIXEL t3, s3, v1, t7
4:
RESTORE_REGS_FROM_STACK 40, s0, s1, s2, s3, s4, s5, s6, s7, ra
j ra
nop
END(jsimd_h2v2_\colorid\()_merged_upsample_mips_dspr2)
.purgem STORE_H2V2_1_PIXEL
.purgem STORE_H2V2_2_PIXELS
.endm
/*-----------------------------------------id -- pix R1 G1 B1 A1 R2 G2 B2 A2 */
GENERATE_H2V2_MERGED_UPSAMPLE_MIPS_DSPR2 extrgb, 6, 0, 1, 2, 6, 3, 4, 5, 6
GENERATE_H2V2_MERGED_UPSAMPLE_MIPS_DSPR2 extbgr, 6, 2, 1, 0, 3, 5, 4, 3, 6
GENERATE_H2V2_MERGED_UPSAMPLE_MIPS_DSPR2 extrgbx, 8, 0, 1, 2, 3, 4, 5, 6, 7
GENERATE_H2V2_MERGED_UPSAMPLE_MIPS_DSPR2 extbgrx, 8, 2, 1, 0, 3, 6, 5, 4, 7
GENERATE_H2V2_MERGED_UPSAMPLE_MIPS_DSPR2 extxbgr, 8, 3, 2, 1, 0, 7, 6, 5, 4
GENERATE_H2V2_MERGED_UPSAMPLE_MIPS_DSPR2 extxrgb, 8, 1, 2, 3, 0, 5, 6, 7, 4
/*****************************************************************************/
/*
* jsimd_h2v1_merged_upsample_mips_dspr2
* jsimd_h2v1_extrgb_merged_upsample_mips_dspr2
* jsimd_h2v1_extrgbx_merged_upsample_mips_dspr2
* jsimd_h2v1_extbgr_merged_upsample_mips_dspr2
* jsimd_h2v1_extbgrx_merged_upsample_mips_dspr2
* jsimd_h2v1_extxbgr_merged_upsample_mips_dspr2
* jsimd_h2v1_extxrgb_merged_upsample_mips_dspr2
*
* Merged h2v1 upsample routines
*/
.macro GENERATE_H2V1_MERGED_UPSAMPLE_MIPS_DSPR2 colorid, \
pixel_size, \
r1_offs, \
g1_offs, \
b1_offs, \
a1_offs, \
r2_offs, \
g2_offs, \
b2_offs, \
a2_offs
.macro STORE_H2V1_2_PIXELS scratch0 \
scratch1 \
scratch2 \
scratch3 \
scratch4 \
scratch5 \
outptr
sb \scratch0, \r1_offs(\outptr)
sb \scratch1, \g1_offs(\outptr)
sb \scratch2, \b1_offs(\outptr)
sb \scratch3, \r2_offs(\outptr)
sb \scratch4, \g2_offs(\outptr)
sb \scratch5, \b2_offs(\outptr)
.if (\pixel_size == 8)
li t0, 0xFF
sb t0, \a1_offs(\outptr)
sb t0, \a2_offs(\outptr)
.endif
addiu \outptr, \pixel_size
.endm
.macro STORE_H2V1_1_PIXEL scratch0 \
scratch1 \
scratch2 \
outptr
sb \scratch0, \r1_offs(\outptr)
sb \scratch1, \g1_offs(\outptr)
sb \scratch2, \b1_offs(\outptr)
.if (\pixel_size == 8)
li t0, 0xFF
sb t0, \a1_offs(\outptr)
.endif
.endm
LEAF_MIPS_DSPR2(jsimd_h2v1_\colorid\()_merged_upsample_mips_dspr2)
/*
* a0 - cinfo->output_width
* a1 - input_buf
* a2 - in_row_group_ctr
* a3 - output_buf
* 16(sp) - range_limit
*/
SAVE_REGS_ON_STACK 40, s0, s1, s2, s3, s4, s5, s6, s7, ra
li t0, 0xe6ea
lw t1, 0(a1) // t1 = input_buf[0]
lw t2, 4(a1) // t2 = input_buf[1]
lw t3, 8(a1) // t3 = input_buf[2]
lw t8, 56(sp) // t8 = range_limit
addiu s1, t0, 0x7fff // s1 = 0x166e9 [FIX(1.40200)]
addiu s2, s1, 0x5eb9 // s2 = 0x1c5a2 [FIX(1.77200)]
addiu s0, t0, 0x9916 // s0 = 0x8000
addiu s4, zero, 0xa7e6 // s4 = 0xffffa7e6 [-FIX(0.34414)]
xori s3, s4, 0xeec8 // s3 = 0xffff492e [-FIX(0.71414)]
srl t0, a0, 1
sll t4, a2, 2
lwx s5, t4(t1) // s5 = inptr0
lwx s6, t4(t2) // s6 = inptr1
lwx s7, t4(t3) // s7 = inptr2
lw t7, 0(a3) // t7 = outptr
blez t0, 2f
addu t9, s6, t0 // t9 = end address
1:
lbu t2, 0(s6) // t2 = cb
lbu t0, 0(s7) // t0 = cr
lbu t1, 0(s5) // t1 = y
addiu t2, t2, -128 // t2 = cb - 128
addiu t0, t0, -128 // t0 = cr - 128
mult $ac1, s4, t2
madd $ac1, s3, t0
sll t0, t0, 15
sll t2, t2, 15
mulq_rs.w t0, s1, t0 // t0 = (C1*cr + ONE_HALF)>> SCALEBITS
extr_r.w t5, $ac1, 16
mulq_rs.w t6, s2, t2 // t6 = (C2*cb + ONE_HALF)>> SCALEBITS
addiu s7, s7, 1
addiu s6, s6, 1
addu t2, t1, t0 // t2 = y + cred
addu t3, t1, t5 // t3 = y + cgreen
addu t4, t1, t6 // t4 = y + cblue
addu t2, t8, t2
addu t3, t8, t3
addu t4, t8, t4
lbu t1, 1(s5)
lbu v0, 0(t2)
lbu v1, 0(t3)
lbu ra, 0(t4)
addu t2, t1, t0
addu t3, t1, t5
addu t4, t1, t6
addu t2, t8, t2
addu t3, t8, t3
addu t4, t8, t4
lbu t2, 0(t2)
lbu t3, 0(t3)
lbu t4, 0(t4)
STORE_H2V1_2_PIXELS v0, v1, ra, t2, t3, t4, t7
bne t9, s6, 1b
addiu s5, s5, 2
2:
andi t0, a0, 1
beqz t0, 4f
nop
3:
lbu t2, 0(s6)
lbu t0, 0(s7)
lbu t1, 0(s5)
addiu t2, t2, -128 //(cb - 128)
addiu t0, t0, -128 //(cr - 128)
mul t3, s4, t2
mul t4, s3, t0
sll t0, t0, 15
sll t2, t2, 15
mulq_rs.w t0, s1, t0 // (C1*cr + ONE_HALF)>> SCALEBITS
mulq_rs.w t6, s2, t2 // (C2*cb + ONE_HALF)>> SCALEBITS
addu t3, t3, s0
addu t3, t4, t3
sra t5, t3, 16 // (C4*cb + ONE_HALF + C3*cr)>> SCALEBITS
addu t2, t1, t0 // y + cred
addu t3, t1, t5 // y + cgreen
addu t4, t1, t6 // y + cblue
addu t2, t8, t2
addu t3, t8, t3
addu t4, t8, t4
lbu t2, 0(t2)
lbu t3, 0(t3)
lbu t4, 0(t4)
STORE_H2V1_1_PIXEL t2, t3, t4, t7
4:
RESTORE_REGS_FROM_STACK 40, s0, s1, s2, s3, s4, s5, s6, s7, ra
j ra
nop
END(jsimd_h2v1_\colorid\()_merged_upsample_mips_dspr2)
.purgem STORE_H2V1_1_PIXEL
.purgem STORE_H2V1_2_PIXELS
.endm
/*-----------------------------------------id -- pix R1 G1 B1 A1 R2 G2 B2 A2 */
GENERATE_H2V1_MERGED_UPSAMPLE_MIPS_DSPR2 extrgb, 6, 0, 1, 2, 6, 3, 4, 5, 6
GENERATE_H2V1_MERGED_UPSAMPLE_MIPS_DSPR2 extbgr, 6, 2, 1, 0, 3, 5, 4, 3, 6
GENERATE_H2V1_MERGED_UPSAMPLE_MIPS_DSPR2 extrgbx, 8, 0, 1, 2, 3, 4, 5, 6, 7
GENERATE_H2V1_MERGED_UPSAMPLE_MIPS_DSPR2 extbgrx, 8, 2, 1, 0, 3, 6, 5, 4, 7
GENERATE_H2V1_MERGED_UPSAMPLE_MIPS_DSPR2 extxbgr, 8, 3, 2, 1, 0, 7, 6, 5, 4
GENERATE_H2V1_MERGED_UPSAMPLE_MIPS_DSPR2 extxrgb, 8, 1, 2, 3, 0, 5, 6, 7, 4
/*****************************************************************************/
/*
* jsimd_h2v2_fancy_upsample_mips_dspr2
*
* Fancy processing for the common case of 2:1 horizontal and 2:1 vertical.
*/
LEAF_MIPS_DSPR2(jsimd_h2v2_fancy_upsample_mips_dspr2)
/*
* a0 - cinfo->max_v_samp_factor
* a1 - downsampled_width
* a2 - input_data
* a3 - output_data_ptr
*/
SAVE_REGS_ON_STACK 24, s0, s1, s2, s3, s4, s5
li s4, 0
lw s2, 0(a3) // s2 = *output_data_ptr
0:
li t9, 2
lw s1, -4(a2) // s1 = inptr1
1:
lw s0, 0(a2) // s0 = inptr0
lwx s3, s4(s2)
addiu s5, a1, -2 // s5 = downsampled_width - 2
srl t4, s5, 1
sll t4, t4, 1
lbu t0, 0(s0)
lbu t1, 1(s0)
lbu t2, 0(s1)
lbu t3, 1(s1)
addiu s0, 2
addiu s1, 2
addu t8, s0, t4 // t8 = end address
andi s5, s5, 1 // s5 = residual
sll t4, t0, 1
sll t6, t1, 1
addu t0, t0, t4 // t0 = (*inptr0++) * 3
addu t1, t1, t6 // t1 = (*inptr0++) * 3
addu t7, t0, t2 // t7 = thiscolsum
addu t6, t1, t3 // t5 = nextcolsum
sll t0, t7, 2 // t0 = thiscolsum * 4
subu t1, t0, t7 // t1 = thiscolsum * 3
shra_r.w t0, t0, 4
addiu t1, 7
addu t1, t1, t6
srl t1, t1, 4
sb t0, 0(s3)
sb t1, 1(s3)
beq t8, s0, 22f // skip to final iteration if width == 3
addiu s3, 2
2:
lh t0, 0(s0) // t0 = A3|A2
lh t2, 0(s1) // t2 = B3|B2
addiu s0, 2
addiu s1, 2
preceu.ph.qbr t0, t0 // t0 = 0|A3|0|A2
preceu.ph.qbr t2, t2 // t2 = 0|B3|0|B2
shll.ph t1, t0, 1
sll t3, t6, 1
addu.ph t0, t1, t0 // t0 = A3*3|A2*3
addu t3, t3, t6 // t3 = this * 3
addu.ph t0, t0, t2 // t0 = next2|next1
addu t1, t3, t7
andi t7, t0, 0xFFFF // t7 = next1
sll t2, t7, 1
addu t2, t7, t2 // t2 = next1*3
addu t4, t2, t6
srl t6, t0, 16 // t6 = next2
shra_r.w t1, t1, 4 // t1 = (this*3 + last + 8) >> 4
addu t0, t3, t7
addiu t0, 7
srl t0, t0, 4 // t0 = (this*3 + next1 + 7) >> 4
shra_r.w t4, t4, 4 // t3 = (next1*3 + this + 8) >> 4
addu t2, t2, t6
addiu t2, 7
srl t2, t2, 4 // t2 = (next1*3 + next2 + 7) >> 4
sb t1, 0(s3)
sb t0, 1(s3)
sb t4, 2(s3)
sb t2, 3(s3)
bne t8, s0, 2b
addiu s3, 4
22:
beqz s5, 4f
addu t8, s0, s5
3:
lbu t0, 0(s0)
lbu t2, 0(s1)
addiu s0, 1
addiu s1, 1
sll t3, t6, 1
sll t1, t0, 1
addu t1, t0, t1 // t1 = inptr0 * 3
addu t3, t3, t6 // t3 = thiscolsum * 3
addu t5, t1, t2
addu t1, t3, t7
shra_r.w t1, t1, 4
addu t0, t3, t5
addiu t0, 7
srl t0, t0, 4
sb t1, 0(s3)
sb t0, 1(s3)
addiu s3, 2
move t7, t6
bne t8, s0, 3b
move t6, t5
4:
sll t0, t6, 2 // t0 = thiscolsum * 4
subu t1, t0, t6 // t1 = thiscolsum * 3
addu t1, t1, t7
addiu s4, 4
shra_r.w t1, t1, 4
addiu t0, 7
srl t0, t0, 4
sb t1, 0(s3)
sb t0, 1(s3)
addiu t9, -1
addiu s3, 2
bnez t9, 1b
lw s1, 4(a2)
srl t0, s4, 2
subu t0, a0, t0
bgtz t0, 0b
addiu a2, 4
RESTORE_REGS_FROM_STACK 24, s0, s1, s2, s3, s4, s5
j ra
nop
END(jsimd_h2v2_fancy_upsample_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_h2v1_fancy_upsample_mips_dspr2)
/*
* a0 - cinfo->max_v_samp_factor
* a1 - downsampled_width
* a2 - input_data
* a3 - output_data_ptr
*/
SAVE_REGS_ON_STACK 16, s0, s1, s2, s3
.set at
beqz a0, 3f
sll t0, a0, 2
lw s1, 0(a3)
li s3, 0x10001
addu s0, s1, t0
0:
addiu t8, a1, -2
srl t9, t8, 2
lw t7, 0(a2)
lw s2, 0(s1)
lbu t0, 0(t7)
lbu t1, 1(t7) // t1 = inptr[1]
sll t2, t0, 1
addu t2, t2, t0 // t2 = invalue*3
addu t2, t2, t1
shra_r.w t2, t2, 2
sb t0, 0(s2)
sb t2, 1(s2)
beqz t9, 11f
addiu s2, 2
1:
ulw t0, 0(t7) // t0 = |P3|P2|P1|P0|
ulw t1, 1(t7)
ulh t2, 4(t7) // t2 = |0|0|P5|P4|
preceu.ph.qbl t3, t0 // t3 = |0|P3|0|P2|
preceu.ph.qbr t0, t0 // t0 = |0|P1|0|P0|
preceu.ph.qbr t2, t2 // t2 = |0|P5|0|P4|
preceu.ph.qbl t4, t1 // t4 = |0|P4|0|P3|
preceu.ph.qbr t1, t1 // t1 = |0|P2|0|P1|
shll.ph t5, t4, 1
shll.ph t6, t1, 1
addu.ph t5, t5, t4 // t5 = |P4*3|P3*3|
addu.ph t6, t6, t1 // t6 = |P2*3|P1*3|
addu.ph t4, t3, s3
addu.ph t0, t0, s3
addu.ph t4, t4, t5
addu.ph t0, t0, t6
shrl.ph t4, t4, 2 // t4 = |0|P3|0|P2|
shrl.ph t0, t0, 2 // t0 = |0|P1|0|P0|
addu.ph t2, t2, t5
addu.ph t3, t3, t6
shra_r.ph t2, t2, 2 // t2 = |0|P5|0|P4|
shra_r.ph t3, t3, 2 // t3 = |0|P3|0|P2|
shll.ph t2, t2, 8
shll.ph t3, t3, 8
or t2, t4, t2
or t3, t3, t0
addiu t9, -1
usw t3, 0(s2)
usw t2, 4(s2)
addiu s2, 8
bgtz t9, 1b
addiu t7, 4
11:
andi t8, 3
beqz t8, 22f
addiu t7, 1
2:
lbu t0, 0(t7)
addiu t7, 1
sll t1, t0, 1
addu t2, t0, t1 // t2 = invalue
lbu t3, -2(t7)
lbu t4, 0(t7)
addiu t3, 1
addiu t4, 2
addu t3, t3, t2
addu t4, t4, t2
srl t3, 2
srl t4, 2
sb t3, 0(s2)
sb t4, 1(s2)
addiu t8, -1
bgtz t8, 2b
addiu s2, 2
22:
lbu t0, 0(t7)
lbu t2, -1(t7)
sll t1, t0, 1
addu t1, t1, t0 // t1 = invalue * 3
addu t1, t1, t2
addiu t1, 1
srl t1, t1, 2
sb t1, 0(s2)
sb t0, 1(s2)
addiu s1, 4
bne s1, s0, 0b
addiu a2, 4
3:
RESTORE_REGS_FROM_STACK 16, s0, s1, s2, s3
j ra
nop
END(jsimd_h2v1_fancy_upsample_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_h2v1_downsample_mips_dspr2)
/*
* a0 - cinfo->image_width
* a1 - cinfo->max_v_samp_factor
* a2 - compptr->v_samp_factor
* a3 - compptr->width_in_blocks
* 16(sp) - input_data
* 20(sp) - output_data
*/
.set at
SAVE_REGS_ON_STACK 24, s0, s1, s2, s3, s4
beqz a2, 7f
lw s1, 44(sp) // s1 = output_data
lw s0, 40(sp) // s0 = input_data
srl s2, a0, 2
andi t9, a0, 2
srl t7, t9, 1
addu s2, t7, s2
sll t0, a3, 3 // t0 = width_in_blocks*DCT
srl t7, t0, 1
subu s2, t7, s2
0:
andi t6, a0, 1 // t6 = temp_index
addiu t6, -1
lw t4, 0(s1) // t4 = outptr
lw t5, 0(s0) // t5 = inptr0
li s3, 0 // s3 = bias
srl t7, a0, 1 // t7 = image_width1
srl s4, t7, 2
andi t8, t7, 3
1:
ulhu t0, 0(t5)
ulhu t1, 2(t5)
ulhu t2, 4(t5)
ulhu t3, 6(t5)
raddu.w.qb t0, t0
raddu.w.qb t1, t1
raddu.w.qb t2, t2
raddu.w.qb t3, t3
shra.ph t0, t0, 1
shra_r.ph t1, t1, 1
shra.ph t2, t2, 1
shra_r.ph t3, t3, 1
sb t0, 0(t4)
sb t1, 1(t4)
sb t2, 2(t4)
sb t3, 3(t4)
addiu s4, -1
addiu t4, 4
bgtz s4, 1b
addiu t5, 8
beqz t8, 3f
addu s4, t4, t8
2:
ulhu t0, 0(t5)
raddu.w.qb t0, t0
addqh.w t0, t0, s3
xori s3, s3, 1
sb t0, 0(t4)
addiu t4, 1
bne t4, s4, 2b
addiu t5, 2
3:
lbux t1, t6(t5)
sll t1, 1
addqh.w t2, t1, s3 // t2 = pixval1
xori s3, s3, 1
addqh.w t3, t1, s3 // t3 = pixval2
blez s2, 5f
append t3, t2, 8
addu t5, t4, s2 // t5 = loop_end2
4:
ush t3, 0(t4)
addiu s2, -1
bgtz s2, 4b
addiu t4, 2
5:
beqz t9, 6f
nop
sb t2, 0(t4)
6:
addiu s1, 4
addiu a2, -1
bnez a2, 0b
addiu s0, 4
7:
RESTORE_REGS_FROM_STACK 24, s0, s1, s2, s3, s4
j ra
nop
END(jsimd_h2v1_downsample_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_h2v2_downsample_mips_dspr2)
/*
* a0 - cinfo->image_width
* a1 - cinfo->max_v_samp_factor
* a2 - compptr->v_samp_factor
* a3 - compptr->width_in_blocks
* 16(sp) - input_data
* 20(sp) - output_data
*/
.set at
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
beqz a2, 8f
lw s1, 52(sp) // s1 = output_data
lw s0, 48(sp) // s0 = input_data
andi t6, a0, 1 // t6 = temp_index
addiu t6, -1
srl t7, a0, 1 // t7 = image_width1
srl s4, t7, 2
andi t8, t7, 3
andi t9, a0, 2
srl s2, a0, 2
srl t7, t9, 1
addu s2, t7, s2
sll t0, a3, 3 // s2 = width_in_blocks*DCT
srl t7, t0, 1
subu s2, t7, s2
0:
lw t4, 0(s1) // t4 = outptr
lw t5, 0(s0) // t5 = inptr0
lw s7, 4(s0) // s7 = inptr1
li s6, 1 // s6 = bias
2:
ulw t0, 0(t5) // t0 = |P3|P2|P1|P0|
ulw t1, 0(s7) // t1 = |Q3|Q2|Q1|Q0|
ulw t2, 4(t5)
ulw t3, 4(s7)
precrq.ph.w t7, t0, t1 // t2 = |P3|P2|Q3|Q2|
ins t0, t1, 16, 16 // t0 = |Q1|Q0|P1|P0|
raddu.w.qb t1, t7
raddu.w.qb t0, t0
shra_r.w t1, t1, 2
addiu t0, 1
srl t0, 2
precrq.ph.w t7, t2, t3
ins t2, t3, 16, 16
raddu.w.qb t7, t7
raddu.w.qb t2, t2
shra_r.w t7, t7, 2
addiu t2, 1
srl t2, 2
sb t0, 0(t4)
sb t1, 1(t4)
sb t2, 2(t4)
sb t7, 3(t4)
addiu t4, 4
addiu t5, 8
addiu s4, s4, -1
bgtz s4, 2b
addiu s7, 8
beqz t8, 4f
addu t8, t4, t8
3:
ulhu t0, 0(t5)
ulhu t1, 0(s7)
ins t0, t1, 16, 16
raddu.w.qb t0, t0
addu t0, t0, s6
srl t0, 2
xori s6, s6, 3
sb t0, 0(t4)
addiu t5, 2
addiu t4, 1
bne t8, t4, 3b
addiu s7, 2
4:
lbux t1, t6(t5)
sll t1, 1
lbux t0, t6(s7)
sll t0, 1
addu t1, t1, t0
addu t3, t1, s6
srl t0, t3, 2 // t2 = pixval1
xori s6, s6, 3
addu t2, t1, s6
srl t1, t2, 2 // t3 = pixval2
blez s2, 6f
append t1, t0, 8
5:
ush t1, 0(t4)
addiu s2, -1
bgtz s2, 5b
addiu t4, 2
6:
beqz t9, 7f
nop
sb t0, 0(t4)
7:
addiu s1, 4
addiu a2, -1
bnez a2, 0b
addiu s0, 8
8:
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_h2v2_downsample_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_h2v2_smooth_downsample_mips_dspr2)
/*
* a0 - input_data
* a1 - output_data
* a2 - compptr->v_samp_factor
* a3 - cinfo->max_v_samp_factor
* 16(sp) - cinfo->smoothing_factor
* 20(sp) - compptr->width_in_blocks
* 24(sp) - cinfo->image_width
*/
.set at
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
lw s7, 52(sp) // compptr->width_in_blocks
lw s0, 56(sp) // cinfo->image_width
lw s6, 48(sp) // cinfo->smoothing_factor
sll s7, 3 // output_cols = width_in_blocks * DCTSIZE
sll v0, s7, 1
subu v0, v0, s0
blez v0, 2f
move v1, zero
addiu t0, a3, 2 // t0 = cinfo->max_v_samp_factor + 2
0:
addiu t1, a0, -4
sll t2, v1, 2
lwx t1, t2(t1)
move t3, v0
addu t1, t1, s0
lbu t2, -1(t1)
1:
addiu t3, t3, -1
sb t2, 0(t1)
bgtz t3, 1b
addiu t1, t1, 1
addiu v1, v1, 1
bne v1, t0, 0b
nop
2:
li v0, 80
mul v0, s6, v0
li v1, 16384
move t4, zero
move t5, zero
subu t6, v1, v0 // t6 = 16384 - tmp_smoot_f * 80
sll t7, s6, 4 // t7 = tmp_smoot_f * 16
3:
/* Special case for first column: pretend column -1 is same as column 0 */
sll v0, t4, 2
lwx t8, v0(a1) // outptr = output_data[outrow]
sll v1, t5, 2
addiu t9, v1, 4
addiu s0, v1, -4
addiu s1, v1, 8
lwx s2, v1(a0) // inptr0 = input_data[inrow]
lwx t9, t9(a0) // inptr1 = input_data[inrow+1]
lwx s0, s0(a0) // above_ptr = input_data[inrow-1]
lwx s1, s1(a0) // below_ptr = input_data[inrow+2]
lh v0, 0(s2)
lh v1, 0(t9)
lh t0, 0(s0)
lh t1, 0(s1)
ins v0, v1, 16, 16
ins t0, t1, 16, 16
raddu.w.qb t2, v0
raddu.w.qb s3, t0
lbu v0, 0(s2)
lbu v1, 2(s2)
lbu t0, 0(t9)
lbu t1, 2(t9)
addu v0, v0, v1
mult $ac1,t2, t6
addu t0, t0, t1
lbu t2, 2(s0)
addu t0, t0, v0
lbu t3, 2(s1)
addu s3, t0, s3
lbu v0, 0(s0)
lbu t0, 0(s1)
sll s3, s3, 1
addu v0, v0, t2
addu t0, t0, t3
addu t0, t0, v0
addu s3, t0, s3
madd $ac1,s3, t7
extr_r.w v0, $ac1, 16
addiu t8, t8, 1
addiu s2, s2, 2
addiu t9, t9, 2
addiu s0, s0, 2
addiu s1, s1, 2
sb v0, -1(t8)
addiu s4, s7, -2
and s4, s4, 3
addu s5, s4, t8 //end adress
4:
lh v0, 0(s2)
lh v1, 0(t9)
lh t0, 0(s0)
lh t1, 0(s1)
ins v0, v1, 16, 16
ins t0, t1, 16, 16
raddu.w.qb t2, v0
raddu.w.qb s3, t0
lbu v0, -1(s2)
lbu v1, 2(s2)
lbu t0, -1(t9)
lbu t1, 2(t9)
addu v0, v0, v1
mult $ac1, t2, t6
addu t0, t0, t1
lbu t2, 2(s0)
addu t0, t0, v0
lbu t3, 2(s1)
addu s3, t0, s3
lbu v0, -1(s0)
lbu t0, -1(s1)
sll s3, s3, 1
addu v0, v0, t2
addu t0, t0, t3
addu t0, t0, v0
addu s3, t0, s3
madd $ac1, s3, t7
extr_r.w t2, $ac1, 16
addiu t8, t8, 1
addiu s2, s2, 2
addiu t9, t9, 2
addiu s0, s0, 2
sb t2, -1(t8)
bne s5, t8, 4b
addiu s1, s1, 2
addiu s5, s7, -2
subu s5, s5, s4
addu s5, s5, t8 //end adress
5:
lh v0, 0(s2)
lh v1, 0(t9)
lh t0, 0(s0)
lh t1, 0(s1)
ins v0, v1, 16, 16
ins t0, t1, 16, 16
raddu.w.qb t2, v0
raddu.w.qb s3, t0
lbu v0, -1(s2)
lbu v1, 2(s2)
lbu t0, -1(t9)
lbu t1, 2(t9)
addu v0, v0, v1
mult $ac1, t2, t6
addu t0, t0, t1
lbu t2, 2(s0)
addu t0, t0, v0
lbu t3, 2(s1)
addu s3, t0, s3
lbu v0, -1(s0)
lbu t0, -1(s1)
sll s3, s3, 1
addu v0, v0, t2
addu t0, t0, t3
lh v1, 2(t9)
addu t0, t0, v0
lh v0, 2(s2)
addu s3, t0, s3
lh t0, 2(s0)
lh t1, 2(s1)
madd $ac1, s3, t7
extr_r.w t2, $ac1, 16
ins t0, t1, 16, 16
ins v0, v1, 16, 16
raddu.w.qb s3, t0
lbu v1, 4(s2)
lbu t0, 1(t9)
lbu t1, 4(t9)
sb t2, 0(t8)
raddu.w.qb t3, v0
lbu v0, 1(s2)
addu t0, t0, t1
mult $ac1, t3, t6
addu v0, v0, v1
lbu t2, 4(s0)
addu t0, t0, v0
lbu v0, 1(s0)
addu s3, t0, s3
lbu t0, 1(s1)
lbu t3, 4(s1)
addu v0, v0, t2
sll s3, s3, 1
addu t0, t0, t3
lh v1, 4(t9)
addu t0, t0, v0
lh v0, 4(s2)
addu s3, t0, s3
lh t0, 4(s0)
lh t1, 4(s1)
madd $ac1, s3, t7
extr_r.w t2, $ac1, 16
ins t0, t1, 16, 16
ins v0, v1, 16, 16
raddu.w.qb s3, t0
lbu v1, 6(s2)
lbu t0, 3(t9)
lbu t1, 6(t9)
sb t2, 1(t8)
raddu.w.qb t3, v0
lbu v0, 3(s2)
addu t0, t0,t1
mult $ac1, t3, t6
addu v0, v0, v1
lbu t2, 6(s0)
addu t0, t0, v0
lbu v0, 3(s0)
addu s3, t0, s3
lbu t0, 3(s1)
lbu t3, 6(s1)
addu v0, v0, t2
sll s3, s3, 1
addu t0, t0, t3
lh v1, 6(t9)
addu t0, t0, v0
lh v0, 6(s2)
addu s3, t0, s3
lh t0, 6(s0)
lh t1, 6(s1)
madd $ac1, s3, t7
extr_r.w t3, $ac1, 16
ins t0, t1, 16, 16
ins v0, v1, 16, 16
raddu.w.qb s3, t0
lbu v1, 8(s2)
lbu t0, 5(t9)
lbu t1, 8(t9)
sb t3, 2(t8)
raddu.w.qb t2, v0
lbu v0, 5(s2)
addu t0, t0, t1
mult $ac1, t2, t6
addu v0, v0, v1
lbu t2, 8(s0)
addu t0, t0, v0
lbu v0, 5(s0)
addu s3, t0, s3
lbu t0, 5(s1)
lbu t3, 8(s1)
addu v0, v0, t2
sll s3, s3, 1
addu t0, t0, t3
addiu t8, t8, 4
addu t0, t0, v0
addiu s2, s2, 8
addu s3, t0, s3
addiu t9, t9, 8
madd $ac1, s3, t7
extr_r.w t1, $ac1, 16
addiu s0, s0, 8
addiu s1, s1, 8
bne s5, t8, 5b
sb t1, -1(t8)
/* Special case for last column */
lh v0, 0(s2)
lh v1, 0(t9)
lh t0, 0(s0)
lh t1, 0(s1)
ins v0, v1, 16, 16
ins t0, t1, 16, 16
raddu.w.qb t2, v0
raddu.w.qb s3, t0
lbu v0, -1(s2)
lbu v1, 1(s2)
lbu t0, -1(t9)
lbu t1, 1(t9)
addu v0, v0, v1
mult $ac1, t2, t6
addu t0, t0, t1
lbu t2, 1(s0)
addu t0, t0, v0
lbu t3, 1(s1)
addu s3, t0, s3
lbu v0, -1(s0)
lbu t0, -1(s1)
sll s3, s3, 1
addu v0, v0, t2
addu t0, t0, t3
addu t0, t0, v0
addu s3, t0, s3
madd $ac1, s3, t7
extr_r.w t0, $ac1, 16
addiu t5, t5, 2
sb t0, 0(t8)
addiu t4, t4, 1
bne t4, a2, 3b
addiu t5, t5, 2
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_h2v2_smooth_downsample_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_int_upsample_mips_dspr2)
/*
* a0 - upsample->h_expand[compptr->component_index]
* a1 - upsample->v_expand[compptr->component_index]
* a2 - input_data
* a3 - output_data_ptr
* 16(sp) - cinfo->output_width
* 20(sp) - cinfo->max_v_samp_factor
*/
.set at
SAVE_REGS_ON_STACK 16, s0, s1, s2, s3
lw s0, 0(a3) // s0 = output_data
lw s1, 32(sp) // s1 = cinfo->output_width
lw s2, 36(sp) // s2 = cinfo->max_v_samp_factor
li t6, 0 // t6 = inrow
beqz s2, 10f
li s3, 0 // s3 = outrow
0:
addu t0, a2, t6
addu t7, s0, s3
lw t3, 0(t0) // t3 = inptr
lw t8, 0(t7) // t8 = outptr
beqz s1, 4f
addu t5, t8, s1 // t5 = outend
1:
lb t2, 0(t3) // t2 = invalue = *inptr++
addiu t3, 1
beqz a0, 3f
move t0, a0 // t0 = h_expand
2:
sb t2, 0(t8)
addiu t0, -1
bgtz t0, 2b
addiu t8, 1
3:
bgt t5, t8, 1b
nop
4:
addiu t9, a1, -1 // t9 = v_expand - 1
blez t9, 9f
nop
5:
lw t3, 0(s0)
lw t4, 4(s0)
subu t0, s1, 0xF
blez t0, 7f
addu t5, t3, s1 // t5 = end address
andi t7, s1, 0xF // t7 = residual
subu t8, t5, t7
6:
ulw t0, 0(t3)
ulw t1, 4(t3)
ulw t2, 8(t3)
usw t0, 0(t4)
ulw t0, 12(t3)
usw t1, 4(t4)
usw t2, 8(t4)
usw t0, 12(t4)
addiu t3, 16
bne t3, t8, 6b
addiu t4, 16
beqz t7, 8f
nop
7:
lbu t0, 0(t3)
sb t0, 0(t4)
addiu t3, 1
bne t3, t5, 7b
addiu t4, 1
8:
addiu t9, -1
bgtz t9, 5b
addiu s0, 8
9:
addu s3, s3, a1
bne s3, s2, 0b
addiu t6, 1
10:
RESTORE_REGS_FROM_STACK 16, s0, s1, s2, s3
j ra
nop
END(jsimd_int_upsample_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_h2v1_upsample_mips_dspr2)
/*
* a0 - cinfo->max_v_samp_factor
* a1 - cinfo->output_width
* a2 - input_data
* a3 - output_data_ptr
*/
lw t7, 0(a3) // t7 = output_data
andi t8, a1, 0xf // t8 = residual
sll t0, a0, 2
blez a0, 4f
addu t9, t7, t0 // t9 = output_data end address
0:
lw t5, 0(t7) // t5 = outptr
lw t6, 0(a2) // t6 = inptr
addu t3, t5, a1 // t3 = outptr + output_width (end address)
subu t3, t8 // t3 = end address - residual
beq t5, t3, 2f
move t4, t8
1:
ulw t0, 0(t6) // t0 = |P3|P2|P1|P0|
ulw t2, 4(t6) // t2 = |P7|P6|P5|P4|
srl t1, t0, 16 // t1 = |X|X|P3|P2|
ins t0, t0, 16, 16 // t0 = |P1|P0|P1|P0|
ins t1, t1, 16, 16 // t1 = |P3|P2|P3|P2|
ins t0, t0, 8, 16 // t0 = |P1|P1|P0|P0|
ins t1, t1, 8, 16 // t1 = |P3|P3|P2|P2|
usw t0, 0(t5)
usw t1, 4(t5)
srl t0, t2, 16 // t0 = |X|X|P7|P6|
ins t2, t2, 16, 16 // t2 = |P5|P4|P5|P4|
ins t0, t0, 16, 16 // t0 = |P7|P6|P7|P6|
ins t2, t2, 8, 16 // t2 = |P5|P5|P4|P4|
ins t0, t0, 8, 16 // t0 = |P7|P7|P6|P6|
usw t2, 8(t5)
usw t0, 12(t5)
addiu t5, 16
bne t5, t3, 1b
addiu t6, 8
beqz t8, 3f
move t4, t8
2:
lbu t1, 0(t6)
sb t1, 0(t5)
sb t1, 1(t5)
addiu t4, -2
addiu t6, 1
bgtz t4, 2b
addiu t5, 2
3:
addiu t7, 4
bne t9, t7, 0b
addiu a2, 4
4:
j ra
nop
END(jsimd_h2v1_upsample_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_h2v2_upsample_mips_dspr2)
/*
* a0 - cinfo->max_v_samp_factor
* a1 - cinfo->output_width
* a2 - input_data
* a3 - output_data_ptr
*/
lw t7, 0(a3)
blez a0, 7f
andi t9, a1, 0xf // t9 = residual
0:
lw t6, 0(a2) // t6 = inptr
lw t5, 0(t7) // t5 = outptr
addu t8, t5, a1 // t8 = outptr end address
subu t8, t9 // t8 = end address - residual
beq t5, t8, 2f
move t4, t9
1:
ulw t0, 0(t6)
srl t1, t0, 16
ins t0, t0, 16, 16
ins t0, t0, 8, 16
ins t1, t1, 16, 16
ins t1, t1, 8, 16
ulw t2, 4(t6)
usw t0, 0(t5)
usw t1, 4(t5)
srl t3, t2, 16
ins t2, t2, 16, 16
ins t2, t2, 8, 16
ins t3, t3, 16, 16
ins t3, t3, 8, 16
usw t2, 8(t5)
usw t3, 12(t5)
addiu t5, 16
bne t5, t8, 1b
addiu t6, 8
beqz t9, 3f
move t4, t9
2:
lbu t0, 0(t6)
sb t0, 0(t5)
sb t0, 1(t5)
addiu t4, -2
addiu t6, 1
bgtz t4, 2b
addiu t5, 2
3:
ulw t6, 0(t7) // t6 = outptr
ulw t5, 4(t7) // t5 = outptr[1]
addu t4, t6, a1 // t4 = new end address
subu t8, t4, t9
beqz t8, 5f
nop
4:
ulw t0, 0(t6)
ulw t1, 4(t6)
ulw t2, 8(t6)
usw t0, 0(t5)
ulw t0, 12(t6)
usw t1, 4(t5)
usw t2, 8(t5)
usw t0, 12(t5)
addiu t6, 16
bne t6, t8, 4b
addiu t5, 16
beqz t9, 6f
nop
5:
lbu t0, 0(t6)
sb t0, 0(t5)
addiu t6, 1
bne t6, t4, 5b
addiu t5, 1
6:
addiu t7, 8
addiu a0, -2
bgtz a0, 0b
addiu a2, 4
7:
j ra
nop
END(jsimd_h2v2_upsample_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_idct_islow_mips_dspr2)
/*
* a0 - coef_block
* a1 - compptr->dcttable
* a2 - output
* a3 - range_limit
*/
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
addiu sp, sp, -256
move v0, sp
addiu v1, zero, 8 // v1 = DCTSIZE = 8
1:
lh s4, 32(a0) // s4 = inptr[16]
lh s5, 64(a0) // s5 = inptr[32]
lh s6, 96(a0) // s6 = inptr[48]
lh t1, 112(a0) // t1 = inptr[56]
lh t7, 16(a0) // t7 = inptr[8]
lh t5, 80(a0) // t5 = inptr[40]
lh t3, 48(a0) // t3 = inptr[24]
or s4, s4, t1
or s4, s4, t3
or s4, s4, t5
or s4, s4, t7
or s4, s4, s5
or s4, s4, s6
bnez s4, 2f
addiu v1, v1, -1
lh s5, 0(a1) // quantptr[DCTSIZE*0]
lh s6, 0(a0) // inptr[DCTSIZE*0]
mul s5, s5, s6 // DEQUANTIZE(inptr[0], quantptr[0])
sll s5, s5, 2
sw s5, 0(v0)
sw s5, 32(v0)
sw s5, 64(v0)
sw s5, 96(v0)
sw s5, 128(v0)
sw s5, 160(v0)
sw s5, 192(v0)
b 3f
sw s5, 224(v0)
2:
lh t0, 112(a1)
lh t2, 48(a1)
lh t4, 80(a1)
lh t6, 16(a1)
mul t0, t0, t1 // DEQUANTIZE(inptr[DCTSIZE*7],quant[DCTSIZE*7])
mul t1, t2, t3 // DEQUANTIZE(inptr[DCTSIZE*3],quant[DCTSIZE*3])
mul t2, t4, t5 // DEQUANTIZE(inptr[DCTSIZE*5],quant[DCTSIZE*5])
mul t3, t6, t7 // DEQUANTIZE(inptr[DCTSIZE*1],quant[DCTSIZE*1])
lh t4, 32(a1)
lh t5, 32(a0)
lh t6, 96(a1)
lh t7, 96(a0)
addu s0, t0, t1 // z3 = tmp0 + tmp2
addu s1, t1, t2 // z2 = tmp1 + tmp2
addu s2, t2, t3 // z4 = tmp1 + tmp3
addu s3, s0, s2 // z3 + z4
addiu t9, zero, 9633 // FIX_1_175875602
mul s3, s3, t9 // z5 = MULTIPLY(z3 + z4, FIX_1_175875602)
addu t8, t0, t3 // z1 = tmp0 + tmp3
addiu t9, zero, 2446 // FIX_0_298631336
mul t0, t0, t9 // tmp0 = MULTIPLY(tmp0, FIX_0_298631336)
addiu t9, zero, 16819 // FIX_2_053119869
mul t2, t2, t9 // tmp1 = MULTIPLY(tmp1, FIX_2_053119869)
addiu t9, zero, 25172 // FIX_3_072711026
mul t1, t1, t9 // tmp2 = MULTIPLY(tmp2, FIX_3_072711026)
addiu t9, zero, 12299 // FIX_1_501321110
mul t3, t3, t9 // tmp3 = MULTIPLY(tmp3, FIX_1_501321110)
addiu t9, zero, 16069 // FIX_1_961570560
mul s0, s0, t9 // -z3 = MULTIPLY(z3, FIX_1_961570560)
addiu t9, zero, 3196 // FIX_0_390180644
mul s2, s2, t9 // -z4 = MULTIPLY(z4, FIX_0_390180644)
addiu t9, zero, 7373 // FIX_0_899976223
mul t8, t8, t9 // -z1 = MULTIPLY(z1, FIX_0_899976223)
addiu t9, zero, 20995 // FIX_2_562915447
mul s1, s1, t9 // -z2 = MULTIPLY(z2, FIX_2_562915447)
subu s0, s3, s0 // z3 += z5
addu t0, t0, s0 // tmp0 += z3
addu t1, t1, s0 // tmp2 += z3
subu s2, s3, s2 // z4 += z5
addu t2, t2, s2 // tmp1 += z4
addu t3, t3, s2 // tmp3 += z4
subu t0, t0, t8 // tmp0 += z1
subu t1, t1, s1 // tmp2 += z2
subu t2, t2, s1 // tmp1 += z2
subu t3, t3, t8 // tmp3 += z1
mul s0, t4, t5 // DEQUANTIZE(inptr[DCTSIZE*2],quant[DCTSIZE*2])
addiu t9, zero, 6270 // FIX_0_765366865
mul s1, t6, t7 // DEQUANTIZE(inptr[DCTSIZE*6],quant[DCTSIZE*6])
lh t4, 0(a1)
lh t5, 0(a0)
lh t6, 64(a1)
lh t7, 64(a0)
mul s2, t9, s0 // MULTIPLY(z2, FIX_0_765366865)
mul t5, t4, t5 // DEQUANTIZE(inptr[DCTSIZE*0],quant[DCTSIZE*0])
mul t6, t6, t7 // DEQUANTIZE(inptr[DCTSIZE*4],quant[DCTSIZE*4])
addiu t9, zero, 4433 // FIX_0_541196100
addu s3, s0, s1 // z2 + z3
mul s3, s3, t9 // z1 = MULTIPLY(z2 + z3, FIX_0_541196100)
addiu t9, zero, 15137 // FIX_1_847759065
mul t8, s1, t9 // MULTIPLY(z3, FIX_1_847759065)
addu t4, t5, t6
subu t5, t5, t6
sll t4, t4, 13 // tmp0 = (z2 + z3) << CONST_BITS
sll t5, t5, 13 // tmp1 = (z2 - z3) << CONST_BITS
addu t7, s3, s2 // tmp3 = z1 + MULTIPLY(z2, FIX_0_765366865)
subu t6, s3, t8 // tmp2 = z1 + MULTIPLY(z3, - FIX_1_847759065)
addu s0, t4, t7
subu s1, t4, t7
addu s2, t5, t6
subu s3, t5, t6
addu t4, s0, t3
subu s0, s0, t3
addu t3, s2, t1
subu s2, s2, t1
addu t1, s3, t2
subu s3, s3, t2
addu t2, s1, t0
subu s1, s1, t0
shra_r.w t4, t4, 11
shra_r.w t3, t3, 11
shra_r.w t1, t1, 11
shra_r.w t2, t2, 11
shra_r.w s1, s1, 11
shra_r.w s3, s3, 11
shra_r.w s2, s2, 11
shra_r.w s0, s0, 11
sw t4, 0(v0)
sw t3, 32(v0)
sw t1, 64(v0)
sw t2, 96(v0)
sw s1, 128(v0)
sw s3, 160(v0)
sw s2, 192(v0)
sw s0, 224(v0)
3:
addiu a1, a1, 2
addiu a0, a0, 2
bgtz v1, 1b
addiu v0, v0, 4
move v0, sp
addiu v1, zero, 8
4:
lw t0, 8(v0) // z2 = (INT32) wsptr[2]
lw t1, 24(v0) // z3 = (INT32) wsptr[6]
lw t2, 0(v0) // (INT32) wsptr[0]
lw t3, 16(v0) // (INT32) wsptr[4]
lw s4, 4(v0) // (INT32) wsptr[1]
lw s5, 12(v0) // (INT32) wsptr[3]
lw s6, 20(v0) // (INT32) wsptr[5]
lw s7, 28(v0) // (INT32) wsptr[7]
or s4, s4, t0
or s4, s4, t1
or s4, s4, t3
or s4, s4, s7
or s4, s4, s5
or s4, s4, s6
bnez s4, 5f
addiu v1, v1, -1
shra_r.w s5, t2, 5
andi s5, s5, 0x3ff
lbux s5, s5(a3)
lw s1, 0(a2)
replv.qb s5, s5
usw s5, 0(s1)
usw s5, 4(s1)
b 6f
nop
5:
addu t4, t0, t1 // z2 + z3
addiu t8, zero, 4433 // FIX_0_541196100
mul t5, t4, t8 // z1 = MULTIPLY(z2 + z3, FIX_0_541196100)
addiu t8, zero, 15137 // FIX_1_847759065
mul t1, t1, t8 // MULTIPLY(z3, FIX_1_847759065)
addiu t8, zero, 6270 // FIX_0_765366865
mul t0, t0, t8 // MULTIPLY(z2, FIX_0_765366865)
addu t4, t2, t3 // (INT32) wsptr[0] + (INT32) wsptr[4]
subu t2, t2, t3 // (INT32) wsptr[0] - (INT32) wsptr[4]
sll t4, t4, 13 // tmp0 = ((wsptr[0] + wsptr[4]) << CONST_BITS
sll t2, t2, 13 // tmp1 = ((wsptr[0] - wsptr[4]) << CONST_BITS
subu t1, t5, t1 // tmp2 = z1 + MULTIPLY(z3, - FIX_1_847759065)
subu t3, t2, t1 // tmp12 = tmp1 - tmp2
addu t2, t2, t1 // tmp11 = tmp1 + tmp2
addu t5, t5, t0 // tmp3 = z1 + MULTIPLY(z2, FIX_0_765366865)
subu t1, t4, t5 // tmp13 = tmp0 - tmp3
addu t0, t4, t5 // tmp10 = tmp0 + tmp3
lw t4, 28(v0) // tmp0 = (INT32) wsptr[7]
lw t6, 12(v0) // tmp2 = (INT32) wsptr[3]
lw t5, 20(v0) // tmp1 = (INT32) wsptr[5]
lw t7, 4(v0) // tmp3 = (INT32) wsptr[1]
addu s0, t4, t6 // z3 = tmp0 + tmp2
addiu t8, zero, 9633 // FIX_1_175875602
addu s1, t5, t7 // z4 = tmp1 + tmp3
addu s2, s0, s1 // z3 + z4
mul s2, s2, t8 // z5 = MULTIPLY(z3 + z4, FIX_1_175875602)
addu s3, t4, t7 // z1 = tmp0 + tmp3
addu t9, t5, t6 // z2 = tmp1 + tmp2
addiu t8, zero, 16069 // FIX_1_961570560
mul s0, s0, t8 // -z3 = MULTIPLY(z3, FIX_1_961570560)
addiu t8, zero, 3196 // FIX_0_390180644
mul s1, s1, t8 // -z4 = MULTIPLY(z4, FIX_0_390180644)
addiu t8, zero, 2446 // FIX_0_298631336
mul t4, t4, t8 // tmp0 = MULTIPLY(tmp0, FIX_0_298631336)
addiu t8, zero, 7373 // FIX_0_899976223
mul s3, s3, t8 // -z1 = MULTIPLY(z1, FIX_0_899976223)
addiu t8, zero, 16819 // FIX_2_053119869
mul t5, t5, t8 // tmp1 = MULTIPLY(tmp1, FIX_2_053119869)
addiu t8, zero, 20995 // FIX_2_562915447
mul t9, t9, t8 // -z2 = MULTIPLY(z2, FIX_2_562915447)
addiu t8, zero, 25172 // FIX_3_072711026
mul t6, t6, t8 // tmp2 = MULTIPLY(tmp2, FIX_3_072711026)
addiu t8, zero, 12299 // FIX_1_501321110
mul t7, t7, t8 // tmp3 = MULTIPLY(tmp3, FIX_1_501321110)
subu s0, s2, s0 // z3 += z5
subu s1, s2, s1 // z4 += z5
addu t4, t4, s0
subu t4, t4, s3 // tmp0
addu t5, t5, s1
subu t5, t5, t9 // tmp1
addu t6, t6, s0
subu t6, t6, t9 // tmp2
addu t7, t7, s1
subu t7, t7, s3 // tmp3
addu s0, t0, t7
subu t0, t0, t7
addu t7, t2, t6
subu t2, t2, t6
addu t6, t3, t5
subu t3, t3, t5
addu t5, t1, t4
subu t1, t1, t4
shra_r.w s0, s0, 18
shra_r.w t7, t7, 18
shra_r.w t6, t6, 18
shra_r.w t5, t5, 18
shra_r.w t1, t1, 18
shra_r.w t3, t3, 18
shra_r.w t2, t2, 18
shra_r.w t0, t0, 18
andi s0, s0, 0x3ff
andi t7, t7, 0x3ff
andi t6, t6, 0x3ff
andi t5, t5, 0x3ff
andi t1, t1, 0x3ff
andi t3, t3, 0x3ff
andi t2, t2, 0x3ff
andi t0, t0, 0x3ff
lw s1, 0(a2)
lbux s0, s0(a3)
lbux t7, t7(a3)
lbux t6, t6(a3)
lbux t5, t5(a3)
lbux t1, t1(a3)
lbux t3, t3(a3)
lbux t2, t2(a3)
lbux t0, t0(a3)
sb s0, 0(s1)
sb t7, 1(s1)
sb t6, 2(s1)
sb t5, 3(s1)
sb t1, 4(s1)
sb t3, 5(s1)
sb t2, 6(s1)
sb t0, 7(s1)
6:
addiu v0, v0, 32
bgtz v1, 4b
addiu a2, a2, 4
addiu sp, sp, 256
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_idct_islow_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_idct_ifast_cols_mips_dspr2)
/*
* a0 - inptr
* a1 - quantptr
* a2 - wsptr
* a3 - mips_idct_ifast_coefs
*/
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
addiu t9, a0, 16 // end address
or AT, a3, zero
0:
lw s0, 0(a1) // quantptr[DCTSIZE*0]
lw t0, 0(a0) // inptr[DCTSIZE*0]
lw t1, 16(a0) // inptr[DCTSIZE*1]
muleq_s.w.phl v0, t0, s0 // tmp0 ...
lw t2, 32(a0) // inptr[DCTSIZE*2]
lw t3, 48(a0) // inptr[DCTSIZE*3]
lw t4, 64(a0) // inptr[DCTSIZE*4]
lw t5, 80(a0) // inptr[DCTSIZE*5]
muleq_s.w.phr t0, t0, s0 // ... tmp0 ...
lw t6, 96(a0) // inptr[DCTSIZE*6]
lw t7, 112(a0) // inptr[DCTSIZE*7]
or s4, t1, t2
or s5, t3, t4
bnez s4, 1f
ins t0, v0, 16, 16 // ... tmp0
bnez s5, 1f
or s6, t5, t6
or s6, s6, t7
bnez s6, 1f
sw t0, 0(a2) // wsptr[DCTSIZE*0]
sw t0, 16(a2) // wsptr[DCTSIZE*1]
sw t0, 32(a2) // wsptr[DCTSIZE*2]
sw t0, 48(a2) // wsptr[DCTSIZE*3]
sw t0, 64(a2) // wsptr[DCTSIZE*4]
sw t0, 80(a2) // wsptr[DCTSIZE*5]
sw t0, 96(a2) // wsptr[DCTSIZE*6]
sw t0, 112(a2) // wsptr[DCTSIZE*7]
addiu a0, a0, 4
b 2f
addiu a1, a1, 4
1:
lw s1, 32(a1) // quantptr[DCTSIZE*2]
lw s2, 64(a1) // quantptr[DCTSIZE*4]
muleq_s.w.phl v0, t2, s1 // tmp1 ...
muleq_s.w.phr t2, t2, s1 // ... tmp1 ...
lw s0, 16(a1) // quantptr[DCTSIZE*1]
lw s1, 48(a1) // quantptr[DCTSIZE*3]
lw s3, 96(a1) // quantptr[DCTSIZE*6]
muleq_s.w.phl v1, t4, s2 // tmp2 ...
muleq_s.w.phr t4, t4, s2 // ... tmp2 ...
lw s2, 80(a1) // quantptr[DCTSIZE*5]
lw t8, 4(AT) // FIX(1.414213562)
ins t2, v0, 16, 16 // ... tmp1
muleq_s.w.phl v0, t6, s3 // tmp3 ...
muleq_s.w.phr t6, t6, s3 // ... tmp3 ...
ins t4, v1, 16, 16 // ... tmp2
addq.ph s4, t0, t4 // tmp10
subq.ph s5, t0, t4 // tmp11
ins t6, v0, 16, 16 // ... tmp3
subq.ph s6, t2, t6 // tmp12 ...
addq.ph s7, t2, t6 // tmp13
mulq_s.ph s6, s6, t8 // ... tmp12 ...
addq.ph t0, s4, s7 // tmp0
subq.ph t6, s4, s7 // tmp3
muleq_s.w.phl v0, t1, s0 // tmp4 ...
muleq_s.w.phr t1, t1, s0 // ... tmp4 ...
shll_s.ph s6, s6, 1 // x2
lw s3, 112(a1) // quantptr[DCTSIZE*7]
subq.ph s6, s6, s7 // ... tmp12
muleq_s.w.phl v1, t7, s3 // tmp7 ...
muleq_s.w.phr t7, t7, s3 // ... tmp7 ...
ins t1, v0, 16, 16 // ... tmp4
addq.ph t2, s5, s6 // tmp1
subq.ph t4, s5, s6 // tmp2
muleq_s.w.phl v0, t5, s2 // tmp6 ...
muleq_s.w.phr t5, t5, s2 // ... tmp6 ...
ins t7, v1, 16, 16 // ... tmp7
addq.ph s5, t1, t7 // z11
subq.ph s6, t1, t7 // z12
muleq_s.w.phl v1, t3, s1 // tmp5 ...
muleq_s.w.phr t3, t3, s1 // ... tmp5 ...
ins t5, v0, 16, 16 // ... tmp6
ins t3, v1, 16, 16 // ... tmp5
addq.ph s7, t5, t3 // z13
subq.ph v0, t5, t3 // z10
addq.ph t7, s5, s7 // tmp7
subq.ph s5, s5, s7 // tmp11 ...
addq.ph v1, v0, s6 // z5 ...
mulq_s.ph s5, s5, t8 // ... tmp11
lw t8, 8(AT) // FIX(1.847759065)
lw s4, 0(AT) // FIX(1.082392200)
addq.ph s0, t0, t7
subq.ph s1, t0, t7
mulq_s.ph v1, v1, t8 // ... z5
shll_s.ph s5, s5, 1 // x2
lw t8, 12(AT) // FIX(-2.613125930)
sw s0, 0(a2) // wsptr[DCTSIZE*0]
shll_s.ph v0, v0, 1 // x4
mulq_s.ph v0, v0, t8 // tmp12 ...
mulq_s.ph s4, s6, s4 // tmp10 ...
shll_s.ph v1, v1, 1 // x2
addiu a0, a0, 4
addiu a1, a1, 4
sw s1, 112(a2) // wsptr[DCTSIZE*7]
shll_s.ph s6, v0, 1 // x4
shll_s.ph s4, s4, 1 // x2
addq.ph s6, s6, v1 // ... tmp12
subq.ph t5, s6, t7 // tmp6
subq.ph s4, s4, v1 // ... tmp10
subq.ph t3, s5, t5 // tmp5
addq.ph s2, t2, t5
addq.ph t1, s4, t3 // tmp4
subq.ph s3, t2, t5
sw s2, 16(a2) // wsptr[DCTSIZE*1]
sw s3, 96(a2) // wsptr[DCTSIZE*6]
addq.ph v0, t4, t3
subq.ph v1, t4, t3
sw v0, 32(a2) // wsptr[DCTSIZE*2]
sw v1, 80(a2) // wsptr[DCTSIZE*5]
addq.ph v0, t6, t1
subq.ph v1, t6, t1
sw v0, 64(a2) // wsptr[DCTSIZE*4]
sw v1, 48(a2) // wsptr[DCTSIZE*3]
2:
bne a0, t9, 0b
addiu a2, a2, 4
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_idct_ifast_cols_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_idct_ifast_rows_mips_dspr2)
/*
* a0 - wsptr
* a1 - output_buf
* a2 - output_col
* a3 - mips_idct_ifast_coefs
*/
SAVE_REGS_ON_STACK 40, s0, s1, s2, s3, s4, s5, s6, s7, s8, a3
addiu t9, a0, 128 // end address
lui s8, 0x8080
ori s8, s8, 0x8080
0:
lw AT, 36(sp) // restore $a3 (mips_idct_ifast_coefs)
lw t0, 0(a0) // wsptr[DCTSIZE*0+0/1] b a
lw s0, 16(a0) // wsptr[DCTSIZE*1+0/1] B A
lw t2, 4(a0) // wsptr[DCTSIZE*0+2/3] d c
lw s2, 20(a0) // wsptr[DCTSIZE*1+2/3] D C
lw t4, 8(a0) // wsptr[DCTSIZE*0+4/5] f e
lw s4, 24(a0) // wsptr[DCTSIZE*1+4/5] F E
lw t6, 12(a0) // wsptr[DCTSIZE*0+6/7] h g
lw s6, 28(a0) // wsptr[DCTSIZE*1+6/7] H G
precrq.ph.w t1, s0, t0 // B b
ins t0, s0, 16, 16 // A a
bnez t1, 1f
or s0, t2, s2
bnez s0, 1f
or s0, t4, s4
bnez s0, 1f
or s0, t6, s6
bnez s0, 1f
shll_s.ph s0, t0, 2 // A a
lw a3, 0(a1)
lw AT, 4(a1)
precrq.ph.w t0, s0, s0 // A A
ins s0, s0, 16, 16 // a a
addu a3, a3, a2
addu AT, AT, a2
precrq.qb.ph t0, t0, t0 // A A A A
precrq.qb.ph s0, s0, s0 // a a a a
addu.qb s0, s0, s8
addu.qb t0, t0, s8
sw s0, 0(a3)
sw s0, 4(a3)
sw t0, 0(AT)
sw t0, 4(AT)
addiu a0, a0, 32
bne a0, t9, 0b
addiu a1, a1, 8
b 2f
nop
1:
precrq.ph.w t3, s2, t2
ins t2, s2, 16, 16
precrq.ph.w t5, s4, t4
ins t4, s4, 16, 16
precrq.ph.w t7, s6, t6
ins t6, s6, 16, 16
lw t8, 4(AT) // FIX(1.414213562)
addq.ph s4, t0, t4 // tmp10
subq.ph s5, t0, t4 // tmp11
subq.ph s6, t2, t6 // tmp12 ...
addq.ph s7, t2, t6 // tmp13
mulq_s.ph s6, s6, t8 // ... tmp12 ...
addq.ph t0, s4, s7 // tmp0
subq.ph t6, s4, s7 // tmp3
shll_s.ph s6, s6, 1 // x2
subq.ph s6, s6, s7 // ... tmp12
addq.ph t2, s5, s6 // tmp1
subq.ph t4, s5, s6 // tmp2
addq.ph s5, t1, t7 // z11
subq.ph s6, t1, t7 // z12
addq.ph s7, t5, t3 // z13
subq.ph v0, t5, t3 // z10
addq.ph t7, s5, s7 // tmp7
subq.ph s5, s5, s7 // tmp11 ...
addq.ph v1, v0, s6 // z5 ...
mulq_s.ph s5, s5, t8 // ... tmp11
lw t8, 8(AT) // FIX(1.847759065)
lw s4, 0(AT) // FIX(1.082392200)
addq.ph s0, t0, t7 // tmp0 + tmp7
subq.ph s7, t0, t7 // tmp0 - tmp7
mulq_s.ph v1, v1, t8 // ... z5
lw a3, 0(a1)
lw t8, 12(AT) // FIX(-2.613125930)
shll_s.ph s5, s5, 1 // x2
addu a3, a3, a2
shll_s.ph v0, v0, 1 // x4
mulq_s.ph v0, v0, t8 // tmp12 ...
mulq_s.ph s4, s6, s4 // tmp10 ...
shll_s.ph v1, v1, 1 // x2
addiu a0, a0, 32
addiu a1, a1, 8
shll_s.ph s6, v0, 1 // x4
shll_s.ph s4, s4, 1 // x2
addq.ph s6, s6, v1 // ... tmp12
shll_s.ph s0, s0, 2
subq.ph t5, s6, t7 // tmp6
subq.ph s4, s4, v1 // ... tmp10
subq.ph t3, s5, t5 // tmp5
shll_s.ph s7, s7, 2
addq.ph t1, s4, t3 // tmp4
addq.ph s1, t2, t5 // tmp1 + tmp6
subq.ph s6, t2, t5 // tmp1 - tmp6
addq.ph s2, t4, t3 // tmp2 + tmp5
subq.ph s5, t4, t3 // tmp2 - tmp5
addq.ph s4, t6, t1 // tmp3 + tmp4
subq.ph s3, t6, t1 // tmp3 - tmp4
shll_s.ph s1, s1, 2
shll_s.ph s2, s2, 2
shll_s.ph s3, s3, 2
shll_s.ph s4, s4, 2
shll_s.ph s5, s5, 2
shll_s.ph s6, s6, 2
precrq.ph.w t0, s1, s0 // B A
ins s0, s1, 16, 16 // b a
precrq.ph.w t2, s3, s2 // D C
ins s2, s3, 16, 16 // d c
precrq.ph.w t4, s5, s4 // F E
ins s4, s5, 16, 16 // f e
precrq.ph.w t6, s7, s6 // H G
ins s6, s7, 16, 16 // h g
precrq.qb.ph t0, t2, t0 // D C B A
precrq.qb.ph s0, s2, s0 // d c b a
precrq.qb.ph t4, t6, t4 // H G F E
precrq.qb.ph s4, s6, s4 // h g f e
addu.qb s0, s0, s8
addu.qb s4, s4, s8
sw s0, 0(a3) // outptr[0/1/2/3] d c b a
sw s4, 4(a3) // outptr[4/5/6/7] h g f e
lw a3, -4(a1)
addu.qb t0, t0, s8
addu a3, a3, a2
addu.qb t4, t4, s8
sw t0, 0(a3) // outptr[0/1/2/3] D C B A
bne a0, t9, 0b
sw t4, 4(a3) // outptr[4/5/6/7] H G F E
2:
RESTORE_REGS_FROM_STACK 40, s0, s1, s2, s3, s4, s5, s6, s7, s8, a3
j ra
nop
END(jsimd_idct_ifast_rows_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_fdct_islow_mips_dspr2)
/*
* a0 - data
*/
SAVE_REGS_ON_STACK 40, s0, s1, s2, s3, s4, s5, s6, s7, s8
lui t0, 6437
ori t0, 2260
lui t1, 9633
ori t1, 11363
lui t2, 0xd39e
ori t2, 0xe6dc
lui t3, 0xf72d
ori t3, 9633
lui t4, 2261
ori t4, 9633
lui t5, 0xd39e
ori t5, 6437
lui t6, 9633
ori t6, 0xd39d
lui t7, 0xe6dc
ori t7, 2260
lui t8, 4433
ori t8, 10703
lui t9, 0xd630
ori t9, 4433
li s8, 8
move a1, a0
1:
lw s0, 0(a1) // tmp0 = 1|0
lw s1, 4(a1) // tmp1 = 3|2
lw s2, 8(a1) // tmp2 = 5|4
lw s3, 12(a1) // tmp3 = 7|6
packrl.ph s1, s1, s1 // tmp1 = 2|3
packrl.ph s3, s3, s3 // tmp3 = 6|7
subq.ph s7, s1, s2 // tmp7 = 2-5|3-4 = t5|t4
subq.ph s5, s0, s3 // tmp5 = 1-6|0-7 = t6|t7
mult $0, $0 // ac0 = 0
dpa.w.ph $ac0, s7, t0 // ac0 += t5* 6437 + t4* 2260
dpa.w.ph $ac0, s5, t1 // ac0 += t6* 9633 + t7* 11363
mult $ac1, $0, $0 // ac1 = 0
dpa.w.ph $ac1, s7, t2 // ac1 += t5*-11362 + t4* -6436
dpa.w.ph $ac1, s5, t3 // ac1 += t6* -2259 + t7* 9633
mult $ac2, $0, $0 // ac2 = 0
dpa.w.ph $ac2, s7, t4 // ac2 += t5* 2261 + t4* 9633
dpa.w.ph $ac2, s5, t5 // ac2 += t6*-11362 + t7* 6437
mult $ac3, $0, $0 // ac3 = 0
dpa.w.ph $ac3, s7, t6 // ac3 += t5* 9633 + t4*-11363
dpa.w.ph $ac3, s5, t7 // ac3 += t6* -6436 + t7* 2260
addq.ph s6, s1, s2 // tmp6 = 2+5|3+4 = t2|t3
addq.ph s4, s0, s3 // tmp4 = 1+6|0+7 = t1|t0
extr_r.w s0, $ac0, 11 // tmp0 = (ac0 + 1024) >> 11
extr_r.w s1, $ac1, 11 // tmp1 = (ac1 + 1024) >> 11
extr_r.w s2, $ac2, 11 // tmp2 = (ac2 + 1024) >> 11
extr_r.w s3, $ac3, 11 // tmp3 = (ac3 + 1024) >> 11
addq.ph s5, s4, s6 // tmp5 = t1+t2|t0+t3 = t11|t10
subq.ph s7, s4, s6 // tmp7 = t1-t2|t0-t3 = t12|t13
sh s0, 2(a1)
sh s1, 6(a1)
sh s2, 10(a1)
sh s3, 14(a1)
mult $0, $0 // ac0 = 0
dpa.w.ph $ac0, s7, t8 // ac0 += t12* 4433 + t13* 10703
mult $ac1, $0, $0 // ac1 = 0
dpa.w.ph $ac1, s7, t9 // ac1 += t12*-10704 + t13* 4433
sra s4, s5, 16 // tmp4 = t11
addiu a1, a1, 16
addiu s8, s8, -1
extr_r.w s0, $ac0, 11 // tmp0 = (ac0 + 1024) >> 11
extr_r.w s1, $ac1, 11 // tmp1 = (ac1 + 1024) >> 11
addu s2, s5, s4 // tmp2 = t10 + t11
subu s3, s5, s4 // tmp3 = t10 - t11
sll s2, s2, 2 // tmp2 = (t10 + t11) << 2
sll s3, s3, 2 // tmp3 = (t10 - t11) << 2
sh s2, -16(a1)
sh s3, -8(a1)
sh s0, -12(a1)
bgtz s8, 1b
sh s1, -4(a1)
li t0, 2260
li t1, 11363
li t2, 9633
li t3, 6436
li t4, 6437
li t5, 2261
li t6, 11362
li t7, 2259
li t8, 4433
li t9, 10703
li a1, 10704
li s8, 8
2:
lh a2, 0(a0) // 0
lh a3, 16(a0) // 8
lh v0, 32(a0) // 16
lh v1, 48(a0) // 24
lh s4, 64(a0) // 32
lh s5, 80(a0) // 40
lh s6, 96(a0) // 48
lh s7, 112(a0) // 56
addu s2, v0, s5 // tmp2 = 16 + 40
subu s5, v0, s5 // tmp5 = 16 - 40
addu s3, v1, s4 // tmp3 = 24 + 32
subu s4, v1, s4 // tmp4 = 24 - 32
addu s0, a2, s7 // tmp0 = 0 + 56
subu s7, a2, s7 // tmp7 = 0 - 56
addu s1, a3, s6 // tmp1 = 8 + 48
subu s6, a3, s6 // tmp6 = 8 - 48
addu a2, s0, s3 // tmp10 = tmp0 + tmp3
subu v1, s0, s3 // tmp13 = tmp0 - tmp3
addu a3, s1, s2 // tmp11 = tmp1 + tmp2
subu v0, s1, s2 // tmp12 = tmp1 - tmp2
mult s7, t1 // ac0 = tmp7 * c1
madd s4, t0 // ac0 += tmp4 * c0
madd s5, t4 // ac0 += tmp5 * c4
madd s6, t2 // ac0 += tmp6 * c2
mult $ac1, s7, t2 // ac1 = tmp7 * c2
msub $ac1, s4, t3 // ac1 -= tmp4 * c3
msub $ac1, s5, t6 // ac1 -= tmp5 * c6
msub $ac1, s6, t7 // ac1 -= tmp6 * c7
mult $ac2, s7, t4 // ac2 = tmp7 * c4
madd $ac2, s4, t2 // ac2 += tmp4 * c2
madd $ac2, s5, t5 // ac2 += tmp5 * c5
msub $ac2, s6, t6 // ac2 -= tmp6 * c6
mult $ac3, s7, t0 // ac3 = tmp7 * c0
msub $ac3, s4, t1 // ac3 -= tmp4 * c1
madd $ac3, s5, t2 // ac3 += tmp5 * c2
msub $ac3, s6, t3 // ac3 -= tmp6 * c3
extr_r.w s0, $ac0, 15 // tmp0 = (ac0 + 16384) >> 15
extr_r.w s1, $ac1, 15 // tmp1 = (ac1 + 16384) >> 15
extr_r.w s2, $ac2, 15 // tmp2 = (ac2 + 16384) >> 15
extr_r.w s3, $ac3, 15 // tmp3 = (ac3 + 16384) >> 15
addiu s8, s8, -1
addu s4, a2, a3 // tmp4 = tmp10 + tmp11
subu s5, a2, a3 // tmp5 = tmp10 - tmp11
sh s0, 16(a0)
sh s1, 48(a0)
sh s2, 80(a0)
sh s3, 112(a0)
mult v0, t8 // ac0 = tmp12 * c8
madd v1, t9 // ac0 += tmp13 * c9
mult $ac1, v1, t8 // ac1 = tmp13 * c8
msub $ac1, v0, a1 // ac1 -= tmp12 * c10
addiu a0, a0, 2
extr_r.w s6, $ac0, 15 // tmp6 = (ac0 + 16384) >> 15
extr_r.w s7, $ac1, 15 // tmp7 = (ac1 + 16384) >> 15
shra_r.w s4, s4, 2 // tmp4 = (tmp4 + 2) >> 2
shra_r.w s5, s5, 2 // tmp5 = (tmp5 + 2) >> 2
sh s4, -2(a0)
sh s5, 62(a0)
sh s6, 30(a0)
bgtz s8, 2b
sh s7, 94(a0)
RESTORE_REGS_FROM_STACK 40, s0, s1, s2, s3, s4, s5, s6, s7, s8
jr ra
nop
END(jsimd_fdct_islow_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_fdct_ifast_mips_dspr2)
/*
* a0 - data
*/
.set at
SAVE_REGS_ON_STACK 8, s0, s1
li a1, 0x014e014e // FIX_1_306562965 (334 << 16)|(334 & 0xffff)
li a2, 0x008b008b // FIX_0_541196100 (139 << 16)|(139 & 0xffff)
li a3, 0x00620062 // FIX_0_382683433 (98 << 16) |(98 & 0xffff)
li s1, 0x00b500b5 // FIX_0_707106781 (181 << 16)|(181 & 0xffff)
move v0, a0
addiu v1, v0, 128 // end address
0:
lw t0, 0(v0) // tmp0 = 1|0
lw t1, 4(v0) // tmp1 = 3|2
lw t2, 8(v0) // tmp2 = 5|4
lw t3, 12(v0) // tmp3 = 7|6
packrl.ph t1, t1, t1 // tmp1 = 2|3
packrl.ph t3, t3, t3 // tmp3 = 6|7
subq.ph t7, t1, t2 // tmp7 = 2-5|3-4 = t5|t4
subq.ph t5, t0, t3 // tmp5 = 1-6|0-7 = t6|t7
addq.ph t6, t1, t2 // tmp6 = 2+5|3+4 = t2|t3
addq.ph t4, t0, t3 // tmp4 = 1+6|0+7 = t1|t0
addq.ph t8, t4, t6 // tmp5 = t1+t2|t0+t3 = t11|t10
subq.ph t9, t4, t6 // tmp7 = t1-t2|t0-t3 = t12|t13
sra t4, t8, 16 // tmp4 = t11
mult $0, $0 // ac0 = 0
dpa.w.ph $ac0, t9, s1
mult $ac1, $0, $0 // ac1 = 0
dpa.w.ph $ac1, t7, a3 // ac1 += t4*98 + t5*98
dpsx.w.ph $ac1, t5, a3 // ac1 += t6*98 + t7*98
mult $ac2, $0, $0 // ac2 = 0
dpa.w.ph $ac2, t7, a2 // ac2 += t4*139 + t5*139
mult $ac3, $0, $0 // ac3 = 0
dpa.w.ph $ac3, t5, a1 // ac3 += t6*334 + t7*334
precrq.ph.w t0, t5, t7 // t0 = t5|t6
addq.ph t2, t8, t4 // tmp2 = t10 + t11
subq.ph t3, t8, t4 // tmp3 = t10 - t11
extr.w t4, $ac0, 8
mult $0, $0 // ac0 = 0
dpa.w.ph $ac0, t0, s1 // ac0 += t5*181 + t6*181
extr.w t0, $ac1, 8 // t0 = z5
extr.w t1, $ac2, 8 // t1 = MULTIPLY(tmp10, 139)
extr.w t7, $ac3, 8 // t2 = MULTIPLY(tmp12, 334)
extr.w t8, $ac0, 8 // t8 = z3 = MULTIPLY(tmp11, 181)
add t6, t1, t0 // t6 = z2
add t7, t7, t0 // t7 = z4
subq.ph t0, t5, t8 // t0 = z13 = tmp7 - z3
addq.ph t8, t5, t8 // t9 = z11 = tmp7 + z3
addq.ph t1, t0, t6 // t1 = z13 + z2
subq.ph t6, t0, t6 // t6 = z13 - z2
addq.ph t0, t8, t7 // t0 = z11 + z4
subq.ph t7, t8, t7 // t7 = z11 - z4
addq.ph t5, t4, t9
subq.ph t4, t9, t4
sh t2, 0(v0)
sh t5, 4(v0)
sh t3, 8(v0)
sh t4, 12(v0)
sh t1, 10(v0)
sh t6, 6(v0)
sh t0, 2(v0)
sh t7, 14(v0)
addiu v0, 16
bne v1, v0, 0b
nop
move v0, a0
addiu v1, v0, 16
1:
lh t0, 0(v0) // 0
lh t1, 16(v0) // 8
lh t2, 32(v0) // 16
lh t3, 48(v0) // 24
lh t4, 64(v0) // 32
lh t5, 80(v0) // 40
lh t6, 96(v0) // 48
lh t7, 112(v0) // 56
add t8, t0, t7 // t8 = tmp0
sub t7, t0, t7 // t7 = tmp7
add t0, t1, t6 // t0 = tmp1
sub t1, t1, t6 // t1 = tmp6
add t6, t2, t5 // t6 = tmp2
sub t5, t2, t5 // t5 = tmp5
add t2, t3, t4 // t2 = tmp3
sub t3, t3, t4 // t3 = tmp4
add t4, t8, t2 // t4 = tmp10 = tmp0 + tmp3
sub t8, t8, t2 // t8 = tmp13 = tmp0 - tmp3
sub s0, t0, t6 // s0 = tmp12 = tmp1 - tmp2
ins t8, s0, 16, 16 // t8 = tmp12|tmp13
add t2, t0, t6 // t2 = tmp11 = tmp1 + tmp2
mult $0, $0 // ac0 = 0
dpa.w.ph $ac0, t8, s1 // ac0 += t12*181 + t13*181
add s0, t4, t2 // t8 = tmp10+tmp11
sub t4, t4, t2 // t4 = tmp10-tmp11
sh s0, 0(v0)
sh t4, 64(v0)
extr.w t2, $ac0, 8 // z1 = MULTIPLY(tmp12+tmp13,FIX_0_707106781)
addq.ph t4, t8, t2 // t9 = tmp13 + z1
subq.ph t8, t8, t2 // t2 = tmp13 - z1
sh t4, 32(v0)
sh t8, 96(v0)
add t3, t3, t5 // t3 = tmp10 = tmp4 + tmp5
add t0, t5, t1 // t0 = tmp11 = tmp5 + tmp6
add t1, t1, t7 // t1 = tmp12 = tmp6 + tmp7
andi t4, a1, 0xffff
mul s0, t1, t4
sra s0, s0, 8 // s0 = z4 = MULTIPLY(tmp12, FIX_1_306562965)
ins t1, t3, 16, 16 // t1 = tmp10|tmp12
mult $0, $0 // ac0 = 0
mulsa.w.ph $ac0, t1, a3 // ac0 += t10*98 - t12*98
extr.w t8, $ac0, 8 // z5 = MULTIPLY(tmp10-tmp12,FIX_0_382683433)
add t2, t7, t8 // t2 = tmp7 + z5
sub t7, t7, t8 // t7 = tmp7 - z5
andi t4, a2, 0xffff
mul t8, t3, t4
sra t8, t8, 8 // t8 = z2 = MULTIPLY(tmp10, FIX_0_541196100)
andi t4, s1, 0xffff
mul t6, t0, t4
sra t6, t6, 8 // t6 = z3 = MULTIPLY(tmp11, FIX_0_707106781)
add t0, t6, t8 // t0 = z3 + z2
sub t1, t6, t8 // t1 = z3 - z2
add t3, t6, s0 // t3 = z3 + z4
sub t4, t6, s0 // t4 = z3 - z4
sub t5, t2, t1 // t5 = dataptr[5]
sub t6, t7, t0 // t6 = dataptr[3]
add t3, t2, t3 // t3 = dataptr[1]
add t4, t7, t4 // t4 = dataptr[7]
sh t5, 80(v0)
sh t6, 48(v0)
sh t3, 16(v0)
sh t4, 112(v0)
addiu v0, 2
bne v0, v1, 1b
nop
RESTORE_REGS_FROM_STACK 8, s0, s1
j ra
nop
END(jsimd_fdct_ifast_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_quantize_mips_dspr2)
/*
* a0 - coef_block
* a1 - divisors
* a2 - workspace
*/
.set at
SAVE_REGS_ON_STACK 16, s0, s1, s2
addiu v0, a2, 124 // v0 = workspace_end
lh t0, 0(a2)
lh t1, 0(a1)
lh t2, 128(a1)
sra t3, t0, 15
sll t3, t3, 1
addiu t3, t3, 1
mul t0, t0, t3
lh t4, 384(a1)
lh t5, 130(a1)
lh t6, 2(a2)
lh t7, 2(a1)
lh t8, 386(a1)
1:
andi t1, 0xffff
add t9, t0, t2
andi t9, 0xffff
mul v1, t9, t1
sra s0, t6, 15
sll s0, s0, 1
addiu s0, s0, 1
addiu t9, t4, 16
srav v1, v1, t9
mul v1, v1, t3
mul t6, t6, s0
andi t7, 0xffff
addiu a2, a2, 4
addiu a1, a1, 4
add s1, t6, t5
andi s1, 0xffff
sh v1, 0(a0)
mul s2, s1, t7
addiu s1, t8, 16
srav s2, s2, s1
mul s2,s2, s0
lh t0, 0(a2)
lh t1, 0(a1)
sra t3, t0, 15
sll t3, t3, 1
addiu t3, t3, 1
mul t0, t0, t3
lh t2, 128(a1)
lh t4, 384(a1)
lh t5, 130(a1)
lh t8, 386(a1)
lh t6, 2(a2)
lh t7, 2(a1)
sh s2, 2(a0)
lh t0, 0(a2)
sra t3, t0, 15
sll t3, t3, 1
addiu t3, t3, 1
mul t0, t0,t3
bne a2, v0, 1b
addiu a0, a0, 4
andi t1, 0xffff
add t9, t0, t2
andi t9, 0xffff
mul v1, t9, t1
sra s0, t6, 15
sll s0, s0, 1
addiu s0, s0, 1
addiu t9, t4, 16
srav v1, v1, t9
mul v1, v1, t3
mul t6, t6, s0
andi t7, 0xffff
sh v1, 0(a0)
add s1, t6, t5
andi s1, 0xffff
mul s2, s1, t7
addiu s1, t8, 16
addiu a2, a2, 4
addiu a1, a1, 4
srav s2, s2, s1
mul s2, s2, s0
sh s2, 2(a0)
RESTORE_REGS_FROM_STACK 16, s0, s1, s2
j ra
nop
END(jsimd_quantize_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_quantize_float_mips_dspr2)
/*
* a0 - coef_block
* a1 - divisors
* a2 - workspace
*/
.set at
li t1, 0x46800100 //integer representation 16384.5
mtc1 t1, f0
li t0, 63
0:
lwc1 f1, 0(a2)
lwc1 f5, 0(a1)
lwc1 f2, 4(a2)
lwc1 f6, 4(a1)
lwc1 f3, 8(a2)
lwc1 f7, 8(a1)
lwc1 f4, 12(a2)
lwc1 f8, 12(a1)
madd.s f1, f0, f1, f5
madd.s f2, f0, f2, f6
madd.s f3, f0, f3, f7
madd.s f4, f0, f4, f8
lwc1 f5, 16(a1)
lwc1 f6, 20(a1)
trunc.w.s f1, f1
trunc.w.s f2, f2
trunc.w.s f3, f3
trunc.w.s f4, f4
lwc1 f7, 24(a1)
lwc1 f8, 28(a1)
mfc1 t1, f1
mfc1 t2, f2
mfc1 t3, f3
mfc1 t4, f4
lwc1 f1, 16(a2)
lwc1 f2, 20(a2)
lwc1 f3, 24(a2)
lwc1 f4, 28(a2)
madd.s f1, f0, f1, f5
madd.s f2, f0, f2, f6
madd.s f3, f0, f3, f7
madd.s f4, f0, f4, f8
addiu t1, t1, -16384
addiu t2, t2, -16384
addiu t3, t3, -16384
addiu t4, t4, -16384
trunc.w.s f1, f1
trunc.w.s f2, f2
trunc.w.s f3, f3
trunc.w.s f4, f4
sh t1, 0(a0)
sh t2, 2(a0)
sh t3, 4(a0)
sh t4, 6(a0)
mfc1 t1, f1
mfc1 t2, f2
mfc1 t3, f3
mfc1 t4, f4
addiu t0, t0, -8
addiu a2, a2, 32
addiu a1, a1, 32
addiu t1, t1, -16384
addiu t2, t2, -16384
addiu t3, t3, -16384
addiu t4, t4, -16384
sh t1, 8(a0)
sh t2, 10(a0)
sh t3, 12(a0)
sh t4, 14(a0)
bgez t0, 0b
addiu a0, a0, 16
j ra
nop
END(jsimd_quantize_float_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_idct_2x2_mips_dspr2)
/*
* a0 - compptr->dct_table
* a1 - coef_block
* a2 - output_buf
* a3 - output_col
*/
.set at
SAVE_REGS_ON_STACK 24, s0, s1, s2, s3, s4, s5
addiu sp, sp, -40
move v0, sp
addiu s2, zero, 29692
addiu s3, zero, -10426
addiu s4, zero, 6967
addiu s5, zero, -5906
lh t0, 0(a1) // t0 = inptr[DCTSIZE*0]
lh t5, 0(a0) // t5 = quantptr[DCTSIZE*0]
lh t1, 48(a1) // t1 = inptr[DCTSIZE*3]
lh t6, 48(a0) // t6 = quantptr[DCTSIZE*3]
mul t4, t5, t0
lh t0, 16(a1) // t0 = inptr[DCTSIZE*1]
lh t5, 16(a0) // t5 = quantptr[DCTSIZE*1]
mul t6, t6, t1
mul t5, t5, t0
lh t2, 80(a1) // t2 = inptr[DCTSIZE*5]
lh t7, 80(a0) // t7 = quantptr[DCTSIZE*5]
lh t3, 112(a1) // t3 = inptr[DCTSIZE*7]
lh t8, 112(a0) // t8 = quantptr[DCTSIZE*7]
mul t7, t7, t2
mult zero, zero
mul t8, t8, t3
li s0, 0x73FCD746 // s0 = (29692 << 16) | (-10426 & 0xffff)
li s1, 0x1B37E8EE // s1 = (6967 << 16) | (-5906 & 0xffff)
ins t6, t5, 16, 16 // t6 = t5|t6
sll t4, t4, 15
dpa.w.ph $ac0, t6, s0
lh t1, 2(a1)
lh t6, 2(a0)
ins t8, t7, 16, 16 // t8 = t7|t8
dpa.w.ph $ac0, t8, s1
mflo t0, $ac0
mul t5, t6, t1
lh t1, 18(a1)
lh t6, 18(a0)
lh t2, 50(a1)
lh t7, 50(a0)
mul t6, t6, t1
subu t8, t4, t0
mul t7, t7, t2
addu t0, t4, t0
shra_r.w t0, t0, 13
lh t1, 82(a1)
lh t2, 82(a0)
lh t3, 114(a1)
lh t4, 114(a0)
shra_r.w t8, t8, 13
mul t1, t1, t2
mul t3, t3, t4
sw t0, 0(v0)
sw t8, 20(v0)
sll t4, t5, 15
ins t7, t6, 16, 16
mult zero, zero
dpa.w.ph $ac0, t7, s0
ins t3, t1, 16, 16
lh t1, 6(a1)
lh t6, 6(a0)
dpa.w.ph $ac0, t3, s1
mflo t0, $ac0
mul t5, t6, t1
lh t1, 22(a1)
lh t6, 22(a0)
lh t2, 54(a1)
lh t7, 54(a0)
mul t6, t6, t1
subu t8, t4, t0
mul t7, t7, t2
addu t0, t4, t0
shra_r.w t0, t0, 13
lh t1, 86(a1)
lh t2, 86(a0)
lh t3, 118(a1)
lh t4, 118(a0)
shra_r.w t8, t8, 13
mul t1, t1, t2
mul t3, t3, t4
sw t0, 4(v0)
sw t8, 24(v0)
sll t4, t5, 15
ins t7, t6, 16, 16
mult zero, zero
dpa.w.ph $ac0, t7, s0
ins t3, t1, 16, 16
lh t1, 10(a1)
lh t6, 10(a0)
dpa.w.ph $ac0, t3, s1
mflo t0, $ac0
mul t5, t6, t1
lh t1, 26(a1)
lh t6, 26(a0)
lh t2, 58(a1)
lh t7, 58(a0)
mul t6, t6, t1
subu t8, t4, t0
mul t7, t7, t2
addu t0, t4, t0
shra_r.w t0, t0, 13
lh t1, 90(a1)
lh t2, 90(a0)
lh t3, 122(a1)
lh t4, 122(a0)
shra_r.w t8, t8, 13
mul t1, t1, t2
mul t3, t3, t4
sw t0, 8(v0)
sw t8, 28(v0)
sll t4, t5, 15
ins t7, t6, 16, 16
mult zero, zero
dpa.w.ph $ac0, t7, s0
ins t3, t1, 16, 16
lh t1, 14(a1)
lh t6, 14(a0)
dpa.w.ph $ac0, t3, s1
mflo t0, $ac0
mul t5, t6, t1
lh t1, 30(a1)
lh t6, 30(a0)
lh t2, 62(a1)
lh t7, 62(a0)
mul t6, t6, t1
subu t8, t4, t0
mul t7, t7, t2
addu t0, t4, t0
shra_r.w t0, t0, 13
lh t1, 94(a1)
lh t2, 94(a0)
lh t3, 126(a1)
lh t4, 126(a0)
shra_r.w t8, t8, 13
mul t1, t1, t2
mul t3, t3, t4
sw t0, 12(v0)
sw t8, 32(v0)
sll t4, t5, 15
ins t7, t6, 16, 16
mult zero, zero
dpa.w.ph $ac0, t7, s0
ins t3, t1, 16, 16
dpa.w.ph $ac0, t3, s1
mflo t0, $ac0
lw t9, 0(a2)
lw t3, 0(v0)
lw t7, 4(v0)
lw t1, 8(v0)
addu t9, t9, a3
sll t3, t3, 15
subu t8, t4, t0
addu t0, t4, t0
shra_r.w t0, t0, 13
shra_r.w t8, t8, 13
sw t0, 16(v0)
sw t8, 36(v0)
lw t5, 12(v0)
lw t6, 16(v0)
mult t7, s2
madd t1, s3
madd t5, s4
madd t6, s5
lw t5, 24(v0)
lw t7, 28(v0)
mflo t0, $ac0
lw t8, 32(v0)
lw t2, 36(v0)
mult $ac1, t5, s2
madd $ac1, t7, s3
madd $ac1, t8, s4
madd $ac1, t2, s5
addu t1, t3, t0
subu t6, t3, t0
shra_r.w t1, t1, 20
shra_r.w t6, t6, 20
mflo t4, $ac1
shll_s.w t1, t1, 24
shll_s.w t6, t6, 24
sra t1, t1, 24
sra t6, t6, 24
addiu t1, t1, 128
addiu t6, t6, 128
lw t0, 20(v0)
sb t1, 0(t9)
sb t6, 1(t9)
sll t0, t0, 15
lw t9, 4(a2)
addu t1, t0, t4
subu t6, t0, t4
addu t9, t9, a3
shra_r.w t1, t1, 20
shra_r.w t6, t6, 20
shll_s.w t1, t1, 24
shll_s.w t6, t6, 24
sra t1, t1, 24
sra t6, t6, 24
addiu t1, t1, 128
addiu t6, t6, 128
sb t1, 0(t9)
sb t6, 1(t9)
addiu sp, sp, 40
RESTORE_REGS_FROM_STACK 24, s0, s1, s2, s3, s4, s5
j ra
nop
END(jsimd_idct_2x2_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_idct_4x4_mips_dspr2)
/*
* a0 - compptr->dct_table
* a1 - coef_block
* a2 - output_buf
* a3 - output_col
* 16(sp) - workspace[DCTSIZE*4]; // buffers data between passes
*/
.set at
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
lw v1, 48(sp)
move t0, a1
move t1, v1
li t9, 4
li s0, 0x2e75f93e
li s1, 0x21f9ba79
li s2, 0xecc2efb0
li s3, 0x52031ccd
0:
lh s6, 32(t0) // inptr[DCTSIZE*2]
lh t6, 32(a0) // quantptr[DCTSIZE*2]
lh s7, 96(t0) // inptr[DCTSIZE*6]
lh t7, 96(a0) // quantptr[DCTSIZE*6]
mul t6, s6, t6 // z2 = (inptr[DCTSIZE*2] * quantptr[DCTSIZE*2])
lh s4, 0(t0) // inptr[DCTSIZE*0]
mul t7, s7, t7 // z3 = (inptr[DCTSIZE*6] * quantptr[DCTSIZE*6])
lh s5, 0(a0) // quantptr[0]
li s6, 15137
li s7, 6270
mul t2, s4, s5 // tmp0 = (inptr[0] * quantptr[0])
mul t6, s6, t6 // z2 = (inptr[DCTSIZE*2] * quantptr[DCTSIZE*2])
lh t5, 112(t0) // inptr[DCTSIZE*7]
mul t7, s7, t7 // z3 = (inptr[DCTSIZE*6] * quantptr[DCTSIZE*6])
lh s4, 112(a0) // quantptr[DCTSIZE*7]
lh v0, 80(t0) // inptr[DCTSIZE*5]
lh s5, 80(a0) // quantptr[DCTSIZE*5]
lh s6, 48(a0) // quantptr[DCTSIZE*3]
sll t2, t2, 14 // tmp0 <<= (CONST_BITS+1)
lh s7, 16(a0) // quantptr[DCTSIZE*1]
lh t8, 16(t0) // inptr[DCTSIZE*1]
subu t6, t6, t7 // tmp2 = MULTIPLY(z2, t5) - MULTIPLY(z3, t6)
lh t7, 48(t0) // inptr[DCTSIZE*3]
mul t5, s4, t5 // z1 = (inptr[DCTSIZE*7] * quantptr[DCTSIZE*7])
mul v0, s5, v0 // z2 = (inptr[DCTSIZE*5] * quantptr[DCTSIZE*5])
mul t7, s6, t7 // z3 = (inptr[DCTSIZE*3] * quantptr[DCTSIZE*3])
mul t8, s7, t8 // z4 = (inptr[DCTSIZE*1] * quantptr[DCTSIZE*1])
addu t3, t2, t6 // tmp10 = tmp0 + z2
subu t4, t2, t6 // tmp10 = tmp0 - z2
mult $ac0, zero, zero
mult $ac1, zero, zero
ins t5, v0, 16, 16
ins t7, t8, 16, 16
addiu t9, t9, -1
dpa.w.ph $ac0, t5, s0
dpa.w.ph $ac0, t7, s1
dpa.w.ph $ac1, t5, s2
dpa.w.ph $ac1, t7, s3
mflo s4, $ac0
mflo s5, $ac1
addiu a0, a0, 2
addiu t1, t1, 4
addiu t0, t0, 2
addu t6, t4, s4
subu t5, t4, s4
addu s6, t3, s5
subu s7, t3, s5
shra_r.w t6, t6, 12 // DESCALE(tmp12 + temp1, 12)
shra_r.w t5, t5, 12 // DESCALE(tmp12 - temp1, 12)
shra_r.w s6, s6, 12 // DESCALE(tmp10 + temp2, 12)
shra_r.w s7, s7, 12 // DESCALE(tmp10 - temp2, 12)
sw t6, 28(t1)
sw t5, 60(t1)
sw s6, -4(t1)
bgtz t9, 0b
sw s7, 92(t1)
// second loop three pass
li t9, 3
1:
lh s6, 34(t0) // inptr[DCTSIZE*2]
lh t6, 34(a0) // quantptr[DCTSIZE*2]
lh s7, 98(t0) // inptr[DCTSIZE*6]
lh t7, 98(a0) // quantptr[DCTSIZE*6]
mul t6, s6, t6 // z2 = (inptr[DCTSIZE*2] * quantptr[DCTSIZE*2])
lh s4, 2(t0) // inptr[DCTSIZE*0]
mul t7, s7, t7 // z3 = (inptr[DCTSIZE*6] * quantptr[DCTSIZE*6])
lh s5, 2(a0) // quantptr[DCTSIZE*0]
li s6, 15137
li s7, 6270
mul t2, s4, s5 // tmp0 = (inptr[0] * quantptr[0])
mul v0, s6, t6 // z2 = (inptr[DCTSIZE*2] * quantptr[DCTSIZE*2])
lh t5, 114(t0) // inptr[DCTSIZE*7]
mul t7, s7, t7 // z3 = (inptr[DCTSIZE*6] * quantptr[DCTSIZE*6])
lh s4, 114(a0) // quantptr[DCTSIZE*7]
lh s5, 82(a0) // quantptr[DCTSIZE*5]
lh t6, 82(t0) // inptr[DCTSIZE*5]
sll t2, t2, 14 // tmp0 <<= (CONST_BITS+1)
lh s6, 50(a0) // quantptr[DCTSIZE*3]
lh t8, 18(t0) // inptr[DCTSIZE*1]
subu v0, v0, t7 // tmp2 = MULTIPLY(z2, t5) - MULTIPLY(z3, t6)
lh t7, 50(t0) // inptr[DCTSIZE*3]
lh s7, 18(a0) // quantptr[DCTSIZE*1]
mul t5, s4, t5 // z1 = (inptr[DCTSIZE*7] * quantptr[DCTSIZE*7])
mul t6, s5, t6 // z2 = (inptr[DCTSIZE*5] * quantptr[DCTSIZE*5])
mul t7, s6, t7 // z3 = (inptr[DCTSIZE*3] * quantptr[DCTSIZE*3])
mul t8, s7, t8 // z4 = (inptr[DCTSIZE*1] * quantptr[DCTSIZE*1])
addu t3, t2, v0 // tmp10 = tmp0 + z2
subu t4, t2, v0 // tmp10 = tmp0 - z2
mult $ac0, zero, zero
mult $ac1, zero, zero
ins t5, t6, 16, 16
ins t7, t8, 16, 16
dpa.w.ph $ac0, t5, s0
dpa.w.ph $ac0, t7, s1
dpa.w.ph $ac1, t5, s2
dpa.w.ph $ac1, t7, s3
mflo t5, $ac0
mflo t6, $ac1
addiu t9, t9, -1
addiu t0, t0, 2
addiu a0, a0, 2
addiu t1, t1, 4
addu s5, t4, t5
subu s4, t4, t5
addu s6, t3, t6
subu s7, t3, t6
shra_r.w s5, s5, 12 // DESCALE(tmp12 + temp1, 12)
shra_r.w s4, s4, 12 // DESCALE(tmp12 - temp1, 12)
shra_r.w s6, s6, 12 // DESCALE(tmp10 + temp2, 12)
shra_r.w s7, s7, 12 // DESCALE(tmp10 - temp2, 12)
sw s5, 32(t1)
sw s4, 64(t1)
sw s6, 0(t1)
bgtz t9, 1b
sw s7, 96(t1)
move t1, v1
li s4, 15137
lw s6, 8(t1) // wsptr[2]
li s5, 6270
lw s7, 24(t1) // wsptr[6]
mul s4, s4, s6 // MULTIPLY((INT32) wsptr[2], FIX_1_847759065)
lw t2, 0(t1) // wsptr[0]
mul s5, s5, s7 // MULTIPLY((INT32) wsptr[6], - FIX_0_765366865)
lh t5, 28(t1) // wsptr[7]
lh t6, 20(t1) // wsptr[5]
lh t7, 12(t1) // wsptr[3]
lh t8, 4(t1) // wsptr[1]
ins t5, t6, 16, 16
ins t7, t8, 16, 16
mult $ac0, zero, zero
dpa.w.ph $ac0, t5, s0
dpa.w.ph $ac0, t7, s1
mult $ac1, zero, zero
dpa.w.ph $ac1, t5, s2
dpa.w.ph $ac1, t7, s3
sll t2, t2, 14 // tmp0 = ((INT32) wsptr[0]) << (CONST_BITS+1)
mflo s6, $ac0
// MULTIPLY(wsptr[2], FIX_1_847759065 + MULTIPLY(wsptr[6], -FIX_0_765366865)
subu s4, s4, s5
addu t3, t2, s4 // tmp10 = tmp0 + z2
mflo s7, $ac1
subu t4, t2, s4 // tmp10 = tmp0 - z2
addu t7, t4, s6
subu t8, t4, s6
addu t5, t3, s7
subu t6, t3, s7
shra_r.w t5, t5, 19 // DESCALE(tmp10 + temp2, 19)
shra_r.w t6, t6, 19 // DESCALE(tmp10 - temp2, 19)
shra_r.w t7, t7, 19 // DESCALE(tmp12 + temp1, 19)
shra_r.w t8, t8, 19 // DESCALE(tmp12 - temp1, 19)
sll s4, t9, 2
lw v0, 0(a2) // output_buf[ctr]
shll_s.w t5, t5, 24
shll_s.w t6, t6, 24
shll_s.w t7, t7, 24
shll_s.w t8, t8, 24
sra t5, t5, 24
sra t6, t6, 24
sra t7, t7, 24
sra t8, t8, 24
addu v0, v0, a3 // outptr = output_buf[ctr] + output_col
addiu t5, t5, 128
addiu t6, t6, 128
addiu t7, t7, 128
addiu t8, t8, 128
sb t5, 0(v0)
sb t7, 1(v0)
sb t8, 2(v0)
sb t6, 3(v0)
// 2
li s4, 15137
lw s6, 40(t1) // wsptr[2]
li s5, 6270
lw s7, 56(t1) // wsptr[6]
mul s4, s4, s6 // MULTIPLY((INT32) wsptr[2], FIX_1_847759065)
lw t2, 32(t1) // wsptr[0]
mul s5, s5, s7 // MULTIPLY((INT32) wsptr[6], - FIX_0_765366865)
lh t5, 60(t1) // wsptr[7]
lh t6, 52(t1) // wsptr[5]
lh t7, 44(t1) // wsptr[3]
lh t8, 36(t1) // wsptr[1]
ins t5, t6, 16, 16
ins t7, t8, 16, 16
mult $ac0, zero, zero
dpa.w.ph $ac0, t5, s0
dpa.w.ph $ac0, t7, s1
mult $ac1, zero, zero
dpa.w.ph $ac1, t5, s2
dpa.w.ph $ac1, t7, s3
sll t2, t2, 14 // tmp0 = ((INT32) wsptr[0]) << (CONST_BITS+1)
mflo s6, $ac0
// MULTIPLY(wsptr[2], FIX_1_847759065 + MULTIPLY(wsptr[6], -FIX_0_765366865)
subu s4, s4, s5
addu t3, t2, s4 // tmp10 = tmp0 + z2
mflo s7, $ac1
subu t4, t2, s4 // tmp10 = tmp0 - z2
addu t7, t4, s6
subu t8, t4, s6
addu t5, t3, s7
subu t6, t3, s7
shra_r.w t5, t5, 19 // DESCALE(tmp10 + temp2, CONST_BITS-PASS1_BITS+1)
shra_r.w t6, t6, 19 // DESCALE(tmp10 - temp2, CONST_BITS-PASS1_BITS+1)
shra_r.w t7, t7, 19 // DESCALE(tmp12 + temp1, CONST_BITS-PASS1_BITS+1)
shra_r.w t8, t8, 19 // DESCALE(tmp12 - temp1, CONST_BITS-PASS1_BITS+1)
sll s4, t9, 2
lw v0, 4(a2) // output_buf[ctr]
shll_s.w t5, t5, 24
shll_s.w t6, t6, 24
shll_s.w t7, t7, 24
shll_s.w t8, t8, 24
sra t5, t5, 24
sra t6, t6, 24
sra t7, t7, 24
sra t8, t8, 24
addu v0, v0, a3 // outptr = output_buf[ctr] + output_col
addiu t5, t5, 128
addiu t6, t6, 128
addiu t7, t7, 128
addiu t8, t8, 128
sb t5, 0(v0)
sb t7, 1(v0)
sb t8, 2(v0)
sb t6, 3(v0)
// 3
li s4, 15137
lw s6, 72(t1) // wsptr[2]
li s5, 6270
lw s7, 88(t1) // wsptr[6]
mul s4, s4, s6 // MULTIPLY((INT32) wsptr[2], FIX_1_847759065)
lw t2, 64(t1) // wsptr[0]
mul s5, s5, s7 // MULTIPLY((INT32) wsptr[6], - FIX_0_765366865)
lh t5, 92(t1) // wsptr[7]
lh t6, 84(t1) // wsptr[5]
lh t7, 76(t1) // wsptr[3]
lh t8, 68(t1) // wsptr[1]
ins t5, t6, 16, 16
ins t7, t8, 16, 16
mult $ac0, zero, zero
dpa.w.ph $ac0, t5, s0
dpa.w.ph $ac0, t7, s1
mult $ac1, zero, zero
dpa.w.ph $ac1, t5, s2
dpa.w.ph $ac1, t7, s3
sll t2, t2, 14 // tmp0 = ((INT32) wsptr[0]) << (CONST_BITS+1)
mflo s6, $ac0
// MULTIPLY(wsptr[2], FIX_1_847759065 + MULTIPLY(wsptr[6], -FIX_0_765366865)
subu s4, s4, s5
addu t3, t2, s4 // tmp10 = tmp0 + z2
mflo s7, $ac1
subu t4, t2, s4 // tmp10 = tmp0 - z2
addu t7, t4, s6
subu t8, t4, s6
addu t5, t3, s7
subu t6, t3, s7
shra_r.w t5, t5, 19 // DESCALE(tmp10 + temp2, 19)
shra_r.w t6, t6, 19 // DESCALE(tmp10 - temp2, 19)
shra_r.w t7, t7, 19 // DESCALE(tmp12 + temp1, 19)
shra_r.w t8, t8, 19 // DESCALE(tmp12 - temp1, 19)
sll s4, t9, 2
lw v0, 8(a2) // output_buf[ctr]
shll_s.w t5, t5, 24
shll_s.w t6, t6, 24
shll_s.w t7, t7, 24
shll_s.w t8, t8, 24
sra t5, t5, 24
sra t6, t6, 24
sra t7, t7, 24
sra t8, t8, 24
addu v0, v0, a3 // outptr = output_buf[ctr] + output_col
addiu t5, t5, 128
addiu t6, t6, 128
addiu t7, t7, 128
addiu t8, t8, 128
sb t5, 0(v0)
sb t7, 1(v0)
sb t8, 2(v0)
sb t6, 3(v0)
li s4, 15137
lw s6, 104(t1) // wsptr[2]
li s5, 6270
lw s7, 120(t1) // wsptr[6]
mul s4, s4, s6 // MULTIPLY((INT32) wsptr[2], FIX_1_847759065)
lw t2, 96(t1) // wsptr[0]
mul s5, s5, s7 // MULTIPLY((INT32) wsptr[6], -FIX_0_765366865)
lh t5, 124(t1) // wsptr[7]
lh t6, 116(t1) // wsptr[5]
lh t7, 108(t1) // wsptr[3]
lh t8, 100(t1) // wsptr[1]
ins t5, t6, 16, 16
ins t7, t8, 16, 16
mult $ac0, zero, zero
dpa.w.ph $ac0, t5, s0
dpa.w.ph $ac0, t7, s1
mult $ac1, zero, zero
dpa.w.ph $ac1, t5, s2
dpa.w.ph $ac1, t7, s3
sll t2, t2, 14 // tmp0 = ((INT32) wsptr[0]) << (CONST_BITS+1)
mflo s6, $ac0
// MULTIPLY(wsptr[2], FIX_1_847759065 + MULTIPLY(wsptr[6], -FIX_0_765366865)
subu s4, s4, s5
addu t3, t2, s4 // tmp10 = tmp0 + z2;
mflo s7, $ac1
subu t4, t2, s4 // tmp10 = tmp0 - z2;
addu t7, t4, s6
subu t8, t4, s6
addu t5, t3, s7
subu t6, t3, s7
shra_r.w t5, t5, 19 // DESCALE(tmp10 + temp2, 19)
shra_r.w t6, t6, 19 // DESCALE(tmp10 - temp2, 19)
shra_r.w t7, t7, 19 // DESCALE(tmp12 + temp1, 19)
shra_r.w t8, t8, 19 // DESCALE(tmp12 - temp1, 19)
sll s4, t9, 2
lw v0, 12(a2) // output_buf[ctr]
shll_s.w t5, t5, 24
shll_s.w t6, t6, 24
shll_s.w t7, t7, 24
shll_s.w t8, t8, 24
sra t5, t5, 24
sra t6, t6, 24
sra t7, t7, 24
sra t8, t8, 24
addu v0, v0, a3 // outptr = output_buf[ctr] + output_col
addiu t5, t5, 128
addiu t6, t6, 128
addiu t7, t7, 128
addiu t8, t8, 128
sb t5, 0(v0)
sb t7, 1(v0)
sb t8, 2(v0)
sb t6, 3(v0)
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_idct_4x4_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_idct_6x6_mips_dspr2)
/*
* a0 - compptr->dct_table
* a1 - coef_block
* a2 - output_buf
* a3 - output_col
*/
.set at
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
addiu sp, sp, -144
move v0, sp
addiu v1, v0, 24
addiu t9, zero, 5793
addiu s0, zero, 10033
addiu s1, zero, 2998
1:
lh s2, 0(a0) // q0 = quantptr[ 0]
lh s3, 32(a0) // q1 = quantptr[16]
lh s4, 64(a0) // q2 = quantptr[32]
lh t2, 64(a1) // tmp2 = inptr[32]
lh t1, 32(a1) // tmp1 = inptr[16]
lh t0, 0(a1) // tmp0 = inptr[ 0]
mul t2, t2, s4 // tmp2 = tmp2 * q2
mul t1, t1, s3 // tmp1 = tmp1 * q1
mul t0, t0, s2 // tmp0 = tmp0 * q0
lh t6, 16(a1) // z1 = inptr[ 8]
lh t8, 80(a1) // z3 = inptr[40]
lh t7, 48(a1) // z2 = inptr[24]
lh s2, 16(a0) // q0 = quantptr[ 8]
lh s4, 80(a0) // q2 = quantptr[40]
lh s3, 48(a0) // q1 = quantptr[24]
mul t2, t2, t9 // tmp2 = tmp2 * 5793
mul t1, t1, s0 // tmp1 = tmp1 * 10033
sll t0, t0, 13 // tmp0 = tmp0 << 13
mul t6, t6, s2 // z1 = z1 * q0
mul t8, t8, s4 // z3 = z3 * q2
mul t7, t7, s3 // z2 = z2 * q1
addu t3, t0, t2 // tmp10 = tmp0 + tmp2
sll t2, t2, 1 // tmp2 = tmp2 << 2
subu t4, t0, t2 // tmp11 = tmp0 - tmp2;
subu t5, t3, t1 // tmp12 = tmp10 - tmp1
addu t3, t3, t1 // tmp10 = tmp10 + tmp1
addu t1, t6, t8 // tmp1 = z1 + z3
mul t1, t1, s1 // tmp1 = tmp1 * 2998
shra_r.w t4, t4, 11 // tmp11 = (tmp11 + 1024) >> 11
subu t2, t6, t8 // tmp2 = z1 - z3
subu t2, t2, t7 // tmp2 = tmp2 - z2
sll t2, t2, 2 // tmp2 = tmp2 << 2
addu t0, t6, t7 // tmp0 = z1 + z2
sll t0, t0, 13 // tmp0 = tmp0 << 13
subu s2, t8, t7 // q0 = z3 - z2
sll s2, s2, 13 // q0 = q0 << 13
addu t0, t0, t1 // tmp0 = tmp0 + tmp1
addu t1, s2, t1 // tmp1 = q0 + tmp1
addu s2, t4, t2 // q0 = tmp11 + tmp2
subu s3, t4, t2 // q1 = tmp11 - tmp2
addu t6, t3, t0 // z1 = tmp10 + tmp0
subu t7, t3, t0 // z2 = tmp10 - tmp0
addu t4, t5, t1 // tmp11 = tmp12 + tmp1
subu t5, t5, t1 // tmp12 = tmp12 - tmp1
shra_r.w t6, t6, 11 // z1 = (z1 + 1024) >> 11
shra_r.w t7, t7, 11 // z2 = (z2 + 1024) >> 11
shra_r.w t4, t4, 11 // tmp11 = (tmp11 + 1024) >> 11
shra_r.w t5, t5, 11 // tmp12 = (tmp12 + 1024) >> 11
sw s2, 24(v0)
sw s3, 96(v0)
sw t6, 0(v0)
sw t7, 120(v0)
sw t4, 48(v0)
sw t5, 72(v0)
addiu v0, v0, 4
addiu a1, a1, 2
bne v0, v1, 1b
addiu a0, a0, 2
/* Pass 2: process 6 rows from work array, store into output array. */
move v0, sp
addiu v1, v0, 144
2:
lw t0, 0(v0)
lw t2, 16(v0)
lw s5, 0(a2)
addiu t0, t0, 16
sll t0, t0, 13
mul t3, t2, t9
lw t6, 4(v0)
lw t8, 20(v0)
lw t7, 12(v0)
addu s5, s5, a3
addu s6, t6, t8
mul s6, s6, s1
addu t1, t0, t3
subu t4, t0, t3
subu t4, t4, t3
lw t3, 8(v0)
mul t0, t3, s0
addu s7, t6, t7
sll s7, s7, 13
addu s7, s6, s7
subu t2, t8, t7
sll t2, t2, 13
addu t2, s6, t2
subu s6, t6, t7
subu s6, s6, t8
sll s6, s6, 13
addu t3, t1, t0
subu t5, t1, t0
addu t6, t3, s7
subu t3, t3, s7
addu t7, t4, s6
subu t4, t4, s6
addu t8, t5, t2
subu t5, t5, t2
shll_s.w t6, t6, 6
shll_s.w t3, t3, 6
shll_s.w t7, t7, 6
shll_s.w t4, t4, 6
shll_s.w t8, t8, 6
shll_s.w t5, t5, 6
sra t6, t6, 24
addiu t6, t6, 128
sra t3, t3, 24
addiu t3, t3, 128
sb t6, 0(s5)
sra t7, t7, 24
addiu t7, t7, 128
sb t3, 5(s5)
sra t4, t4, 24
addiu t4, t4, 128
sb t7, 1(s5)
sra t8, t8, 24
addiu t8, t8, 128
sb t4, 4(s5)
addiu v0, v0, 24
sra t5, t5, 24
addiu t5, t5, 128
sb t8, 2(s5)
addiu a2, a2, 4
bne v0, v1, 2b
sb t5, 3(s5)
addiu sp, sp, 144
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_idct_6x6_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_idct_12x12_pass1_mips_dspr2)
/*
* a0 - compptr->dct_table
* a1 - coef_block
* a2 - workspace
*/
SAVE_REGS_ON_STACK 16, s0, s1, s2, s3
li a3, 8
1:
// odd part
lh t0, 48(a1)
lh t1, 48(a0)
lh t2, 16(a1)
lh t3, 16(a0)
lh t4, 80(a1)
lh t5, 80(a0)
lh t6, 112(a1)
lh t7, 112(a0)
mul t0, t0, t1 // z2
mul t1, t2, t3 // z1
mul t2, t4, t5 // z3
mul t3, t6, t7 // z4
li t4, 10703 // FIX(1.306562965)
li t5, 4433 // FIX_0_541196100
li t6, 7053 // FIX(0.860918669)
mul t4, t0,t4 // tmp11
mul t5, t0,t5 // -tmp14
addu t7, t1,t2 // tmp10
addu t8, t7,t3 // tmp10 + z4
mul t6, t6, t8 // tmp15
li t8, 2139 // FIX(0.261052384)
mul t8, t7, t8 // MULTIPLY(tmp10, FIX(0.261052384))
li t7, 2295 // FIX(0.280143716)
mul t7, t1, t7 // MULTIPLY(z1, FIX(0.280143716))
addu t9, t2, t3 // z3 + z4
li s0, 8565 // FIX(1.045510580)
mul t9, t9, s0 // -tmp13
li s0, 12112 // FIX(1.478575242)
mul s0, t2, s0 // MULTIPLY(z3, FIX(1.478575242)
li s1, 12998 // FIX(1.586706681)
mul s1, t3, s1 // MULTIPLY(z4, FIX(1.586706681))
li s2, 5540 // FIX(0.676326758)
mul s2, t1, s2 // MULTIPLY(z1, FIX(0.676326758))
li s3, 16244 // FIX(1.982889723)
mul s3, t3, s3 // MULTIPLY(z4, FIX(1.982889723))
subu t1, t1, t3 // z1-=z4
subu t0, t0, t2 // z2-=z3
addu t2, t0, t1 // z1+z2
li t3, 4433 // FIX_0_541196100
mul t2, t2, t3 // z3
li t3, 6270 // FIX_0_765366865
mul t1, t1, t3 // MULTIPLY(z1, FIX_0_765366865)
li t3, 15137 // FIX_0_765366865
mul t0, t0, t3 // MULTIPLY(z2, FIX_1_847759065)
addu t8, t6, t8 // tmp12
addu t3, t8, t4 // tmp12 + tmp11
addu t3, t3, t7 // tmp10
subu t8, t8, t9 // tmp12 + tmp13
addu s0, t5, s0
subu t8, t8, s0 // tmp12
subu t9, t6, t9
subu s1, s1, t4
addu t9, t9, s1 // tmp13
subu t6, t6, t5
subu t6, t6, s2
subu t6, t6, s3 // tmp15
// even part start
lh t4, 64(a1)
lh t5, 64(a0)
lh t7, 32(a1)
lh s0, 32(a0)
lh s1, 0(a1)
lh s2, 0(a0)
lh s3, 96(a1)
lh v0, 96(a0)
mul t4, t4, t5 // DEQUANTIZE(inptr[DCTSIZE*4],quantptr[DCTSIZE*4])
mul t5, t7, s0 // DEQUANTIZE(inptr[DCTSIZE*2],quantptr[DCTSIZE*2])
mul t7, s1, s2 // DEQUANTIZE(inptr[DCTSIZE*0],quantptr[DCTSIZE*0])
mul s0, s3, v0 // DEQUANTIZE(inptr[DCTSIZE*6],quantptr[DCTSIZE*6])
// odd part end
addu t1, t2, t1 // tmp11
subu t0, t2, t0 // tmp14
// update counter and pointers
addiu a3, a3, -1
addiu a0, a0, 2
addiu a1, a1, 2
// even part rest
li s1, 10033
li s2, 11190
mul t4, t4, s1 // z4
mul s1, t5, s2 // z4
sll t5, t5, 13 // z1
sll t7, t7, 13
addiu t7, t7, 1024 // z3
sll s0, s0, 13 // z2
addu s2, t7, t4 // tmp10
subu t4, t7, t4 // tmp11
subu s3, t5, s0 // tmp12
addu t2, t7, s3 // tmp21
subu s3, t7, s3 // tmp24
addu t7, s1, s0 // tmp12
addu v0, s2, t7 // tmp20
subu s2, s2, t7 // tmp25
subu s1, s1, t5 // z4 - z1
subu s1, s1, s0 // tmp12
addu s0, t4, s1 // tmp22
subu t4, t4, s1 // tmp23
// final output stage
addu t5, v0, t3
subu v0, v0, t3
addu t3, t2, t1
subu t2, t2, t1
addu t1, s0, t8
subu s0, s0, t8
addu t8, t4, t9
subu t4, t4, t9
addu t9, s3, t0
subu s3, s3, t0
addu t0, s2, t6
subu s2, s2, t6
sra t5, t5, 11
sra t3, t3, 11
sra t1, t1, 11
sra t8, t8, 11
sra t9, t9, 11
sra t0, t0, 11
sra s2, s2, 11
sra s3, s3, 11
sra t4, t4, 11
sra s0, s0, 11
sra t2, t2, 11
sra v0, v0, 11
sw t5, 0(a2)
sw t3, 32(a2)
sw t1, 64(a2)
sw t8, 96(a2)
sw t9, 128(a2)
sw t0, 160(a2)
sw s2, 192(a2)
sw s3, 224(a2)
sw t4, 256(a2)
sw s0, 288(a2)
sw t2, 320(a2)
sw v0, 352(a2)
bgtz a3, 1b
addiu a2, a2, 4
RESTORE_REGS_FROM_STACK 16, s0, s1, s2, s3
j ra
nop
END(jsimd_idct_12x12_pass1_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_idct_12x12_pass2_mips_dspr2)
/*
* a0 - workspace
* a1 - output
*/
SAVE_REGS_ON_STACK 16, s0, s1, s2, s3
li a3, 12
1:
// Odd part
lw t0, 12(a0)
lw t1, 4(a0)
lw t2, 20(a0)
lw t3, 28(a0)
li t4, 10703 // FIX(1.306562965)
li t5, 4433 // FIX_0_541196100
mul t4, t0, t4 // tmp11
mul t5, t0, t5 // -tmp14
addu t6, t1, t2 // tmp10
li t7, 2139 // FIX(0.261052384)
mul t7, t6, t7 // MULTIPLY(tmp10, FIX(0.261052384))
addu t6, t6, t3 // tmp10 + z4
li t8, 7053 // FIX(0.860918669)
mul t6, t6, t8 // tmp15
li t8, 2295 // FIX(0.280143716)
mul t8, t1, t8 // MULTIPLY(z1, FIX(0.280143716))
addu t9, t2, t3 // z3 + z4
li s0, 8565 // FIX(1.045510580)
mul t9, t9, s0 // -tmp13
li s0, 12112 // FIX(1.478575242)
mul s0, t2, s0 // MULTIPLY(z3, FIX(1.478575242))
li s1, 12998 // FIX(1.586706681)
mul s1, t3, s1 // MULTIPLY(z4, FIX(1.586706681))
li s2, 5540 // FIX(0.676326758)
mul s2, t1, s2 // MULTIPLY(z1, FIX(0.676326758))
li s3, 16244 // FIX(1.982889723)
mul s3, t3, s3 // MULTIPLY(z4, FIX(1.982889723))
subu t1, t1, t3 // z1 -= z4
subu t0, t0, t2 // z2 -= z3
addu t2, t1, t0 // z1 + z2
li t3, 4433 // FIX_0_541196100
mul t2, t2, t3 // z3
li t3, 6270 // FIX_0_765366865
mul t1, t1, t3 // MULTIPLY(z1, FIX_0_765366865)
li t3, 15137 // FIX_1_847759065
mul t0, t0, t3 // MULTIPLY(z2, FIX_1_847759065)
addu t3, t6, t7 // tmp12
addu t7, t3, t4
addu t7, t7, t8 // tmp10
subu t3, t3, t9
subu t3, t3, t5
subu t3, t3, s0 // tmp12
subu t9, t6, t9
subu t9, t9, t4
addu t9, t9, s1 // tmp13
subu t6, t6, t5
subu t6, t6, s2
subu t6, t6, s3 // tmp15
addu t1, t2, t1 // tmp11
subu t0, t2, t0 // tmp14
// even part
lw t2, 16(a0) // z4
lw t4, 8(a0) // z1
lw t5, 0(a0) // z3
lw t8, 24(a0) // z2
li s0, 10033 // FIX(1.224744871)
li s1, 11190 // FIX(1.366025404)
mul t2, t2, s0 // z4
mul s0, t4, s1 // z4
addiu t5, t5, 0x10
sll t5, t5, 13 // z3
sll t4, t4, 13 // z1
sll t8, t8, 13 // z2
subu s1, t4, t8 // tmp12
addu s2, t5, t2 // tmp10
subu t2, t5, t2 // tmp11
addu s3, t5, s1 // tmp21
subu s1, t5, s1 // tmp24
addu t5, s0, t8 // tmp12
addu v0, s2, t5 // tmp20
subu t5, s2, t5 // tmp25
subu t4, s0, t4
subu t4, t4, t8 // tmp12
addu t8, t2, t4 // tmp22
subu t2, t2, t4 // tmp23
// increment counter and pointers
addiu a3, a3, -1
addiu a0, a0, 32
// Final stage
addu t4, v0, t7
subu v0, v0, t7
addu t7, s3, t1
subu s3, s3, t1
addu t1, t8, t3
subu t8, t8, t3
addu t3, t2, t9
subu t2, t2, t9
addu t9, s1, t0
subu s1, s1, t0
addu t0, t5, t6
subu t5, t5, t6
sll t4, t4, 4
sll t7, t7, 4
sll t1, t1, 4
sll t3, t3, 4
sll t9, t9, 4
sll t0, t0, 4
sll t5, t5, 4
sll s1, s1, 4
sll t2, t2, 4
sll t8, t8, 4
sll s3, s3, 4
sll v0, v0, 4
shll_s.w t4, t4, 2
shll_s.w t7, t7, 2
shll_s.w t1, t1, 2
shll_s.w t3, t3, 2
shll_s.w t9, t9, 2
shll_s.w t0, t0, 2
shll_s.w t5, t5, 2
shll_s.w s1, s1, 2
shll_s.w t2, t2, 2
shll_s.w t8, t8, 2
shll_s.w s3, s3, 2
shll_s.w v0, v0, 2
srl t4, t4, 24
srl t7, t7, 24
srl t1, t1, 24
srl t3, t3, 24
srl t9, t9, 24
srl t0, t0, 24
srl t5, t5, 24
srl s1, s1, 24
srl t2, t2, 24
srl t8, t8, 24
srl s3, s3, 24
srl v0, v0, 24
lw t6, 0(a1)
addiu t4, t4, 0x80
addiu t7, t7, 0x80
addiu t1, t1, 0x80
addiu t3, t3, 0x80
addiu t9, t9, 0x80
addiu t0, t0, 0x80
addiu t5, t5, 0x80
addiu s1, s1, 0x80
addiu t2, t2, 0x80
addiu t8, t8, 0x80
addiu s3, s3, 0x80
addiu v0, v0, 0x80
sb t4, 0(t6)
sb t7, 1(t6)
sb t1, 2(t6)
sb t3, 3(t6)
sb t9, 4(t6)
sb t0, 5(t6)
sb t5, 6(t6)
sb s1, 7(t6)
sb t2, 8(t6)
sb t8, 9(t6)
sb s3, 10(t6)
sb v0, 11(t6)
bgtz a3, 1b
addiu a1, a1, 4
RESTORE_REGS_FROM_STACK 16, s0, s1, s2, s3
jr ra
nop
END(jsimd_idct_12x12_pass2_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_convsamp_mips_dspr2)
/*
* a0 - sample_data
* a1 - start_col
* a2 - workspace
*/
lw t0, 0(a0)
li t7, 0xff80ff80
addu t0, t0, a1
ulw t1, 0(t0)
ulw t2, 4(t0)
preceu.ph.qbr t3, t1
preceu.ph.qbl t4, t1
lw t0, 4(a0)
preceu.ph.qbr t5, t2
preceu.ph.qbl t6, t2
addu t0, t0, a1
addu.ph t3, t3, t7
addu.ph t4, t4, t7
ulw t1, 0(t0)
ulw t2, 4(t0)
addu.ph t5, t5, t7
addu.ph t6, t6, t7
usw t3, 0(a2)
usw t4, 4(a2)
preceu.ph.qbr t3, t1
preceu.ph.qbl t4, t1
usw t5, 8(a2)
usw t6, 12(a2)
lw t0, 8(a0)
preceu.ph.qbr t5, t2
preceu.ph.qbl t6, t2
addu t0, t0, a1
addu.ph t3, t3, t7
addu.ph t4, t4, t7
ulw t1, 0(t0)
ulw t2, 4(t0)
addu.ph t5, t5, t7
addu.ph t6, t6, t7
usw t3, 16(a2)
usw t4, 20(a2)
preceu.ph.qbr t3, t1
preceu.ph.qbl t4, t1
usw t5, 24(a2)
usw t6, 28(a2)
lw t0, 12(a0)
preceu.ph.qbr t5, t2
preceu.ph.qbl t6, t2
addu t0, t0, a1
addu.ph t3, t3, t7
addu.ph t4, t4, t7
ulw t1, 0(t0)
ulw t2, 4(t0)
addu.ph t5, t5, t7
addu.ph t6, t6, t7
usw t3, 32(a2)
usw t4, 36(a2)
preceu.ph.qbr t3, t1
preceu.ph.qbl t4, t1
usw t5, 40(a2)
usw t6, 44(a2)
lw t0, 16(a0)
preceu.ph.qbr t5, t2
preceu.ph.qbl t6, t2
addu t0, t0, a1
addu.ph t3, t3, t7
addu.ph t4, t4, t7
ulw t1, 0(t0)
ulw t2, 4(t0)
addu.ph t5, t5, t7
addu.ph t6, t6, t7
usw t3, 48(a2)
usw t4, 52(a2)
preceu.ph.qbr t3, t1
preceu.ph.qbl t4, t1
usw t5, 56(a2)
usw t6, 60(a2)
lw t0, 20(a0)
preceu.ph.qbr t5, t2
preceu.ph.qbl t6, t2
addu t0, t0, a1
addu.ph t3, t3, t7
addu.ph t4, t4, t7
ulw t1, 0(t0)
ulw t2, 4(t0)
addu.ph t5, t5, t7
addu.ph t6, t6, t7
usw t3, 64(a2)
usw t4, 68(a2)
preceu.ph.qbr t3, t1
preceu.ph.qbl t4, t1
usw t5, 72(a2)
usw t6, 76(a2)
lw t0, 24(a0)
preceu.ph.qbr t5, t2
preceu.ph.qbl t6, t2
addu t0, t0, a1
addu.ph t3, t3, t7
addu.ph t4, t4, t7
ulw t1, 0(t0)
ulw t2, 4(t0)
addu.ph t5, t5, t7
addu.ph t6, t6, t7
usw t3, 80(a2)
usw t4, 84(a2)
preceu.ph.qbr t3, t1
preceu.ph.qbl t4, t1
usw t5, 88(a2)
usw t6, 92(a2)
lw t0, 28(a0)
preceu.ph.qbr t5, t2
preceu.ph.qbl t6, t2
addu t0, t0, a1
addu.ph t3, t3, t7
addu.ph t4, t4, t7
ulw t1, 0(t0)
ulw t2, 4(t0)
addu.ph t5, t5, t7
addu.ph t6, t6, t7
usw t3, 96(a2)
usw t4, 100(a2)
preceu.ph.qbr t3, t1
preceu.ph.qbl t4, t1
usw t5, 104(a2)
usw t6, 108(a2)
preceu.ph.qbr t5, t2
preceu.ph.qbl t6, t2
addu.ph t3, t3, t7
addu.ph t4, t4, t7
addu.ph t5, t5, t7
addu.ph t6, t6, t7
usw t3, 112(a2)
usw t4, 116(a2)
usw t5, 120(a2)
usw t6, 124(a2)
j ra
nop
END(jsimd_convsamp_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_convsamp_float_mips_dspr2)
/*
* a0 - sample_data
* a1 - start_col
* a2 - workspace
*/
.set at
lw t0, 0(a0)
addu t0, t0, a1
lbu t1, 0(t0)
lbu t2, 1(t0)
lbu t3, 2(t0)
lbu t4, 3(t0)
lbu t5, 4(t0)
lbu t6, 5(t0)
lbu t7, 6(t0)
lbu t8, 7(t0)
addiu t1, t1, -128
addiu t2, t2, -128
addiu t3, t3, -128
addiu t4, t4, -128
addiu t5, t5, -128
addiu t6, t6, -128
addiu t7, t7, -128
addiu t8, t8, -128
mtc1 t1, f1
mtc1 t2, f2
mtc1 t3, f3
mtc1 t4, f4
mtc1 t5, f5
mtc1 t6, f6
mtc1 t7, f7
mtc1 t8, f8
cvt.s.w f1, f1
cvt.s.w f2, f2
cvt.s.w f3, f3
cvt.s.w f4, f4
cvt.s.w f5, f5
cvt.s.w f6, f6
cvt.s.w f7, f7
cvt.s.w f8, f8
lw t0, 4(a0)
swc1 f1, 0(a2)
swc1 f2, 4(a2)
swc1 f3, 8(a2)
addu t0, t0, a1
swc1 f4, 12(a2)
swc1 f5, 16(a2)
swc1 f6, 20(a2)
swc1 f7, 24(a2)
swc1 f8, 28(a2)
//elemr 1
lbu t1, 0(t0)
lbu t2, 1(t0)
lbu t3, 2(t0)
lbu t4, 3(t0)
lbu t5, 4(t0)
lbu t6, 5(t0)
lbu t7, 6(t0)
lbu t8, 7(t0)
addiu t1, t1, -128
addiu t2, t2, -128
addiu t3, t3, -128
addiu t4, t4, -128
addiu t5, t5, -128
addiu t6, t6, -128
addiu t7, t7, -128
addiu t8, t8, -128
mtc1 t1, f1
mtc1 t2, f2
mtc1 t3, f3
mtc1 t4, f4
mtc1 t5, f5
mtc1 t6, f6
mtc1 t7, f7
mtc1 t8, f8
cvt.s.w f1, f1
cvt.s.w f2, f2
cvt.s.w f3, f3
cvt.s.w f4, f4
cvt.s.w f5, f5
cvt.s.w f6, f6
cvt.s.w f7, f7
cvt.s.w f8, f8
lw t0, 8(a0)
swc1 f1, 32(a2)
swc1 f2, 36(a2)
swc1 f3, 40(a2)
addu t0, t0, a1
swc1 f4, 44(a2)
swc1 f5, 48(a2)
swc1 f6, 52(a2)
swc1 f7, 56(a2)
swc1 f8, 60(a2)
//elemr 2
lbu t1, 0(t0)
lbu t2, 1(t0)
lbu t3, 2(t0)
lbu t4, 3(t0)
lbu t5, 4(t0)
lbu t6, 5(t0)
lbu t7, 6(t0)
lbu t8, 7(t0)
addiu t1, t1, -128
addiu t2, t2, -128
addiu t3, t3, -128
addiu t4, t4, -128
addiu t5, t5, -128
addiu t6, t6, -128
addiu t7, t7, -128
addiu t8, t8, -128
mtc1 t1, f1
mtc1 t2, f2
mtc1 t3, f3
mtc1 t4, f4
mtc1 t5, f5
mtc1 t6, f6
mtc1 t7, f7
mtc1 t8, f8
cvt.s.w f1, f1
cvt.s.w f2, f2
cvt.s.w f3, f3
cvt.s.w f4, f4
cvt.s.w f5, f5
cvt.s.w f6, f6
cvt.s.w f7, f7
cvt.s.w f8, f8
lw t0, 12(a0)
swc1 f1, 64(a2)
swc1 f2, 68(a2)
swc1 f3, 72(a2)
addu t0, t0, a1
swc1 f4, 76(a2)
swc1 f5, 80(a2)
swc1 f6, 84(a2)
swc1 f7, 88(a2)
swc1 f8, 92(a2)
//elemr 3
lbu t1, 0(t0)
lbu t2, 1(t0)
lbu t3, 2(t0)
lbu t4, 3(t0)
lbu t5, 4(t0)
lbu t6, 5(t0)
lbu t7, 6(t0)
lbu t8, 7(t0)
addiu t1, t1, -128
addiu t2, t2, -128
addiu t3, t3, -128
addiu t4, t4, -128
addiu t5, t5, -128
addiu t6, t6, -128
addiu t7, t7, -128
addiu t8, t8, -128
mtc1 t1, f1
mtc1 t2, f2
mtc1 t3, f3
mtc1 t4, f4
mtc1 t5, f5
mtc1 t6, f6
mtc1 t7, f7
mtc1 t8, f8
cvt.s.w f1, f1
cvt.s.w f2, f2
cvt.s.w f3, f3
cvt.s.w f4, f4
cvt.s.w f5, f5
cvt.s.w f6, f6
cvt.s.w f7, f7
cvt.s.w f8, f8
lw t0, 16(a0)
swc1 f1, 96(a2)
swc1 f2, 100(a2)
swc1 f3, 104(a2)
addu t0, t0, a1
swc1 f4, 108(a2)
swc1 f5, 112(a2)
swc1 f6, 116(a2)
swc1 f7, 120(a2)
swc1 f8, 124(a2)
//elemr 4
lbu t1, 0(t0)
lbu t2, 1(t0)
lbu t3, 2(t0)
lbu t4, 3(t0)
lbu t5, 4(t0)
lbu t6, 5(t0)
lbu t7, 6(t0)
lbu t8, 7(t0)
addiu t1, t1, -128
addiu t2, t2, -128
addiu t3, t3, -128
addiu t4, t4, -128
addiu t5, t5, -128
addiu t6, t6, -128
addiu t7, t7, -128
addiu t8, t8, -128
mtc1 t1, f1
mtc1 t2, f2
mtc1 t3, f3
mtc1 t4, f4
mtc1 t5, f5
mtc1 t6, f6
mtc1 t7, f7
mtc1 t8, f8
cvt.s.w f1, f1
cvt.s.w f2, f2
cvt.s.w f3, f3
cvt.s.w f4, f4
cvt.s.w f5, f5
cvt.s.w f6, f6
cvt.s.w f7, f7
cvt.s.w f8, f8
lw t0, 20(a0)
swc1 f1, 128(a2)
swc1 f2, 132(a2)
swc1 f3, 136(a2)
addu t0, t0, a1
swc1 f4, 140(a2)
swc1 f5, 144(a2)
swc1 f6, 148(a2)
swc1 f7, 152(a2)
swc1 f8, 156(a2)
//elemr 5
lbu t1, 0(t0)
lbu t2, 1(t0)
lbu t3, 2(t0)
lbu t4, 3(t0)
lbu t5, 4(t0)
lbu t6, 5(t0)
lbu t7, 6(t0)
lbu t8, 7(t0)
addiu t1, t1, -128
addiu t2, t2, -128
addiu t3, t3, -128
addiu t4, t4, -128
addiu t5, t5, -128
addiu t6, t6, -128
addiu t7, t7, -128
addiu t8, t8, -128
mtc1 t1, f1
mtc1 t2, f2
mtc1 t3, f3
mtc1 t4, f4
mtc1 t5, f5
mtc1 t6, f6
mtc1 t7, f7
mtc1 t8, f8
cvt.s.w f1, f1
cvt.s.w f2, f2
cvt.s.w f3, f3
cvt.s.w f4, f4
cvt.s.w f5, f5
cvt.s.w f6, f6
cvt.s.w f7, f7
cvt.s.w f8, f8
lw t0, 24(a0)
swc1 f1, 160(a2)
swc1 f2, 164(a2)
swc1 f3, 168(a2)
addu t0, t0, a1
swc1 f4, 172(a2)
swc1 f5, 176(a2)
swc1 f6, 180(a2)
swc1 f7, 184(a2)
swc1 f8, 188(a2)
//elemr 6
lbu t1, 0(t0)
lbu t2, 1(t0)
lbu t3, 2(t0)
lbu t4, 3(t0)
lbu t5, 4(t0)
lbu t6, 5(t0)
lbu t7, 6(t0)
lbu t8, 7(t0)
addiu t1, t1, -128
addiu t2, t2, -128
addiu t3, t3, -128
addiu t4, t4, -128
addiu t5, t5, -128
addiu t6, t6, -128
addiu t7, t7, -128
addiu t8, t8, -128
mtc1 t1, f1
mtc1 t2, f2
mtc1 t3, f3
mtc1 t4, f4
mtc1 t5, f5
mtc1 t6, f6
mtc1 t7, f7
mtc1 t8, f8
cvt.s.w f1, f1
cvt.s.w f2, f2
cvt.s.w f3, f3
cvt.s.w f4, f4
cvt.s.w f5, f5
cvt.s.w f6, f6
cvt.s.w f7, f7
cvt.s.w f8, f8
lw t0, 28(a0)
swc1 f1, 192(a2)
swc1 f2, 196(a2)
swc1 f3, 200(a2)
addu t0, t0, a1
swc1 f4, 204(a2)
swc1 f5, 208(a2)
swc1 f6, 212(a2)
swc1 f7, 216(a2)
swc1 f8, 220(a2)
//elemr 7
lbu t1, 0(t0)
lbu t2, 1(t0)
lbu t3, 2(t0)
lbu t4, 3(t0)
lbu t5, 4(t0)
lbu t6, 5(t0)
lbu t7, 6(t0)
lbu t8, 7(t0)
addiu t1, t1, -128
addiu t2, t2, -128
addiu t3, t3, -128
addiu t4, t4, -128
addiu t5, t5, -128
addiu t6, t6, -128
addiu t7, t7, -128
addiu t8, t8, -128
mtc1 t1, f1
mtc1 t2, f2
mtc1 t3, f3
mtc1 t4, f4
mtc1 t5, f5
mtc1 t6, f6
mtc1 t7, f7
mtc1 t8, f8
cvt.s.w f1, f1
cvt.s.w f2, f2
cvt.s.w f3, f3
cvt.s.w f4, f4
cvt.s.w f5, f5
cvt.s.w f6, f6
cvt.s.w f7, f7
cvt.s.w f8, f8
swc1 f1, 224(a2)
swc1 f2, 228(a2)
swc1 f3, 232(a2)
swc1 f4, 236(a2)
swc1 f5, 240(a2)
swc1 f6, 244(a2)
swc1 f7, 248(a2)
swc1 f8, 252(a2)
j ra
nop
END(jsimd_convsamp_float_mips_dspr2)
/*****************************************************************************/
|
lvonasek/3DLiveScanner | 79,762 | third_party/libjpeg-turbo/src/simd/jsimd_arm64_neon.S | /*
* ARMv8 NEON optimizations for libjpeg-turbo
*
* Copyright (C) 2009-2011 Nokia Corporation and/or its subsidiary(-ies).
* All rights reserved.
* Author: Siarhei Siamashka <siarhei.siamashka@nokia.com>
* Copyright (C) 2013-2014, Linaro Limited
* Author: Ragesh Radhakrishnan <ragesh.r@linaro.org>
* Copyright (C) 2014, D. R. Commander. All rights reserved.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*/
#if defined(__linux__) && defined(__ELF__)
.section .note.GNU-stack,"",%progbits /* mark stack as non-executable */
#endif
.text
.arch armv8-a+fp+simd
#define RESPECT_STRICT_ALIGNMENT 1
/*****************************************************************************/
/* Supplementary macro for setting function attributes */
.macro asm_function fname
#ifdef __APPLE__
.globl _\fname
_\fname:
#else
.global \fname
#ifdef __ELF__
.hidden \fname
.type \fname, %function
#endif
\fname:
#endif
.endm
/* Transpose elements of single 128 bit registers */
.macro transpose_single x0,x1,xi,xilen,literal
ins \xi\xilen[0], \x0\xilen[0]
ins \x1\xilen[0], \x0\xilen[1]
trn1 \x0\literal, \x0\literal, \x1\literal
trn2 \x1\literal, \xi\literal, \x1\literal
.endm
/* Transpose elements of 2 differnet registers */
.macro transpose x0,x1,xi,xilen,literal
mov \xi\xilen, \x0\xilen
trn1 \x0\literal, \x0\literal, \x1\literal
trn2 \x1\literal, \xi\literal, \x1\literal
.endm
/* Transpose a block of 4x4 coefficients in four 64-bit registers */
.macro transpose_4x4_32 x0,x0len x1,x1len x2,x2len x3,x3len,xi,xilen
mov \xi\xilen, \x0\xilen
trn1 \x0\x0len, \x0\x0len, \x2\x2len
trn2 \x2\x2len, \xi\x0len, \x2\x2len
mov \xi\xilen, \x1\xilen
trn1 \x1\x1len, \x1\x1len, \x3\x3len
trn2 \x3\x3len, \xi\x1len, \x3\x3len
.endm
.macro transpose_4x4_16 x0,x0len x1,x1len, x2,x2len, x3,x3len,xi,xilen
mov \xi\xilen, \x0\xilen
trn1 \x0\x0len, \x0\x0len, \x1\x1len
trn2 \x1\x2len, \xi\x0len, \x1\x2len
mov \xi\xilen, \x2\xilen
trn1 \x2\x2len, \x2\x2len, \x3\x3len
trn2 \x3\x2len, \xi\x1len, \x3\x3len
.endm
.macro transpose_4x4 x0, x1, x2, x3,x5
transpose_4x4_16 \x0,.4h, \x1,.4h, \x2,.4h,\x3,.4h,\x5,.16b
transpose_4x4_32 \x0,.2s, \x1,.2s, \x2,.2s,\x3,.2s,\x5,.16b
.endm
#define CENTERJSAMPLE 128
/*****************************************************************************/
/*
* Perform dequantization and inverse DCT on one block of coefficients.
*
* GLOBAL(void)
* jsimd_idct_islow_neon (void * dct_table, JCOEFPTR coef_block,
* JSAMPARRAY output_buf, JDIMENSION output_col)
*/
#define FIX_0_298631336 (2446)
#define FIX_0_390180644 (3196)
#define FIX_0_541196100 (4433)
#define FIX_0_765366865 (6270)
#define FIX_0_899976223 (7373)
#define FIX_1_175875602 (9633)
#define FIX_1_501321110 (12299)
#define FIX_1_847759065 (15137)
#define FIX_1_961570560 (16069)
#define FIX_2_053119869 (16819)
#define FIX_2_562915447 (20995)
#define FIX_3_072711026 (25172)
#define FIX_1_175875602_MINUS_1_961570560 (FIX_1_175875602 - FIX_1_961570560)
#define FIX_1_175875602_MINUS_0_390180644 (FIX_1_175875602 - FIX_0_390180644)
#define FIX_0_541196100_MINUS_1_847759065 (FIX_0_541196100 - FIX_1_847759065)
#define FIX_3_072711026_MINUS_2_562915447 (FIX_3_072711026 - FIX_2_562915447)
#define FIX_0_298631336_MINUS_0_899976223 (FIX_0_298631336 - FIX_0_899976223)
#define FIX_1_501321110_MINUS_0_899976223 (FIX_1_501321110 - FIX_0_899976223)
#define FIX_2_053119869_MINUS_2_562915447 (FIX_2_053119869 - FIX_2_562915447)
#define FIX_0_541196100_PLUS_0_765366865 (FIX_0_541196100 + FIX_0_765366865)
/*
* Reference SIMD-friendly 1-D ISLOW iDCT C implementation.
* Uses some ideas from the comments in 'simd/jiss2int-64.asm'
*/
#define REF_1D_IDCT(xrow0, xrow1, xrow2, xrow3, xrow4, xrow5, xrow6, xrow7) \
{ \
DCTELEM row0, row1, row2, row3, row4, row5, row6, row7; \
INT32 q1, q2, q3, q4, q5, q6, q7; \
INT32 tmp11_plus_tmp2, tmp11_minus_tmp2; \
\
/* 1-D iDCT input data */ \
row0 = xrow0; \
row1 = xrow1; \
row2 = xrow2; \
row3 = xrow3; \
row4 = xrow4; \
row5 = xrow5; \
row6 = xrow6; \
row7 = xrow7; \
\
q5 = row7 + row3; \
q4 = row5 + row1; \
q6 = MULTIPLY(q5, FIX_1_175875602_MINUS_1_961570560) + \
MULTIPLY(q4, FIX_1_175875602); \
q7 = MULTIPLY(q5, FIX_1_175875602) + \
MULTIPLY(q4, FIX_1_175875602_MINUS_0_390180644); \
q2 = MULTIPLY(row2, FIX_0_541196100) + \
MULTIPLY(row6, FIX_0_541196100_MINUS_1_847759065); \
q4 = q6; \
q3 = ((INT32) row0 - (INT32) row4) << 13; \
q6 += MULTIPLY(row5, -FIX_2_562915447) + \
MULTIPLY(row3, FIX_3_072711026_MINUS_2_562915447); \
/* now we can use q1 (reloadable constants have been used up) */ \
q1 = q3 + q2; \
q4 += MULTIPLY(row7, FIX_0_298631336_MINUS_0_899976223) + \
MULTIPLY(row1, -FIX_0_899976223); \
q5 = q7; \
q1 = q1 + q6; \
q7 += MULTIPLY(row7, -FIX_0_899976223) + \
MULTIPLY(row1, FIX_1_501321110_MINUS_0_899976223); \
\
/* (tmp11 + tmp2) has been calculated (out_row1 before descale) */ \
tmp11_plus_tmp2 = q1; \
row1 = 0; \
\
q1 = q1 - q6; \
q5 += MULTIPLY(row5, FIX_2_053119869_MINUS_2_562915447) + \
MULTIPLY(row3, -FIX_2_562915447); \
q1 = q1 - q6; \
q6 = MULTIPLY(row2, FIX_0_541196100_PLUS_0_765366865) + \
MULTIPLY(row6, FIX_0_541196100); \
q3 = q3 - q2; \
\
/* (tmp11 - tmp2) has been calculated (out_row6 before descale) */ \
tmp11_minus_tmp2 = q1; \
\
q1 = ((INT32) row0 + (INT32) row4) << 13; \
q2 = q1 + q6; \
q1 = q1 - q6; \
\
/* pick up the results */ \
tmp0 = q4; \
tmp1 = q5; \
tmp2 = (tmp11_plus_tmp2 - tmp11_minus_tmp2) / 2; \
tmp3 = q7; \
tmp10 = q2; \
tmp11 = (tmp11_plus_tmp2 + tmp11_minus_tmp2) / 2; \
tmp12 = q3; \
tmp13 = q1; \
}
#define XFIX_0_899976223 v0.h[0]
#define XFIX_0_541196100 v0.h[1]
#define XFIX_2_562915447 v0.h[2]
#define XFIX_0_298631336_MINUS_0_899976223 v0.h[3]
#define XFIX_1_501321110_MINUS_0_899976223 v1.h[0]
#define XFIX_2_053119869_MINUS_2_562915447 v1.h[1]
#define XFIX_0_541196100_PLUS_0_765366865 v1.h[2]
#define XFIX_1_175875602 v1.h[3]
#define XFIX_1_175875602_MINUS_0_390180644 v2.h[0]
#define XFIX_0_541196100_MINUS_1_847759065 v2.h[1]
#define XFIX_3_072711026_MINUS_2_562915447 v2.h[2]
#define XFIX_1_175875602_MINUS_1_961570560 v2.h[3]
.balign 16
Ljsimd_idct_islow_neon_consts:
.short FIX_0_899976223 /* d0[0] */
.short FIX_0_541196100 /* d0[1] */
.short FIX_2_562915447 /* d0[2] */
.short FIX_0_298631336_MINUS_0_899976223 /* d0[3] */
.short FIX_1_501321110_MINUS_0_899976223 /* d1[0] */
.short FIX_2_053119869_MINUS_2_562915447 /* d1[1] */
.short FIX_0_541196100_PLUS_0_765366865 /* d1[2] */
.short FIX_1_175875602 /* d1[3] */
/* reloadable constants */
.short FIX_1_175875602_MINUS_0_390180644 /* d2[0] */
.short FIX_0_541196100_MINUS_1_847759065 /* d2[1] */
.short FIX_3_072711026_MINUS_2_562915447 /* d2[2] */
.short FIX_1_175875602_MINUS_1_961570560 /* d2[3] */
asm_function jsimd_idct_islow_neon
DCT_TABLE .req x0
COEF_BLOCK .req x1
OUTPUT_BUF .req x2
OUTPUT_COL .req x3
TMP1 .req x0
TMP2 .req x1
TMP3 .req x2
TMP4 .req x15
ROW0L .req v16
ROW0R .req v17
ROW1L .req v18
ROW1R .req v19
ROW2L .req v20
ROW2R .req v21
ROW3L .req v22
ROW3R .req v23
ROW4L .req v24
ROW4R .req v25
ROW5L .req v26
ROW5R .req v27
ROW6L .req v28
ROW6R .req v29
ROW7L .req v30
ROW7R .req v31
/* Save all NEON registers and x15 (32 NEON registers * 8 bytes + 16) */
sub sp, sp, 272
str x15, [sp], 16
adr x15, Ljsimd_idct_islow_neon_consts
st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [sp], 32
st1 {v4.8b, v5.8b, v6.8b, v7.8b}, [sp], 32
st1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
st1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
st1 {v16.8b, v17.8b, v18.8b, v19.8b}, [sp], 32
st1 {v20.8b, v21.8b, v22.8b, v23.8b}, [sp], 32
st1 {v24.8b, v25.8b, v26.8b, v27.8b}, [sp], 32
st1 {v28.8b, v29.8b, v30.8b, v31.8b}, [sp], 32
ld1 {v16.4h, v17.4h, v18.4h, v19.4h}, [COEF_BLOCK], 32
ld1 {v0.4h, v1.4h, v2.4h, v3.4h}, [DCT_TABLE], 32
ld1 {v20.4h, v21.4h, v22.4h, v23.4h}, [COEF_BLOCK], 32
mul v16.4h, v16.4h, v0.4h
mul v17.4h, v17.4h, v1.4h
ins v16.d[1], v17.d[0] /* 128 bit q8 */
ld1 {v4.4h, v5.4h, v6.4h, v7.4h}, [DCT_TABLE], 32
mul v18.4h, v18.4h, v2.4h
mul v19.4h, v19.4h, v3.4h
ins v18.d[1], v19.d[0] /* 128 bit q9 */
ld1 {v24.4h, v25.4h, v26.4h, v27.4h}, [COEF_BLOCK], 32
mul v20.4h, v20.4h, v4.4h
mul v21.4h, v21.4h, v5.4h
ins v20.d[1], v21.d[0] /* 128 bit q10 */
ld1 {v0.4h, v1.4h, v2.4h, v3.4h}, [DCT_TABLE], 32
mul v22.4h, v22.4h, v6.4h
mul v23.4h, v23.4h, v7.4h
ins v22.d[1], v23.d[0] /* 128 bit q11 */
ld1 {v28.4h, v29.4h, v30.4h, v31.4h}, [COEF_BLOCK]
mul v24.4h, v24.4h, v0.4h
mul v25.4h, v25.4h, v1.4h
ins v24.d[1], v25.d[0] /* 128 bit q12 */
ld1 {v4.4h, v5.4h, v6.4h, v7.4h}, [DCT_TABLE], 32
mul v28.4h, v28.4h, v4.4h
mul v29.4h, v29.4h, v5.4h
ins v28.d[1], v29.d[0] /* 128 bit q14 */
mul v26.4h, v26.4h, v2.4h
mul v27.4h, v27.4h, v3.4h
ins v26.d[1], v27.d[0] /* 128 bit q13 */
ld1 {v0.4h, v1.4h, v2.4h, v3.4h}, [x15] /* load constants */
add x15, x15, #16
mul v30.4h, v30.4h, v6.4h
mul v31.4h, v31.4h, v7.4h
ins v30.d[1], v31.d[0] /* 128 bit q15 */
/* Go to the bottom of the stack */
sub sp, sp, 352
stp x4, x5, [sp], 16
st1 {v8.4h, v9.4h, v10.4h, v11.4h}, [sp], 32 /* save NEON registers */
st1 {v12.4h, v13.4h, v14.4h, v15.4h}, [sp], 32
/* 1-D IDCT, pass 1, left 4x8 half */
add v4.4h, ROW7L.4h, ROW3L.4h
add v5.4h, ROW5L.4h, ROW1L.4h
smull v12.4s, v4.4h, XFIX_1_175875602_MINUS_1_961570560
smlal v12.4s, v5.4h, XFIX_1_175875602
smull v14.4s, v4.4h, XFIX_1_175875602
/* Check for the zero coefficients in the right 4x8 half */
smlal v14.4s, v5.4h, XFIX_1_175875602_MINUS_0_390180644
ssubl v6.4s, ROW0L.4h, ROW4L.4h
ldp w4, w5, [COEF_BLOCK, #(-96 + 2 * (4 + 1 * 8))]
smull v4.4s, ROW2L.4h, XFIX_0_541196100
smlal v4.4s, ROW6L.4h, XFIX_0_541196100_MINUS_1_847759065
orr x0, x4, x5
mov v8.16b, v12.16b
smlsl v12.4s, ROW5L.4h, XFIX_2_562915447
ldp w4, w5, [COEF_BLOCK, #(-96 + 2 * (4 + 2 * 8))]
smlal v12.4s, ROW3L.4h, XFIX_3_072711026_MINUS_2_562915447
shl v6.4s, v6.4s, #13
orr x0, x0, x4
smlsl v8.4s, ROW1L.4h, XFIX_0_899976223
orr x0, x0 , x5
add v2.4s, v6.4s, v4.4s
ldp w4, w5, [COEF_BLOCK, #(-96 + 2 * (4 + 3 * 8))]
mov v10.16b, v14.16b
add v2.4s, v2.4s, v12.4s
orr x0, x0, x4
smlsl v14.4s, ROW7L.4h, XFIX_0_899976223
orr x0, x0, x5
smlal v14.4s, ROW1L.4h, XFIX_1_501321110_MINUS_0_899976223
rshrn ROW1L.4h, v2.4s, #11
ldp w4, w5, [COEF_BLOCK, #(-96 + 2 * (4 + 4 * 8))]
sub v2.4s, v2.4s, v12.4s
smlal v10.4s, ROW5L.4h, XFIX_2_053119869_MINUS_2_562915447
orr x0, x0, x4
smlsl v10.4s, ROW3L.4h, XFIX_2_562915447
orr x0, x0, x5
sub v2.4s, v2.4s, v12.4s
smull v12.4s, ROW2L.4h, XFIX_0_541196100_PLUS_0_765366865
ldp w4, w5, [COEF_BLOCK, #(-96 + 2 * (4 + 5 * 8))]
smlal v12.4s, ROW6L.4h, XFIX_0_541196100
sub v6.4s, v6.4s, v4.4s
orr x0, x0, x4
rshrn ROW6L.4h, v2.4s, #11
orr x0, x0, x5
add v2.4s, v6.4s, v10.4s
ldp w4, w5, [COEF_BLOCK, #(-96 + 2 * (4 + 6 * 8))]
sub v6.4s, v6.4s, v10.4s
saddl v10.4s, ROW0L.4h, ROW4L.4h
orr x0, x0, x4
rshrn ROW2L.4h, v2.4s, #11
orr x0, x0, x5
rshrn ROW5L.4h, v6.4s, #11
ldp w4, w5, [COEF_BLOCK, #(-96 + 2 * (4 + 7 * 8))]
shl v10.4s, v10.4s, #13
smlal v8.4s, ROW7L.4h, XFIX_0_298631336_MINUS_0_899976223
orr x0, x0, x4
add v4.4s, v10.4s, v12.4s
orr x0, x0, x5
cmp x0, #0 /* orrs instruction removed */
sub v2.4s, v10.4s, v12.4s
add v12.4s, v4.4s, v14.4s
ldp w4, w5, [COEF_BLOCK, #(-96 + 2 * (4 + 0 * 8))]
sub v4.4s, v4.4s, v14.4s
add v10.4s, v2.4s, v8.4s
orr x0, x4, x5
sub v6.4s, v2.4s, v8.4s
/* pop {x4, x5} */
sub sp, sp, 80
ldp x4, x5, [sp], 16
rshrn ROW7L.4h, v4.4s, #11
rshrn ROW3L.4h, v10.4s, #11
rshrn ROW0L.4h, v12.4s, #11
rshrn ROW4L.4h, v6.4s, #11
b.eq 3f /* Go to do some special handling for the sparse right 4x8 half */
/* 1-D IDCT, pass 1, right 4x8 half */
ld1 {v2.4h}, [x15] /* reload constants */
add v10.4h, ROW7R.4h, ROW3R.4h
add v8.4h, ROW5R.4h, ROW1R.4h
/* Transpose ROW6L <-> ROW7L (v3 available free register) */
transpose ROW6L, ROW7L, v3, .16b, .4h
smull v12.4s, v10.4h, XFIX_1_175875602_MINUS_1_961570560
smlal v12.4s, v8.4h, XFIX_1_175875602
/* Transpose ROW2L <-> ROW3L (v3 available free register) */
transpose ROW2L, ROW3L, v3, .16b, .4h
smull v14.4s, v10.4h, XFIX_1_175875602
smlal v14.4s, v8.4h, XFIX_1_175875602_MINUS_0_390180644
/* Transpose ROW0L <-> ROW1L (v3 available free register) */
transpose ROW0L, ROW1L, v3, .16b, .4h
ssubl v6.4s, ROW0R.4h, ROW4R.4h
smull v4.4s, ROW2R.4h, XFIX_0_541196100
smlal v4.4s, ROW6R.4h, XFIX_0_541196100_MINUS_1_847759065
/* Transpose ROW4L <-> ROW5L (v3 available free register) */
transpose ROW4L, ROW5L, v3, .16b, .4h
mov v8.16b, v12.16b
smlsl v12.4s, ROW5R.4h, XFIX_2_562915447
smlal v12.4s, ROW3R.4h, XFIX_3_072711026_MINUS_2_562915447
/* Transpose ROW1L <-> ROW3L (v3 available free register) */
transpose ROW1L, ROW3L, v3, .16b, .2s
shl v6.4s, v6.4s, #13
smlsl v8.4s, ROW1R.4h, XFIX_0_899976223
/* Transpose ROW4L <-> ROW6L (v3 available free register) */
transpose ROW4L, ROW6L, v3, .16b, .2s
add v2.4s, v6.4s, v4.4s
mov v10.16b, v14.16b
add v2.4s, v2.4s, v12.4s
/* Transpose ROW0L <-> ROW2L (v3 available free register) */
transpose ROW0L, ROW2L, v3, .16b, .2s
smlsl v14.4s, ROW7R.4h, XFIX_0_899976223
smlal v14.4s, ROW1R.4h, XFIX_1_501321110_MINUS_0_899976223
rshrn ROW1R.4h, v2.4s, #11
/* Transpose ROW5L <-> ROW7L (v3 available free register) */
transpose ROW5L, ROW7L, v3, .16b, .2s
sub v2.4s, v2.4s, v12.4s
smlal v10.4s, ROW5R.4h, XFIX_2_053119869_MINUS_2_562915447
smlsl v10.4s, ROW3R.4h, XFIX_2_562915447
sub v2.4s, v2.4s, v12.4s
smull v12.4s, ROW2R.4h, XFIX_0_541196100_PLUS_0_765366865
smlal v12.4s, ROW6R.4h, XFIX_0_541196100
sub v6.4s, v6.4s, v4.4s
rshrn ROW6R.4h, v2.4s, #11
add v2.4s, v6.4s, v10.4s
sub v6.4s, v6.4s, v10.4s
saddl v10.4s, ROW0R.4h, ROW4R.4h
rshrn ROW2R.4h, v2.4s, #11
rshrn ROW5R.4h, v6.4s, #11
shl v10.4s, v10.4s, #13
smlal v8.4s, ROW7R.4h, XFIX_0_298631336_MINUS_0_899976223
add v4.4s, v10.4s, v12.4s
sub v2.4s, v10.4s, v12.4s
add v12.4s, v4.4s, v14.4s
sub v4.4s, v4.4s, v14.4s
add v10.4s, v2.4s, v8.4s
sub v6.4s, v2.4s, v8.4s
rshrn ROW7R.4h, v4.4s, #11
rshrn ROW3R.4h, v10.4s, #11
rshrn ROW0R.4h, v12.4s, #11
rshrn ROW4R.4h, v6.4s, #11
/* Transpose right 4x8 half */
transpose ROW6R, ROW7R, v3, .16b, .4h
transpose ROW2R, ROW3R, v3, .16b, .4h
transpose ROW0R, ROW1R, v3, .16b, .4h
transpose ROW4R, ROW5R, v3, .16b, .4h
transpose ROW1R, ROW3R, v3, .16b, .2s
transpose ROW4R, ROW6R, v3, .16b, .2s
transpose ROW0R, ROW2R, v3, .16b, .2s
transpose ROW5R, ROW7R, v3, .16b, .2s
1: /* 1-D IDCT, pass 2 (normal variant), left 4x8 half */
ld1 {v2.4h}, [x15] /* reload constants */
smull v12.4S, ROW1R.4h, XFIX_1_175875602 /* ROW5L.4h <-> ROW1R.4h */
smlal v12.4s, ROW1L.4h, XFIX_1_175875602
smlal v12.4s, ROW3R.4h, XFIX_1_175875602_MINUS_1_961570560 /* ROW7L.4h <-> ROW3R.4h */
smlal v12.4s, ROW3L.4h, XFIX_1_175875602_MINUS_1_961570560
smull v14.4s, ROW3R.4h, XFIX_1_175875602 /* ROW7L.4h <-> ROW3R.4h */
smlal v14.4s, ROW3L.4h, XFIX_1_175875602
smlal v14.4s, ROW1R.4h, XFIX_1_175875602_MINUS_0_390180644 /* ROW5L.4h <-> ROW1R.4h */
smlal v14.4s, ROW1L.4h, XFIX_1_175875602_MINUS_0_390180644
ssubl v6.4s, ROW0L.4h, ROW0R.4h /* ROW4L.4h <-> ROW0R.4h */
smull v4.4s, ROW2L.4h, XFIX_0_541196100
smlal v4.4s, ROW2R.4h, XFIX_0_541196100_MINUS_1_847759065 /* ROW6L.4h <-> ROW2R.4h */
mov v8.16b, v12.16b
smlsl v12.4s, ROW1R.4h, XFIX_2_562915447 /* ROW5L.4h <-> ROW1R.4h */
smlal v12.4s, ROW3L.4h, XFIX_3_072711026_MINUS_2_562915447
shl v6.4s, v6.4s, #13
smlsl v8.4s, ROW1L.4h, XFIX_0_899976223
add v2.4s, v6.4s, v4.4s
mov v10.16b, v14.16b
add v2.4s, v2.4s, v12.4s
smlsl v14.4s, ROW3R.4h, XFIX_0_899976223 /* ROW7L.4h <-> ROW3R.4h */
smlal v14.4s, ROW1L.4h, XFIX_1_501321110_MINUS_0_899976223
shrn ROW1L.4h, v2.4s, #16
sub v2.4s, v2.4s, v12.4s
smlal v10.4s, ROW1R.4h, XFIX_2_053119869_MINUS_2_562915447 /* ROW5L.4h <-> ROW1R.4h */
smlsl v10.4s, ROW3L.4h, XFIX_2_562915447
sub v2.4s, v2.4s, v12.4s
smull v12.4s, ROW2L.4h, XFIX_0_541196100_PLUS_0_765366865
smlal v12.4s, ROW2R.4h, XFIX_0_541196100 /* ROW6L.4h <-> ROW2R.4h */
sub v6.4s, v6.4s, v4.4s
shrn ROW2R.4h, v2.4s, #16 /* ROW6L.4h <-> ROW2R.4h */
add v2.4s, v6.4s, v10.4s
sub v6.4s, v6.4s, v10.4s
saddl v10.4s, ROW0L.4h, ROW0R.4h /* ROW4L.4h <-> ROW0R.4h */
shrn ROW2L.4h, v2.4s, #16
shrn ROW1R.4h, v6.4s, #16 /* ROW5L.4h <-> ROW1R.4h */
shl v10.4s, v10.4s, #13
smlal v8.4s, ROW3R.4h, XFIX_0_298631336_MINUS_0_899976223 /* ROW7L.4h <-> ROW3R.4h */
add v4.4s, v10.4s, v12.4s
sub v2.4s, v10.4s, v12.4s
add v12.4s, v4.4s, v14.4s
sub v4.4s, v4.4s, v14.4s
add v10.4s, v2.4s, v8.4s
sub v6.4s, v2.4s, v8.4s
shrn ROW3R.4h, v4.4s, #16 /* ROW7L.4h <-> ROW3R.4h */
shrn ROW3L.4h, v10.4s, #16
shrn ROW0L.4h, v12.4s, #16
shrn ROW0R.4h, v6.4s, #16 /* ROW4L.4h <-> ROW0R.4h */
/* 1-D IDCT, pass 2, right 4x8 half */
ld1 {v2.4h}, [x15] /* reload constants */
smull v12.4s, ROW5R.4h, XFIX_1_175875602
smlal v12.4s, ROW5L.4h, XFIX_1_175875602 /* ROW5L.4h <-> ROW1R.4h */
smlal v12.4s, ROW7R.4h, XFIX_1_175875602_MINUS_1_961570560
smlal v12.4s, ROW7L.4h, XFIX_1_175875602_MINUS_1_961570560 /* ROW7L.4h <-> ROW3R.4h */
smull v14.4s, ROW7R.4h, XFIX_1_175875602
smlal v14.4s, ROW7L.4h, XFIX_1_175875602 /* ROW7L.4h <-> ROW3R.4h */
smlal v14.4s, ROW5R.4h, XFIX_1_175875602_MINUS_0_390180644
smlal v14.4s, ROW5L.4h, XFIX_1_175875602_MINUS_0_390180644 /* ROW5L.4h <-> ROW1R.4h */
ssubl v6.4s, ROW4L.4h, ROW4R.4h /* ROW4L.4h <-> ROW0R.4h */
smull v4.4s, ROW6L.4h, XFIX_0_541196100 /* ROW6L.4h <-> ROW2R.4h */
smlal v4.4s, ROW6R.4h, XFIX_0_541196100_MINUS_1_847759065
mov v8.16b, v12.16b
smlsl v12.4s, ROW5R.4h, XFIX_2_562915447
smlal v12.4s, ROW7L.4h, XFIX_3_072711026_MINUS_2_562915447 /* ROW7L.4h <-> ROW3R.4h */
shl v6.4s, v6.4s, #13
smlsl v8.4s, ROW5L.4h, XFIX_0_899976223 /* ROW5L.4h <-> ROW1R.4h */
add v2.4s, v6.4s, v4.4s
mov v10.16b, v14.16b
add v2.4s, v2.4s, v12.4s
smlsl v14.4s, ROW7R.4h, XFIX_0_899976223
smlal v14.4s, ROW5L.4h, XFIX_1_501321110_MINUS_0_899976223 /* ROW5L.4h <-> ROW1R.4h */
shrn ROW5L.4h, v2.4s, #16 /* ROW5L.4h <-> ROW1R.4h */
sub v2.4s, v2.4s, v12.4s
smlal v10.4s, ROW5R.4h, XFIX_2_053119869_MINUS_2_562915447
smlsl v10.4s, ROW7L.4h, XFIX_2_562915447 /* ROW7L.4h <-> ROW3R.4h */
sub v2.4s, v2.4s, v12.4s
smull v12.4s, ROW6L.4h, XFIX_0_541196100_PLUS_0_765366865 /* ROW6L.4h <-> ROW2R.4h */
smlal v12.4s, ROW6R.4h, XFIX_0_541196100
sub v6.4s, v6.4s, v4.4s
shrn ROW6R.4h, v2.4s, #16
add v2.4s, v6.4s, v10.4s
sub v6.4s, v6.4s, v10.4s
saddl v10.4s, ROW4L.4h, ROW4R.4h /* ROW4L.4h <-> ROW0R.4h */
shrn ROW6L.4h, v2.4s, #16 /* ROW6L.4h <-> ROW2R.4h */
shrn ROW5R.4h, v6.4s, #16
shl v10.4s, v10.4s, #13
smlal v8.4s, ROW7R.4h, XFIX_0_298631336_MINUS_0_899976223
add v4.4s, v10.4s, v12.4s
sub v2.4s, v10.4s, v12.4s
add v12.4s, v4.4s, v14.4s
sub v4.4s, v4.4s, v14.4s
add v10.4s, v2.4s, v8.4s
sub v6.4s, v2.4s, v8.4s
shrn ROW7R.4h, v4.4s, #16
shrn ROW7L.4h, v10.4s, #16 /* ROW7L.4h <-> ROW3R.4h */
shrn ROW4L.4h, v12.4s, #16 /* ROW4L.4h <-> ROW0R.4h */
shrn ROW4R.4h, v6.4s, #16
2: /* Descale to 8-bit and range limit */
ins v16.d[1], v17.d[0]
ins v18.d[1], v19.d[0]
ins v20.d[1], v21.d[0]
ins v22.d[1], v23.d[0]
sqrshrn v16.8b, v16.8h, #2
sqrshrn2 v16.16b, v18.8h, #2
sqrshrn v18.8b, v20.8h, #2
sqrshrn2 v18.16b, v22.8h, #2
/* vpop {v8.4h - d15.4h} */ /* restore NEON registers */
ld1 {v8.4h, v9.4h, v10.4h, v11.4h}, [sp], 32
ld1 {v12.4h, v13.4h, v14.4h, v15.4h}, [sp], 32
ins v24.d[1], v25.d[0]
sqrshrn v20.8b, v24.8h, #2
/* Transpose the final 8-bit samples and do signed->unsigned conversion */
/* trn1 v16.8h, v16.8h, v18.8h */
transpose v16, v18, v3, .16b, .8h
ins v26.d[1], v27.d[0]
ins v28.d[1], v29.d[0]
ins v30.d[1], v31.d[0]
sqrshrn2 v20.16b, v26.8h, #2
sqrshrn v22.8b, v28.8h, #2
movi v0.16b, #(CENTERJSAMPLE)
sqrshrn2 v22.16b, v30.8h, #2
transpose_single v16, v17, v3, .d, .8b
transpose_single v18, v19, v3, .d, .8b
add v16.8b, v16.8b, v0.8b
add v17.8b, v17.8b, v0.8b
add v18.8b, v18.8b, v0.8b
add v19.8b, v19.8b, v0.8b
transpose v20, v22, v3, .16b, .8h
/* Store results to the output buffer */
ldp TMP1, TMP2, [OUTPUT_BUF], 16
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
st1 {v16.8b}, [TMP1]
transpose_single v20, v21, v3, .d, .8b
st1 {v17.8b}, [TMP2]
ldp TMP1, TMP2, [OUTPUT_BUF], 16
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
st1 {v18.8b}, [TMP1]
add v20.8b, v20.8b, v0.8b
add v21.8b, v21.8b, v0.8b
st1 {v19.8b}, [TMP2]
ldp TMP1, TMP2, [OUTPUT_BUF], 16
ldp TMP3, TMP4, [OUTPUT_BUF]
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
add TMP3, TMP3, OUTPUT_COL
add TMP4, TMP4, OUTPUT_COL
transpose_single v22, v23, v3, .d, .8b
st1 {v20.8b}, [TMP1]
add v22.8b, v22.8b, v0.8b
add v23.8b, v23.8b, v0.8b
st1 {v21.8b}, [TMP2]
st1 {v22.8b}, [TMP3]
st1 {v23.8b}, [TMP4]
ldr x15, [sp], 16
ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [sp], 32
ld1 {v4.8b, v5.8b, v6.8b, v7.8b}, [sp], 32
ld1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
ld1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
ld1 {v16.8b, v17.8b, v18.8b, v19.8b}, [sp], 32
ld1 {v20.8b, v21.8b, v22.8b, v23.8b}, [sp], 32
ld1 {v24.8b, v25.8b, v26.8b, v27.8b}, [sp], 32
ld1 {v28.8b, v29.8b, v30.8b, v31.8b}, [sp], 32
blr x30
3: /* Left 4x8 half is done, right 4x8 half contains mostly zeros */
/* Transpose left 4x8 half */
transpose ROW6L, ROW7L, v3, .16b, .4h
transpose ROW2L, ROW3L, v3, .16b, .4h
transpose ROW0L, ROW1L, v3, .16b, .4h
transpose ROW4L, ROW5L, v3, .16b, .4h
shl ROW0R.4h, ROW0R.4h, #2 /* PASS1_BITS */
transpose ROW1L, ROW3L, v3, .16b, .2s
transpose ROW4L, ROW6L, v3, .16b, .2s
transpose ROW0L, ROW2L, v3, .16b, .2s
transpose ROW5L, ROW7L, v3, .16b, .2s
cmp x0, #0
b.eq 4f /* Right 4x8 half has all zeros, go to 'sparse' second pass */
/* Only row 0 is non-zero for the right 4x8 half */
dup ROW1R.4h, ROW0R.h[1]
dup ROW2R.4h, ROW0R.h[2]
dup ROW3R.4h, ROW0R.h[3]
dup ROW4R.4h, ROW0R.h[0]
dup ROW5R.4h, ROW0R.h[1]
dup ROW6R.4h, ROW0R.h[2]
dup ROW7R.4h, ROW0R.h[3]
dup ROW0R.4h, ROW0R.h[0]
b 1b /* Go to 'normal' second pass */
4: /* 1-D IDCT, pass 2 (sparse variant with zero rows 4-7), left 4x8 half */
ld1 {v2.4h}, [x15] /* reload constants */
smull v12.4s, ROW1L.4h, XFIX_1_175875602
smlal v12.4s, ROW3L.4h, XFIX_1_175875602_MINUS_1_961570560
smull v14.4s, ROW3L.4h, XFIX_1_175875602
smlal v14.4s, ROW1L.4h, XFIX_1_175875602_MINUS_0_390180644
smull v4.4s, ROW2L.4h, XFIX_0_541196100
sshll v6.4s, ROW0L.4h, #13
mov v8.16b, v12.16b
smlal v12.4s, ROW3L.4h, XFIX_3_072711026_MINUS_2_562915447
smlsl v8.4s, ROW1L.4h, XFIX_0_899976223
add v2.4s, v6.4s, v4.4s
mov v10.16b, v14.16b
smlal v14.4s, ROW1L.4h, XFIX_1_501321110_MINUS_0_899976223
add v2.4s, v2.4s, v12.4s
add v12.4s, v12.4s, v12.4s
smlsl v10.4s, ROW3L.4h, XFIX_2_562915447
shrn ROW1L.4h, v2.4s, #16
sub v2.4s, v2.4s, v12.4s
smull v12.4s, ROW2L.4h, XFIX_0_541196100_PLUS_0_765366865
sub v6.4s, v6.4s, v4.4s
shrn ROW2R.4h, v2.4s, #16 /* ROW6L.4h <-> ROW2R.4h */
add v2.4s, v6.4s, v10.4s
sub v6.4s, v6.4s, v10.4s
sshll v10.4s, ROW0L.4h, #13
shrn ROW2L.4h, v2.4s, #16
shrn ROW1R.4h, v6.4s, #16 /* ROW5L.4h <-> ROW1R.4h */
add v4.4s, v10.4s, v12.4s
sub v2.4s, v10.4s, v12.4s
add v12.4s, v4.4s, v14.4s
sub v4.4s, v4.4s, v14.4s
add v10.4s, v2.4s, v8.4s
sub v6.4s, v2.4s, v8.4s
shrn ROW3R.4h, v4.4s, #16 /* ROW7L.4h <-> ROW3R.4h */
shrn ROW3L.4h, v10.4s, #16
shrn ROW0L.4h, v12.4s, #16
shrn ROW0R.4h, v6.4s, #16 /* ROW4L.4h <-> ROW0R.4h */
/* 1-D IDCT, pass 2 (sparse variant with zero rows 4-7), right 4x8 half */
ld1 {v2.4h}, [x15] /* reload constants */
smull v12.4s, ROW5L.4h, XFIX_1_175875602
smlal v12.4s, ROW7L.4h, XFIX_1_175875602_MINUS_1_961570560
smull v14.4s, ROW7L.4h, XFIX_1_175875602
smlal v14.4s, ROW5L.4h, XFIX_1_175875602_MINUS_0_390180644
smull v4.4s, ROW6L.4h, XFIX_0_541196100
sshll v6.4s, ROW4L.4h, #13
mov v8.16b, v12.16b
smlal v12.4s, ROW7L.4h, XFIX_3_072711026_MINUS_2_562915447
smlsl v8.4s, ROW5L.4h, XFIX_0_899976223
add v2.4s, v6.4s, v4.4s
mov v10.16b, v14.16b
smlal v14.4s, ROW5L.4h, XFIX_1_501321110_MINUS_0_899976223
add v2.4s, v2.4s, v12.4s
add v12.4s, v12.4s, v12.4s
smlsl v10.4s, ROW7L.4h, XFIX_2_562915447
shrn ROW5L.4h, v2.4s, #16 /* ROW5L.4h <-> ROW1R.4h */
sub v2.4s, v2.4s, v12.4s
smull v12.4s, ROW6L.4h, XFIX_0_541196100_PLUS_0_765366865
sub v6.4s, v6.4s, v4.4s
shrn ROW6R.4h, v2.4s, #16
add v2.4s, v6.4s, v10.4s
sub v6.4s, v6.4s, v10.4s
sshll v10.4s, ROW4L.4h, #13
shrn ROW6L.4h, v2.4s, #16 /* ROW6L.4h <-> ROW2R.4h */
shrn ROW5R.4h, v6.4s, #16
add v4.4s, v10.4s, v12.4s
sub v2.4s, v10.4s, v12.4s
add v12.4s, v4.4s, v14.4s
sub v4.4s, v4.4s, v14.4s
add v10.4s, v2.4s, v8.4s
sub v6.4s, v2.4s, v8.4s
shrn ROW7R.4h, v4.4s, #16
shrn ROW7L.4h, v10.4s, #16 /* ROW7L.4h <-> ROW3R.4h */
shrn ROW4L.4h, v12.4s, #16 /* ROW4L.4h <-> ROW0R.4h */
shrn ROW4R.4h, v6.4s, #16
b 2b /* Go to epilogue */
.unreq DCT_TABLE
.unreq COEF_BLOCK
.unreq OUTPUT_BUF
.unreq OUTPUT_COL
.unreq TMP1
.unreq TMP2
.unreq TMP3
.unreq TMP4
.unreq ROW0L
.unreq ROW0R
.unreq ROW1L
.unreq ROW1R
.unreq ROW2L
.unreq ROW2R
.unreq ROW3L
.unreq ROW3R
.unreq ROW4L
.unreq ROW4R
.unreq ROW5L
.unreq ROW5R
.unreq ROW6L
.unreq ROW6R
.unreq ROW7L
.unreq ROW7R
/*****************************************************************************/
/*
* jsimd_idct_ifast_neon
*
* This function contains a fast, not so accurate integer implementation of
* the inverse DCT (Discrete Cosine Transform). It uses the same calculations
* and produces exactly the same output as IJG's original 'jpeg_idct_ifast'
* function from jidctfst.c
*
* Normally 1-D AAN DCT needs 5 multiplications and 29 additions.
* But in ARM NEON case some extra additions are required because VQDMULH
* instruction can't handle the constants larger than 1. So the expressions
* like "x * 1.082392200" have to be converted to "x * 0.082392200 + x",
* which introduces an extra addition. Overall, there are 6 extra additions
* per 1-D IDCT pass, totalling to 5 VQDMULH and 35 VADD/VSUB instructions.
*/
#define XFIX_1_082392200 v0.h[0]
#define XFIX_1_414213562 v0.h[1]
#define XFIX_1_847759065 v0.h[2]
#define XFIX_2_613125930 v0.h[3]
.balign 16
Ljsimd_idct_ifast_neon_consts:
.short (277 * 128 - 256 * 128) /* XFIX_1_082392200 */
.short (362 * 128 - 256 * 128) /* XFIX_1_414213562 */
.short (473 * 128 - 256 * 128) /* XFIX_1_847759065 */
.short (669 * 128 - 512 * 128) /* XFIX_2_613125930 */
asm_function jsimd_idct_ifast_neon
DCT_TABLE .req x0
COEF_BLOCK .req x1
OUTPUT_BUF .req x2
OUTPUT_COL .req x3
TMP1 .req x0
TMP2 .req x1
TMP3 .req x2
TMP4 .req x22
TMP5 .req x23
/* Load and dequantize coefficients into NEON registers
* with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | d16 | d17 ( v8.8h )
* 1 | d18 | d19 ( v9.8h )
* 2 | d20 | d21 ( v10.8h )
* 3 | d22 | d23 ( v11.8h )
* 4 | d24 | d25 ( v12.8h )
* 5 | d26 | d27 ( v13.8h )
* 6 | d28 | d29 ( v14.8h )
* 7 | d30 | d31 ( v15.8h )
*/
/* Save NEON registers used in fast IDCT */
sub sp, sp, #176
stp x22, x23, [sp], 16
adr x23, Ljsimd_idct_ifast_neon_consts
st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [sp], 32
st1 {v4.8b, v5.8b, v6.8b, v7.8b}, [sp], 32
st1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
st1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
st1 {v16.8b, v17.8b, v18.8b, v19.8b}, [sp], 32
ld1 {v8.8h, v9.8h}, [COEF_BLOCK], 32
ld1 {v0.8h, v1.8h}, [DCT_TABLE], 32
ld1 {v10.8h, v11.8h}, [COEF_BLOCK], 32
mul v8.8h, v8.8h, v0.8h
ld1 {v2.8h, v3.8h}, [DCT_TABLE], 32
mul v9.8h, v9.8h, v1.8h
ld1 {v12.8h, v13.8h}, [COEF_BLOCK], 32
mul v10.8h, v10.8h, v2.8h
ld1 {v0.8h, v1.8h}, [DCT_TABLE], 32
mul v11.8h, v11.8h, v3.8h
ld1 {v14.8h, v15.8h}, [COEF_BLOCK], 32
mul v12.8h, v12.8h, v0.8h
ld1 {v2.8h, v3.8h}, [DCT_TABLE], 32
mul v14.8h, v14.8h, v2.8h
mul v13.8h, v13.8h, v1.8h
ld1 {v0.4h}, [x23] /* load constants */
mul v15.8h, v15.8h, v3.8h
/* 1-D IDCT, pass 1 */
sub v2.8h, v10.8h, v14.8h
add v14.8h, v10.8h, v14.8h
sub v1.8h, v11.8h, v13.8h
add v13.8h, v11.8h, v13.8h
sub v5.8h, v9.8h, v15.8h
add v15.8h, v9.8h, v15.8h
sqdmulh v4.8h, v2.8h, XFIX_1_414213562
sqdmulh v6.8h, v1.8h, XFIX_2_613125930
add v3.8h, v1.8h, v1.8h
sub v1.8h, v5.8h, v1.8h
add v10.8h, v2.8h, v4.8h
sqdmulh v4.8h, v1.8h, XFIX_1_847759065
sub v2.8h, v15.8h, v13.8h
add v3.8h, v3.8h, v6.8h
sqdmulh v6.8h, v2.8h, XFIX_1_414213562
add v1.8h, v1.8h, v4.8h
sqdmulh v4.8h, v5.8h, XFIX_1_082392200
sub v10.8h, v10.8h, v14.8h
add v2.8h, v2.8h, v6.8h
sub v6.8h, v8.8h, v12.8h
add v12.8h, v8.8h, v12.8h
add v9.8h, v5.8h, v4.8h
add v5.8h, v6.8h, v10.8h
sub v10.8h, v6.8h, v10.8h
add v6.8h, v15.8h, v13.8h
add v8.8h, v12.8h, v14.8h
sub v3.8h, v6.8h, v3.8h
sub v12.8h, v12.8h, v14.8h
sub v3.8h, v3.8h, v1.8h
sub v1.8h, v9.8h, v1.8h
add v2.8h, v3.8h, v2.8h
sub v15.8h, v8.8h, v6.8h
add v1.8h, v1.8h, v2.8h
add v8.8h, v8.8h, v6.8h
add v14.8h, v5.8h, v3.8h
sub v9.8h, v5.8h, v3.8h
sub v13.8h, v10.8h, v2.8h
add v10.8h, v10.8h, v2.8h
/* Transpose q8-q9 */
mov v18.16b, v8.16b
trn1 v8.8h, v8.8h, v9.8h
trn2 v9.8h, v18.8h, v9.8h
sub v11.8h, v12.8h, v1.8h
/* Transpose q14-q15 */
mov v18.16b, v14.16b
trn1 v14.8h, v14.8h, v15.8h
trn2 v15.8h, v18.8h, v15.8h
add v12.8h, v12.8h, v1.8h
/* Transpose q10-q11 */
mov v18.16b, v10.16b
trn1 v10.8h, v10.8h, v11.8h
trn2 v11.8h, v18.8h, v11.8h
/* Transpose q12-q13 */
mov v18.16b, v12.16b
trn1 v12.8h, v12.8h, v13.8h
trn2 v13.8h, v18.8h, v13.8h
/* Transpose q9-q11 */
mov v18.16b, v9.16b
trn1 v9.4s, v9.4s, v11.4s
trn2 v11.4s, v18.4s, v11.4s
/* Transpose q12-q14 */
mov v18.16b, v12.16b
trn1 v12.4s, v12.4s, v14.4s
trn2 v14.4s, v18.4s, v14.4s
/* Transpose q8-q10 */
mov v18.16b, v8.16b
trn1 v8.4s, v8.4s, v10.4s
trn2 v10.4s, v18.4s, v10.4s
/* Transpose q13-q15 */
mov v18.16b, v13.16b
trn1 v13.4s, v13.4s, v15.4s
trn2 v15.4s, v18.4s, v15.4s
/* vswp v14.4h, v10-MSB.4h */
umov x22, v14.d[0]
ins v14.d[0], v10.d[1]
ins v10.d[1], x22
/* vswp v13.4h, v9MSB.4h */
umov x22, v13.d[0]
ins v13.d[0], v9.d[1]
ins v9.d[1], x22
/* 1-D IDCT, pass 2 */
sub v2.8h, v10.8h, v14.8h
/* vswp v15.4h, v11MSB.4h */
umov x22, v15.d[0]
ins v15.d[0], v11.d[1]
ins v11.d[1], x22
add v14.8h, v10.8h, v14.8h
/* vswp v12.4h, v8-MSB.4h */
umov x22, v12.d[0]
ins v12.d[0], v8.d[1]
ins v8.d[1], x22
sub v1.8h, v11.8h, v13.8h
add v13.8h, v11.8h, v13.8h
sub v5.8h, v9.8h, v15.8h
add v15.8h, v9.8h, v15.8h
sqdmulh v4.8h, v2.8h, XFIX_1_414213562
sqdmulh v6.8h, v1.8h, XFIX_2_613125930
add v3.8h, v1.8h, v1.8h
sub v1.8h, v5.8h, v1.8h
add v10.8h, v2.8h, v4.8h
sqdmulh v4.8h, v1.8h, XFIX_1_847759065
sub v2.8h, v15.8h, v13.8h
add v3.8h, v3.8h, v6.8h
sqdmulh v6.8h, v2.8h, XFIX_1_414213562
add v1.8h, v1.8h, v4.8h
sqdmulh v4.8h, v5.8h, XFIX_1_082392200
sub v10.8h, v10.8h, v14.8h
add v2.8h, v2.8h, v6.8h
sub v6.8h, v8.8h, v12.8h
add v12.8h, v8.8h, v12.8h
add v9.8h, v5.8h, v4.8h
add v5.8h, v6.8h, v10.8h
sub v10.8h, v6.8h, v10.8h
add v6.8h, v15.8h, v13.8h
add v8.8h, v12.8h, v14.8h
sub v3.8h, v6.8h, v3.8h
sub v12.8h, v12.8h, v14.8h
sub v3.8h, v3.8h, v1.8h
sub v1.8h, v9.8h, v1.8h
add v2.8h, v3.8h, v2.8h
sub v15.8h, v8.8h, v6.8h
add v1.8h, v1.8h, v2.8h
add v8.8h, v8.8h, v6.8h
add v14.8h, v5.8h, v3.8h
sub v9.8h, v5.8h, v3.8h
sub v13.8h, v10.8h, v2.8h
add v10.8h, v10.8h, v2.8h
sub v11.8h, v12.8h, v1.8h
add v12.8h, v12.8h, v1.8h
/* Descale to 8-bit and range limit */
movi v0.16b, #0x80
sqshrn v8.8b, v8.8h, #5
sqshrn2 v8.16b, v9.8h, #5
sqshrn v9.8b, v10.8h, #5
sqshrn2 v9.16b, v11.8h, #5
sqshrn v10.8b, v12.8h, #5
sqshrn2 v10.16b, v13.8h, #5
sqshrn v11.8b, v14.8h, #5
sqshrn2 v11.16b, v15.8h, #5
add v8.16b, v8.16b, v0.16b
add v9.16b, v9.16b, v0.16b
add v10.16b, v10.16b, v0.16b
add v11.16b, v11.16b, v0.16b
/* Transpose the final 8-bit samples */
/* Transpose q8-q9 */
mov v18.16b, v8.16b
trn1 v8.8h, v8.8h, v9.8h
trn2 v9.8h, v18.8h, v9.8h
/* Transpose q10-q11 */
mov v18.16b, v10.16b
trn1 v10.8h, v10.8h, v11.8h
trn2 v11.8h, v18.8h, v11.8h
/* Transpose q8-q10 */
mov v18.16b, v8.16b
trn1 v8.4s, v8.4s, v10.4s
trn2 v10.4s, v18.4s, v10.4s
/* Transpose q9-q11 */
mov v18.16b, v9.16b
trn1 v9.4s, v9.4s, v11.4s
trn2 v11.4s, v18.4s, v11.4s
/* make copy */
ins v17.d[0], v8.d[1]
/* Transpose d16-d17-msb */
mov v18.16b, v8.16b
trn1 v8.8b, v8.8b, v17.8b
trn2 v17.8b, v18.8b, v17.8b
/* make copy */
ins v19.d[0], v9.d[1]
mov v18.16b, v9.16b
trn1 v9.8b, v9.8b, v19.8b
trn2 v19.8b, v18.8b, v19.8b
/* Store results to the output buffer */
ldp TMP1, TMP2, [OUTPUT_BUF], 16
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
st1 {v8.8b}, [TMP1]
st1 {v17.8b}, [TMP2]
ldp TMP1, TMP2, [OUTPUT_BUF], 16
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
st1 {v9.8b}, [TMP1]
/* make copy */
ins v7.d[0], v10.d[1]
mov v18.16b, v10.16b
trn1 v10.8b, v10.8b, v7.8b
trn2 v7.8b, v18.8b, v7.8b
st1 {v19.8b}, [TMP2]
ldp TMP1, TMP2, [OUTPUT_BUF], 16
ldp TMP4, TMP5, [OUTPUT_BUF], 16
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
add TMP4, TMP4, OUTPUT_COL
add TMP5, TMP5, OUTPUT_COL
st1 {v10.8b}, [TMP1]
/* make copy */
ins v16.d[0], v11.d[1]
mov v18.16b, v11.16b
trn1 v11.8b, v11.8b, v16.8b
trn2 v16.8b, v18.8b, v16.8b
st1 {v7.8b}, [TMP2]
st1 {v11.8b}, [TMP4]
st1 {v16.8b}, [TMP5]
sub sp, sp, #176
ldp x22, x23, [sp], 16
ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [sp], 32
ld1 {v4.8b, v5.8b, v6.8b, v7.8b}, [sp], 32
ld1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
ld1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
ld1 {v16.8b, v17.8b, v18.8b, v19.8b}, [sp], 32
blr x30
.unreq DCT_TABLE
.unreq COEF_BLOCK
.unreq OUTPUT_BUF
.unreq OUTPUT_COL
.unreq TMP1
.unreq TMP2
.unreq TMP3
.unreq TMP4
/*****************************************************************************/
/*
* jsimd_idct_4x4_neon
*
* This function contains inverse-DCT code for getting reduced-size
* 4x4 pixels output from an 8x8 DCT block. It uses the same calculations
* and produces exactly the same output as IJG's original 'jpeg_idct_4x4'
* function from jpeg-6b (jidctred.c).
*
* NOTE: jpeg-8 has an improved implementation of 4x4 inverse-DCT, which
* requires much less arithmetic operations and hence should be faster.
* The primary purpose of this particular NEON optimized function is
* bit exact compatibility with jpeg-6b.
*
* TODO: a bit better instructions scheduling can be achieved by expanding
* idct_helper/transpose_4x4 macros and reordering instructions,
* but readability will suffer somewhat.
*/
#define CONST_BITS 13
#define FIX_0_211164243 (1730) /* FIX(0.211164243) */
#define FIX_0_509795579 (4176) /* FIX(0.509795579) */
#define FIX_0_601344887 (4926) /* FIX(0.601344887) */
#define FIX_0_720959822 (5906) /* FIX(0.720959822) */
#define FIX_0_765366865 (6270) /* FIX(0.765366865) */
#define FIX_0_850430095 (6967) /* FIX(0.850430095) */
#define FIX_0_899976223 (7373) /* FIX(0.899976223) */
#define FIX_1_061594337 (8697) /* FIX(1.061594337) */
#define FIX_1_272758580 (10426) /* FIX(1.272758580) */
#define FIX_1_451774981 (11893) /* FIX(1.451774981) */
#define FIX_1_847759065 (15137) /* FIX(1.847759065) */
#define FIX_2_172734803 (17799) /* FIX(2.172734803) */
#define FIX_2_562915447 (20995) /* FIX(2.562915447) */
#define FIX_3_624509785 (29692) /* FIX(3.624509785) */
.balign 16
Ljsimd_idct_4x4_neon_consts:
.short FIX_1_847759065 /* v0.h[0] */
.short -FIX_0_765366865 /* v0.h[1] */
.short -FIX_0_211164243 /* v0.h[2] */
.short FIX_1_451774981 /* v0.h[3] */
.short -FIX_2_172734803 /* d1[0] */
.short FIX_1_061594337 /* d1[1] */
.short -FIX_0_509795579 /* d1[2] */
.short -FIX_0_601344887 /* d1[3] */
.short FIX_0_899976223 /* v2.h[0] */
.short FIX_2_562915447 /* v2.h[1] */
.short 1 << (CONST_BITS+1) /* v2.h[2] */
.short 0 /* v2.h[3] */
.macro idct_helper x4, x6, x8, x10, x12, x14, x16, shift, y26, y27, y28, y29
smull v28.4s, \x4, v2.h[2]
smlal v28.4s, \x8, v0.h[0]
smlal v28.4s, \x14, v0.h[1]
smull v26.4s, \x16, v1.h[2]
smlal v26.4s, \x12, v1.h[3]
smlal v26.4s, \x10, v2.h[0]
smlal v26.4s, \x6, v2.h[1]
smull v30.4s, \x4, v2.h[2]
smlsl v30.4s, \x8, v0.h[0]
smlsl v30.4s, \x14, v0.h[1]
smull v24.4s, \x16, v0.h[2]
smlal v24.4s, \x12, v0.h[3]
smlal v24.4s, \x10, v1.h[0]
smlal v24.4s, \x6, v1.h[1]
add v20.4s, v28.4s, v26.4s
sub v28.4s, v28.4s, v26.4s
.if \shift > 16
srshr v20.4s, v20.4s, #\shift
srshr v28.4s, v28.4s, #\shift
xtn \y26, v20.4s
xtn \y29, v28.4s
.else
rshrn \y26, v20.4s, #\shift
rshrn \y29, v28.4s, #\shift
.endif
add v20.4s, v30.4s, v24.4s
sub v30.4s, v30.4s, v24.4s
.if \shift > 16
srshr v20.4s, v20.4s, #\shift
srshr v30.4s, v30.4s, #\shift
xtn \y27, v20.4s
xtn \y28, v30.4s
.else
rshrn \y27, v20.4s, #\shift
rshrn \y28, v30.4s, #\shift
.endif
.endm
asm_function jsimd_idct_4x4_neon
DCT_TABLE .req x0
COEF_BLOCK .req x1
OUTPUT_BUF .req x2
OUTPUT_COL .req x3
TMP1 .req x0
TMP2 .req x1
TMP3 .req x2
TMP4 .req x15
/* Save all used NEON registers */
sub sp, sp, 272
str x15, [sp], 16
/* Load constants (v3.4h is just used for padding) */
adr TMP4, Ljsimd_idct_4x4_neon_consts
st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [sp], 32
st1 {v4.8b, v5.8b, v6.8b, v7.8b}, [sp], 32
st1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
st1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
st1 {v16.8b, v17.8b, v18.8b, v19.8b}, [sp], 32
st1 {v20.8b, v21.8b, v22.8b, v23.8b}, [sp], 32
st1 {v24.8b, v25.8b, v26.8b, v27.8b}, [sp], 32
st1 {v28.8b, v29.8b, v30.8b, v31.8b}, [sp], 32
ld1 {v0.4h, v1.4h, v2.4h, v3.4h}, [TMP4]
/* Load all COEF_BLOCK into NEON registers with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | v4.4h | v5.4h
* 1 | v6.4h | v7.4h
* 2 | v8.4h | v9.4h
* 3 | v10.4h | v11.4h
* 4 | - | -
* 5 | v12.4h | v13.4h
* 6 | v14.4h | v15.4h
* 7 | v16.4h | v17.4h
*/
ld1 {v4.4h, v5.4h, v6.4h, v7.4h}, [COEF_BLOCK], 32
ld1 {v8.4h, v9.4h, v10.4h, v11.4h}, [COEF_BLOCK], 32
add COEF_BLOCK, COEF_BLOCK, #16
ld1 {v12.4h, v13.4h, v14.4h, v15.4h}, [COEF_BLOCK], 32
ld1 {v16.4h, v17.4h}, [COEF_BLOCK], 16
/* dequantize */
ld1 {v18.4h, v19.4h, v20.4h, v21.4h}, [DCT_TABLE], 32
mul v4.4h, v4.4h, v18.4h
mul v5.4h, v5.4h, v19.4h
ins v4.d[1], v5.d[0] /* 128 bit q4 */
ld1 {v22.4h, v23.4h, v24.4h, v25.4h}, [DCT_TABLE], 32
mul v6.4h, v6.4h, v20.4h
mul v7.4h, v7.4h, v21.4h
ins v6.d[1], v7.d[0] /* 128 bit q6 */
mul v8.4h, v8.4h, v22.4h
mul v9.4h, v9.4h, v23.4h
ins v8.d[1], v9.d[0] /* 128 bit q8 */
add DCT_TABLE, DCT_TABLE, #16
ld1 {v26.4h, v27.4h, v28.4h, v29.4h}, [DCT_TABLE], 32
mul v10.4h, v10.4h, v24.4h
mul v11.4h, v11.4h, v25.4h
ins v10.d[1], v11.d[0] /* 128 bit q10 */
mul v12.4h, v12.4h, v26.4h
mul v13.4h, v13.4h, v27.4h
ins v12.d[1], v13.d[0] /* 128 bit q12 */
ld1 {v30.4h, v31.4h}, [DCT_TABLE], 16
mul v14.4h, v14.4h, v28.4h
mul v15.4h, v15.4h, v29.4h
ins v14.d[1], v15.d[0] /* 128 bit q14 */
mul v16.4h, v16.4h, v30.4h
mul v17.4h, v17.4h, v31.4h
ins v16.d[1], v17.d[0] /* 128 bit q16 */
/* Pass 1 */
idct_helper v4.4h, v6.4h, v8.4h, v10.4h, v12.4h, v14.4h, v16.4h, 12, v4.4h, v6.4h, v8.4h, v10.4h
transpose_4x4 v4, v6, v8, v10, v3
ins v10.d[1], v11.d[0]
idct_helper v5.4h, v7.4h, v9.4h, v11.4h, v13.4h, v15.4h, v17.4h, 12, v5.4h, v7.4h, v9.4h, v11.4h
transpose_4x4 v5, v7, v9, v11, v3
ins v10.d[1], v11.d[0]
/* Pass 2 */
idct_helper v4.4h, v6.4h, v8.4h, v10.4h, v7.4h, v9.4h, v11.4h, 19, v26.4h, v27.4h, v28.4h, v29.4h
transpose_4x4 v26, v27, v28, v29, v3
/* Range limit */
movi v30.8h, #0x80
ins v26.d[1], v27.d[0]
ins v28.d[1], v29.d[0]
add v26.8h, v26.8h, v30.8h
add v28.8h, v28.8h, v30.8h
sqxtun v26.8b, v26.8h
sqxtun v27.8b, v28.8h
/* Store results to the output buffer */
ldp TMP1, TMP2, [OUTPUT_BUF], 16
ldp TMP3, TMP4, [OUTPUT_BUF]
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
add TMP3, TMP3, OUTPUT_COL
add TMP4, TMP4, OUTPUT_COL
#if defined(__ARMEL__) && !RESPECT_STRICT_ALIGNMENT
/* We can use much less instructions on little endian systems if the
* OS kernel is not configured to trap unaligned memory accesses
*/
st1 {v26.s}[0], [TMP1], 4
st1 {v27.s}[0], [TMP3], 4
st1 {v26.s}[1], [TMP2], 4
st1 {v27.s}[1], [TMP4], 4
#else
st1 {v26.b}[0], [TMP1], 1
st1 {v27.b}[0], [TMP3], 1
st1 {v26.b}[1], [TMP1], 1
st1 {v27.b}[1], [TMP3], 1
st1 {v26.b}[2], [TMP1], 1
st1 {v27.b}[2], [TMP3], 1
st1 {v26.b}[3], [TMP1], 1
st1 {v27.b}[3], [TMP3], 1
st1 {v26.b}[4], [TMP2], 1
st1 {v27.b}[4], [TMP4], 1
st1 {v26.b}[5], [TMP2], 1
st1 {v27.b}[5], [TMP4], 1
st1 {v26.b}[6], [TMP2], 1
st1 {v27.b}[6], [TMP4], 1
st1 {v26.b}[7], [TMP2], 1
st1 {v27.b}[7], [TMP4], 1
#endif
/* vpop {v8.4h - v15.4h} ;not available */
sub sp, sp, #272
ldr x15, [sp], 16
ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [sp], 32
ld1 {v4.8b, v5.8b, v6.8b, v7.8b}, [sp], 32
ld1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
ld1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
ld1 {v16.8b, v17.8b, v18.8b, v19.8b}, [sp], 32
ld1 {v20.8b, v21.8b, v22.8b, v23.8b}, [sp], 32
ld1 {v24.8b, v25.8b, v26.8b, v27.8b}, [sp], 32
ld1 {v28.8b, v29.8b, v30.8b, v31.8b}, [sp], 32
blr x30
.unreq DCT_TABLE
.unreq COEF_BLOCK
.unreq OUTPUT_BUF
.unreq OUTPUT_COL
.unreq TMP1
.unreq TMP2
.unreq TMP3
.unreq TMP4
.purgem idct_helper
/*****************************************************************************/
/*
* jsimd_idct_2x2_neon
*
* This function contains inverse-DCT code for getting reduced-size
* 2x2 pixels output from an 8x8 DCT block. It uses the same calculations
* and produces exactly the same output as IJG's original 'jpeg_idct_2x2'
* function from jpeg-6b (jidctred.c).
*
* NOTE: jpeg-8 has an improved implementation of 2x2 inverse-DCT, which
* requires much less arithmetic operations and hence should be faster.
* The primary purpose of this particular NEON optimized function is
* bit exact compatibility with jpeg-6b.
*/
.balign 8
Ljsimd_idct_2x2_neon_consts:
.short -FIX_0_720959822 /* v14[0] */
.short FIX_0_850430095 /* v14[1] */
.short -FIX_1_272758580 /* v14[2] */
.short FIX_3_624509785 /* v14[3] */
.macro idct_helper x4, x6, x10, x12, x16, shift, y26, y27
sshll v15.4s, \x4, #15
smull v26.4s, \x6, v14.h[3]
smlal v26.4s, \x10, v14.h[2]
smlal v26.4s, \x12, v14.h[1]
smlal v26.4s, \x16, v14.h[0]
add v20.4s, v15.4s, v26.4s
sub v15.4s, v15.4s, v26.4s
.if \shift > 16
srshr v20.4s, v20.4s, #\shift
srshr v15.4s, v15.4s, #\shift
xtn \y26, v20.4s
xtn \y27, v15.4s
.else
rshrn \y26, v20.4s, #\shift
rshrn \y27, v15.4s, #\shift
.endif
.endm
asm_function jsimd_idct_2x2_neon
DCT_TABLE .req x0
COEF_BLOCK .req x1
OUTPUT_BUF .req x2
OUTPUT_COL .req x3
TMP1 .req x0
TMP2 .req x15
/* vpush {v8.4h - v15.4h} ; not available */
sub sp, sp, 208
str x15, [sp], 16
/* Load constants */
adr TMP2, Ljsimd_idct_2x2_neon_consts
st1 {v4.8b, v5.8b, v6.8b, v7.8b}, [sp], 32
st1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
st1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
st1 {v16.8b, v17.8b, v18.8b, v19.8b}, [sp], 32
st1 {v21.8b, v22.8b}, [sp], 16
st1 {v24.8b, v25.8b, v26.8b, v27.8b}, [sp], 32
st1 {v30.8b, v31.8b}, [sp], 16
ld1 {v14.4h}, [TMP2]
/* Load all COEF_BLOCK into NEON registers with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | v4.4h | v5.4h
* 1 | v6.4h | v7.4h
* 2 | - | -
* 3 | v10.4h | v11.4h
* 4 | - | -
* 5 | v12.4h | v13.4h
* 6 | - | -
* 7 | v16.4h | v17.4h
*/
ld1 {v4.4h, v5.4h, v6.4h, v7.4h}, [COEF_BLOCK], 32
add COEF_BLOCK, COEF_BLOCK, #16
ld1 {v10.4h, v11.4h}, [COEF_BLOCK], 16
add COEF_BLOCK, COEF_BLOCK, #16
ld1 {v12.4h, v13.4h}, [COEF_BLOCK], 16
add COEF_BLOCK, COEF_BLOCK, #16
ld1 {v16.4h, v17.4h}, [COEF_BLOCK], 16
/* Dequantize */
ld1 {v18.4h, v19.4h, v20.4h, v21.4h}, [DCT_TABLE], 32
mul v4.4h, v4.4h, v18.4h
mul v5.4h, v5.4h, v19.4h
ins v4.d[1], v5.d[0]
mul v6.4h, v6.4h, v20.4h
mul v7.4h, v7.4h, v21.4h
ins v6.d[1], v7.d[0]
add DCT_TABLE, DCT_TABLE, #16
ld1 {v24.4h, v25.4h}, [DCT_TABLE], 16
mul v10.4h, v10.4h, v24.4h
mul v11.4h, v11.4h, v25.4h
ins v10.d[1], v11.d[0]
add DCT_TABLE, DCT_TABLE, #16
ld1 {v26.4h, v27.4h}, [DCT_TABLE], 16
mul v12.4h, v12.4h, v26.4h
mul v13.4h, v13.4h, v27.4h
ins v12.d[1], v13.d[0]
add DCT_TABLE, DCT_TABLE, #16
ld1 {v30.4h, v31.4h}, [DCT_TABLE], 16
mul v16.4h, v16.4h, v30.4h
mul v17.4h, v17.4h, v31.4h
ins v16.d[1], v17.d[0]
/* Pass 1 */
#if 0
idct_helper v4.4h, v6.4h, v10.4h, v12.4h, v16.4h, 13, v4.4h, v6.4h
transpose_4x4 v4.4h, v6.4h, v8.4h, v10.4h
idct_helper v5.4h, v7.4h, v11.4h, v13.4h, v17.4h, 13, v5.4h, v7.4h
transpose_4x4 v5.4h, v7.4h, v9.4h, v11.4h
#else
smull v26.4s, v6.4h, v14.h[3]
smlal v26.4s, v10.4h, v14.h[2]
smlal v26.4s, v12.4h, v14.h[1]
smlal v26.4s, v16.4h, v14.h[0]
smull v24.4s, v7.4h, v14.h[3]
smlal v24.4s, v11.4h, v14.h[2]
smlal v24.4s, v13.4h, v14.h[1]
smlal v24.4s, v17.4h, v14.h[0]
sshll v15.4s, v4.4h, #15
sshll v30.4s, v5.4h, #15
add v20.4s, v15.4s, v26.4s
sub v15.4s, v15.4s, v26.4s
rshrn v4.4h, v20.4s, #13
rshrn v6.4h, v15.4s, #13
add v20.4s, v30.4s, v24.4s
sub v15.4s, v30.4s, v24.4s
rshrn v5.4h, v20.4s, #13
rshrn v7.4h, v15.4s, #13
ins v4.d[1], v5.d[0]
ins v6.d[1], v7.d[0]
transpose v4, v6, v3, .16b, .8h
transpose v6, v10, v3, .16b, .4s
ins v11.d[0], v10.d[1]
ins v7.d[0], v6.d[1]
#endif
/* Pass 2 */
idct_helper v4.4h, v6.4h, v10.4h, v7.4h, v11.4h, 20, v26.4h, v27.4h
/* Range limit */
movi v30.8h, #0x80
ins v26.d[1], v27.d[0]
add v26.8h, v26.8h, v30.8h
sqxtun v30.8b, v26.8h
ins v26.d[0], v30.d[0]
sqxtun v27.8b, v26.8h
/* Store results to the output buffer */
ldp TMP1, TMP2, [OUTPUT_BUF]
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
st1 {v26.b}[0], [TMP1], 1
st1 {v27.b}[4], [TMP1], 1
st1 {v26.b}[1], [TMP2], 1
st1 {v27.b}[5], [TMP2], 1
sub sp, sp, #208
ldr x15, [sp], 16
ld1 {v4.8b, v5.8b, v6.8b, v7.8b}, [sp], 32
ld1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
ld1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
ld1 {v16.8b, v17.8b, v18.8b, v19.8b}, [sp], 32
ld1 {v21.8b, v22.8b}, [sp], 16
ld1 {v24.8b, v25.8b, v26.8b, v27.8b}, [sp], 32
ld1 {v30.8b, v31.8b}, [sp], 16
blr x30
.unreq DCT_TABLE
.unreq COEF_BLOCK
.unreq OUTPUT_BUF
.unreq OUTPUT_COL
.unreq TMP1
.unreq TMP2
.purgem idct_helper
/*****************************************************************************/
/*
* jsimd_ycc_extrgb_convert_neon
* jsimd_ycc_extbgr_convert_neon
* jsimd_ycc_extrgbx_convert_neon
* jsimd_ycc_extbgrx_convert_neon
* jsimd_ycc_extxbgr_convert_neon
* jsimd_ycc_extxrgb_convert_neon
*
* Colorspace conversion YCbCr -> RGB
*/
.macro do_load size
.if \size == 8
ld1 {v4.8b}, [U], 8
ld1 {v5.8b}, [V], 8
ld1 {v0.8b}, [Y], 8
prfm pldl1keep, [U, #64]
prfm pldl1keep, [V, #64]
prfm pldl1keep, [Y, #64]
.elseif \size == 4
ld1 {v4.b}[0], [U], 1
ld1 {v4.b}[1], [U], 1
ld1 {v4.b}[2], [U], 1
ld1 {v4.b}[3], [U], 1
ld1 {v5.b}[0], [V], 1
ld1 {v5.b}[1], [V], 1
ld1 {v5.b}[2], [V], 1
ld1 {v5.b}[3], [V], 1
ld1 {v0.b}[0], [Y], 1
ld1 {v0.b}[1], [Y], 1
ld1 {v0.b}[2], [Y], 1
ld1 {v0.b}[3], [Y], 1
.elseif \size == 2
ld1 {v4.b}[4], [U], 1
ld1 {v4.b}[5], [U], 1
ld1 {v5.b}[4], [V], 1
ld1 {v5.b}[5], [V], 1
ld1 {v0.b}[4], [Y], 1
ld1 {v0.b}[5], [Y], 1
.elseif \size == 1
ld1 {v4.b}[6], [U], 1
ld1 {v5.b}[6], [V], 1
ld1 {v0.b}[6], [Y], 1
.else
.error unsupported macroblock size
.endif
.endm
.macro do_store bpp, size
.if \bpp == 24
.if \size == 8
st3 {v10.8b, v11.8b, v12.8b}, [RGB], 24
.elseif \size == 4
st3 {v10.b, v11.b, v12.b}[0], [RGB], 3
st3 {v10.b, v11.b, v12.b}[1], [RGB], 3
st3 {v10.b, v11.b, v12.b}[2], [RGB], 3
st3 {v10.b, v11.b, v12.b}[3], [RGB], 3
.elseif \size == 2
st3 {v10.b, v11.b, v12.b}[4], [RGB], 3
st3 {v10.b, v11.b, v12.b}[5], [RGB], 3
.elseif \size == 1
st3 {v10.b, v11.b, v12.b}[6], [RGB], 3
.else
.error unsupported macroblock size
.endif
.elseif \bpp == 32
.if \size == 8
st4 {v10.8b, v11.8b, v12.8b, v13.8b}, [RGB], 32
.elseif \size == 4
st4 {v10.b, v11.b, v12.b, v13.b}[0], [RGB], 4
st4 {v10.b, v11.b, v12.b, v13.b}[1], [RGB], 4
st4 {v10.b, v11.b, v12.b, v13.b}[2], [RGB], 4
st4 {v10.b, v11.b, v12.b, v13.b}[3], [RGB], 4
.elseif \size == 2
st4 {v10.b, v11.b, v12.b, v13.b}[4], [RGB], 4
st4 {v10.b, v11.b, v12.b, v13.b}[5], [RGB], 4
.elseif \size == 1
st4 {v10.b, v11.b, v12.b, v13.b}[6], [RGB], 4
.else
.error unsupported macroblock size
.endif
.elseif \bpp==16
.if \size == 8
st1 {v25.8h}, [RGB],16
.elseif \size == 4
st1 {v25.4h}, [RGB],8
.elseif \size == 2
st1 {v25.h}[4], [RGB],2
st1 {v25.h}[5], [RGB],2
.elseif \size == 1
st1 {v25.h}[6], [RGB],2
.else
.error unsupported macroblock size
.endif
.else
.error unsupported bpp
.endif
.endm
.macro generate_jsimd_ycc_rgb_convert_neon colorid, bpp, r_offs, rsize, g_offs, gsize, b_offs, bsize, defsize
/*
* 2-stage pipelined YCbCr->RGB conversion
*/
.macro do_yuv_to_rgb_stage1
uaddw v6.8h, v2.8h, v4.8b /* q3 = u - 128 */
uaddw v8.8h, v2.8h, v5.8b /* q2 = v - 128 */
smull v20.4s, v6.4h, v1.h[1] /* multiply by -11277 */
smlal v20.4s, v8.4h, v1.h[2] /* multiply by -23401 */
smull2 v22.4s, v6.8h, v1.h[1] /* multiply by -11277 */
smlal2 v22.4s, v8.8h, v1.h[2] /* multiply by -23401 */
smull v24.4s, v8.4h, v1.h[0] /* multiply by 22971 */
smull2 v26.4s, v8.8h, v1.h[0] /* multiply by 22971 */
smull v28.4s, v6.4h, v1.h[3] /* multiply by 29033 */
smull2 v30.4s, v6.8h, v1.h[3] /* multiply by 29033 */
.endm
.macro do_yuv_to_rgb_stage2
rshrn v20.4h, v20.4s, #15
rshrn2 v20.8h, v22.4s, #15
rshrn v24.4h, v24.4s, #14
rshrn2 v24.8h, v26.4s, #14
rshrn v28.4h, v28.4s, #14
rshrn2 v28.8h, v30.4s, #14
uaddw v20.8h, v20.8h, v0.8b
uaddw v24.8h, v24.8h, v0.8b
uaddw v28.8h, v28.8h, v0.8b
.if \bpp != 16
sqxtun v1\g_offs\defsize, v20.8h
sqxtun v1\r_offs\defsize, v24.8h
sqxtun v1\b_offs\defsize, v28.8h
.else
sqshlu v21.8h, v20.8h, #8
sqshlu v25.8h, v24.8h, #8
sqshlu v29.8h, v28.8h, #8
sri v25.8h, v21.8h, #5
sri v25.8h, v29.8h, #11
.endif
.endm
.macro do_yuv_to_rgb_stage2_store_load_stage1
rshrn v20.4h, v20.4s, #15
rshrn v24.4h, v24.4s, #14
rshrn v28.4h, v28.4s, #14
ld1 {v4.8b}, [U], 8
rshrn2 v20.8h, v22.4s, #15
rshrn2 v24.8h, v26.4s, #14
rshrn2 v28.8h, v30.4s, #14
ld1 {v5.8b}, [V], 8
uaddw v20.8h, v20.8h, v0.8b
uaddw v24.8h, v24.8h, v0.8b
uaddw v28.8h, v28.8h, v0.8b
.if \bpp != 16 /**************** rgb24/rgb32 *********************************/
sqxtun v1\g_offs\defsize, v20.8h
ld1 {v0.8b}, [Y], 8
sqxtun v1\r_offs\defsize, v24.8h
prfm pldl1keep, [U, #64]
prfm pldl1keep, [V, #64]
prfm pldl1keep, [Y, #64]
sqxtun v1\b_offs\defsize, v28.8h
uaddw v6.8h, v2.8h, v4.8b /* v6.16b = u - 128 */
uaddw v8.8h, v2.8h, v5.8b /* q2 = v - 128 */
smull v20.4s, v6.4h, v1.h[1] /* multiply by -11277 */
smlal v20.4s, v8.4h, v1.h[2] /* multiply by -23401 */
smull2 v22.4s, v6.8h, v1.h[1] /* multiply by -11277 */
smlal2 v22.4s, v8.8h, v1.h[2] /* multiply by -23401 */
smull v24.4s, v8.4h, v1.h[0] /* multiply by 22971 */
smull2 v26.4s, v8.8h, v1.h[0] /* multiply by 22971 */
.else /**************************** rgb565 ***********************************/
sqshlu v21.8h, v20.8h, #8
sqshlu v25.8h, v24.8h, #8
sqshlu v29.8h, v28.8h, #8
uaddw v6.8h, v2.8h, v4.8b /* v6.16b = u - 128 */
uaddw v8.8h, v2.8h, v5.8b /* q2 = v - 128 */
ld1 {v0.8b}, [Y], 8
smull v20.4s, v6.4h, v1.h[1] /* multiply by -11277 */
smlal v20.4s, v8.4h, v1.h[2] /* multiply by -23401 */
smull2 v22.4s, v6.8h, v1.h[1] /* multiply by -11277 */
smlal2 v22.4s, v8.8h, v1.h[2] /* multiply by -23401 */
sri v25.8h, v21.8h, #5
smull v24.4s, v8.4h, v1.h[0] /* multiply by 22971 */
smull2 v26.4s, v8.8h, v1.h[0] /* multiply by 22971 */
prfm pldl1keep, [U, #64]
prfm pldl1keep, [V, #64]
prfm pldl1keep, [Y, #64]
sri v25.8h, v29.8h, #11
.endif
do_store \bpp, 8
smull v28.4s, v6.4h, v1.h[3] /* multiply by 29033 */
smull2 v30.4s, v6.8h, v1.h[3] /* multiply by 29033 */
.endm
.macro do_yuv_to_rgb
do_yuv_to_rgb_stage1
do_yuv_to_rgb_stage2
.endm
/* Apple gas crashes on adrl, work around that by using adr.
* But this requires a copy of these constants for each function.
*/
.balign 16
Ljsimd_ycc_\colorid\()_neon_consts:
.short 0, 0, 0, 0
.short 22971, -11277, -23401, 29033
.short -128, -128, -128, -128
.short -128, -128, -128, -128
asm_function jsimd_ycc_\colorid\()_convert_neon
OUTPUT_WIDTH .req x0
INPUT_BUF .req x1
INPUT_ROW .req x2
OUTPUT_BUF .req x3
NUM_ROWS .req x4
INPUT_BUF0 .req x5
INPUT_BUF1 .req x6
INPUT_BUF2 .req x1
RGB .req x7
Y .req x8
U .req x9
V .req x10
N .req x15
sub sp, sp, 336
str x15, [sp], 16
/* Load constants to d1, d2, d3 (v0.4h is just used for padding) */
adr x15, Ljsimd_ycc_\colorid\()_neon_consts
/* Save NEON registers */
st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [sp], 32
st1 {v4.8b, v5.8b, v6.8b, v7.8b}, [sp], 32
st1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
st1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
st1 {v16.8b, v17.8b, v18.8b, v19.8b}, [sp], 32
st1 {v20.8b, v21.8b, v22.8b, v23.8b}, [sp], 32
st1 {v24.8b, v25.8b, v26.8b, v27.8b}, [sp], 32
st1 {v28.8b, v29.8b, v30.8b, v31.8b}, [sp], 32
ld1 {v0.4h, v1.4h}, [x15], 16
ld1 {v2.8h}, [x15]
/* Save ARM registers and handle input arguments */
/* push {x4, x5, x6, x7, x8, x9, x10, x30} */
stp x4, x5, [sp], 16
stp x6, x7, [sp], 16
stp x8, x9, [sp], 16
stp x10, x30, [sp], 16
ldr INPUT_BUF0, [INPUT_BUF]
ldr INPUT_BUF1, [INPUT_BUF, #8]
ldr INPUT_BUF2, [INPUT_BUF, #16]
.unreq INPUT_BUF
/* Initially set v10, v11.4h, v12.8b, d13 to 0xFF */
movi v10.16b, #255
movi v13.16b, #255
/* Outer loop over scanlines */
cmp NUM_ROWS, #1
b.lt 9f
0:
lsl x16, INPUT_ROW, #3
ldr Y, [INPUT_BUF0, x16]
ldr U, [INPUT_BUF1, x16]
mov N, OUTPUT_WIDTH
ldr V, [INPUT_BUF2, x16]
add INPUT_ROW, INPUT_ROW, #1
ldr RGB, [OUTPUT_BUF], #8
/* Inner loop over pixels */
subs N, N, #8
b.lt 3f
do_load 8
do_yuv_to_rgb_stage1
subs N, N, #8
b.lt 2f
1:
do_yuv_to_rgb_stage2_store_load_stage1
subs N, N, #8
b.ge 1b
2:
do_yuv_to_rgb_stage2
do_store \bpp, 8
tst N, #7
b.eq 8f
3:
tst N, #4
b.eq 3f
do_load 4
3:
tst N, #2
b.eq 4f
do_load 2
4:
tst N, #1
b.eq 5f
do_load 1
5:
do_yuv_to_rgb
tst N, #4
b.eq 6f
do_store \bpp, 4
6:
tst N, #2
b.eq 7f
do_store \bpp, 2
7:
tst N, #1
b.eq 8f
do_store \bpp, 1
8:
subs NUM_ROWS, NUM_ROWS, #1
b.gt 0b
9:
/* Restore all registers and return */
sub sp, sp, #336
ldr x15, [sp], 16
ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [sp], 32
ld1 {v4.8b, v5.8b, v6.8b, v7.8b}, [sp], 32
ld1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
ld1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
ld1 {v16.8b, v17.8b, v18.8b, v19.8b}, [sp], 32
ld1 {v20.8b, v21.8b, v22.8b, v23.8b}, [sp], 32
ld1 {v24.8b, v25.8b, v26.8b, v27.8b}, [sp], 32
ld1 {v28.8b, v29.8b, v30.8b, v31.8b}, [sp], 32
/* pop {r4, r5, r6, r7, r8, r9, r10, pc} */
ldp x4, x5, [sp], 16
ldp x6, x7, [sp], 16
ldp x8, x9, [sp], 16
ldp x10, x30, [sp], 16
br x30
.unreq OUTPUT_WIDTH
.unreq INPUT_ROW
.unreq OUTPUT_BUF
.unreq NUM_ROWS
.unreq INPUT_BUF0
.unreq INPUT_BUF1
.unreq INPUT_BUF2
.unreq RGB
.unreq Y
.unreq U
.unreq V
.unreq N
.purgem do_yuv_to_rgb
.purgem do_yuv_to_rgb_stage1
.purgem do_yuv_to_rgb_stage2
.purgem do_yuv_to_rgb_stage2_store_load_stage1
.endm
/*--------------------------------- id ----- bpp R rsize G gsize B bsize defsize */
generate_jsimd_ycc_rgb_convert_neon extrgb, 24, 0, .4h, 1, .4h, 2, .4h, .8b
generate_jsimd_ycc_rgb_convert_neon extbgr, 24, 2, .4h, 1, .4h, 0, .4h, .8b
generate_jsimd_ycc_rgb_convert_neon extrgbx, 32, 0, .4h, 1, .4h, 2, .4h, .8b
generate_jsimd_ycc_rgb_convert_neon extbgrx, 32, 2, .4h, 1, .4h, 0, .4h, .8b
generate_jsimd_ycc_rgb_convert_neon extxbgr, 32, 3, .4h, 2, .4h, 1, .4h, .8b
generate_jsimd_ycc_rgb_convert_neon extxrgb, 32, 1, .4h, 2, .4h, 3, .4h, .8b
generate_jsimd_ycc_rgb_convert_neon rgb565, 16, 0, .4h, 0, .4h, 0, .4h, .8b
.purgem do_load
.purgem do_store
|
lvonasek/3DLiveScanner | 87,641 | third_party/libjpeg-turbo/src/simd/jsimd_arm_neon.S | /*
* ARMv7 NEON optimizations for libjpeg-turbo
*
* Copyright (C) 2009-2011 Nokia Corporation and/or its subsidiary(-ies).
* All rights reserved.
* Author: Siarhei Siamashka <siarhei.siamashka@nokia.com>
* Copyright (C) 2014 Siarhei Siamashka. All Rights Reserved.
* Copyright (C) 2014 Linaro Limited. All Rights Reserved.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*/
#if defined(__linux__) && defined(__ELF__)
.section .note.GNU-stack,"",%progbits /* mark stack as non-executable */
#endif
.text
.fpu neon
.arch armv7a
.object_arch armv4
.arm
#define RESPECT_STRICT_ALIGNMENT 1
/*****************************************************************************/
/* Supplementary macro for setting function attributes */
.macro asm_function fname
#ifdef __APPLE__
.globl _\fname
_\fname:
#else
.global \fname
#ifdef __ELF__
.hidden \fname
.type \fname, %function
#endif
\fname:
#endif
.endm
/* Transpose a block of 4x4 coefficients in four 64-bit registers */
.macro transpose_4x4 x0, x1, x2, x3
vtrn.16 \x0, \x1
vtrn.16 \x2, \x3
vtrn.32 \x0, \x2
vtrn.32 \x1, \x3
.endm
#define CENTERJSAMPLE 128
/*****************************************************************************/
/*
* Perform dequantization and inverse DCT on one block of coefficients.
*
* GLOBAL(void)
* jsimd_idct_islow_neon (void * dct_table, JCOEFPTR coef_block,
* JSAMPARRAY output_buf, JDIMENSION output_col)
*/
#define FIX_0_298631336 (2446)
#define FIX_0_390180644 (3196)
#define FIX_0_541196100 (4433)
#define FIX_0_765366865 (6270)
#define FIX_0_899976223 (7373)
#define FIX_1_175875602 (9633)
#define FIX_1_501321110 (12299)
#define FIX_1_847759065 (15137)
#define FIX_1_961570560 (16069)
#define FIX_2_053119869 (16819)
#define FIX_2_562915447 (20995)
#define FIX_3_072711026 (25172)
#define FIX_1_175875602_MINUS_1_961570560 (FIX_1_175875602 - FIX_1_961570560)
#define FIX_1_175875602_MINUS_0_390180644 (FIX_1_175875602 - FIX_0_390180644)
#define FIX_0_541196100_MINUS_1_847759065 (FIX_0_541196100 - FIX_1_847759065)
#define FIX_3_072711026_MINUS_2_562915447 (FIX_3_072711026 - FIX_2_562915447)
#define FIX_0_298631336_MINUS_0_899976223 (FIX_0_298631336 - FIX_0_899976223)
#define FIX_1_501321110_MINUS_0_899976223 (FIX_1_501321110 - FIX_0_899976223)
#define FIX_2_053119869_MINUS_2_562915447 (FIX_2_053119869 - FIX_2_562915447)
#define FIX_0_541196100_PLUS_0_765366865 (FIX_0_541196100 + FIX_0_765366865)
/*
* Reference SIMD-friendly 1-D ISLOW iDCT C implementation.
* Uses some ideas from the comments in 'simd/jiss2int-64.asm'
*/
#define REF_1D_IDCT(xrow0, xrow1, xrow2, xrow3, xrow4, xrow5, xrow6, xrow7) \
{ \
DCTELEM row0, row1, row2, row3, row4, row5, row6, row7; \
INT32 q1, q2, q3, q4, q5, q6, q7; \
INT32 tmp11_plus_tmp2, tmp11_minus_tmp2; \
\
/* 1-D iDCT input data */ \
row0 = xrow0; \
row1 = xrow1; \
row2 = xrow2; \
row3 = xrow3; \
row4 = xrow4; \
row5 = xrow5; \
row6 = xrow6; \
row7 = xrow7; \
\
q5 = row7 + row3; \
q4 = row5 + row1; \
q6 = MULTIPLY(q5, FIX_1_175875602_MINUS_1_961570560) + \
MULTIPLY(q4, FIX_1_175875602); \
q7 = MULTIPLY(q5, FIX_1_175875602) + \
MULTIPLY(q4, FIX_1_175875602_MINUS_0_390180644); \
q2 = MULTIPLY(row2, FIX_0_541196100) + \
MULTIPLY(row6, FIX_0_541196100_MINUS_1_847759065); \
q4 = q6; \
q3 = ((INT32) row0 - (INT32) row4) << 13; \
q6 += MULTIPLY(row5, -FIX_2_562915447) + \
MULTIPLY(row3, FIX_3_072711026_MINUS_2_562915447); \
/* now we can use q1 (reloadable constants have been used up) */ \
q1 = q3 + q2; \
q4 += MULTIPLY(row7, FIX_0_298631336_MINUS_0_899976223) + \
MULTIPLY(row1, -FIX_0_899976223); \
q5 = q7; \
q1 = q1 + q6; \
q7 += MULTIPLY(row7, -FIX_0_899976223) + \
MULTIPLY(row1, FIX_1_501321110_MINUS_0_899976223); \
\
/* (tmp11 + tmp2) has been calculated (out_row1 before descale) */ \
tmp11_plus_tmp2 = q1; \
row1 = 0; \
\
q1 = q1 - q6; \
q5 += MULTIPLY(row5, FIX_2_053119869_MINUS_2_562915447) + \
MULTIPLY(row3, -FIX_2_562915447); \
q1 = q1 - q6; \
q6 = MULTIPLY(row2, FIX_0_541196100_PLUS_0_765366865) + \
MULTIPLY(row6, FIX_0_541196100); \
q3 = q3 - q2; \
\
/* (tmp11 - tmp2) has been calculated (out_row6 before descale) */ \
tmp11_minus_tmp2 = q1; \
\
q1 = ((INT32) row0 + (INT32) row4) << 13; \
q2 = q1 + q6; \
q1 = q1 - q6; \
\
/* pick up the results */ \
tmp0 = q4; \
tmp1 = q5; \
tmp2 = (tmp11_plus_tmp2 - tmp11_minus_tmp2) / 2; \
tmp3 = q7; \
tmp10 = q2; \
tmp11 = (tmp11_plus_tmp2 + tmp11_minus_tmp2) / 2; \
tmp12 = q3; \
tmp13 = q1; \
}
#define XFIX_0_899976223 d0[0]
#define XFIX_0_541196100 d0[1]
#define XFIX_2_562915447 d0[2]
#define XFIX_0_298631336_MINUS_0_899976223 d0[3]
#define XFIX_1_501321110_MINUS_0_899976223 d1[0]
#define XFIX_2_053119869_MINUS_2_562915447 d1[1]
#define XFIX_0_541196100_PLUS_0_765366865 d1[2]
#define XFIX_1_175875602 d1[3]
#define XFIX_1_175875602_MINUS_0_390180644 d2[0]
#define XFIX_0_541196100_MINUS_1_847759065 d2[1]
#define XFIX_3_072711026_MINUS_2_562915447 d2[2]
#define XFIX_1_175875602_MINUS_1_961570560 d2[3]
.balign 16
jsimd_idct_islow_neon_consts:
.short FIX_0_899976223 /* d0[0] */
.short FIX_0_541196100 /* d0[1] */
.short FIX_2_562915447 /* d0[2] */
.short FIX_0_298631336_MINUS_0_899976223 /* d0[3] */
.short FIX_1_501321110_MINUS_0_899976223 /* d1[0] */
.short FIX_2_053119869_MINUS_2_562915447 /* d1[1] */
.short FIX_0_541196100_PLUS_0_765366865 /* d1[2] */
.short FIX_1_175875602 /* d1[3] */
/* reloadable constants */
.short FIX_1_175875602_MINUS_0_390180644 /* d2[0] */
.short FIX_0_541196100_MINUS_1_847759065 /* d2[1] */
.short FIX_3_072711026_MINUS_2_562915447 /* d2[2] */
.short FIX_1_175875602_MINUS_1_961570560 /* d2[3] */
asm_function jsimd_idct_islow_neon
DCT_TABLE .req r0
COEF_BLOCK .req r1
OUTPUT_BUF .req r2
OUTPUT_COL .req r3
TMP1 .req r0
TMP2 .req r1
TMP3 .req r2
TMP4 .req ip
ROW0L .req d16
ROW0R .req d17
ROW1L .req d18
ROW1R .req d19
ROW2L .req d20
ROW2R .req d21
ROW3L .req d22
ROW3R .req d23
ROW4L .req d24
ROW4R .req d25
ROW5L .req d26
ROW5R .req d27
ROW6L .req d28
ROW6R .req d29
ROW7L .req d30
ROW7R .req d31
/* Load and dequantize coefficients into NEON registers
* with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | d16 | d17 ( q8 )
* 1 | d18 | d19 ( q9 )
* 2 | d20 | d21 ( q10 )
* 3 | d22 | d23 ( q11 )
* 4 | d24 | d25 ( q12 )
* 5 | d26 | d27 ( q13 )
* 6 | d28 | d29 ( q14 )
* 7 | d30 | d31 ( q15 )
*/
adr ip, jsimd_idct_islow_neon_consts
vld1.16 {d16, d17, d18, d19}, [COEF_BLOCK, :128]!
vld1.16 {d0, d1, d2, d3}, [DCT_TABLE, :128]!
vld1.16 {d20, d21, d22, d23}, [COEF_BLOCK, :128]!
vmul.s16 q8, q8, q0
vld1.16 {d4, d5, d6, d7}, [DCT_TABLE, :128]!
vmul.s16 q9, q9, q1
vld1.16 {d24, d25, d26, d27}, [COEF_BLOCK, :128]!
vmul.s16 q10, q10, q2
vld1.16 {d0, d1, d2, d3}, [DCT_TABLE, :128]!
vmul.s16 q11, q11, q3
vld1.16 {d28, d29, d30, d31}, [COEF_BLOCK, :128]
vmul.s16 q12, q12, q0
vld1.16 {d4, d5, d6, d7}, [DCT_TABLE, :128]!
vmul.s16 q14, q14, q2
vmul.s16 q13, q13, q1
vld1.16 {d0, d1, d2, d3}, [ip, :128] /* load constants */
add ip, ip, #16
vmul.s16 q15, q15, q3
vpush {d8-d15} /* save NEON registers */
/* 1-D IDCT, pass 1, left 4x8 half */
vadd.s16 d4, ROW7L, ROW3L
vadd.s16 d5, ROW5L, ROW1L
vmull.s16 q6, d4, XFIX_1_175875602_MINUS_1_961570560
vmlal.s16 q6, d5, XFIX_1_175875602
vmull.s16 q7, d4, XFIX_1_175875602
/* Check for the zero coefficients in the right 4x8 half */
push {r4, r5}
vmlal.s16 q7, d5, XFIX_1_175875602_MINUS_0_390180644
vsubl.s16 q3, ROW0L, ROW4L
ldrd r4, [COEF_BLOCK, #(-96 + 2 * (4 + 1 * 8))]
vmull.s16 q2, ROW2L, XFIX_0_541196100
vmlal.s16 q2, ROW6L, XFIX_0_541196100_MINUS_1_847759065
orr r0, r4, r5
vmov q4, q6
vmlsl.s16 q6, ROW5L, XFIX_2_562915447
ldrd r4, [COEF_BLOCK, #(-96 + 2 * (4 + 2 * 8))]
vmlal.s16 q6, ROW3L, XFIX_3_072711026_MINUS_2_562915447
vshl.s32 q3, q3, #13
orr r0, r0, r4
vmlsl.s16 q4, ROW1L, XFIX_0_899976223
orr r0, r0, r5
vadd.s32 q1, q3, q2
ldrd r4, [COEF_BLOCK, #(-96 + 2 * (4 + 3 * 8))]
vmov q5, q7
vadd.s32 q1, q1, q6
orr r0, r0, r4
vmlsl.s16 q7, ROW7L, XFIX_0_899976223
orr r0, r0, r5
vmlal.s16 q7, ROW1L, XFIX_1_501321110_MINUS_0_899976223
vrshrn.s32 ROW1L, q1, #11
ldrd r4, [COEF_BLOCK, #(-96 + 2 * (4 + 4 * 8))]
vsub.s32 q1, q1, q6
vmlal.s16 q5, ROW5L, XFIX_2_053119869_MINUS_2_562915447
orr r0, r0, r4
vmlsl.s16 q5, ROW3L, XFIX_2_562915447
orr r0, r0, r5
vsub.s32 q1, q1, q6
vmull.s16 q6, ROW2L, XFIX_0_541196100_PLUS_0_765366865
ldrd r4, [COEF_BLOCK, #(-96 + 2 * (4 + 5 * 8))]
vmlal.s16 q6, ROW6L, XFIX_0_541196100
vsub.s32 q3, q3, q2
orr r0, r0, r4
vrshrn.s32 ROW6L, q1, #11
orr r0, r0, r5
vadd.s32 q1, q3, q5
ldrd r4, [COEF_BLOCK, #(-96 + 2 * (4 + 6 * 8))]
vsub.s32 q3, q3, q5
vaddl.s16 q5, ROW0L, ROW4L
orr r0, r0, r4
vrshrn.s32 ROW2L, q1, #11
orr r0, r0, r5
vrshrn.s32 ROW5L, q3, #11
ldrd r4, [COEF_BLOCK, #(-96 + 2 * (4 + 7 * 8))]
vshl.s32 q5, q5, #13
vmlal.s16 q4, ROW7L, XFIX_0_298631336_MINUS_0_899976223
orr r0, r0, r4
vadd.s32 q2, q5, q6
orrs r0, r0, r5
vsub.s32 q1, q5, q6
vadd.s32 q6, q2, q7
ldrd r4, [COEF_BLOCK, #(-96 + 2 * (4 + 0 * 8))]
vsub.s32 q2, q2, q7
vadd.s32 q5, q1, q4
orr r0, r4, r5
vsub.s32 q3, q1, q4
pop {r4, r5}
vrshrn.s32 ROW7L, q2, #11
vrshrn.s32 ROW3L, q5, #11
vrshrn.s32 ROW0L, q6, #11
vrshrn.s32 ROW4L, q3, #11
beq 3f /* Go to do some special handling for the sparse right 4x8 half */
/* 1-D IDCT, pass 1, right 4x8 half */
vld1.s16 {d2}, [ip, :64] /* reload constants */
vadd.s16 d10, ROW7R, ROW3R
vadd.s16 d8, ROW5R, ROW1R
/* Transpose left 4x8 half */
vtrn.16 ROW6L, ROW7L
vmull.s16 q6, d10, XFIX_1_175875602_MINUS_1_961570560
vmlal.s16 q6, d8, XFIX_1_175875602
vtrn.16 ROW2L, ROW3L
vmull.s16 q7, d10, XFIX_1_175875602
vmlal.s16 q7, d8, XFIX_1_175875602_MINUS_0_390180644
vtrn.16 ROW0L, ROW1L
vsubl.s16 q3, ROW0R, ROW4R
vmull.s16 q2, ROW2R, XFIX_0_541196100
vmlal.s16 q2, ROW6R, XFIX_0_541196100_MINUS_1_847759065
vtrn.16 ROW4L, ROW5L
vmov q4, q6
vmlsl.s16 q6, ROW5R, XFIX_2_562915447
vmlal.s16 q6, ROW3R, XFIX_3_072711026_MINUS_2_562915447
vtrn.32 ROW1L, ROW3L
vshl.s32 q3, q3, #13
vmlsl.s16 q4, ROW1R, XFIX_0_899976223
vtrn.32 ROW4L, ROW6L
vadd.s32 q1, q3, q2
vmov q5, q7
vadd.s32 q1, q1, q6
vtrn.32 ROW0L, ROW2L
vmlsl.s16 q7, ROW7R, XFIX_0_899976223
vmlal.s16 q7, ROW1R, XFIX_1_501321110_MINUS_0_899976223
vrshrn.s32 ROW1R, q1, #11
vtrn.32 ROW5L, ROW7L
vsub.s32 q1, q1, q6
vmlal.s16 q5, ROW5R, XFIX_2_053119869_MINUS_2_562915447
vmlsl.s16 q5, ROW3R, XFIX_2_562915447
vsub.s32 q1, q1, q6
vmull.s16 q6, ROW2R, XFIX_0_541196100_PLUS_0_765366865
vmlal.s16 q6, ROW6R, XFIX_0_541196100
vsub.s32 q3, q3, q2
vrshrn.s32 ROW6R, q1, #11
vadd.s32 q1, q3, q5
vsub.s32 q3, q3, q5
vaddl.s16 q5, ROW0R, ROW4R
vrshrn.s32 ROW2R, q1, #11
vrshrn.s32 ROW5R, q3, #11
vshl.s32 q5, q5, #13
vmlal.s16 q4, ROW7R, XFIX_0_298631336_MINUS_0_899976223
vadd.s32 q2, q5, q6
vsub.s32 q1, q5, q6
vadd.s32 q6, q2, q7
vsub.s32 q2, q2, q7
vadd.s32 q5, q1, q4
vsub.s32 q3, q1, q4
vrshrn.s32 ROW7R, q2, #11
vrshrn.s32 ROW3R, q5, #11
vrshrn.s32 ROW0R, q6, #11
vrshrn.s32 ROW4R, q3, #11
/* Transpose right 4x8 half */
vtrn.16 ROW6R, ROW7R
vtrn.16 ROW2R, ROW3R
vtrn.16 ROW0R, ROW1R
vtrn.16 ROW4R, ROW5R
vtrn.32 ROW1R, ROW3R
vtrn.32 ROW4R, ROW6R
vtrn.32 ROW0R, ROW2R
vtrn.32 ROW5R, ROW7R
1: /* 1-D IDCT, pass 2 (normal variant), left 4x8 half */
vld1.s16 {d2}, [ip, :64] /* reload constants */
vmull.s16 q6, ROW1R, XFIX_1_175875602 /* ROW5L <-> ROW1R */
vmlal.s16 q6, ROW1L, XFIX_1_175875602
vmlal.s16 q6, ROW3R, XFIX_1_175875602_MINUS_1_961570560 /* ROW7L <-> ROW3R */
vmlal.s16 q6, ROW3L, XFIX_1_175875602_MINUS_1_961570560
vmull.s16 q7, ROW3R, XFIX_1_175875602 /* ROW7L <-> ROW3R */
vmlal.s16 q7, ROW3L, XFIX_1_175875602
vmlal.s16 q7, ROW1R, XFIX_1_175875602_MINUS_0_390180644 /* ROW5L <-> ROW1R */
vmlal.s16 q7, ROW1L, XFIX_1_175875602_MINUS_0_390180644
vsubl.s16 q3, ROW0L, ROW0R /* ROW4L <-> ROW0R */
vmull.s16 q2, ROW2L, XFIX_0_541196100
vmlal.s16 q2, ROW2R, XFIX_0_541196100_MINUS_1_847759065 /* ROW6L <-> ROW2R */
vmov q4, q6
vmlsl.s16 q6, ROW1R, XFIX_2_562915447 /* ROW5L <-> ROW1R */
vmlal.s16 q6, ROW3L, XFIX_3_072711026_MINUS_2_562915447
vshl.s32 q3, q3, #13
vmlsl.s16 q4, ROW1L, XFIX_0_899976223
vadd.s32 q1, q3, q2
vmov q5, q7
vadd.s32 q1, q1, q6
vmlsl.s16 q7, ROW3R, XFIX_0_899976223 /* ROW7L <-> ROW3R */
vmlal.s16 q7, ROW1L, XFIX_1_501321110_MINUS_0_899976223
vshrn.s32 ROW1L, q1, #16
vsub.s32 q1, q1, q6
vmlal.s16 q5, ROW1R, XFIX_2_053119869_MINUS_2_562915447 /* ROW5L <-> ROW1R */
vmlsl.s16 q5, ROW3L, XFIX_2_562915447
vsub.s32 q1, q1, q6
vmull.s16 q6, ROW2L, XFIX_0_541196100_PLUS_0_765366865
vmlal.s16 q6, ROW2R, XFIX_0_541196100 /* ROW6L <-> ROW2R */
vsub.s32 q3, q3, q2
vshrn.s32 ROW2R, q1, #16 /* ROW6L <-> ROW2R */
vadd.s32 q1, q3, q5
vsub.s32 q3, q3, q5
vaddl.s16 q5, ROW0L, ROW0R /* ROW4L <-> ROW0R */
vshrn.s32 ROW2L, q1, #16
vshrn.s32 ROW1R, q3, #16 /* ROW5L <-> ROW1R */
vshl.s32 q5, q5, #13
vmlal.s16 q4, ROW3R, XFIX_0_298631336_MINUS_0_899976223 /* ROW7L <-> ROW3R */
vadd.s32 q2, q5, q6
vsub.s32 q1, q5, q6
vadd.s32 q6, q2, q7
vsub.s32 q2, q2, q7
vadd.s32 q5, q1, q4
vsub.s32 q3, q1, q4
vshrn.s32 ROW3R, q2, #16 /* ROW7L <-> ROW3R */
vshrn.s32 ROW3L, q5, #16
vshrn.s32 ROW0L, q6, #16
vshrn.s32 ROW0R, q3, #16 /* ROW4L <-> ROW0R */
/* 1-D IDCT, pass 2, right 4x8 half */
vld1.s16 {d2}, [ip, :64] /* reload constants */
vmull.s16 q6, ROW5R, XFIX_1_175875602
vmlal.s16 q6, ROW5L, XFIX_1_175875602 /* ROW5L <-> ROW1R */
vmlal.s16 q6, ROW7R, XFIX_1_175875602_MINUS_1_961570560
vmlal.s16 q6, ROW7L, XFIX_1_175875602_MINUS_1_961570560 /* ROW7L <-> ROW3R */
vmull.s16 q7, ROW7R, XFIX_1_175875602
vmlal.s16 q7, ROW7L, XFIX_1_175875602 /* ROW7L <-> ROW3R */
vmlal.s16 q7, ROW5R, XFIX_1_175875602_MINUS_0_390180644
vmlal.s16 q7, ROW5L, XFIX_1_175875602_MINUS_0_390180644 /* ROW5L <-> ROW1R */
vsubl.s16 q3, ROW4L, ROW4R /* ROW4L <-> ROW0R */
vmull.s16 q2, ROW6L, XFIX_0_541196100 /* ROW6L <-> ROW2R */
vmlal.s16 q2, ROW6R, XFIX_0_541196100_MINUS_1_847759065
vmov q4, q6
vmlsl.s16 q6, ROW5R, XFIX_2_562915447
vmlal.s16 q6, ROW7L, XFIX_3_072711026_MINUS_2_562915447 /* ROW7L <-> ROW3R */
vshl.s32 q3, q3, #13
vmlsl.s16 q4, ROW5L, XFIX_0_899976223 /* ROW5L <-> ROW1R */
vadd.s32 q1, q3, q2
vmov q5, q7
vadd.s32 q1, q1, q6
vmlsl.s16 q7, ROW7R, XFIX_0_899976223
vmlal.s16 q7, ROW5L, XFIX_1_501321110_MINUS_0_899976223 /* ROW5L <-> ROW1R */
vshrn.s32 ROW5L, q1, #16 /* ROW5L <-> ROW1R */
vsub.s32 q1, q1, q6
vmlal.s16 q5, ROW5R, XFIX_2_053119869_MINUS_2_562915447
vmlsl.s16 q5, ROW7L, XFIX_2_562915447 /* ROW7L <-> ROW3R */
vsub.s32 q1, q1, q6
vmull.s16 q6, ROW6L, XFIX_0_541196100_PLUS_0_765366865 /* ROW6L <-> ROW2R */
vmlal.s16 q6, ROW6R, XFIX_0_541196100
vsub.s32 q3, q3, q2
vshrn.s32 ROW6R, q1, #16
vadd.s32 q1, q3, q5
vsub.s32 q3, q3, q5
vaddl.s16 q5, ROW4L, ROW4R /* ROW4L <-> ROW0R */
vshrn.s32 ROW6L, q1, #16 /* ROW6L <-> ROW2R */
vshrn.s32 ROW5R, q3, #16
vshl.s32 q5, q5, #13
vmlal.s16 q4, ROW7R, XFIX_0_298631336_MINUS_0_899976223
vadd.s32 q2, q5, q6
vsub.s32 q1, q5, q6
vadd.s32 q6, q2, q7
vsub.s32 q2, q2, q7
vadd.s32 q5, q1, q4
vsub.s32 q3, q1, q4
vshrn.s32 ROW7R, q2, #16
vshrn.s32 ROW7L, q5, #16 /* ROW7L <-> ROW3R */
vshrn.s32 ROW4L, q6, #16 /* ROW4L <-> ROW0R */
vshrn.s32 ROW4R, q3, #16
2: /* Descale to 8-bit and range limit */
vqrshrn.s16 d16, q8, #2
vqrshrn.s16 d17, q9, #2
vqrshrn.s16 d18, q10, #2
vqrshrn.s16 d19, q11, #2
vpop {d8-d15} /* restore NEON registers */
vqrshrn.s16 d20, q12, #2
/* Transpose the final 8-bit samples and do signed->unsigned conversion */
vtrn.16 q8, q9
vqrshrn.s16 d21, q13, #2
vqrshrn.s16 d22, q14, #2
vmov.u8 q0, #(CENTERJSAMPLE)
vqrshrn.s16 d23, q15, #2
vtrn.8 d16, d17
vtrn.8 d18, d19
vadd.u8 q8, q8, q0
vadd.u8 q9, q9, q0
vtrn.16 q10, q11
/* Store results to the output buffer */
ldmia OUTPUT_BUF!, {TMP1, TMP2}
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
vst1.8 {d16}, [TMP1]
vtrn.8 d20, d21
vst1.8 {d17}, [TMP2]
ldmia OUTPUT_BUF!, {TMP1, TMP2}
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
vst1.8 {d18}, [TMP1]
vadd.u8 q10, q10, q0
vst1.8 {d19}, [TMP2]
ldmia OUTPUT_BUF, {TMP1, TMP2, TMP3, TMP4}
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
add TMP3, TMP3, OUTPUT_COL
add TMP4, TMP4, OUTPUT_COL
vtrn.8 d22, d23
vst1.8 {d20}, [TMP1]
vadd.u8 q11, q11, q0
vst1.8 {d21}, [TMP2]
vst1.8 {d22}, [TMP3]
vst1.8 {d23}, [TMP4]
bx lr
3: /* Left 4x8 half is done, right 4x8 half contains mostly zeros */
/* Transpose left 4x8 half */
vtrn.16 ROW6L, ROW7L
vtrn.16 ROW2L, ROW3L
vtrn.16 ROW0L, ROW1L
vtrn.16 ROW4L, ROW5L
vshl.s16 ROW0R, ROW0R, #2 /* PASS1_BITS */
vtrn.32 ROW1L, ROW3L
vtrn.32 ROW4L, ROW6L
vtrn.32 ROW0L, ROW2L
vtrn.32 ROW5L, ROW7L
cmp r0, #0
beq 4f /* Right 4x8 half has all zeros, go to 'sparse' second pass */
/* Only row 0 is non-zero for the right 4x8 half */
vdup.s16 ROW1R, ROW0R[1]
vdup.s16 ROW2R, ROW0R[2]
vdup.s16 ROW3R, ROW0R[3]
vdup.s16 ROW4R, ROW0R[0]
vdup.s16 ROW5R, ROW0R[1]
vdup.s16 ROW6R, ROW0R[2]
vdup.s16 ROW7R, ROW0R[3]
vdup.s16 ROW0R, ROW0R[0]
b 1b /* Go to 'normal' second pass */
4: /* 1-D IDCT, pass 2 (sparse variant with zero rows 4-7), left 4x8 half */
vld1.s16 {d2}, [ip, :64] /* reload constants */
vmull.s16 q6, ROW1L, XFIX_1_175875602
vmlal.s16 q6, ROW3L, XFIX_1_175875602_MINUS_1_961570560
vmull.s16 q7, ROW3L, XFIX_1_175875602
vmlal.s16 q7, ROW1L, XFIX_1_175875602_MINUS_0_390180644
vmull.s16 q2, ROW2L, XFIX_0_541196100
vshll.s16 q3, ROW0L, #13
vmov q4, q6
vmlal.s16 q6, ROW3L, XFIX_3_072711026_MINUS_2_562915447
vmlsl.s16 q4, ROW1L, XFIX_0_899976223
vadd.s32 q1, q3, q2
vmov q5, q7
vmlal.s16 q7, ROW1L, XFIX_1_501321110_MINUS_0_899976223
vadd.s32 q1, q1, q6
vadd.s32 q6, q6, q6
vmlsl.s16 q5, ROW3L, XFIX_2_562915447
vshrn.s32 ROW1L, q1, #16
vsub.s32 q1, q1, q6
vmull.s16 q6, ROW2L, XFIX_0_541196100_PLUS_0_765366865
vsub.s32 q3, q3, q2
vshrn.s32 ROW2R, q1, #16 /* ROW6L <-> ROW2R */
vadd.s32 q1, q3, q5
vsub.s32 q3, q3, q5
vshll.s16 q5, ROW0L, #13
vshrn.s32 ROW2L, q1, #16
vshrn.s32 ROW1R, q3, #16 /* ROW5L <-> ROW1R */
vadd.s32 q2, q5, q6
vsub.s32 q1, q5, q6
vadd.s32 q6, q2, q7
vsub.s32 q2, q2, q7
vadd.s32 q5, q1, q4
vsub.s32 q3, q1, q4
vshrn.s32 ROW3R, q2, #16 /* ROW7L <-> ROW3R */
vshrn.s32 ROW3L, q5, #16
vshrn.s32 ROW0L, q6, #16
vshrn.s32 ROW0R, q3, #16 /* ROW4L <-> ROW0R */
/* 1-D IDCT, pass 2 (sparse variant with zero rows 4-7), right 4x8 half */
vld1.s16 {d2}, [ip, :64] /* reload constants */
vmull.s16 q6, ROW5L, XFIX_1_175875602
vmlal.s16 q6, ROW7L, XFIX_1_175875602_MINUS_1_961570560
vmull.s16 q7, ROW7L, XFIX_1_175875602
vmlal.s16 q7, ROW5L, XFIX_1_175875602_MINUS_0_390180644
vmull.s16 q2, ROW6L, XFIX_0_541196100
vshll.s16 q3, ROW4L, #13
vmov q4, q6
vmlal.s16 q6, ROW7L, XFIX_3_072711026_MINUS_2_562915447
vmlsl.s16 q4, ROW5L, XFIX_0_899976223
vadd.s32 q1, q3, q2
vmov q5, q7
vmlal.s16 q7, ROW5L, XFIX_1_501321110_MINUS_0_899976223
vadd.s32 q1, q1, q6
vadd.s32 q6, q6, q6
vmlsl.s16 q5, ROW7L, XFIX_2_562915447
vshrn.s32 ROW5L, q1, #16 /* ROW5L <-> ROW1R */
vsub.s32 q1, q1, q6
vmull.s16 q6, ROW6L, XFIX_0_541196100_PLUS_0_765366865
vsub.s32 q3, q3, q2
vshrn.s32 ROW6R, q1, #16
vadd.s32 q1, q3, q5
vsub.s32 q3, q3, q5
vshll.s16 q5, ROW4L, #13
vshrn.s32 ROW6L, q1, #16 /* ROW6L <-> ROW2R */
vshrn.s32 ROW5R, q3, #16
vadd.s32 q2, q5, q6
vsub.s32 q1, q5, q6
vadd.s32 q6, q2, q7
vsub.s32 q2, q2, q7
vadd.s32 q5, q1, q4
vsub.s32 q3, q1, q4
vshrn.s32 ROW7R, q2, #16
vshrn.s32 ROW7L, q5, #16 /* ROW7L <-> ROW3R */
vshrn.s32 ROW4L, q6, #16 /* ROW4L <-> ROW0R */
vshrn.s32 ROW4R, q3, #16
b 2b /* Go to epilogue */
.unreq DCT_TABLE
.unreq COEF_BLOCK
.unreq OUTPUT_BUF
.unreq OUTPUT_COL
.unreq TMP1
.unreq TMP2
.unreq TMP3
.unreq TMP4
.unreq ROW0L
.unreq ROW0R
.unreq ROW1L
.unreq ROW1R
.unreq ROW2L
.unreq ROW2R
.unreq ROW3L
.unreq ROW3R
.unreq ROW4L
.unreq ROW4R
.unreq ROW5L
.unreq ROW5R
.unreq ROW6L
.unreq ROW6R
.unreq ROW7L
.unreq ROW7R
/*****************************************************************************/
/*
* jsimd_idct_ifast_neon
*
* This function contains a fast, not so accurate integer implementation of
* the inverse DCT (Discrete Cosine Transform). It uses the same calculations
* and produces exactly the same output as IJG's original 'jpeg_idct_ifast'
* function from jidctfst.c
*
* Normally 1-D AAN DCT needs 5 multiplications and 29 additions.
* But in ARM NEON case some extra additions are required because VQDMULH
* instruction can't handle the constants larger than 1. So the expressions
* like "x * 1.082392200" have to be converted to "x * 0.082392200 + x",
* which introduces an extra addition. Overall, there are 6 extra additions
* per 1-D IDCT pass, totalling to 5 VQDMULH and 35 VADD/VSUB instructions.
*/
#define XFIX_1_082392200 d0[0]
#define XFIX_1_414213562 d0[1]
#define XFIX_1_847759065 d0[2]
#define XFIX_2_613125930 d0[3]
.balign 16
jsimd_idct_ifast_neon_consts:
.short (277 * 128 - 256 * 128) /* XFIX_1_082392200 */
.short (362 * 128 - 256 * 128) /* XFIX_1_414213562 */
.short (473 * 128 - 256 * 128) /* XFIX_1_847759065 */
.short (669 * 128 - 512 * 128) /* XFIX_2_613125930 */
asm_function jsimd_idct_ifast_neon
DCT_TABLE .req r0
COEF_BLOCK .req r1
OUTPUT_BUF .req r2
OUTPUT_COL .req r3
TMP1 .req r0
TMP2 .req r1
TMP3 .req r2
TMP4 .req ip
/* Load and dequantize coefficients into NEON registers
* with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | d16 | d17 ( q8 )
* 1 | d18 | d19 ( q9 )
* 2 | d20 | d21 ( q10 )
* 3 | d22 | d23 ( q11 )
* 4 | d24 | d25 ( q12 )
* 5 | d26 | d27 ( q13 )
* 6 | d28 | d29 ( q14 )
* 7 | d30 | d31 ( q15 )
*/
adr ip, jsimd_idct_ifast_neon_consts
vld1.16 {d16, d17, d18, d19}, [COEF_BLOCK, :128]!
vld1.16 {d0, d1, d2, d3}, [DCT_TABLE, :128]!
vld1.16 {d20, d21, d22, d23}, [COEF_BLOCK, :128]!
vmul.s16 q8, q8, q0
vld1.16 {d4, d5, d6, d7}, [DCT_TABLE, :128]!
vmul.s16 q9, q9, q1
vld1.16 {d24, d25, d26, d27}, [COEF_BLOCK, :128]!
vmul.s16 q10, q10, q2
vld1.16 {d0, d1, d2, d3}, [DCT_TABLE, :128]!
vmul.s16 q11, q11, q3
vld1.16 {d28, d29, d30, d31}, [COEF_BLOCK, :128]
vmul.s16 q12, q12, q0
vld1.16 {d4, d5, d6, d7}, [DCT_TABLE, :128]!
vmul.s16 q14, q14, q2
vmul.s16 q13, q13, q1
vld1.16 {d0}, [ip, :64] /* load constants */
vmul.s16 q15, q15, q3
vpush {d8-d13} /* save NEON registers */
/* 1-D IDCT, pass 1 */
vsub.s16 q2, q10, q14
vadd.s16 q14, q10, q14
vsub.s16 q1, q11, q13
vadd.s16 q13, q11, q13
vsub.s16 q5, q9, q15
vadd.s16 q15, q9, q15
vqdmulh.s16 q4, q2, XFIX_1_414213562
vqdmulh.s16 q6, q1, XFIX_2_613125930
vadd.s16 q3, q1, q1
vsub.s16 q1, q5, q1
vadd.s16 q10, q2, q4
vqdmulh.s16 q4, q1, XFIX_1_847759065
vsub.s16 q2, q15, q13
vadd.s16 q3, q3, q6
vqdmulh.s16 q6, q2, XFIX_1_414213562
vadd.s16 q1, q1, q4
vqdmulh.s16 q4, q5, XFIX_1_082392200
vsub.s16 q10, q10, q14
vadd.s16 q2, q2, q6
vsub.s16 q6, q8, q12
vadd.s16 q12, q8, q12
vadd.s16 q9, q5, q4
vadd.s16 q5, q6, q10
vsub.s16 q10, q6, q10
vadd.s16 q6, q15, q13
vadd.s16 q8, q12, q14
vsub.s16 q3, q6, q3
vsub.s16 q12, q12, q14
vsub.s16 q3, q3, q1
vsub.s16 q1, q9, q1
vadd.s16 q2, q3, q2
vsub.s16 q15, q8, q6
vadd.s16 q1, q1, q2
vadd.s16 q8, q8, q6
vadd.s16 q14, q5, q3
vsub.s16 q9, q5, q3
vsub.s16 q13, q10, q2
vadd.s16 q10, q10, q2
/* Transpose */
vtrn.16 q8, q9
vsub.s16 q11, q12, q1
vtrn.16 q14, q15
vadd.s16 q12, q12, q1
vtrn.16 q10, q11
vtrn.16 q12, q13
vtrn.32 q9, q11
vtrn.32 q12, q14
vtrn.32 q8, q10
vtrn.32 q13, q15
vswp d28, d21
vswp d26, d19
/* 1-D IDCT, pass 2 */
vsub.s16 q2, q10, q14
vswp d30, d23
vadd.s16 q14, q10, q14
vswp d24, d17
vsub.s16 q1, q11, q13
vadd.s16 q13, q11, q13
vsub.s16 q5, q9, q15
vadd.s16 q15, q9, q15
vqdmulh.s16 q4, q2, XFIX_1_414213562
vqdmulh.s16 q6, q1, XFIX_2_613125930
vadd.s16 q3, q1, q1
vsub.s16 q1, q5, q1
vadd.s16 q10, q2, q4
vqdmulh.s16 q4, q1, XFIX_1_847759065
vsub.s16 q2, q15, q13
vadd.s16 q3, q3, q6
vqdmulh.s16 q6, q2, XFIX_1_414213562
vadd.s16 q1, q1, q4
vqdmulh.s16 q4, q5, XFIX_1_082392200
vsub.s16 q10, q10, q14
vadd.s16 q2, q2, q6
vsub.s16 q6, q8, q12
vadd.s16 q12, q8, q12
vadd.s16 q9, q5, q4
vadd.s16 q5, q6, q10
vsub.s16 q10, q6, q10
vadd.s16 q6, q15, q13
vadd.s16 q8, q12, q14
vsub.s16 q3, q6, q3
vsub.s16 q12, q12, q14
vsub.s16 q3, q3, q1
vsub.s16 q1, q9, q1
vadd.s16 q2, q3, q2
vsub.s16 q15, q8, q6
vadd.s16 q1, q1, q2
vadd.s16 q8, q8, q6
vadd.s16 q14, q5, q3
vsub.s16 q9, q5, q3
vsub.s16 q13, q10, q2
vpop {d8-d13} /* restore NEON registers */
vadd.s16 q10, q10, q2
vsub.s16 q11, q12, q1
vadd.s16 q12, q12, q1
/* Descale to 8-bit and range limit */
vmov.u8 q0, #0x80
vqshrn.s16 d16, q8, #5
vqshrn.s16 d17, q9, #5
vqshrn.s16 d18, q10, #5
vqshrn.s16 d19, q11, #5
vqshrn.s16 d20, q12, #5
vqshrn.s16 d21, q13, #5
vqshrn.s16 d22, q14, #5
vqshrn.s16 d23, q15, #5
vadd.u8 q8, q8, q0
vadd.u8 q9, q9, q0
vadd.u8 q10, q10, q0
vadd.u8 q11, q11, q0
/* Transpose the final 8-bit samples */
vtrn.16 q8, q9
vtrn.16 q10, q11
vtrn.32 q8, q10
vtrn.32 q9, q11
vtrn.8 d16, d17
vtrn.8 d18, d19
/* Store results to the output buffer */
ldmia OUTPUT_BUF!, {TMP1, TMP2}
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
vst1.8 {d16}, [TMP1]
vst1.8 {d17}, [TMP2]
ldmia OUTPUT_BUF!, {TMP1, TMP2}
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
vst1.8 {d18}, [TMP1]
vtrn.8 d20, d21
vst1.8 {d19}, [TMP2]
ldmia OUTPUT_BUF, {TMP1, TMP2, TMP3, TMP4}
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
add TMP3, TMP3, OUTPUT_COL
add TMP4, TMP4, OUTPUT_COL
vst1.8 {d20}, [TMP1]
vtrn.8 d22, d23
vst1.8 {d21}, [TMP2]
vst1.8 {d22}, [TMP3]
vst1.8 {d23}, [TMP4]
bx lr
.unreq DCT_TABLE
.unreq COEF_BLOCK
.unreq OUTPUT_BUF
.unreq OUTPUT_COL
.unreq TMP1
.unreq TMP2
.unreq TMP3
.unreq TMP4
/*****************************************************************************/
/*
* jsimd_idct_4x4_neon
*
* This function contains inverse-DCT code for getting reduced-size
* 4x4 pixels output from an 8x8 DCT block. It uses the same calculations
* and produces exactly the same output as IJG's original 'jpeg_idct_4x4'
* function from jpeg-6b (jidctred.c).
*
* NOTE: jpeg-8 has an improved implementation of 4x4 inverse-DCT, which
* requires much less arithmetic operations and hence should be faster.
* The primary purpose of this particular NEON optimized function is
* bit exact compatibility with jpeg-6b.
*
* TODO: a bit better instructions scheduling can be achieved by expanding
* idct_helper/transpose_4x4 macros and reordering instructions,
* but readability will suffer somewhat.
*/
#define CONST_BITS 13
#define FIX_0_211164243 (1730) /* FIX(0.211164243) */
#define FIX_0_509795579 (4176) /* FIX(0.509795579) */
#define FIX_0_601344887 (4926) /* FIX(0.601344887) */
#define FIX_0_720959822 (5906) /* FIX(0.720959822) */
#define FIX_0_765366865 (6270) /* FIX(0.765366865) */
#define FIX_0_850430095 (6967) /* FIX(0.850430095) */
#define FIX_0_899976223 (7373) /* FIX(0.899976223) */
#define FIX_1_061594337 (8697) /* FIX(1.061594337) */
#define FIX_1_272758580 (10426) /* FIX(1.272758580) */
#define FIX_1_451774981 (11893) /* FIX(1.451774981) */
#define FIX_1_847759065 (15137) /* FIX(1.847759065) */
#define FIX_2_172734803 (17799) /* FIX(2.172734803) */
#define FIX_2_562915447 (20995) /* FIX(2.562915447) */
#define FIX_3_624509785 (29692) /* FIX(3.624509785) */
.balign 16
jsimd_idct_4x4_neon_consts:
.short FIX_1_847759065 /* d0[0] */
.short -FIX_0_765366865 /* d0[1] */
.short -FIX_0_211164243 /* d0[2] */
.short FIX_1_451774981 /* d0[3] */
.short -FIX_2_172734803 /* d1[0] */
.short FIX_1_061594337 /* d1[1] */
.short -FIX_0_509795579 /* d1[2] */
.short -FIX_0_601344887 /* d1[3] */
.short FIX_0_899976223 /* d2[0] */
.short FIX_2_562915447 /* d2[1] */
.short 1 << (CONST_BITS+1) /* d2[2] */
.short 0 /* d2[3] */
.macro idct_helper x4, x6, x8, x10, x12, x14, x16, shift, y26, y27, y28, y29
vmull.s16 q14, \x4, d2[2]
vmlal.s16 q14, \x8, d0[0]
vmlal.s16 q14, \x14, d0[1]
vmull.s16 q13, \x16, d1[2]
vmlal.s16 q13, \x12, d1[3]
vmlal.s16 q13, \x10, d2[0]
vmlal.s16 q13, \x6, d2[1]
vmull.s16 q15, \x4, d2[2]
vmlsl.s16 q15, \x8, d0[0]
vmlsl.s16 q15, \x14, d0[1]
vmull.s16 q12, \x16, d0[2]
vmlal.s16 q12, \x12, d0[3]
vmlal.s16 q12, \x10, d1[0]
vmlal.s16 q12, \x6, d1[1]
vadd.s32 q10, q14, q13
vsub.s32 q14, q14, q13
.if \shift > 16
vrshr.s32 q10, q10, #\shift
vrshr.s32 q14, q14, #\shift
vmovn.s32 \y26, q10
vmovn.s32 \y29, q14
.else
vrshrn.s32 \y26, q10, #\shift
vrshrn.s32 \y29, q14, #\shift
.endif
vadd.s32 q10, q15, q12
vsub.s32 q15, q15, q12
.if \shift > 16
vrshr.s32 q10, q10, #\shift
vrshr.s32 q15, q15, #\shift
vmovn.s32 \y27, q10
vmovn.s32 \y28, q15
.else
vrshrn.s32 \y27, q10, #\shift
vrshrn.s32 \y28, q15, #\shift
.endif
.endm
asm_function jsimd_idct_4x4_neon
DCT_TABLE .req r0
COEF_BLOCK .req r1
OUTPUT_BUF .req r2
OUTPUT_COL .req r3
TMP1 .req r0
TMP2 .req r1
TMP3 .req r2
TMP4 .req ip
vpush {d8-d15}
/* Load constants (d3 is just used for padding) */
adr TMP4, jsimd_idct_4x4_neon_consts
vld1.16 {d0, d1, d2, d3}, [TMP4, :128]
/* Load all COEF_BLOCK into NEON registers with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | d4 | d5
* 1 | d6 | d7
* 2 | d8 | d9
* 3 | d10 | d11
* 4 | - | -
* 5 | d12 | d13
* 6 | d14 | d15
* 7 | d16 | d17
*/
vld1.16 {d4, d5, d6, d7}, [COEF_BLOCK, :128]!
vld1.16 {d8, d9, d10, d11}, [COEF_BLOCK, :128]!
add COEF_BLOCK, COEF_BLOCK, #16
vld1.16 {d12, d13, d14, d15}, [COEF_BLOCK, :128]!
vld1.16 {d16, d17}, [COEF_BLOCK, :128]!
/* dequantize */
vld1.16 {d18, d19, d20, d21}, [DCT_TABLE, :128]!
vmul.s16 q2, q2, q9
vld1.16 {d22, d23, d24, d25}, [DCT_TABLE, :128]!
vmul.s16 q3, q3, q10
vmul.s16 q4, q4, q11
add DCT_TABLE, DCT_TABLE, #16
vld1.16 {d26, d27, d28, d29}, [DCT_TABLE, :128]!
vmul.s16 q5, q5, q12
vmul.s16 q6, q6, q13
vld1.16 {d30, d31}, [DCT_TABLE, :128]!
vmul.s16 q7, q7, q14
vmul.s16 q8, q8, q15
/* Pass 1 */
idct_helper d4, d6, d8, d10, d12, d14, d16, 12, d4, d6, d8, d10
transpose_4x4 d4, d6, d8, d10
idct_helper d5, d7, d9, d11, d13, d15, d17, 12, d5, d7, d9, d11
transpose_4x4 d5, d7, d9, d11
/* Pass 2 */
idct_helper d4, d6, d8, d10, d7, d9, d11, 19, d26, d27, d28, d29
transpose_4x4 d26, d27, d28, d29
/* Range limit */
vmov.u16 q15, #0x80
vadd.s16 q13, q13, q15
vadd.s16 q14, q14, q15
vqmovun.s16 d26, q13
vqmovun.s16 d27, q14
/* Store results to the output buffer */
ldmia OUTPUT_BUF, {TMP1, TMP2, TMP3, TMP4}
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
add TMP3, TMP3, OUTPUT_COL
add TMP4, TMP4, OUTPUT_COL
#if defined(__ARMEL__) && !RESPECT_STRICT_ALIGNMENT
/* We can use much less instructions on little endian systems if the
* OS kernel is not configured to trap unaligned memory accesses
*/
vst1.32 {d26[0]}, [TMP1]!
vst1.32 {d27[0]}, [TMP3]!
vst1.32 {d26[1]}, [TMP2]!
vst1.32 {d27[1]}, [TMP4]!
#else
vst1.8 {d26[0]}, [TMP1]!
vst1.8 {d27[0]}, [TMP3]!
vst1.8 {d26[1]}, [TMP1]!
vst1.8 {d27[1]}, [TMP3]!
vst1.8 {d26[2]}, [TMP1]!
vst1.8 {d27[2]}, [TMP3]!
vst1.8 {d26[3]}, [TMP1]!
vst1.8 {d27[3]}, [TMP3]!
vst1.8 {d26[4]}, [TMP2]!
vst1.8 {d27[4]}, [TMP4]!
vst1.8 {d26[5]}, [TMP2]!
vst1.8 {d27[5]}, [TMP4]!
vst1.8 {d26[6]}, [TMP2]!
vst1.8 {d27[6]}, [TMP4]!
vst1.8 {d26[7]}, [TMP2]!
vst1.8 {d27[7]}, [TMP4]!
#endif
vpop {d8-d15}
bx lr
.unreq DCT_TABLE
.unreq COEF_BLOCK
.unreq OUTPUT_BUF
.unreq OUTPUT_COL
.unreq TMP1
.unreq TMP2
.unreq TMP3
.unreq TMP4
.purgem idct_helper
/*****************************************************************************/
/*
* jsimd_idct_2x2_neon
*
* This function contains inverse-DCT code for getting reduced-size
* 2x2 pixels output from an 8x8 DCT block. It uses the same calculations
* and produces exactly the same output as IJG's original 'jpeg_idct_2x2'
* function from jpeg-6b (jidctred.c).
*
* NOTE: jpeg-8 has an improved implementation of 2x2 inverse-DCT, which
* requires much less arithmetic operations and hence should be faster.
* The primary purpose of this particular NEON optimized function is
* bit exact compatibility with jpeg-6b.
*/
.balign 8
jsimd_idct_2x2_neon_consts:
.short -FIX_0_720959822 /* d0[0] */
.short FIX_0_850430095 /* d0[1] */
.short -FIX_1_272758580 /* d0[2] */
.short FIX_3_624509785 /* d0[3] */
.macro idct_helper x4, x6, x10, x12, x16, shift, y26, y27
vshll.s16 q14, \x4, #15
vmull.s16 q13, \x6, d0[3]
vmlal.s16 q13, \x10, d0[2]
vmlal.s16 q13, \x12, d0[1]
vmlal.s16 q13, \x16, d0[0]
vadd.s32 q10, q14, q13
vsub.s32 q14, q14, q13
.if \shift > 16
vrshr.s32 q10, q10, #\shift
vrshr.s32 q14, q14, #\shift
vmovn.s32 \y26, q10
vmovn.s32 \y27, q14
.else
vrshrn.s32 \y26, q10, #\shift
vrshrn.s32 \y27, q14, #\shift
.endif
.endm
asm_function jsimd_idct_2x2_neon
DCT_TABLE .req r0
COEF_BLOCK .req r1
OUTPUT_BUF .req r2
OUTPUT_COL .req r3
TMP1 .req r0
TMP2 .req ip
vpush {d8-d15}
/* Load constants */
adr TMP2, jsimd_idct_2x2_neon_consts
vld1.16 {d0}, [TMP2, :64]
/* Load all COEF_BLOCK into NEON registers with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | d4 | d5
* 1 | d6 | d7
* 2 | - | -
* 3 | d10 | d11
* 4 | - | -
* 5 | d12 | d13
* 6 | - | -
* 7 | d16 | d17
*/
vld1.16 {d4, d5, d6, d7}, [COEF_BLOCK, :128]!
add COEF_BLOCK, COEF_BLOCK, #16
vld1.16 {d10, d11}, [COEF_BLOCK, :128]!
add COEF_BLOCK, COEF_BLOCK, #16
vld1.16 {d12, d13}, [COEF_BLOCK, :128]!
add COEF_BLOCK, COEF_BLOCK, #16
vld1.16 {d16, d17}, [COEF_BLOCK, :128]!
/* Dequantize */
vld1.16 {d18, d19, d20, d21}, [DCT_TABLE, :128]!
vmul.s16 q2, q2, q9
vmul.s16 q3, q3, q10
add DCT_TABLE, DCT_TABLE, #16
vld1.16 {d24, d25}, [DCT_TABLE, :128]!
vmul.s16 q5, q5, q12
add DCT_TABLE, DCT_TABLE, #16
vld1.16 {d26, d27}, [DCT_TABLE, :128]!
vmul.s16 q6, q6, q13
add DCT_TABLE, DCT_TABLE, #16
vld1.16 {d30, d31}, [DCT_TABLE, :128]!
vmul.s16 q8, q8, q15
/* Pass 1 */
#if 0
idct_helper d4, d6, d10, d12, d16, 13, d4, d6
transpose_4x4 d4, d6, d8, d10
idct_helper d5, d7, d11, d13, d17, 13, d5, d7
transpose_4x4 d5, d7, d9, d11
#else
vmull.s16 q13, d6, d0[3]
vmlal.s16 q13, d10, d0[2]
vmlal.s16 q13, d12, d0[1]
vmlal.s16 q13, d16, d0[0]
vmull.s16 q12, d7, d0[3]
vmlal.s16 q12, d11, d0[2]
vmlal.s16 q12, d13, d0[1]
vmlal.s16 q12, d17, d0[0]
vshll.s16 q14, d4, #15
vshll.s16 q15, d5, #15
vadd.s32 q10, q14, q13
vsub.s32 q14, q14, q13
vrshrn.s32 d4, q10, #13
vrshrn.s32 d6, q14, #13
vadd.s32 q10, q15, q12
vsub.s32 q14, q15, q12
vrshrn.s32 d5, q10, #13
vrshrn.s32 d7, q14, #13
vtrn.16 q2, q3
vtrn.32 q3, q5
#endif
/* Pass 2 */
idct_helper d4, d6, d10, d7, d11, 20, d26, d27
/* Range limit */
vmov.u16 q15, #0x80
vadd.s16 q13, q13, q15
vqmovun.s16 d26, q13
vqmovun.s16 d27, q13
/* Store results to the output buffer */
ldmia OUTPUT_BUF, {TMP1, TMP2}
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
vst1.8 {d26[0]}, [TMP1]!
vst1.8 {d27[4]}, [TMP1]!
vst1.8 {d26[1]}, [TMP2]!
vst1.8 {d27[5]}, [TMP2]!
vpop {d8-d15}
bx lr
.unreq DCT_TABLE
.unreq COEF_BLOCK
.unreq OUTPUT_BUF
.unreq OUTPUT_COL
.unreq TMP1
.unreq TMP2
.purgem idct_helper
/*****************************************************************************/
/*
* jsimd_ycc_extrgb_convert_neon
* jsimd_ycc_extbgr_convert_neon
* jsimd_ycc_extrgbx_convert_neon
* jsimd_ycc_extbgrx_convert_neon
* jsimd_ycc_extxbgr_convert_neon
* jsimd_ycc_extxrgb_convert_neon
*
* Colorspace conversion YCbCr -> RGB
*/
.macro do_load size
.if \size == 8
vld1.8 {d4}, [U, :64]!
vld1.8 {d5}, [V, :64]!
vld1.8 {d0}, [Y, :64]!
pld [U, #64]
pld [V, #64]
pld [Y, #64]
.elseif \size == 4
vld1.8 {d4[0]}, [U]!
vld1.8 {d4[1]}, [U]!
vld1.8 {d4[2]}, [U]!
vld1.8 {d4[3]}, [U]!
vld1.8 {d5[0]}, [V]!
vld1.8 {d5[1]}, [V]!
vld1.8 {d5[2]}, [V]!
vld1.8 {d5[3]}, [V]!
vld1.8 {d0[0]}, [Y]!
vld1.8 {d0[1]}, [Y]!
vld1.8 {d0[2]}, [Y]!
vld1.8 {d0[3]}, [Y]!
.elseif \size == 2
vld1.8 {d4[4]}, [U]!
vld1.8 {d4[5]}, [U]!
vld1.8 {d5[4]}, [V]!
vld1.8 {d5[5]}, [V]!
vld1.8 {d0[4]}, [Y]!
vld1.8 {d0[5]}, [Y]!
.elseif \size == 1
vld1.8 {d4[6]}, [U]!
vld1.8 {d5[6]}, [V]!
vld1.8 {d0[6]}, [Y]!
.else
.error unsupported macroblock size
.endif
.endm
.macro do_store bpp, size
.if \bpp == 24
.if \size == 8
vst3.8 {d10, d11, d12}, [RGB]!
.elseif \size == 4
vst3.8 {d10[0], d11[0], d12[0]}, [RGB]!
vst3.8 {d10[1], d11[1], d12[1]}, [RGB]!
vst3.8 {d10[2], d11[2], d12[2]}, [RGB]!
vst3.8 {d10[3], d11[3], d12[3]}, [RGB]!
.elseif \size == 2
vst3.8 {d10[4], d11[4], d12[4]}, [RGB]!
vst3.8 {d10[5], d11[5], d12[5]}, [RGB]!
.elseif \size == 1
vst3.8 {d10[6], d11[6], d12[6]}, [RGB]!
.else
.error unsupported macroblock size
.endif
.elseif \bpp == 32
.if \size == 8
vst4.8 {d10, d11, d12, d13}, [RGB]!
.elseif \size == 4
vst4.8 {d10[0], d11[0], d12[0], d13[0]}, [RGB]!
vst4.8 {d10[1], d11[1], d12[1], d13[1]}, [RGB]!
vst4.8 {d10[2], d11[2], d12[2], d13[2]}, [RGB]!
vst4.8 {d10[3], d11[3], d12[3], d13[3]}, [RGB]!
.elseif \size == 2
vst4.8 {d10[4], d11[4], d12[4], d13[4]}, [RGB]!
vst4.8 {d10[5], d11[5], d12[5], d13[5]}, [RGB]!
.elseif \size == 1
vst4.8 {d10[6], d11[6], d12[6], d13[6]}, [RGB]!
.else
.error unsupported macroblock size
.endif
.elseif \bpp == 16
.if \size == 8
vst1.16 {q15}, [RGB]!
.elseif \size == 4
vst1.16 {d30}, [RGB]!
.elseif \size == 2
vst1.16 {d31[0]}, [RGB]!
vst1.16 {d31[1]}, [RGB]!
.elseif \size == 1
vst1.16 {d31[2]}, [RGB]!
.else
.error unsupported macroblock size
.endif
.else
.error unsupported bpp
.endif
.endm
.macro generate_jsimd_ycc_rgb_convert_neon colorid, bpp, r_offs, g_offs, b_offs
/*
* 2 stage pipelined YCbCr->RGB conversion
*/
.macro do_yuv_to_rgb_stage1
vaddw.u8 q3, q1, d4 /* q3 = u - 128 */
vaddw.u8 q4, q1, d5 /* q2 = v - 128 */
vmull.s16 q10, d6, d1[1] /* multiply by -11277 */
vmlal.s16 q10, d8, d1[2] /* multiply by -23401 */
vmull.s16 q11, d7, d1[1] /* multiply by -11277 */
vmlal.s16 q11, d9, d1[2] /* multiply by -23401 */
vmull.s16 q12, d8, d1[0] /* multiply by 22971 */
vmull.s16 q13, d9, d1[0] /* multiply by 22971 */
vmull.s16 q14, d6, d1[3] /* multiply by 29033 */
vmull.s16 q15, d7, d1[3] /* multiply by 29033 */
.endm
.macro do_yuv_to_rgb_stage2
vrshrn.s32 d20, q10, #15
vrshrn.s32 d21, q11, #15
vrshrn.s32 d24, q12, #14
vrshrn.s32 d25, q13, #14
vrshrn.s32 d28, q14, #14
vrshrn.s32 d29, q15, #14
vaddw.u8 q11, q10, d0
vaddw.u8 q12, q12, d0
vaddw.u8 q14, q14, d0
.if \bpp != 16
vqmovun.s16 d1\g_offs, q11
vqmovun.s16 d1\r_offs, q12
vqmovun.s16 d1\b_offs, q14
.else /* rgb565 */
vqshlu.s16 q13, q11, #8
vqshlu.s16 q15, q12, #8
vqshlu.s16 q14, q14, #8
vsri.u16 q15, q13, #5
vsri.u16 q15, q14, #11
.endif
.endm
.macro do_yuv_to_rgb_stage2_store_load_stage1
/* "do_yuv_to_rgb_stage2" and "store" */
vrshrn.s32 d20, q10, #15
/* "load" and "do_yuv_to_rgb_stage1" */
pld [U, #64]
vrshrn.s32 d21, q11, #15
pld [V, #64]
vrshrn.s32 d24, q12, #14
vrshrn.s32 d25, q13, #14
vld1.8 {d4}, [U, :64]!
vrshrn.s32 d28, q14, #14
vld1.8 {d5}, [V, :64]!
vrshrn.s32 d29, q15, #14
vaddw.u8 q3, q1, d4 /* q3 = u - 128 */
vaddw.u8 q4, q1, d5 /* q2 = v - 128 */
vaddw.u8 q11, q10, d0
vmull.s16 q10, d6, d1[1] /* multiply by -11277 */
vmlal.s16 q10, d8, d1[2] /* multiply by -23401 */
vaddw.u8 q12, q12, d0
vaddw.u8 q14, q14, d0
.if \bpp != 16 /**************** rgb24/rgb32 *********************************/
vqmovun.s16 d1\g_offs, q11
pld [Y, #64]
vqmovun.s16 d1\r_offs, q12
vld1.8 {d0}, [Y, :64]!
vqmovun.s16 d1\b_offs, q14
vmull.s16 q11, d7, d1[1] /* multiply by -11277 */
vmlal.s16 q11, d9, d1[2] /* multiply by -23401 */
do_store \bpp, 8
vmull.s16 q12, d8, d1[0] /* multiply by 22971 */
vmull.s16 q13, d9, d1[0] /* multiply by 22971 */
vmull.s16 q14, d6, d1[3] /* multiply by 29033 */
vmull.s16 q15, d7, d1[3] /* multiply by 29033 */
.else /**************************** rgb565 ***********************************/
vqshlu.s16 q13, q11, #8
pld [Y, #64]
vqshlu.s16 q15, q12, #8
vqshlu.s16 q14, q14, #8
vld1.8 {d0}, [Y, :64]!
vmull.s16 q11, d7, d1[1]
vmlal.s16 q11, d9, d1[2]
vsri.u16 q15, q13, #5
vmull.s16 q12, d8, d1[0]
vsri.u16 q15, q14, #11
vmull.s16 q13, d9, d1[0]
vmull.s16 q14, d6, d1[3]
do_store \bpp, 8
vmull.s16 q15, d7, d1[3]
.endif
.endm
.macro do_yuv_to_rgb
do_yuv_to_rgb_stage1
do_yuv_to_rgb_stage2
.endm
/* Apple gas crashes on adrl, work around that by using adr.
* But this requires a copy of these constants for each function.
*/
.balign 16
jsimd_ycc_\colorid\()_neon_consts:
.short 0, 0, 0, 0
.short 22971, -11277, -23401, 29033
.short -128, -128, -128, -128
.short -128, -128, -128, -128
asm_function jsimd_ycc_\colorid\()_convert_neon
OUTPUT_WIDTH .req r0
INPUT_BUF .req r1
INPUT_ROW .req r2
OUTPUT_BUF .req r3
NUM_ROWS .req r4
INPUT_BUF0 .req r5
INPUT_BUF1 .req r6
INPUT_BUF2 .req INPUT_BUF
RGB .req r7
Y .req r8
U .req r9
V .req r10
N .req ip
/* Load constants to d1, d2, d3 (d0 is just used for padding) */
adr ip, jsimd_ycc_\colorid\()_neon_consts
vld1.16 {d0, d1, d2, d3}, [ip, :128]
/* Save ARM registers and handle input arguments */
push {r4, r5, r6, r7, r8, r9, r10, lr}
ldr NUM_ROWS, [sp, #(4 * 8)]
ldr INPUT_BUF0, [INPUT_BUF]
ldr INPUT_BUF1, [INPUT_BUF, #4]
ldr INPUT_BUF2, [INPUT_BUF, #8]
.unreq INPUT_BUF
/* Save NEON registers */
vpush {d8-d15}
/* Initially set d10, d11, d12, d13 to 0xFF */
vmov.u8 q5, #255
vmov.u8 q6, #255
/* Outer loop over scanlines */
cmp NUM_ROWS, #1
blt 9f
0:
ldr Y, [INPUT_BUF0, INPUT_ROW, lsl #2]
ldr U, [INPUT_BUF1, INPUT_ROW, lsl #2]
mov N, OUTPUT_WIDTH
ldr V, [INPUT_BUF2, INPUT_ROW, lsl #2]
add INPUT_ROW, INPUT_ROW, #1
ldr RGB, [OUTPUT_BUF], #4
/* Inner loop over pixels */
subs N, N, #8
blt 3f
do_load 8
do_yuv_to_rgb_stage1
subs N, N, #8
blt 2f
1:
do_yuv_to_rgb_stage2_store_load_stage1
subs N, N, #8
bge 1b
2:
do_yuv_to_rgb_stage2
do_store \bpp, 8
tst N, #7
beq 8f
3:
tst N, #4
beq 3f
do_load 4
3:
tst N, #2
beq 4f
do_load 2
4:
tst N, #1
beq 5f
do_load 1
5:
do_yuv_to_rgb
tst N, #4
beq 6f
do_store \bpp, 4
6:
tst N, #2
beq 7f
do_store \bpp, 2
7:
tst N, #1
beq 8f
do_store \bpp, 1
8:
subs NUM_ROWS, NUM_ROWS, #1
bgt 0b
9:
/* Restore all registers and return */
vpop {d8-d15}
pop {r4, r5, r6, r7, r8, r9, r10, pc}
.unreq OUTPUT_WIDTH
.unreq INPUT_ROW
.unreq OUTPUT_BUF
.unreq NUM_ROWS
.unreq INPUT_BUF0
.unreq INPUT_BUF1
.unreq INPUT_BUF2
.unreq RGB
.unreq Y
.unreq U
.unreq V
.unreq N
.purgem do_yuv_to_rgb
.purgem do_yuv_to_rgb_stage1
.purgem do_yuv_to_rgb_stage2
.purgem do_yuv_to_rgb_stage2_store_load_stage1
.endm
/*--------------------------------- id ----- bpp R G B */
generate_jsimd_ycc_rgb_convert_neon extrgb, 24, 0, 1, 2
generate_jsimd_ycc_rgb_convert_neon extbgr, 24, 2, 1, 0
generate_jsimd_ycc_rgb_convert_neon extrgbx, 32, 0, 1, 2
generate_jsimd_ycc_rgb_convert_neon extbgrx, 32, 2, 1, 0
generate_jsimd_ycc_rgb_convert_neon extxbgr, 32, 3, 2, 1
generate_jsimd_ycc_rgb_convert_neon extxrgb, 32, 1, 2, 3
generate_jsimd_ycc_rgb_convert_neon rgb565, 16, 0, 0, 0
.purgem do_load
.purgem do_store
/*****************************************************************************/
/*
* jsimd_extrgb_ycc_convert_neon
* jsimd_extbgr_ycc_convert_neon
* jsimd_extrgbx_ycc_convert_neon
* jsimd_extbgrx_ycc_convert_neon
* jsimd_extxbgr_ycc_convert_neon
* jsimd_extxrgb_ycc_convert_neon
*
* Colorspace conversion RGB -> YCbCr
*/
.macro do_store size
.if \size == 8
vst1.8 {d20}, [Y]!
vst1.8 {d21}, [U]!
vst1.8 {d22}, [V]!
.elseif \size == 4
vst1.8 {d20[0]}, [Y]!
vst1.8 {d20[1]}, [Y]!
vst1.8 {d20[2]}, [Y]!
vst1.8 {d20[3]}, [Y]!
vst1.8 {d21[0]}, [U]!
vst1.8 {d21[1]}, [U]!
vst1.8 {d21[2]}, [U]!
vst1.8 {d21[3]}, [U]!
vst1.8 {d22[0]}, [V]!
vst1.8 {d22[1]}, [V]!
vst1.8 {d22[2]}, [V]!
vst1.8 {d22[3]}, [V]!
.elseif \size == 2
vst1.8 {d20[4]}, [Y]!
vst1.8 {d20[5]}, [Y]!
vst1.8 {d21[4]}, [U]!
vst1.8 {d21[5]}, [U]!
vst1.8 {d22[4]}, [V]!
vst1.8 {d22[5]}, [V]!
.elseif \size == 1
vst1.8 {d20[6]}, [Y]!
vst1.8 {d21[6]}, [U]!
vst1.8 {d22[6]}, [V]!
.else
.error unsupported macroblock size
.endif
.endm
.macro do_load bpp, size
.if \bpp == 24
.if \size == 8
vld3.8 {d10, d11, d12}, [RGB]!
pld [RGB, #128]
.elseif \size == 4
vld3.8 {d10[0], d11[0], d12[0]}, [RGB]!
vld3.8 {d10[1], d11[1], d12[1]}, [RGB]!
vld3.8 {d10[2], d11[2], d12[2]}, [RGB]!
vld3.8 {d10[3], d11[3], d12[3]}, [RGB]!
.elseif \size == 2
vld3.8 {d10[4], d11[4], d12[4]}, [RGB]!
vld3.8 {d10[5], d11[5], d12[5]}, [RGB]!
.elseif \size == 1
vld3.8 {d10[6], d11[6], d12[6]}, [RGB]!
.else
.error unsupported macroblock size
.endif
.elseif \bpp == 32
.if \size == 8
vld4.8 {d10, d11, d12, d13}, [RGB]!
pld [RGB, #128]
.elseif \size == 4
vld4.8 {d10[0], d11[0], d12[0], d13[0]}, [RGB]!
vld4.8 {d10[1], d11[1], d12[1], d13[1]}, [RGB]!
vld4.8 {d10[2], d11[2], d12[2], d13[2]}, [RGB]!
vld4.8 {d10[3], d11[3], d12[3], d13[3]}, [RGB]!
.elseif \size == 2
vld4.8 {d10[4], d11[4], d12[4], d13[4]}, [RGB]!
vld4.8 {d10[5], d11[5], d12[5], d13[5]}, [RGB]!
.elseif \size == 1
vld4.8 {d10[6], d11[6], d12[6], d13[6]}, [RGB]!
.else
.error unsupported macroblock size
.endif
.else
.error unsupported bpp
.endif
.endm
.macro generate_jsimd_rgb_ycc_convert_neon colorid, bpp, r_offs, g_offs, b_offs
/*
* 2 stage pipelined RGB->YCbCr conversion
*/
.macro do_rgb_to_yuv_stage1
vmovl.u8 q2, d1\r_offs /* r = { d4, d5 } */
vmovl.u8 q3, d1\g_offs /* g = { d6, d7 } */
vmovl.u8 q4, d1\b_offs /* b = { d8, d9 } */
vmull.u16 q7, d4, d0[0]
vmlal.u16 q7, d6, d0[1]
vmlal.u16 q7, d8, d0[2]
vmull.u16 q8, d5, d0[0]
vmlal.u16 q8, d7, d0[1]
vmlal.u16 q8, d9, d0[2]
vrev64.32 q9, q1
vrev64.32 q13, q1
vmlsl.u16 q9, d4, d0[3]
vmlsl.u16 q9, d6, d1[0]
vmlal.u16 q9, d8, d1[1]
vmlsl.u16 q13, d5, d0[3]
vmlsl.u16 q13, d7, d1[0]
vmlal.u16 q13, d9, d1[1]
vrev64.32 q14, q1
vrev64.32 q15, q1
vmlal.u16 q14, d4, d1[1]
vmlsl.u16 q14, d6, d1[2]
vmlsl.u16 q14, d8, d1[3]
vmlal.u16 q15, d5, d1[1]
vmlsl.u16 q15, d7, d1[2]
vmlsl.u16 q15, d9, d1[3]
.endm
.macro do_rgb_to_yuv_stage2
vrshrn.u32 d20, q7, #16
vrshrn.u32 d21, q8, #16
vshrn.u32 d22, q9, #16
vshrn.u32 d23, q13, #16
vshrn.u32 d24, q14, #16
vshrn.u32 d25, q15, #16
vmovn.u16 d20, q10 /* d20 = y */
vmovn.u16 d21, q11 /* d21 = u */
vmovn.u16 d22, q12 /* d22 = v */
.endm
.macro do_rgb_to_yuv
do_rgb_to_yuv_stage1
do_rgb_to_yuv_stage2
.endm
.macro do_rgb_to_yuv_stage2_store_load_stage1
vrshrn.u32 d20, q7, #16
vrshrn.u32 d21, q8, #16
vshrn.u32 d22, q9, #16
vrev64.32 q9, q1
vshrn.u32 d23, q13, #16
vrev64.32 q13, q1
vshrn.u32 d24, q14, #16
vshrn.u32 d25, q15, #16
do_load \bpp, 8
vmovn.u16 d20, q10 /* d20 = y */
vmovl.u8 q2, d1\r_offs /* r = { d4, d5 } */
vmovn.u16 d21, q11 /* d21 = u */
vmovl.u8 q3, d1\g_offs /* g = { d6, d7 } */
vmovn.u16 d22, q12 /* d22 = v */
vmovl.u8 q4, d1\b_offs /* b = { d8, d9 } */
vmull.u16 q7, d4, d0[0]
vmlal.u16 q7, d6, d0[1]
vmlal.u16 q7, d8, d0[2]
vst1.8 {d20}, [Y]!
vmull.u16 q8, d5, d0[0]
vmlal.u16 q8, d7, d0[1]
vmlal.u16 q8, d9, d0[2]
vmlsl.u16 q9, d4, d0[3]
vmlsl.u16 q9, d6, d1[0]
vmlal.u16 q9, d8, d1[1]
vst1.8 {d21}, [U]!
vmlsl.u16 q13, d5, d0[3]
vmlsl.u16 q13, d7, d1[0]
vmlal.u16 q13, d9, d1[1]
vrev64.32 q14, q1
vrev64.32 q15, q1
vmlal.u16 q14, d4, d1[1]
vmlsl.u16 q14, d6, d1[2]
vmlsl.u16 q14, d8, d1[3]
vst1.8 {d22}, [V]!
vmlal.u16 q15, d5, d1[1]
vmlsl.u16 q15, d7, d1[2]
vmlsl.u16 q15, d9, d1[3]
.endm
.balign 16
jsimd_\colorid\()_ycc_neon_consts:
.short 19595, 38470, 7471, 11059
.short 21709, 32768, 27439, 5329
.short 32767, 128, 32767, 128
.short 32767, 128, 32767, 128
asm_function jsimd_\colorid\()_ycc_convert_neon
OUTPUT_WIDTH .req r0
INPUT_BUF .req r1
OUTPUT_BUF .req r2
OUTPUT_ROW .req r3
NUM_ROWS .req r4
OUTPUT_BUF0 .req r5
OUTPUT_BUF1 .req r6
OUTPUT_BUF2 .req OUTPUT_BUF
RGB .req r7
Y .req r8
U .req r9
V .req r10
N .req ip
/* Load constants to d0, d1, d2, d3 */
adr ip, jsimd_\colorid\()_ycc_neon_consts
vld1.16 {d0, d1, d2, d3}, [ip, :128]
/* Save ARM registers and handle input arguments */
push {r4, r5, r6, r7, r8, r9, r10, lr}
ldr NUM_ROWS, [sp, #(4 * 8)]
ldr OUTPUT_BUF0, [OUTPUT_BUF]
ldr OUTPUT_BUF1, [OUTPUT_BUF, #4]
ldr OUTPUT_BUF2, [OUTPUT_BUF, #8]
.unreq OUTPUT_BUF
/* Save NEON registers */
vpush {d8-d15}
/* Outer loop over scanlines */
cmp NUM_ROWS, #1
blt 9f
0:
ldr Y, [OUTPUT_BUF0, OUTPUT_ROW, lsl #2]
ldr U, [OUTPUT_BUF1, OUTPUT_ROW, lsl #2]
mov N, OUTPUT_WIDTH
ldr V, [OUTPUT_BUF2, OUTPUT_ROW, lsl #2]
add OUTPUT_ROW, OUTPUT_ROW, #1
ldr RGB, [INPUT_BUF], #4
/* Inner loop over pixels */
subs N, N, #8
blt 3f
do_load \bpp, 8
do_rgb_to_yuv_stage1
subs N, N, #8
blt 2f
1:
do_rgb_to_yuv_stage2_store_load_stage1
subs N, N, #8
bge 1b
2:
do_rgb_to_yuv_stage2
do_store 8
tst N, #7
beq 8f
3:
tst N, #4
beq 3f
do_load \bpp, 4
3:
tst N, #2
beq 4f
do_load \bpp, 2
4:
tst N, #1
beq 5f
do_load \bpp, 1
5:
do_rgb_to_yuv
tst N, #4
beq 6f
do_store 4
6:
tst N, #2
beq 7f
do_store 2
7:
tst N, #1
beq 8f
do_store 1
8:
subs NUM_ROWS, NUM_ROWS, #1
bgt 0b
9:
/* Restore all registers and return */
vpop {d8-d15}
pop {r4, r5, r6, r7, r8, r9, r10, pc}
.unreq OUTPUT_WIDTH
.unreq OUTPUT_ROW
.unreq INPUT_BUF
.unreq NUM_ROWS
.unreq OUTPUT_BUF0
.unreq OUTPUT_BUF1
.unreq OUTPUT_BUF2
.unreq RGB
.unreq Y
.unreq U
.unreq V
.unreq N
.purgem do_rgb_to_yuv
.purgem do_rgb_to_yuv_stage1
.purgem do_rgb_to_yuv_stage2
.purgem do_rgb_to_yuv_stage2_store_load_stage1
.endm
/*--------------------------------- id ----- bpp R G B */
generate_jsimd_rgb_ycc_convert_neon extrgb, 24, 0, 1, 2
generate_jsimd_rgb_ycc_convert_neon extbgr, 24, 2, 1, 0
generate_jsimd_rgb_ycc_convert_neon extrgbx, 32, 0, 1, 2
generate_jsimd_rgb_ycc_convert_neon extbgrx, 32, 2, 1, 0
generate_jsimd_rgb_ycc_convert_neon extxbgr, 32, 3, 2, 1
generate_jsimd_rgb_ycc_convert_neon extxrgb, 32, 1, 2, 3
.purgem do_load
.purgem do_store
/*****************************************************************************/
/*
* Load data into workspace, applying unsigned->signed conversion
*
* TODO: can be combined with 'jsimd_fdct_ifast_neon' to get
* rid of VST1.16 instructions
*/
asm_function jsimd_convsamp_neon
SAMPLE_DATA .req r0
START_COL .req r1
WORKSPACE .req r2
TMP1 .req r3
TMP2 .req r4
TMP3 .req r5
TMP4 .req ip
push {r4, r5}
vmov.u8 d0, #128
ldmia SAMPLE_DATA!, {TMP1, TMP2, TMP3, TMP4}
add TMP1, TMP1, START_COL
add TMP2, TMP2, START_COL
add TMP3, TMP3, START_COL
add TMP4, TMP4, START_COL
vld1.8 {d16}, [TMP1]
vsubl.u8 q8, d16, d0
vld1.8 {d18}, [TMP2]
vsubl.u8 q9, d18, d0
vld1.8 {d20}, [TMP3]
vsubl.u8 q10, d20, d0
vld1.8 {d22}, [TMP4]
ldmia SAMPLE_DATA!, {TMP1, TMP2, TMP3, TMP4}
vsubl.u8 q11, d22, d0
vst1.16 {d16, d17, d18, d19}, [WORKSPACE, :128]!
add TMP1, TMP1, START_COL
add TMP2, TMP2, START_COL
vst1.16 {d20, d21, d22, d23}, [WORKSPACE, :128]!
add TMP3, TMP3, START_COL
add TMP4, TMP4, START_COL
vld1.8 {d24}, [TMP1]
vsubl.u8 q12, d24, d0
vld1.8 {d26}, [TMP2]
vsubl.u8 q13, d26, d0
vld1.8 {d28}, [TMP3]
vsubl.u8 q14, d28, d0
vld1.8 {d30}, [TMP4]
vsubl.u8 q15, d30, d0
vst1.16 {d24, d25, d26, d27}, [WORKSPACE, :128]!
vst1.16 {d28, d29, d30, d31}, [WORKSPACE, :128]!
pop {r4, r5}
bx lr
.unreq SAMPLE_DATA
.unreq START_COL
.unreq WORKSPACE
.unreq TMP1
.unreq TMP2
.unreq TMP3
.unreq TMP4
/*****************************************************************************/
/*
* jsimd_fdct_ifast_neon
*
* This function contains a fast, not so accurate integer implementation of
* the forward DCT (Discrete Cosine Transform). It uses the same calculations
* and produces exactly the same output as IJG's original 'jpeg_fdct_ifast'
* function from jfdctfst.c
*
* TODO: can be combined with 'jsimd_convsamp_neon' to get
* rid of a bunch of VLD1.16 instructions
*/
#define XFIX_0_382683433 d0[0]
#define XFIX_0_541196100 d0[1]
#define XFIX_0_707106781 d0[2]
#define XFIX_1_306562965 d0[3]
.balign 16
jsimd_fdct_ifast_neon_consts:
.short (98 * 128) /* XFIX_0_382683433 */
.short (139 * 128) /* XFIX_0_541196100 */
.short (181 * 128) /* XFIX_0_707106781 */
.short (334 * 128 - 256 * 128) /* XFIX_1_306562965 */
asm_function jsimd_fdct_ifast_neon
DATA .req r0
TMP .req ip
vpush {d8-d15}
/* Load constants */
adr TMP, jsimd_fdct_ifast_neon_consts
vld1.16 {d0}, [TMP, :64]
/* Load all DATA into NEON registers with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | d16 | d17 | q8
* 1 | d18 | d19 | q9
* 2 | d20 | d21 | q10
* 3 | d22 | d23 | q11
* 4 | d24 | d25 | q12
* 5 | d26 | d27 | q13
* 6 | d28 | d29 | q14
* 7 | d30 | d31 | q15
*/
vld1.16 {d16, d17, d18, d19}, [DATA, :128]!
vld1.16 {d20, d21, d22, d23}, [DATA, :128]!
vld1.16 {d24, d25, d26, d27}, [DATA, :128]!
vld1.16 {d28, d29, d30, d31}, [DATA, :128]
sub DATA, DATA, #(128 - 32)
mov TMP, #2
1:
/* Transpose */
vtrn.16 q12, q13
vtrn.16 q10, q11
vtrn.16 q8, q9
vtrn.16 q14, q15
vtrn.32 q9, q11
vtrn.32 q13, q15
vtrn.32 q8, q10
vtrn.32 q12, q14
vswp d30, d23
vswp d24, d17
vswp d26, d19
/* 1-D FDCT */
vadd.s16 q2, q11, q12
vswp d28, d21
vsub.s16 q12, q11, q12
vsub.s16 q6, q10, q13
vadd.s16 q10, q10, q13
vsub.s16 q7, q9, q14
vadd.s16 q9, q9, q14
vsub.s16 q1, q8, q15
vadd.s16 q8, q8, q15
vsub.s16 q4, q9, q10
vsub.s16 q5, q8, q2
vadd.s16 q3, q9, q10
vadd.s16 q4, q4, q5
vadd.s16 q2, q8, q2
vqdmulh.s16 q4, q4, XFIX_0_707106781
vadd.s16 q11, q12, q6
vadd.s16 q8, q2, q3
vsub.s16 q12, q2, q3
vadd.s16 q3, q6, q7
vadd.s16 q7, q7, q1
vqdmulh.s16 q3, q3, XFIX_0_707106781
vsub.s16 q6, q11, q7
vadd.s16 q10, q5, q4
vqdmulh.s16 q6, q6, XFIX_0_382683433
vsub.s16 q14, q5, q4
vqdmulh.s16 q11, q11, XFIX_0_541196100
vqdmulh.s16 q5, q7, XFIX_1_306562965
vadd.s16 q4, q1, q3
vsub.s16 q3, q1, q3
vadd.s16 q7, q7, q6
vadd.s16 q11, q11, q6
vadd.s16 q7, q7, q5
vadd.s16 q13, q3, q11
vsub.s16 q11, q3, q11
vadd.s16 q9, q4, q7
vsub.s16 q15, q4, q7
subs TMP, TMP, #1
bne 1b
/* store results */
vst1.16 {d16, d17, d18, d19}, [DATA, :128]!
vst1.16 {d20, d21, d22, d23}, [DATA, :128]!
vst1.16 {d24, d25, d26, d27}, [DATA, :128]!
vst1.16 {d28, d29, d30, d31}, [DATA, :128]
vpop {d8-d15}
bx lr
.unreq DATA
.unreq TMP
/*****************************************************************************/
/*
* GLOBAL(void)
* jsimd_quantize_neon (JCOEFPTR coef_block, DCTELEM * divisors,
* DCTELEM * workspace);
*
* Note: the code uses 2 stage pipelining in order to improve instructions
* scheduling and eliminate stalls (this provides ~15% better
* performance for this function on both ARM Cortex-A8 and
* ARM Cortex-A9 when compared to the non-pipelined variant).
* The instructions which belong to the second stage use different
* indentation for better readiability.
*/
asm_function jsimd_quantize_neon
COEF_BLOCK .req r0
DIVISORS .req r1
WORKSPACE .req r2
RECIPROCAL .req DIVISORS
CORRECTION .req r3
SHIFT .req ip
LOOP_COUNT .req r4
vld1.16 {d0, d1, d2, d3}, [WORKSPACE, :128]!
vabs.s16 q12, q0
add CORRECTION, DIVISORS, #(64 * 2)
add SHIFT, DIVISORS, #(64 * 6)
vld1.16 {d20, d21, d22, d23}, [CORRECTION, :128]!
vabs.s16 q13, q1
vld1.16 {d16, d17, d18, d19}, [RECIPROCAL, :128]!
vadd.u16 q12, q12, q10 /* add correction */
vadd.u16 q13, q13, q11
vmull.u16 q10, d24, d16 /* multiply by reciprocal */
vmull.u16 q11, d25, d17
vmull.u16 q8, d26, d18
vmull.u16 q9, d27, d19
vld1.16 {d24, d25, d26, d27}, [SHIFT, :128]!
vshrn.u32 d20, q10, #16
vshrn.u32 d21, q11, #16
vshrn.u32 d22, q8, #16
vshrn.u32 d23, q9, #16
vneg.s16 q12, q12
vneg.s16 q13, q13
vshr.s16 q2, q0, #15 /* extract sign */
vshr.s16 q3, q1, #15
vshl.u16 q14, q10, q12 /* shift */
vshl.u16 q15, q11, q13
push {r4, r5}
mov LOOP_COUNT, #3
1:
vld1.16 {d0, d1, d2, d3}, [WORKSPACE, :128]!
veor.u16 q14, q14, q2 /* restore sign */
vabs.s16 q12, q0
vld1.16 {d20, d21, d22, d23}, [CORRECTION, :128]!
vabs.s16 q13, q1
veor.u16 q15, q15, q3
vld1.16 {d16, d17, d18, d19}, [RECIPROCAL, :128]!
vadd.u16 q12, q12, q10 /* add correction */
vadd.u16 q13, q13, q11
vmull.u16 q10, d24, d16 /* multiply by reciprocal */
vmull.u16 q11, d25, d17
vmull.u16 q8, d26, d18
vmull.u16 q9, d27, d19
vsub.u16 q14, q14, q2
vld1.16 {d24, d25, d26, d27}, [SHIFT, :128]!
vsub.u16 q15, q15, q3
vshrn.u32 d20, q10, #16
vshrn.u32 d21, q11, #16
vst1.16 {d28, d29, d30, d31}, [COEF_BLOCK, :128]!
vshrn.u32 d22, q8, #16
vshrn.u32 d23, q9, #16
vneg.s16 q12, q12
vneg.s16 q13, q13
vshr.s16 q2, q0, #15 /* extract sign */
vshr.s16 q3, q1, #15
vshl.u16 q14, q10, q12 /* shift */
vshl.u16 q15, q11, q13
subs LOOP_COUNT, LOOP_COUNT, #1
bne 1b
pop {r4, r5}
veor.u16 q14, q14, q2 /* restore sign */
veor.u16 q15, q15, q3
vsub.u16 q14, q14, q2
vsub.u16 q15, q15, q3
vst1.16 {d28, d29, d30, d31}, [COEF_BLOCK, :128]!
bx lr /* return */
.unreq COEF_BLOCK
.unreq DIVISORS
.unreq WORKSPACE
.unreq RECIPROCAL
.unreq CORRECTION
.unreq SHIFT
.unreq LOOP_COUNT
/*****************************************************************************/
/*
* GLOBAL(void)
* jsimd_h2v1_fancy_upsample_neon (int max_v_samp_factor,
* JDIMENSION downsampled_width,
* JSAMPARRAY input_data,
* JSAMPARRAY * output_data_ptr);
*
* Note: the use of unaligned writes is the main remaining bottleneck in
* this code, which can be potentially solved to get up to tens
* of percents performance improvement on Cortex-A8/Cortex-A9.
*/
/*
* Upsample 16 source pixels to 32 destination pixels. The new 16 source
* pixels are loaded to q0. The previous 16 source pixels are in q1. The
* shifted-by-one source pixels are constructed in q2 by using q0 and q1.
* Register d28 is used for multiplication by 3. Register q15 is used
* for adding +1 bias.
*/
.macro upsample16 OUTPTR, INPTR
vld1.8 {q0}, [\INPTR]!
vmovl.u8 q8, d0
vext.8 q2, q1, q0, #15
vmovl.u8 q9, d1
vaddw.u8 q10, q15, d4
vaddw.u8 q11, q15, d5
vmlal.u8 q8, d4, d28
vmlal.u8 q9, d5, d28
vmlal.u8 q10, d0, d28
vmlal.u8 q11, d1, d28
vmov q1, q0 /* backup source pixels to q1 */
vrshrn.u16 d6, q8, #2
vrshrn.u16 d7, q9, #2
vshrn.u16 d8, q10, #2
vshrn.u16 d9, q11, #2
vst2.8 {d6, d7, d8, d9}, [\OUTPTR]!
.endm
/*
* Upsample 32 source pixels to 64 destination pixels. Compared to 'usample16'
* macro, the roles of q0 and q1 registers are reversed for even and odd
* groups of 16 pixels, that's why "vmov q1, q0" instructions are not needed.
* Also this unrolling allows to reorder loads and stores to compensate
* multiplication latency and reduce stalls.
*/
.macro upsample32 OUTPTR, INPTR
/* even 16 pixels group */
vld1.8 {q0}, [\INPTR]!
vmovl.u8 q8, d0
vext.8 q2, q1, q0, #15
vmovl.u8 q9, d1
vaddw.u8 q10, q15, d4
vaddw.u8 q11, q15, d5
vmlal.u8 q8, d4, d28
vmlal.u8 q9, d5, d28
vmlal.u8 q10, d0, d28
vmlal.u8 q11, d1, d28
/* odd 16 pixels group */
vld1.8 {q1}, [\INPTR]!
vrshrn.u16 d6, q8, #2
vrshrn.u16 d7, q9, #2
vshrn.u16 d8, q10, #2
vshrn.u16 d9, q11, #2
vmovl.u8 q8, d2
vext.8 q2, q0, q1, #15
vmovl.u8 q9, d3
vaddw.u8 q10, q15, d4
vaddw.u8 q11, q15, d5
vmlal.u8 q8, d4, d28
vmlal.u8 q9, d5, d28
vmlal.u8 q10, d2, d28
vmlal.u8 q11, d3, d28
vst2.8 {d6, d7, d8, d9}, [\OUTPTR]!
vrshrn.u16 d6, q8, #2
vrshrn.u16 d7, q9, #2
vshrn.u16 d8, q10, #2
vshrn.u16 d9, q11, #2
vst2.8 {d6, d7, d8, d9}, [\OUTPTR]!
.endm
/*
* Upsample a row of WIDTH pixels from INPTR to OUTPTR.
*/
.macro upsample_row OUTPTR, INPTR, WIDTH, TMP1
/* special case for the first and last pixels */
sub \WIDTH, \WIDTH, #1
add \OUTPTR, \OUTPTR, #1
ldrb \TMP1, [\INPTR, \WIDTH]
strb \TMP1, [\OUTPTR, \WIDTH, asl #1]
ldrb \TMP1, [\INPTR], #1
strb \TMP1, [\OUTPTR, #-1]
vmov.8 d3[7], \TMP1
subs \WIDTH, \WIDTH, #32
blt 5f
0: /* process 32 pixels per iteration */
upsample32 \OUTPTR, \INPTR
subs \WIDTH, \WIDTH, #32
bge 0b
5:
adds \WIDTH, \WIDTH, #16
blt 1f
0: /* process 16 pixels if needed */
upsample16 \OUTPTR, \INPTR
subs \WIDTH, \WIDTH, #16
1:
adds \WIDTH, \WIDTH, #16
beq 9f
/* load the remaining 1-15 pixels */
add \INPTR, \INPTR, \WIDTH
tst \WIDTH, #1
beq 2f
sub \INPTR, \INPTR, #1
vld1.8 {d0[0]}, [\INPTR]
2:
tst \WIDTH, #2
beq 2f
vext.8 d0, d0, d0, #6
sub \INPTR, \INPTR, #1
vld1.8 {d0[1]}, [\INPTR]
sub \INPTR, \INPTR, #1
vld1.8 {d0[0]}, [\INPTR]
2:
tst \WIDTH, #4
beq 2f
vrev64.32 d0, d0
sub \INPTR, \INPTR, #1
vld1.8 {d0[3]}, [\INPTR]
sub \INPTR, \INPTR, #1
vld1.8 {d0[2]}, [\INPTR]
sub \INPTR, \INPTR, #1
vld1.8 {d0[1]}, [\INPTR]
sub \INPTR, \INPTR, #1
vld1.8 {d0[0]}, [\INPTR]
2:
tst \WIDTH, #8
beq 2f
vmov d1, d0
sub \INPTR, \INPTR, #8
vld1.8 {d0}, [\INPTR]
2: /* upsample the remaining pixels */
vmovl.u8 q8, d0
vext.8 q2, q1, q0, #15
vmovl.u8 q9, d1
vaddw.u8 q10, q15, d4
vaddw.u8 q11, q15, d5
vmlal.u8 q8, d4, d28
vmlal.u8 q9, d5, d28
vmlal.u8 q10, d0, d28
vmlal.u8 q11, d1, d28
vrshrn.u16 d10, q8, #2
vrshrn.u16 d12, q9, #2
vshrn.u16 d11, q10, #2
vshrn.u16 d13, q11, #2
vzip.8 d10, d11
vzip.8 d12, d13
/* store the remaining pixels */
tst \WIDTH, #8
beq 2f
vst1.8 {d10, d11}, [\OUTPTR]!
vmov q5, q6
2:
tst \WIDTH, #4
beq 2f
vst1.8 {d10}, [\OUTPTR]!
vmov d10, d11
2:
tst \WIDTH, #2
beq 2f
vst1.8 {d10[0]}, [\OUTPTR]!
vst1.8 {d10[1]}, [\OUTPTR]!
vst1.8 {d10[2]}, [\OUTPTR]!
vst1.8 {d10[3]}, [\OUTPTR]!
vext.8 d10, d10, d10, #4
2:
tst \WIDTH, #1
beq 2f
vst1.8 {d10[0]}, [\OUTPTR]!
vst1.8 {d10[1]}, [\OUTPTR]!
2:
9:
.endm
asm_function jsimd_h2v1_fancy_upsample_neon
MAX_V_SAMP_FACTOR .req r0
DOWNSAMPLED_WIDTH .req r1
INPUT_DATA .req r2
OUTPUT_DATA_PTR .req r3
OUTPUT_DATA .req OUTPUT_DATA_PTR
OUTPTR .req r4
INPTR .req r5
WIDTH .req ip
TMP .req lr
push {r4, r5, r6, lr}
vpush {d8-d15}
ldr OUTPUT_DATA, [OUTPUT_DATA_PTR]
cmp MAX_V_SAMP_FACTOR, #0
ble 99f
/* initialize constants */
vmov.u8 d28, #3
vmov.u16 q15, #1
11:
ldr INPTR, [INPUT_DATA], #4
ldr OUTPTR, [OUTPUT_DATA], #4
mov WIDTH, DOWNSAMPLED_WIDTH
upsample_row OUTPTR, INPTR, WIDTH, TMP
subs MAX_V_SAMP_FACTOR, MAX_V_SAMP_FACTOR, #1
bgt 11b
99:
vpop {d8-d15}
pop {r4, r5, r6, pc}
.unreq MAX_V_SAMP_FACTOR
.unreq DOWNSAMPLED_WIDTH
.unreq INPUT_DATA
.unreq OUTPUT_DATA_PTR
.unreq OUTPUT_DATA
.unreq OUTPTR
.unreq INPTR
.unreq WIDTH
.unreq TMP
.purgem upsample16
.purgem upsample32
.purgem upsample_row
|
lvonasek/3DLiveScanner | 8,153 | third_party/libpng/arm/filter_neon.S |
/* filter_neon.S - NEON optimised filter functions
*
* Copyright (c) 2013 Glenn Randers-Pehrson
* Written by Mans Rullgard, 2011.
* Last changed in libpng 1.6.8 [December 19, 2013]
*
* This code is released under the libpng license.
* For conditions of distribution and use, see the disclaimer
* and license in png.h
*/
/* This is required to get the symbol renames, which are #defines, and also
* includes the definition (or not) of PNG_ARM_NEON_OPT and
* PNG_ARM_NEON_IMPLEMENTATION.
*/
#define PNG_VERSION_INFO_ONLY
#include "../pngpriv.h"
#if defined(__linux__) && defined(__ELF__)
.section .note.GNU-stack,"",%progbits /* mark stack as non-executable */
#endif
/* Assembler NEON support - only works for 32-bit ARM (i.e. it does not work for
* ARM64). The code in arm/filter_neon_intrinsics.c supports ARM64, however it
* only works if -mfpu=neon is specified on the GCC command line. See pngpriv.h
* for the logic which sets PNG_USE_ARM_NEON_ASM:
*/
#if PNG_ARM_NEON_IMPLEMENTATION == 2 /* hand-coded assembler */
#ifdef PNG_READ_SUPPORTED
#if PNG_ARM_NEON_OPT > 0
#ifdef __ELF__
# define ELF
#else
# define ELF @
#endif
.arch armv7-a
.fpu neon
.macro func name, export=0
.macro endfunc
ELF .size \name, . - \name
.endfunc
.purgem endfunc
.endm
.text
.if \export
.global \name
.endif
ELF .type \name, STT_FUNC
.func \name
\name:
.endm
func png_read_filter_row_sub4_neon, export=1
ldr r3, [r0, #4] @ rowbytes
vmov.i8 d3, #0
1:
vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
vadd.u8 d0, d3, d4
vadd.u8 d1, d0, d5
vadd.u8 d2, d1, d6
vadd.u8 d3, d2, d7
vst4.32 {d0[0],d1[0],d2[0],d3[0]},[r1,:128]!
subs r3, r3, #16
bgt 1b
bx lr
endfunc
func png_read_filter_row_sub3_neon, export=1
ldr r3, [r0, #4] @ rowbytes
vmov.i8 d3, #0
mov r0, r1
mov r2, #3
mov r12, #12
vld1.8 {q11}, [r0], r12
1:
vext.8 d5, d22, d23, #3
vadd.u8 d0, d3, d22
vext.8 d6, d22, d23, #6
vadd.u8 d1, d0, d5
vext.8 d7, d23, d23, #1
vld1.8 {q11}, [r0], r12
vst1.32 {d0[0]}, [r1,:32], r2
vadd.u8 d2, d1, d6
vst1.32 {d1[0]}, [r1], r2
vadd.u8 d3, d2, d7
vst1.32 {d2[0]}, [r1], r2
vst1.32 {d3[0]}, [r1], r2
subs r3, r3, #12
bgt 1b
bx lr
endfunc
func png_read_filter_row_up_neon, export=1
ldr r3, [r0, #4] @ rowbytes
1:
vld1.8 {q0}, [r1,:128]
vld1.8 {q1}, [r2,:128]!
vadd.u8 q0, q0, q1
vst1.8 {q0}, [r1,:128]!
subs r3, r3, #16
bgt 1b
bx lr
endfunc
func png_read_filter_row_avg4_neon, export=1
ldr r12, [r0, #4] @ rowbytes
vmov.i8 d3, #0
1:
vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
vld4.32 {d16[],d17[],d18[],d19[]},[r2,:128]!
vhadd.u8 d0, d3, d16
vadd.u8 d0, d0, d4
vhadd.u8 d1, d0, d17
vadd.u8 d1, d1, d5
vhadd.u8 d2, d1, d18
vadd.u8 d2, d2, d6
vhadd.u8 d3, d2, d19
vadd.u8 d3, d3, d7
vst4.32 {d0[0],d1[0],d2[0],d3[0]},[r1,:128]!
subs r12, r12, #16
bgt 1b
bx lr
endfunc
func png_read_filter_row_avg3_neon, export=1
push {r4,lr}
ldr r12, [r0, #4] @ rowbytes
vmov.i8 d3, #0
mov r0, r1
mov r4, #3
mov lr, #12
vld1.8 {q11}, [r0], lr
1:
vld1.8 {q10}, [r2], lr
vext.8 d5, d22, d23, #3
vhadd.u8 d0, d3, d20
vext.8 d17, d20, d21, #3
vadd.u8 d0, d0, d22
vext.8 d6, d22, d23, #6
vhadd.u8 d1, d0, d17
vext.8 d18, d20, d21, #6
vadd.u8 d1, d1, d5
vext.8 d7, d23, d23, #1
vld1.8 {q11}, [r0], lr
vst1.32 {d0[0]}, [r1,:32], r4
vhadd.u8 d2, d1, d18
vst1.32 {d1[0]}, [r1], r4
vext.8 d19, d21, d21, #1
vadd.u8 d2, d2, d6
vhadd.u8 d3, d2, d19
vst1.32 {d2[0]}, [r1], r4
vadd.u8 d3, d3, d7
vst1.32 {d3[0]}, [r1], r4
subs r12, r12, #12
bgt 1b
pop {r4,pc}
endfunc
.macro paeth rx, ra, rb, rc
vaddl.u8 q12, \ra, \rb @ a + b
vaddl.u8 q15, \rc, \rc @ 2*c
vabdl.u8 q13, \rb, \rc @ pa
vabdl.u8 q14, \ra, \rc @ pb
vabd.u16 q15, q12, q15 @ pc
vcle.u16 q12, q13, q14 @ pa <= pb
vcle.u16 q13, q13, q15 @ pa <= pc
vcle.u16 q14, q14, q15 @ pb <= pc
vand q12, q12, q13 @ pa <= pb && pa <= pc
vmovn.u16 d28, q14
vmovn.u16 \rx, q12
vbsl d28, \rb, \rc
vbsl \rx, \ra, d28
.endm
func png_read_filter_row_paeth4_neon, export=1
ldr r12, [r0, #4] @ rowbytes
vmov.i8 d3, #0
vmov.i8 d20, #0
1:
vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
vld4.32 {d16[],d17[],d18[],d19[]},[r2,:128]!
paeth d0, d3, d16, d20
vadd.u8 d0, d0, d4
paeth d1, d0, d17, d16
vadd.u8 d1, d1, d5
paeth d2, d1, d18, d17
vadd.u8 d2, d2, d6
paeth d3, d2, d19, d18
vmov d20, d19
vadd.u8 d3, d3, d7
vst4.32 {d0[0],d1[0],d2[0],d3[0]},[r1,:128]!
subs r12, r12, #16
bgt 1b
bx lr
endfunc
func png_read_filter_row_paeth3_neon, export=1
push {r4,lr}
ldr r12, [r0, #4] @ rowbytes
vmov.i8 d3, #0
vmov.i8 d4, #0
mov r0, r1
mov r4, #3
mov lr, #12
vld1.8 {q11}, [r0], lr
1:
vld1.8 {q10}, [r2], lr
paeth d0, d3, d20, d4
vext.8 d5, d22, d23, #3
vadd.u8 d0, d0, d22
vext.8 d17, d20, d21, #3
paeth d1, d0, d17, d20
vst1.32 {d0[0]}, [r1,:32], r4
vext.8 d6, d22, d23, #6
vadd.u8 d1, d1, d5
vext.8 d18, d20, d21, #6
paeth d2, d1, d18, d17
vext.8 d7, d23, d23, #1
vld1.8 {q11}, [r0], lr
vst1.32 {d1[0]}, [r1], r4
vadd.u8 d2, d2, d6
vext.8 d19, d21, d21, #1
paeth d3, d2, d19, d18
vst1.32 {d2[0]}, [r1], r4
vmov d4, d19
vadd.u8 d3, d3, d7
vst1.32 {d3[0]}, [r1], r4
subs r12, r12, #12
bgt 1b
pop {r4,pc}
endfunc
#endif /* PNG_ARM_NEON_OPT > 0 */
#endif /* PNG_READ_SUPPORTED */
#endif /* PNG_ARM_NEON_IMPLEMENTATION == 2 (assembler) */
|
M2IHP13-admin/JonesForth-arm | 34,625 | jonesforth.S | @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@
@ Jones' Forth port for ARM EABI
@ Copyright (C) 2013 M2IHP'13 class, see AUTHORS for the full list of
@ contributors.
@
@ Original x86 and forth code: Richard W.M. Jones <rich@annexia.org>
@
@ The extensive comments from Jones' x86 version have been removed. You should
@ check them out, they are really detailed, well written and pedagogical.
@
@ The DIVMOD routine is taken from the ARM Software Development Toolkit User
@ Guide 2.50.
@
@ This program is free software: you can redistribute it and/or modify it under
@ the terms of the GNU Lesser General Public License as published by the Free
@ Software Foundation, either version 3 of the License, or (at your option) any
@ later version.
@
@ This program is distributed in the hope that it will be useful, but WITHOUT
@ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
@ FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
@ details.
@
@ You should have received a copy of the GNU Lesser General Public License
@ along with this program. If not, see <http://www.gnu.org/licenses/>.
@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
.set JONES_VERSION,47
#include <asm/unistd.h>
@ Reserve three special registers:
@ DSP (r13) points to the top of the data stack
@ RSP (r11) points to the top of the return stack
@ IP (r10) points to the next forth word that will be executed
#define DSP r13
#define RSP r11
#define IP r10
@ Define stdin, stdout, stderr file descriptors numbers
.set stdin, 0
.set stdout, 1
.set stderr, 2
@ Implement NEXT, which:
@ 1. finds the address of the forth word to execute by
@ dereferencing the IP
@ 2. increment IP
@ 3. executes the forth word
.macro NEXT
ldr r0, [IP], #4
ldr r1, [r0]
bx r1
.endm
@ Define macros to push and pop from the data
@ and return stacks
.macro PUSHRSP reg
str \reg, [RSP, #-4]!
.endm
.macro POPRSP reg
ldr \reg, [RSP], #4
.endm
.macro push reg
str \reg, [DSP, #-4]!
.endm
.macro pop reg
ldr \reg, [DSP], #4
.endm
@ DOCOL is the assembly subroutine that is called
@ at the start of every forth word execution.
@ It saves the old IP on the return stack, and
@ makes IP point to the first codeword.
@ Then it calls NEXT to start interpreting the word.
.text
.align 2
DOCOL:
PUSHRSP IP
add IP, r0, #4
NEXT
@ _start is the program entry point
.text
.align 2
.global _start
_start:
ldr r0, =var_S0
str DSP, [r0] @ Save the original stack position in var_S0
ldr RSP, =return_stack_top @ Set the initial return stack position
bl set_up_data_segment @ Set up the data segment
ldr IP, =cold_start @ Make the IP point to cold_start
NEXT @ Start the interpreter
@ Allocate a data segment to define new words and data
@ structures
.set INITIAL_DATA_SEGMENT_SIZE,65536
.text
.align 2
set_up_data_segment:
mov r1, #0
mov r7, #__NR_brk
swi 0 @ Call brk(0) to get value of Program Break
ldr r1, =var_HERE
str r0, [r1] @ Initialize HERE to point at the beginning
@ of data segment
add r0, #INITIAL_DATA_SEGMENT_SIZE
swi 0 @ Allocate Memory
bx lr @ Return
@ cold_start is used to bootstrap the interpreter, the first word executed
@ is QUIT
.section .rodata
cold_start:
.int QUIT
@@ Now we define a set of helper macros that are syntactic sugar
@@ to ease the declaration of Forth words, Native words, Forth variables
@@ and Forth constants.
@ define the word flags
.set F_IMMED,0x80
.set F_HIDDEN,0x20
.set F_LENMASK,0x1f
@ link is used to chain the words in the dictionary as they are defined
.set link,0
@ defword macro helps defining new forth words in assembly
.macro defword name, namelen, flags=0, label
.section .rodata
.align 2
.global name_\label
name_\label :
.int link @ link
.set link,name_\label
.byte \flags+\namelen @ flags + length byte
.ascii "\name" @ the name
.align 2 @ padding to next 4 byte boundary
.global \label
\label :
.int DOCOL @ codeword - the interpreter
@ list of word pointers follow
.endm
@ defcode macro helps defining new native words in assembly
.macro defcode name, namelen, flags=0, label
.section .rodata
.align 2
.globl name_\label
name_\label :
.int link @ link
.set link,name_\label
.byte \flags+\namelen @ flags + length byte
.ascii "\name" @ the name
.align 2 @ padding to next 4 byte boundary
.global \label
\label :
.int code_\label @ codeword
.text
.global code_\label
code_\label : @ assembler code follows
.endm
@ defvar macro helps defining Forth variables in assembly
.macro defvar name, namelen, flags=0, label, initial=0
defcode \name,\namelen,\flags,\label
ldr r0, =var_\name
push r0
NEXT
.data
.align 2
var_\name :
.int \initial
.endm
@defconst macro helps defining Forth constants in assembly
.macro defconst name, namelen, flags=0, label, value
defcode \name,\namelen,\flags,\label
ldr r0, =\value
push r0
NEXT
.endm
@ EXIT is the last codeword of a forth word.
@ It restores the IP and returns to the caller using NEXT.
@ (See DOCOL)
defcode "EXIT",4,,EXIT
POPRSP IP
NEXT
@ DIVMOD computes the unsigned integer division and remainder
@ The implementation is based upon the algorithm extracted from 'ARM Software
@ Development Toolkit User Guide v2.50' published by ARM in 1997-1998
@ The algorithm is split in two steps: search the biggest divisor b^(2^n)
@ lesser than a and then subtract it and all b^(2^i) (for i from 0 to n)
@ to a.
@ ( a b -- r q ) where a = q * b + r
defcode "/MOD",4,,DIVMOD
pop r1 @ Get b
pop r0 @ Get a
mov r3, r1 @ Put b in tmp
cmp r3, r0, LSR #1
1: movls r3, r3, LSL #1 @ Double tmp
cmp r3, r0, LSR #1
bls 1b @ Jump until 2 * tmp > a
mov r2, #0 @ Initialize q
2: cmp r0, r3 @ If a - tmp > 0
subcs r0, r0, r3 @ a <= a - tmp
adc r2, r2, r2 @ Increment q
mov r3, r3, LSR #1 @ Halve tmp
cmp r3, r1 @ Jump until tmp < b
bhs 2b
push r0 @ Put r
push r2 @ Put q
NEXT
@ Alternative to DIVMOD: signed implementation using Euclidean division.
defcode "S/MOD",5,,SDIVMOD
@ Denominator
pop r2
@ Numerator
pop r1
bl _DIVMOD
@ Remainder
push r1
@ Quotient
push r0
NEXT
_DIVMOD:
@ Division by 0.
cmp r2, #0
beq 4f
@ r0 will store the quotient at the end.
mov r0, #0
@ r3 will be 1 if numerator and denominator have the same
@ sign, -1 otherwise.
@ r4 will be 1 if the numerator is positive, -1 otherwise.
mov r3, #1
mov r4, #1
rsblt r3, r3, #0 @ r3 = -r3 if negative denominator
rsblt r2, r2, #0 @ denominator = abs(denominator)
cmp r1, #0
rsblt r4, r4, #0 @ r4 = sign(numerator)
rsblt r3, r3, #0 @ r3 = -r3 if negative numerator
rsblt r1, r1, #0 @ numerator = abs(numerator)
cmp r3, #-1
beq 2f
1: @ Case where denominator and numerator have the same sign.
cmp r1, r2
blt 3f
11:
add r0, r0, #1
sub r1, r1, r2
cmp r1, r2
bge 11b
b 3f
2: @ Case where denominator and numerator have different sign.
cmp r1, #0
beq 3f
21:
sub r0, r0, #1
sub r1, r1, r2
cmp r1, #0
bgt 21b
3:
@ If numerator and denominator were negative:
@ remainder = -remainder
cmp r4, #-1
rsbeq r1, r1, #0
b 5f
4: @ Error, division by 0.
# Display error message on stderr.
mov r0, #stderr
ldr r1, =div0msg
mov r2, #div0msgend-div0msg
mov r7, #__NR_write
swi 0
5:
bx lr
.section .rodata
div0msg: .ascii "Division by 0!\n"
div0msgend:
@ DROP ( a -- ) drops the top element of the stack
defcode "DROP",4,,DROP
pop r0 @( )
NEXT
@ SWAP ( a b -- b a ) swaps the two top elements
defcode "SWAP",4,,SWAP
@ ( a b -- )
pop r0 @ ( a ) , r0 = b
pop r1 @ ( ) , r0 = b, r1 = a
push r0 @ ( b ) , r0 = b, r1 = a
push r1 @ ( b a ) , r0 = b, r1 = a
NEXT
@ DUP ( a -- a a ) duplicates the top element
defcode "DUP",3,,DUP
@ ( a -- )
pop r0 @ ( ) , r0 = a
push r0 @ ( a ) , r0 = a
push r0 @ ( a a ) , r0 = a
NEXT
@ OVER ( a b c -- a b c b ) pushes the second element on top
defcode "OVER",4,,OVER
@ ( a b c) r0 = b we take the element at DSP + 4
@ and since DSP is the top of the stack we will load
@ the second element of the stack in r0
ldr r0, [DSP, #4]
push r0 @ ( a b c b )
NEXT
@ ROT ( a b c -- b c a) rotation
defcode "ROT",3,,ROT
pop r0 @ ( a b ) r0 = c
pop r1 @ ( a ) r1 = b
pop r2 @ ( ) r2 = a
push r1 @ ( b )
push r0 @ ( b c )
push r2 @ ( b c a )
NEXT
@ -ROT ( a b c -- c a b ) backwards rotation
defcode "-ROT",4,,NROT
pop r0 @ ( a b ) r0 = c
pop r1 @ ( a ) r1 = b
pop r2 @ ( ) r2 = a
push r0 @ ( c )
push r2 @ ( c a )
push r1 @ ( c a b )
NEXT
@ ?DUP ( 0 -- 0 | a -- a a ) duplicates if non-zero
defcode "?DUP", 4,,QDUP
@ (x --)
ldr r0, [DSP] @ r0 = x
cmp r0, #0 @ test if x==0
beq 1f @ if x==0 we jump to 1
push r0 @ ( a a ) it's now duplicated
1: NEXT @ ( a a / 0 )
@ 1+ ( a | a+1 ) increments the top element
defcode "1+",2,,INCR
pop r0
add r0,r0,#1
push r0
NEXT
@ 1- ( a | a-1 ) decrements the top element
defcode "1-",2,,DECR
pop r0
sub r0,r0,#1
push r0
NEXT
@ 4+ ( a | a+4 ) increments by 4 the top element
defcode "4+",2,,INCR4
pop r0
add r0,r0,#4
push r0
NEXT
@ 4- ( a | a-4 ) decrements by 4 the top element
defcode "4-",2,,DECR4
pop r0
sub r0,r0,#4
push r0
NEXT
@ + ( a b | a+b)
defcode "+",1,,ADD
pop r0
pop r1
add r0,r0,r1
push r0
NEXT
@ + ( a b | a-b)
defcode "-",1,,SUB
pop r1
pop r0
sub r0,r0,r1
push r0
NEXT
@ + ( a b | a*b)
defcode "*",1,,MUL
pop r0
pop r1
mul r2,r0,r1
push r2
NEXT
@ = ( a b | p ) where p is 1 when a and b are equal (0 otherwise)
defcode "=",1,,EQU
pop r1
pop r0
cmp r0, r1
moveq r0, #1
movne r0, #0
push r0
NEXT
@ <> ( a b | p) where p = a <> b
defcode "<>",2,,NEQU
pop r1
pop r0
cmp r0, r1
movne r0, #1
moveq r0, #0
push r0
NEXT
@ < ( a b | p) where p = a < b
defcode "<",1,,LT
pop r1
pop r0
cmp r0, r1
movlt r0, #1
movge r0, #0
push r0
NEXT
@ < ( a b | p) where p = a < b
defcode ">",1,,GT
pop r1
pop r0
cmp r0, r1
movgt r0, #1
movle r0, #0
push r0
NEXT
@ <= ( a b | p) where p = a <= b
defcode "<=",2,,LE
pop r1
pop r0
cmp r0, r1
movle r0, #1
movgt r0, #0
push r0
NEXT
@ >= ( a b | p) where p = a >= b
defcode ">=",2,,GE
pop r1
pop r0
cmp r0, r1
movge r0, #1
movlt r0, #0
push r0
NEXT
@ AND ( a b | a&b) bitwise and
defcode "AND",3,,AND
pop r0
pop r1
and r0, r1, r0
push r0
NEXT
@ OR ( a b | a|b) bitwise or
defcode "OR",2,,OR
pop r0
pop r1
orr r0, r1, r0
push r0
NEXT
@ XOR ( a b | a^b) bitwise xor
defcode "XOR",3,,XOR
pop r0
pop r1
eor r0, r1, r0
push r0
NEXT
@ INVERT ( a | ~a ) bitwise not
defcode "INVERT",6,,INVERT
pop r0
mvn r0, r0
push r0
NEXT
@ LIT is used to compile literals in forth word.
@ When LIT is executed it pushes the literal (which is the next codeword)
@ into the stack and skips it (since the literal is not executable).
defcode "LIT", 3,, LIT
ldr r1, [IP], #4
push r1
NEXT
@ ! ( value address -- ) write value at address
defcode "!",1,,STORE
pop r0
pop r1
str r1, [r0]
NEXT
@ @ ( address -- value ) reads value from address
defcode "@",1,,FETCH
pop r1
ldr r0, [r1]
push r0
NEXT
@ C! and @! are the same for bytes
defcode "C!",2,,STOREBYTE
pop r0
pop r1
strb r1, [r0]
NEXT
defcode "C@",2,,FETCHBYTE
pop r0
mov r1, #0
ldrb r1, [r0]
push r1
NEXT
@ CMOVE ( source dest length -- ) copies a chunk of length bytes from source
@ address to dest address
defcode "CMOVE",5,,CMOVE
pop r0
pop r1
pop r2
1:
cmp r0, #0 @ while length > 0
ldrgtb r3, [r2], #1 @ read character from source
strgtb r3, [r1], #1 @ and write it to dest (increment both pointers)
subgt r0, r0, #1 @ decrement length
bgt 1b
NEXT
@ Define some variables and constants needed by the Forth interpreter
defvar "STATE",5,,STATE
defvar "HERE",4,,HERE
defvar "LATEST",6,,LATEST,name_SYSCALL0 @ must point to the last word
@ defined in assembly, SYSCALL0
defvar "S0",2,,SZ
defvar "BASE",4,,BASE,10
defconst "VERSION",7,,VERSION,JONES_VERSION
defconst "R0",2,,RZ,return_stack_top
defconst "DOCOL",5,,__DOCOL,DOCOL
defconst "F_IMMED",7,,__F_IMMED,F_IMMED
defconst "F_HIDDEN",8,,__F_HIDDEN,F_HIDDEN
defconst "F_LENMASK",9,,__F_LENMASK,F_LENMASK
defconst "SYS_EXIT",8,,SYS_EXIT,__NR_exit
defconst "SYS_OPEN",8,,SYS_OPEN,__NR_open
defconst "SYS_CLOSE",9,,SYS_CLOSE,__NR_close
defconst "SYS_READ",8,,SYS_READ,__NR_read
defconst "SYS_WRITE",9,,SYS_WRITE,__NR_write
defconst "SYS_CREAT",9,,SYS_CREAT,__NR_creat
defconst "SYS_BRK",7,,SYS_BRK,__NR_brk
defconst "O_RDONLY",8,,__O_RDONLY,0
defconst "O_WRONLY",8,,__O_WRONLY,1
defconst "O_RDWR",6,,__O_RDWR,2
defconst "O_CREAT",7,,__O_CREAT,0100
defconst "O_EXCL",6,,__O_EXCL,0200
defconst "O_TRUNC",7,,__O_TRUNC,01000
defconst "O_APPEND",8,,__O_APPEND,02000
defconst "O_NONBLOCK",10,,__O_NONBLOCK,04000
@ >R ( a -- ) move the top element from the data stack to the return stack
defcode ">R",2,,TOR
pop r0
PUSHRSP r0
NEXT
@ R> ( -- a ) move the top element from the return stack to the data stack
defcode "R>",2,,FROMR
POPRSP r0
push r0
NEXT
@ RDROP drops the top element from the return stack
defcode "RDROP",5,,RDROP
add RSP,RSP,#4
NEXT
@ RSP@, RSP!, DSP@, DSP! manipulate the return and data stack pointers
defcode "RSP@",4,,RSPFETCH
push RSP
NEXT
defcode "RSP!",4,,RSPSTORE
pop RSP
NEXT
defcode "DSP@",4,,DSPFETCH
mov r0, DSP
push r0
NEXT
defcode "DSP!",4,,DSPSTORE
pop r0
mov r0, DSP
NEXT
@ KEY ( -- c ) Reads a key from the user
@ the implementation uses a cached buffer that is
@ refilled, when empty, with a read syscall.
defcode "KEY",3,,KEY
bl _KEY @ Call _KEY
push r0 @ push the return value on the stack
NEXT
_KEY:
ldr r3, =currkey @ Load the address of currkey
ldr r1, [r3] @ Get the value of currkey
ldr r3, =bufftop @ Load the address of bufftop
ldr r2, [r3] @ Get the value of bufftop
cmp r2, r1
ble 1f @ if bufftop <= currkey
ldrb r0, [r1] @ load the first byte of currkey
ldr r3, =currkey
add r1, #1 @ Increments CURRKEY
str r1, [r3]
bx lr @ return
1:
ldr r3, =currkey
mov r0, #0 @ 1st arg: STDIN
ldr r1, =buffer @ 2nd arg : buffer add
str r1, [r3] @ CURRKEY := BUFFER
mov r2, #BUFFER_SIZE @ 3rd arg : buffer sz
mov r7, #__NR_read @ read syscall flag
swi 0 @ call
cmp r0, #0
ble 2f @ if errors goto 2
add r1,r0 @ Set bufftop at the end of the word
ldr r4, =bufftop
str r1, [r4] @ update bufftop
b _KEY
2: @ read syscall returned with an error
mov r0, #0
mov r7, #__NR_exit @ exit(0)
swi 0
@ buffer for KEY
.data
.align 2
currkey:
.int buffer
bufftop:
.int buffer
@ EMIT ( c -- ) outputs character c to stdout
defcode "EMIT",4,,EMIT
pop r0
bl _EMIT
NEXT
_EMIT:
ldr r2, =emit_scratch
str r0, [r2] @ write character to memory
mov r1, r2
mov r2, #1 @ write 1 byte
mov r0, #stdout @ write on standard output
mov r7, #__NR_write @ write syscall flag
swi 0 @ write syscall
bx lr
.data
emit_scratch:
.space 1
@ WORD ( -- addr length ) reads next word from stdin
@ skips spaces and comments, limited to 32 characters
defcode "WORD",4,,WORD
bl _WORD
push r0 @ adress
push r1 @ length
NEXT
_WORD:
stmfd sp!, {r6,lr} @ preserve r6 and lr
1:
bl _KEY @ read a character
cmp r0, #'\\'
beq 3f @ skip comments until end of line
cmp r0, #' '
ble 1b @ skip blank character
ldr r6, =word_buffer
2:
strb r0, [r6], #1 @ store character in word buffer
bl _KEY @ read more characters until a space is found
cmp r0, #' '
bgt 2b
ldr r0, =word_buffer @ r0, address of word
sub r1, r6, r0 @ r1, length of word
ldmfd sp!, {r6,lr} @ restore r6 and lr
bx lr
3:
bl _KEY @ skip all characters until end of line
cmp r0, #'\n'
bne 3b
b 1b
@ word_buffer for WORD
.data
word_buffer:
.space 32
@ NUMBER ( addr length -- n e ) converts string to number
@ n is the parsed number
@ e is the number of unparsed characters
defcode "NUMBER",6,,NUMBER
pop r1
pop r0
bl _NUMBER
push r0
push r1
NEXT
_NUMBER:
stmfd sp!, {r4-r6, lr}
@ Save address of the string.
mov r2, r0
@ r0 will store the result after conversion.
mov r0, #0
@ Check if length is positive, otherwise this is an error.
cmp r1, #0
ble 5f
@ Load current base.
ldr r3, =var_BASE
ldr r3, [r3]
@ Load first character and increment pointer.
ldrb r4, [r2], #1
@ Check trailing '-'.
mov r5, #0
cmp r4, #45 @ 45 in '-' en ASCII
@ Number is positive.
bne 2f
@ Number is negative.
mov r5, #1
sub r1, r1, #1
@ Check if we have more than just '-' in the string.
cmp r1, #0
@ No, proceed with conversion.
bgt 1f
@ Error.
mov r1, #1
b 5f
1:
@ number *= BASE
@ Arithmetic shift right.
@ On ARM we need to use an additional register for MUL.
mul r6, r0, r3
mov r0, r6
@ Load the next character.
ldrb r4, [r2], #1
2:
@ Convert the character into a digit.
sub r4, r4, #48 @ r4 = r4 - '0'
cmp r4, #0
blt 4f @ End, < 0
cmp r4, #9
ble 3f @ chiffre compris entre 0 et 9
@ Test if hexadecimal character.
sub r4, r4, #17 @ 17 = 'A' - '0'
cmp r4, #0
blt 4f @ End, < 'A'
add r4, r4, #10
3:
@ Compare to the current base.
cmp r4, r3
bge 4f @ End, > BASE
@ Everything is fine.
@ Add the digit to the result.
add r0, r0, r4
sub r1, r1, #1
@ Continue processing while there are still characters to read.
cmp r1, #0
bgt 1b
4:
@ Negate result if we had a '-'.
cmp r5, #1
rsbeq r0, r0, #0
5:
@ Back to the caller.
ldmfd sp!, {r4-r6, pc}
@ FIND ( addr length -- dictionary_address )
@ Tries to find a word in the dictionary and returns its address.
@ If the word is not found, NULL is returned.
defcode "FIND",4,,FIND
pop r1 @length
pop r0 @addr
bl _FIND
push r0
NEXT
_FIND:
stmfd sp!, {r5,r6,r8,r9} @ save callee save registers
ldr r2, =var_LATEST
ldr r3, [r2] @ get the last defined word address
1:
cmp r3, #0 @ did we check all the words ?
beq 4f @ then exit
ldrb r2, [r3, #4] @ read the length field
and r2, r2, #(F_HIDDEN|F_LENMASK) @ keep only length + hidden bits
cmp r2, r1 @ do the lengths match ?
@ (note that if a word is hidden,
@ the test will be always negative)
bne 3f @ branch if they do not match
@ Now we compare strings characters
mov r5, r0 @ r5 contains searched string
mov r6, r3 @ r6 contains dict string
add r6, r6, #5 @ (we skip link and length fields)
@ r2 contains the length
2:
ldrb r8, [r5], #1 @ compare character per character
ldrb r9, [r6], #1
cmp r8,r9
bne 3f @ if they do not match, branch to 3
subs r2,r2,#1 @ decrement length
bne 2b @ loop
@ here, strings are equal
b 4f @ branch to 4
3:
ldr r3, [r3] @ Mismatch, follow link to the next
b 1b @ dictionary word
4:
mov r0, r3 @ move result to r0
ldmfd sp!, {r5,r6,r8,r9} @ restore callee save registers
bx lr
@ >CFA ( dictionary_address -- executable_address )
@ Transformat a dictionary address into a code field address
defcode ">CFA",4,,TCFA
pop r0
bl _TCFA
push r0
NEXT
_TCFA:
add r0,r0,#4 @ skip link field
ldrb r1, [r0], #1 @ load and skip the length field
and r1,r1,#F_LENMASK @ keep only the length
add r0,r0,r1 @ skip the name field
add r0,r0,#3 @ find the next 4-byte boundary
and r0,r0,#~3
bx lr
@ >DFA ( dictionary_address -- data_field_address )
@ Return the address of the first data field
defword ">DFA",4,,TDFA
.int TCFA
.int INCR4
.int EXIT
@ CREATE ( address length -- ) Creates a new dictionary entry
@ in the data segment.
@ CREATE ( address length -- ) Creates a new dictionary entry
@ in the data segment.
defcode "CREATE",6,,CREATE
pop r1 @ length of the word to insert into the dictionnary
pop r0 @ address of the word to insert into the dictionnary
ldr r2,=var_HERE
ldr r3,[r2] @ load into r3 and r8 the location of the header
mov r8,r3
ldr r4,=var_LATEST
ldr r5,[r4] @ load into r5 the link pointer
str r5,[r3] @ store link here -> last
add r3,r3,#4 @ skip link adress
strb r1,[r3] @ store the length of the word
add r3,r3,#1 @ skip the length adress
mov r7,#0 @ initialize the incrementation
1:
cmp r7,r1 @ if the word is completley read
beq 2f
ldrb r6,[r0,r7] @ read and store a character
strb r6,[r3,r7]
add r7,r7,#1 @ ready to rad the next character
b 1b
2:
add r3,r3,r7 @ skip the word
add r3,r3,#3 @ align to next 4 byte boundary
and r3,r3,#~3
str r8,[r4] @ update LATEST and HERE
str r3,[r2]
NEXT
@ , ( n -- ) writes the top element from the stack at HERE
defcode ",",1,,COMMA
pop r0
bl _COMMA
NEXT
_COMMA:
ldr r1, =var_HERE
ldr r2, [r1] @ read HERE
str r0, [r2], #4 @ write value and increment address
str r2, [r1] @ update HERE
bx lr
@ [ ( -- ) Change interpreter state to Immediate mode
defcode "[",1,F_IMMED,LBRAC
ldr r0, =var_STATE
mov r1, #0
str r1, [r0]
NEXT
@ ] ( -- ) Change interpreter state to Compilation mode
defcode "]",1,,RBRAC
ldr r0, =var_STATE
mov r1, #1
str r1, [r0]
NEXT
@ : ( -- ) Define a new forth word
defword ":",1,,COLON
.int WORD @ Get the name of the new word
.int CREATE @ CREATE the dictionary entry / header
.int LIT, DOCOL, COMMA @ Append DOCOL (the codeword).
.int LATEST, FETCH, HIDDEN @ Make the word hidden
@ (see below for definition).
.int RBRAC @ Go into compile mode.
.int EXIT @ Return from the function.
defword ";",1,F_IMMED,SEMICOLON
.int LIT, EXIT, COMMA @ Append EXIT (so the word will return).
.int LATEST, FETCH, HIDDEN @ Toggle hidden flag -- unhide the word
@ (see below for definition).
.int LBRAC @ Go back to IMMEDIATE mode.
.int EXIT @ Return from the function.
@ IMMEDIATE ( -- ) sets IMMEDIATE flag of last defined word
defcode "IMMEDIATE",9,F_IMMED,IMMEDIATE
ldr r0, =var_LATEST @
ldr r1, [r0] @ get the Last word
add r1, r1, #4 @ points to the flag byte
@
mov r2, #0 @
ldrb r2, [r1] @ load the flag into r2
@
eor r2, r2, #F_IMMED @ r2 = r2 xor F_IMMED
strb r2, [r1] @ update the flag
NEXT
@ HIDDEN ( dictionary_address -- ) sets HIDDEN flag of a word
defcode "HIDDEN",6,,HIDDEN
pop r0
ldr r1, [r0, #4]!
eor r1, r1, #F_HIDDEN
str r1, [r0]
NEXT
@ HIDE ( -- ) hide a word
defword "HIDE",4,,HIDE
.int WORD @ Get the word (after HIDE).
.int FIND @ Look up in the dictionary.
.int HIDDEN @ Set F_HIDDEN flag.
.int EXIT @ Return.
@ TICK ( -- ) returns the codeword address of next read word
@ only works in compile mode. Implementation is identical to LIT.
defcode "'",1,,TICK
ldr r1, [IP], #4
push r1
NEXT
@ BRANCH ( -- ) changes IP by offset which is found in the next codeword
defcode "BRANCH",6,,BRANCH
ldr r1, [IP]
add IP, IP, r1
NEXT
@ 0BRANCH ( p -- ) branch if the top of the stack is zero
defcode "0BRANCH",7,,ZBRANCH
pop r0
cmp r0, #0 @ if the top of the stack is zero
beq code_BRANCH @ then branch
add IP, IP, #4 @ else, skip the offset
NEXT
@ LITSTRING ( -- ) as LIT but for strings
defcode "LITSTRING",9,,LITSTRING
ldr r0, [IP], #4 @ read length
push IP @ push address
push r0 @ push string
add IP, IP, r0 @ skip the string
add IP, IP, #3 @ find the next 4-byte boundary
and IP, IP, #~3
NEXT
@ TELL ( addr length -- ) writes a string to stdout
defcode "TELL",4,,TELL
mov r0, #stdout
pop r2 @length
pop r1 @addr
ldr r7, =__NR_write
swi 0
NEXT
@ QUIT ( -- ) the first word to be executed
defword "QUIT", 4,, QUIT
.int RZ, RSPSTORE @ Set up return stack
.int INTERPRET @ Interpret a word
.int BRANCH,-8 @ loop
@ INTERPRET, reads a word from stdin and executes or compiles it
defcode "INTERPRET",9,,INTERPRET
@ No need to backup callee save registers here, since
@ we are the top level routine
mov r8, #0 @ interpret_is_lit = 0
bl _WORD @ read a word from stdin
mov r4, r0 @ store it in r4,r5
mov r5, r1
bl _FIND @ find its dictionary entry
cmp r0, #0 @ if not found go to 1
beq 1f
@ Here the entry is found
ldrb r6, [r0, #4] @ read length and flags field
bl _TCFA @ find code field address
tst r6, #F_IMMED @ if the word is immediate
bne 4f @ branch to 6 (execute)
b 2f @ otherwise, branch to 2
1: @ Not found in dictionary
mov r8, #1 @ interpret_is_lit = 1
mov r0, r4 @ restore word
mov r1, r5
bl _NUMBER @ convert it to number
cmp r1, #0 @ if errors were found
bne 6f @ then fail
@ it's a literal
mov r6, r0 @ keep the parsed number if r6
ldr r0, =LIT @ we will compile a LIT codeword
2: @ Compiling or Executing
ldr r1, =var_STATE @ Are we compiling or executing ?
ldr r1, [r1]
cmp r1, #0
beq 4f @ Go to 4 if in interpret mode
@ Here in compile mode
bl _COMMA @ Call comma to compile the codeword
cmp r8,#1 @ If it's a literal, we have to compile
moveq r0,r6 @ the integer ...
bleq _COMMA @ .. too
NEXT
4: @ Executing
cmp r8,#1 @ if it's a literal, branch to 5
beq 5f
@ not a literal, execute now
ldr r1, [r0] @ (it's important here that
bx r1 @ IP address in r0, since DOCOL
@ assummes it)
5: @ Push literal on the stack
push r6
NEXT
6: @ Parse error
mov r0, #stderr @ Write an error message
ldr r1, =errmsg
mov r2, #(errmsgend-errmsg)
ldr r7, =__NR_write
swi 0
mov r0, #stderr @ with the word that could not be parsed
mov r1, r4
mov r2, r5
ldr r7, =__NR_write
swi 0
mov r0, #stderr
ldr r1, =errmsg2
mov r2, #(errmsg2end-errmsg2)
ldr r7, =__NR_write
swi 0
NEXT
.section .rodata
errmsg: .ascii "PARSE ERROR<"
errmsgend:
errmsg2: .ascii ">\n"
errmsg2end:
@ CHAR ( -- c ) put the ASCII code of the first character of the next word
@ on the stack
defcode "CHAR",4,,CHAR
bl _WORD
ldrb r1, [r0]
push r1
NEXT
@ EXECUTE ( xt -- ) jump to the address on the stack
defcode "EXECUTE",7,,EXECUTE
pop r0
ldr r1, [r0]
bx r1
@ Wrappers for doing syscalls from the forth word
@ SYSCALLX have to be used for a syscall with X arguments
@ In ARM, syscalls arguments must be located in r0-r2 and
@ the syscall index is in r7.
@ The return value is then pushed in the stack.
@ SYSCALLX ( i [arg1 arg2 ar3] -- r )
defcode "SYSCALL3",8,,SYSCALL3
pop r7
pop r0
pop r1
pop r2
swi 0
push r0
NEXT
defcode "SYSCALL2",8,,SYSCALL2
pop r7
pop r0
pop r1
swi 0
push r0
NEXT
defcode "SYSCALL1",8,,SYSCALL1
pop r7
pop r0
swi 0
push r0
NEXT
defcode "SYSCALL0",8,,SYSCALL0
pop r7
swi 0
push r0
NEXT
@ Reserve space for the return stack and the read buffer (for KEY)
.bss
.set RETURN_STACK_SIZE,8192
.set BUFFER_SIZE,4096
.align 12
return_stack:
.space RETURN_STACK_SIZE
return_stack_top:
.align 12
buffer:
.space BUFFER_SIZE
|
maharmstone/ntfs2btrfs | 3,557 | src/crc32c-gas.S | /* Copyright (c) Mark Harmstone 2020
*
* This file is part of WinBtrfs.
*
* WinBtrfs is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public Licence as published by
* the Free Software Foundation, either version 3 of the Licence, or
* (at your option) any later version.
*
* WinBtrfs is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public Licence for more details.
*
* You should have received a copy of the GNU Lesser General Public Licence
* along with WinBtrfs. If not, see <http://www.gnu.org/licenses/>. */
#ifdef __i386__
.intel_syntax noprefix
#ifdef __MINGW32__
.extern _crctable
.global _calc_crc32c_sw@12
.global _calc_crc32c_hw@12
#else
.extern crctable
.global calc_crc32c_sw
.global calc_crc32c_hw
#endif
/* uint32_t __stdcall calc_crc32c_sw(uint32_t seed, uint8_t* msg, uint32_t msglen); */
#ifdef __MINGW32__
_calc_crc32c_sw@12:
#else
calc_crc32c_sw:
#endif
push ebp
mov ebp, esp
push esi
push ebx
mov eax, [ebp+8]
mov edx, [ebp+12]
mov ebx, [ebp+16]
/* eax = crc / seed
* ebx = len
* esi = tmp
* edx = buf
* ecx = tmp2 */
crcloop:
test ebx, ebx
jz crcend
mov esi, eax
shr esi, 8
mov cl, byte ptr [edx]
xor al, cl
and eax, 255
shl eax, 2
#ifdef __MINGW32__
mov eax, [_crctable + eax]
#else
mov eax, [crctable + eax]
#endif
xor eax, esi
inc edx
dec ebx
jmp crcloop
crcend:
pop ebx
pop esi
pop ebp
ret 12
/****************************************************/
/* uint32_t __stdcall calc_crc32c_hw(uint32_t seed, uint8_t* msg, uint32_t msglen); */
#ifdef __MINGW32__
_calc_crc32c_hw@12:
#else
calc_crc32c_hw:
#endif
push ebp
mov ebp, esp
mov eax, [ebp+8]
mov edx, [ebp+12]
mov ecx, [ebp+16]
/* eax = crc / seed
* ecx = len
* edx = buf */
crchw_loop:
cmp ecx, 4
jl crchw_stragglers
crc32 eax, dword ptr [edx]
add edx, 4
sub ecx, 4
jmp crchw_loop
crchw_stragglers:
cmp ecx, 2
jl crchw_stragglers2
crc32 eax, word ptr [edx]
add edx, 2
sub ecx, 2
crchw_stragglers2:
test ecx, ecx
jz crchw_end
crc32 eax, byte ptr [edx]
inc edx
dec ecx
jmp crchw_stragglers2
crchw_end:
pop ebp
ret 12
#elif defined(__x86_64__)
.intel_syntax noprefix
.extern crctable
.global calc_crc32c_sw
.global calc_crc32c_hw
/* uint32_t __stdcall calc_crc32c_sw(uint32_t seed, uint8_t* msg, uint32_t msglen); */
calc_crc32c_sw:
/* rax = crc / seed
* rdx = buf
* r8 = len
* rcx = tmp
* r10 = tmp2
* r11 = crctable */
lea r11, [rip + crctable]
mov rax, rcx
crcloop:
test r8, r8
jz crcend
mov rcx, rax
shr rcx, 8
mov r10b, byte ptr [rdx]
xor al, r10b
and rax, 255
shl rax, 2
mov eax, [r11 + rax]
xor rax, rcx
inc rdx
dec r8
jmp crcloop
crcend:
ret
/****************************************************/
/* uint32_t __stdcall calc_crc32c_hw(uint32_t seed, uint8_t* msg, uint32_t msglen); */
calc_crc32c_hw:
/* rax = crc / seed
* rdx = buf
* r8 = len */
mov rax, rcx
crchw_loop:
cmp r8, 8
jl crchw_stragglers
crc32 rax, qword ptr [rdx]
add rdx, 8
sub r8, 8
jmp crchw_loop
crchw_stragglers:
cmp r8, 4
jl crchw_stragglers2
crc32 eax, dword ptr [rdx]
add rdx, 4
sub r8, 4
crchw_stragglers2:
cmp r8, 2
jl crchw_stragglers3
crc32 eax, word ptr [rdx]
add rdx, 2
sub r8, 2
crchw_stragglers3:
test r8, r8
jz crchw_end
crc32 eax, byte ptr [rdx]
inc rdx
dec r8
jmp crchw_stragglers3
crchw_end:
ret
#endif
#if defined(__linux__) && defined(__ELF__)
.section .note.GNU-stack,"",%progbits
#endif
|
mangpo/greenthumb | 1,045 | arm/programs/p17_p21_o0.s | str r0, [fp, #-24]
str r1, [fp, #-28]
str r2, [fp, #-32]
str r3, [fp, #-36]
ldr r2, [fp, #-24]
ldr r3, [fp, #-36]
cmp r2, r3
movne r3, #0
moveq r3, #1
rsb r3, r3, #0
str r3, [fp, #-20]
ldr r2, [fp, #-28]
ldr r3, [fp, #-36]
eor r3, r2, r3
str r3, [fp, #-16]
ldr r2, [fp, #-24]
ldr r3, [fp, #-28]
cmp r2, r3
movne r3, #0
moveq r3, #1
rsb r3, r3, #0
str r3, [fp, #-12]
ldr r2, [fp, #-32]
ldr r3, [fp, #-36]
eor r3, r2, r3
str r3, [fp, #-8]
ldr r2, [fp, #-20]
ldr r3, [fp, #-16]
and r3, r2, r3
str r3, [fp, #-20]
ldr r2, [fp, #-12]
ldr r3, [fp, #-8]
and r3, r2, r3
str r3, [fp, #-12]
ldr r2, [fp, #-20]
ldr r3, [fp, #-12]
eor r3, r2, r3
str r3, [fp, #-20]
ldr r2, [fp, #-20]
ldr r3, [fp, #-36]
eor r3, r2, r3
mov r0, r3
str r0, [fp, #-16]
ldr r3, [fp, #-16]
sub r3, r3, #1
str r3, [fp, #-8]
ldr r2, [fp, #-8]
ldr r3, [fp, #-16]
orr r3, r2, r3
str r3, [fp, #-8]
ldr r3, [fp, #-8]
add r3, r3, #1
str r3, [fp, #-8]
ldr r2, [fp, #-8]
ldr r3, [fp, #-16]
and r3, r2, r3
mov r0, r3
|
mangpo/greenthumb | 1,731 | arm/programs/p14_p15_p17_p21_o0.s | str r4, [fp, #-16]
str r5, [fp, #-20]
ldr r12, [fp, #-16]
ldr r13, [fp, #-20]
and r13, r12, r13
str r13, [fp, #-12]
ldr r12, [fp, #-16]
ldr r13, [fp, #-20]
eor r13, r12, r13
str r13, [fp, #-8]
ldr r13, [fp, #-8]
mov r13, r13, asr #1
str r13, [fp, #-8]
ldr r12, [fp, #-12]
ldr r13, [fp, #-8]
add r13, r12, r13
mov r4, r13
str r0, [fp, #-16]
str r4, [fp, #-20]
ldr r12, [fp, #-16]
ldr r13, [fp, #-20]
orr r13, r12, r13
str r13, [fp, #-12]
ldr r12, [fp, #-16]
ldr r13, [fp, #-20]
eor r13, r12, r13
str r13, [fp, #-8]
ldr r13, [fp, #-8]
mov r13, r13, asr #1
str r13, [fp, #-8]
ldr r12, [fp, #-12]
ldr r13, [fp, #-8]
rsb r13, r13, r12
mov r0, r13
str r0, [fp, #-24]
str r1, [fp, #-28]
str r2, [fp, #-32]
str r3, [fp, #-36]
ldr r2, [fp, #-24]
ldr r3, [fp, #-36]
cmp r2, r3
movne r3, #0
moveq r3, #1
rsb r3, r3, #0
str r3, [fp, #-20]
ldr r2, [fp, #-28]
ldr r3, [fp, #-36]
eor r3, r2, r3
str r3, [fp, #-16]
ldr r2, [fp, #-24]
ldr r3, [fp, #-28]
cmp r2, r3
movne r3, #0
moveq r3, #1
rsb r3, r3, #0
str r3, [fp, #-12]
ldr r2, [fp, #-32]
ldr r3, [fp, #-36]
eor r3, r2, r3
str r3, [fp, #-8]
ldr r2, [fp, #-20]
ldr r3, [fp, #-16]
and r3, r2, r3
str r3, [fp, #-20]
ldr r2, [fp, #-12]
ldr r3, [fp, #-8]
and r3, r2, r3
str r3, [fp, #-12]
ldr r2, [fp, #-20]
ldr r3, [fp, #-12]
eor r3, r2, r3
str r3, [fp, #-20]
ldr r2, [fp, #-20]
ldr r3, [fp, #-36]
eor r3, r2, r3
mov r0, r3
str r0, [fp, #-16]
ldr r3, [fp, #-16]
sub r3, r3, #1
str r3, [fp, #-8]
ldr r2, [fp, #-8]
ldr r3, [fp, #-16]
orr r3, r2, r3
str r3, [fp, #-8]
ldr r3, [fp, #-8]
add r3, r3, #1
str r3, [fp, #-8]
ldr r2, [fp, #-8]
ldr r3, [fp, #-16]
and r3, r2, r3
mov r0, r3
|
mariopartyrd/marioparty4 | 37,866 | src/TRK_MINNOW_DOLPHIN/__exception.s | .include "macros.inc"
.file "__exception.s"
# 0x80003534..0x80005468 | size: 0x1F34
.section .init, "ax"
.balign 4
# .init:0x0 | 0x80003534 | size: 0x0
.sym gTRKInterruptVectorTable, global
# .init:0x0 | 0x80003534 | size: 0x1F34
.fn pad_00_80003534_init, local
.4byte 0x4D657472
xoris r23, r27, 0x6572
xori r19, r27, 0x2054
ori r18, r11, 0x6765
andis. r0, r1, 0x5265
andi. r9, r27, 0x6465
xoris r20, r19, 0x204b
oris r18, r11, 0x6e65
xoris r0, r1, 0x666f
andi. r0, r17, 0x506f
andis. r5, r27, 0x7250
.L_80003560:
.4byte 0x43000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
b 0x1e34
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mfsrr0 r2
icbi r0, r2
mfdar r2
dcbi r0, r2
mfsprg r2, 1
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x200
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x300
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
# .init:0x348 | 0x8000387C | size: 0x0
.sym lbl_8000387C, global
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
# .init:0x3AC | 0x800038E0 | size: 0x0
.sym lbl_800038E0, global
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x400
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x500
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x600
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x700
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x800
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x900
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0xc00
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0xd00
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0xe00
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
b .L_80004488
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0xf20
rfi
.L_80004488:
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0xf00
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mfcr r2
mtsprg 2, r2
mfmsr r2
andis. r2, r2, 0x2
beq .L_80004564
mfmsr r2
xoris r2, r2, 0x2
sync
mtmsr r2
sync
mtsprg 1, r2
.L_80004564:
mfsprg r2, 2
mtcrf 255, r2
mfsprg r2, 1
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x1000
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mfcr r2
mtsprg 2, r2
mfmsr r2
andis. r2, r2, 0x2
beq .L_80004664
mfmsr r2
xoris r2, r2, 0x2
sync
mtmsr r2
sync
mtsprg 1, r2
.L_80004664:
mfsprg r2, 2
mtcrf 255, r2
mfsprg r2, 1
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x1100
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mfcr r2
mtsprg 2, r2
mfmsr r2
andis. r2, r2, 0x2
beq .L_80004764
mfmsr r2
xoris r2, r2, 0x2
sync
mtmsr r2
sync
mtsprg 1, r2
.L_80004764:
mfsprg r2, 2
mtcrf 255, r2
mfsprg r2, 1
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x1200
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x1300
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x1400
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x1600
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x1700
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x1c00
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x1d00
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x1e00
rfi
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
.4byte 0x00000000
mtsprg 1, r2
mtsprg 2, r3
mtsprg 3, r4
mfsrr0 r2
mfsrr1 r4
mfmsr r3
ori r3, r3, 0x30
mtsrr1 r3
lis r3, 0x800f
ori r3, r3, 0x4a0
mtsrr0 r3
li r3, 0x1f00
rfi
.endfn pad_00_80003534_init
|
marler8997/reloader | 1,324 | c/sys/arch/x86_64/start.s | .global _start
.text
# STACK (Low to High)
# ------------------------------
# RSP --> | argc |
# argv --> | argv[0] |
# | argv[1] |
# | ... |
# | argv[argc] (NULL) |
# envp --> | envp[0] |
# | envp[1] |
# | ... |
# | (NULL) |
_start:
xor %rbp, %rbp # zero the frame pointer register
# I think this helps backtraces know the call stack is over
#
# set argc
#
pop %rdi # RDI(first arg to main) = argc
#
# set argv
#
mov %rsp, %rsi # RSI(second arg to main) = argv (pointer to stack)
#
# set envp
#
mov %rdi, %rdx # first put the argc count into rdx (where env will go)
add $1, %rdx # add 1 to value from argc (handle on NULL pointer after argv)
shl $3, %rdx # multiple argc by 8 (get offset of envp)
add %rsp, %rdx # offset this value from the current stack pointer
#
# prepare stack for main
#
add $-8, %rsp # move stack pointer below argc
and $0xf8, %spl # align stack pointer on 8-byte boundary
call main
#
# exit syscall
#
mov %rax, %rdi # syscall param 1 = rax (return value of main)
mov $60, %rax
syscall
|
marler8997/ziglibc | 1,123 | src/linux/jmp.s | /* Copyright 2011-2012 Nicholas J. Kain, licensed under standard MIT license */
/* NOTE: this was copied from musl */
.global __setjmp
.global _setjmp
.global setjmp
.type __setjmp,@function
.type _setjmp,@function
.type setjmp,@function
__setjmp:
_setjmp:
setjmp:
mov %rbx,(%rdi) /* rdi is jmp_buf, move registers onto it */
mov %rbp,8(%rdi)
mov %r12,16(%rdi)
mov %r13,24(%rdi)
mov %r14,32(%rdi)
mov %r15,40(%rdi)
lea 8(%rsp),%rdx /* this is our rsp WITHOUT current ret addr */
mov %rdx,48(%rdi)
mov (%rsp),%rdx /* save return addr ptr for new rip */
mov %rdx,56(%rdi)
xor %eax,%eax /* always return 0 */
ret
.global _longjmp
.global longjmp
.type _longjmp,@function
.type longjmp,@function
_longjmp:
longjmp:
xor %eax,%eax
cmp $1,%esi /* CF = val ? 0 : 1 */
adc %esi,%eax /* eax = val + !val */
mov (%rdi),%rbx /* rdi is the jmp_buf, restore regs from it */
mov 8(%rdi),%rbp
mov 16(%rdi),%r12
mov 24(%rdi),%r13
mov 32(%rdi),%r14
mov 40(%rdi),%r15
mov 48(%rdi),%rsp
jmp *56(%rdi) /* goto saved address without altering rsp */
|
marqs85/ossc_pro | 2,325 | software/sys_controller/crt0.boot.S | // Copyright 2017 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
#include "pulpino.h"
#define EXCEPTION_STACK_SIZE 72
/* ========================================================= [ entry ] === */
.section .text
default_exc_handler:
jal x0, default_exc_handler
reset_handler:
/* set all registers to zero */
mv x1, x0
mv x2, x1
mv x3, x1
mv x4, x1
mv x5, x1
mv x6, x1
mv x7, x1
mv x8, x1
mv x9, x1
mv x10, x1
mv x11, x1
mv x12, x1
mv x13, x1
mv x14, x1
mv x15, x1
mv x16, x1
mv x17, x1
mv x18, x1
mv x19, x1
mv x20, x1
mv x21, x1
mv x22, x1
mv x23, x1
mv x24, x1
mv x25, x1
mv x26, x1
mv x27, x1
mv x28, x1
mv x29, x1
mv x30, x1
mv x31, x1
/* stack initilization */
la x2, _stack_start
_start:
.global _start
/* clear BSS */
la x26, _bss_start
la x27, _bss_end
bge x26, x27, zero_loop_end
zero_loop:
sw x0, 0(x26)
addi x26, x26, 4
ble x26, x27, zero_loop
zero_loop_end:
copy_sections:
jal alt_load
copy_sections_end:
cache_setup:
fence.i
csrwi 0x7C0, 1
cache_setup_end:
main_entry:
/* jump to alt_main program entry point */
jal alt_main
/* =================================================== [ exceptions ] === */
/* This section has to be down here, since we have to disable rvc for it */
.section .vectors, "ax"
.option norvc;
// external interrupts are handled by the same callback
// until compiler supports IRQ routines
.org 0x00
.rept 31
nop
.endr
jal x0, default_exc_handler
// reset vector
.org 0x80
jal x0, reset_handler
// illegal instruction exception
.org 0x84
jal x0, default_exc_handler
// ecall handler
.org 0x88
jal x0, default_exc_handler
|
marqs85/ossc_pro | 2,117 | software/sys_controller/crt0.boot_E.S | // Copyright 2017 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
#include "pulpino.h"
#define EXCEPTION_STACK_SIZE 72
/* ========================================================= [ entry ] === */
.section .text
default_exc_handler:
jal x0, default_exc_handler
reset_handler:
/* set all registers to zero */
mv x1, x0
mv x2, x1
mv x3, x1
mv x4, x1
mv x5, x1
mv x6, x1
mv x7, x1
mv x8, x1
mv x9, x1
mv x10, x1
mv x11, x1
mv x12, x1
mv x13, x1
mv x14, x1
mv x15, x1
/* stack initilization */
la x2, _stack_start
_start:
.global _start
/* clear BSS */
la x14, _bss_start
la x15, _bss_end
bge x14, x15, zero_loop_end
zero_loop:
sw x0, 0(x14)
addi x14, x14, 4
ble x14, x15, zero_loop
zero_loop_end:
copy_sections:
jal alt_load
copy_sections_end:
cache_setup:
fence.i
csrwi 0x7C0, 1
cache_setup_end:
main_entry:
/* jump to alt_main program entry point */
jal alt_main
/* =================================================== [ exceptions ] === */
/* This section has to be down here, since we have to disable rvc for it */
.section .vectors, "ax"
.option norvc;
// external interrupts are handled by the same callback
// until compiler supports IRQ routines
.org 0x00
.rept 31
nop
.endr
jal x0, default_exc_handler
// reset vector
.org 0x80
jal x0, reset_handler
// illegal instruction exception
.org 0x84
jal x0, default_exc_handler
// ecall handler
.org 0x88
jal x0, default_exc_handler
|
marqs85/ossc_pro | 4,009 | software/sys_controller_bsp/HAL/src/alt_exception_trap.S | /******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the trap exception handler for Nios2.
*/
/*
* Provide a label which can be used to pull this file in.
*/
.section .exceptions.start
.globl alt_exception_trap
alt_exception_trap:
/*
* Pull in the entry/exit code.
*/
.globl alt_exception
.section .exceptions.soft, "xa"
.Ltrap_handler:
/*
* Did a trap instruction cause the exception?
*
* The instruction which the exception occurred on has been loaded
* into r2 by code in alt_exception_entry.S
*
*/
#ifdef ALT_CPU_CPU_ARCH_NIOS2_R2
movhi r3,0xb41d /* upper half of trap opcode */
ori r3,r3,0x0020 /* lower half of trap opcode */
beq r2,r3,.Lis_trap
#ifdef NIOS2_CDX_PRESENT
mov r3,r2
andhi r3,r3,0xffff
ori r3,r3,0xd009 /* trap.n opcode */
beq r2,r3,.Lis_trap
#endif
br .Lnot_trap
#else
movhi r3,0x003b /* upper half of trap opcode */
ori r3,r3,0x683a /* lower half of trap opcode */
bne r2,r3,.Lnot_trap
#endif
.Lis_trap:
/*
* There is no trap handler defined here, and so executing a trap
* instruction causes a software break. If you provide a trap handler,
* then you must replace the break instruction below with your handler.
* Your handler must preserve ea and the usual callee saved registers.
*/
break
br .Lexception_exit
.Lnot_trap:
.section .exceptions.exit.label
.Lexception_exit:
|
marqs85/ossc_pro | 1,919 | software/sys_controller_bsp/HAL/src/alt_log_macro.S | /* alt_log_macro.S
*
* Implements the function tx_log_str, called by the assembly macro
* ALT_LOG_PUTS(). The macro will be empty when logging is turned off,
* and this function will not be compiled. When logging is on,
* this function is used to print out the strings defined in the beginning
* of alt_log_printf.c, using port information taken from system.h and
* alt_log_printf.h.
*
* This routine only handles strings, and sends a character into the defined
* output device's output buffer when the device is ready. It's intended for
* debugging purposes, where messages can be set to print out at certain
* points in the boot code to indicate the progress of the program.
*
*/
#ifndef __ALT_LOG_MACROS__
#define __ALT_LOG_MACROS__
/* define this flag to skip assembly-incompatible parts
* of various include files. */
#define ALT_ASM_SRC
#ifdef ALT_LOG_ENABLE // only compile this function if this flag is defined.
#include "system.h"
#include "sys/alt_log_printf.h"
.global tx_log_str
tx_log_str:
/* load base uart / jtag uart address into r6 */
movhi r6, %hiadj(ALT_LOG_PORT_BASE)
addi r6, r6, %lo(ALT_LOG_PORT_BASE)
tx_next_char:
/* if pointer points to null, return
* r4 is the pointer to the str to be printed, set by ALT_LOG_PUTS */
ldb r7, (r4)
beq r0, r7, end_tx
/* check device transmit ready */
wait_tx_ready_loop:
ldwio r8, ALT_LOG_PRINT_REG_OFFSET(r6)
/*UART, ALT_LOG_PRINT_MSK == 0x40
JTAG UART, ALT_LOG_PRINT_MSK == 0xFFFF0000 */
andhi r5, r8, %hi(ALT_LOG_PRINT_MSK)
andi r8, r8, %lo(ALT_LOG_PRINT_MSK)
or r5, r5, r8
beq r5, r0, wait_tx_ready_loop
/* write char */
stwio r7, ALT_LOG_PRINT_TXDATA_REG_OFFSET (r6)
/* advance string pointer */
addi r4, r4, 1
br tx_next_char
end_tx:
ret
#endif
#endif /* __ALT_LOG_MACROS__ */
|
marqs85/ossc_pro | 8,293 | software/sys_controller_bsp/HAL/src/alt_mcount.S | /******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2010 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/* mcount or _mcount is inserted by GCC before the function prologue of every
* function when a program is compiled for profiling. At the start of mcount,
* we guarantee that:
* ra = self_pc (an address in the function which called mcount)
* r8 = from_pc (an address in the function which called mcount's caller)
*
* Because this is always called at the start of a function we can corrupt
* r2,r3 and r11-r15. We must not corrupt r4-r7 (because they might contain
* function arguments for the instrumented function) or r8 (which holds ra
* for the instrumented function).
*/
.global __mcount_fn_head
.global mcount
/* _mcount is used by gcc4 */
.global _mcount
_mcount:
mcount:
/* Use a hash to speed up locating fn_entry. We use bits 5 upwards to choose
* the bucket because bits 1:0 will always be 0, and because the distribution
* of values for bits 4:2 won't be even (aligning on cache line boundaries
* will skew it). Higher bits should be fairly random.
*/
/* fn_head = mcount_fn_head + (((unsigned int)self_pc >> 5) & (HASH_BUCKETS - 1)); */
srli r2, ra, 3
movhi r3, %hiadj(__mcount_fn_head)
addi r3, r3, %lo(__mcount_fn_head)
andi r2, r2, 0xFC
add r11, r2, r3
/* The fast case is where we have already allocated a function arc, and so
* also a function pointer.
*/
/* First find the function being called (using self_pc) */
mov r10, r11
0:
ldw r10, 0(r10)
beq r10, zero, .Lnew_arc
ldw r2, 4(r10)
bne r2, ra, 0b
/* Found a function entry for this PC. Now look for an arc with a matching
* from_pc value. There will always be at least one arc. */
ldw r3, 8(r10)
0:
ldw r2, 4(r3)
beq r2, r8, .Lfound_arc
ldw r3, 0(r3)
bne r3, zero, 0b
.Lnew_arc:
addi sp, sp, -24
.LCFI0:
stw ra, 0(sp)
stw r4, 4(sp)
stw r5, 8(sp)
stw r6, 12(sp)
stw r7, 16(sp)
stw r8, 20(sp)
.LCFI1:
/* __mcount_record(orig_ra, orig_r8, fn_entry, *fn_head); */
mov r4, ra
mov r5, r8
mov r6, r10
mov r7, r11
call __mcount_record
/* restore registers from the stack */
ldw ra, 0(sp)
ldw r4, 4(sp)
ldw r5, 8(sp)
ldw r6, 12(sp)
ldw r7, 16(sp)
ldw r8, 20(sp)
addi sp, sp, 24
.LCFI2:
ret
.Lfound_arc:
/* We've found the correct arc record. Increment the count and return */
ldw r2, 8(r3)
addi r2, r2, 1
stw r2, 8(r3)
ret
.Lmcount_end:
/*
* Dwarf2 debug information for the function. This provides GDB with the
* information it needs to backtrace out of this function.
*/
.section .debug_frame,"",@progbits
.LCIE:
.4byte 2f - 1f /* Length */
1:
.4byte 0xffffffff /* CIE id */
.byte 0x1 /* Version */
.string "" /* Augmentation */
.uleb128 0x1 /* Code alignment factor */
.sleb128 -4 /* Data alignment factor */
.byte 0x1f /* Return address register */
.byte 0xc /* Define CFA */
.uleb128 0x1b /* Register 27 (sp) */
.uleb128 0x0 /* Offset 0 */
.align 2 /* Padding */
2:
.LFDE_mcount:
.4byte 2f - 1f /* Length */
1:
.4byte .LCIE /* Pointer to CIE */
.4byte mcount /* Start of table entry */
.4byte .Lmcount_end - mcount /* Size of table entry */
.byte 0x4 /* Advance location */
.4byte .LCFI0 - mcount /* to .LCFI0 */
.byte 0xe /* Define CFA offset */
.uleb128 24 /* to 24 */
.byte 0x4 /* Advance location */
.4byte .LCFI1 - .LCFI0 /* to .LCFI1 */
.byte 0x9f /* Store ra */
.uleb128 0x6 /* at CFA-24 */
.byte 0x84 /* Store r4 */
.uleb128 0x5 /* at CFA-20 */
.byte 0x85 /* Store r5 */
.uleb128 0x4 /* at CFA-16 */
.byte 0x86 /* Store r6 */
.uleb128 0x3 /* at CFA-12 */
.byte 0x87 /* Store r7 */
.uleb128 0x2 /* at CFA-8 */
.byte 0x88 /* Store r8 */
.uleb128 0x1 /* at CFA-4 */
.byte 0x4 /* Advance location */
.4byte .LCFI2 - .LCFI1 /* to .LCFI2 */
.byte 0xe /* Define CFA offset */
.uleb128 0 /* to 0 */
.byte 0x8 /* Same value */
.uleb128 31 /* for ra */
.byte 0x8 /* Same value */
.uleb128 4 /* for r4 */
.byte 0x8 /* Same value */
.uleb128 5 /* for r5 */
.byte 0x8 /* Same value */
.uleb128 6 /* for r6 */
.byte 0x8 /* Same value */
.uleb128 7 /* for r7 */
.byte 0x8 /* Same value */
.uleb128 8 /* for r8 */
.align 2
2:
|
marqs85/ossc_pro | 16,181 | software/sys_controller_bsp/HAL/src/alt_exception_entry.S | /******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2008 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
/*
* This is the exception entry point code, which saves all the caller saved
* registers and then handles the appropriate exception. It should be pulled
* in using a .globl from all the exception handler routines. This scheme is
* used so that if an interrupt is never registered, then this code will not
* appear in the generated executable, thereby improving code footprint.
*
* If an external interrpt controller (EIC) is present, it will supply an
* interrupt vector address to the processor when an interrupt occurs. For
* The Altera Vectored Interrupt Controller (VIC) driver will establish a
* vector table and the processor will jump directly to the appropriate
* table entry, funnel routine, and then user ISR. This will bypass this code
* in entirety. This code might still be linked into a system with an EIC,
* but would then be used only for non-interrupt exceptions.
*/
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the assembler.
*/
.set noat
/*
* The top and bottom of the exception stack.
*/
#ifdef ALT_EXCEPTION_STACK
.globl __alt_exception_stack_pointer
#ifdef ALT_STACK_CHECK
.globl __alt_exception_stack_limit
/*
* Store the value of the stack limit after interrupt somewhere.
*/
.globl alt_exception_old_stack_limit
#endif /* ALT_STACK_CHECK */
#endif /* ALT_EXCEPTION_STACK */
/*
* The code at alt_exception is located at the Nios II exception
* handler address.
*/
.section .exceptions.entry.label, "xa"
.globl alt_exception
.type alt_exception, @function
alt_exception:
/*
* The code for detecting a likely fatal ECC exception is
* linked here before the normal exception handler code if required.
* This is handled by the linker script and putting that code
* in the .exceptions.entry.ecc_fatal section.
*/
/*
* Now start the normal exception handler code.
*/
.section .exceptions.entry, "xa"
#ifdef ALT_EXCEPTION_STACK
#ifdef ALT_STACK_CHECK
/*
* When runtime stack checking is enabled, the et register
* contains the stack limit. Save this in memory before
* overwriting the et register.
*/
stw et, %gprel(alt_exception_old_stack_limit)(gp)
#endif /* ALT_STACK_CHECK */
/*
* Switch to the exception stack and save the current stack pointer
* in memory. Uses the et register as a scratch register.
*/
movhi et, %hi(__alt_exception_stack_pointer - 80)
ori et, et, %lo(__alt_exception_stack_pointer - 80)
stw sp, 76(et)
mov sp, et
#ifdef ALT_STACK_CHECK
/*
* Restore the stack limit from memory to the et register.
*/
movhi et, %hi(__alt_exception_stack_limit)
ori et, et, %lo(__alt_exception_stack_limit)
stw et, %gprel(alt_stack_limit_value)(gp)
#endif /* ALT_STACK_CHECK */
#else /* ALT_EXCEPTION_STACK disabled */
/*
* Reserve space on normal stack for registers about to be pushed.
*/
addi sp, sp, -76
#ifdef ALT_STACK_CHECK
/* Ensure stack didn't just overflow. */
bltu sp, et, .Lstack_overflow
#endif /* ALT_STACK_CHECK */
#endif /* ALT_EXCEPTION_STACK */
/*
* Process an exception. For all exceptions we must preserve all
* caller saved registers on the stack (See the Nios II ABI
* documentation for details).
*
* Leave a gap in the stack frame at 4(sp) for the muldiv handler to
* store zero into.
*/
stw ra, 0(sp)
stw r1, 8(sp)
stw r2, 12(sp)
stw r3, 16(sp)
stw r4, 20(sp)
stw r5, 24(sp)
stw r6, 28(sp)
stw r7, 32(sp)
rdctl r5, estatus /* Read early to avoid usage stall */
stw r8, 36(sp)
stw r9, 40(sp)
stw r10, 44(sp)
stw r11, 48(sp)
stw r12, 52(sp)
stw r13, 56(sp)
stw r14, 60(sp)
stw r15, 64(sp)
/*
* ea-4 contains the address of the instruction being executed
* when the exception occured. For interrupt exceptions, we will
* will be re-issue the isntruction. Store it in 72(sp)
*/
stw r5, 68(sp) /* estatus */
addi r15, ea, -4 /* instruction that caused exception */
stw r15, 72(sp)
/*
* The interrupt testing code (.exceptions.irqtest) will be
* linked here. If the Internal Interrupt Controller (IIC) is
* present (an EIC is not present), the presense of an interrupt
* is determined by examining CPU control registers or an interrupt
* custom instruction, if present.
*
* If the IIC is used and an interrupt is active, the code linked
* here will call the HAL IRQ handler (alt_irq_handler()) which
* successively calls registered interrupt handler(s) until no
* interrupts remain pending. It then jumps to .exceptions.exit. If
* there is no interrupt then it continues to .exception.notirq, below.
*/
.section .exceptions.notirq, "xa"
/*
* Prepare to service unimplemtned instructions or traps,
* each of which is optionally inked into section .exceptions.soft,
* which will preceed .exceptions.unknown below.
*
* Unlike interrupts, we want to skip the exception-causing instructon
* upon completion, so we write ea (address of instruction *after*
* the one where the exception occured) into 72(sp). The actual
* instruction that caused the exception is written in r2, which these
* handlers will utilize.
*/
stw ea, 72(sp) /* EA is PC+4 so will skip over instruction causing exception */
#ifdef NIOS2_CDX_PRESENT
mov.n r4, ea /* EA contains PC+4 of instruction that caused the exception */
subi.n r4, r4, 4 /* Calculate PC */
ldhu.n r2, 0(r4) /* Load least-significant 16 bits of instruction */
andi r5, r2, 0x7 /* Mask off all bits except the 3 most-significant bits of OP field */
/*
* These instructions compare the MSB 3 bits of OP to 0x1, 0x3, and 0x5
* which is where all the 16-bit instructions live.
*/
subi.n r5, r5, 1
beqz.n r5, .Lunknown_16bit
subi.n r5, r5, 2
beqz.n r5, .Lunknown_16bit
subi.n r5, r5, 2
beqz.n r5, .Lunknown_16bit
.Lunknown_32bit:
stw ea, 72(sp) /* EA is PC+4 so will skip over instruction causing exception */
/* Load most-significant 16 bits of instruction */
ldhu.n r3, 2(r4)
slli.n r3, r3, 16
or.n r2, r2, r3 /* 32-bit instruction value that caused exception */
br.n .Lunknown_inst_loaded
.Lunknown_16bit:
addi.n r4, r4, 2 /* Need PC+2 to skip over instruction causing exception */
stw r4, 72(sp)
#else /* CDX is not Enabled and all instructions are 32bits */
ldw r2, -4(ea) /* Instruction value that caused exception */
#endif
.Lunknown_inst_loaded:
/*
* Other exception handling code, if enabled, will be linked here.
* This includes unimplemted (multiply/divide) instruction support
* (a BSP generaton option), and a trap handler (that would typically
* be augmented with user-specific code). These are not linked in by
* default.
*/
/*
* In the context of linker sections, "unknown" are all exceptions
* not handled by the built-in handlers above (interupt, and trap or
* unimplemented instruction decoding, if enabled).
*
* Advanced exception types can be serviced by registering a handler.
* To do so, enable the "Enable Instruction-related Exception API" HAL
* BSP setting. If this setting is disabled, this handler code will
* either break (if the debug core is present) or enter an infinite
* loop because we don't how how to handle the exception.
*/
.section .exceptions.unknown
#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
/*
* The C-based HAL routine alt_instruction_exception_entry() will
* attempt to service the exception by calling a user-registered
* exception handler using alt_instruction_exception_register().
* If no handler was registered it will either break (if the
* debugger is present) or go into an infinite loop since the
* handling behavior is undefined; in that case we will not return here.
*/
/* Load exception-causing address as first argument (r4) */
addi r4, ea, -4
/* Call the instruction-exception entry */
call alt_instruction_exception_entry
/*
* If alt_instruction_exception_entry() returned, the exception was
* serviced by a user-registered routine. Its return code (now in r2)
* indicates whether to re-issue or skip the exception-causing
* instruction
*
* Return code was 0: Skip. The instruction after the exception is
* already stored in 72(sp).
*/
bne r2, r0, .Lexception_exit
/*
* Otherwise, modify 72(sp) to re-issue the instruction that caused the
* exception.
*/
addi r15, ea, -4 /* instruction that caused exception */
stw r15, 72(sp)
#else /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API disabled */
/*
* We got here because an instruction-related exception occured, but the
* handler API was not compiled in. We do not presume to know how to
* handle it. If the debugger is present, break, otherwise hang.
*
* If you get here then one of the following could have happened:
*
* - An instruction-generated exception occured, and the processor
* does not have the extra exceptions feature enabled, or you
* have not registered a handler using
* alt_instruction_exception_register()
*
* Some examples of instruction-generated exceptions and why they
* might occur:
*
* - Your program could have been compiled for a full-featured
* Nios II core, but it is running on a smaller core, and
* instruction emulation has been disabled by defining
* ALT_NO_INSTRUCTION_EMULATION.
*
* You can work around the problem by re-enabling instruction
* emulation, or you can figure out why your program is being
* compiled for a system other than the one that it is running on.
*
* - Your program has executed a trap instruction, but has not
* implemented a handler for this instruction.
*
* - Your program has executed an illegal instruction (one which is
* not defined in the instruction set).
*
* - Your processor includes an MMU or MPU, and you have enabled it
* before registering an exception handler to service exceptions it
* generates.
*
* The problem could also be hardware related:
* - If your hardware is broken and is generating spurious interrupts
* (a peripheral which negates its interrupt output before its
* interrupt handler has been executed will cause spurious
* interrupts)
*/
alt_exception_unknown:
#ifdef NIOS2_HAS_DEBUG_STUB
/*
* Either tell the user now (if there is a debugger attached) or go into
* the debug monitor which will loop until a debugger is attached.
*/
break
#else /* NIOS2_HAS_DEBUG_STUB disabled */
/*
* If there is no debug stub, an infinite loop is more useful.
*/
br alt_exception_unknown
#endif /* NIOS2_HAS_DEBUG_STUB */
#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */
.section .exceptions.exit.label
.Lexception_exit:
.section .exceptions.exit, "xa"
/*
* Restore the saved registers, so that all general purpose registers
* have been restored to their state at the time the interrupt occured.
*/
ldw r5, 68(sp)
ldw ea, 72(sp) /* This becomes the PC once eret is executed */
ldw ra, 0(sp)
wrctl estatus, r5
ldw r1, 8(sp)
ldw r2, 12(sp)
ldw r3, 16(sp)
ldw r4, 20(sp)
ldw r5, 24(sp)
ldw r6, 28(sp)
ldw r7, 32(sp)
#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK)
ldw et, %gprel(alt_exception_old_stack_limit)(gp)
#endif
ldw r8, 36(sp)
ldw r9, 40(sp)
ldw r10, 44(sp)
ldw r11, 48(sp)
ldw r12, 52(sp)
ldw r13, 56(sp)
ldw r14, 60(sp)
ldw r15, 64(sp)
#ifdef ALT_EXCEPTION_STACK
#ifdef ALT_STACK_CHECK
stw et, %gprel(alt_stack_limit_value)(gp)
stw zero, %gprel(alt_exception_old_stack_limit)(gp)
#endif /* ALT_STACK_CHECK */
ldw sp, 76(sp)
#else /* ALT_EXCEPTION_STACK disabled */
addi sp, sp, 76
#endif /* ALT_EXCEPTION_STACK */
/*
* Return to the interrupted instruction.
*/
eret
#ifdef ALT_STACK_CHECK
.Lstack_overflow:
break 3
#endif /* ALT_STACK_CHECK */
|
marqs85/ossc_pro | 21,315 | software/sys_controller_bsp/HAL/src/alt_exception_muldiv.S | /******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the software multiply/divide handler for Nios2.
*/
/*
* Provide a label which can be used to pull this file in.
*/
.section .exceptions.start
.globl alt_exception_muldiv
alt_exception_muldiv:
/*
* Pull in the entry/exit code.
*/
.globl alt_exception
.section .exceptions.soft, "xa"
/* INSTRUCTION EMULATION
* ---------------------
*
* Nios II processors generate exceptions for unimplemented instructions.
* The routines below emulate these instructions. Depending on the
* processor core, the only instructions that might need to be emulated
* are div, divu, mul, muli, mulxss, mulxsu, and mulxuu.
*
* The emulations match the instructions, except for the following
* limitations:
*
* 1) The emulation routines do not emulate the use of the exception
* temporary register (et) as a source operand because the exception
* handler already has modified it.
*
* 2) The routines do not emulate the use of the stack pointer (sp) or the
* exception return address register (ea) as a destination because
* modifying these registers crashes the exception handler or the
* interrupted routine.
*
* 3) To save code size, the routines do not emulate the use of the
* breakpoint registers (ba and bt) as operands.
*
* Detailed Design
* ---------------
*
* The emulation routines expect the contents of integer registers r0-r31
* to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp). The
* routines retrieve source operands from the stack and modify the
* destination register's value on the stack prior to the end of the
* exception handler. Then all registers except the destination register
* are restored to their previous values.
*
* The instruction that causes the exception is found at address -4(ea).
* The instruction's OP and OPX fields identify the operation to be
* performed.
*
* One instruction, muli, is an I-type instruction that is identified by
* an OP field of 0x24.
*
* muli AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24-
* 27 22 6 0 <-- LSB of field
*
* The remaining emulated instructions are R-type and have an OP field
* of 0x3a. Their OPX fields identify them.
*
* R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a-
* 27 22 17 11 6 0 <-- LSB of field
*
*
*/
/*
* Split the instruction into its fields. We need 4*A, 4*B, and 4*C as
* offsets to the stack pointer for access to the stored register values.
*/
/* r2 = AAAAA,BBBBB,IIIIIIIIIIIIIIII,PPPPPP */
roli r3, r2, 7 /* r3 = BBB,IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BB */
roli r4, r3, 3 /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB */
roli r6, r4, 2 /* r6 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II */
srai r4, r4, 16 /* r4 = (sign-extended) IMM16 */
xori r6, r6, 0x42 /* r6 = CCC,XXXXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cC */
roli r7, r6, 5 /* r7 = XXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cCCCC,XX */
andi r5, r2, 0x3f /* r5 = 00000000000000000000000000,PPPPPP */
xori r3, r3, 0x40
andi r3, r3, 0x7c /* r3 = 0000000000000000000000000,aAAAA,00 */
andi r6, r6, 0x7c /* r6 = 0000000000000000000000000,bBBBB,00 */
andi r7, r7, 0x7c /* r7 = 0000000000000000000000000,cCCCC,00 */
/* Now either
* r5 = OP
* r3 = 4*(A^16)
* r4 = IMM16 (sign extended)
* r6 = 4*(B^16)
* r7 = 4*(C^16)
* or
* r5 = OP
*/
/*
* Save everything on the stack to make it easy for the emulation routines
* to retrieve the source register operands. The exception entry code has
* already saved some of this so we don't need to do it all again.
*/
addi sp, sp, -60
stw zero, 64(sp) /* Save zero on stack to avoid special case for r0. */
/* Register at and r2-r15 have already been saved. */
stw r16, 0(sp)
stw r17, 4(sp)
stw r18, 8(sp)
stw r19, 12(sp)
stw r20, 16(sp)
stw r21, 20(sp)
stw r22, 24(sp)
stw r23, 28(sp)
/* et @ 32 - Has already been changed.*/
/* bt @ 36 - Usually isn't an operand. */
stw gp, 40(sp)
stw sp, 44(sp)
stw fp, 48(sp)
/* ea @ 52 - Don't bother to save - it's already been changed */
/* ba @ 56 - Breakpoint register usually isn't an operand */
/* ra @ 60 - Has already been saved */
/*
* Prepare for either multiplication or division loop.
* They both loop 32 times.
*/
movi r14, 32
/*
* Get the operands.
*
* It is necessary to check for muli because it uses an I-type instruction
* format, while the other instructions are have an R-type format.
*/
add r3, r3, sp /* r3 = address of A-operand. */
ldw r3, 0(r3) /* r3 = A-operand. */
movi r15, 0x24 /* muli opcode (I-type instruction format) */
beq r5, r15, .Lmul_immed /* muli doesn't use the B register as a source */
add r6, r6, sp /* r6 = address of B-operand. */
ldw r6, 0(r6) /* r6 = B-operand. */
/* r4 = SSSSSSSSSSSSSSSS,-----IMM16------ */
/* IMM16 not needed, align OPX portion */
/* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */
srli r4, r4, 5 /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */
andi r4, r4, 0x3f /* r4 = 00000000000000000000000000,-OPX-- */
/* Now
* r5 = OP
* r3 = src1
* r6 = src2
* r4 = OPX (no longer can be muli)
* r7 = 4*(C^16)
* r14 = loop counter
*/
/* ILLEGAL-INSTRUCTION EXCEPTION
* -----------------------------
*
* This code is for Nios II cores that generate exceptions when attempting
* to execute illegal instructions. Nios II cores that support an
* illegal-instruction exception are identified by the presence of the
* macro definition NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION in system.h .
*
* Remember that illegal instructions are different than unimplemented
* instructions. Illegal instructions are instruction encodings that
* have not been defined by the Nios II ISA. Unimplemented instructions
* are legal instructions that must be emulated by some Nios II cores.
*
* If we get here, all instructions except multiplies and divides
* are illegal.
*
* This code assumes that OP is not muli (because muli was tested above).
* All other multiplies and divides are legal. Anything else is illegal.
*/
movi r8, 0x3a /* OP for R-type mul* and div* */
bne r5, r8, .Lnot_muldiv
/* r15 already is 0x24 */ /* OPX of divu */
beq r4, r15, .Ldivide
movi r15,0x27 /* OPX of mul */
beq r4, r15, .Lmultiply
movi r15,0x07 /* OPX of mulxuu */
beq r4, r15, .Lmultiply
movi r15,0x17 /* OPX of mulxsu */
beq r4, r15, .Lmultiply
movi r15,0x1f /* OPX of mulxss */
beq r4, r15, .Lmultiply
movi r15,0x25 /* OPX of div */
bne r4, r15, .Lnot_muldiv
/* DIVISION
*
* Divide an unsigned dividend by an unsigned divisor using
* a shift-and-subtract algorithm. The example below shows
* 43 div 7 = 6 for 8-bit integers. This classic algorithm uses a
* single register to store both the dividend and the quotient,
* allowing both values to be shifted with a single instruction.
*
* remainder dividend:quotient
* --------- -----------------
* initialize 00000000 00101011:
* shift 00000000 0101011:_
* remainder >= divisor? no 00000000 0101011:0
* shift 00000000 101011:0_
* remainder >= divisor? no 00000000 101011:00
* shift 00000001 01011:00_
* remainder >= divisor? no 00000001 01011:000
* shift 00000010 1011:000_
* remainder >= divisor? no 00000010 1011:0000
* shift 00000101 011:0000_
* remainder >= divisor? no 00000101 011:00000
* shift 00001010 11:00000_
* remainder >= divisor? yes 00001010 11:000001
* remainder -= divisor - 00000111
* ----------
* 00000011 11:000001
* shift 00000111 1:000001_
* remainder >= divisor? yes 00000111 1:0000011
* remainder -= divisor - 00000111
* ----------
* 00000000 1:0000011
* shift 00000001 :0000011_
* remainder >= divisor? no 00000001 :00000110
*
* The quotient is 00000110.
*/
.Ldivide:
/*
* Prepare for division by assuming the result
* is unsigned, and storing its "sign" as 0.
*/
movi r17, 0
/* Which division opcode? */
xori r15, r4, 0x25 /* OPX of div */
bne r15, zero, .Lunsigned_division
/*
* OPX is div. Determine and store the sign of the quotient.
* Then take the absolute value of both operands.
*/
xor r17, r3, r6 /* MSB contains sign of quotient */
bge r3, zero, 0f
sub r3, zero, r3 /* -r3 */
0:
bge r6, zero, 0f
sub r6, zero, r6 /* -r6 */
0:
.Lunsigned_division:
/* Initialize the unsigned-division loop. */
movi r13, 0 /* remainder = 0 */
/* Now
* r3 = dividend : quotient
* r4 = 0x25 for div, 0x24 for divu
* r6 = divisor
* r13 = remainder
* r14 = loop counter (already initialized to 32)
* r17 = MSB contains sign of quotient
*/
/*
* for (count = 32; count > 0; --count)
* {
*/
.Ldivide_loop:
/*
* Division:
*
* (remainder:dividend:quotient) <<= 1;
*/
slli r13, r13, 1
cmplt r15, r3, zero /* r15 = MSB of r3 */
or r13, r13, r15
slli r3, r3, 1
/*
* if (remainder >= divisor)
* {
* set LSB of quotient
* remainder -= divisor;
* }
*/
bltu r13, r6, .Ldiv_skip
ori r3, r3, 1
sub r13, r13, r6
.Ldiv_skip:
/*
* }
*/
subi r14, r14, 1
bne r14, zero, .Ldivide_loop
mov r9, r3
/* Now
* r9 = quotient
* r4 = 0x25 for div, 0x24 for divu
* r7 = 4*(C^16)
* r17 = MSB contains sign of quotient
*/
/*
* Conditionally negate signed quotient. If quotient is unsigned,
* the sign already is initialized to 0.
*/
bge r17, zero, .Lstore_result
sub r9, zero, r9 /* -r9 */
br .Lstore_result
/* MULTIPLICATION
*
* A "product" is the number that one gets by summing a "multiplicand"
* several times. The "multiplier" specifies the number of copies of the
* multiplicand that are summed.
*
* Actual multiplication algorithms don't use repeated addition, however.
* Shift-and-add algorithms get the same answer as repeated addition, and
* they are faster. To compute the lower half of a product (pppp below)
* one shifts the product left before adding in each of the partial products
* (a * mmmm) through (d * mmmm).
*
* To compute the upper half of a product (PPPP below), one adds in the
* partial products (d * mmmm) through (a * mmmm), each time following the
* add by a right shift of the product.
*
* mmmm
* * abcd
* ------
* #### = d * mmmm
* #### = c * mmmm
* #### = b * mmmm
* #### = a * mmmm
* --------
* PPPPpppp
*
* The example above shows 4 partial products. Computing actual Nios II
* products requires 32 partials.
*
* It is possible to compute the result of mulxsu from the result of mulxuu
* because the only difference between the results of these two opcodes is
* the value of the partial product associated with the sign bit of rA.
*
* mulxsu = mulxuu - ((rA < 0) ? rB : 0);
*
* It is possible to compute the result of mulxss from the result of mulxsu
* because the only difference between the results of these two opcodes is
* the value of the partial product associated with the sign bit of rB.
*
* mulxss = mulxsu - ((rB < 0) ? rA : 0);
*
*/
.Lmul_immed:
/* Opcode is muli. Change it into mul for remainder of algorithm. */
mov r7, r6 /* Field B is dest register, not field C. */
mov r6, r4 /* Field IMM16 is src2, not field B. */
movi r4, 0x27 /* OPX of mul is 0x27 */
.Lmultiply:
/* Initialize the multiplication loop. */
movi r9, 0 /* mul_product = 0 */
movi r10, 0 /* mulxuu_product = 0 */
mov r11, r6 /* save original multiplier for mulxsu and mulxss */
mov r12, r6 /* mulxuu_multiplier (will be shifted) */
movi r16, 1 /* used to create "rori B,A,1" from "ror B,A,r16" */
/* Now
* r3 = multiplicand
* r6 = mul_multiplier
* r7 = 4 * dest_register (used later as offset to sp)
* r9 = mul_product
* r10 = mulxuu_product
* r11 = original multiplier
* r12 = mulxuu_multiplier
* r14 = loop counter (already initialized)
* r15 = temp
* r16 = 1
*/
/*
* for (count = 32; count > 0; --count)
* {
*/
.Lmultiply_loop:
/*
* mul_product <<= 1;
* lsb = multiplier & 1;
*/
slli r9, r9, 1
andi r15, r12, 1
/*
* if (lsb == 1)
* {
* mulxuu_product += multiplicand;
* }
*/
beq r15, zero, .Lmulx_skip
add r10, r10, r3
cmpltu r15, r10, r3 /* Save the carry from the MSB of mulxuu_product. */
ror r15, r15, r16 /* r15 = 0x80000000 on carry, or else 0x00000000 */
.Lmulx_skip:
/*
* if (MSB of mul_multiplier == 1)
* {
* mul_product += multiplicand;
* }
*/
bge r6, zero, .Lmul_skip
add r9, r9, r3
.Lmul_skip:
/*
* mulxuu_product >>= 1; logical shift
* mul_multiplier <<= 1; done with MSB
* mulx_multiplier >>= 1; done with LSB
*/
srli r10, r10, 1
or r10, r10, r15 /* OR in the saved carry bit. */
slli r6, r6, 1
srli r12, r12, 1
/*
* }
*/
subi r14, r14, 1
bne r14, zero, .Lmultiply_loop
/*
* Multiply emulation loop done.
*/
/* Now
* r3 = multiplicand
* r4 = OPX
* r7 = 4 * dest_register (used later as offset to sp)
* r9 = mul_product
* r10 = mulxuu_product
* r11 = original multiplier
* r15 = temp
*/
/*
* Select/compute the result based on OPX.
*/
/* OPX == mul? Then store. */
xori r15, r4, 0x27
beq r15, zero, .Lstore_result
/* It's one of the mulx.. opcodes. Move over the result. */
mov r9, r10
/* OPX == mulxuu? Then store. */
xori r15, r4, 0x07
beq r15, zero, .Lstore_result
/* Compute mulxsu
*
* mulxsu = mulxuu - ((rA < 0) ? rB : 0);
*/
bge r3, zero, .Lmulxsu_skip
sub r9, r9, r11
.Lmulxsu_skip:
/* OPX == mulxsu? Then store. */
xori r15, r4, 0x17
beq r15, zero, .Lstore_result
/* Compute mulxss
*
* mulxss = mulxsu - ((rB < 0) ? rA : 0);
*/
bge r11, zero, .Lmulxss_skip
sub r9, r9, r3
.Lmulxss_skip:
/* At this point, assume that OPX is mulxss, so store */
.Lstore_result:
add r7, r7, sp
stw r9, 0(r7)
ldw r16, 0(sp)
ldw r17, 4(sp)
ldw r18, 8(sp)
ldw r19, 12(sp)
ldw r20, 16(sp)
ldw r21, 20(sp)
ldw r22, 24(sp)
ldw r23, 28(sp)
/* bt @ 32 - Breakpoint register usually isn't an operand. */
/* et @ 36 - Don't corrupt et. */
/* gp @ 40 - Don't corrupt gp. */
/* sp @ 44 - Don't corrupt sp. */
ldw fp, 48(sp)
/* ea @ 52 - Don't corrupt ea. */
/* ba @ 56 - Breakpoint register usually isn't an operand. */
addi sp, sp, 60
br .Lexception_exit
.Lnot_muldiv:
addi sp, sp, 60
.section .exceptions.exit.label
.Lexception_exit:
|
marqs85/ossc_pro | 16,585 | software/sys_controller_bsp/HAL/src/crt0.S | /******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
#include "nios2.h"
/* Setup header files to work with assembler code. */
#define ALT_ASM_SRC
/* Debug logging facility */
#include "sys/alt_log_printf.h"
/*************************************************************************\
| MACROS |
\*************************************************************************/
/*
* The new build tools explicitly define macros when alt_load()
* must be called. The define ALT_LOAD_EXPLICITLY_CONTROLLED tells us that
* those macros are controlling if alt_load() needs to be called.
*/
#ifdef ALT_LOAD_EXPLICITLY_CONTROLLED
/* Need to call alt_load() if any of these sections are being copied. */
#if defined(ALT_LOAD_COPY_RODATA) || defined(ALT_LOAD_COPY_RWDATA) || defined(ALT_LOAD_COPY_EXCEPTIONS)
#define CALL_ALT_LOAD
#endif
#else /* !ALT_LOAD_EXPLICITLY_CONTROLLED */
/*
* The legacy build tools use the following macros to detect when alt_load()
* needs to be called.
*/
#define __ALT_LOAD_SECTIONS(res, text, rodata, exc) \
((res##_BASE != rodata##_BASE) || \
(res##_BASE != rwdata##_BASE) || \
(res##_BASE != exc##_BASE))
#define _ALT_LOAD_SECTIONS(res, text, rodata, exc) \
__ALT_LOAD_SECTIONS(res, text, rodata, exc)
#define ALT_LOAD_SECTIONS _ALT_LOAD_SECTIONS(ALT_RESET_DEVICE, \
ALT_RODATA_DEVICE, \
ALT_RWDATA_DEVICE, \
ALT_EXCEPTIONS_DEVICE)
/* Call alt_load() if there is no bootloader and ALT_LOAD_SECTIONS isn't 0. */
#if defined(ALT_NO_BOOTLOADER) && ALT_LOAD_SECTIONS
#define CALL_ALT_LOAD
#endif
#endif /* !ALT_LOAD_EXPLICITLY_CONTROLLED */
/*
* When the legacy build tools define a macro called ALT_NO_BOOTLOADER,
* it indicates that initialization code is allowed at the reset address.
* The new build tools define a macro called ALT_ALLOW_CODE_AT_RESET for
* the same purpose.
*/
#ifdef ALT_NO_BOOTLOADER
#define ALT_ALLOW_CODE_AT_RESET
#endif
/*************************************************************************\
| EXTERNAL REFERENCES |
\*************************************************************************/
/*
* The entry point for user code is either "main" in hosted mode, or
* "alt_main" in standalone mode. These are explicitly referenced here,
* to ensure they are built into the executable. This allows the user
* to build them into libraries, rather than supplying them in object
* files at link time.
*/
.globl main
.globl alt_main
/*
* Create a reference to the software multiply/divide and trap handers,
* so that if they are provided, they will appear in the executable.
*/
#ifndef ALT_NO_INSTRUCTION_EMULATION
.globl alt_exception_muldiv
#endif
#ifdef ALT_TRAP_HANDLER
.globl alt_exception_trap
#endif
/*
* Linker defined symbols used to initialize bss.
*/
.globl __bss_start
.globl __bss_end
/*************************************************************************\
| RESET SECTION (.entry) |
\*************************************************************************/
/*
* This is the reset entry point for Nios II.
*
* At reset, only the cache line which contain the reset vector is
* initialized by the hardware. The code within the first cache line
* initializes the remainder of the instruction cache.
*/
.section .entry, "xa"
.align 5
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the assembler.
*/
.set noat
/*
* Some tools want to know where the reset vector is.
* Code isn't always provided at the reset vector but at least the
* __reset label always contains the reset vector address because
* it is defined at the start of the .entry section.
*/
.globl __reset
.type __reset, @function
__reset:
/*
* Initialize the instruction cache if present (i.e. size > 0) and
* reset code is allowed unless optimizing for RTL simulation.
* RTL simulations can ensure the instruction cache is already initialized
* so skipping this loop speeds up RTL simulation.
*
* When ECC is present, need to execute initi for each word address
* to ensure ECC parity bits in cache RAM get initialized.
*/
#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && (!defined(ALT_SIM_OPTIMIZE) || defined(NIOS2_ECC_PRESENT))
/* Assume the instruction cache size is always a power of two. */
#if NIOS2_ICACHE_SIZE > 0x8000
movhi r2, %hi(NIOS2_ICACHE_SIZE)
#else
movui r2, NIOS2_ICACHE_SIZE
#endif
0:
initi r2
addi r2, r2, -NIOS2_ICACHE_LINE_SIZE
bgt r2, zero, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 1, 1, 0b, 1b
.popsection
#endif /* Initialize Instruction Cache */
/*
* Jump to the _start entry point in the .text section if reset code
* is allowed or if optimizing for RTL simulation.
*/
#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE)
/* Jump to the _start entry point in the .text section. */
movhi r1, %hi(_start)
ori r1, r1, %lo(_start)
jmp r1
.size __reset, . - __reset
#endif /* Jump to _start */
/*
* When not using exit, provide an _exit symbol to prevent unresolved
* references to _exit from the linker script.
*/
#ifdef ALT_NO_EXIT
.globl _exit
_exit:
#endif
/*************************************************************************\
| TEXT SECTION (.text) |
\*************************************************************************/
/*
* Start of the .text section, and also the code entry point when
* the code is executed by a bootloader rather than directly from reset.
*/
.section .text
.align 2
.globl _start
.type _start, @function
_start:
#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0)
/*
* Ensure that the current register set is 0 upon
* entry to this code. Switch register set to 0 by
* writing zero to SSTATUS register and executing an ERET instruction
* to set STATUS.CRS to 0.
*/
/* Get the current register set number (STATUS.CRS). */
rdctl r2, status
andi r2, r2, NIOS2_STATUS_CRS_MSK
/* Skip switching register set if STATUS.CRS is 0. */
beq r2, zero, 0f
/* Set SSTATUS to 0 to get to set SSTATUS.PRS to 0. */
.set nobreak
movui sstatus, 0
.set break
/* Switch to register set 0 and jump to label. */
movhi ea, %hi(0f)
ori ea, ea, %lo(0f)
eret
0:
#endif /* NIOS2_NUM_OF_SHADOW_REG_SETS > 0 */
/*
* Initialize the data cache if present (i.e. size > 0).
* Skip initialization if optimizing for RTL simulation and ECC isn't present.
* RTL simulations can ensure the data cache tag RAM is already initialized
* (but not the data RAM for ECC) so skipping this speeds up RTL simulation.
*
* When ECC is present, need to execute initd for each word address
* to ensure ECC parity bits in data RAM get initialized.
* Otherwise, only need to execute initd for each line address.
*/
#if NIOS2_DCACHE_SIZE > 0 && (!defined(ALT_SIM_OPTIMIZE) || defined(NIOS2_ECC_PRESENT))
/* Assume the data cache size is always a power of two. */
#if NIOS2_DCACHE_SIZE > 0x8000
movhi r2, %hi(NIOS2_DCACHE_SIZE)
#else
movui r2, NIOS2_DCACHE_SIZE
#endif
0:
initd 0(r2)
#ifdef NIOS2_ECC_PRESENT
addi r2, r2, -4
#else
addi r2, r2, -NIOS2_DCACHE_LINE_SIZE
#endif
bgt r2, zero, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 2, 1, 0b, 1b
.popsection
#endif /* Initialize Data Cache */
/* Log that caches have been initialized. */
ALT_LOG_PUTS(alt_log_msg_cache)
/* Log that the stack pointer is about to be setup. */
ALT_LOG_PUTS(alt_log_msg_stackpointer)
/*
* Now that the caches are initialized, set up the stack pointer and global pointer.
* The values provided by the linker are assumed to be correctly aligned.
*/
movhi sp, %hi(__alt_stack_pointer)
ori sp, sp, %lo(__alt_stack_pointer)
movhi gp, %hi(_gp)
ori gp, gp, %lo(_gp)
#ifdef NIOS2_ECC_PRESENT
/*
* Initialize all general-purpose registers so that ECC can be enabled
* later without accidentally triggering a spurious ECC error.
*/
movui r1, 0
movui r2, 0
movui r3, 0
movui r4, 0
movui r5, 0
movui r6, 0
movui r7, 0
movui r8, 0
movui r9, 0
movui r10, 0
movui r11, 0
movui r12, 0
movui r13, 0
movui r14, 0
movui r15, 0
movui r16, 0
movui r17, 0
movui r18, 0
movui r19, 0
movui r20, 0
movui r21, 0
movui r22, 0
movui r23, 0
/* Skip r24 (et) because only exception handler should write it. */
/* Skip r25 (bt) because only debugger should write it. */
/* Skip r26 (gp) because it is already been initialized. */
/* Skip r27 (sp) because it is already been initialized. */
movui r28, 0 /* fp */
movui r29, 0 /* ea */
.set nobreak
movui r30, 0 /* sstatus */
.set break
movui r31, 0 /* ra */
#endif /* NIOS2_ECC_PRESENT */
#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0)
/*
* Setup registers in shadow register sets
* from 1 to NIOS2_NUM_OF_SHADOW_REG_SETS.
*/
movui r2, 0 /* Contains value written into STATUS */
movui r3, NIOS2_NUM_OF_SHADOW_REG_SETS /* counter */
movhi r4, 1 /* Constant to increment STATUS.PRS */
.Linitialize_shadow_registers:
/* Increment STATUS.PRS */
add r2, r2, r4
wrctl status, r2
/* Clear r0 in the shadow register set (not done by hardware) */
wrprs r0, r0
/* Write the GP in previous register set */
wrprs gp, gp
/*
* Only write the SP in previous register set
* if using the separate exception stack. For normal case (single stack),
* funnel code would read the SP from previous register set with a RDPRS.
*/
#ifdef ALT_INTERRUPT_STACK
movhi et, %hiadj(__alt_interrupt_stack_pointer)
addi et, et, %lo(__alt_interrupt_stack_pointer)
wrprs sp, et
#endif /* ALT_INTERRUPT_STACK */
#ifdef NIOS2_ECC_PRESENT
/*
* Initialize all general-purpose registers so that ECC can be enabled
* later without accidentally triggering a spurious ECC error.
*/
wrprs r1, r0
wrprs r2, r0
wrprs r3, r0
wrprs r4, r0
wrprs r5, r0
wrprs r6, r0
wrprs r7, r0
wrprs r8, r0
wrprs r9, r0
wrprs r10, r0
wrprs r11, r0
wrprs r12, r0
wrprs r13, r0
wrprs r14, r0
wrprs r15, r0
wrprs r16, r0
wrprs r17, r0
wrprs r18, r0
wrprs r19, r0
wrprs r20, r0
wrprs r21, r0
wrprs r22, r0
wrprs r23, r0
/* Skip r24 (et) because only exception handler should write it. */
/* Skip r25 (bt) because only debugger should write it. */
/* Skip r26 (gp) because it is already been initialized. */
/* Skip r27 (sp) because it was initialized above or will be by a rdprs if not above */
wrprs r28, r0 /* fp */
wrprs r29, r0 /* ea */
wrprs r30, r0 /* ba */
wrprs r31, r0 /* ra */
#endif /* NIOS2_ECC_PRESENT */
/* Decrement shadow register set counter */
addi r3, r3, -1
/* Done if index is 0. */
bne r3, zero, .Linitialize_shadow_registers
#endif /* (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) */
/*
* Clear the BSS if not optimizing for RTL simulation.
*
* This uses the symbols: __bss_start and __bss_end, which are defined
* by the linker script. They mark the begining and the end of the bss
* region. The linker script guarantees that these values are word aligned.
*/
#ifndef ALT_SIM_OPTIMIZE
/* Log that the BSS is about to be cleared. */
ALT_LOG_PUTS(alt_log_msg_bss)
movhi r2, %hi(__bss_start)
ori r2, r2, %lo(__bss_start)
movhi r3, %hi(__bss_end)
ori r3, r3, %lo(__bss_end)
beq r2, r3, 1f
0:
stw zero, (r2)
addi r2, r2, 4
bltu r2, r3, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 3, 1, 0b, 1b
.popsection
#endif /* ALT_SIM_OPTIMIZE */
/*
* Turn off the use of r1 (the assembler temporary register)
* so that call instructions can be safely relaxed across a
* 256MB boundary if needed
*/
.set at
/*
* The alt_load() facility is normally used when there is no bootloader.
* It copies some sections into RAM so it acts like a mini-bootloader.
*/
#ifdef CALL_ALT_LOAD
#ifdef ALT_STACK_CHECK
/*
* If the user has selected stack checking then we need to set up a safe
* value in the stack limit register so that the relocation functions
* don't think the stack has overflowed (the contents of the rwdata
* section aren't defined until alt_load() has been called).
*/
mov et, zero
#endif
call alt_load
#endif /* CALL_ALT_LOAD */
#ifdef ALT_STACK_CHECK
/*
* Set up the stack limit (if required). The linker has set up the
* copy of the variable which is in memory.
*/
ldw et, %gprel(alt_stack_limit_value)(gp)
#endif
/* Log that alt_main is about to be called. */
ALT_LOG_PUTS(alt_log_msg_alt_main)
/* Call the C entry point. It should never return. */
call alt_main
/* Wait in infinite loop in case alt_main does return. */
alt_after_alt_main:
br alt_after_alt_main
.size _start, . - _start
/*
* Add information about the stack base if stack overflow checking is enabled.
*/
#ifdef ALT_STACK_CHECK
.globl alt_stack_limit_value
.section .sdata,"aws",@progbits
.align 2
.type alt_stack_limit_value, @object
.size alt_stack_limit_value, 4
alt_stack_limit_value:
.long __alt_stack_limit
#endif
|
marqs85/ossc_pro | 2,989 | software/sys_controller_bsp/HAL/src/alt_software_exception.S | /******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This file provides the global symbol: software_exception. It is provided to
* support legacy code, and should not be used by new software.
*
* It is used by legacy code to invoke the software exception handler as
* defined by version 1.0 of the Nios II kit. It should only be used when you
* are providing your own interrupt entry point, i.e. you are not using
* alt_irq_entry.
*/
#include "system.h"
/*
* Pull in the exception handler.
*/
.globl alt_exception
.section .exceptions.entry.label, "xa"
.globl software_exception
.type software_exception, @function
software_exception:
|
marqs85/ossc_pro | 5,245 | software/sys_controller_bsp/HAL/src/alt_ecc_fatal_entry.S | /******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the code called at the beginning of the exception handler
* to detect a likely fatal ECC error exception and then jump to
* user-provided code to handle it.
*
* This code is pulled in from a .globl in alt_ecc_fatal_exception.c.
* This scheme is used so that if a handler is never registered, then this
* code will not appear in the generated executable, thereby improving
* code footprint.
*
* This code is located in its own section that the linker script
* explicitly mentions and ensures it gets linked at the beginning
* of the exception handler.
*/
/*
* Pull in the exception handler register save code.
*/
.globl alt_exception
.section .exceptions.entry.ecc_fatal, "xa"
/*
* This might be handling an unrecoverable ECC error exception
* in the register file and/or data cache.
* Must avoid reading registers or performing load/store instructions
* before this is determined because they could trigger another
* unrecoverable ECC error exception and create an infinite loop.
*
* The EXCEPTION register is always present when ECC is present.
* Bit 31 of this register indicates that there was an unrecoverable
* ECC error exception in the register file and/or data cache.
* Test this (using blt to check sign bit) to determine if this is
* what we are dealing with. Otherwise, just do normal processing.
*
* Jump to an application-provided routine to handle this condition.
* Pass in the return address in the et register in case this code
* can clean up the ECC error and then return here (unlikely).
*
* Runtime stack checking can't be enabled when ECC is present
* because they both want to use the et register.
*/
rdctl et, exception
bge et, r0, alt_exception_not_ecc_fatal /* Not ECCFTL if bit 31 is 0 */
/*
* Load ECC fatal handler pointer into et register.
* Using a ldwio is safe because it completely bypasses the data cache.
*/
movhi et, %hi(alt_exception_ecc_fatal_handler)
ori et, et, %lo(alt_exception_ecc_fatal_handler)
ldwio et, 0(et)
/*
* If ECC fatal handler pointer is not 0, assume a handler
* has been provided by the application.
*/
beq et, r0, alt_exception_not_ecc_fatal
/*
* The et register contains the address of the ECC fatal handler.
* Jump to this address to invoke the handler.
*/
jmp et
/*
* An ECC fatal handler can jump to this label if it able
* to recover from the fatal error (rare) and wants to continue
* with normal exception processing.
*/
.globl alt_exception_not_ecc_fatal
alt_exception_not_ecc_fatal:
|
marqs85/ossc_pro | 4,685 | software/sys_controller_bsp/HAL/src/alt_irq_entry.S | /******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
/*
* This is the interrupt exception entry point code, which saves all the
* registers and calls the interrupt handler. It should be pulled in using
* a .globl from alt_irq_register.c. This scheme is used so that if an
* interrupt is never registered, then this code will not appear in the
* generated executable, thereby improving code footprint.
*/
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the compiler.
*/
.set noat
/*
* Pull in the exception handler register save code.
*/
.globl alt_exception
.globl alt_irq_entry
.section .exceptions.entry.label, "xa"
alt_irq_entry:
/*
* Section .exceptions.entry is in alt_exception_entry.S
* This saves all the caller saved registers and reads estatus into r5
*/
.section .exceptions.irqtest, "xa"
#ifdef ALT_CI_INTERRUPT_VECTOR_N
/*
* Use the interrupt vector custom instruction if present to accelerate
* this code.
* If the interrupt vector custom instruction returns a negative
* value, there are no interrupts active (estatus.pie is 0
* or ipending is 0) so assume it is a software exception.
*/
custom ALT_CI_INTERRUPT_VECTOR_N, r4, r0, r0
blt r4, r0, .Lnot_irq
#else
/*
* Test to see if the exception was a software exception or caused
* by an external interrupt, and vector accordingly.
*/
rdctl r4, ipending
andi r2, r5, 1
beq r2, zero, .Lnot_irq
beq r4, zero, .Lnot_irq
#endif /* ALT_CI_INTERRUPT_VECTOR_N */
.section .exceptions.irqhandler, "xa"
/*
* Now that all necessary registers have been preserved, call
* alt_irq_handler() to process the interrupts.
*/
call alt_irq_handler
.section .exceptions.irqreturn, "xa"
br .Lexception_exit
.section .exceptions.notirq.label, "xa"
.Lnot_irq:
/*
* Section .exceptions.exit is in alt_exception_entry.S
* This restores all the caller saved registers
*/
.section .exceptions.exit.label
.Lexception_exit:
|
Maschell/saviine | 3,168 | src/kernel/kernel_hooks.S | # This stuff may need a change in different kernel versions
# This is only needed when launched directly through browser and not SD card.
.section ".kernel_code"
.globl SaveAndResetDataBATs_And_SRs_hook
SaveAndResetDataBATs_And_SRs_hook:
# setup CTR to the position we need to return to
mflr r5
mtctr r5
# set link register to its original value
mtlr r7
# setup us a nice DBAT for our code data with same region as our code
mfspr r5, 560
mtspr 570, r5
mfspr r5, 561
mtspr 571, r5
# restore the original kernel instructions that we replaced
lwz r5, 0x34(r3)
lwz r6, 0x38(r3)
lwz r7, 0x3C(r3)
lwz r8, 0x40(r3)
lwz r9, 0x44(r3)
lwz r10, 0x48(r3)
lwz r11, 0x4C(r3)
lwz r3, 0x50(r3)
isync
mtsr 7, r5
# jump back to the position in kernel after our patch (from LR)
bctr
.extern my_PrepareTitle
.globl my_PrepareTitle_hook
my_PrepareTitle_hook:
# store all registers on stack to avoid issues with the call to C functions
stwu r1, -0x90(r1)
# registers for our own usage
# only need r31 and rest is from tests before, just leaving it for later tests
stw r28, 0x20(r1)
stw r29, 0x24(r1)
stw r30, 0x28(r1)
stw r31, 0x2C(r1)
stw r3, 0x30(r1)
stw r4, 0x34(r1)
stw r5, 0x38(r1)
stw r6, 0x3C(r1)
stw r7, 0x40(r1)
stw r8, 0x44(r1)
stw r9, 0x48(r1)
stw r10, 0x4C(r1)
stw r11, 0x50(r1)
stw r12, 0x54(r1)
stw r13, 0x58(r1)
stw r14, 0x5C(r1)
stw r15, 0x60(r1)
stw r16, 0x64(r1)
stw r17, 0x68(r1)
stw r18, 0x6C(r1)
stw r19, 0x70(r1)
stw r20, 0x74(r1)
stw r21, 0x78(r1)
stw r22, 0x7C(r1)
# save original DBAT registers
mfdbatu r28, 0
mfdbatl r29, 0
# setup access to our data memory range
lis r3, 0xC000
ori r3, r3, 0x1FFF
mtdbatu 0, r3
lis r3, 0x3000
ori r3, r3, 0x0012
mtdbatl 0, r3
# memory barrier
eieio
isync
# save the LR from where we came
mflr r31
# the cos.xml/app.xml structure is at the location 0x68 of r11
# there are actually many places that can be hooked for it
# e.g. 0xFFF16130 and r27 points to this structure
addi r3, r11, 0x68
bl my_PrepareTitle
# restore original DBAT registers
mtdbatu 0, r28
mtdbatl 0, r29
# memory barrier
eieio
isync
# setup LR to jump back to kernel code
mtlr r31
# restore all original values of registers from stack
lwz r28, 0x20(r1)
lwz r29, 0x24(r1)
lwz r30, 0x28(r1)
lwz r31, 0x2C(r1)
lwz r3, 0x30(r1)
lwz r4, 0x34(r1)
lwz r5, 0x38(r1)
lwz r6, 0x3C(r1)
lwz r7, 0x40(r1)
lwz r8, 0x44(r1)
lwz r9, 0x48(r1)
lwz r10, 0x4C(r1)
lwz r11, 0x50(r1)
lwz r12, 0x54(r1)
lwz r13, 0x58(r1)
lwz r14, 0x5C(r1)
lwz r15, 0x60(r1)
lwz r16, 0x64(r1)
lwz r17, 0x68(r1)
lwz r18, 0x6C(r1)
lwz r19, 0x70(r1)
lwz r20, 0x74(r1)
lwz r21, 0x78(r1)
lwz r22, 0x7C(r1)
# restore the stack
addi r1, r1, 0x90
# restore original instruction that we replaced in the kernel
clrlwi r7, r12, 0
# jump back
blr
|
masahi/torchscript-to-tvm | 1,558,504 | detr/rocm_fp16_asm.s | .text
.amdgcn_target "amdgcn-amd-amdhsa-hcc-gfx1032"
.globl tvmgen_default_fused_add_reshape_cast_1_kernel0
.p2align 8
.type tvmgen_default_fused_add_reshape_cast_1_kernel0,@function
tvmgen_default_fused_add_reshape_cast_1_kernel0:
v_lshlrev_b32_e32 v0, 1, v0
s_clause 0x1
s_load_dwordx2 s[0:1], s[4:5], 0x10
s_load_dwordx2 s[2:3], s[4:5], 0x8
v_lshl_add_u32 v0, s6, 9, v0
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_dwordx2 v[4:5], v[4:5], off
global_load_dwordx2 v[2:3], v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v5, v3
v_add_f32_e32 v2, v4, v2
v_cvt_f16_f32_e32 v3, v3
v_cvt_f16_f32_e32 v2, v2
v_pack_b32_f16 v2, v2, v3
global_store_dword v[0:1], v2, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_add_reshape_cast_1_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size tvmgen_default_fused_add_reshape_cast_1_kernel0, .Lfunc_end0-tvmgen_default_fused_add_reshape_cast_1_kernel0
.globl tvmgen_default_fused_add_reshape_cast_kernel0
.p2align 8
.type tvmgen_default_fused_add_reshape_cast_kernel0,@function
tvmgen_default_fused_add_reshape_cast_kernel0:
s_clause 0x2
s_load_dwordx2 s[2:3], s[4:5], 0x0
s_load_dwordx2 s[8:9], s[4:5], 0x8
s_load_dwordx2 s[4:5], s[4:5], 0x10
v_lshlrev_b32_e32 v1, 1, v0
s_lshl_b32 s7, s6, 9
v_lshl_add_u32 v3, s6, 8, v0
s_mov_b32 s10, 0x25800
s_lshl_b32 s6, s6, 1
v_add_nc_u32_e32 v4, s7, v1
v_cmp_gt_i32_e64 s0, 0x12c00, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v3
v_cmp_gt_i32_e64 s1, s10, v4
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB1_2
v_lshrrev_b32_e32 v2, 7, v0
v_add_nc_u32_e32 v2, s6, v2
v_mul_hi_i32 v5, 0x1b4e81b5, v2
v_lshrrev_b32_e32 v6, 31, v5
v_lshrrev_b32_e32 v5, 6, v5
v_add_nc_u32_e32 v5, v5, v6
v_and_b32_e32 v6, 0xfe, v1
v_mul_lo_u32 v5, 0x258, v5
v_sub_nc_u32_e32 v2, v2, v5
v_lshl_or_b32 v5, v2, 8, v6
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, s0, s4, v5
v_add_co_ci_u32_e64 v8, s0, s5, v6, s0
v_add_co_u32 v5, s0, s8, v5
v_add_co_ci_u32_e64 v6, s0, s9, v6, s0
global_load_dword v2, v[7:8], off
global_load_dword v6, v[5:6], off
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v6
v_lshlrev_b64 v[5:6], 1, v[4:5]
v_cvt_f16_f32_e32 v2, v2
v_add_co_u32 v5, s0, s2, v5
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
global_store_short v[5:6], v2, off
BB1_2:
s_or_b32 exec_lo, exec_lo, s1
v_or_b32_e32 v2, 1, v1
s_xor_b32 s1, vcc_lo, -1
v_add_nc_u32_e32 v5, s7, v2
v_cmp_gt_i32_e64 s0, s10, v5
s_and_b32 s1, s0, s1
s_and_saveexec_b32 s0, s1
s_cbranch_execz BB1_4
v_lshrrev_b32_e32 v6, 7, v0
v_add_nc_u32_e32 v6, s6, v6
v_mul_hi_i32 v7, 0x1b4e81b5, v6
v_lshrrev_b32_e32 v8, 31, v7
v_ashrrev_i32_e32 v7, 6, v7
v_add_nc_u32_e32 v7, v7, v8
v_mul_lo_u32 v7, 0x258, v7
v_sub_nc_u32_e32 v6, v6, v7
v_perm_b32 v6, v6, v2, 0x6050400
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
global_load_dword v8, v[8:9], off
global_load_dword v7, v[6:7], off
v_ashrrev_i32_e32 v6, 31, v5
s_waitcnt vmcnt(0)
v_add_f32_e32 v8, v8, v7
v_lshlrev_b64 v[6:7], 1, v[5:6]
v_cvt_f16_f32_e32 v8, v8
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_store_short v[6:7], v8, off
BB1_4:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s7, 0x20000
v_add_nc_u32_e32 v6, 0x10000, v3
v_add_nc_u32_e32 v3, s7, v4
s_mov_b32 s10, 0x25800
s_addk_i32 s6, 0x200
v_cmp_gt_i32_e64 s0, 0x12c00, v6
v_cmp_gt_i32_e64 s1, s10, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v6
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB1_6
v_lshrrev_b32_e32 v4, 7, v0
v_and_b32_e32 v1, 0xfe, v1
v_add_nc_u32_e32 v4, s6, v4
v_mul_hi_i32 v6, 0x1b4e81b5, v4
v_lshrrev_b32_e32 v7, 31, v6
v_lshrrev_b32_e32 v6, 6, v6
v_add_nc_u32_e32 v6, v6, v7
v_mul_lo_u32 v6, 0x258, v6
v_sub_nc_u32_e32 v4, v4, v6
v_lshl_or_b32 v6, v4, 8, v1
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, s0, s4, v6
v_add_co_ci_u32_e64 v9, s0, s5, v7, s0
v_add_co_u32 v6, s0, s8, v6
v_add_co_ci_u32_e64 v7, s0, s9, v7, s0
v_add_co_u32 v3, s0, s2, v3
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
global_load_dword v1, v[8:9], off
global_load_dword v6, v[6:7], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v6
v_cvt_f16_f32_e32 v1, v1
global_store_short v[3:4], v1, off
BB1_6:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, s7, v5
s_xor_b32 s1, vcc_lo, -1
v_cmp_gt_i32_e64 s0, s10, v1
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB1_8
v_lshrrev_b32_e32 v0, 7, v0
v_add_nc_u32_e32 v0, s6, v0
v_mul_hi_i32 v3, 0x1b4e81b5, v0
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 6, v3
v_add_nc_u32_e32 v3, v3, v4
v_mul_lo_u32 v3, 0x258, v3
v_sub_nc_u32_e32 v0, v0, v3
v_perm_b32 v2, v0, v2, 0x6050400
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_dword v0, v[4:5], off
global_load_dword v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v0, v3
v_lshlrev_b64 v[0:1], 1, v[1:2]
v_cvt_f16_f32_e32 v2, v3
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_short v[0:1], v2, off
BB1_8:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_add_reshape_cast_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 11
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size tvmgen_default_fused_add_reshape_cast_kernel0, .Lfunc_end1-tvmgen_default_fused_add_reshape_cast_kernel0
.globl tvmgen_default_fused_cast_add_reshape_cast_kernel0
.p2align 8
.type tvmgen_default_fused_cast_add_reshape_cast_kernel0,@function
tvmgen_default_fused_cast_add_reshape_cast_kernel0:
s_clause 0x2
s_load_dwordx2 s[2:3], s[4:5], 0x0
s_load_dwordx2 s[8:9], s[4:5], 0x8
s_load_dwordx2 s[4:5], s[4:5], 0x10
v_lshlrev_b32_e32 v1, 1, v0
s_lshl_b32 s7, s6, 9
v_lshl_add_u32 v3, s6, 8, v0
s_mov_b32 s10, 0x25800
s_lshl_b32 s6, s6, 1
v_add_nc_u32_e32 v4, s7, v1
v_cmp_gt_i32_e64 s0, 0x12c00, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v3
v_cmp_gt_i32_e64 s1, s10, v4
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB2_2
v_lshrrev_b32_e32 v2, 7, v0
v_add_nc_u32_e32 v2, s6, v2
v_mul_hi_i32 v5, 0x1b4e81b5, v2
v_lshrrev_b32_e32 v6, 31, v5
v_lshrrev_b32_e32 v5, 6, v5
v_add_nc_u32_e32 v5, v5, v6
v_and_b32_e32 v6, 0xfe, v1
v_mul_lo_u32 v5, 0x258, v5
v_sub_nc_u32_e32 v2, v2, v5
v_lshl_or_b32 v5, v2, 8, v6
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[7:8], 1, v[5:6]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, s0, s8, v7
v_add_co_ci_u32_e64 v8, s0, s9, v8, s0
v_add_co_u32 v5, s0, s4, v5
v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
global_load_ushort v2, v[7:8], off
global_load_dword v6, v[5:6], off
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt vmcnt(1)
v_cvt_f32_f16_e32 v2, v2
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v6, v2
v_lshlrev_b64 v[5:6], 1, v[4:5]
v_cvt_f16_f32_e32 v2, v2
v_add_co_u32 v5, s0, s2, v5
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
global_store_short v[5:6], v2, off
BB2_2:
s_or_b32 exec_lo, exec_lo, s1
v_or_b32_e32 v2, 1, v1
s_xor_b32 s1, vcc_lo, -1
v_add_nc_u32_e32 v5, s7, v2
v_cmp_gt_i32_e64 s0, s10, v5
s_and_b32 s1, s0, s1
s_and_saveexec_b32 s0, s1
s_cbranch_execz BB2_4
v_lshrrev_b32_e32 v6, 7, v0
v_add_nc_u32_e32 v6, s6, v6
v_mul_hi_i32 v7, 0x1b4e81b5, v6
v_lshrrev_b32_e32 v8, 31, v7
v_ashrrev_i32_e32 v7, 6, v7
v_add_nc_u32_e32 v7, v7, v8
v_mul_lo_u32 v7, 0x258, v7
v_sub_nc_u32_e32 v6, v6, v7
v_perm_b32 v6, v6, v2, 0x6050400
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[8:9], 1, v[6:7]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_ushort v8, v[8:9], off
global_load_dword v7, v[6:7], off
v_ashrrev_i32_e32 v6, 31, v5
s_waitcnt vmcnt(1)
v_cvt_f32_f16_e32 v8, v8
s_waitcnt vmcnt(0)
v_add_f32_e32 v8, v7, v8
v_lshlrev_b64 v[6:7], 1, v[5:6]
v_cvt_f16_f32_e32 v8, v8
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_store_short v[6:7], v8, off
BB2_4:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s7, 0x20000
v_add_nc_u32_e32 v6, 0x10000, v3
v_add_nc_u32_e32 v3, s7, v4
s_mov_b32 s10, 0x25800
s_addk_i32 s6, 0x200
v_cmp_gt_i32_e64 s0, 0x12c00, v6
v_cmp_gt_i32_e64 s1, s10, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v6
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB2_6
v_lshrrev_b32_e32 v4, 7, v0
v_and_b32_e32 v1, 0xfe, v1
v_add_nc_u32_e32 v4, s6, v4
v_mul_hi_i32 v6, 0x1b4e81b5, v4
v_lshrrev_b32_e32 v7, 31, v6
v_lshrrev_b32_e32 v6, 6, v6
v_add_nc_u32_e32 v6, v6, v7
v_mul_lo_u32 v6, 0x258, v6
v_sub_nc_u32_e32 v4, v4, v6
v_lshl_or_b32 v6, v4, 8, v1
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_lshlrev_b64 v[8:9], 1, v[6:7]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, s0, s8, v8
v_add_co_ci_u32_e64 v9, s0, s9, v9, s0
v_add_co_u32 v6, s0, s4, v6
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
v_add_co_u32 v3, s0, s2, v3
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
global_load_ushort v1, v[8:9], off
global_load_dword v6, v[6:7], off
s_waitcnt vmcnt(1)
v_cvt_f32_f16_e32 v1, v1
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v6, v1
v_cvt_f16_f32_e32 v1, v1
global_store_short v[3:4], v1, off
BB2_6:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, s7, v5
s_xor_b32 s1, vcc_lo, -1
v_cmp_gt_i32_e64 s0, s10, v1
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB2_8
v_lshrrev_b32_e32 v0, 7, v0
v_add_nc_u32_e32 v0, s6, v0
v_mul_hi_i32 v3, 0x1b4e81b5, v0
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 6, v3
v_add_nc_u32_e32 v3, v3, v4
v_mul_lo_u32 v3, 0x258, v3
v_sub_nc_u32_e32 v0, v0, v3
v_perm_b32 v2, v0, v2, 0x6050400
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 1, v[2:3]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_ushort v0, v[4:5], off
global_load_dword v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt vmcnt(1)
v_cvt_f32_f16_e32 v0, v0
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v0
v_lshlrev_b64 v[0:1], 1, v[1:2]
v_cvt_f16_f32_e32 v2, v3
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_short v[0:1], v2, off
BB2_8:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_cast_add_reshape_cast_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 11
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size tvmgen_default_fused_cast_add_reshape_cast_kernel0, .Lfunc_end2-tvmgen_default_fused_cast_add_reshape_cast_kernel0
.globl tvmgen_default_fused_cast_logical_not_kernel0
.p2align 8
.type tvmgen_default_fused_cast_logical_not_kernel0,@function
tvmgen_default_fused_cast_logical_not_kernel0:
v_lshl_add_u32 v0, s6, 8, v0
v_cmp_gt_i32_e32 vcc_lo, 0x258, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB3_2
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
global_load_dword v2, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_nlg_f32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
global_store_byte v[0:1], v2, off
BB3_2:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_cast_logical_not_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size tvmgen_default_fused_cast_logical_not_kernel0, .Lfunc_end3-tvmgen_default_fused_cast_logical_not_kernel0
.globl tvmgen_default_fused_cast_split_squeeze_stack_layout_transform_kernel0
.p2align 8
.type tvmgen_default_fused_cast_split_squeeze_stack_layout_transform_kernel0,@function
tvmgen_default_fused_cast_split_squeeze_stack_layout_transform_kernel0:
s_mulk_i32 s6, 0x1f4
s_mov_b32 s0, 0x55555556
v_lshl_add_u32 v0, v0, 1, s6
s_load_dwordx2 s[6:7], s[4:5], 0x8
s_movk_i32 s1, 0x320
s_mov_b32 s2, 0x1d4c0
s_mov_b32 s3, 0x3a980
v_mul_hi_i32 v1, 0x1b4e81b5, v0
v_or_b32_e32 v3, 1, v0
v_mul_hi_i32 v4, v0, s0
s_mov_b32 s8, 0x57e40
s_mov_b32 s9, 0x75300
s_load_dwordx2 s[4:5], s[4:5], 0x0
v_mul_hi_i32 v5, v3, s0
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v1, 8, v1
v_lshrrev_b32_e32 v6, 31, v4
v_add_nc_u32_e32 v23, v1, v2
v_lshrrev_b32_e32 v7, 31, v5
v_add_nc_u32_e32 v4, v4, v6
v_mul_i32_i24_e32 v1, 0x960, v23
v_add_nc_u32_e32 v5, v5, v7
v_mul_lo_u32 v4, v4, 3
v_mad_i32_i24 v18, v23, s1, 0x27100
v_mad_i32_i24 v21, v23, s1, 0x30d40
v_sub_nc_u32_e32 v1, v0, v1
v_mul_lo_u32 v5, v5, 3
v_mad_i32_i24 v26, v23, s1, s8
v_add_nc_u32_e32 v2, 1, v1
v_mul_hi_i32 v8, v1, s0
v_sub_nc_u32_e32 v4, v0, v4
v_sub_nc_u32_e32 v3, v3, v5
v_mul_hi_i32 v6, v2, s0
s_mov_b32 s0, 0x927c0
v_cmp_lt_i32_e32 vcc_lo, -1, v4
v_lshrrev_b32_e32 v7, 31, v8
v_lshrrev_b32_e32 v9, 31, v6
v_add_nc_u32_e32 v7, v8, v7
v_add_nc_u32_e32 v8, 3, v4
v_add_nc_u32_e32 v5, v6, v9
v_mul_lo_u32 v6, v7, 3
v_cndmask_b32_e32 v4, v8, v4, vcc_lo
v_add_nc_u32_e32 v9, 3, v3
v_cmp_lt_i32_e32 vcc_lo, -1, v3
v_mul_lo_u32 v10, v5, 3
v_mad_i32_i24 v8, v23, s1, s2
v_mul_lo_u32 v4, v4, s0
v_sub_nc_u32_e32 v1, v1, v6
v_cndmask_b32_e32 v3, v9, v3, vcc_lo
v_mad_i32_i24 v6, v23, s1, 0x13880
v_sub_nc_u32_e32 v2, v2, v10
v_ashrrev_i32_e32 v1, 31, v1
v_mul_lo_u32 v3, v3, s0
v_ashrrev_i32_e32 v2, 31, v2
v_add3_u32 v24, v1, v7, v4
v_mad_i32_i24 v4, v23, s1, 0x9c40
v_add3_u32 v25, v2, v5, v3
v_mad_i32_i24 v1, v23, s1, v24
v_add_nc_u32_e32 v3, v24, v4
v_add_nc_u32_e32 v5, v24, v6
v_add_nc_u32_e32 v7, v24, v8
v_add_nc_u32_e32 v11, v25, v4
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
v_mad_i32_i24 v9, v23, s1, v25
v_add_nc_u32_e32 v13, v25, v6
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_ashrrev_i32_e32 v14, 31, v13
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_nc_u32_e32 v15, v25, v8
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_ashrrev_i32_e32 v8, 31, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v9
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_ashrrev_i32_e32 v16, 31, v15
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v11
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
v_add_co_u32 v13, vcc_lo, s6, v13
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
v_add_nc_u32_e32 v19, v24, v18
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_nc_u32_e32 v17, v25, v18
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
v_add_co_u32 v15, vcc_lo, s6, v15
v_ashrrev_i32_e32 v20, 31, v19
v_add_co_ci_u32_e32 v16, vcc_lo, s7, v16, vcc_lo
s_clause 0x7
global_load_dword v27, v[1:2], off
global_load_dword v28, v[9:10], off
global_load_dword v29, v[3:4], off
global_load_dword v30, v[11:12], off
global_load_dword v31, v[5:6], off
global_load_dword v32, v[13:14], off
global_load_dword v33, v[7:8], off
global_load_dword v34, v[15:16], off
v_add_nc_u32_e32 v7, v24, v21
v_mad_i32_i24 v10, v23, s1, s3
v_ashrrev_i32_e32 v18, 31, v17
v_add_nc_u32_e32 v5, v25, v21
v_lshlrev_b64 v[1:2], 2, v[19:20]
v_ashrrev_i32_e32 v8, 31, v7
v_add_nc_u32_e32 v11, v24, v10
v_mad_i32_i24 v14, v23, s1, 0x445c0
v_lshlrev_b64 v[3:4], 2, v[17:18]
v_ashrrev_i32_e32 v6, 31, v5
v_add_nc_u32_e32 v9, v25, v10
v_add_co_u32 v1, vcc_lo, s6, v1
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_ashrrev_i32_e32 v12, 31, v11
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_add_nc_u32_e32 v13, v24, v14
v_add_co_u32 v3, vcc_lo, s6, v3
v_mad_i32_i24 v19, v23, s1, 0x4e200
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_ashrrev_i32_e32 v10, 31, v9
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_nc_u32_e32 v15, v25, v14
v_add_co_u32 v7, vcc_lo, s6, v7
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_ashrrev_i32_e32 v14, 31, v13
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
v_add_nc_u32_e32 v17, v24, v19
v_add_co_u32 v5, vcc_lo, s6, v5
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_ashrrev_i32_e32 v16, 31, v15
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v11
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_ashrrev_i32_e32 v18, 31, v17
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v9
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v13, vcc_lo, s6, v13
v_lshlrev_b64 v[17:18], 2, v[17:18]
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
v_add_nc_u32_e32 v19, v25, v19
v_add_co_u32 v15, vcc_lo, s6, v15
v_add_nc_u32_e32 v21, v24, v26
v_add_co_ci_u32_e32 v16, vcc_lo, s7, v16, vcc_lo
v_add_co_u32 v17, vcc_lo, s6, v17
s_clause 0x7
global_load_dword v35, v[1:2], off
global_load_dword v36, v[3:4], off
global_load_dword v37, v[7:8], off
global_load_dword v38, v[5:6], off
global_load_dword v39, v[11:12], off
global_load_dword v40, v[9:10], off
global_load_dword v41, v[13:14], off
global_load_dword v42, v[15:16], off
v_add_co_ci_u32_e32 v18, vcc_lo, s7, v18, vcc_lo
v_mad_i32_i24 v8, v23, s1, 0x61a80
v_ashrrev_i32_e32 v20, 31, v19
v_add_nc_u32_e32 v3, v25, v26
v_ashrrev_i32_e32 v22, 31, v21
global_load_dword v43, v[17:18], off
v_mad_i32_i24 v17, v23, s1, s9
v_add_nc_u32_e32 v7, v24, v8
v_lshlrev_b64 v[1:2], 2, v[19:20]
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[21:22]
v_add_nc_u32_e32 v13, v24, v17
v_add_nc_u32_e32 v9, v25, v8
v_ashrrev_i32_e32 v8, 31, v7
v_mad_i32_i24 v12, v23, s1, 0x6b6c0
v_add_co_u32 v1, vcc_lo, s6, v1
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_ashrrev_i32_e32 v14, 31, v13
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_nc_u32_e32 v11, v24, v12
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_ashrrev_i32_e32 v10, 31, v9
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_nc_u32_e32 v15, v25, v12
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_ashrrev_i32_e32 v12, 31, v11
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_nc_u32_e32 v17, v25, v17
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_ashrrev_i32_e32 v16, 31, v15
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
v_add_co_u32 v13, vcc_lo, s6, v13
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
v_ashrrev_i32_e32 v18, 31, v17
v_add_co_u32 v9, vcc_lo, s6, v9
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v11
global_load_dword v44, v[13:14], off
v_lshlrev_b64 v[13:14], 2, v[17:18]
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
v_add_co_u32 v15, vcc_lo, s6, v15
v_mad_i32_i24 v17, v23, s1, 0x7ef40
v_add_co_ci_u32_e32 v16, vcc_lo, s7, v16, vcc_lo
v_add_nc_u32_e32 v18, 0x107ac0, v0
v_add_co_u32 v13, vcc_lo, s6, v13
v_add_nc_u32_e32 v20, 0x124f80, v0
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
s_clause 0x7
global_load_dword v45, v[1:2], off
global_load_dword v46, v[5:6], off
global_load_dword v47, v[3:4], off
global_load_dword v48, v[7:8], off
global_load_dword v49, v[9:10], off
global_load_dword v50, v[11:12], off
global_load_dword v51, v[15:16], off
global_load_dword v52, v[13:14], off
v_add_nc_u32_e32 v1, v24, v17
v_add_nc_u32_e32 v3, v25, v17
v_mad_i32_i24 v6, v23, s1, 0x88b80
v_add_nc_u32_e32 v10, s0, v0
v_add_nc_u32_e32 v12, 0xafc80, v0
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v5, v25, v6
v_add_nc_u32_e32 v7, v24, v6
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
v_add_nc_u32_e32 v14, 0xcd140, v0
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_u32 v1, vcc_lo, s6, v1
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_nc_u32_e32 v16, 0xea600, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_nc_u32_e32 v22, 0x142440, v0
v_ashrrev_i32_e32 v15, 31, v14
v_ashrrev_i32_e32 v19, 31, v18
s_clause 0x1
global_load_dword v53, v[1:2], off
global_load_dword v54, v[3:4], off
v_lshlrev_b64 v[1:2], 2, v[7:8]
v_add_co_u32 v3, vcc_lo, s6, v5
v_add_nc_u32_e32 v8, s9, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
v_add_nc_u32_e32 v6, s8, v0
v_ashrrev_i32_e32 v17, 31, v16
v_add_co_u32 v1, vcc_lo, s6, v1
v_ashrrev_i32_e32 v9, 31, v8
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v21, 31, v20
v_ashrrev_i32_e32 v23, 31, v22
s_clause 0x1
global_load_dword v55, v[3:4], off
global_load_dword v56, v[1:2], off
v_add_nc_u32_e32 v2, s2, v0
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v4, s3, v0
v_add_nc_u32_e32 v24, 0x15f900, v0
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[25:26], 1, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[1:2], 1, v[2:3]
v_add_co_u32 v25, vcc_lo, s4, v25
v_lshlrev_b64 v[3:4], 1, v[4:5]
v_add_co_ci_u32_e32 v26, vcc_lo, s5, v26, vcc_lo
v_lshlrev_b64 v[5:6], 1, v[6:7]
v_add_co_u32 v1, vcc_lo, s4, v1
v_lshlrev_b64 v[7:8], 1, v[8:9]
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_lshlrev_b64 v[9:10], 1, v[10:11]
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v5
v_lshlrev_b64 v[11:12], 1, v[12:13]
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v7
v_lshlrev_b64 v[13:14], 1, v[14:15]
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v9
v_lshlrev_b64 v[15:16], 1, v[16:17]
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v11
v_lshlrev_b64 v[17:18], 1, v[18:19]
v_lshlrev_b64 v[19:20], 1, v[20:21]
v_lshlrev_b64 v[21:22], 1, v[22:23]
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
v_add_co_u32 v15, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
v_add_co_u32 v17, vcc_lo, s4, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v18, vcc_lo
v_add_co_u32 v19, vcc_lo, s4, v19
v_add_co_ci_u32_e32 v20, vcc_lo, s5, v20, vcc_lo
s_waitcnt vmcnt(29)
v_cvt_f16_f32_e32 v23, v27
s_waitcnt vmcnt(28)
v_cvt_f16_f32_e32 v28, v28
s_waitcnt vmcnt(27)
v_cvt_f16_f32_e32 v29, v29
s_waitcnt vmcnt(26)
v_cvt_f16_f32_e32 v30, v30
s_waitcnt vmcnt(25)
v_cvt_f16_f32_e32 v31, v31
s_waitcnt vmcnt(24)
v_cvt_f16_f32_e32 v32, v32
s_waitcnt vmcnt(23)
v_cvt_f16_f32_e32 v33, v33
s_waitcnt vmcnt(22)
v_cvt_f16_f32_e32 v34, v34
v_pack_b32_f16 v23, v23, v28
v_pack_b32_f16 v28, v29, v30
v_pack_b32_f16 v29, v31, v32
v_pack_b32_f16 v30, v33, v34
s_waitcnt vmcnt(21)
v_cvt_f16_f32_e32 v27, v35
s_waitcnt vmcnt(20)
v_cvt_f16_f32_e32 v36, v36
s_waitcnt vmcnt(19)
v_cvt_f16_f32_e32 v37, v37
s_waitcnt vmcnt(18)
v_cvt_f16_f32_e32 v38, v38
s_waitcnt vmcnt(17)
v_cvt_f16_f32_e32 v39, v39
s_waitcnt vmcnt(16)
v_cvt_f16_f32_e32 v40, v40
s_waitcnt vmcnt(15)
v_cvt_f16_f32_e32 v41, v41
s_waitcnt vmcnt(14)
v_cvt_f16_f32_e32 v42, v42
v_pack_b32_f16 v27, v27, v36
v_pack_b32_f16 v31, v37, v38
v_pack_b32_f16 v32, v39, v40
v_pack_b32_f16 v33, v41, v42
s_waitcnt vmcnt(13)
v_cvt_f16_f32_e32 v35, v43
s_waitcnt vmcnt(12)
v_cvt_f16_f32_e32 v43, v44
s_waitcnt vmcnt(11)
v_cvt_f16_f32_e32 v44, v45
s_waitcnt vmcnt(10)
v_cvt_f16_f32_e32 v46, v46
s_waitcnt vmcnt(9)
v_cvt_f16_f32_e32 v45, v47
s_waitcnt vmcnt(8)
v_cvt_f16_f32_e32 v48, v48
s_waitcnt vmcnt(7)
v_cvt_f16_f32_e32 v47, v49
v_pack_b32_f16 v34, v35, v44
s_waitcnt vmcnt(5)
v_cvt_f16_f32_e32 v49, v51
v_pack_b32_f16 v35, v46, v45
global_store_dword v[25:26], v23, off
global_store_dword v[1:2], v28, off
global_store_dword v[3:4], v29, off
global_store_dword v[5:6], v30, off
global_store_dword v[7:8], v27, off
global_store_dword v[9:10], v31, off
global_store_dword v[11:12], v32, off
global_store_dword v[13:14], v33, off
global_store_dword v[15:16], v34, off
global_store_dword v[17:18], v35, off
v_add_nc_u32_e32 v3, 0x17cdc0, v0
v_ashrrev_i32_e32 v25, 31, v24
v_add_nc_u32_e32 v7, 0x19a280, v0
v_add_co_u32 v1, vcc_lo, s4, v21
v_cvt_f16_f32_e32 v50, v50
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 1, v[24:25]
v_ashrrev_i32_e32 v8, 31, v7
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v22, vcc_lo
s_waitcnt vmcnt(4)
v_cvt_f16_f32_e32 v51, v52
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_pack_b32_f16 v36, v48, v47
v_add_co_u32 v5, vcc_lo, s4, v5
v_lshlrev_b64 v[7:8], 1, v[7:8]
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_pack_b32_f16 v37, v50, v49
v_add_co_u32 v3, vcc_lo, s4, v3
v_pack_b32_f16 v9, v43, v51
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_waitcnt vmcnt(3)
v_cvt_f16_f32_e32 v11, v53
s_waitcnt vmcnt(2)
v_cvt_f16_f32_e32 v10, v54
v_pack_b32_f16 v0, v11, v10
s_waitcnt vmcnt(1)
v_cvt_f16_f32_e32 v10, v55
s_waitcnt vmcnt(0)
v_cvt_f16_f32_e32 v11, v56
v_pack_b32_f16 v10, v11, v10
global_store_dword v[19:20], v36, off
global_store_dword v[1:2], v37, off
global_store_dword v[5:6], v9, off
global_store_dword v[3:4], v0, off
global_store_dword v[7:8], v10, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_cast_split_squeeze_stack_layout_transform_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 57
.amdhsa_next_free_sgpr 10
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size tvmgen_default_fused_cast_split_squeeze_stack_layout_transform_kernel0, .Lfunc_end4-tvmgen_default_fused_cast_split_squeeze_stack_layout_transform_kernel0
.globl tvmgen_default_fused_cumsum_1_kernel0
.p2align 8
.type tvmgen_default_fused_cumsum_1_kernel0,@function
tvmgen_default_fused_cumsum_1_kernel0:
v_lshl_add_u32 v0, s6, 8, v0
v_cmp_gt_i32_e32 vcc_lo, 0x258, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB5_2
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_lshlrev_b64 v[0:1], 2, v[0:1]
global_load_ubyte v2, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
global_store_dword v[0:1], v2, off
BB5_2:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_cumsum_1_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size tvmgen_default_fused_cumsum_1_kernel0, .Lfunc_end5-tvmgen_default_fused_cumsum_1_kernel0
.globl tvmgen_default_fused_cumsum_1_kernel1
.p2align 8
.type tvmgen_default_fused_cumsum_1_kernel1,@function
tvmgen_default_fused_cumsum_1_kernel1:
v_cmp_gt_i32_e32 vcc_lo, 25, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB6_2
s_load_dwordx2 s[0:1], s[4:5], 0x8
s_mul_i32 s7, s7, 25
v_add_nc_u32_e32 v0, s7, v0
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_lshlrev_b64 v[0:1], 2, v[0:1]
global_load_ubyte v2, v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, 1, v2
v_cmp_eq_u32_e32 vcc_lo, 1, v2
v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_dword v[0:1], v2, off
BB6_2:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_cumsum_1_kernel1
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end6:
.size tvmgen_default_fused_cumsum_1_kernel1, .Lfunc_end6-tvmgen_default_fused_cumsum_1_kernel1
.globl tvmgen_default_fused_cumsum_1_kernel2
.p2align 8
.type tvmgen_default_fused_cumsum_1_kernel2,@function
tvmgen_default_fused_cumsum_1_kernel2:
s_load_dword s2, s[4:5], 0x8
s_mov_b32 s0, s6
s_ashr_i32 s1, s6, 31
s_lshl_b64 s[0:1], s[0:1], 8
v_add_co_u32 v0, s0, s0, v0
v_add_co_ci_u32_e64 v1, s0, s1, 0, s0
s_waitcnt lgkmcnt(0)
s_lshl_b64 s[2:3], 2, s2
v_mul_lo_u32 v3, s3, v0
v_mul_lo_u32 v1, s2, v1
v_mul_hi_u32 v4, s2, v0
v_mul_lo_u32 v2, s2, v0
s_ashr_i64 s[0:1], s[2:3], 1
v_add3_u32 v3, v4, v1, v3
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
v_cmp_gt_i64_e32 vcc_lo, 25, v[2:3]
v_cmp_gt_i64_e64 s0, 25, v[0:1]
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB7_2
v_add_co_u32 v2, vcc_lo, v2, s2
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_mad_i64_i32 v[0:1], s2, s7, 25, v[0:1]
v_cmp_gt_i64_e32 vcc_lo, 25, v[2:3]
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cndmask_b32_e32 v2, 25, v2, vcc_lo
v_mad_i64_i32 v[2:3], s2, s7, 25, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_dword v0, v[0:1], off offset:-4
global_load_dword v1, v[2:3], off offset:-4
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v1
global_store_dword v[2:3], v0, off offset:-4
BB7_2:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_cumsum_1_kernel2
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end7:
.size tvmgen_default_fused_cumsum_1_kernel2, .Lfunc_end7-tvmgen_default_fused_cumsum_1_kernel2
.globl tvmgen_default_fused_cumsum_1_kernel3
.p2align 8
.type tvmgen_default_fused_cumsum_1_kernel3,@function
tvmgen_default_fused_cumsum_1_kernel3:
s_load_dwordx2 s[0:1], s[4:5], 0x0
s_mul_i32 s2, s6, 25
v_mov_b32_e32 v0, 0
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_dword v0, v0, s[0:1] offset:96
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_cumsum_1_kernel3
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_vcc 0
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end8:
.size tvmgen_default_fused_cumsum_1_kernel3, .Lfunc_end8-tvmgen_default_fused_cumsum_1_kernel3
.globl tvmgen_default_fused_cumsum_1_kernel4
.p2align 8
.type tvmgen_default_fused_cumsum_1_kernel4,@function
tvmgen_default_fused_cumsum_1_kernel4:
s_load_dword s2, s[4:5], 0x8
s_mov_b32 s0, s6
s_ashr_i32 s1, s6, 31
s_lshl_b64 s[0:1], s[0:1], 8
v_add_co_u32 v0, s0, s0, v0
v_add_co_ci_u32_e64 v1, s0, s1, 0, s0
s_waitcnt lgkmcnt(0)
s_not_b32 s2, s2
s_add_i32 s2, s2, 5
s_lshl_b64 s[2:3], 2, s2
v_mul_lo_u32 v3, s3, v0
v_mul_lo_u32 v1, s2, v1
v_mul_hi_u32 v4, s2, v0
v_mul_lo_u32 v2, s2, v0
s_ashr_i64 s[0:1], s[2:3], 1
v_add3_u32 v3, v4, v1, v3
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
v_cmp_gt_i64_e32 vcc_lo, 25, v[2:3]
v_cmp_gt_i64_e64 s0, 25, v[0:1]
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB9_2
v_add_co_u32 v2, vcc_lo, v2, s2
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_mad_i64_i32 v[0:1], s2, s7, 25, v[0:1]
v_cmp_gt_i64_e32 vcc_lo, 25, v[2:3]
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cndmask_b32_e32 v2, 25, v2, vcc_lo
v_mad_i64_i32 v[2:3], s2, s7, 25, v[2:3]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_load_dword v4, v[2:3], off offset:-4
global_load_dword v5, v[0:1], off offset:-4
s_waitcnt vmcnt(1)
global_store_dword v[0:1], v4, off offset:-4
global_load_dword v0, v[2:3], off offset:-4
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v5, v0
global_store_dword v[2:3], v0, off offset:-4
BB9_2:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_cumsum_1_kernel4
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end9:
.size tvmgen_default_fused_cumsum_1_kernel4, .Lfunc_end9-tvmgen_default_fused_cumsum_1_kernel4
.globl tvmgen_default_fused_cumsum_1_kernel5
.p2align 8
.type tvmgen_default_fused_cumsum_1_kernel5,@function
tvmgen_default_fused_cumsum_1_kernel5:
v_lshl_add_u32 v0, s6, 8, v0
v_cmp_gt_i32_e32 vcc_lo, 0x258, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB10_2
s_clause 0x1
s_load_dwordx2 s[0:1], s[4:5], 0x10
s_load_dwordx2 s[2:3], s[4:5], 0x8
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
global_load_dword v2, v[2:3], off
global_load_dword v3, v[4:5], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_dword v[0:1], v2, off
BB10_2:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_cumsum_1_kernel5
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end10:
.size tvmgen_default_fused_cumsum_1_kernel5, .Lfunc_end10-tvmgen_default_fused_cumsum_1_kernel5
.globl tvmgen_default_fused_cumsum_kernel0
.p2align 8
.type tvmgen_default_fused_cumsum_kernel0,@function
tvmgen_default_fused_cumsum_kernel0:
v_lshl_add_u32 v0, s6, 8, v0
v_cmp_gt_i32_e32 vcc_lo, 0x258, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB11_2
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_lshlrev_b64 v[0:1], 2, v[0:1]
global_load_ubyte v2, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
global_store_dword v[0:1], v2, off
BB11_2:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_cumsum_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end11:
.size tvmgen_default_fused_cumsum_kernel0, .Lfunc_end11-tvmgen_default_fused_cumsum_kernel0
.globl tvmgen_default_fused_cumsum_kernel1
.p2align 8
.type tvmgen_default_fused_cumsum_kernel1,@function
tvmgen_default_fused_cumsum_kernel1:
v_lshl_add_u32 v0, s6, 8, v0
v_cmp_gt_i32_e32 vcc_lo, 0x258, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB12_2
v_mul_hi_i32 v1, 0x2aaaaaab, v0
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v1, 2, v1
v_add_nc_u32_e32 v1, v1, v2
v_mul_lo_u32 v2, v1, 24
v_sub_nc_u32_e32 v2, v0, v2
v_mul_lo_u32 v2, v2, 25
v_add_nc_u32_e32 v1, v2, v1
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
global_load_ubyte v1, v[1:2], off
v_ashrrev_i32_e32 v2, 31, v0
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v1
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_byte v[0:1], v3, off
BB12_2:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_cumsum_kernel1
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end12:
.size tvmgen_default_fused_cumsum_kernel1, .Lfunc_end12-tvmgen_default_fused_cumsum_kernel1
.globl tvmgen_default_fused_cumsum_kernel2
.p2align 8
.type tvmgen_default_fused_cumsum_kernel2,@function
tvmgen_default_fused_cumsum_kernel2:
v_cmp_gt_i32_e32 vcc_lo, 24, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB13_2
s_load_dwordx2 s[0:1], s[4:5], 0x8
s_mul_i32 s7, s7, 24
v_add_nc_u32_e32 v0, s7, v0
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_lshlrev_b64 v[0:1], 2, v[0:1]
global_load_ubyte v2, v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, 1, v2
v_cmp_eq_u32_e32 vcc_lo, 1, v2
v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_dword v[0:1], v2, off
BB13_2:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_cumsum_kernel2
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end13:
.size tvmgen_default_fused_cumsum_kernel2, .Lfunc_end13-tvmgen_default_fused_cumsum_kernel2
.globl tvmgen_default_fused_cumsum_kernel3
.p2align 8
.type tvmgen_default_fused_cumsum_kernel3,@function
tvmgen_default_fused_cumsum_kernel3:
s_load_dword s2, s[4:5], 0x8
s_mov_b32 s0, s6
s_ashr_i32 s1, s6, 31
s_lshl_b64 s[0:1], s[0:1], 8
v_add_co_u32 v0, s0, s0, v0
v_add_co_ci_u32_e64 v1, s0, s1, 0, s0
s_waitcnt lgkmcnt(0)
s_lshl_b64 s[2:3], 2, s2
v_mul_lo_u32 v3, s3, v0
v_mul_lo_u32 v1, s2, v1
v_mul_hi_u32 v4, s2, v0
v_mul_lo_u32 v2, s2, v0
s_ashr_i64 s[0:1], s[2:3], 1
v_add3_u32 v3, v4, v1, v3
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
v_cmp_gt_i64_e32 vcc_lo, 24, v[2:3]
v_cmp_gt_i64_e64 s0, 24, v[0:1]
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB14_2
v_add_co_u32 v2, vcc_lo, v2, s2
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_mad_i64_i32 v[0:1], s2, s7, 24, v[0:1]
v_cmp_gt_i64_e32 vcc_lo, 24, v[2:3]
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cndmask_b32_e32 v2, 24, v2, vcc_lo
v_mad_i64_i32 v[2:3], s2, s7, 24, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_dword v0, v[0:1], off offset:-4
global_load_dword v1, v[2:3], off offset:-4
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v1
global_store_dword v[2:3], v0, off offset:-4
BB14_2:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_cumsum_kernel3
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end14:
.size tvmgen_default_fused_cumsum_kernel3, .Lfunc_end14-tvmgen_default_fused_cumsum_kernel3
.globl tvmgen_default_fused_cumsum_kernel4
.p2align 8
.type tvmgen_default_fused_cumsum_kernel4,@function
tvmgen_default_fused_cumsum_kernel4:
s_load_dwordx2 s[0:1], s[4:5], 0x0
s_mul_i32 s2, s6, 24
v_mov_b32_e32 v0, 0
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_dword v0, v0, s[0:1] offset:92
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_cumsum_kernel4
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_vcc 0
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end15:
.size tvmgen_default_fused_cumsum_kernel4, .Lfunc_end15-tvmgen_default_fused_cumsum_kernel4
.globl tvmgen_default_fused_cumsum_kernel5
.p2align 8
.type tvmgen_default_fused_cumsum_kernel5,@function
tvmgen_default_fused_cumsum_kernel5:
s_load_dword s2, s[4:5], 0x8
s_mov_b32 s0, s6
s_ashr_i32 s1, s6, 31
s_lshl_b64 s[0:1], s[0:1], 8
v_add_co_u32 v0, s0, s0, v0
v_add_co_ci_u32_e64 v1, s0, s1, 0, s0
s_waitcnt lgkmcnt(0)
s_not_b32 s2, s2
s_add_i32 s2, s2, 5
s_lshl_b64 s[2:3], 2, s2
v_mul_lo_u32 v3, s3, v0
v_mul_lo_u32 v1, s2, v1
v_mul_hi_u32 v4, s2, v0
v_mul_lo_u32 v2, s2, v0
s_ashr_i64 s[0:1], s[2:3], 1
v_add3_u32 v3, v4, v1, v3
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
v_cmp_gt_i64_e32 vcc_lo, 24, v[2:3]
v_cmp_gt_i64_e64 s0, 24, v[0:1]
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB16_2
v_add_co_u32 v2, vcc_lo, v2, s2
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_mad_i64_i32 v[0:1], s2, s7, 24, v[0:1]
v_cmp_gt_i64_e32 vcc_lo, 24, v[2:3]
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cndmask_b32_e32 v2, 24, v2, vcc_lo
v_mad_i64_i32 v[2:3], s2, s7, 24, v[2:3]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_load_dword v4, v[2:3], off offset:-4
global_load_dword v5, v[0:1], off offset:-4
s_waitcnt vmcnt(1)
global_store_dword v[0:1], v4, off offset:-4
global_load_dword v0, v[2:3], off offset:-4
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v5, v0
global_store_dword v[2:3], v0, off offset:-4
BB16_2:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_cumsum_kernel5
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end16:
.size tvmgen_default_fused_cumsum_kernel5, .Lfunc_end16-tvmgen_default_fused_cumsum_kernel5
.globl tvmgen_default_fused_cumsum_kernel6
.p2align 8
.type tvmgen_default_fused_cumsum_kernel6,@function
tvmgen_default_fused_cumsum_kernel6:
v_lshl_add_u32 v0, s6, 8, v0
v_cmp_gt_i32_e32 vcc_lo, 0x258, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB17_2
v_mul_hi_i32 v1, 0x51eb851f, v0
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v1, 3, v1
v_add_nc_u32_e32 v1, v1, v2
v_mul_lo_u32 v2, v1, 25
v_sub_nc_u32_e32 v2, v0, v2
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v1, v2, v1
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
global_load_dword v2, v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_dword v[0:1], v2, off
BB17_2:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_cumsum_kernel6
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end17:
.size tvmgen_default_fused_cumsum_kernel6, .Lfunc_end17-tvmgen_default_fused_cumsum_kernel6
.globl tvmgen_default_fused_cumsum_kernel7
.p2align 8
.type tvmgen_default_fused_cumsum_kernel7,@function
tvmgen_default_fused_cumsum_kernel7:
v_lshl_add_u32 v0, s6, 8, v0
v_cmp_gt_i32_e32 vcc_lo, 0x258, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB18_2
s_clause 0x1
s_load_dwordx2 s[0:1], s[4:5], 0x10
s_load_dwordx2 s[2:3], s[4:5], 0x8
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
global_load_dword v2, v[2:3], off
global_load_dword v3, v[4:5], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_dword v[0:1], v2, off
BB18_2:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_cumsum_kernel7
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end18:
.size tvmgen_default_fused_cumsum_kernel7, .Lfunc_end18-tvmgen_default_fused_cumsum_kernel7
.globl tvmgen_default_fused_layout_transform_reshape_squeeze_transpose_kernel0
.p2align 8
.type tvmgen_default_fused_layout_transform_reshape_squeeze_transpose_kernel0,@function
tvmgen_default_fused_layout_transform_reshape_squeeze_transpose_kernel0:
s_clause 0x1
s_load_dwordx2 s[2:3], s[4:5], 0x0
s_load_dwordx2 s[4:5], s[4:5], 0x8
v_lshlrev_b32_e32 v1, 1, v0
s_lshl_b32 s7, s6, 9
v_lshl_add_u32 v3, s6, 8, v0
s_mov_b32 s8, 0x25800
s_lshl_b32 s6, s6, 1
v_add_nc_u32_e32 v4, s7, v1
v_cmp_gt_i32_e64 s0, 0x12c00, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v3
v_cmp_gt_i32_e64 s1, s8, v4
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB19_2
v_lshrrev_b32_e32 v2, 7, v0
s_mov_b32 s0, 0x51eb851f
v_mul_hi_i32 v6, v4, s0
v_add_nc_u32_e32 v2, s6, v2
v_mul_hi_i32 v5, v2, s0
v_lshrrev_b32_e32 v8, 31, v6
v_ashrrev_i32_e32 v6, 11, v6
v_add_nc_u32_e32 v6, v6, v8
v_lshrrev_b32_e32 v7, 31, v5
v_lshrrev_b32_e32 v5, 3, v5
v_mul_i32_i24_e32 v6, 0x1900, v6
v_add_nc_u32_e32 v5, v5, v7
v_and_or_b32 v6, 0xfe, v1, v6
v_mul_lo_u32 v5, v5, 25
v_sub_nc_u32_e32 v2, v2, v5
v_lshl_add_u32 v5, v2, 8, v6
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 1, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, s0, s4, v5
v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
global_load_ushort v2, v[5:6], off
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[5:6], 1, v[4:5]
v_add_co_u32 v5, s0, s2, v5
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
s_waitcnt vmcnt(0)
global_store_short v[5:6], v2, off
BB19_2:
s_or_b32 exec_lo, exec_lo, s1
v_or_b32_e32 v2, 1, v1
s_xor_b32 s1, vcc_lo, -1
v_add_nc_u32_e32 v5, s7, v2
v_cmp_gt_i32_e64 s0, s8, v5
s_and_b32 s1, s0, s1
s_and_saveexec_b32 s0, s1
s_cbranch_execz BB19_4
v_lshrrev_b32_e32 v6, 7, v0
s_mov_b32 s1, 0x51eb851f
v_mul_hi_i32 v8, v5, s1
v_add_nc_u32_e32 v6, s6, v6
v_mul_hi_i32 v7, v6, s1
v_lshrrev_b32_e32 v10, 31, v8
v_ashrrev_i32_e32 v8, 11, v8
v_add_nc_u32_e32 v8, v8, v10
v_lshrrev_b32_e32 v9, 31, v7
v_lshrrev_b32_e32 v7, 3, v7
v_mul_i32_i24_e32 v8, 0x1900, v8
v_add_nc_u32_e32 v7, v7, v9
v_and_or_b32 v8, 0xff, v2, v8
v_mul_lo_u32 v7, v7, 25
v_sub_nc_u32_e32 v6, v6, v7
v_lshl_add_u32 v6, v6, 8, v8
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 1, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_ushort v8, v[6:7], off
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[6:7], 1, v[5:6]
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_short v[6:7], v8, off
BB19_4:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s7, 0x20000
v_add_nc_u32_e32 v6, 0x10000, v3
v_add_nc_u32_e32 v3, s7, v4
s_mov_b32 s8, 0x25800
s_addk_i32 s6, 0x200
v_cmp_gt_i32_e64 s0, 0x12c00, v6
v_cmp_gt_i32_e64 s1, s8, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v6
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB19_6
v_lshrrev_b32_e32 v4, 7, v0
s_mov_b32 s0, 0x51eb851f
v_mul_hi_i32 v7, v3, s0
v_add_nc_u32_e32 v4, s6, v4
v_mul_hi_i32 v6, v4, s0
v_lshrrev_b32_e32 v9, 31, v7
v_ashrrev_i32_e32 v7, 11, v7
v_add_nc_u32_e32 v7, v7, v9
v_lshrrev_b32_e32 v8, 31, v6
v_lshrrev_b32_e32 v6, 3, v6
v_mul_i32_i24_e32 v7, 0x1900, v7
v_add_nc_u32_e32 v6, v6, v8
v_and_or_b32 v1, 0xfe, v1, v7
v_mul_lo_u32 v6, v6, 25
v_sub_nc_u32_e32 v4, v4, v6
v_lshl_add_u32 v6, v4, 8, v1
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_lshlrev_b64 v[6:7], 1, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, s0, s4, v6
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
v_add_co_u32 v3, s0, s2, v3
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
global_load_ushort v1, v[6:7], off
s_waitcnt vmcnt(0)
global_store_short v[3:4], v1, off
BB19_6:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, s7, v5
s_xor_b32 s1, vcc_lo, -1
v_cmp_gt_i32_e64 s0, s8, v1
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB19_8
v_lshrrev_b32_e32 v0, 7, v0
s_mov_b32 s0, 0x51eb851f
v_mul_hi_i32 v4, v1, s0
v_add_nc_u32_e32 v0, s6, v0
v_mul_hi_i32 v3, v0, s0
v_lshrrev_b32_e32 v6, 31, v4
v_ashrrev_i32_e32 v4, 11, v4
v_add_nc_u32_e32 v4, v4, v6
v_lshrrev_b32_e32 v5, 31, v3
v_lshrrev_b32_e32 v3, 3, v3
v_mul_i32_i24_e32 v4, 0x1900, v4
v_add_nc_u32_e32 v3, v3, v5
v_and_or_b32 v2, 0xff, v2, v4
v_mul_lo_u32 v3, v3, 25
v_sub_nc_u32_e32 v0, v0, v3
v_lshl_add_u32 v2, v0, 8, v2
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_ushort v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 1, v[1:2]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_short v[0:1], v3, off
BB19_8:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_layout_transform_reshape_squeeze_transpose_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 9
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end19:
.size tvmgen_default_fused_layout_transform_reshape_squeeze_transpose_kernel0, .Lfunc_end19-tvmgen_default_fused_layout_transform_reshape_squeeze_transpose_kernel0
.globl tvmgen_default_fused_mean_1_kernel0
.p2align 8
.type tvmgen_default_fused_mean_1_kernel0,@function
tvmgen_default_fused_mean_1_kernel0:
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_lshl_add_u32 v1, s6, 8, v0
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, 16, v0
s_clause 0x7
global_load_dword v3, v[1:2], off
global_load_dword v4, v[1:2], off offset:128
global_load_dword v5, v[1:2], off offset:256
global_load_dword v6, v[1:2], off offset:384
global_load_dword v7, v[1:2], off offset:512
global_load_dword v8, v[1:2], off offset:640
global_load_dword v9, v[1:2], off offset:768
global_load_dword v2, v[1:2], off offset:896
s_waitcnt vmcnt(0)
s_barrier
v_add_f32_e32 v1, 0, v3
v_add_f32_e32 v1, v1, v4
v_add_f32_e32 v1, v1, v5
v_add_f32_e32 v1, v1, v6
v_add_f32_e32 v1, v1, v7
v_add_f32_e32 v1, v1, v8
v_add_f32_e32 v3, v1, v9
v_lshlrev_b32_e32 v1, 2, v0
v_add_f32_e32 v2, v3, v2
ds_write_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB20_2
ds_read_b32 v2, v1 offset:64
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
ds_read_b32 v2, v1 offset:32
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
ds_read_b32 v2, v1 offset:16
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
ds_read_b32 v2, v1 offset:8
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
ds_read_b32 v2, v1 offset:4
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
BB20_2:
s_or_b32 exec_lo, exec_lo, s0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_barrier
v_cmp_gt_i32_e32 vcc_lo, 1, v0
ds_read_b32 v2, v1
s_waitcnt lgkmcnt(0)
ds_write_b32 v1, v2 offset:128
s_waitcnt lgkmcnt(0)
s_barrier
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB20_4
v_lshlrev_b32_e32 v1, 2, v0
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_add_nc_u32_e32 v0, s6, v0
ds_read_b32 v2, v1 offset:128
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_mul_f32_e32 v2, 0x3b800000, v2
global_store_dword v[0:1], v2, off
BB20_4:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_mean_1_kernel0
.amdhsa_group_segment_fixed_size 132
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end20:
.size tvmgen_default_fused_mean_1_kernel0, .Lfunc_end20-tvmgen_default_fused_mean_1_kernel0
.globl tvmgen_default_fused_mean_kernel0
.p2align 8
.type tvmgen_default_fused_mean_kernel0,@function
tvmgen_default_fused_mean_kernel0:
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_lshl_add_u32 v1, s6, 8, v0
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, 16, v0
s_clause 0x7
global_load_dword v3, v[1:2], off
global_load_dword v4, v[1:2], off offset:128
global_load_dword v5, v[1:2], off offset:256
global_load_dword v6, v[1:2], off offset:384
global_load_dword v7, v[1:2], off offset:512
global_load_dword v8, v[1:2], off offset:640
global_load_dword v9, v[1:2], off offset:768
global_load_dword v2, v[1:2], off offset:896
s_waitcnt vmcnt(0)
s_barrier
v_add_f32_e32 v1, 0, v3
v_add_f32_e32 v1, v1, v4
v_add_f32_e32 v1, v1, v5
v_add_f32_e32 v1, v1, v6
v_add_f32_e32 v1, v1, v7
v_add_f32_e32 v1, v1, v8
v_add_f32_e32 v3, v1, v9
v_lshlrev_b32_e32 v1, 2, v0
v_add_f32_e32 v2, v3, v2
ds_write_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB21_2
ds_read_b32 v2, v1 offset:64
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
ds_read_b32 v2, v1 offset:32
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
ds_read_b32 v2, v1 offset:16
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
ds_read_b32 v2, v1 offset:8
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
ds_read_b32 v2, v1 offset:4
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
BB21_2:
s_or_b32 exec_lo, exec_lo, s0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_barrier
v_cmp_gt_i32_e32 vcc_lo, 1, v0
ds_read_b32 v2, v1
s_waitcnt lgkmcnt(0)
ds_write_b32 v1, v2 offset:128
s_waitcnt lgkmcnt(0)
s_barrier
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB21_4
v_lshlrev_b32_e32 v1, 2, v0
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_add_nc_u32_e32 v0, s6, v0
ds_read_b32 v2, v1 offset:128
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_mul_f32_e32 v2, 0x3b800000, v2
global_store_dword v[0:1], v2, off
BB21_4:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_mean_kernel0
.amdhsa_group_segment_fixed_size 132
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end21:
.size tvmgen_default_fused_mean_kernel0, .Lfunc_end21-tvmgen_default_fused_mean_kernel0
.globl tvmgen_default_fused_nn_batch_matmul_1_kernel0
.p2align 8
.type tvmgen_default_fused_nn_batch_matmul_1_kernel0,@function
tvmgen_default_fused_nn_batch_matmul_1_kernel0:
s_mov_b32 s7, 0x66666667
v_add_nc_u32_e32 v3, 0x3c0, v0
v_mul_hi_i32 v13, v0, s7
s_mov_b32 s14, 0x10624dd3
s_movk_i32 s16, 0x500
s_movk_i32 s12, 0x258
v_add_nc_u32_e32 v8, s16, v0
v_mul_hi_u32 v3, v3, s14
s_and_b32 s2, s6, 3
s_ashr_i32 s3, s6, 2
v_ashrrev_i32_e32 v1, 4, v13
v_lshrrev_b32_e32 v14, 31, v13
v_mul_hi_u32 v8, v8, s14
s_clause 0x2
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[0:1], s[4:5], 0x10
s_mul_i32 s4, s2, 0x3a98
s_mul_i32 s5, s3, 0x1d4c0
v_add_nc_u32_e32 v1, v1, v14
s_mov_b32 s15, 0xea60
v_add_nc_u32_e32 v18, 0x730, v0
v_add_nc_u32_e32 v19, 0x780, v0
v_lshrrev_b32_e32 v8, 6, v8
v_add_nc_u32_e32 v4, 24, v1
v_mul_lo_u32 v16, v1, 40
v_ashrrev_i32_e32 v13, 1, v13
v_mul_hi_u32 v18, v18, s14
v_mul_hi_u32 v20, v19, s14
v_mul_hi_i32 v9, 0x51eb851f, v4
v_add_nc_u32_e32 v5, 0x410, v0
v_add_nc_u32_e32 v21, v13, v14
v_mad_u32_u24 v14, v0, 7, v19
v_add_nc_u32_e32 v6, 0x460, v0
v_add_nc_u32_e32 v7, 0x4b0, v0
v_lshrrev_b32_e32 v13, 6, v18
v_lshrrev_b32_e32 v18, 6, v20
v_lshrrev_b32_e32 v15, 31, v9
v_lshrrev_b32_e32 v9, 3, v9
v_add_nc_u32_e32 v10, 0x550, v0
v_add_nc_u32_e32 v11, 0x5a0, v0
v_add_nc_u32_e32 v12, 0x5f0, v0
v_mul_lo_u32 v19, v21, 5
v_add_nc_u32_e32 v9, v9, v15
v_lshrrev_b32_e32 v15, 6, v3
v_sub_nc_u32_e32 v3, v0, v16
v_mul_lo_u32 v16, v1, s12
v_mul_hi_i32 v22, v14, s7
v_mul_lo_u32 v9, v9, 25
v_mul_i32_i24_e32 v15, s15, v15
v_add3_u32 v17, s5, s4, v3
v_mul_i32_i24_e32 v20, s15, v13
v_mul_hi_u32 v5, v5, s14
v_mul_hi_u32 v6, v6, s14
v_mul_hi_u32 v7, v7, s14
v_mul_hi_u32 v10, v10, s14
v_sub_nc_u32_e32 v9, v4, v9
v_add_nc_u32_e32 v4, v17, v16
v_mul_i32_i24_e32 v16, s15, v8
v_mul_hi_u32 v11, v11, s14
v_mul_hi_u32 v12, v12, s14
v_mul_i32_i24_e32 v9, s12, v9
v_mul_i32_i24_e32 v18, s15, v18
v_sub_nc_u32_e32 v19, v0, v19
v_lshrrev_b32_e32 v5, 6, v5
v_lshrrev_b32_e32 v6, 6, v6
v_add3_u32 v8, v17, v15, v9
v_add3_u32 v9, v4, v16, 0x1068
v_add_nc_u32_e32 v16, 0x690, v0
v_add_nc_u32_e32 v15, 0x640, v0
v_add_nc_u32_e32 v17, 0x6e0, v0
v_lshrrev_b32_e32 v7, 6, v7
v_lshrrev_b32_e32 v10, 6, v10
v_mul_hi_u32 v16, v16, s14
v_mul_hi_u32 v15, v15, s14
v_mul_hi_u32 v17, v17, s14
v_lshrrev_b32_e32 v11, 6, v11
v_lshrrev_b32_e32 v12, 6, v12
v_lshlrev_b32_e32 v19, 3, v19
v_and_b32_e32 v23, 7, v0
v_lshrrev_b32_e32 v24, 3, v0
v_lshrrev_b32_e32 v16, 6, v16
v_lshrrev_b32_e32 v15, 6, v15
v_lshrrev_b32_e32 v17, 6, v17
v_mul_lo_u32 v25, v1, s16
v_mul_i32_i24_e32 v5, s15, v5
v_mul_i32_i24_e32 v16, s15, v16
v_mul_i32_i24_e32 v15, s15, v15
v_mul_i32_i24_e32 v17, s15, v17
v_mul_i32_i24_e32 v6, s15, v6
v_mul_i32_i24_e32 v7, s15, v7
v_add3_u32 v14, v4, v16, 0x27d8
v_add3_u32 v16, v4, v20, 0x3138
v_lshrrev_b32_e32 v20, 9, v22
v_add3_u32 v13, v4, v15, 0x2328
v_add3_u32 v15, v4, v17, 0x2c88
v_add3_u32 v17, v4, v18, 0x35e8
v_mul_lo_u32 v18, v21, s12
v_mul_lo_u32 v21, v21, 40
v_mul_i32_i24_e32 v22, s16, v20
v_mul_i32_i24_e32 v10, s15, v10
v_mul_i32_i24_e32 v11, s15, v11
v_mul_i32_i24_e32 v12, s15, v12
s_movk_i32 s13, 0x1400
s_mul_i32 s4, s3, 0x9600
v_lshl_add_u32 v2, v0, 1, s13
v_add3_u32 v21, v21, v19, v22
v_mul_u32_u24_e32 v22, 0xa0, v23
v_mul_u32_u24_e32 v23, 0xc8, v24
v_add3_u32 v18, v19, s4, v18
v_add3_u32 v5, v4, v5, s12
v_add3_u32 v6, v4, v6, 0x708
v_add_lshl_u32 v22, v22, v25, 1
v_add3_u32 v7, v4, v7, 0xbb8
v_add3_u32 v10, v4, v10, 0x1518
v_add3_u32 v11, v4, v11, 0x19c8
v_add3_u32 v12, v4, v12, 0x1e78
v_lshlrev_b32_e32 v19, 4, v0
v_mul_i32_i24_e32 v20, 0x4b00, v20
v_lshl_add_u32 v21, v21, 1, s16
v_lshl_add_u32 v23, v23, 1, s13
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v24, 0xffff
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v28, 0
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v30, 0
v_mov_b32_e32 v29, 0
v_mov_b32_e32 v32, 0
v_mov_b32_e32 v31, 0
v_mov_b32_e32 v34, 0
v_mov_b32_e32 v33, 0
s_mov_b32 s4, 0
s_movk_i32 s5, 0x4800
BB22_1:
s_mul_i32 s6, s4, 40
v_add_nc_u32_e32 v35, s6, v4
v_add_nc_u32_e32 v37, s6, v8
v_add_nc_u32_e32 v39, s6, v5
v_add_nc_u32_e32 v49, s6, v6
v_add_nc_u32_e32 v53, s6, v7
v_ashrrev_i32_e32 v36, 31, v35
v_ashrrev_i32_e32 v38, 31, v37
v_ashrrev_i32_e32 v40, 31, v39
v_ashrrev_i32_e32 v50, 31, v49
v_ashrrev_i32_e32 v54, 31, v53
v_lshlrev_b64 v[35:36], 1, v[35:36]
v_lshlrev_b64 v[37:38], 1, v[37:38]
v_lshlrev_b64 v[39:40], 1, v[39:40]
v_add_nc_u32_e32 v57, s6, v10
v_lshlrev_b64 v[53:54], 1, v[53:54]
v_add_nc_u32_e32 v61, s6, v12
s_waitcnt lgkmcnt(0)
v_add_co_u32 v35, vcc_lo, s8, v35
v_add_nc_u32_e32 v63, s6, v13
v_add_co_ci_u32_e32 v36, vcc_lo, s9, v36, vcc_lo
v_ashrrev_i32_e32 v58, 31, v57
v_ashrrev_i32_e32 v62, 31, v61
v_add_co_u32 v41, vcc_lo, 0x800, v35
v_add_nc_u32_e32 v65, s6, v14
v_add_co_ci_u32_e32 v42, vcc_lo, 0, v36, vcc_lo
v_add_co_u32 v43, vcc_lo, 0x1000, v35
v_lshlrev_b64 v[57:58], 1, v[57:58]
v_add_co_ci_u32_e32 v44, vcc_lo, 0, v36, vcc_lo
v_add_co_u32 v45, vcc_lo, 0x1800, v35
v_ashrrev_i32_e32 v64, 31, v63
v_add_co_ci_u32_e32 v46, vcc_lo, 0, v36, vcc_lo
v_add_co_u32 v47, vcc_lo, 0x2000, v35
v_add_nc_u32_e32 v67, s6, v15
v_add_co_ci_u32_e32 v48, vcc_lo, 0, v36, vcc_lo
v_add_co_u32 v51, vcc_lo, 0x2800, v35
v_lshlrev_b64 v[61:62], 1, v[61:62]
v_add_co_ci_u32_e32 v52, vcc_lo, 0, v36, vcc_lo
v_add_co_u32 v55, vcc_lo, s8, v37
v_ashrrev_i32_e32 v66, 31, v65
v_add_co_ci_u32_e32 v56, vcc_lo, s9, v38, vcc_lo
v_lshlrev_b64 v[37:38], 1, v[49:50]
v_add_nc_u32_e32 v49, s6, v9
v_add_co_u32 v39, vcc_lo, s8, v39
v_add_nc_u32_e32 v69, s6, v16
v_add_co_ci_u32_e32 v40, vcc_lo, s9, v40, vcc_lo
v_lshlrev_b64 v[63:64], 1, v[63:64]
v_ashrrev_i32_e32 v50, 31, v49
v_add_co_u32 v59, vcc_lo, s8, v37
v_ashrrev_i32_e32 v68, 31, v67
v_add_co_ci_u32_e32 v60, vcc_lo, s9, v38, vcc_lo
v_add_co_u32 v53, vcc_lo, s8, v53
v_lshlrev_b64 v[37:38], 1, v[49:50]
v_add_nc_u32_e32 v49, s6, v11
v_add_co_ci_u32_e32 v54, vcc_lo, s9, v54, vcc_lo
v_add_nc_u32_e32 v71, s6, v17
v_lshlrev_b64 v[65:66], 1, v[65:66]
v_ashrrev_i32_e32 v70, 31, v69
v_ashrrev_i32_e32 v50, 31, v49
v_add_co_u32 v37, vcc_lo, s8, v37
v_lshlrev_b64 v[67:68], 1, v[67:68]
v_add_co_ci_u32_e32 v38, vcc_lo, s9, v38, vcc_lo
v_add_co_u32 v57, vcc_lo, s8, v57
v_lshlrev_b64 v[49:50], 1, v[49:50]
v_add_co_ci_u32_e32 v58, vcc_lo, s9, v58, vcc_lo
v_ashrrev_i32_e32 v72, 31, v71
v_lshlrev_b64 v[69:70], 1, v[69:70]
v_add_nc_u32_e32 v83, s6, v18
s_mov_b32 s6, 0
v_add_co_u32 v49, vcc_lo, s8, v49
v_lshlrev_b64 v[71:72], 1, v[71:72]
v_add_co_ci_u32_e32 v50, vcc_lo, s9, v50, vcc_lo
v_add_co_u32 v61, vcc_lo, s8, v61
v_ashrrev_i32_e32 v84, 31, v83
v_add_co_ci_u32_e32 v62, vcc_lo, s9, v62, vcc_lo
v_add_co_u32 v63, vcc_lo, s8, v63
v_add_co_ci_u32_e32 v64, vcc_lo, s9, v64, vcc_lo
v_add_co_u32 v65, vcc_lo, s8, v65
v_add_co_ci_u32_e32 v66, vcc_lo, s9, v66, vcc_lo
v_add_co_u32 v67, vcc_lo, s8, v67
v_add_co_ci_u32_e32 v68, vcc_lo, s9, v68, vcc_lo
v_add_co_u32 v69, vcc_lo, s8, v69
v_add_co_ci_u32_e32 v70, vcc_lo, s9, v70, vcc_lo
v_add_co_u32 v71, vcc_lo, s8, v71
v_add_co_ci_u32_e32 v72, vcc_lo, s9, v72, vcc_lo
v_add_co_u32 v73, vcc_lo, 0x3800, v35
v_add_co_ci_u32_e32 v74, vcc_lo, 0, v36, vcc_lo
v_add_co_u32 v75, vcc_lo, 0x4000, v35
v_add_co_ci_u32_e32 v76, vcc_lo, 0, v36, vcc_lo
v_add_co_u32 v77, vcc_lo, s5, v35
s_clause 0x7
global_load_ushort v87, v[35:36], off
global_load_ushort v88, v[41:42], off offset:352
global_load_ushort v89, v[43:44], off offset:704
global_load_ushort v90, v[45:46], off offset:1056
global_load_ushort v91, v[47:48], off offset:1408
global_load_ushort v51, v[51:52], off offset:1760
global_load_ushort v52, v[73:74], off offset:64
global_load_ushort v73, v[75:76], off offset:416
v_add_co_ci_u32_e32 v78, vcc_lo, 0, v36, vcc_lo
v_add_co_u32 v79, vcc_lo, 0x5000, v35
v_add3_u32 v41, v83, v20, 0x2580
v_add_co_ci_u32_e32 v80, vcc_lo, 0, v36, vcc_lo
v_add_co_u32 v81, vcc_lo, 0x5800, v35
s_clause 0x8
global_load_ushort v74, v[37:38], off
global_load_ushort v57, v[57:58], off
global_load_ushort v58, v[49:50], off
global_load_ushort v61, v[61:62], off
global_load_ushort v62, v[63:64], off
global_load_ushort v63, v[65:66], off
global_load_ushort v64, v[67:68], off
global_load_ushort v65, v[69:70], off
global_load_ushort v66, v[71:72], off
v_add_co_ci_u32_e32 v82, vcc_lo, 0, v36, vcc_lo
v_add_co_u32 v85, vcc_lo, 0x6000, v35
v_ashrrev_i32_e32 v42, 31, v41
v_add_co_ci_u32_e32 v86, vcc_lo, 0, v36, vcc_lo
v_lshlrev_b64 v[35:36], 1, v[83:84]
v_lshlrev_b64 v[41:42], 1, v[41:42]
v_add_co_u32 v43, vcc_lo, s10, v35
v_add_co_ci_u32_e32 v44, vcc_lo, s11, v36, vcc_lo
v_add_co_u32 v45, vcc_lo, s5, v43
v_add_co_ci_u32_e32 v46, vcc_lo, 0, v44, vcc_lo
v_add_co_u32 v47, vcc_lo, s10, v41
global_load_dwordx4 v[35:38], v[43:44], off
v_add_co_ci_u32_e32 v48, vcc_lo, s11, v42, vcc_lo
v_add_co_u32 v43, vcc_lo, 0x9000, v43
v_add_co_ci_u32_e32 v44, vcc_lo, 0, v44, vcc_lo
s_clause 0x7
global_load_ushort v67, v[77:78], off offset:768
global_load_ushort v68, v[79:80], off offset:1120
global_load_ushort v69, v[81:82], off offset:1472
global_load_ushort v70, v[85:86], off offset:1824
global_load_ushort v55, v[55:56], off
global_load_ushort v56, v[39:40], off
global_load_ushort v59, v[59:60], off
global_load_ushort v53, v[53:54], off
s_clause 0x2
global_load_dwordx4 v[39:42], v[45:46], off offset:768
global_load_dwordx4 v[43:46], v[43:44], off offset:1536
global_load_dwordx4 v[47:50], v[47:48], off
s_waitcnt vmcnt(0)
s_barrier
ds_write_b16 v2, v87
ds_write_b16 v2, v74 offset:2560
ds_write_b16 v2, v57 offset:2720
ds_write_b16 v2, v58 offset:2880
ds_write_b16 v2, v61 offset:3040
ds_write_b16 v2, v62 offset:3200
ds_write_b16 v2, v63 offset:3360
ds_write_b16 v2, v64 offset:3520
ds_write_b16 v2, v65 offset:3680
ds_write_b16 v2, v66 offset:3840
ds_write_b128 v19, v[35:38]
ds_write_b16 v2, v88 offset:160
ds_write_b16 v2, v89 offset:320
ds_write_b16 v2, v90 offset:480
ds_write_b16 v2, v91 offset:640
ds_write_b16 v2, v51 offset:800
ds_write_b16 v2, v52 offset:960
ds_write_b16 v2, v73 offset:1120
ds_write_b16 v2, v67 offset:1280
ds_write_b16 v2, v68 offset:1440
ds_write_b16 v2, v69 offset:1600
ds_write_b16 v2, v70 offset:1760
ds_write_b16 v2, v55 offset:1920
ds_write_b16 v2, v56 offset:2080
ds_write_b16 v2, v59 offset:2240
ds_write_b16 v2, v53 offset:2400
ds_write_b128 v19, v[39:42] offset:1280
ds_write_b128 v19, v[43:46] offset:2560
ds_write_b128 v21, v[47:50]
s_waitcnt lgkmcnt(0)
s_barrier
BB22_2:
v_add_nc_u32_e32 v47, s6, v22
v_add_nc_u32_e32 v67, s6, v23
s_add_i32 s6, s6, 16
s_cmpk_lg_i32 s6, 0x50
ds_read_b128 v[35:38], v47 offset:80
ds_read_b128 v[39:42], v47
ds_read_b128 v[43:46], v47 offset:160
ds_read_b128 v[47:50], v47 offset:240
ds_read_b128 v[51:54], v67
ds_read_b128 v[55:58], v67 offset:80
ds_read_b128 v[59:62], v67 offset:160
ds_read_b128 v[63:66], v67 offset:240
ds_read_b128 v[67:70], v67 offset:320
s_waitcnt lgkmcnt(8)
v_lshrrev_b32_e32 v71, 16, v35
s_waitcnt lgkmcnt(7)
v_and_b32_e32 v75, v24, v39
s_waitcnt lgkmcnt(6)
v_and_b32_e32 v79, v24, v43
v_and_b32_sdwa v39, v24, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
s_waitcnt lgkmcnt(5)
v_lshrrev_b32_e32 v83, 16, v47
v_and_b32_sdwa v43, v24, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v35, v35, 16, v75
v_lshl_or_b32 v47, v47, 16, v79
v_and_b32_e32 v76, v24, v40
v_and_b32_e32 v80, v24, v44
v_lshl_or_b32 v39, v71, 16, v39
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v34, v51, v35, v34 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v32, v55, v35, v32 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v30, v59, v35, v30 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v28, v63, v35, v28 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v25, v67, v35, v25 op_sel_hi:[0,1,1]
v_lshl_or_b32 v43, v83, 16, v43
v_pk_fma_f16 v33, v51, v47, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v55, v47, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v59, v47, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v63, v47, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v67, v47, v26 op_sel_hi:[0,1,1]
v_lshrrev_b32_e32 v72, 16, v36
v_and_b32_sdwa v40, v24, v40 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v84, 16, v48
v_and_b32_sdwa v44, v24, v44 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v36, v36, 16, v76
v_pk_fma_f16 v34, v51, v39, v34 op_sel:[1,0,0]
v_pk_fma_f16 v32, v55, v39, v32 op_sel:[1,0,0]
v_pk_fma_f16 v30, v59, v39, v30 op_sel:[1,0,0]
v_pk_fma_f16 v28, v63, v39, v28 op_sel:[1,0,0]
v_pk_fma_f16 v25, v67, v39, v25 op_sel:[1,0,0]
v_lshl_or_b32 v48, v48, 16, v80
v_pk_fma_f16 v33, v51, v43, v33 op_sel:[1,0,0]
v_pk_fma_f16 v31, v55, v43, v31 op_sel:[1,0,0]
v_pk_fma_f16 v29, v59, v43, v29 op_sel:[1,0,0]
v_pk_fma_f16 v27, v63, v43, v27 op_sel:[1,0,0]
v_pk_fma_f16 v26, v67, v43, v26 op_sel:[1,0,0]
v_and_b32_e32 v77, v24, v41
v_and_b32_e32 v81, v24, v45
v_lshl_or_b32 v40, v72, 16, v40
v_pk_fma_f16 v34, v52, v36, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v56, v36, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v60, v36, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v64, v36, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v68, v36, v25 op_sel_hi:[0,1,1]
v_lshl_or_b32 v44, v84, 16, v44
v_pk_fma_f16 v33, v52, v48, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v56, v48, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v60, v48, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v64, v48, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v68, v48, v26 op_sel_hi:[0,1,1]
v_lshrrev_b32_e32 v73, 16, v37
v_and_b32_sdwa v41, v24, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v85, 16, v49
v_and_b32_sdwa v45, v24, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v37, v37, 16, v77
v_pk_fma_f16 v34, v52, v40, v34 op_sel:[1,0,0]
v_pk_fma_f16 v32, v56, v40, v32 op_sel:[1,0,0]
v_pk_fma_f16 v30, v60, v40, v30 op_sel:[1,0,0]
v_pk_fma_f16 v28, v64, v40, v28 op_sel:[1,0,0]
v_pk_fma_f16 v25, v68, v40, v25 op_sel:[1,0,0]
v_lshl_or_b32 v49, v49, 16, v81
v_pk_fma_f16 v33, v52, v44, v33 op_sel:[1,0,0]
v_pk_fma_f16 v31, v56, v44, v31 op_sel:[1,0,0]
v_pk_fma_f16 v29, v60, v44, v29 op_sel:[1,0,0]
v_pk_fma_f16 v27, v64, v44, v27 op_sel:[1,0,0]
v_pk_fma_f16 v26, v68, v44, v26 op_sel:[1,0,0]
v_and_b32_e32 v78, v24, v42
v_and_b32_e32 v82, v24, v46
v_lshl_or_b32 v41, v73, 16, v41
v_pk_fma_f16 v34, v53, v37, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v57, v37, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v61, v37, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v65, v37, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v69, v37, v25 op_sel_hi:[0,1,1]
v_lshl_or_b32 v45, v85, 16, v45
v_pk_fma_f16 v33, v53, v49, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v57, v49, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v61, v49, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v65, v49, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v69, v49, v26 op_sel_hi:[0,1,1]
v_lshrrev_b32_e32 v74, 16, v38
v_and_b32_sdwa v42, v24, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v86, 16, v50
v_and_b32_sdwa v46, v24, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v38, v38, 16, v78
v_pk_fma_f16 v34, v53, v41, v34 op_sel:[1,0,0]
v_pk_fma_f16 v32, v57, v41, v32 op_sel:[1,0,0]
v_pk_fma_f16 v30, v61, v41, v30 op_sel:[1,0,0]
v_pk_fma_f16 v28, v65, v41, v28 op_sel:[1,0,0]
v_pk_fma_f16 v25, v69, v41, v25 op_sel:[1,0,0]
v_lshl_or_b32 v50, v50, 16, v82
v_pk_fma_f16 v33, v53, v45, v33 op_sel:[1,0,0]
v_pk_fma_f16 v31, v57, v45, v31 op_sel:[1,0,0]
v_pk_fma_f16 v29, v61, v45, v29 op_sel:[1,0,0]
v_pk_fma_f16 v27, v65, v45, v27 op_sel:[1,0,0]
v_pk_fma_f16 v26, v69, v45, v26 op_sel:[1,0,0]
v_lshl_or_b32 v42, v74, 16, v42
v_pk_fma_f16 v34, v54, v38, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v58, v38, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v62, v38, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v66, v38, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v70, v38, v25 op_sel_hi:[0,1,1]
v_lshl_or_b32 v46, v86, 16, v46
v_pk_fma_f16 v33, v54, v50, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v58, v50, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v62, v50, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v66, v50, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v70, v50, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v54, v42, v34 op_sel:[1,0,0]
v_pk_fma_f16 v33, v54, v46, v33 op_sel:[1,0,0]
v_pk_fma_f16 v32, v58, v42, v32 op_sel:[1,0,0]
v_pk_fma_f16 v31, v58, v46, v31 op_sel:[1,0,0]
v_pk_fma_f16 v30, v62, v42, v30 op_sel:[1,0,0]
v_pk_fma_f16 v29, v62, v46, v29 op_sel:[1,0,0]
v_pk_fma_f16 v28, v66, v42, v28 op_sel:[1,0,0]
v_pk_fma_f16 v27, v66, v46, v27 op_sel:[1,0,0]
v_pk_fma_f16 v25, v70, v42, v25 op_sel:[1,0,0]
v_pk_fma_f16 v26, v70, v46, v26 op_sel:[1,0,0]
s_cbranch_scc1 BB22_2
s_add_i32 s4, s4, 1
s_cmp_eq_u32 s4, 15
s_cbranch_scc0 BB22_1
v_mul_lo_u32 v1, 0xc80, v1
v_ashrrev_i32_e32 v2, 3, v3
s_mulk_i32 s2, 0x320
s_mulk_i32 s3, 0x1900
v_lshlrev_b32_e32 v0, 2, v0
v_mul_lo_u32 v2, 0xa0, v2
v_add3_u32 v1, s2, s3, v1
v_and_or_b32 v0, v0, 28, v1
v_add_nc_u32_e32 v0, v0, v2
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_dword v[0:1], v34, off
global_store_dword v[0:1], v33, off offset:4
global_store_dword v[0:1], v32, off offset:64
global_store_dword v[0:1], v31, off offset:68
global_store_dword v[0:1], v30, off offset:128
global_store_dword v[0:1], v29, off offset:132
global_store_dword v[0:1], v28, off offset:192
global_store_dword v[0:1], v27, off offset:196
global_store_dword v[0:1], v25, off offset:256
global_store_dword v[0:1], v26, off offset:260
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_batch_matmul_1_kernel0
.amdhsa_group_segment_fixed_size 9120
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 92
.amdhsa_next_free_sgpr 17
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end22:
.size tvmgen_default_fused_nn_batch_matmul_1_kernel0, .Lfunc_end22-tvmgen_default_fused_nn_batch_matmul_1_kernel0
.globl tvmgen_default_fused_nn_batch_matmul_2_kernel0
.p2align 8
.type tvmgen_default_fused_nn_batch_matmul_2_kernel0,@function
tvmgen_default_fused_nn_batch_matmul_2_kernel0:
s_mov_b32 s0, 0x66666667
s_mov_b32 s12, 0x51eb851f
v_mul_hi_i32 v1, v0, s0
s_mul_hi_i32 s3, s6, s0
s_clause 0x2
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[0:1], s[4:5], 0x10
s_lshr_b32 s4, s3, 31
s_ashr_i32 s3, s3, 3
s_movk_i32 s7, 0x64
s_add_i32 s5, s3, s4
v_add_nc_u32_e32 v3, 0x230, v0
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v1, 3, v1
s_mul_i32 s4, s5, 0x4e20
s_movk_i32 s13, 0x2710
v_add_nc_u32_e32 v5, 0xf0, v0
v_mul_hi_u32 v7, v3, s12
v_add_nc_u32_e32 v4, v1, v2
v_add_nc_u32_e32 v2, 0x1e0, v0
s_movk_i32 s14, 0x320
s_and_b32 s3, s6, 3
s_movk_i32 s2, 0x280
v_mul_i32_i24_e32 v1, 20, v4
v_mul_hi_u32 v2, v2, s12
v_mad_i32_i24 v19, v4, s7, 0x190
v_lshrrev_b32_e32 v21, 7, v7
v_mul_i32_i24_e32 v7, s7, v4
v_sub_nc_u32_e32 v18, v0, v1
s_mul_i32 s15, s3, s14
v_add_nc_u32_e32 v6, s2, v0
v_add_nc_u32_e32 v23, 0x2d0, v0
v_lshrrev_b32_e32 v2, 7, v2
v_add_nc_u32_e32 v1, s4, v18
s_mul_i32 s4, s5, 20
s_mulk_i32 s5, 0x1900
s_sub_i32 s4, s6, s4
s_add_i32 s15, s15, s5
v_mad_i32_i24 v8, v4, s7, v1
s_ashr_i32 s4, s4, 2
v_mad_i32_i24 v1, v2, s13, v1
s_mul_i32 s16, s4, 0x7d0
v_add3_u32 v7, v7, v18, s15
v_add_nc_u32_e32 v9, s16, v8
s_movk_i32 s6, 0xc80
v_add3_u32 v3, v1, s16, v19
v_add_nc_u32_e32 v18, s15, v18
v_mad_i32_i24 v21, v21, s13, v8
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v4, 31, v3
v_mul_hi_u32 v20, v6, s12
v_add3_u32 v22, v21, s16, s14
v_lshlrev_b64 v[1:2], 1, v[9:10]
v_mul_hi_u32 v10, 0xcccccccd, v5
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_lshlrev_b64 v[7:8], 1, v[7:8]
v_mul_hi_u32 v21, v23, s12
v_ashrrev_i32_e32 v23, 31, v22
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s8, v1
v_lshrrev_b32_e32 v20, 7, v20
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
v_lshrrev_b32_e32 v10, 7, v10
v_lshlrev_b64 v[28:29], 1, v[22:23]
v_add_co_u32 v5, vcc_lo, 0x800, v1
v_mul_i32_i24_e32 v20, s13, v20
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v2, vcc_lo
v_mul_i32_i24_e32 v10, s6, v10
v_add_co_u32 v3, vcc_lo, s8, v3
s_clause 0x3
global_load_ushort v12, v[1:2], off
global_load_ushort v13, v[1:2], off offset:800
global_load_ushort v14, v[1:2], off offset:1600
global_load_ushort v11, v[5:6], off offset:352
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
v_add_co_u32 v16, vcc_lo, 0x4800, v1
v_add3_u32 v18, v18, v10, v19
v_add_co_ci_u32_e32 v17, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v7, vcc_lo, s10, v7
v_lshrrev_b32_e32 v10, 7, v21
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
v_ashrrev_i32_e32 v19, 31, v18
v_add3_u32 v26, v9, v20, 0x4b0
v_add_co_u32 v24, vcc_lo, 0x1800, v7
v_mul_i32_i24_e32 v10, s13, v10
v_add_co_ci_u32_e32 v25, vcc_lo, 0, v8, vcc_lo
v_lshlrev_b64 v[18:19], 1, v[18:19]
s_clause 0x1
global_load_ushort v20, v[7:8], off
global_load_ushort v21, v[7:8], off offset:800
global_load_ushort v15, v[3:4], off
v_add3_u32 v9, v9, v10, 0x640
v_ashrrev_i32_e32 v27, 31, v26
v_lshrrev_b32_e32 v35, 3, v0
v_add_co_u32 v18, vcc_lo, s10, v18
v_and_b32_e32 v36, 7, v0
v_add_co_ci_u32_e32 v19, vcc_lo, s11, v19, vcc_lo
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[26:27], 1, v[26:27]
v_add_co_u32 v31, vcc_lo, s8, v28
s_clause 0x1
global_load_ushort v22, v[24:25], off offset:256
global_load_ushort v23, v[18:19], off
v_add_co_ci_u32_e32 v32, vcc_lo, s9, v29, vcc_lo
v_lshlrev_b64 v[9:10], 1, v[9:10]
v_mul_u32_u24_e32 v37, 40, v35
v_add_co_u32 v33, vcc_lo, s8, v26
v_mul_u32_u24_e32 v38, 20, v36
v_add_co_ci_u32_e32 v34, vcc_lo, s9, v27, vcc_lo
v_lshlrev_b32_e32 v95, 1, v0
v_add_co_u32 v9, vcc_lo, s8, v9
v_lshlrev_b32_e32 v37, 1, v37
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
s_clause 0xe
global_load_ushort v26, v[5:6], off offset:1152
global_load_ushort v27, v[16:17], off offset:1568
global_load_ushort v28, v[31:32], off
global_load_ushort v29, v[33:34], off
global_load_ushort v30, v[9:10], off
global_load_ushort v67, v[1:2], off offset:40
global_load_ushort v68, v[1:2], off offset:840
global_load_ushort v69, v[1:2], off offset:1640
global_load_ushort v70, v[5:6], off offset:392
global_load_ushort v71, v[5:6], off offset:1192
global_load_ushort v72, v[16:17], off offset:1608
global_load_ushort v73, v[3:4], off offset:40
global_load_ushort v74, v[31:32], off offset:40
global_load_ushort v75, v[33:34], off offset:40
global_load_ushort v76, v[9:10], off offset:40
s_clause 0x3
global_load_ushort v77, v[7:8], off offset:40
global_load_ushort v78, v[7:8], off offset:840
global_load_ushort v79, v[24:25], off offset:296
global_load_ushort v80, v[18:19], off offset:40
s_clause 0x9
global_load_ushort v81, v[1:2], off offset:80
global_load_ushort v82, v[1:2], off offset:880
global_load_ushort v83, v[1:2], off offset:1680
global_load_ushort v84, v[5:6], off offset:432
global_load_ushort v85, v[5:6], off offset:1232
global_load_ushort v86, v[16:17], off offset:1648
global_load_ushort v87, v[3:4], off offset:80
global_load_ushort v88, v[31:32], off offset:80
global_load_ushort v89, v[33:34], off offset:80
global_load_ushort v90, v[9:10], off offset:80
s_clause 0x3
global_load_ushort v91, v[7:8], off offset:80
global_load_ushort v92, v[7:8], off offset:880
global_load_ushort v93, v[24:25], off offset:336
global_load_ushort v94, v[18:19], off offset:80
v_lshlrev_b32_e32 v38, 1, v38
s_clause 0x4
global_load_ushort v96, v[7:8], off offset:120
global_load_ushort v97, v[7:8], off offset:160
global_load_ushort v98, v[24:25], off offset:376
global_load_ushort v99, v[24:25], off offset:416
global_load_ushort v100, v[7:8], off offset:960
s_clause 0xe
global_load_ushort v101, v[1:2], off offset:120
global_load_ushort v102, v[1:2], off offset:1720
global_load_ushort v103, v[1:2], off offset:160
global_load_ushort v104, v[16:17], off offset:1688
global_load_ushort v105, v[16:17], off offset:1728
global_load_ushort v106, v[31:32], off offset:120
global_load_ushort v107, v[31:32], off offset:160
global_load_ushort v108, v[33:34], off offset:120
global_load_ushort v109, v[33:34], off offset:160
global_load_ushort v110, v[1:2], off offset:1760
global_load_ushort v111, v[1:2], off offset:960
global_load_ushort v112, v[5:6], off offset:1272
global_load_ushort v113, v[5:6], off offset:512
global_load_ushort v114, v[5:6], off offset:1312
global_load_ushort v115, v[3:4], off offset:160
global_load_ushort v118, v[7:8], off offset:920
global_load_ushort v119, v[5:6], off offset:472
s_mul_i32 s4, s4, s2
s_waitcnt vmcnt(59)
ds_write_b16 v95, v20
s_waitcnt vmcnt(58)
ds_write_b16 v95, v21 offset:160
s_waitcnt vmcnt(56)
ds_write_b16 v95, v22 offset:320
s_waitcnt vmcnt(55)
ds_write_b16 v95, v23 offset:480
ds_write_b16 v95, v12 offset:640
ds_write_b16 v95, v13 offset:800
ds_write_b16 v95, v14 offset:960
ds_write_b16 v95, v15 offset:1600
ds_write_b16 v95, v11 offset:1120
s_waitcnt vmcnt(54)
ds_write_b16 v95, v26 offset:1280
s_waitcnt vmcnt(53)
ds_write_b16 v95, v27 offset:1440
s_waitcnt vmcnt(52)
ds_write_b16 v95, v28 offset:1760
s_waitcnt vmcnt(51)
ds_write_b16 v95, v29 offset:1920
s_waitcnt vmcnt(50)
ds_write_b16 v95, v30 offset:2080
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
ds_read_b128 v[11:14], v37 offset:640
ds_read2_b64 v[20:23], v38 offset1:1
ds_read2_b64 v[24:27], v37 offset0:85 offset1:86
s_clause 0x1
global_load_ushort v116, v[18:19], off offset:120
global_load_ushort v117, v[18:19], off offset:160
ds_read_b128 v[15:18], v37 offset:656
ds_read2_b64 v[28:31], v38 offset0:2 offset1:3
ds_read2_b64 v[39:42], v37 offset0:87 offset1:88
s_clause 0x3
global_load_ushort v120, v[3:4], off offset:120
global_load_ushort v121, v[1:2], off offset:920
global_load_ushort v122, v[9:10], off offset:120
global_load_ushort v123, v[9:10], off offset:160
s_waitcnt lgkmcnt(5)
v_lshrrev_b32_e32 v19, 16, v11
s_waitcnt lgkmcnt(4)
v_lshrrev_b32_e32 v32, 16, v20
v_fma_f16 v0, v11, v20, 0
s_waitcnt lgkmcnt(3)
v_lshrrev_b32_e32 v8, 16, v24
v_fma_f16 v7, v24, v20, 0
v_lshrrev_b32_e32 v5, 16, v12
v_lshrrev_b32_e32 v6, 16, v21
v_fmac_f16_e32 v0, v19, v32
v_lshrrev_b32_e32 v1, 16, v25
v_fmac_f16_e32 v7, v8, v32
v_lshrrev_b32_e32 v24, 16, v22
v_fmac_f16_e32 v0, v12, v21
v_lshrrev_b32_e32 v12, 16, v13
v_fmac_f16_e32 v7, v25, v21
v_fmac_f16_e32 v0, v5, v6
ds_read_b128 v[2:5], v37 offset:1440
ds_read_b128 v[8:11], v37 offset:1456
v_fmac_f16_e32 v7, v1, v6
v_lshrrev_b32_e32 v1, 16, v26
v_fmac_f16_e32 v0, v13, v22
v_lshrrev_b32_e32 v13, 16, v23
v_fmac_f16_e32 v7, v26, v22
ds_read2_b64 v[19:22], v38 offset0:40 offset1:41
ds_read2_b64 v[43:46], v38 offset0:42 offset1:43
ds_read2_b64 v[47:50], v37 offset0:185 offset1:186
ds_read2_b64 v[51:54], v37 offset0:187 offset1:188
ds_read2_b64 v[55:58], v38 offset0:4 offset1:44
ds_read2_b64 v[59:62], v37 offset0:84 offset1:89
ds_read2_b64 v[63:66], v37 offset0:184 offset1:189
v_fmac_f16_e32 v0, v12, v24
v_lshrrev_b32_e32 v12, 16, v14
v_fmac_f16_e32 v7, v1, v24
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
ds_write_b16 v95, v67 offset:640
ds_write_b16 v95, v68 offset:800
ds_write_b16 v95, v69 offset:960
ds_write_b16 v95, v70 offset:1120
ds_write_b16 v95, v71 offset:1280
ds_write_b16 v95, v72 offset:1440
ds_write_b16 v95, v73 offset:1600
ds_write_b16 v95, v74 offset:1760
ds_write_b16 v95, v75 offset:1920
ds_write_b16 v95, v76 offset:2080
ds_write_b16 v95, v77
ds_write_b16 v95, v78 offset:160
v_fmac_f16_e32 v0, v14, v23
ds_write_b16 v95, v79 offset:320
v_fmac_f16_e32 v7, v27, v23
v_lshrrev_b32_e32 v27, 16, v27
ds_write_b16 v95, v80 offset:480
v_lshrrev_b32_e32 v6, 16, v2
v_fmac_f16_e32 v0, v12, v13
v_lshrrev_b32_e32 v12, 16, v15
v_fmac_f16_e32 v7, v27, v13
v_lshrrev_b32_e32 v13, 16, v28
v_lshrrev_b32_e32 v23, 16, v47
v_lshrrev_b32_e32 v33, 16, v50
v_fma_f16 v1, v2, v19, 0
v_lshrrev_b32_e32 v14, 16, v19
v_fma_f16 v2, v47, v19, 0
v_lshrrev_b32_e32 v32, 16, v22
v_fmac_f16_e32 v0, v15, v28
v_lshrrev_b32_e32 v15, 16, v39
v_fmac_f16_e32 v1, v6, v14
v_fmac_f16_e32 v2, v23, v14
v_lshrrev_b32_e32 v6, 16, v3
v_lshrrev_b32_e32 v14, 16, v20
v_fmac_f16_e32 v7, v39, v28
v_fmac_f16_e32 v1, v3, v20
v_lshrrev_b32_e32 v3, 16, v48
v_fmac_f16_e32 v2, v48, v20
v_fmac_f16_e32 v0, v12, v13
v_fmac_f16_e32 v7, v15, v13
v_fmac_f16_e32 v1, v6, v14
v_lshrrev_b32_e32 v6, 16, v21
v_fmac_f16_e32 v2, v3, v14
v_lshrrev_b32_e32 v3, 16, v4
v_lshrrev_b32_e32 v14, 16, v5
v_fmac_f16_e32 v1, v4, v21
v_lshrrev_b32_e32 v4, 16, v49
v_fmac_f16_e32 v2, v49, v21
v_lshrrev_b32_e32 v27, 16, v8
v_lshrrev_b32_e32 v12, 16, v43
v_fmac_f16_e32 v1, v3, v6
v_lshrrev_b32_e32 v13, 16, v29
v_fmac_f16_e32 v2, v4, v6
v_fmac_f16_e32 v0, v16, v29
v_fmac_f16_e32 v7, v40, v29
v_fmac_f16_e32 v1, v5, v22
v_lshrrev_b32_e32 v15, 16, v17
v_fmac_f16_e32 v2, v50, v22
s_waitcnt lgkmcnt(0)
s_barrier
ds_read_b128 v[3:6], v37 offset:640
ds_read2_b64 v[23:26], v37 offset0:83 offset1:84
v_fmac_f16_e32 v1, v14, v32
v_lshrrev_b32_e32 v14, 16, v16
v_fmac_f16_e32 v2, v33, v32
v_lshrrev_b32_e32 v16, 16, v18
ds_read2_b64 v[19:22], v38 offset1:1
ds_read2_b64 v[47:50], v38 offset0:3 offset1:4
v_fmac_f16_e32 v1, v8, v43
v_lshrrev_b32_e32 v8, 16, v51
v_fmac_f16_e32 v2, v51, v43
v_fmac_f16_e32 v0, v14, v13
v_lshrrev_b32_e32 v14, 16, v44
v_fmac_f16_e32 v1, v27, v12
v_lshrrev_b32_e32 v51, 16, v31
v_fmac_f16_e32 v2, v8, v12
v_lshrrev_b32_e32 v8, 16, v40
v_lshrrev_b32_e32 v12, 16, v9
v_fmac_f16_e32 v1, v9, v44
v_fmac_f16_e32 v0, v17, v30
v_fmac_f16_e32 v2, v52, v44
v_fmac_f16_e32 v7, v8, v13
v_lshrrev_b32_e32 v8, 16, v52
v_fmac_f16_e32 v1, v12, v14
v_lshrrev_b32_e32 v9, 16, v30
v_lshrrev_b32_e32 v12, 16, v10
v_fmac_f16_e32 v7, v41, v30
v_fmac_f16_e32 v2, v8, v14
v_lshrrev_b32_e32 v8, 16, v41
v_fmac_f16_e32 v0, v15, v9
v_lshrrev_b32_e32 v17, 16, v45
v_fmac_f16_e32 v1, v10, v45
v_fmac_f16_e32 v2, v53, v45
v_fmac_f16_e32 v7, v8, v9
v_lshrrev_b32_e32 v8, 16, v53
v_fmac_f16_e32 v0, v18, v31
v_fmac_f16_e32 v1, v12, v17
v_lshrrev_b32_e32 v52, 16, v42
v_fmac_f16_e32 v7, v42, v31
v_fmac_f16_e32 v2, v8, v17
v_fmac_f16_e32 v0, v16, v51
v_lshrrev_b32_e32 v18, 16, v11
v_fmac_f16_e32 v1, v11, v46
v_lshrrev_b32_e32 v17, 16, v46
v_fmac_f16_e32 v2, v54, v46
v_lshrrev_b32_e32 v53, 16, v54
v_fmac_f16_e32 v7, v52, v51
v_lshrrev_b32_e32 v16, 16, v55
v_fmac_f16_e32 v1, v18, v17
v_lshrrev_b32_e32 v51, 16, v59
v_fmac_f16_e32 v2, v53, v17
v_fmac_f16_e32 v0, v59, v55
v_lshrrev_b32_e32 v18, 16, v61
v_fmac_f16_e32 v7, v61, v55
ds_read2_b64 v[12:15], v37 offset0:85 offset1:86
ds_read_b128 v[27:30], v37 offset:704
v_lshrrev_b32_e32 v17, 16, v57
v_fmac_f16_e32 v0, v51, v16
v_lshrrev_b32_e32 v52, 16, v63
v_fmac_f16_e32 v1, v63, v57
v_lshrrev_b32_e32 v51, 16, v65
v_fmac_f16_e32 v2, v65, v57
v_fmac_f16_e32 v7, v18, v16
v_lshrrev_b32_e32 v16, 16, v56
v_fmac_f16_e32 v1, v52, v17
v_lshrrev_b32_e32 v63, 16, v60
v_fmac_f16_e32 v2, v51, v17
v_fmac_f16_e32 v0, v60, v56
v_lshrrev_b32_e32 v17, 16, v62
v_fmac_f16_e32 v7, v62, v56
ds_read2_b64 v[8:11], v38 offset0:40 offset1:41
ds_read2_b64 v[31:34], v38 offset0:43 offset1:44
ds_read_b128 v[39:42], v37 offset:1440
ds_read_b128 v[43:46], v37 offset:1504
v_lshrrev_b32_e32 v18, 16, v58
v_fmac_f16_e32 v1, v64, v58
v_fmac_f16_e32 v2, v66, v58
ds_read2_b64 v[51:54], v37 offset0:185 offset1:186
ds_read2_b64 v[55:58], v37 offset0:183 offset1:184
ds_read2_b64 v[59:62], v37 offset0:82 offset1:87
ds_read2_b64 v[67:70], v38 offset0:2 offset1:42
ds_read2_b64 v[71:74], v37 offset0:182 offset1:187
v_fmac_f16_e32 v7, v17, v16
v_fmac_f16_e32 v0, v63, v16
v_lshrrev_b32_e32 v78, 16, v64
v_lshrrev_b32_e32 v79, 16, v66
s_waitcnt lgkmcnt(12)
v_lshrrev_b32_e32 v75, 16, v19
s_waitcnt lgkmcnt(10)
v_lshrrev_b32_e32 v16, 16, v12
v_fmac_f16_e32 v7, v12, v19
v_fmac_f16_e32 v0, v3, v19
v_lshrrev_b32_e32 v3, 16, v3
v_fmac_f16_e32 v2, v79, v18
v_fmac_f16_e32 v1, v78, v18
v_fmac_f16_e32 v7, v16, v75
v_lshrrev_b32_e32 v76, 16, v20
v_fmac_f16_e32 v0, v3, v75
v_lshrrev_b32_e32 v3, 16, v4
s_waitcnt lgkmcnt(8)
v_lshrrev_b32_e32 v17, 16, v8
s_waitcnt lgkmcnt(6)
v_fmac_f16_e32 v1, v39, v8
s_waitcnt lgkmcnt(4)
v_fmac_f16_e32 v2, v51, v8
v_fmac_f16_e32 v0, v4, v20
v_fmac_f16_e32 v7, v13, v20
v_lshrrev_b32_e32 v8, 16, v13
v_lshrrev_b32_e32 v12, 16, v39
v_lshrrev_b32_e32 v16, 16, v51
v_fmac_f16_e32 v0, v3, v76
v_lshrrev_b32_e32 v3, 16, v5
v_fmac_f16_e32 v7, v8, v76
v_fmac_f16_e32 v1, v12, v17
v_fmac_f16_e32 v2, v16, v17
v_lshrrev_b32_e32 v77, 16, v21
v_fmac_f16_e32 v0, v5, v21
v_fmac_f16_e32 v7, v14, v21
v_lshrrev_b32_e32 v12, 16, v14
v_lshrrev_b32_e32 v13, 16, v40
v_lshrrev_b32_e32 v16, 16, v9
v_fmac_f16_e32 v0, v3, v77
v_fmac_f16_e32 v1, v40, v9
v_fmac_f16_e32 v7, v12, v77
v_fmac_f16_e32 v2, v52, v9
v_lshrrev_b32_e32 v8, 16, v52
v_lshrrev_b32_e32 v80, 16, v6
v_fmac_f16_e32 v1, v13, v16
v_fmac_f16_e32 v0, v6, v22
v_lshrrev_b32_e32 v9, 16, v22
v_fmac_f16_e32 v2, v8, v16
v_fmac_f16_e32 v7, v15, v22
v_lshrrev_b32_e32 v21, 16, v15
v_lshrrev_b32_e32 v20, 16, v41
v_fmac_f16_e32 v0, v80, v9
v_lshrrev_b32_e32 v8, 16, v10
v_fmac_f16_e32 v1, v41, v10
v_fmac_f16_e32 v7, v21, v9
v_lshrrev_b32_e32 v39, 16, v53
v_fmac_f16_e32 v2, v53, v10
s_waitcnt lgkmcnt(2)
v_lshrrev_b32_e32 v51, 16, v59
v_fmac_f16_e32 v1, v20, v8
s_waitcnt lgkmcnt(1)
v_fmac_f16_e32 v0, v59, v67
v_lshrrev_b32_e32 v52, 16, v67
v_fmac_f16_e32 v2, v39, v8
v_fmac_f16_e32 v7, v61, v67
v_lshrrev_b32_e32 v21, 16, v61
v_lshrrev_b32_e32 v22, 16, v42
v_fmac_f16_e32 v0, v51, v52
v_lshrrev_b32_e32 v20, 16, v11
v_fmac_f16_e32 v1, v42, v11
v_fmac_f16_e32 v7, v21, v52
v_fmac_f16_e32 v2, v54, v11
v_lshrrev_b32_e32 v59, 16, v54
v_fmac_f16_e32 v0, v60, v68
v_fmac_f16_e32 v1, v22, v20
v_lshrrev_b32_e32 v22, 16, v60
v_lshrrev_b32_e32 v61, 16, v68
v_fmac_f16_e32 v2, v59, v20
v_fmac_f16_e32 v7, v62, v68
v_lshrrev_b32_e32 v59, 16, v62
v_lshrrev_b32_e32 v21, 16, v69
v_fmac_f16_e32 v0, v22, v61
s_waitcnt lgkmcnt(0)
v_lshrrev_b32_e32 v20, 16, v71
v_fmac_f16_e32 v1, v71, v69
v_fmac_f16_e32 v7, v59, v61
v_fmac_f16_e32 v2, v73, v69
v_lshrrev_b32_e32 v60, 16, v73
v_lshrrev_b32_e32 v71, 16, v23
v_fmac_f16_e32 v1, v20, v21
v_lshrrev_b32_e32 v73, 16, v47
v_fmac_f16_e32 v0, v23, v47
v_fmac_f16_e32 v7, v27, v47
v_lshrrev_b32_e32 v79, 16, v27
v_fmac_f16_e32 v2, v60, v21
v_lshrrev_b32_e32 v67, 16, v70
v_fmac_f16_e32 v0, v71, v73
v_lshrrev_b32_e32 v68, 16, v72
v_fmac_f16_e32 v1, v72, v70
v_fmac_f16_e32 v7, v79, v73
v_fmac_f16_e32 v2, v74, v70
v_lshrrev_b32_e32 v69, 16, v74
v_lshrrev_b32_e32 v27, 16, v24
v_fmac_f16_e32 v1, v68, v67
v_fmac_f16_e32 v0, v24, v48
v_lshrrev_b32_e32 v47, 16, v48
v_lshrrev_b32_e32 v68, 16, v28
v_fmac_f16_e32 v7, v28, v48
v_fmac_f16_e32 v2, v69, v67
v_lshrrev_b32_e32 v24, 16, v55
v_fmac_f16_e32 v0, v27, v47
v_fmac_f16_e32 v1, v55, v31
v_fmac_f16_e32 v7, v68, v47
v_lshrrev_b32_e32 v28, 16, v31
v_lshrrev_b32_e32 v70, 16, v25
v_lshrrev_b32_e32 v71, 16, v49
v_fmac_f16_e32 v0, v25, v49
v_lshrrev_b32_e32 v27, 16, v29
v_fmac_f16_e32 v7, v29, v49
v_fmac_f16_e32 v1, v24, v28
v_lshrrev_b32_e32 v29, 16, v43
v_fmac_f16_e32 v2, v43, v31
s_barrier
ds_write_b16 v95, v81 offset:640
ds_write_b16 v95, v82 offset:800
ds_write_b16 v95, v83 offset:960
ds_write_b16 v95, v84 offset:1120
ds_write_b16 v95, v85 offset:1280
ds_write_b16 v95, v86 offset:1440
ds_write_b16 v95, v87 offset:1600
ds_write_b16 v95, v88 offset:1760
ds_write_b16 v95, v89 offset:1920
ds_write_b16 v95, v90 offset:2080
ds_write_b16 v95, v91
ds_write_b16 v95, v92 offset:160
ds_write_b16 v95, v93 offset:320
ds_write_b16 v95, v94 offset:480
s_waitcnt lgkmcnt(0)
s_barrier
ds_read_b128 v[3:6], v37 offset:640
ds_read_b128 v[63:66], v37 offset:656
ds_read2_b64 v[12:15], v38 offset1:1
ds_read2_b64 v[16:19], v38 offset0:2 offset1:3
v_fmac_f16_e32 v0, v70, v71
v_fmac_f16_e32 v2, v29, v28
v_lshrrev_b32_e32 v55, 16, v56
v_fmac_f16_e32 v1, v56, v32
v_lshrrev_b32_e32 v68, 16, v32
ds_read2_b64 v[8:11], v37 offset0:85 offset1:86
ds_read2_b64 v[39:42], v37 offset0:87 offset1:88
v_fmac_f16_e32 v7, v27, v71
v_fmac_f16_e32 v2, v44, v32
v_lshrrev_b32_e32 v67, 16, v26
v_fmac_f16_e32 v1, v55, v68
v_lshrrev_b32_e32 v55, 16, v44
v_lshrrev_b32_e32 v72, 16, v50
v_fmac_f16_e32 v0, v26, v50
v_fmac_f16_e32 v7, v30, v50
v_lshrrev_b32_e32 v43, 16, v30
v_fmac_f16_e32 v2, v55, v68
v_lshrrev_b32_e32 v56, 16, v57
v_fmac_f16_e32 v0, v67, v72
v_lshrrev_b32_e32 v32, 16, v33
v_fmac_f16_e32 v7, v43, v72
v_fmac_f16_e32 v1, v57, v33
v_fmac_f16_e32 v2, v45, v33
v_lshrrev_b32_e32 v44, 16, v45
s_waitcnt lgkmcnt(5)
v_lshrrev_b32_e32 v67, 16, v3
s_waitcnt lgkmcnt(3)
v_fmac_f16_e32 v0, v3, v12
v_lshrrev_b32_e32 v71, 16, v12
ds_read_b128 v[51:54], v37 offset:1440
ds_read_b128 v[75:78], v37 offset:1456
ds_read2_b64 v[20:23], v38 offset0:40 offset1:41
ds_read2_b64 v[59:62], v38 offset0:42 offset1:43
ds_read2_b64 v[24:27], v37 offset0:185 offset1:186
ds_read2_b64 v[47:50], v37 offset0:187 offset1:188
v_fmac_f16_e32 v2, v44, v32
v_fmac_f16_e32 v1, v56, v32
v_fmac_f16_e32 v0, v67, v71
s_waitcnt lgkmcnt(7)
v_fmac_f16_e32 v7, v8, v12
v_lshrrev_b32_e32 v43, 16, v8
v_lshrrev_b32_e32 v3, 16, v58
v_fmac_f16_e32 v1, v58, v34
v_lshrrev_b32_e32 v32, 16, v34
v_fmac_f16_e32 v2, v46, v34
v_fmac_f16_e32 v7, v43, v71
v_lshrrev_b32_e32 v33, 16, v4
v_fmac_f16_e32 v0, v4, v13
v_lshrrev_b32_e32 v4, 16, v46
v_lshrrev_b32_e32 v44, 16, v13
v_fmac_f16_e32 v1, v3, v32
v_fmac_f16_e32 v7, v9, v13
v_lshrrev_b32_e32 v8, 16, v9
v_fmac_f16_e32 v2, v4, v32
v_fmac_f16_e32 v0, v33, v44
v_lshrrev_b32_e32 v33, 16, v5
v_lshrrev_b32_e32 v34, 16, v14
v_fmac_f16_e32 v7, v8, v44
s_waitcnt lgkmcnt(5)
v_lshrrev_b32_e32 v43, 16, v51
v_fmac_f16_e32 v0, v5, v14
s_waitcnt lgkmcnt(3)
v_fmac_f16_e32 v1, v51, v20
v_lshrrev_b32_e32 v45, 16, v20
s_waitcnt lgkmcnt(1)
v_fmac_f16_e32 v2, v24, v20
v_lshrrev_b32_e32 v44, 16, v24
v_fmac_f16_e32 v0, v33, v34
v_lshrrev_b32_e32 v5, 16, v6
v_fmac_f16_e32 v1, v43, v45
v_lshrrev_b32_e32 v9, 16, v21
v_fmac_f16_e32 v2, v44, v45
v_fmac_f16_e32 v0, v6, v15
v_lshrrev_b32_e32 v6, 16, v52
v_fmac_f16_e32 v1, v52, v21
v_lshrrev_b32_e32 v3, 16, v25
v_fmac_f16_e32 v2, v25, v21
v_fmac_f16_e32 v7, v10, v14
v_lshrrev_b32_e32 v12, 16, v10
v_fmac_f16_e32 v1, v6, v9
v_lshrrev_b32_e32 v13, 16, v53
v_fmac_f16_e32 v2, v3, v9
v_lshrrev_b32_e32 v46, 16, v22
v_fmac_f16_e32 v7, v12, v34
v_fmac_f16_e32 v1, v53, v22
v_lshrrev_b32_e32 v4, 16, v26
v_fmac_f16_e32 v2, v26, v22
v_lshrrev_b32_e32 v33, 16, v15
v_fmac_f16_e32 v7, v11, v15
v_fmac_f16_e32 v1, v13, v46
v_lshrrev_b32_e32 v12, 16, v11
v_fmac_f16_e32 v2, v4, v46
v_fmac_f16_e32 v0, v5, v33
v_lshrrev_b32_e32 v8, 16, v54
v_lshrrev_b32_e32 v10, 16, v23
v_fmac_f16_e32 v1, v54, v23
v_fmac_f16_e32 v7, v12, v33
v_fmac_f16_e32 v2, v27, v23
v_lshrrev_b32_e32 v14, 16, v27
v_lshrrev_b32_e32 v20, 16, v63
v_fmac_f16_e32 v1, v8, v10
v_lshrrev_b32_e32 v24, 16, v16
v_fmac_f16_e32 v0, v63, v16
v_fmac_f16_e32 v2, v14, v10
v_lshrrev_b32_e32 v25, 16, v39
v_fmac_f16_e32 v7, v39, v16
v_lshrrev_b32_e32 v6, 16, v75
v_fmac_f16_e32 v0, v20, v24
v_lshrrev_b32_e32 v3, 16, v59
v_fmac_f16_e32 v1, v75, v59
v_fmac_f16_e32 v7, v25, v24
s_waitcnt lgkmcnt(0)
v_lshrrev_b32_e32 v9, 16, v47
v_fmac_f16_e32 v2, v47, v59
v_lshrrev_b32_e32 v32, 16, v64
v_fmac_f16_e32 v1, v6, v3
v_lshrrev_b32_e32 v11, 16, v17
v_fmac_f16_e32 v0, v64, v17
v_fmac_f16_e32 v2, v9, v3
v_lshrrev_b32_e32 v43, 16, v40
v_fmac_f16_e32 v7, v40, v17
v_lshrrev_b32_e32 v22, 16, v76
v_fmac_f16_e32 v0, v32, v11
v_lshrrev_b32_e32 v26, 16, v60
v_fmac_f16_e32 v1, v76, v60
v_fmac_f16_e32 v7, v43, v11
v_lshrrev_b32_e32 v13, 16, v48
v_fmac_f16_e32 v2, v48, v60
ds_read2_b64 v[28:31], v38 offset0:4 offset1:44
v_fmac_f16_e32 v1, v22, v26
ds_read2_b64 v[55:58], v37 offset0:84 offset1:89
v_lshrrev_b32_e32 v15, 16, v65
v_fmac_f16_e32 v2, v13, v26
v_lshrrev_b32_e32 v34, 16, v18
v_fmac_f16_e32 v0, v65, v18
v_fmac_f16_e32 v7, v41, v18
v_lshrrev_b32_e32 v4, 16, v41
ds_read2_b64 v[67:70], v37 offset0:184 offset1:189
v_lshrrev_b32_e32 v44, 16, v77
v_fmac_f16_e32 v0, v15, v34
v_lshrrev_b32_e32 v45, 16, v61
v_fmac_f16_e32 v1, v77, v61
v_fmac_f16_e32 v7, v4, v34
v_lshrrev_b32_e32 v46, 16, v49
v_fmac_f16_e32 v2, v49, v61
v_lshrrev_b32_e32 v21, 16, v66
v_fmac_f16_e32 v1, v44, v45
v_lshrrev_b32_e32 v52, 16, v19
v_fmac_f16_e32 v0, v66, v19
v_fmac_f16_e32 v2, v46, v45
v_fmac_f16_e32 v7, v42, v19
v_lshrrev_b32_e32 v23, 16, v42
v_lshrrev_b32_e32 v51, 16, v78
v_fmac_f16_e32 v0, v21, v52
v_lshrrev_b32_e32 v27, 16, v62
v_fmac_f16_e32 v1, v78, v62
v_fmac_f16_e32 v7, v23, v52
v_lshrrev_b32_e32 v53, 16, v50
v_fmac_f16_e32 v2, v50, v62
s_waitcnt lgkmcnt(0)
s_barrier
v_fmac_f16_e32 v1, v51, v27
ds_write_b16 v95, v101 offset:640
ds_write_b16 v95, v121 offset:800
ds_write_b16 v95, v102 offset:960
ds_write_b16 v95, v119 offset:1120
ds_write_b16 v95, v112 offset:1280
ds_write_b16 v95, v104 offset:1440
ds_write_b16 v95, v120 offset:1600
ds_write_b16 v95, v106 offset:1760
ds_write_b16 v95, v108 offset:1920
ds_write_b16 v95, v122 offset:2080
ds_write_b16 v95, v96
ds_write_b16 v95, v118 offset:160
ds_write_b16 v95, v98 offset:320
ds_write_b16 v95, v116 offset:480
s_waitcnt lgkmcnt(0)
s_barrier
v_fmac_f16_e32 v2, v53, v27
v_lshrrev_b32_e32 v12, 16, v28
v_lshrrev_b32_e32 v20, 16, v55
v_fmac_f16_e32 v0, v55, v28
v_lshrrev_b32_e32 v13, 16, v57
v_fmac_f16_e32 v7, v57, v28
ds_read2_b64 v[3:6], v37 offset0:80 offset1:85
ds_read2_b64 v[8:11], v38 offset1:40
v_fmac_f16_e32 v0, v20, v12
v_lshrrev_b32_e32 v14, 16, v30
v_fmac_f16_e32 v7, v13, v12
v_lshrrev_b32_e32 v15, 16, v67
v_fmac_f16_e32 v1, v67, v30
v_fmac_f16_e32 v2, v69, v30
v_lshrrev_b32_e32 v22, 16, v69
v_lshrrev_b32_e32 v16, 16, v29
v_lshrrev_b32_e32 v18, 16, v56
v_fmac_f16_e32 v1, v15, v14
v_fmac_f16_e32 v0, v56, v29
v_fmac_f16_e32 v2, v22, v14
ds_read2_b64 v[12:15], v37 offset0:180 offset1:185
v_fmac_f16_e32 v7, v58, v29
v_lshrrev_b32_e32 v19, 16, v58
v_fmac_f16_e32 v0, v18, v16
v_lshrrev_b32_e32 v17, 16, v31
v_lshrrev_b32_e32 v21, 16, v68
v_fmac_f16_e32 v1, v68, v31
v_fmac_f16_e32 v7, v19, v16
v_fmac_f16_e32 v2, v70, v31
v_lshrrev_b32_e32 v20, 16, v70
s_waitcnt lgkmcnt(2)
v_lshrrev_b32_e32 v28, 16, v3
s_waitcnt lgkmcnt(1)
v_fmac_f16_e32 v0, v3, v8
v_lshrrev_b32_e32 v30, 16, v8
v_fmac_f16_e32 v7, v5, v8
v_lshrrev_b32_e32 v3, 16, v5
v_fmac_f16_e32 v1, v21, v17
v_fmac_f16_e32 v2, v20, v17
v_fmac_f16_e32 v0, v28, v30
ds_read_b128 v[16:19], v37 offset:688
v_fmac_f16_e32 v7, v3, v30
v_lshrrev_b32_e32 v29, 16, v4
v_lshrrev_b32_e32 v31, 16, v9
v_fmac_f16_e32 v0, v4, v9
ds_read2_b64 v[20:23], v37 offset0:81 offset1:82
ds_read2_b64 v[24:27], v38 offset0:1 offset1:2
v_fmac_f16_e32 v7, v6, v9
v_lshrrev_b32_e32 v8, 16, v6
v_lshrrev_b32_e32 v5, 16, v10
s_waitcnt lgkmcnt(3)
v_lshrrev_b32_e32 v32, 16, v12
v_fmac_f16_e32 v1, v12, v10
v_fmac_f16_e32 v2, v14, v10
v_lshrrev_b32_e32 v3, 16, v14
v_fmac_f16_e32 v7, v8, v31
v_fmac_f16_e32 v0, v29, v31
v_fmac_f16_e32 v1, v32, v5
ds_read2_b64 v[28:31], v38 offset0:3 offset1:4
v_fmac_f16_e32 v2, v3, v5
ds_read2_b64 v[3:6], v37 offset0:83 offset1:84
ds_read_b128 v[39:42], v37 offset:704
ds_read2_b64 v[43:46], v37 offset0:181 offset1:182
ds_read2_b64 v[47:50], v38 offset0:41 offset1:42
ds_read_b128 v[51:54], v37 offset:1488
v_lshrrev_b32_e32 v12, 16, v11
v_lshrrev_b32_e32 v14, 16, v13
v_fmac_f16_e32 v1, v13, v11
s_waitcnt lgkmcnt(7)
v_lshrrev_b32_e32 v8, 16, v20
s_waitcnt lgkmcnt(6)
v_fmac_f16_e32 v0, v20, v24
v_lshrrev_b32_e32 v9, 16, v24
v_fmac_f16_e32 v7, v16, v24
v_lshrrev_b32_e32 v10, 16, v16
v_fmac_f16_e32 v1, v14, v12
v_lshrrev_b32_e32 v16, 16, v15
v_fmac_f16_e32 v2, v15, v11
v_fmac_f16_e32 v0, v8, v9
v_fmac_f16_e32 v7, v10, v9
v_lshrrev_b32_e32 v8, 16, v21
v_lshrrev_b32_e32 v20, 16, v25
v_fmac_f16_e32 v2, v16, v12
v_fmac_f16_e32 v0, v21, v25
s_waitcnt lgkmcnt(2)
v_lshrrev_b32_e32 v24, 16, v43
s_waitcnt lgkmcnt(1)
v_fmac_f16_e32 v1, v43, v47
v_lshrrev_b32_e32 v16, 16, v47
v_fmac_f16_e32 v7, v17, v25
v_lshrrev_b32_e32 v21, 16, v17
s_waitcnt lgkmcnt(0)
v_fmac_f16_e32 v2, v51, v47
v_lshrrev_b32_e32 v25, 16, v51
v_fmac_f16_e32 v1, v24, v16
v_fmac_f16_e32 v0, v8, v20
v_fmac_f16_e32 v7, v21, v20
v_lshrrev_b32_e32 v20, 16, v44
v_fmac_f16_e32 v2, v25, v16
v_lshrrev_b32_e32 v21, 16, v48
v_fmac_f16_e32 v1, v44, v48
v_lshrrev_b32_e32 v17, 16, v22
v_fmac_f16_e32 v0, v22, v26
v_lshrrev_b32_e32 v32, 16, v26
v_lshrrev_b32_e32 v16, 16, v18
v_fmac_f16_e32 v7, v18, v26
v_fmac_f16_e32 v1, v20, v21
v_fmac_f16_e32 v2, v52, v48
v_lshrrev_b32_e32 v22, 16, v52
v_fmac_f16_e32 v0, v17, v32
v_fmac_f16_e32 v7, v16, v32
ds_read2_b64 v[8:11], v37 offset0:183 offset1:184
ds_read2_b64 v[12:15], v38 offset0:43 offset1:44
v_fmac_f16_e32 v2, v22, v21
v_lshrrev_b32_e32 v16, 16, v45
v_lshrrev_b32_e32 v18, 16, v49
v_fmac_f16_e32 v1, v45, v49
ds_read_b128 v[55:58], v37 offset:1504
v_lshrrev_b32_e32 v17, 16, v23
v_fmac_f16_e32 v2, v53, v49
v_lshrrev_b32_e32 v20, 16, v53
v_fmac_f16_e32 v1, v16, v18
v_lshrrev_b32_e32 v21, 16, v27
v_fmac_f16_e32 v0, v23, v27
v_fmac_f16_e32 v7, v19, v27
v_fmac_f16_e32 v2, v20, v18
v_lshrrev_b32_e32 v16, 16, v19
v_lshrrev_b32_e32 v18, 16, v46
v_fmac_f16_e32 v0, v17, v21
v_fmac_f16_e32 v1, v46, v50
v_lshrrev_b32_e32 v19, 16, v50
v_fmac_f16_e32 v7, v16, v21
v_fmac_f16_e32 v2, v54, v50
v_lshrrev_b32_e32 v20, 16, v54
v_lshrrev_b32_e32 v16, 16, v3
v_fmac_f16_e32 v1, v18, v19
v_fmac_f16_e32 v0, v3, v28
v_lshrrev_b32_e32 v18, 16, v28
v_fmac_f16_e32 v2, v20, v19
s_waitcnt lgkmcnt(2)
v_lshrrev_b32_e32 v3, 16, v8
s_waitcnt lgkmcnt(1)
v_fmac_f16_e32 v1, v8, v12
v_fmac_f16_e32 v7, v39, v28
v_fmac_f16_e32 v0, v16, v18
v_lshrrev_b32_e32 v16, 16, v12
v_lshrrev_b32_e32 v21, 16, v39
s_waitcnt lgkmcnt(0)
v_fmac_f16_e32 v2, v55, v12
v_lshrrev_b32_e32 v8, 16, v55
v_lshrrev_b32_e32 v17, 16, v4
v_fmac_f16_e32 v1, v3, v16
v_fmac_f16_e32 v7, v21, v18
v_fmac_f16_e32 v0, v4, v29
v_fmac_f16_e32 v2, v8, v16
v_lshrrev_b32_e32 v19, 16, v29
v_lshrrev_b32_e32 v20, 16, v9
v_fmac_f16_e32 v1, v9, v13
v_lshrrev_b32_e32 v12, 16, v13
v_fmac_f16_e32 v2, v56, v13
v_fmac_f16_e32 v0, v17, v19
v_lshrrev_b32_e32 v8, 16, v56
v_lshrrev_b32_e32 v4, 16, v40
v_fmac_f16_e32 v7, v40, v29
v_fmac_f16_e32 v1, v20, v12
v_lshrrev_b32_e32 v24, 16, v5
v_fmac_f16_e32 v2, v8, v12
v_lshrrev_b32_e32 v33, 16, v30
v_fmac_f16_e32 v7, v4, v19
v_fmac_f16_e32 v0, v5, v30
v_lshrrev_b32_e32 v25, 16, v10
v_lshrrev_b32_e32 v3, 16, v14
v_fmac_f16_e32 v1, v10, v14
s_barrier
v_fmac_f16_e32 v0, v24, v33
ds_write_b16 v95, v103 offset:640
ds_write_b16 v95, v111 offset:800
ds_write_b16 v95, v110 offset:960
ds_write_b16 v95, v113 offset:1120
ds_write_b16 v95, v114 offset:1280
ds_write_b16 v95, v105 offset:1440
ds_write_b16 v95, v115 offset:1600
ds_write_b16 v95, v107 offset:1760
ds_write_b16 v95, v109 offset:1920
ds_write_b16 v95, v123 offset:2080
ds_write_b16 v95, v97
ds_write_b16 v95, v100 offset:160
ds_write_b16 v95, v99 offset:320
ds_write_b16 v95, v117 offset:480
s_waitcnt lgkmcnt(0)
s_barrier
v_fmac_f16_e32 v1, v25, v3
v_lshrrev_b32_e32 v4, 16, v41
v_fmac_f16_e32 v7, v41, v30
v_lshrrev_b32_e32 v9, 16, v57
v_fmac_f16_e32 v2, v57, v14
ds_read_b128 v[16:19], v37 offset:640
ds_read2_b64 v[20:23], v38 offset1:1
ds_read2_b64 v[43:46], v37 offset0:85 offset1:86
v_fmac_f16_e32 v7, v4, v33
v_fmac_f16_e32 v2, v9, v3
v_lshrrev_b32_e32 v32, 16, v6
v_fmac_f16_e32 v0, v6, v31
v_lshrrev_b32_e32 v28, 16, v11
v_fmac_f16_e32 v1, v11, v15
ds_read_b128 v[24:27], v37 offset:1440
ds_read2_b64 v[3:6], v38 offset0:40 offset1:41
ds_read2_b64 v[8:11], v37 offset0:185 offset1:186
v_lshrrev_b32_e32 v34, 16, v31
v_lshrrev_b32_e32 v13, 16, v42
v_fmac_f16_e32 v7, v42, v31
v_lshrrev_b32_e32 v39, 16, v15
v_lshrrev_b32_e32 v12, 16, v58
v_fmac_f16_e32 v2, v58, v15
v_fmac_f16_e32 v0, v32, v34
v_fmac_f16_e32 v7, v13, v34
v_fmac_f16_e32 v1, v28, v39
s_waitcnt lgkmcnt(5)
v_lshrrev_b32_e32 v32, 16, v16
v_fmac_f16_e32 v2, v12, v39
s_waitcnt lgkmcnt(4)
v_fmac_f16_e32 v0, v16, v20
v_lshrrev_b32_e32 v33, 16, v20
s_waitcnt lgkmcnt(3)
v_fmac_f16_e32 v7, v43, v20
v_lshrrev_b32_e32 v34, 16, v43
ds_read_b128 v[12:15], v37 offset:656
ds_read2_b64 v[28:31], v38 offset0:2 offset1:3
v_fmac_f16_e32 v0, v32, v33
s_waitcnt lgkmcnt(4)
v_lshrrev_b32_e32 v16, 16, v24
v_fmac_f16_e32 v7, v34, v33
s_waitcnt lgkmcnt(3)
v_fmac_f16_e32 v1, v24, v3
v_lshrrev_b32_e32 v20, 16, v3
s_waitcnt lgkmcnt(2)
v_fmac_f16_e32 v2, v8, v3
v_lshrrev_b32_e32 v24, 16, v8
v_lshrrev_b32_e32 v3, 16, v17
v_fmac_f16_e32 v0, v17, v21
v_fmac_f16_e32 v1, v16, v20
v_lshrrev_b32_e32 v8, 16, v21
v_fmac_f16_e32 v2, v24, v20
v_lshrrev_b32_e32 v16, 16, v44
v_fmac_f16_e32 v7, v44, v21
v_lshrrev_b32_e32 v17, 16, v25
v_fmac_f16_e32 v0, v3, v8
v_lshrrev_b32_e32 v3, 16, v4
v_fmac_f16_e32 v1, v25, v4
v_fmac_f16_e32 v7, v16, v8
v_fmac_f16_e32 v2, v9, v4
v_lshrrev_b32_e32 v8, 16, v9
v_lshrrev_b32_e32 v4, 16, v18
v_fmac_f16_e32 v1, v17, v3
v_fmac_f16_e32 v0, v18, v22
v_lshrrev_b32_e32 v9, 16, v22
v_fmac_f16_e32 v2, v8, v3
ds_read_b128 v[39:42], v37 offset:1456
ds_read2_b64 v[51:54], v38 offset0:42 offset1:43
v_fmac_f16_e32 v7, v45, v22
v_fmac_f16_e32 v0, v4, v9
v_lshrrev_b32_e32 v3, 16, v45
ds_read2_b64 v[55:58], v37 offset0:187 offset1:188
v_lshrrev_b32_e32 v8, 16, v26
v_fmac_f16_e32 v1, v26, v5
v_lshrrev_b32_e32 v4, 16, v5
v_fmac_f16_e32 v2, v10, v5
v_lshrrev_b32_e32 v16, 16, v10
v_fmac_f16_e32 v7, v3, v9
ds_read2_b64 v[47:50], v37 offset0:87 offset1:88
v_fmac_f16_e32 v1, v8, v4
v_lshrrev_b32_e32 v3, 16, v19
v_fmac_f16_e32 v2, v16, v4
v_fmac_f16_e32 v0, v19, v23
v_lshrrev_b32_e32 v5, 16, v23
v_fmac_f16_e32 v7, v46, v23
v_lshrrev_b32_e32 v9, 16, v46
v_lshrrev_b32_e32 v4, 16, v27
v_fmac_f16_e32 v1, v27, v6
v_fmac_f16_e32 v0, v3, v5
v_lshrrev_b32_e32 v8, 16, v6
v_fmac_f16_e32 v2, v11, v6
v_lshrrev_b32_e32 v10, 16, v11
v_fmac_f16_e32 v7, v9, v5
s_waitcnt lgkmcnt(5)
v_lshrrev_b32_e32 v3, 16, v12
v_fmac_f16_e32 v1, v4, v8
s_waitcnt lgkmcnt(4)
v_fmac_f16_e32 v0, v12, v28
v_fmac_f16_e32 v2, v10, v8
v_lshrrev_b32_e32 v5, 16, v28
s_waitcnt lgkmcnt(3)
v_lshrrev_b32_e32 v8, 16, v39
s_waitcnt lgkmcnt(2)
v_lshrrev_b32_e32 v10, 16, v51
v_fmac_f16_e32 v1, v39, v51
s_waitcnt lgkmcnt(1)
v_lshrrev_b32_e32 v26, 16, v55
v_fmac_f16_e32 v0, v3, v5
v_fmac_f16_e32 v2, v55, v51
v_lshrrev_b32_e32 v4, 16, v13
v_fmac_f16_e32 v1, v8, v10
v_lshrrev_b32_e32 v6, 16, v29
v_fmac_f16_e32 v0, v13, v29
v_fmac_f16_e32 v2, v26, v10
s_waitcnt lgkmcnt(0)
v_lshrrev_b32_e32 v23, 16, v47
v_fmac_f16_e32 v7, v47, v28
v_lshrrev_b32_e32 v9, 16, v40
v_fmac_f16_e32 v0, v4, v6
v_lshrrev_b32_e32 v11, 16, v52
v_fmac_f16_e32 v1, v40, v52
v_fmac_f16_e32 v7, v23, v5
v_lshrrev_b32_e32 v3, 16, v56
v_fmac_f16_e32 v2, v56, v52
v_lshrrev_b32_e32 v16, 16, v14
v_fmac_f16_e32 v1, v9, v11
v_lshrrev_b32_e32 v18, 16, v30
v_fmac_f16_e32 v0, v14, v30
v_fmac_f16_e32 v2, v3, v11
v_lshrrev_b32_e32 v24, 16, v48
v_fmac_f16_e32 v7, v48, v29
v_lshrrev_b32_e32 v12, 16, v41
v_fmac_f16_e32 v0, v16, v18
v_lshrrev_b32_e32 v21, 16, v53
v_fmac_f16_e32 v1, v41, v53
v_fmac_f16_e32 v7, v24, v6
v_lshrrev_b32_e32 v13, 16, v57
v_fmac_f16_e32 v2, v57, v53
ds_read2_b64 v[8:11], v37 offset0:84 offset1:89
v_fmac_f16_e32 v1, v12, v21
v_lshrrev_b32_e32 v17, 16, v15
v_lshrrev_b32_e32 v25, 16, v49
v_fmac_f16_e32 v2, v13, v21
v_fmac_f16_e32 v7, v49, v30
v_fmac_f16_e32 v0, v15, v31
ds_read2_b64 v[12:15], v37 offset0:184 offset1:189
ds_read2_b64 v[3:6], v38 offset0:4 offset1:44
v_lshrrev_b32_e32 v20, 16, v42
v_fmac_f16_e32 v7, v25, v18
v_lshrrev_b32_e32 v22, 16, v54
v_fmac_f16_e32 v1, v42, v54
v_lshrrev_b32_e32 v16, 16, v58
v_fmac_f16_e32 v2, v58, v54
v_lshrrev_b32_e32 v19, 16, v31
v_lshrrev_b32_e32 v27, 16, v50
v_fmac_f16_e32 v1, v20, v22
v_fmac_f16_e32 v7, v50, v31
v_fmac_f16_e32 v2, v16, v22
v_or_b32_e32 v22, s5, v36
v_fmac_f16_e32 v0, v17, v19
s_waitcnt lgkmcnt(2)
v_lshrrev_b32_e32 v20, 16, v8
v_fmac_f16_e32 v7, v27, v19
v_lshrrev_b32_e32 v21, 16, v9
v_lshl_add_u32 v22, v35, 6, v22
v_lshrrev_b32_e32 v23, 16, v11
s_waitcnt lgkmcnt(1)
v_lshrrev_b32_e32 v24, 16, v15
s_waitcnt lgkmcnt(0)
v_fmac_f16_e32 v0, v8, v3
v_lshrrev_b32_e32 v16, 16, v3
v_fmac_f16_e32 v7, v10, v3
v_lshrrev_b32_e32 v18, 16, v5
v_lshrrev_b32_e32 v3, 16, v12
v_fmac_f16_e32 v1, v12, v5
v_fmac_f16_e32 v2, v14, v5
v_lshl_or_b32 v5, s3, 3, v22
v_lshrrev_b32_e32 v8, 16, v10
v_lshrrev_b32_e32 v12, 16, v14
v_fmac_f16_e32 v1, v3, v18
v_fmac_f16_e32 v0, v20, v16
v_add_nc_u32_e32 v3, s4, v5
v_fmac_f16_e32 v7, v8, v16
v_fmac_f16_e32 v2, v12, v18
v_lshrrev_b32_e32 v17, 16, v4
v_fmac_f16_e32 v0, v9, v4
v_add_nc_u32_e32 v5, s6, v3
v_fmac_f16_e32 v7, v11, v4
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v8, 0xca0, v3
v_lshrrev_b32_e32 v19, 16, v6
v_fmac_f16_e32 v2, v15, v6
v_fmac_f16_e32 v1, v13, v6
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_ashrrev_i32_e32 v9, 31, v8
v_lshrrev_b32_e32 v10, 16, v13
v_fmac_f16_e32 v0, v21, v17
v_lshlrev_b64 v[5:6], 1, v[5:6]
v_fmac_f16_e32 v7, v23, v17
v_add_co_u32 v3, vcc_lo, s0, v3
v_lshlrev_b64 v[8:9], 1, v[8:9]
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_fmac_f16_e32 v1, v10, v19
v_add_co_u32 v5, vcc_lo, s0, v5
v_fmac_f16_e32 v2, v24, v19
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v8, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
global_store_short v[3:4], v0, off
global_store_short v[3:4], v7, off offset:64
global_store_short v[5:6], v1, off
global_store_short v[8:9], v2, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_batch_matmul_2_kernel0
.amdhsa_group_segment_fixed_size 2240
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 124
.amdhsa_next_free_sgpr 17
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end23:
.size tvmgen_default_fused_nn_batch_matmul_2_kernel0, .Lfunc_end23-tvmgen_default_fused_nn_batch_matmul_2_kernel0
.globl tvmgen_default_fused_nn_batch_matmul_cast_add_1_kernel0
.p2align 8
.type tvmgen_default_fused_nn_batch_matmul_cast_add_1_kernel0,@function
tvmgen_default_fused_nn_batch_matmul_cast_add_1_kernel0:
v_lshrrev_b32_e32 v1, 3, v0
s_mov_b32 s12, 0xcccccccd
v_add_nc_u32_e32 v5, 0x60, v0
v_add_nc_u32_e32 v6, 0xc0, v0
v_add_nc_u32_e32 v7, 0x120, v0
v_add_nc_u32_e32 v2, 12, v1
v_add_nc_u32_e32 v4, 16, v1
v_mul_hi_u32 v5, v5, s12
v_mul_hi_u32 v6, v6, s12
v_add_nc_u32_e32 v9, 0x180, v0
v_mul_hi_u32 v3, v2, s12
v_mul_hi_u32 v8, v4, s12
v_add_nc_u32_e32 v10, 0x240, v0
v_mul_hi_u32 v7, v7, s12
v_lshlrev_b32_e32 v18, 5, v1
v_lshrrev_b32_e32 v5, 7, v5
s_movk_i32 s13, 0xc80
s_movk_i32 s14, 0x300
v_lshrrev_b32_e32 v3, 4, v3
v_lshrrev_b32_e32 v8, 4, v8
v_mul_i32_i24_e32 v19, s13, v5
v_lshrrev_b32_e32 v5, 7, v7
s_mul_hi_i32 s1, s6, 0x51eb851f
v_mul_u32_u24_e32 v3, 20, v3
v_mul_u32_u24_e32 v1, 20, v8
s_lshr_b32 s7, s1, 31
v_mul_i32_i24_e32 v24, s13, v5
s_ashr_i32 s1, s1, 3
v_sub_nc_u32_e32 v2, v2, v3
v_lshrrev_b32_e32 v3, 7, v6
v_mul_hi_u32 v6, v10, s12
v_sub_nc_u32_e32 v1, v4, v1
s_add_i32 s1, s1, s7
v_lshlrev_b32_e32 v20, 5, v2
v_mul_hi_u32 v2, v9, s12
v_mul_i32_i24_e32 v22, s13, v3
v_lshlrev_b32_e32 v23, 5, v1
v_add_nc_u32_e32 v3, s14, v0
v_lshrrev_b32_e32 v5, 7, v6
v_mul_hi_i32 v6, 0x2aaaaaab, v0
v_add_nc_u32_e32 v9, 0x480, v0
s_movk_i32 s7, 0x4800
v_lshrrev_b32_e32 v1, 7, v2
v_add_nc_u32_e32 v2, 0x2a0, v0
v_mul_hi_u32 v3, v3, s12
v_mul_i32_i24_e32 v30, s13, v5
v_add_nc_u32_e32 v5, 0x420, v0
v_mul_i32_i24_e32 v29, s13, v1
v_mul_hi_u32 v2, v2, s12
v_add_nc_u32_e32 v1, 0x360, v0
v_ashrrev_i32_e32 v7, 2, v6
v_lshrrev_b32_e32 v8, 31, v6
v_lshrrev_b32_e32 v3, 7, v3
s_mul_i32 s14, s6, s14
v_mul_hi_u32 v1, v1, s12
v_mul_hi_u32 v5, v5, s12
v_lshrrev_b32_e32 v2, 7, v2
v_add_nc_u32_e32 v7, v7, v8
v_mul_i32_i24_e32 v33, s13, v3
v_mul_hi_u32 v3, v9, s12
v_add_nc_u32_e32 v9, 0x4e0, v0
v_mul_i32_i24_e32 v31, s13, v2
v_mul_lo_u32 v2, v7, s7
v_lshrrev_b32_e32 v7, 7, v1
v_lshlrev_b32_e32 v1, 5, v0
v_ashrrev_i32_e32 v6, 1, v6
s_clause 0x3
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[4:5], s[4:5], 0x18
v_lshrrev_b32_e32 v5, 7, v5
v_lshlrev_b32_e32 v40, 4, v0
s_movk_i32 s0, 0xc00
v_add3_u32 v1, v2, s14, v1
v_lshrrev_b32_e32 v2, 7, v3
v_mul_hi_u32 v3, v9, s12
s_mul_i32 s12, s1, 0x4b00
v_add_nc_u32_e32 v28, v6, v8
v_subrev_nc_u32_e32 v1, s12, v1
v_mul_i32_i24_e32 v37, s13, v2
v_mul_i32_i24_e32 v36, s13, v5
v_lshl_add_u32 v15, v0, 1, s0
v_mul_lo_u32 v5, 0x140, v28
v_ashrrev_i32_e32 v2, 31, v1
v_lshrrev_b32_e32 v3, 7, v3
v_mul_i32_i24_e32 v35, s13, v7
v_lshlrev_b32_e32 v39, 5, v4
v_and_b32_e32 v13, 7, v0
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_mul_i32_i24_e32 v41, s13, v3
v_add_nc_u32_e32 v42, s0, v5
v_add_nc_u32_e32 v21, 0x80, v18
v_add_nc_u32_e32 v27, 0x100, v18
v_cmp_gt_i32_e32 vcc_lo, 32, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v44, s0, s10, v1
v_add_nc_u32_e32 v43, v40, v40
v_add_co_ci_u32_e64 v45, s0, s11, v2, s0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v32, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v34, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v38, 0
s_mul_i32 s12, s1, 25
s_mul_i32 s10, s1, 0x280
s_sub_i32 s6, s6, s12
s_mov_b32 s11, 0
s_branch BB24_2
BB24_1:
s_or_b32 exec_lo, exec_lo, s12
v_add_co_u32 v50, s0, 0x25800, v44
v_mov_b32_e32 v102, 0xffff
v_add_co_ci_u32_e64 v51, s0, 0, v45, s0
s_add_i32 s11, s11, 8
s_cmp_eq_u32 s11, 32
s_clause 0x1
global_load_dwordx4 v[46:49], v[44:45], off
global_load_dwordx4 v[50:53], v[50:51], off
v_add_co_u32 v44, s0, v44, 16
v_add_co_ci_u32_e64 v45, s0, 0, v45, s0
s_waitcnt vmcnt(1)
ds_write_b128 v40, v[46:49]
s_waitcnt vmcnt(0)
ds_write_b128 v40, v[50:53] offset:1536
s_waitcnt lgkmcnt(0)
s_barrier
ds_read_b128 v[46:49], v43 offset:16
ds_read_b128 v[50:53], v43
ds_read2_b64 v[54:57], v42 offset1:1
ds_read2_b64 v[58:61], v42 offset0:2 offset1:3
ds_read2_b64 v[62:65], v42 offset0:10 offset1:11
ds_read2_b64 v[66:69], v42 offset0:8 offset1:9
ds_read2_b64 v[70:73], v42 offset0:20 offset1:21
ds_read2_b64 v[74:77], v42 offset0:22 offset1:23
ds_read2_b64 v[78:81], v42 offset0:30 offset1:31
ds_read2_b64 v[82:85], v42 offset0:28 offset1:29
ds_read2_b64 v[86:89], v42 offset0:12 offset1:13
ds_read2_b64 v[90:93], v42 offset0:14 offset1:15
ds_read2_b64 v[94:97], v42 offset0:32 offset1:33
ds_read2_b64 v[98:101], v42 offset0:34 offset1:35
s_waitcnt lgkmcnt(13)
v_and_b32_e32 v103, v102, v46
s_waitcnt lgkmcnt(12)
v_lshrrev_b32_e32 v104, 16, v50
v_and_b32_sdwa v46, v102, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v105, v102, v47
v_lshrrev_b32_e32 v106, 16, v51
v_lshl_or_b32 v110, v50, 16, v103
v_and_b32_sdwa v47, v102, v47 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v111, v104, 16, v46
v_lshl_or_b32 v112, v51, 16, v105
v_and_b32_e32 v107, v102, v48
s_waitcnt lgkmcnt(11)
v_pk_fma_f16 v38, v54, v110, v38 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(9)
v_pk_fma_f16 v34, v62, v110, v34 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(7)
v_pk_fma_f16 v32, v70, v110, v32 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v26, v78, v110, v26 op_sel_hi:[0,1,1]
v_lshl_or_b32 v113, v106, 16, v47
v_pk_fma_f16 v38, v54, v111, v38 op_sel:[1,0,0]
v_pk_fma_f16 v34, v62, v111, v34 op_sel:[1,0,0]
v_pk_fma_f16 v32, v70, v111, v32 op_sel:[1,0,0]
v_pk_fma_f16 v26, v78, v111, v26 op_sel:[1,0,0]
v_lshrrev_b32_e32 v50, 16, v52
v_pk_fma_f16 v38, v55, v112, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v63, v112, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v71, v112, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v79, v112, v26 op_sel_hi:[0,1,1]
v_and_b32_sdwa v48, v102, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v114, v52, 16, v107
v_pk_fma_f16 v38, v55, v113, v38 op_sel:[1,0,0]
v_pk_fma_f16 v34, v63, v113, v34 op_sel:[1,0,0]
v_pk_fma_f16 v32, v71, v113, v32 op_sel:[1,0,0]
v_pk_fma_f16 v26, v79, v113, v26 op_sel:[1,0,0]
v_and_b32_e32 v103, v102, v49
v_lshl_or_b32 v115, v50, 16, v48
v_pk_fma_f16 v38, v56, v114, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v64, v114, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v72, v114, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v80, v114, v26 op_sel_hi:[0,1,1]
v_and_b32_sdwa v46, v102, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v49, 16, v53
v_lshl_or_b32 v116, v53, 16, v103
v_pk_fma_f16 v38, v56, v115, v38 op_sel:[1,0,0]
v_pk_fma_f16 v34, v64, v115, v34 op_sel:[1,0,0]
v_pk_fma_f16 v32, v72, v115, v32 op_sel:[1,0,0]
v_pk_fma_f16 v26, v80, v115, v26 op_sel:[1,0,0]
v_lshl_or_b32 v117, v49, 16, v46
v_pk_fma_f16 v38, v57, v116, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v65, v116, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v73, v116, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v81, v116, v26 op_sel_hi:[0,1,1]
ds_read2_b64 v[46:49], v42 offset0:4 offset1:5
ds_read2_b64 v[50:53], v42 offset0:6 offset1:7
v_pk_fma_f16 v38, v57, v117, v38 op_sel:[1,0,0]
v_pk_fma_f16 v34, v65, v117, v34 op_sel:[1,0,0]
ds_read2_b64 v[54:57], v42 offset0:24 offset1:25
ds_read2_b64 v[62:65], v42 offset0:16 offset1:17
v_pk_fma_f16 v32, v73, v117, v32 op_sel:[1,0,0]
ds_read2_b64 v[70:73], v42 offset0:26 offset1:27
v_pk_fma_f16 v26, v81, v117, v26 op_sel:[1,0,0]
ds_read2_b64 v[78:81], v42 offset0:18 offset1:19
ds_read2_b64 v[102:105], v42 offset0:36 offset1:37
ds_read2_b64 v[106:109], v42 offset0:38 offset1:39
v_pk_fma_f16 v25, v58, v110, v25 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(11)
v_pk_fma_f16 v17, v86, v110, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v74, v110, v16 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(9)
v_pk_fma_f16 v14, v94, v110, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v90, v110, v11 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(8)
v_pk_fma_f16 v9, v98, v110, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v66, v110, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v82, v110, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v58, v111, v25 op_sel:[1,0,0]
v_pk_fma_f16 v17, v86, v111, v17 op_sel:[1,0,0]
s_waitcnt lgkmcnt(7)
v_pk_fma_f16 v12, v46, v110, v12 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(6)
v_pk_fma_f16 v8, v50, v110, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v74, v111, v16 op_sel:[1,0,0]
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v10, v54, v110, v10 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v7, v62, v110, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v94, v111, v14 op_sel:[1,0,0]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v6, v70, v110, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v46, v111, v12 op_sel:[1,0,0]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v5, v102, v110, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v78, v110, v3 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v1, v106, v110, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v90, v111, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v54, v111, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v98, v111, v9 op_sel:[1,0,0]
v_pk_fma_f16 v8, v50, v111, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v62, v111, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v70, v111, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v102, v111, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v66, v111, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v78, v111, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v82, v111, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v106, v111, v1 op_sel:[1,0,0]
v_pk_fma_f16 v25, v59, v112, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v87, v112, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v75, v112, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v95, v112, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v47, v112, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v91, v112, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v55, v112, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v99, v112, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v51, v112, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v63, v112, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v71, v112, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v103, v112, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v67, v112, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v79, v112, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v83, v112, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v107, v112, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v59, v113, v25 op_sel:[1,0,0]
v_pk_fma_f16 v17, v87, v113, v17 op_sel:[1,0,0]
v_pk_fma_f16 v16, v75, v113, v16 op_sel:[1,0,0]
v_pk_fma_f16 v14, v95, v113, v14 op_sel:[1,0,0]
v_pk_fma_f16 v12, v47, v113, v12 op_sel:[1,0,0]
v_pk_fma_f16 v11, v91, v113, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v55, v113, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v99, v113, v9 op_sel:[1,0,0]
v_pk_fma_f16 v8, v51, v113, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v63, v113, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v71, v113, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v103, v113, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v67, v113, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v79, v113, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v83, v113, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v107, v113, v1 op_sel:[1,0,0]
v_pk_fma_f16 v25, v60, v114, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v88, v114, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v76, v114, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v96, v114, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v48, v114, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v92, v114, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v56, v114, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v100, v114, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v52, v114, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v64, v114, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v72, v114, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v104, v114, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v68, v114, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v80, v114, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v84, v114, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v108, v114, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v60, v115, v25 op_sel:[1,0,0]
v_pk_fma_f16 v17, v88, v115, v17 op_sel:[1,0,0]
v_pk_fma_f16 v16, v76, v115, v16 op_sel:[1,0,0]
v_pk_fma_f16 v14, v96, v115, v14 op_sel:[1,0,0]
v_pk_fma_f16 v12, v48, v115, v12 op_sel:[1,0,0]
v_pk_fma_f16 v11, v92, v115, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v56, v115, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v100, v115, v9 op_sel:[1,0,0]
v_pk_fma_f16 v8, v52, v115, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v64, v115, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v72, v115, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v104, v115, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v68, v115, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v80, v115, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v84, v115, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v108, v115, v1 op_sel:[1,0,0]
v_pk_fma_f16 v25, v61, v116, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v89, v116, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v77, v116, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v97, v116, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v49, v116, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v93, v116, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v57, v116, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v101, v116, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v53, v116, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v65, v116, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v73, v116, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v105, v116, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v69, v116, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v81, v116, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v85, v116, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v109, v116, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v61, v117, v25 op_sel:[1,0,0]
v_pk_fma_f16 v17, v89, v117, v17 op_sel:[1,0,0]
v_pk_fma_f16 v16, v77, v117, v16 op_sel:[1,0,0]
v_pk_fma_f16 v14, v97, v117, v14 op_sel:[1,0,0]
v_pk_fma_f16 v12, v49, v117, v12 op_sel:[1,0,0]
v_pk_fma_f16 v11, v93, v117, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v57, v117, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v101, v117, v9 op_sel:[1,0,0]
v_pk_fma_f16 v8, v53, v117, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v65, v117, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v73, v117, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v105, v117, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v69, v117, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v81, v117, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v85, v117, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v109, v117, v1 op_sel:[1,0,0]
s_cbranch_scc1 BB24_4
BB24_2:
s_add_i32 s0, s10, s11
v_or_b32_e32 v46, s0, v13
v_add_nc_u32_e32 v47, v46, v18
v_add3_u32 v49, v46, v19, v20
v_add3_u32 v51, v46, v22, v21
v_add3_u32 v53, v46, v24, v23
v_add3_u32 v55, v46, v29, v27
v_ashrrev_i32_e32 v48, 31, v47
v_ashrrev_i32_e32 v50, 31, v49
v_ashrrev_i32_e32 v52, 31, v51
v_ashrrev_i32_e32 v54, 31, v53
v_ashrrev_i32_e32 v56, 31, v55
v_lshlrev_b64 v[47:48], 1, v[47:48]
v_lshlrev_b64 v[49:50], 1, v[49:50]
v_lshlrev_b64 v[51:52], 1, v[51:52]
v_lshlrev_b64 v[53:54], 1, v[53:54]
v_lshlrev_b64 v[55:56], 1, v[55:56]
v_add3_u32 v57, v46, v30, v20
v_add_co_u32 v47, s0, s8, v47
v_add3_u32 v59, v46, v33, v23
v_add_co_ci_u32_e64 v48, s0, s9, v48, s0
v_add_co_u32 v49, s0, s8, v49
v_ashrrev_i32_e32 v58, 31, v57
v_add_co_ci_u32_e64 v50, s0, s9, v50, s0
v_add_co_u32 v51, s0, s8, v51
v_ashrrev_i32_e32 v60, 31, v59
v_add_co_ci_u32_e64 v52, s0, s9, v52, s0
v_add_co_u32 v53, s0, s8, v53
v_add3_u32 v61, v46, v37, v21
v_add_co_ci_u32_e64 v54, s0, s9, v54, s0
v_add_co_u32 v55, s0, s8, v55
v_add_co_ci_u32_e64 v56, s0, s9, v56, s0
s_clause 0x4
global_load_ushort v63, v[47:48], off
global_load_ushort v64, v[49:50], off
global_load_ushort v65, v[51:52], off
global_load_ushort v66, v[53:54], off
global_load_ushort v67, v[55:56], off
v_add3_u32 v53, v46, v35, v27
v_lshlrev_b64 v[49:50], 1, v[57:58]
v_add3_u32 v51, v46, v31, v21
v_add_co_u32 v55, s0, s7, v47
v_lshlrev_b64 v[57:58], 1, v[59:60]
v_ashrrev_i32_e32 v54, 31, v53
v_add_co_ci_u32_e64 v56, s0, 0, v48, s0
v_add_co_u32 v49, s0, s8, v49
v_ashrrev_i32_e32 v52, 31, v51
v_add_co_ci_u32_e64 v50, s0, s9, v50, s0
v_lshlrev_b64 v[53:54], 1, v[53:54]
v_add3_u32 v59, v46, v36, v20
v_add_co_u32 v57, s0, s8, v57
v_lshlrev_b64 v[51:52], 1, v[51:52]
v_add_co_ci_u32_e64 v58, s0, s9, v58, s0
v_ashrrev_i32_e32 v62, 31, v61
v_add_co_u32 v53, s0, s8, v53
v_ashrrev_i32_e32 v60, 31, v59
v_add_co_ci_u32_e64 v54, s0, s9, v54, s0
v_add_co_u32 v51, s0, s8, v51
v_add_co_ci_u32_e64 v52, s0, s9, v52, s0
s_clause 0x1
global_load_ushort v68, v[57:58], off
global_load_ushort v69, v[53:54], off
v_lshlrev_b64 v[53:54], 1, v[59:60]
v_add_co_u32 v47, s0, 0x9000, v47
v_lshlrev_b64 v[57:58], 1, v[61:62]
v_add_co_ci_u32_e64 v48, s0, 0, v48, s0
v_add_co_u32 v53, s0, s8, v53
v_add_co_ci_u32_e64 v54, s0, s9, v54, s0
v_add_co_u32 v57, s0, s8, v57
v_add_co_ci_u32_e64 v58, s0, s9, v58, s0
s_clause 0x5
global_load_ushort v55, v[55:56], off offset:768
global_load_ushort v49, v[49:50], off
global_load_ushort v50, v[51:52], off
global_load_ushort v47, v[47:48], off offset:1536
global_load_ushort v48, v[53:54], off
global_load_ushort v51, v[57:58], off
s_waitcnt vmcnt(0)
s_barrier
ds_write_b16 v15, v63
ds_write_b16 v15, v64 offset:192
ds_write_b16 v15, v65 offset:384
ds_write_b16 v15, v66 offset:576
ds_write_b16 v15, v67 offset:768
ds_write_b16 v15, v68 offset:1536
ds_write_b16 v15, v69 offset:1728
ds_write_b16 v15, v55 offset:960
ds_write_b16 v15, v49 offset:1152
ds_write_b16 v15, v50 offset:1344
ds_write_b16 v15, v47 offset:1920
ds_write_b16 v15, v48 offset:2112
ds_write_b16 v15, v51 offset:2304
s_and_saveexec_b32 s12, vcc_lo
s_cbranch_execz BB24_1
v_add3_u32 v46, v46, v41, v39
v_ashrrev_i32_e32 v47, 31, v46
v_lshlrev_b64 v[46:47], 1, v[46:47]
v_add_co_u32 v46, s0, s8, v46
v_add_co_ci_u32_e64 v47, s0, s9, v47, s0
global_load_ushort v46, v[46:47], off
s_waitcnt vmcnt(0)
ds_write_b16 v15, v46 offset:2496
s_branch BB24_1
BB24_4:
v_mul_lo_u32 v13, v28, 12
s_movk_i32 s0, 0x258
s_mul_i32 s6, s6, 24
s_mulk_i32 s1, 0x2ee0
v_cvt_f32_f16_sdwa v81, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v87, v1
v_cvt_f32_f16_sdwa v48, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_sdwa v49, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_sub_nc_u32_e32 v0, v0, v13
v_mul_lo_u32 v13, v28, s0
v_cvt_f32_f16_sdwa v50, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_sdwa v51, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v52, v38
v_lshl_add_u32 v0, v0, 1, s6
v_cvt_f32_f16_e32 v53, v34
v_cvt_f32_f16_e32 v82, v32
v_cvt_f32_f16_e32 v83, v26
v_cvt_f32_f16_sdwa v56, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_add_nc_u32_e32 v18, v0, v13
v_mul_lo_u32 v13, 0xea60, v28
v_cvt_f32_f16_sdwa v57, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v60, v16
v_cvt_f32_f16_e32 v61, v14
v_ashrrev_i32_e32 v19, 31, v18
v_cvt_f32_f16_sdwa v62, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_sdwa v64, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v66, v12
v_add3_u32 v0, v0, s1, v13
v_lshlrev_b64 v[18:19], 2, v[18:19]
v_cvt_f32_f16_e32 v68, v10
v_cvt_f32_f16_sdwa v70, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v74, v8
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v12, 0x19c8, v0
v_add_co_u32 v18, vcc_lo, s4, v18
v_add_nc_u32_e32 v14, 0x2580, v0
v_add_co_ci_u32_e32 v19, vcc_lo, s5, v19, vcc_lo
v_add_nc_u32_e32 v20, 0x1068, v0
v_add_nc_u32_e32 v22, 0x1c20, v0
v_add_nc_u32_e32 v26, 0x708, v0
v_add_nc_u32_e32 v28, 0x12c0, v0
global_load_dwordx2 v[18:19], v[18:19], off
v_add_nc_u32_e32 v30, 0x1e78, v0
v_add_nc_u32_e32 v32, 0x2a30, v0
v_add_nc_u32_e32 v34, 0x960, v0
v_add_nc_u32_e32 v36, 0x1518, v0
v_add_nc_u32_e32 v38, 0x20d0, v0
v_add_nc_u32_e32 v40, 0x2c88, v0
v_cvt_f32_f16_sdwa v72, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v76, v6
v_cvt_f32_f16_sdwa v78, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v84, v4
v_cvt_f32_f16_sdwa v80, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v86, v2
v_add_nc_u32_e32 v2, 0xbb9, v0
v_add_nc_u32_e32 v4, 0x1771, v0
v_add_nc_u32_e32 v6, 0x2329, v0
v_add_nc_u32_e32 v8, s0, v0
v_add_nc_u32_e32 v10, 0xe10, v0
v_add_nc_u32_e32 v16, 0x4b0, v0
v_add_nc_u32_e32 v24, 0x27d8, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_cvt_f32_f16_sdwa v79, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v85, v3
v_ashrrev_i32_e32 v3, 31, v2
v_cvt_f32_f16_sdwa v73, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v77, v5
v_add_co_u32 v0, vcc_lo, s2, v0
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_cvt_f32_f16_sdwa v71, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_add_co_u32 v42, vcc_lo, 0x2800, v0
v_cvt_f32_f16_e32 v75, v7
v_add_co_ci_u32_e32 v43, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v44, vcc_lo, 0x5800, v0
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_ci_u32_e32 v45, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v46, vcc_lo, 0x8800, v0
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_cvt_f32_f16_sdwa v65, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v69, v9
v_ashrrev_i32_e32 v9, 31, v8
v_add_co_ci_u32_e32 v47, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_cvt_f32_f16_sdwa v63, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v67, v11
v_ashrrev_i32_e32 v11, 31, v10
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_ashrrev_i32_e32 v15, 31, v14
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s2, v8
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_cvt_f32_f16_sdwa v55, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v59, v17
v_ashrrev_i32_e32 v17, 31, v16
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s2, v10
v_lshlrev_b64 v[14:15], 2, v[14:15]
v_ashrrev_i32_e32 v21, 31, v20
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
v_add_co_u32 v12, vcc_lo, s2, v12
v_lshlrev_b64 v[16:17], 2, v[16:17]
v_ashrrev_i32_e32 v23, 31, v22
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
v_add_co_u32 v14, vcc_lo, s2, v14
v_lshlrev_b64 v[20:21], 2, v[20:21]
v_cvt_f32_f16_sdwa v54, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v58, v25
v_ashrrev_i32_e32 v25, 31, v24
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
v_add_co_u32 v16, vcc_lo, s2, v16
v_lshlrev_b64 v[22:23], 2, v[22:23]
v_ashrrev_i32_e32 v27, 31, v26
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
v_add_co_u32 v20, vcc_lo, s2, v20
v_lshlrev_b64 v[24:25], 2, v[24:25]
v_ashrrev_i32_e32 v29, 31, v28
v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo
v_add_co_u32 v22, vcc_lo, s2, v22
v_lshlrev_b64 v[26:27], 2, v[26:27]
v_ashrrev_i32_e32 v31, 31, v30
v_add_co_ci_u32_e32 v23, vcc_lo, s3, v23, vcc_lo
v_add_co_u32 v24, vcc_lo, s2, v24
v_lshlrev_b64 v[28:29], 2, v[28:29]
v_ashrrev_i32_e32 v33, 31, v32
v_add_co_ci_u32_e32 v25, vcc_lo, s3, v25, vcc_lo
v_add_co_u32 v26, vcc_lo, s2, v26
v_lshlrev_b64 v[30:31], 2, v[30:31]
v_ashrrev_i32_e32 v35, 31, v34
v_add_co_ci_u32_e32 v27, vcc_lo, s3, v27, vcc_lo
v_add_co_u32 v28, vcc_lo, s2, v28
v_lshlrev_b64 v[32:33], 2, v[32:33]
v_ashrrev_i32_e32 v37, 31, v36
v_add_co_ci_u32_e32 v29, vcc_lo, s3, v29, vcc_lo
v_add_co_u32 v30, vcc_lo, s2, v30
v_lshlrev_b64 v[34:35], 2, v[34:35]
v_ashrrev_i32_e32 v39, 31, v38
v_add_co_ci_u32_e32 v31, vcc_lo, s3, v31, vcc_lo
v_add_co_u32 v32, vcc_lo, s2, v32
v_lshlrev_b64 v[36:37], 2, v[36:37]
v_ashrrev_i32_e32 v41, 31, v40
v_add_co_ci_u32_e32 v33, vcc_lo, s3, v33, vcc_lo
v_add_co_u32 v34, vcc_lo, s2, v34
v_lshlrev_b64 v[38:39], 2, v[38:39]
v_add_co_ci_u32_e32 v35, vcc_lo, s3, v35, vcc_lo
v_add_co_u32 v36, vcc_lo, s2, v36
v_lshlrev_b64 v[40:41], 2, v[40:41]
v_add_co_ci_u32_e32 v37, vcc_lo, s3, v37, vcc_lo
v_add_co_u32 v38, vcc_lo, s2, v38
v_add_co_ci_u32_e32 v39, vcc_lo, s3, v39, vcc_lo
v_add_co_u32 v40, vcc_lo, s2, v40
v_add_co_ci_u32_e32 v41, vcc_lo, s3, v41, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v88, v18, v49
v_add_f32_e32 v89, v18, v50
v_add_f32_e32 v49, v19, v52
v_add_f32_e32 v48, v18, v48
v_add_f32_e32 v90, v18, v51
v_add_f32_e32 v91, v19, v53
v_add_f32_e32 v50, v18, v54
v_add_f32_e32 v52, v18, v55
v_add_f32_e32 v51, v19, v58
v_add_f32_e32 v54, v18, v56
v_add_f32_e32 v53, v19, v59
v_add_f32_e32 v56, v18, v57
v_add_f32_e32 v55, v19, v60
v_add_f32_e32 v57, v19, v61
v_add_f32_e32 v58, v18, v62
v_add_f32_e32 v60, v18, v63
v_add_f32_e32 v59, v19, v66
v_add_f32_e32 v62, v18, v64
v_add_f32_e32 v61, v19, v67
v_add_f32_e32 v64, v18, v65
v_add_f32_e32 v63, v19, v68
v_add_f32_e32 v65, v19, v69
v_add_f32_e32 v66, v18, v70
v_add_f32_e32 v68, v18, v71
v_add_f32_e32 v67, v19, v74
v_add_f32_e32 v70, v18, v72
v_add_f32_e32 v69, v19, v75
v_add_f32_e32 v72, v18, v73
v_add_f32_e32 v71, v19, v76
v_add_f32_e32 v73, v19, v77
v_add_f32_e32 v74, v18, v78
v_add_f32_e32 v76, v18, v79
v_add_f32_e32 v78, v18, v80
v_add_f32_e32 v80, v18, v81
v_add_f32_e32 v75, v19, v84
v_add_f32_e32 v77, v19, v85
v_add_f32_e32 v79, v19, v86
v_add_f32_e32 v81, v19, v87
v_add_f32_e32 v18, v19, v82
v_add_f32_e32 v19, v19, v83
global_store_dword v[42:43], v88, off offset:1760
global_store_dword v[44:45], v89, off offset:1472
global_store_dwordx2 v[0:1], v[48:49], off
global_store_dword v[46:47], v90, off offset:1184
global_store_dword v[2:3], v91, off
global_store_dword v[4:5], v18, off
global_store_dword v[6:7], v19, off
global_store_dwordx2 v[8:9], v[50:51], off
global_store_dwordx2 v[10:11], v[52:53], off
global_store_dwordx2 v[12:13], v[54:55], off
global_store_dwordx2 v[14:15], v[56:57], off
global_store_dwordx2 v[16:17], v[58:59], off
global_store_dwordx2 v[20:21], v[60:61], off
global_store_dwordx2 v[22:23], v[62:63], off
global_store_dwordx2 v[24:25], v[64:65], off
global_store_dwordx2 v[26:27], v[66:67], off
global_store_dwordx2 v[28:29], v[68:69], off
global_store_dwordx2 v[30:31], v[70:71], off
global_store_dwordx2 v[32:33], v[72:73], off
global_store_dwordx2 v[34:35], v[74:75], off
global_store_dwordx2 v[36:37], v[76:77], off
global_store_dwordx2 v[38:39], v[78:79], off
global_store_dwordx2 v[40:41], v[80:81], off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_batch_matmul_cast_add_1_kernel0
.amdhsa_group_segment_fixed_size 5632
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 118
.amdhsa_next_free_sgpr 15
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end24:
.size tvmgen_default_fused_nn_batch_matmul_cast_add_1_kernel0, .Lfunc_end24-tvmgen_default_fused_nn_batch_matmul_cast_add_1_kernel0
.globl tvmgen_default_fused_nn_batch_matmul_cast_add_kernel0
.p2align 8
.type tvmgen_default_fused_nn_batch_matmul_cast_add_kernel0,@function
tvmgen_default_fused_nn_batch_matmul_cast_add_kernel0:
v_mul_hi_i32 v1, 0x88888889, v0
s_mul_hi_i32 s2, s6, 0x51eb851f
v_lshlrev_b32_e32 v3, 5, v0
s_lshr_b32 s7, s2, 31
s_ashr_i32 s2, s2, 5
s_movk_i32 s12, 0x780
s_movk_i32 s0, 0x4b00
s_add_i32 s7, s2, s7
v_add_nc_u32_e32 v1, v1, v0
s_mul_hi_i32 s1, s6, 0x66666667
s_mul_i32 s3, s6, s12
s_mul_i32 s2, s7, s0
s_lshr_b32 s8, s1, 31
s_ashr_i32 s1, s1, 2
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v1, 4, v1
v_add3_u32 v4, s2, s3, v3
s_add_i32 s1, s1, s8
s_clause 0x1
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_mul_i32 s0, s1, s0
v_add_nc_u32_e32 v1, v1, v2
v_subrev_nc_u32_e32 v2, s0, v4
s_mul_i32 s0, s1, s12
s_clause 0x1
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[4:5], s[4:5], 0x18
v_add_nc_u32_e32 v11, s0, v3
v_mul_lo_u32 v4, v1, 30
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b32_e32 v7, 4, v0
s_movk_i32 s13, 0x3c0
v_ashrrev_i32_e32 v12, 31, v11
v_cmp_gt_i32_e32 vcc_lo, 60, v0
v_lshlrev_b64 v[2:3], 1, v[2:3]
v_add_nc_u32_e32 v8, s13, v7
v_sub_nc_u32_e32 v5, v0, v4
v_lshlrev_b64 v[14:15], 1, v[11:12]
v_lshl_add_u32 v9, v1, 4, s13
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v6, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v11, s0, s10, v2
v_lshlrev_b32_e32 v10, 4, v5
v_add_co_ci_u32_e64 v12, s0, s11, v3, s0
v_add_co_u32 v14, s0, s8, v14
v_mov_b32_e32 v4, 0
v_add_co_ci_u32_e64 v15, s0, s9, v15, s0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v0, 0
s_mul_i32 s12, s1, 10
s_mov_b64 s[8:9], 0
s_sub_i32 s6, s6, s12
s_branch BB25_2
BB25_1:
s_or_b32 exec_lo, exec_lo, s10
s_waitcnt lgkmcnt(0)
s_barrier
ds_read_b128 v[16:19], v10 offset:480
ds_read_b128 v[20:23], v10
ds_read_b128 v[24:27], v9
ds_read_b128 v[28:31], v9 offset:160
ds_read_b128 v[32:35], v9 offset:320
ds_read_b128 v[36:39], v9 offset:480
ds_read_b128 v[40:43], v9 offset:640
ds_read_b128 v[44:47], v9 offset:800
v_mov_b32_e32 v48, 0xffff
s_add_u32 s8, s8, 16
s_addc_u32 s9, s9, 0
s_cmp_eq_u32 s8, 64
s_waitcnt lgkmcnt(7)
v_lshrrev_b32_e32 v49, 16, v16
s_waitcnt lgkmcnt(6)
v_and_b32_e32 v53, v48, v20
v_and_b32_sdwa v20, v48, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v54, v48, v21
v_lshrrev_b32_e32 v50, 16, v17
v_and_b32_sdwa v21, v48, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v16, v16, 16, v53
v_lshl_or_b32 v20, v49, 16, v20
v_lshl_or_b32 v17, v17, 16, v54
v_and_b32_e32 v55, v48, v22
v_lshl_or_b32 v21, v50, 16, v21
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v13, v24, v16, v13 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v6, v28, v16, v6 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v4, v32, v16, v4 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v3, v36, v16, v3 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v2, v40, v16, v2 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v0, v44, v16, v0 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v24, v20, v13 op_sel:[1,0,0]
v_pk_fma_f16 v6, v28, v20, v6 op_sel:[1,0,0]
v_pk_fma_f16 v4, v32, v20, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v36, v20, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v40, v20, v2 op_sel:[1,0,0]
v_pk_fma_f16 v0, v44, v20, v0 op_sel:[1,0,0]
v_pk_fma_f16 v13, v25, v17, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v29, v17, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v33, v17, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v37, v17, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v41, v17, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v45, v17, v0 op_sel_hi:[0,1,1]
v_lshrrev_b32_e32 v51, 16, v18
v_and_b32_sdwa v22, v48, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v18, v18, 16, v55
v_pk_fma_f16 v13, v25, v21, v13 op_sel:[1,0,0]
v_pk_fma_f16 v6, v29, v21, v6 op_sel:[1,0,0]
v_pk_fma_f16 v4, v33, v21, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v37, v21, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v41, v21, v2 op_sel:[1,0,0]
v_pk_fma_f16 v0, v45, v21, v0 op_sel:[1,0,0]
v_and_b32_e32 v17, v48, v23
v_pk_fma_f16 v13, v26, v18, v13 op_sel_hi:[0,1,1]
v_lshl_or_b32 v16, v51, 16, v22
v_pk_fma_f16 v6, v30, v18, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v34, v18, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v38, v18, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v42, v18, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v46, v18, v0 op_sel_hi:[0,1,1]
v_lshrrev_b32_e32 v52, 16, v19
v_pk_fma_f16 v13, v26, v16, v13 op_sel:[1,0,0]
v_lshl_or_b32 v17, v19, 16, v17
v_pk_fma_f16 v6, v30, v16, v6 op_sel:[1,0,0]
v_pk_fma_f16 v4, v34, v16, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v38, v16, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v42, v16, v2 op_sel:[1,0,0]
v_pk_fma_f16 v0, v46, v16, v0 op_sel:[1,0,0]
v_and_b32_sdwa v18, v48, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_fma_f16 v13, v27, v17, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v31, v17, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v35, v17, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v39, v17, v3 op_sel_hi:[0,1,1]
v_lshl_or_b32 v16, v52, 16, v18
v_pk_fma_f16 v2, v43, v17, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v47, v17, v0 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v27, v16, v13 op_sel:[1,0,0]
v_pk_fma_f16 v6, v31, v16, v6 op_sel:[1,0,0]
v_pk_fma_f16 v4, v35, v16, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v39, v16, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v43, v16, v2 op_sel:[1,0,0]
v_pk_fma_f16 v0, v47, v16, v0 op_sel:[1,0,0]
s_cbranch_scc1 BB25_4
BB25_2:
s_barrier
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz BB25_1
v_add_co_u32 v16, s0, v14, s8
v_add_co_ci_u32_e64 v17, s0, s9, v15, s0
v_add_co_u32 v20, s0, v11, s8
v_add_co_ci_u32_e64 v21, s0, s9, v12, s0
global_load_dwordx4 v[16:19], v[16:17], off
global_load_dwordx4 v[20:23], v[20:21], off
s_waitcnt vmcnt(1)
ds_write_b128 v8, v[16:19]
s_waitcnt vmcnt(0)
ds_write_b128 v7, v[20:23]
s_branch BB25_1
BB25_4:
s_mul_i32 s6, s6, 60
s_movk_i32 s0, 0x258
v_add_nc_u32_e32 v5, s6, v5
s_mul_i32 s7, s7, s0
v_mul_lo_u32 v1, v1, s0
s_mul_i32 s1, s1, 0x8ca0
v_cvt_f32_f16_e32 v19, v4
v_add_nc_u32_e32 v7, s7, v5
v_cvt_f32_f16_sdwa v20, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v23, v2
v_cvt_f32_f16_sdwa v24, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v21, v3
v_ashrrev_i32_e32 v8, 31, v7
v_cvt_f32_f16_sdwa v22, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v16, v13
v_cvt_f32_f16_sdwa v13, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v17, v6
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_cvt_f32_f16_sdwa v18, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_cvt_f32_f16_e32 v25, v0
v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_clause 0x1
global_load_dword v14, v[7:8], off
global_load_dword v15, v[7:8], off offset:120
v_add3_u32 v7, v5, v1, s1
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[4:5], 2, v[7:8]
v_add_co_u32 v1, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v3, vcc_lo, 0x5800, v1
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, 0xb800, v1
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v7, vcc_lo, 0x11800, v1
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v9, vcc_lo, 0x17000, v1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v11, vcc_lo, 0x1d000, v1
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v2, vcc_lo
s_waitcnt vmcnt(1)
v_add_f32_e32 v16, v14, v16
s_waitcnt vmcnt(0)
v_add_f32_e32 v13, v15, v13
v_add_f32_e32 v17, v14, v17
v_add_f32_e32 v18, v15, v18
v_add_f32_e32 v19, v14, v19
v_add_f32_e32 v20, v15, v20
v_add_f32_e32 v21, v14, v21
v_add_f32_e32 v23, v14, v23
v_add_f32_e32 v22, v15, v22
v_add_f32_e32 v24, v15, v24
v_add_f32_e32 v14, v14, v25
v_add_f32_e32 v0, v15, v0
global_store_dword v[1:2], v16, off
global_store_dword v[1:2], v13, off offset:120
global_store_dword v[3:4], v17, off offset:1472
global_store_dword v[3:4], v18, off offset:1592
global_store_dword v[5:6], v19, off offset:896
global_store_dword v[5:6], v20, off offset:1016
global_store_dword v[7:8], v21, off offset:320
global_store_dword v[7:8], v22, off offset:440
global_store_dword v[9:10], v23, off offset:1792
global_store_dword v[9:10], v24, off offset:1912
global_store_dword v[11:12], v14, off offset:1216
global_store_dword v[11:12], v0, off offset:1336
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_batch_matmul_cast_add_kernel0
.amdhsa_group_segment_fixed_size 1920
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 56
.amdhsa_next_free_sgpr 14
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end25:
.size tvmgen_default_fused_nn_batch_matmul_cast_add_kernel0, .Lfunc_end25-tvmgen_default_fused_nn_batch_matmul_cast_add_kernel0
.globl tvmgen_default_fused_nn_batch_matmul_cast_kernel0
.p2align 8
.type tvmgen_default_fused_nn_batch_matmul_cast_kernel0,@function
tvmgen_default_fused_nn_batch_matmul_cast_kernel0:
s_clause 0x1
s_load_dwordx2 s[2:3], s[4:5], 0x0
s_load_dwordx2 s[8:9], s[4:5], 0x8
v_cmp_lt_i32_e32 vcc_lo, 39, v0
v_cmp_gt_i32_e64 s0, 40, v0
s_mul_hi_i32 s10, s6, 0x66666667
s_mul_hi_i32 s7, s6, 0x51eb851f
s_and_saveexec_b32 s11, s0
s_cbranch_execz BB26_2
v_lshlrev_b32_e32 v1, 4, v0
s_lshr_b32 s1, s10, 31
s_ashr_i32 s12, s10, 2
v_lshlrev_b32_e32 v10, 3, v0
s_add_i32 s1, s12, s1
v_and_b32_e32 v1, 0x3fe0, v1
s_mul_i32 s13, s1, 0x280
v_lshlrev_b32_e32 v9, 2, v0
s_mul_i32 s1, s1, 10
s_lshr_b32 s12, s7, 31
v_add_nc_u32_e32 v7, s13, v1
s_ashr_i32 s14, s7, 4
v_and_b32_e32 v3, 0x1fe0, v10
s_sub_i32 s1, s6, s1
s_add_i32 s12, s14, s12
v_or_b32_e32 v2, 2, v9
s_mulk_i32 s1, 0x140
s_mulk_i32 s12, 0xc80
v_and_or_b32 v1, v9, 4, v7
v_add3_u32 v11, s12, s1, v3
v_lshlrev_b32_e32 v8, 1, v0
v_and_or_b32 v3, v2, 6, v7
v_ashrrev_i32_e32 v2, 31, v1
v_and_or_b32 v5, v8, 6, v11
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[3:4], 1, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, s1, s2, v1
v_lshlrev_b64 v[5:6], 1, v[5:6]
v_add_co_ci_u32_e64 v2, s1, s3, v2, s1
v_add_co_u32 v3, s1, s2, v3
v_add_co_ci_u32_e64 v4, s1, s3, v4, s1
v_add_co_u32 v5, s1, s8, v5
v_add_co_ci_u32_e64 v6, s1, s9, v6, s1
s_clause 0x1
global_load_ushort v1, v[1:2], off
global_load_ushort v2, v[3:4], off
global_load_ushort v12, v[5:6], off
v_or_b32_e32 v3, 1, v9
v_or_b32_e32 v4, 3, v9
v_or_b32_e32 v6, 1, v8
v_and_or_b32 v3, v3, 5, v7
v_and_or_b32 v5, v4, 7, v7
v_and_or_b32 v7, v6, 7, v11
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_lshlrev_b64 v[5:6], 1, v[5:6]
v_lshlrev_b64 v[7:8], 1, v[7:8]
v_add_co_u32 v3, s1, s2, v3
v_add_co_ci_u32_e64 v4, s1, s3, v4, s1
v_add_co_u32 v5, s1, s2, v5
v_add_co_ci_u32_e64 v6, s1, s3, v6, s1
v_add_co_u32 v7, s1, s8, v7
v_add_co_ci_u32_e64 v8, s1, s9, v8, s1
s_waitcnt vmcnt(2)
global_load_short_d16_hi v1, v[3:4], off
s_waitcnt vmcnt(2)
global_load_short_d16_hi v2, v[5:6], off
s_waitcnt vmcnt(2)
global_load_short_d16_hi v12, v[7:8], off
s_waitcnt vmcnt(1)
ds_write_b64 v10, v[1:2] offset:160
s_waitcnt vmcnt(0)
ds_write_b32 v9, v12
BB26_2:
s_or_b32 exec_lo, exec_lo, s11
s_mov_b32 s1, 0x66666667
s_waitcnt lgkmcnt(0)
s_barrier
v_mul_hi_i32 v1, v0, s1
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v1, 2, v1
v_add_nc_u32_e32 v1, v1, v2
v_mul_lo_u32 v2, v1, 10
v_lshlrev_b32_e32 v3, 6, v1
v_sub_nc_u32_e32 v2, v0, v2
v_lshlrev_b32_e32 v4, 4, v2
ds_read_b128 v[5:8], v3 offset:160
ds_read_b128 v[9:12], v3 offset:176
ds_read_b128 v[21:24], v3 offset:192
ds_read_b128 v[17:20], v3 offset:208
ds_read_b128 v[13:16], v4
v_add_nc_u32_e32 v3, 0xa0, v3
s_waitcnt lgkmcnt(0)
s_barrier
s_and_saveexec_b32 s11, s0
s_cbranch_execz BB26_4
v_lshlrev_b32_e32 v25, 4, v0
s_mul_hi_i32 s1, s6, s1
v_lshlrev_b32_e32 v34, 3, v0
s_lshr_b32 s12, s1, 31
s_ashr_i32 s1, s1, 2
v_and_b32_e32 v25, 0x3fe0, v25
s_add_i32 s1, s1, s12
v_lshlrev_b32_e32 v33, 2, v0
s_mul_i32 s12, s1, 0x280
s_mul_i32 s1, s1, 10
v_add_nc_u32_e32 v31, s12, v25
s_lshr_b32 s13, s7, 31
s_ashr_i32 s12, s7, 4
v_and_b32_e32 v27, 0x1fe0, v34
s_sub_i32 s1, s6, s1
s_add_i32 s12, s12, s13
v_or_b32_e32 v26, 2, v33
s_mulk_i32 s1, 0x140
s_mulk_i32 s12, 0xc80
v_and_or_b32 v25, v33, 4, v31
v_add3_u32 v35, s12, s1, v27
v_lshlrev_b32_e32 v32, 1, v0
v_and_or_b32 v27, v26, 6, v31
v_ashrrev_i32_e32 v26, 31, v25
v_and_or_b32 v29, v32, 6, v35
v_ashrrev_i32_e32 v28, 31, v27
v_lshlrev_b64 v[25:26], 1, v[25:26]
v_ashrrev_i32_e32 v30, 31, v29
v_lshlrev_b64 v[27:28], 1, v[27:28]
v_add_co_u32 v25, s1, s2, v25
v_lshlrev_b64 v[29:30], 1, v[29:30]
v_add_co_ci_u32_e64 v26, s1, s3, v26, s1
v_add_co_u32 v27, s1, s2, v27
v_add_co_ci_u32_e64 v28, s1, s3, v28, s1
v_add_co_u32 v29, s1, s8, v29
v_add_co_ci_u32_e64 v30, s1, s9, v30, s1
s_clause 0x1
global_load_ushort v25, v[25:26], off offset:16
global_load_ushort v26, v[27:28], off offset:16
global_load_ushort v36, v[29:30], off offset:16
v_or_b32_e32 v27, 1, v33
v_or_b32_e32 v28, 3, v33
v_and_or_b32 v27, v27, 5, v31
v_and_or_b32 v29, v28, 7, v31
v_or_b32_e32 v31, 1, v32
v_ashrrev_i32_e32 v28, 31, v27
v_ashrrev_i32_e32 v30, 31, v29
v_and_or_b32 v31, v31, 7, v35
v_lshlrev_b64 v[27:28], 1, v[27:28]
v_lshlrev_b64 v[29:30], 1, v[29:30]
v_ashrrev_i32_e32 v32, 31, v31
v_add_co_u32 v27, s1, s2, v27
v_lshlrev_b64 v[31:32], 1, v[31:32]
v_add_co_ci_u32_e64 v28, s1, s3, v28, s1
v_add_co_u32 v29, s1, s2, v29
v_add_co_ci_u32_e64 v30, s1, s3, v30, s1
v_add_co_u32 v31, s1, s8, v31
v_add_co_ci_u32_e64 v32, s1, s9, v32, s1
s_waitcnt vmcnt(2)
global_load_short_d16_hi v25, v[27:28], off offset:16
s_waitcnt vmcnt(2)
global_load_short_d16_hi v26, v[29:30], off offset:16
s_waitcnt vmcnt(2)
global_load_short_d16_hi v36, v[31:32], off offset:16
s_waitcnt vmcnt(1)
ds_write_b64 v34, v[25:26] offset:160
s_waitcnt vmcnt(0)
ds_write_b32 v33, v36
BB26_4:
s_or_b32 exec_lo, exec_lo, s11
s_waitcnt lgkmcnt(0)
s_barrier
ds_read_b128 v[25:28], v3
ds_read_b128 v[29:32], v3 offset:16
ds_read_b128 v[41:44], v3 offset:32
ds_read_b128 v[37:40], v3 offset:48
ds_read_b128 v[33:36], v4
s_waitcnt lgkmcnt(0)
s_barrier
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB26_6
v_lshlrev_b32_e32 v45, 4, v0
s_lshr_b32 s0, s10, 31
s_ashr_i32 s11, s10, 2
v_lshlrev_b32_e32 v54, 3, v0
s_add_i32 s0, s11, s0
v_and_b32_e32 v45, 0x3fe0, v45
s_mul_i32 s12, s0, 0x280
v_lshlrev_b32_e32 v53, 2, v0
s_mul_i32 s0, s0, 10
s_lshr_b32 s11, s7, 31
v_add_nc_u32_e32 v51, s12, v45
s_ashr_i32 s13, s7, 4
v_and_b32_e32 v47, 0x1fe0, v54
s_sub_i32 s0, s6, s0
s_add_i32 s11, s13, s11
v_or_b32_e32 v46, 2, v53
s_mulk_i32 s0, 0x140
s_mulk_i32 s11, 0xc80
v_and_or_b32 v45, v53, 4, v51
v_add3_u32 v55, s11, s0, v47
v_lshlrev_b32_e32 v52, 1, v0
v_and_or_b32 v47, v46, 6, v51
v_ashrrev_i32_e32 v46, 31, v45
v_and_or_b32 v49, v52, 6, v55
v_ashrrev_i32_e32 v48, 31, v47
v_lshlrev_b64 v[45:46], 1, v[45:46]
v_ashrrev_i32_e32 v50, 31, v49
v_lshlrev_b64 v[47:48], 1, v[47:48]
v_add_co_u32 v45, s0, s2, v45
v_lshlrev_b64 v[49:50], 1, v[49:50]
v_add_co_ci_u32_e64 v46, s0, s3, v46, s0
v_add_co_u32 v47, s0, s2, v47
v_add_co_ci_u32_e64 v48, s0, s3, v48, s0
v_add_co_u32 v49, s0, s8, v49
v_add_co_ci_u32_e64 v50, s0, s9, v50, s0
s_clause 0x1
global_load_ushort v45, v[45:46], off offset:32
global_load_ushort v46, v[47:48], off offset:32
global_load_ushort v56, v[49:50], off offset:32
v_or_b32_e32 v47, 1, v53
v_or_b32_e32 v48, 3, v53
v_or_b32_e32 v50, 1, v52
v_and_or_b32 v47, v47, 5, v51
v_and_or_b32 v49, v48, 7, v51
v_and_or_b32 v51, v50, 7, v55
v_ashrrev_i32_e32 v48, 31, v47
v_ashrrev_i32_e32 v50, 31, v49
v_ashrrev_i32_e32 v52, 31, v51
v_lshlrev_b64 v[47:48], 1, v[47:48]
v_lshlrev_b64 v[49:50], 1, v[49:50]
v_lshlrev_b64 v[51:52], 1, v[51:52]
v_add_co_u32 v47, s0, s2, v47
v_add_co_ci_u32_e64 v48, s0, s3, v48, s0
v_add_co_u32 v49, s0, s2, v49
v_add_co_ci_u32_e64 v50, s0, s3, v50, s0
v_add_co_u32 v51, s0, s8, v51
v_add_co_ci_u32_e64 v52, s0, s9, v52, s0
s_waitcnt vmcnt(2)
global_load_short_d16_hi v45, v[47:48], off offset:32
s_waitcnt vmcnt(2)
global_load_short_d16_hi v46, v[49:50], off offset:32
s_waitcnt vmcnt(2)
global_load_short_d16_hi v56, v[51:52], off offset:32
s_waitcnt vmcnt(1)
ds_write_b64 v54, v[45:46] offset:160
s_waitcnt vmcnt(0)
ds_write_b32 v53, v56
BB26_6:
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_barrier
ds_read_b128 v[45:48], v3
ds_read_b128 v[49:52], v3 offset:16
ds_read_b128 v[53:56], v3 offset:32
ds_read_b128 v[61:64], v3 offset:48
ds_read_b128 v[57:60], v4
s_load_dwordx2 s[0:1], s[4:5], 0x10
s_waitcnt lgkmcnt(0)
s_barrier
s_and_saveexec_b32 s4, vcc_lo
s_xor_b32 s4, exec_lo, s4
s_lshr_b32 s5, s10, 31
s_ashr_i32 s11, s10, 2
s_add_i32 s11, s11, s5
s_mul_i32 s5, s11, 10
s_sub_i32 s5, s6, s5
s_or_saveexec_b32 s4, s4
v_mov_b32_e32 v65, s11
v_mov_b32_e32 v66, s5
s_xor_b32 exec_lo, exec_lo, s4
s_cbranch_execz BB26_10
v_lshlrev_b32_e32 v65, 4, v0
s_lshr_b32 s5, s10, 31
s_ashr_i32 s10, s10, 2
v_lshlrev_b32_e32 v74, 3, v0
s_add_i32 s5, s10, s5
v_and_b32_e32 v65, 0x3fe0, v65
v_lshlrev_b32_e32 v73, 2, v0
s_mul_i32 s11, s5, 0x280
s_lshr_b32 s10, s7, 31
s_ashr_i32 s7, s7, 4
v_add_nc_u32_e32 v75, s11, v65
s_mul_i32 s11, s5, 10
v_and_b32_e32 v67, 0x1fe0, v74
s_add_i32 s7, s7, s10
s_sub_i32 s6, s6, s11
v_or_b32_e32 v66, 2, v73
s_mul_i32 s10, s6, 0x140
s_mulk_i32 s7, 0xc80
v_and_or_b32 v65, v73, 4, v75
v_add3_u32 v76, s7, s10, v67
v_lshlrev_b32_e32 v0, 1, v0
v_and_or_b32 v67, v66, 6, v75
v_ashrrev_i32_e32 v66, 31, v65
v_and_or_b32 v69, v0, 6, v76
v_ashrrev_i32_e32 v68, 31, v67
v_or_b32_e32 v0, 1, v0
v_lshlrev_b64 v[65:66], 1, v[65:66]
v_ashrrev_i32_e32 v70, 31, v69
v_lshlrev_b64 v[67:68], 1, v[67:68]
v_add_co_u32 v65, vcc_lo, s2, v65
v_lshlrev_b64 v[69:70], 1, v[69:70]
v_add_co_ci_u32_e32 v66, vcc_lo, s3, v66, vcc_lo
v_add_co_u32 v67, vcc_lo, s2, v67
v_add_co_ci_u32_e32 v68, vcc_lo, s3, v68, vcc_lo
v_add_co_u32 v69, vcc_lo, s8, v69
v_add_co_ci_u32_e32 v70, vcc_lo, s9, v70, vcc_lo
s_clause 0x1
global_load_ushort v71, v[65:66], off offset:48
global_load_ushort v72, v[67:68], off offset:48
global_load_ushort v77, v[69:70], off offset:48
v_or_b32_e32 v65, 1, v73
v_or_b32_e32 v66, 3, v73
v_and_or_b32 v69, v0, 7, v76
v_and_or_b32 v65, v65, 5, v75
v_and_or_b32 v67, v66, 7, v75
v_ashrrev_i32_e32 v70, 31, v69
v_ashrrev_i32_e32 v66, 31, v65
v_ashrrev_i32_e32 v68, 31, v67
v_lshlrev_b64 v[69:70], 1, v[69:70]
v_lshlrev_b64 v[65:66], 1, v[65:66]
v_lshlrev_b64 v[67:68], 1, v[67:68]
v_add_co_u32 v65, vcc_lo, s2, v65
v_add_co_ci_u32_e32 v66, vcc_lo, s3, v66, vcc_lo
v_add_co_u32 v67, vcc_lo, s2, v67
v_add_co_ci_u32_e32 v68, vcc_lo, s3, v68, vcc_lo
v_add_co_u32 v69, vcc_lo, s8, v69
v_add_co_ci_u32_e32 v70, vcc_lo, s9, v70, vcc_lo
s_waitcnt vmcnt(2)
global_load_short_d16_hi v71, v[65:66], off offset:48
s_waitcnt vmcnt(2)
global_load_short_d16_hi v72, v[67:68], off offset:48
s_waitcnt vmcnt(2)
global_load_short_d16_hi v77, v[69:70], off offset:48
v_mov_b32_e32 v65, s5
v_mov_b32_e32 v66, s6
s_waitcnt vmcnt(1)
ds_write_b64 v74, v[71:72] offset:160
s_waitcnt vmcnt(0)
ds_write_b32 v73, v77
BB26_10:
s_or_b32 exec_lo, exec_lo, s4
v_lshrrev_b32_e32 v0, 16, v13
v_lshrrev_b32_e32 v67, 16, v21
v_fma_f16 v68, v21, v13, 0
v_lshrrev_b32_e32 v21, 16, v17
v_fma_f16 v69, v17, v13, 0
v_lshrrev_b32_e32 v17, 16, v14
v_fma_f16 v70, v5, v13, 0
v_fmac_f16_e32 v68, v67, v0
v_fma_f16 v67, v9, v13, 0
v_fmac_f16_e32 v69, v21, v0
v_lshrrev_b32_e32 v21, 16, v22
v_lshrrev_b32_e32 v13, 16, v24
v_fmac_f16_e32 v68, v22, v14
v_lshrrev_b32_e32 v22, 16, v18
v_fmac_f16_e32 v69, v18, v14
v_lshrrev_b32_e32 v18, 16, v15
v_lshrrev_b32_e32 v71, 16, v33
v_fmac_f16_e32 v68, v21, v17
v_lshrrev_b32_e32 v21, 16, v23
v_fmac_f16_e32 v69, v22, v17
v_lshrrev_b32_e32 v22, 16, v9
v_lshrrev_b32_e32 v9, 16, v5
v_fmac_f16_e32 v68, v23, v15
v_lshrrev_b32_e32 v23, 16, v19
v_fmac_f16_e32 v69, v19, v15
v_fmac_f16_e32 v67, v22, v0
v_fmac_f16_e32 v70, v9, v0
v_lshrrev_b32_e32 v5, 16, v10
v_lshrrev_b32_e32 v19, 16, v6
v_fmac_f16_e32 v68, v21, v18
v_fmac_f16_e32 v67, v10, v14
v_fmac_f16_e32 v70, v6, v14
v_fmac_f16_e32 v69, v23, v18
v_lshrrev_b32_e32 v21, 16, v11
v_fmac_f16_e32 v68, v24, v16
v_fmac_f16_e32 v67, v5, v17
v_fmac_f16_e32 v70, v19, v17
v_lshrrev_b32_e32 v24, 16, v7
v_lshrrev_b32_e32 v23, 16, v16
v_fmac_f16_e32 v69, v20, v16
v_fmac_f16_e32 v67, v11, v15
v_fmac_f16_e32 v70, v7, v15
v_lshrrev_b32_e32 v20, 16, v20
v_lshrrev_b32_e32 v10, 16, v8
v_lshrrev_b32_e32 v14, 16, v12
v_fmac_f16_e32 v67, v21, v18
v_fmac_f16_e32 v70, v24, v18
v_fmac_f16_e32 v69, v20, v23
v_fmac_f16_e32 v68, v13, v23
v_lshrrev_b32_e32 v7, 16, v37
v_fmac_f16_e32 v67, v12, v16
v_fmac_f16_e32 v70, v8, v16
v_fmac_f16_e32 v69, v37, v33
v_lshrrev_b32_e32 v13, 16, v41
v_fmac_f16_e32 v68, v41, v33
v_fmac_f16_e32 v67, v14, v23
v_fmac_f16_e32 v70, v10, v23
v_fmac_f16_e32 v69, v7, v71
v_lshrrev_b32_e32 v10, 16, v29
v_lshrrev_b32_e32 v12, 16, v25
v_fmac_f16_e32 v67, v29, v33
v_fmac_f16_e32 v70, v25, v33
v_fmac_f16_e32 v68, v13, v71
v_lshrrev_b32_e32 v72, 16, v34
v_lshrrev_b32_e32 v7, 16, v38
v_fmac_f16_e32 v67, v10, v71
v_fmac_f16_e32 v70, v12, v71
v_fmac_f16_e32 v69, v38, v34
v_lshrrev_b32_e32 v22, 16, v42
v_fmac_f16_e32 v68, v42, v34
v_lshrrev_b32_e32 v10, 16, v30
v_fmac_f16_e32 v67, v30, v34
v_fmac_f16_e32 v69, v7, v72
v_lshrrev_b32_e32 v12, 16, v26
v_fmac_f16_e32 v70, v26, v34
v_fmac_f16_e32 v68, v22, v72
v_fmac_f16_e32 v67, v10, v72
v_lshrrev_b32_e32 v0, 16, v35
v_lshrrev_b32_e32 v7, 16, v39
v_fmac_f16_e32 v70, v12, v72
v_fmac_f16_e32 v69, v39, v35
v_lshrrev_b32_e32 v9, 16, v43
v_fmac_f16_e32 v68, v43, v35
v_lshrrev_b32_e32 v12, 16, v31
v_fmac_f16_e32 v67, v31, v35
v_fmac_f16_e32 v69, v7, v0
v_lshrrev_b32_e32 v17, 16, v27
v_fmac_f16_e32 v70, v27, v35
v_fmac_f16_e32 v68, v9, v0
v_fmac_f16_e32 v67, v12, v0
v_fmac_f16_e32 v69, v40, v36
v_lshrrev_b32_e32 v16, 16, v40
v_fmac_f16_e32 v70, v17, v0
v_lshrrev_b32_e32 v18, 16, v36
v_lshrrev_b32_e32 v6, 16, v44
v_fmac_f16_e32 v68, v44, v36
v_fmac_f16_e32 v67, v32, v36
v_lshrrev_b32_e32 v19, 16, v32
v_fmac_f16_e32 v69, v16, v18
v_lshrrev_b32_e32 v16, 16, v28
v_fmac_f16_e32 v70, v28, v36
v_fmac_f16_e32 v68, v6, v18
v_fmac_f16_e32 v67, v19, v18
v_lshrrev_b32_e32 v5, 16, v45
v_lshrrev_b32_e32 v9, 16, v57
v_fmac_f16_e32 v70, v16, v18
v_lshrrev_b32_e32 v7, 16, v49
v_fmac_f16_e32 v67, v49, v57
v_lshrrev_b32_e32 v12, 16, v53
v_fmac_f16_e32 v68, v53, v57
v_fmac_f16_e32 v70, v45, v57
v_lshrrev_b32_e32 v20, 16, v61
v_fmac_f16_e32 v69, v61, v57
v_fmac_f16_e32 v67, v7, v9
v_fmac_f16_e32 v68, v12, v9
v_fmac_f16_e32 v70, v5, v9
v_lshrrev_b32_e32 v11, 16, v46
v_fmac_f16_e32 v69, v20, v9
v_lshrrev_b32_e32 v8, 16, v58
v_lshrrev_b32_e32 v10, 16, v50
v_fmac_f16_e32 v67, v50, v58
v_fmac_f16_e32 v70, v46, v58
v_lshrrev_b32_e32 v0, 16, v54
v_fmac_f16_e32 v68, v54, v58
v_lshrrev_b32_e32 v6, 16, v62
v_fmac_f16_e32 v69, v62, v58
v_fmac_f16_e32 v67, v10, v8
v_fmac_f16_e32 v70, v11, v8
v_fmac_f16_e32 v68, v0, v8
v_lshrrev_b32_e32 v13, 16, v47
v_fmac_f16_e32 v69, v6, v8
v_lshrrev_b32_e32 v15, 16, v59
v_fmac_f16_e32 v70, v47, v59
v_lshrrev_b32_e32 v14, 16, v51
v_fmac_f16_e32 v67, v51, v59
v_lshrrev_b32_e32 v17, 16, v55
v_fmac_f16_e32 v68, v55, v59
v_lshrrev_b32_e32 v16, 16, v63
v_fmac_f16_e32 v69, v63, v59
v_fmac_f16_e32 v67, v14, v15
v_fmac_f16_e32 v70, v13, v15
v_fmac_f16_e32 v68, v17, v15
v_lshrrev_b32_e32 v21, 16, v48
v_fmac_f16_e32 v69, v16, v15
v_lshrrev_b32_e32 v22, 16, v60
v_fmac_f16_e32 v70, v48, v60
v_lshrrev_b32_e32 v23, 16, v52
v_fmac_f16_e32 v67, v52, v60
v_lshrrev_b32_e32 v24, 16, v56
v_fmac_f16_e32 v68, v56, v60
v_lshrrev_b32_e32 v25, 16, v64
v_fmac_f16_e32 v69, v64, v60
s_waitcnt lgkmcnt(0)
s_barrier
ds_read_b128 v[9:12], v4
ds_read_b128 v[5:8], v3
ds_read_b128 v[13:16], v3 offset:16
ds_read_b128 v[17:20], v3 offset:32
v_fmac_f16_e32 v68, v24, v22
v_fmac_f16_e32 v67, v23, v22
v_fmac_f16_e32 v70, v21, v22
v_fmac_f16_e32 v69, v25, v22
ds_read_b128 v[21:24], v3 offset:48
s_waitcnt lgkmcnt(4)
v_lshrrev_b32_e32 v26, 16, v9
s_waitcnt lgkmcnt(3)
v_lshrrev_b32_e32 v0, 16, v5
v_fmac_f16_e32 v70, v5, v9
s_waitcnt lgkmcnt(2)
v_lshrrev_b32_e32 v5, 16, v13
v_fmac_f16_e32 v67, v13, v9
s_waitcnt lgkmcnt(1)
v_lshrrev_b32_e32 v13, 16, v17
v_fmac_f16_e32 v68, v17, v9
v_fmac_f16_e32 v70, v0, v26
s_waitcnt lgkmcnt(0)
v_fmac_f16_e32 v69, v21, v9
v_lshrrev_b32_e32 v17, 16, v21
v_fmac_f16_e32 v67, v5, v26
v_fmac_f16_e32 v68, v13, v26
v_mul_lo_u32 v0, 0x190, v1
v_lshrrev_b32_e32 v3, 16, v6
v_fmac_f16_e32 v69, v17, v26
v_lshrrev_b32_e32 v27, 16, v10
v_fmac_f16_e32 v70, v6, v10
v_lshrrev_b32_e32 v30, 16, v14
v_fmac_f16_e32 v67, v14, v10
v_lshrrev_b32_e32 v33, 16, v18
v_fmac_f16_e32 v68, v18, v10
v_lshrrev_b32_e32 v36, 16, v22
v_fmac_f16_e32 v69, v22, v10
v_fmac_f16_e32 v70, v3, v27
v_mul_lo_u32 v1, v66, 10
v_mul_lo_u32 v3, 0x7d0, v65
v_fmac_f16_e32 v67, v30, v27
v_fmac_f16_e32 v68, v33, v27
v_add_nc_u32_e32 v0, v0, v2
v_fmac_f16_e32 v69, v36, v27
v_lshrrev_b32_e32 v4, 16, v7
v_lshrrev_b32_e32 v28, 16, v11
v_fmac_f16_e32 v70, v7, v11
v_lshrrev_b32_e32 v31, 16, v15
v_fmac_f16_e32 v67, v15, v11
v_add3_u32 v0, v0, v3, v1
v_lshrrev_b32_e32 v34, 16, v19
v_fmac_f16_e32 v68, v19, v11
v_lshrrev_b32_e32 v9, 16, v23
v_fmac_f16_e32 v69, v23, v11
v_fmac_f16_e32 v70, v4, v28
v_fmac_f16_e32 v67, v31, v28
v_ashrrev_i32_e32 v1, 31, v0
v_fmac_f16_e32 v68, v34, v28
v_fmac_f16_e32 v69, v9, v28
v_lshrrev_b32_e32 v25, 16, v8
v_lshrrev_b32_e32 v29, 16, v12
v_fmac_f16_e32 v70, v8, v12
v_lshrrev_b32_e32 v32, 16, v16
v_fmac_f16_e32 v67, v16, v12
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshrrev_b32_e32 v35, 16, v20
v_fmac_f16_e32 v68, v20, v12
v_lshrrev_b32_e32 v5, 16, v24
v_fmac_f16_e32 v69, v24, v12
v_fmac_f16_e32 v70, v25, v29
v_fmac_f16_e32 v67, v32, v29
v_fmac_f16_e32 v68, v35, v29
v_add_co_u32 v0, vcc_lo, s0, v0
v_fmac_f16_e32 v69, v5, v29
v_cvt_f32_f16_e32 v2, v70
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_cvt_f32_f16_e32 v3, v67
v_cvt_f32_f16_e32 v4, v68
v_cvt_f32_f16_e32 v5, v69
global_store_dword v[0:1], v2, off
global_store_dword v[0:1], v3, off offset:400
global_store_dword v[0:1], v4, off offset:800
global_store_dword v[0:1], v5, off offset:1200
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_batch_matmul_cast_kernel0
.amdhsa_group_segment_fixed_size 480
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 78
.amdhsa_next_free_sgpr 15
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end26:
.size tvmgen_default_fused_nn_batch_matmul_cast_kernel0, .Lfunc_end26-tvmgen_default_fused_nn_batch_matmul_cast_kernel0
.globl tvmgen_default_fused_nn_batch_matmul_kernel0
.p2align 8
.type tvmgen_default_fused_nn_batch_matmul_kernel0,@function
tvmgen_default_fused_nn_batch_matmul_kernel0:
s_mov_b32 s0, 0x66666667
v_add_nc_u32_e32 v3, 64, v0
v_mul_hi_i32 v2, v0, s0
s_mov_b32 s7, 0xcccccccd
v_add_nc_u32_e32 v1, 32, v0
v_add_nc_u32_e32 v7, 0x80, v0
v_mul_hi_u32 v3, v3, s7
s_clause 0x2
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_movk_i32 s4, 0x258
v_mul_hi_u32 v4, v1, s7
v_ashrrev_i32_e32 v5, 3, v2
v_lshrrev_b32_e32 v6, 31, v2
v_mul_hi_u32 v10, v7, s7
v_add_nc_u32_e32 v8, 0xc0, v0
v_lshrrev_b32_e32 v3, 4, v3
v_ashrrev_i32_e32 v2, 1, v2
v_add_nc_u32_e32 v12, v5, v6
v_add_nc_u32_e32 v5, 0x60, v0
v_lshrrev_b32_e32 v4, 4, v4
v_mul_i32_i24_e32 v14, s4, v3
v_add_nc_u32_e32 v3, 0xe0, v0
v_mul_hi_u32 v8, v8, s7
v_mul_hi_u32 v5, v5, s7
v_mul_i32_i24_e32 v13, s4, v4
v_lshlrev_b32_e32 v19, 2, v0
v_mul_hi_u32 v3, v3, s7
v_add_nc_u32_e32 v21, v2, v6
v_mad_u32_u24 v2, v0, 3, v7
s_mul_hi_i32 s5, s6, 0x51eb851f
v_lshrrev_b32_e32 v8, 4, v8
v_lshrrev_b32_e32 v4, 4, v5
v_lshrrev_b32_e32 v5, 4, v10
v_add_nc_u32_e32 v10, 8, v0
v_lshrrev_b32_e32 v20, 4, v3
v_mul_i32_i24_e32 v18, s4, v8
v_mul_i32_i24_e32 v16, s4, v4
v_add_nc_u32_e32 v8, 0x200, v19
v_mad_u32_u24 v4, v0, 3, v10
v_mul_i32_i24_e32 v17, s4, v5
v_add_nc_u32_e32 v5, 0x100, v19
v_mul_hi_i32 v6, v2, s0
v_add_nc_u32_e32 v7, 0x180, v19
v_mul_hi_i32 v3, v4, s0
v_mul_hi_u32 v8, v8, s7
v_mul_hi_u32 v5, v5, s7
s_lshr_b32 s12, s5, 31
v_mul_hi_u32 v7, v7, s7
s_ashr_i32 s5, s5, 4
v_lshrrev_b32_e32 v23, 3, v6
v_add_nc_u32_e32 v6, 4, v19
v_lshrrev_b32_e32 v3, 3, v3
v_lshrrev_b32_e32 v8, 4, v8
v_lshrrev_b32_e32 v5, 4, v5
s_add_i32 s5, s5, s12
v_mul_hi_u32 v6, v6, s7
v_mul_u32_u24_e32 v3, 20, v3
v_lshrrev_b32_e32 v7, 4, v7
v_mul_i32_i24_e32 v5, s4, v5
v_mul_i32_i24_e32 v8, s4, v8
s_mulk_i32 s5, 0x4b00
v_sub_nc_u32_e32 v22, v4, v3
v_add_nc_u32_e32 v4, 16, v19
v_add_nc_u32_e32 v3, 12, v19
v_mul_i32_i24_e32 v7, s4, v7
v_lshrrev_b32_e32 v6, 4, v6
v_add3_u32 v8, v8, s5, v19
v_mul_hi_u32 v4, v4, s7
v_mul_hi_u32 v24, v3, s7
v_add3_u32 v5, v5, s5, v19
v_and_b32_e32 v26, 15, v0
v_mul_hi_u32 v10, v10, s7
v_add_nc_u32_e32 v11, 4, v0
v_add3_u32 v7, v7, s5, v19
v_mul_u32_u24_e32 v6, 20, v6
v_lshrrev_b32_e32 v4, 4, v4
v_lshrrev_b32_e32 v24, 4, v24
v_add_nc_u32_e32 v15, 16, v0
v_lshrrev_b32_e32 v3, 4, v0
s_movk_i32 s0, 0x244
v_mul_u32_u24_e32 v27, 20, v4
v_mul_u32_u24_e32 v24, 20, v24
v_add_nc_u32_e32 v9, 12, v0
v_mul_u32_u24_e32 v26, 40, v26
v_sub_nc_u32_e32 v7, v7, v6
v_mul_lo_u32 v21, v21, s0
v_sub_nc_u32_e32 v8, v8, v24
v_sub_nc_u32_e32 v24, v5, v27
v_mul_hi_u32 v15, v15, s7
v_lshlrev_b32_e32 v5, 1, v26
v_mul_u32_u24_e32 v25, 0x78, v3
v_add_nc_u32_e32 v6, 12, v8
v_add_nc_u32_e32 v8, 16, v24
v_mul_hi_u32 v24, v11, s7
v_lshrrev_b32_e32 v10, 4, v10
v_mul_hi_u32 v26, v9, s7
s_movk_i32 s1, 0x500
v_mad_i32_i24 v20, v20, s4, v0
v_lshl_add_u32 v4, v25, 1, s1
v_mul_u32_u24_e32 v25, 20, v10
v_add3_u32 v10, s5, v21, v19
v_lshrrev_b32_e32 v19, 4, v24
v_lshl_add_u32 v1, v0, 1, s1
s_mul_i32 s1, s6, 0x1c20
v_lshrrev_b32_e32 v15, 4, v15
v_add3_u32 v11, v20, s1, 4
v_lshrrev_b32_e32 v20, 4, v26
v_add3_u32 v14, v14, v0, s1
v_mul_u32_u24_e32 v19, 20, v19
v_add3_u32 v17, v17, v0, s1
v_add3_u32 v16, v16, v0, s1
v_mul_u32_u24_e32 v15, 20, v15
v_add3_u32 v18, v18, v0, s1
v_mul_u32_u24_e32 v20, 20, v20
v_add3_u32 v13, v13, v0, s1
v_sub_nc_u32_e32 v14, v14, v19
v_mul_lo_u32 v19, v12, s0
v_mul_u32_u24_e32 v23, s4, v23
v_sub_nc_u32_e32 v17, v17, v25
v_sub_nc_u32_e32 v15, v16, v15
v_sub_nc_u32_e32 v16, v18, v20
v_sub_nc_u32_e32 v18, v13, v20
v_add3_u32 v9, v22, s5, v23
v_add_nc_u32_e32 v12, 8, v17
v_add_nc_u32_e32 v13, 16, v15
v_add_nc_u32_e32 v15, 12, v16
v_add_nc_u32_e32 v16, 12, v18
v_add3_u32 v17, v0, s1, v19
v_cmp_gt_i32_e32 vcc_lo, 16, v0
v_lshlrev_b32_e32 v2, 3, v0
v_add_nc_u32_e32 v7, 4, v7
v_add_nc_u32_e32 v14, 4, v14
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v18, 0
s_mov_b32 s5, 0
s_branch BB27_2
BB27_1:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v24, s5, v10
v_add_nc_u32_e32 v26, s5, v9
v_add_nc_u32_e32 v28, s5, v8
v_add_nc_u32_e32 v30, s5, v7
v_add_nc_u32_e32 v32, s5, v6
v_ashrrev_i32_e32 v25, 31, v24
v_ashrrev_i32_e32 v27, 31, v26
v_ashrrev_i32_e32 v29, 31, v28
v_ashrrev_i32_e32 v31, 31, v30
v_ashrrev_i32_e32 v33, 31, v32
v_lshlrev_b64 v[24:25], 1, v[24:25]
v_lshlrev_b64 v[26:27], 1, v[26:27]
v_lshlrev_b64 v[28:29], 1, v[28:29]
v_lshlrev_b64 v[30:31], 1, v[30:31]
v_lshlrev_b64 v[32:33], 1, v[32:33]
v_lshrrev_b32_e32 v53, 16, v18
v_add_co_u32 v24, s0, s10, v24
v_add_co_u32 v26, s1, s10, v26
v_add_co_ci_u32_e64 v25, s0, s11, v25, s0
v_add_co_ci_u32_e64 v27, s0, s11, v27, s1
v_add_co_u32 v28, s0, s10, v28
v_mov_b32_e32 v52, 0xffff
v_add_co_ci_u32_e64 v29, s0, s11, v29, s0
v_add_co_u32 v30, s0, s10, v30
s_add_i32 s5, s5, 20
v_add_co_ci_u32_e64 v31, s0, s11, v31, s0
v_add_co_u32 v32, s0, s10, v32
s_cmp_eq_u32 s5, s4
v_add_co_ci_u32_e64 v33, s0, s11, v33, s0
s_clause 0x4
global_load_dwordx2 v[24:25], v[24:25], off
global_load_dwordx2 v[26:27], v[26:27], off
global_load_dwordx2 v[28:29], v[28:29], off
global_load_dwordx2 v[30:31], v[30:31], off
global_load_dwordx2 v[32:33], v[32:33], off
s_waitcnt vmcnt(3)
ds_write2_b64 v2, v[24:25], v[26:27] offset1:32
s_waitcnt vmcnt(1)
ds_write2_b64 v2, v[28:29], v[30:31] offset0:64 offset1:96
s_waitcnt vmcnt(0)
ds_write_b64 v2, v[32:33] offset:1024
s_waitcnt lgkmcnt(0)
s_barrier
ds_read_b128 v[24:27], v5
ds_read_b128 v[28:31], v5 offset:32
ds_read2_b64 v[32:35], v4 offset0:5 offset1:6
ds_read_b128 v[36:39], v5 offset:48
ds_read_b128 v[40:43], v5 offset:64
ds_read_b128 v[44:47], v4
ds_read_b128 v[48:51], v5 offset:16
s_waitcnt lgkmcnt(6)
v_lshrrev_b32_e32 v54, 16, v24
s_waitcnt lgkmcnt(5)
v_lshrrev_b32_e32 v58, 16, v30
s_waitcnt lgkmcnt(4)
v_lshrrev_b32_e32 v61, 16, v32
v_fmac_f16_e32 v18, v32, v24
v_fmac_f16_e32 v53, v32, v30
v_and_b32_e32 v60, v52, v24
v_lshrrev_b32_e32 v55, 16, v25
v_lshrrev_b32_e32 v59, 16, v31
v_fmac_f16_e32 v18, v61, v54
v_fmac_f16_e32 v53, v61, v58
v_lshrrev_b32_e32 v24, 16, v33
s_waitcnt lgkmcnt(0)
v_and_b32_e32 v65, v52, v51
v_lshrrev_b32_e32 v56, 16, v26
v_fmac_f16_e32 v18, v33, v25
v_fmac_f16_e32 v53, v33, v31
v_and_b32_e32 v33, v52, v50
v_lshrrev_b32_e32 v32, 16, v34
v_lshrrev_b32_e32 v62, 16, v36
v_fmac_f16_e32 v18, v24, v55
v_fmac_f16_e32 v53, v24, v59
v_and_b32_e32 v66, v52, v28
v_and_b32_e32 v24, v52, v29
v_lshrrev_b32_e32 v61, 16, v40
v_fmac_f16_e32 v18, v34, v26
v_fmac_f16_e32 v53, v34, v36
v_lshl_or_b32 v67, v40, 16, v33
v_lshrrev_b32_e32 v63, 16, v41
v_lshl_or_b32 v65, v41, 16, v65
v_fmac_f16_e32 v18, v32, v56
v_fmac_f16_e32 v53, v32, v62
v_and_b32_e32 v40, v52, v54
v_and_b32_e32 v41, v52, v55
v_lshrrev_b32_e32 v57, 16, v27
v_lshrrev_b32_e32 v64, 16, v42
v_lshl_or_b32 v66, v42, 16, v66
v_lshl_or_b32 v55, v58, 16, v40
v_lshl_or_b32 v68, v43, 16, v24
v_lshrrev_b32_e32 v69, 16, v43
v_lshl_or_b32 v58, v59, 16, v41
v_and_b32_e32 v70, v52, v25
v_and_b32_e32 v71, v52, v26
v_and_b32_e32 v72, v52, v27
v_fmac_f16_e32 v18, v35, v27
v_lshrrev_b32_e32 v73, 16, v35
v_fmac_f16_e32 v53, v35, v37
ds_read_b128 v[24:27], v4 offset:80
ds_read2_b64 v[32:35], v4 offset0:15 offset1:16
ds_read_b128 v[40:43], v4 offset:160
v_lshl_or_b32 v30, v30, 16, v60
v_fmac_f16_e32 v18, v73, v57
v_and_b32_sdwa v28, v52, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v29, v52, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_fma_f16 v54, v44, v30, v23 op_sel_hi:[0,1,1]
v_lshl_or_b32 v28, v64, 16, v28
v_lshl_or_b32 v29, v69, 16, v29
v_pk_fma_f16 v44, v44, v55, v54 op_sel:[1,0,0]
v_lshrrev_b32_e32 v54, 16, v38
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v59, v24, v30, v22 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v60, v32, v30, v21 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v74, v40, v30, v20 op_sel_hi:[0,1,1]
ds_read2_b64 v[20:23], v4 offset0:25 offset1:26
v_pk_fma_f16 v24, v24, v55, v59 op_sel:[1,0,0]
v_pk_fma_f16 v32, v32, v55, v60 op_sel:[1,0,0]
v_pk_fma_f16 v40, v40, v55, v74 op_sel:[1,0,0]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v19, v20, v30, v19 op_sel_hi:[0,1,1]
v_and_b32_e32 v30, v52, v56
v_pk_fma_f16 v19, v20, v55, v19 op_sel:[1,0,0]
v_lshl_or_b32 v20, v31, 16, v70
v_lshl_or_b32 v30, v62, 16, v30
v_and_b32_sdwa v62, v52, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v55, v52, v48
v_and_b32_sdwa v70, v52, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_fma_f16 v19, v21, v20, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v25, v20, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v45, v20, v44 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v33, v20, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v40, v41, v20, v40 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v21, v58, v19 op_sel:[1,0,0]
v_lshl_or_b32 v21, v36, 16, v71
v_pk_fma_f16 v20, v45, v58, v31 op_sel:[1,0,0]
v_pk_fma_f16 v24, v25, v58, v24 op_sel:[1,0,0]
v_pk_fma_f16 v25, v33, v58, v32 op_sel:[1,0,0]
v_pk_fma_f16 v31, v41, v58, v40 op_sel:[1,0,0]
v_pk_fma_f16 v19, v22, v21, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v46, v21, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v26, v21, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v34, v21, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v42, v21, v31 op_sel_hi:[0,1,1]
v_lshl_or_b32 v21, v37, 16, v72
v_pk_fma_f16 v19, v22, v30, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v46, v30, v20 op_sel:[1,0,0]
v_lshrrev_b32_e32 v44, 16, v37
v_pk_fma_f16 v24, v26, v30, v24 op_sel:[1,0,0]
v_pk_fma_f16 v25, v34, v30, v25 op_sel:[1,0,0]
v_pk_fma_f16 v40, v23, v21, v19 op_sel_hi:[0,1,1]
v_and_b32_e32 v19, v52, v57
v_pk_fma_f16 v26, v42, v30, v31 op_sel:[1,0,0]
v_pk_fma_f16 v20, v47, v21, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v27, v21, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v35, v21, v25 op_sel_hi:[0,1,1]
v_lshl_or_b32 v41, v44, 16, v19
v_pk_fma_f16 v34, v43, v21, v26 op_sel_hi:[0,1,1]
v_fmac_f16_e32 v53, v73, v44
v_and_b32_sdwa v71, v52, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v57, v52, v49
v_pk_fma_f16 v56, v47, v41, v20 op_sel:[1,0,0]
ds_read2_b64 v[19:22], v4 offset0:2 offset1:7
v_pk_fma_f16 v58, v27, v41, v24 op_sel:[1,0,0]
v_pk_fma_f16 v59, v35, v41, v30 op_sel:[1,0,0]
v_pk_fma_f16 v60, v43, v41, v34 op_sel:[1,0,0]
ds_read2_b64 v[24:27], v4 offset0:12 offset1:17
ds_read_b128 v[30:33], v4 offset:176
ds_read2_b64 v[34:37], v4 offset0:27 offset1:28
v_pk_fma_f16 v23, v23, v41, v40 op_sel:[1,0,0]
v_lshl_or_b32 v72, v38, 16, v55
v_and_b32_sdwa v52, v52, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v62, v54, 16, v62
v_lshrrev_b32_e32 v54, 16, v39
v_lshl_or_b32 v39, v39, 16, v57
ds_read2_b64 v[40:43], v4 offset0:3 offset1:4
ds_read_b128 v[44:47], v4 offset:64
v_lshl_or_b32 v63, v63, 16, v52
v_lshl_or_b32 v61, v61, 16, v71
s_waitcnt lgkmcnt(5)
v_fmac_f16_e32 v18, v21, v48
v_fmac_f16_e32 v53, v21, v38
v_pk_fma_f16 v56, v19, v72, v56 op_sel_hi:[0,1,1]
ds_read2_b64 v[48:51], v4 offset0:13 offset1:14
v_lshl_or_b32 v38, v54, 16, v70
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v57, v26, v72, v59 op_sel_hi:[0,1,1]
v_pack_b32_f16 v18, v18, v53
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v23, v34, v72, v23 op_sel_hi:[0,1,1]
ds_read_b128 v[52:55], v4 offset:144
v_pk_fma_f16 v19, v19, v62, v56 op_sel:[1,0,0]
v_pk_fma_f16 v18, v21, v62, v18 op_sel:[1,0,0]
v_pk_fma_f16 v21, v24, v72, v58 op_sel_hi:[0,1,1]
v_pk_fma_f16 v58, v30, v72, v60 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v34, v62, v23 op_sel:[1,0,0]
v_pk_fma_f16 v19, v20, v39, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v22, v39, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v24, v62, v21 op_sel:[1,0,0]
v_pk_fma_f16 v24, v26, v62, v57 op_sel:[1,0,0]
v_pk_fma_f16 v26, v30, v62, v58 op_sel:[1,0,0]
v_pk_fma_f16 v23, v35, v39, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v22, v38, v18 op_sel:[1,0,0]
v_pk_fma_f16 v21, v25, v39, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v27, v39, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v31, v39, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v20, v38, v19 op_sel:[1,0,0]
v_pk_fma_f16 v23, v35, v38, v23 op_sel:[1,0,0]
v_pk_fma_f16 v20, v25, v38, v21 op_sel:[1,0,0]
v_pk_fma_f16 v21, v27, v38, v22 op_sel:[1,0,0]
v_pk_fma_f16 v22, v31, v38, v24 op_sel:[1,0,0]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v18, v44, v67, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v40, v67, v19 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v20, v48, v67, v20 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v21, v52, v67, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v32, v67, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v36, v67, v23 op_sel_hi:[0,1,1]
ds_read2_b64 v[56:59], v4 offset0:24 offset1:29
v_pk_fma_f16 v18, v44, v61, v18 op_sel:[1,0,0]
v_pk_fma_f16 v19, v40, v61, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v48, v61, v20 op_sel:[1,0,0]
v_pk_fma_f16 v21, v52, v61, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v32, v61, v22 op_sel:[1,0,0]
v_pk_fma_f16 v23, v36, v61, v23 op_sel:[1,0,0]
v_pk_fma_f16 v18, v45, v65, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v41, v65, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v49, v65, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v53, v65, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v33, v65, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v37, v65, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v45, v63, v18 op_sel:[1,0,0]
v_pk_fma_f16 v19, v41, v63, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v49, v63, v20 op_sel:[1,0,0]
v_pk_fma_f16 v21, v53, v63, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v33, v63, v22 op_sel:[1,0,0]
v_pk_fma_f16 v23, v37, v63, v23 op_sel:[1,0,0]
v_pk_fma_f16 v18, v46, v66, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v42, v66, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v50, v66, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v54, v66, v21 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v22, v56, v66, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v58, v66, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v46, v28, v18 op_sel:[1,0,0]
v_pk_fma_f16 v19, v42, v28, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v50, v28, v20 op_sel:[1,0,0]
v_pk_fma_f16 v21, v54, v28, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v56, v28, v22 op_sel:[1,0,0]
v_pk_fma_f16 v23, v58, v28, v23 op_sel:[1,0,0]
v_pk_fma_f16 v18, v47, v68, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v43, v68, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v55, v68, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v51, v68, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v57, v68, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v59, v68, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v43, v29, v19 op_sel:[1,0,0]
v_pk_fma_f16 v18, v47, v29, v18 op_sel:[1,0,0]
v_pk_fma_f16 v22, v51, v29, v20 op_sel:[1,0,0]
v_pk_fma_f16 v21, v55, v29, v21 op_sel:[1,0,0]
v_pk_fma_f16 v20, v57, v29, v24 op_sel:[1,0,0]
v_pk_fma_f16 v19, v59, v29, v25 op_sel:[1,0,0]
s_cbranch_scc1 BB27_4
BB27_2:
v_add_nc_u32_e32 v24, s5, v17
v_add_nc_u32_e32 v26, s5, v16
v_add_nc_u32_e32 v28, s5, v14
v_add_nc_u32_e32 v30, s5, v13
v_add_nc_u32_e32 v32, s5, v12
v_ashrrev_i32_e32 v25, 31, v24
v_ashrrev_i32_e32 v27, 31, v26
v_ashrrev_i32_e32 v29, 31, v28
v_ashrrev_i32_e32 v31, 31, v30
v_ashrrev_i32_e32 v33, 31, v32
v_lshlrev_b64 v[24:25], 1, v[24:25]
v_lshlrev_b64 v[26:27], 1, v[26:27]
v_lshlrev_b64 v[28:29], 1, v[28:29]
v_add_nc_u32_e32 v34, s5, v15
v_lshlrev_b64 v[30:31], 1, v[30:31]
v_lshlrev_b64 v[32:33], 1, v[32:33]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v24, s0, s8, v24
v_add_co_ci_u32_e64 v25, s0, s9, v25, s0
v_add_co_u32 v26, s0, s8, v26
v_ashrrev_i32_e32 v35, 31, v34
v_add_co_ci_u32_e64 v27, s0, s9, v27, s0
v_add_co_u32 v28, s0, s8, v28
v_add_co_ci_u32_e64 v29, s0, s9, v29, s0
v_add_co_u32 v30, s0, s8, v30
v_lshlrev_b64 v[34:35], 1, v[34:35]
v_add_co_ci_u32_e64 v31, s0, s9, v31, s0
v_add_co_u32 v32, s0, s8, v32
v_add_co_ci_u32_e64 v33, s0, s9, v33, s0
v_add_co_u32 v36, s0, 0x2000, v24
v_add_co_ci_u32_e64 v37, s0, 0, v25, s0
v_add_co_u32 v34, s0, s8, v34
v_add_co_ci_u32_e64 v35, s0, s9, v35, s0
s_clause 0x6
global_load_ushort v24, v[24:25], off
global_load_ushort v25, v[26:27], off
global_load_ushort v26, v[28:29], off
global_load_ushort v27, v[30:31], off
global_load_ushort v28, v[32:33], off
global_load_ushort v29, v[36:37], off offset:1408
global_load_ushort v30, v[34:35], off
s_waitcnt vmcnt(0)
s_barrier
ds_write_b16 v1, v24
ds_write_b16 v1, v25 offset:64
ds_write_b16 v1, v26 offset:128
ds_write_b16 v1, v27 offset:192
ds_write_b16 v1, v28 offset:256
ds_write_b16 v1, v29 offset:320
ds_write_b16 v1, v30 offset:384
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz BB27_1
v_add_nc_u32_e32 v24, s5, v11
v_ashrrev_i32_e32 v25, 31, v24
v_lshlrev_b64 v[24:25], 1, v[24:25]
v_add_co_u32 v24, s0, s8, v24
v_add_co_ci_u32_e64 v25, s0, s9, v25, s0
global_load_ushort v24, v[24:25], off
s_waitcnt vmcnt(0)
ds_write_b16 v1, v24 offset:448
s_branch BB27_1
BB27_4:
s_mulk_i32 s6, 0x180
v_lshlrev_b32_e32 v0, 1, v0
v_mad_u32_u24 v1, 0xc0, v3, s6
v_and_or_b32 v0, v0, 30, v1
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_dword v[0:1], v23, off
global_store_short v[0:1], v18, off offset:64
global_store_short_d16_hi v[0:1], v18, off offset:66
global_store_dword v[0:1], v22, off offset:128
global_store_dword v[0:1], v21, off offset:192
global_store_dword v[0:1], v20, off offset:256
global_store_dword v[0:1], v19, off offset:320
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_batch_matmul_kernel0
.amdhsa_group_segment_fixed_size 1760
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 75
.amdhsa_next_free_sgpr 13
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end27:
.size tvmgen_default_fused_nn_batch_matmul_kernel0, .Lfunc_end27-tvmgen_default_fused_nn_batch_matmul_kernel0
.globl tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel0
.p2align 8
.type tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel0,@function
tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel0:
s_mul_hi_i32 s0, s6, 0xae4c415d
s_add_i32 s0, s0, s6
s_lshr_b32 s1, s0, 31
s_ashr_i32 s2, s0, 6
s_ashr_i32 s0, s0, 5
s_add_i32 s2, s2, s1
s_add_i32 s0, s0, s1
s_mul_i32 s3, s2, 0x5e
s_mul_i32 s0, s0, 47
s_sub_i32 s3, s6, s3
s_bfe_i32 s1, s3, 0x80000
s_sub_i32 s3, s6, s0
v_mul_lo_u16 v1, s1, 11
s_mul_i32 s1, s2, 47
s_add_i32 s8, s1, s3
v_lshrrev_b16 v2, 15, v1
v_ashrrev_i16 v1, 9, v1
s_mul_hi_i32 s0, s8, 0x51eb851f
s_lshr_b32 s1, s0, 31
s_ashr_i32 s0, s0, 4
v_add_nc_u16 v1, v1, v2
v_mov_b32_e32 v2, 6
s_add_i32 s9, s0, s1
s_clause 0x1
s_load_dwordx2 s[6:7], s[4:5], 0x0
s_load_dwordx2 s[0:1], s[4:5], 0x8
s_mul_i32 s4, s9, 50
v_lshlrev_b32_sdwa v2, v2, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
s_sub_i32 s4, s8, s4
s_lshl_b32 s8, s9, 1
s_lshl_b32 s5, s4, 8
s_lshl_b32 s4, s4, 1
v_add_nc_u32_e32 v1, s5, v2
s_mul_i32 s5, s9, 0x6400
s_add_i32 s9, s8, -1
v_add_nc_u32_e32 v1, s5, v1
s_add_i32 s5, s4, -1
s_cmpk_gt_u32 s9, 0x5d
v_add3_u32 v8, v0, v1, 0xffffcd80
s_cbranch_scc1 BB28_20
v_ashrrev_i32_e32 v9, 31, v8
v_mov_b32_e32 v1, 0
s_cmpk_gt_u32 s5, 0x63
v_lshlrev_b64 v[3:4], 1, v[8:9]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v4, vcc_lo
v_mov_b32_e32 v4, 0
s_cbranch_scc0 BB28_24
v_cmp_gt_u32_e64 s9, 0x64, s4
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz BB28_25
BB28_3:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v5, 0
s_andn2_b32 vcc_lo, exec_lo, s9
s_cbranch_vccz BB28_26
BB28_4:
s_add_i32 s9, s4, 2
s_cmpk_gt_u32 s9, 0x63
s_cbranch_scc0 BB28_27
BB28_5:
v_cmp_gt_u32_e64 s9, 0x5e, s8
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccz BB28_21
BB28_6:
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v6, 0
s_movk_i32 s11, 0x63
s_cmp_gt_u32 s5, s11
s_cbranch_scc0 BB28_28
v_cmp_gt_u32_e64 s10, 0x64, s4
s_cmp_gt_u32 s4, s11
s_cbranch_scc0 BB28_29
BB28_8:
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v10, 0
s_andn2_b32 vcc_lo, exec_lo, s10
s_cbranch_vccz BB28_30
BB28_9:
s_add_i32 s10, s4, 2
s_cmpk_gt_u32 s10, 0x63
s_cbranch_scc0 BB28_31
BB28_10:
s_andn2_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz BB28_22
BB28_11:
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v12, 0
s_movk_i32 s10, 0x63
s_cmp_gt_u32 s5, s10
s_cbranch_scc0 BB28_32
v_cmp_gt_u32_e64 s9, 0x64, s4
s_cmp_gt_u32 s4, s10
s_cbranch_scc0 BB28_33
BB28_13:
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v14, 0
s_andn2_b32 vcc_lo, exec_lo, s9
s_cbranch_vccz BB28_34
BB28_14:
s_add_i32 s9, s4, 2
s_cmpk_gt_u32 s9, 0x63
s_cbranch_scc0 BB28_35
BB28_15:
s_add_i32 s8, s8, 2
s_cmpk_gt_u32 s8, 0x5d
s_cbranch_scc1 BB28_23
BB28_16:
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v16, 0
s_movk_i32 s8, 0x63
s_cmp_gt_u32 s5, s8
s_cbranch_scc0 BB28_36
v_cmp_gt_u32_e64 s5, 0x64, s4
s_cmp_gt_u32 s4, s8
s_cbranch_scc0 BB28_37
BB28_18:
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v18, 0
s_andn2_b32 vcc_lo, exec_lo, s5
s_cbranch_vccz BB28_38
BB28_19:
s_add_i32 s4, s4, 2
s_cmpk_gt_u32 s4, 0x63
s_cbranch_scc0 BB28_39
s_branch BB28_40
BB28_20:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v4, 0
v_cmp_gt_u32_e64 s9, 0x5e, s8
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz BB28_6
BB28_21:
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v6, 0
s_andn2_b32 vcc_lo, exec_lo, s9
s_cbranch_vccz BB28_11
BB28_22:
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v12, 0
s_add_i32 s8, s8, 2
s_cmpk_gt_u32 s8, 0x5d
s_cbranch_scc0 BB28_16
BB28_23:
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v16, 0
s_branch BB28_40
BB28_24:
global_load_ushort v4, v[6:7], off
v_cmp_gt_u32_e64 s9, 0x64, s4
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccz BB28_3
BB28_25:
global_load_ushort v1, v[6:7], off offset:256
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v5, 0
s_andn2_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz BB28_4
BB28_26:
global_load_ushort v5, v[6:7], off offset:512
s_add_i32 s9, s4, 2
s_cmpk_gt_u32 s9, 0x63
s_cbranch_scc1 BB28_5
BB28_27:
global_load_ushort v3, v[6:7], off offset:768
v_cmp_gt_u32_e64 s9, 0x5e, s8
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz BB28_6
s_branch BB28_21
BB28_28:
v_add_nc_u32_e32 v6, 0x3200, v8
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 1, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_ushort v6, v[6:7], off
v_cmp_gt_u32_e64 s10, 0x64, s4
s_cmp_gt_u32 s4, s11
s_cbranch_scc1 BB28_8
BB28_29:
v_add_nc_u32_e32 v9, 0x3280, v8
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 1, v[9:10]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_ushort v9, v[9:10], off
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v10, 0
s_andn2_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz BB28_9
BB28_30:
v_add_nc_u32_e32 v10, 0x3300, v8
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 1, v[10:11]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
global_load_ushort v10, v[10:11], off
s_add_i32 s10, s4, 2
s_cmpk_gt_u32 s10, 0x63
s_cbranch_scc1 BB28_10
BB28_31:
v_add_nc_u32_e32 v11, 0x3380, v8
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 1, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_ushort v7, v[11:12], off
s_andn2_b32 vcc_lo, exec_lo, s9
s_cbranch_vccz BB28_11
s_branch BB28_22
BB28_32:
v_add_nc_u32_e32 v12, 0x6400, v8
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 1, v[12:13]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
global_load_ushort v12, v[12:13], off
v_cmp_gt_u32_e64 s9, 0x64, s4
s_cmp_gt_u32 s4, s10
s_cbranch_scc1 BB28_13
BB28_33:
v_add_nc_u32_e32 v13, 0x6480, v8
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 1, v[13:14]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, vcc_lo, s6, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
global_load_ushort v11, v[13:14], off
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v14, 0
s_andn2_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz BB28_14
BB28_34:
v_add_nc_u32_e32 v14, 0x6500, v8
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[14:15], 1, v[14:15]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v14, vcc_lo, s6, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
global_load_ushort v14, v[14:15], off
s_add_i32 s9, s4, 2
s_cmpk_gt_u32 s9, 0x63
s_cbranch_scc1 BB28_15
BB28_35:
v_add_nc_u32_e32 v15, 0x6580, v8
v_ashrrev_i32_e32 v16, 31, v15
v_lshlrev_b64 v[15:16], 1, v[15:16]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v15, vcc_lo, s6, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s7, v16, vcc_lo
global_load_ushort v13, v[15:16], off
s_add_i32 s8, s8, 2
s_cmpk_gt_u32 s8, 0x5d
s_cbranch_scc0 BB28_16
s_branch BB28_23
BB28_36:
v_add_nc_u32_e32 v16, 0x9600, v8
v_ashrrev_i32_e32 v17, 31, v16
v_lshlrev_b64 v[16:17], 1, v[16:17]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v16, vcc_lo, s6, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s7, v17, vcc_lo
global_load_ushort v16, v[16:17], off
v_cmp_gt_u32_e64 s5, 0x64, s4
s_cmp_gt_u32 s4, s8
s_cbranch_scc1 BB28_18
BB28_37:
v_add_nc_u32_e32 v17, 0x9680, v8
v_ashrrev_i32_e32 v18, 31, v17
v_lshlrev_b64 v[17:18], 1, v[17:18]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v17, vcc_lo, s6, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s7, v18, vcc_lo
global_load_ushort v15, v[17:18], off
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v18, 0
s_andn2_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz BB28_19
BB28_38:
v_add_nc_u32_e32 v18, 0x9700, v8
v_ashrrev_i32_e32 v19, 31, v18
v_lshlrev_b64 v[18:19], 1, v[18:19]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v18, vcc_lo, s6, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo
global_load_ushort v18, v[18:19], off
s_add_i32 s4, s4, 2
s_cmpk_gt_u32 s4, 0x63
s_cbranch_scc1 BB28_40
BB28_39:
v_add_nc_u32_e32 v19, 0x9780, v8
v_ashrrev_i32_e32 v20, 31, v19
v_lshlrev_b64 v[19:20], 1, v[19:20]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v19, vcc_lo, s6, v19
v_add_co_ci_u32_e32 v20, vcc_lo, s7, v20, vcc_lo
global_load_ushort v17, v[19:20], off
BB28_40:
s_mulk_i32 s2, 0x1780
s_waitcnt vmcnt(0)
v_add_f16_e32 v8, 0, v1
v_add_nc_u32_e32 v2, s2, v2
s_lshl_b32 s2, s3, 7
v_add_f16_e32 v4, 0, v4
v_sub_f16_e32 v20, 0, v6
v_sub_f16_e32 v24, 0, v9
v_add3_u32 v0, v2, s2, v0
v_sub_f16_e32 v2, 0, v1
v_sub_f16_e32 v4, v4, v5
v_add_f16_e32 v6, 0, v6
v_ashrrev_i32_e32 v1, 31, v0
v_add_f16_e32 v19, v5, v2
v_add_f16_e32 v5, v5, v8
v_add_f16_e32 v8, v2, v3
v_sub_f16_e32 v4, v4, v12
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_add_f16_e32 v2, v19, v11
v_sub_f16_e32 v5, v5, v11
v_add_f16_e32 v8, v8, v11
v_add_f16_e32 v4, v4, v14
v_sub_f16_e32 v6, v6, v10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_sub_f16_e32 v19, v2, v14
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_sub_f16_e32 v21, v5, v14
v_sub_f16_e32 v8, v8, v13
v_add_co_u32 v2, vcc_lo, 0x92800, v0
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
global_store_short v[0:1], v4, off
global_store_short v[2:3], v19, off offset:1536
v_add_f16_e32 v19, v20, v10
v_add_co_u32 v2, vcc_lo, 0x125800, v0
v_add_f16_e32 v20, 0, v9
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, 0x1b8800, v0
v_add_f16_e32 v22, v12, v19
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_sub_f16_e32 v23, v20, v10
v_sub_f16_e32 v27, v20, v7
global_store_short v[2:3], v21, off offset:1024
global_store_short v[4:5], v8, off offset:512
v_sub_f16_e32 v21, v22, v14
v_sub_f16_e32 v22, v24, v10
v_sub_f16_e32 v4, v23, v11
v_add_co_u32 v2, vcc_lo, 0x24b800, v0
v_sub_f16_e32 v28, v27, v11
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v8, v11, v22
v_add_f16_e32 v25, v14, v4
v_add_co_u32 v4, vcc_lo, 0x2de000, v0
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v26, v14, v8
v_add_co_u32 v8, vcc_lo, 0x371000, v0
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo
global_store_short v[2:3], v21, off
global_store_short v[4:5], v25, off offset:1536
global_store_short v[8:9], v26, off offset:1024
v_add_f16_e32 v5, v10, v24
v_add_f16_e32 v4, v12, v6
v_add_f16_e32 v8, v10, v20
v_add_co_u32 v2, vcc_lo, 0x404000, v0
v_add_f16_e32 v21, v13, v28
v_sub_f16_e32 v6, v5, v11
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
v_sub_f16_e32 v12, v4, v14
v_add_co_u32 v4, vcc_lo, 0x497000, v0
v_add_f16_e32 v20, v24, v7
v_add_f16_e32 v10, v14, v6
v_add_f16_e32 v6, v11, v8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, 0x529800, v0
v_sub_f16_e32 v11, v20, v11
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v14, v14, v6
v_add_co_u32 v6, vcc_lo, 0x5bc800, v0
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
global_store_short v[2:3], v21, off offset:512
global_store_short v[4:5], v12, off
global_store_short v[8:9], v10, off offset:1536
global_store_short v[6:7], v14, off offset:1024
v_add_f16_e32 v4, v19, v16
v_add_co_u32 v2, vcc_lo, 0x64f800, v0
v_sub_f16_e32 v6, v23, v15
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v10, v13, v11
v_sub_f16_e32 v11, v4, v18
v_add_co_u32 v4, vcc_lo, 0x6e2800, v0
v_add_f16_e32 v8, v22, v15
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v12, v18, v6
v_add_co_u32 v6, vcc_lo, 0x775000, v0
v_sub_f16_e32 v14, v27, v15
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v13, v18, v8
v_add_co_u32 v8, vcc_lo, 0x808000, v0
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, 0x89b000, v0
v_add_f16_e32 v14, v14, v17
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
global_store_short v[2:3], v10, off offset:512
global_store_short v[4:5], v11, off
global_store_short v[6:7], v12, off offset:1536
global_store_short v[8:9], v13, off offset:1024
global_store_short v[0:1], v14, off offset:512
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 29
.amdhsa_next_free_sgpr 12
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end28:
.size tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel0, .Lfunc_end28-tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel0
.globl tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel1
.p2align 8
.type tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel1,@function
tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel1:
s_mul_hi_i32 s0, s6, 0xae4c415d
s_lshl_b32 s2, s6, 13
s_add_i32 s0, s0, s6
s_clause 0x1
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_lshr_b32 s1, s0, 31
s_lshr_b32 s0, s0, 6
v_lshrrev_b32_e32 v6, 4, v0
s_add_i32 s0, s0, s1
s_and_b32 s1, s2, 0x2000
s_lshl_b32 s0, s0, 14
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_or_b32 s0, s0, s1
v_and_b32_e32 v3, 7, v0
v_lshl_add_u32 v1, v0, 7, s0
v_lshlrev_b32_e32 v7, 4, v0
v_mul_u32_u24_e32 v5, 0x50, v6
v_lshlrev_b32_e32 v4, 5, v0
s_ashr_i32 s1, s6, 1
v_ashrrev_i32_e32 v2, 31, v1
v_and_or_b32 v3, 0x3f80, v7, v3
s_movk_i32 s0, 0x400
s_mulk_i32 s1, 0x1900
v_lshl_add_u32 v13, v5, 1, s0
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_lshl_add_u32 v10, v0, 1, s0
v_and_b32_e32 v12, 0x1e0, v4
v_add_nc_u32_e32 v18, s1, v3
v_cmp_gt_i32_e32 vcc_lo, 64, v0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v14, s0, s10, v1
v_mov_b32_e32 v1, 0
v_add_co_ci_u32_e64 v15, s0, s11, v2, s0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v28, 0
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v24, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v20, 0
s_mov_b32 s4, 0
s_branch BB29_2
BB29_1:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_barrier
ds_read_b128 v[29:32], v12 offset:16
ds_read_b128 v[33:36], v12
ds_read_b128 v[37:40], v12 offset:528
ds_read_b128 v[41:44], v12 offset:512
ds_read_b128 v[45:48], v13
ds_read_b128 v[49:52], v13 offset:16
v_mov_b32_e32 v53, 0xffff
v_add_co_u32 v14, s0, v14, 16
s_add_i32 s4, s4, 8
v_add_co_ci_u32_e64 v15, s0, 0, v15, s0
s_cmpk_eq_i32 s4, 0x80
s_waitcnt lgkmcnt(5)
v_lshrrev_b32_e32 v54, 16, v29
s_waitcnt lgkmcnt(4)
v_and_b32_e32 v58, v53, v33
v_and_b32_sdwa v33, v53, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
s_waitcnt lgkmcnt(2)
v_and_b32_e32 v60, v53, v41
v_lshrrev_b32_e32 v59, 16, v37
v_and_b32_sdwa v41, v53, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v58, v29, 16, v58
v_and_b32_e32 v61, v53, v34
v_lshl_or_b32 v60, v37, 16, v60
v_and_b32_e32 v65, v53, v42
v_lshl_or_b32 v59, v59, 16, v41
v_lshl_or_b32 v54, v54, 16, v33
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v11, v45, v58, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v45, v60, v16 op_sel_hi:[0,1,1]
v_lshrrev_b32_e32 v55, 16, v30
v_lshl_or_b32 v61, v30, 16, v61
v_lshrrev_b32_e32 v64, 16, v38
v_pk_fma_f16 v11, v45, v54, v11 op_sel:[1,0,0]
v_lshl_or_b32 v65, v38, 16, v65
v_pk_fma_f16 v16, v45, v59, v16 op_sel:[1,0,0]
v_and_b32_sdwa v34, v53, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v42, v53, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v62, v53, v35
v_and_b32_e32 v29, v53, v43
v_pk_fma_f16 v11, v46, v61, v11 op_sel_hi:[0,1,1]
v_lshl_or_b32 v45, v55, 16, v34
v_lshl_or_b32 v55, v64, 16, v42
v_pk_fma_f16 v16, v46, v65, v16 op_sel_hi:[0,1,1]
v_and_b32_e32 v30, v53, v44
v_lshrrev_b32_e32 v56, 16, v31
v_lshl_or_b32 v62, v31, 16, v62
v_pk_fma_f16 v11, v46, v45, v11 op_sel:[1,0,0]
v_lshrrev_b32_e32 v37, 16, v39
v_lshl_or_b32 v64, v39, 16, v29
v_pk_fma_f16 v16, v46, v55, v16 op_sel:[1,0,0]
v_and_b32_sdwa v39, v53, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v41, v53, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v63, v53, v36
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v19, v49, v58, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v49, v60, v20 op_sel_hi:[0,1,1]
v_lshl_or_b32 v46, v56, 16, v39
v_pk_fma_f16 v11, v47, v62, v11 op_sel_hi:[0,1,1]
v_lshl_or_b32 v56, v37, 16, v41
v_pk_fma_f16 v16, v47, v64, v16 op_sel_hi:[0,1,1]
v_and_b32_sdwa v37, v53, v44 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v57, 16, v32
v_lshl_or_b32 v66, v40, 16, v30
v_lshrrev_b32_e32 v38, 16, v40
v_and_b32_sdwa v40, v53, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
ds_read_b128 v[33:36], v13 offset:48
v_pk_fma_f16 v16, v47, v56, v16 op_sel:[1,0,0]
v_pk_fma_f16 v19, v49, v54, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v49, v59, v20 op_sel:[1,0,0]
v_lshl_or_b32 v63, v32, 16, v63
v_pk_fma_f16 v11, v47, v46, v11 op_sel:[1,0,0]
ds_read_b128 v[29:32], v13 offset:32
v_lshl_or_b32 v47, v57, 16, v40
v_lshl_or_b32 v49, v38, 16, v37
ds_read_b128 v[37:40], v13 offset:64
ds_read_b128 v[41:44], v13 offset:80
v_pk_fma_f16 v11, v48, v63, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v48, v66, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v50, v61, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v50, v65, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v48, v47, v11 op_sel:[1,0,0]
v_pk_fma_f16 v16, v48, v49, v16 op_sel:[1,0,0]
v_pk_fma_f16 v19, v50, v45, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v50, v55, v20 op_sel:[1,0,0]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v26, v33, v58, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v33, v60, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v51, v62, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v51, v64, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v33, v54, v26 op_sel:[1,0,0]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v24, v29, v58, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v29, v60, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v33, v59, v25 op_sel:[1,0,0]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v22, v37, v58, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v37, v60, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v29, v54, v24 op_sel:[1,0,0]
v_pk_fma_f16 v21, v29, v59, v21 op_sel:[1,0,0]
v_pk_fma_f16 v26, v34, v61, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v34, v65, v25 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v27, v41, v58, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v37, v54, v22 op_sel:[1,0,0]
v_pk_fma_f16 v23, v37, v59, v23 op_sel:[1,0,0]
v_pk_fma_f16 v24, v30, v61, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v30, v65, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v34, v45, v26 op_sel:[1,0,0]
v_pk_fma_f16 v28, v41, v60, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v34, v55, v25 op_sel:[1,0,0]
v_pk_fma_f16 v27, v41, v54, v27 op_sel:[1,0,0]
v_pk_fma_f16 v22, v38, v61, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v38, v65, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v30, v45, v24 op_sel:[1,0,0]
v_pk_fma_f16 v21, v30, v55, v21 op_sel:[1,0,0]
v_pk_fma_f16 v26, v35, v62, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v38, v45, v22 op_sel:[1,0,0]
v_pk_fma_f16 v23, v38, v55, v23 op_sel:[1,0,0]
v_pk_fma_f16 v25, v35, v64, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v41, v59, v28 op_sel:[1,0,0]
v_pk_fma_f16 v27, v42, v61, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v31, v62, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v31, v64, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v35, v46, v26 op_sel:[1,0,0]
v_pk_fma_f16 v25, v35, v56, v25 op_sel:[1,0,0]
v_pk_fma_f16 v22, v39, v62, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v39, v64, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v42, v65, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v42, v45, v27 op_sel:[1,0,0]
v_pk_fma_f16 v24, v31, v46, v24 op_sel:[1,0,0]
v_pk_fma_f16 v21, v31, v56, v21 op_sel:[1,0,0]
v_pk_fma_f16 v26, v36, v63, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v42, v55, v37 op_sel:[1,0,0]
v_pk_fma_f16 v25, v36, v66, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v39, v46, v22 op_sel:[1,0,0]
v_pk_fma_f16 v23, v39, v56, v23 op_sel:[1,0,0]
v_pk_fma_f16 v37, v43, v62, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v32, v63, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v32, v66, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v40, v63, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v40, v66, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v36, v47, v26 op_sel:[1,0,0]
v_pk_fma_f16 v25, v36, v49, v25 op_sel:[1,0,0]
v_pk_fma_f16 v36, v43, v46, v37 op_sel:[1,0,0]
v_pk_fma_f16 v35, v43, v64, v35 op_sel_hi:[0,1,1]
ds_read2_b64 v[27:30], v13 offset0:12 offset1:13
v_pk_fma_f16 v24, v32, v47, v24 op_sel:[1,0,0]
v_pk_fma_f16 v21, v32, v49, v21 op_sel:[1,0,0]
ds_read2_b64 v[31:34], v13 offset0:14 offset1:15
v_pk_fma_f16 v43, v43, v56, v35 op_sel:[1,0,0]
v_pk_fma_f16 v48, v44, v63, v36 op_sel_hi:[0,1,1]
ds_read2_b64 v[35:38], v13 offset0:16 offset1:17
v_pk_fma_f16 v22, v40, v47, v22 op_sel:[1,0,0]
v_pk_fma_f16 v23, v40, v49, v23 op_sel:[1,0,0]
ds_read2_b64 v[39:42], v13 offset0:18 offset1:19
v_pk_fma_f16 v19, v51, v46, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v51, v56, v20 op_sel:[1,0,0]
v_pk_fma_f16 v19, v52, v63, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v52, v66, v20 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v17, v27, v58, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v27, v60, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v52, v47, v19 op_sel:[1,0,0]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v8, v31, v58, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v31, v60, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v27, v54, v17 op_sel:[1,0,0]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v4, v35, v58, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v35, v60, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v27, v59, v9 op_sel:[1,0,0]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v2, v39, v58, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v39, v60, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v31, v54, v8 op_sel:[1,0,0]
v_pk_fma_f16 v5, v31, v59, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v35, v54, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v35, v59, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v39, v54, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v39, v59, v1 op_sel:[1,0,0]
v_pk_fma_f16 v17, v28, v61, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v28, v65, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v32, v61, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v32, v65, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v36, v61, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v36, v65, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v40, v61, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v40, v65, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v28, v45, v17 op_sel:[1,0,0]
v_pk_fma_f16 v9, v28, v55, v9 op_sel:[1,0,0]
v_pk_fma_f16 v8, v32, v45, v8 op_sel:[1,0,0]
v_pk_fma_f16 v5, v32, v55, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v36, v45, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v36, v55, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v40, v45, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v40, v55, v1 op_sel:[1,0,0]
v_pk_fma_f16 v17, v29, v62, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v29, v64, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v33, v62, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v33, v64, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v37, v62, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v37, v64, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v41, v62, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v41, v64, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v29, v46, v17 op_sel:[1,0,0]
v_pk_fma_f16 v9, v29, v56, v9 op_sel:[1,0,0]
v_pk_fma_f16 v8, v33, v46, v8 op_sel:[1,0,0]
v_pk_fma_f16 v5, v33, v56, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v37, v46, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v37, v56, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v41, v46, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v41, v56, v1 op_sel:[1,0,0]
v_pk_fma_f16 v17, v30, v63, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v30, v66, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v34, v63, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v34, v66, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v38, v63, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v38, v66, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v42, v63, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v42, v66, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v44, v66, v43 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v52, v49, v20 op_sel:[1,0,0]
v_pk_fma_f16 v27, v44, v47, v48 op_sel:[1,0,0]
v_pk_fma_f16 v17, v30, v47, v17 op_sel:[1,0,0]
v_pk_fma_f16 v9, v30, v49, v9 op_sel:[1,0,0]
v_pk_fma_f16 v28, v44, v49, v31 op_sel:[1,0,0]
v_pk_fma_f16 v8, v34, v47, v8 op_sel:[1,0,0]
v_pk_fma_f16 v5, v34, v49, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v38, v47, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v38, v49, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v42, v47, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v42, v49, v1 op_sel:[1,0,0]
s_cbranch_scc1 BB29_4
BB29_2:
v_add_nc_u32_e32 v29, s4, v18
v_ashrrev_i32_e32 v30, 31, v29
v_lshlrev_b64 v[29:30], 1, v[29:30]
v_add_co_u32 v29, s0, s8, v29
v_add_co_ci_u32_e64 v30, s0, s9, v30, s0
v_add_co_u32 v31, s0, 0x800, v29
v_add_co_ci_u32_e64 v32, s0, 0, v30, s0
v_add_co_u32 v33, s0, 0x1000, v29
v_add_co_ci_u32_e64 v34, s0, 0, v30, s0
v_add_co_u32 v35, s0, 0x1800, v29
v_add_co_ci_u32_e64 v36, s0, 0, v30, s0
v_add_co_u32 v37, s0, 0x2800, v29
v_add_co_ci_u32_e64 v38, s0, 0, v30, s0
s_clause 0x4
global_load_ushort v29, v[29:30], off
global_load_ushort v30, v[31:32], off offset:512
global_load_ushort v31, v[33:34], off offset:1024
global_load_ushort v32, v[35:36], off offset:1536
global_load_ushort v33, v[37:38], off
s_waitcnt vmcnt(0)
s_barrier
ds_write_b16 v10, v29
ds_write_b16 v10, v30 offset:160
ds_write_b16 v10, v31 offset:320
ds_write_b16 v10, v32 offset:480
ds_write_b16 v10, v33 offset:640
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB29_1
global_load_dwordx4 v[29:32], v[14:15], off
s_waitcnt vmcnt(0)
ds_write_b128 v7, v[29:32]
s_branch BB29_1
BB29_4:
v_lshlrev_b32_e32 v0, 1, v0
v_mad_u32_u24 v6, 0x500, v6, s1
s_lshl_b32 s0, s6, 6
s_and_b32 s0, s0, 64
v_and_b32_e32 v0, 30, v0
v_or3_b32 v6, v6, s0, v0
v_ashrrev_i32_e32 v7, 31, v6
v_add_nc_u32_e32 v14, 0x400, v6
v_add_nc_u32_e32 v29, 0x420, v6
v_lshlrev_b64 v[12:13], 1, v[6:7]
v_add_nc_u32_e32 v7, 0x480, v6
v_ashrrev_i32_e32 v15, 31, v14
v_ashrrev_i32_e32 v30, 31, v29
v_add_nc_u32_e32 v6, 0x4a0, v6
v_add_co_u32 v12, vcc_lo, s2, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
global_store_short v[12:13], v16, off offset:64
global_store_dword v[12:13], v11, off
global_store_short_d16_hi v[12:13], v16, off offset:66
global_store_short v[12:13], v19, off offset:256
global_store_short v[12:13], v20, off offset:320
global_store_short_d16_hi v[12:13], v19, off offset:258
global_store_short_d16_hi v[12:13], v20, off offset:322
global_store_dword v[12:13], v24, off offset:512
global_store_dword v[12:13], v21, off offset:576
global_store_dword v[12:13], v26, off offset:768
global_store_dword v[12:13], v25, off offset:832
global_store_dword v[12:13], v22, off offset:1024
global_store_dword v[12:13], v23, off offset:1088
global_store_dword v[12:13], v27, off offset:1280
global_store_dword v[12:13], v28, off offset:1344
global_store_dword v[12:13], v17, off offset:1536
global_store_dword v[12:13], v8, off offset:1792
v_ashrrev_i32_e32 v8, 31, v7
global_store_dword v[12:13], v9, off offset:1600
v_lshlrev_b64 v[9:10], 1, v[14:15]
v_lshlrev_b64 v[14:15], 1, v[29:30]
v_lshlrev_b64 v[16:17], 1, v[7:8]
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
v_add_co_u32 v14, vcc_lo, s2, v14
v_lshlrev_b64 v[6:7], 1, v[6:7]
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
v_add_co_u32 v16, vcc_lo, s2, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_store_dword v[12:13], v5, off offset:1856
global_store_dword v[9:10], v4, off
global_store_dword v[14:15], v3, off
global_store_dword v[16:17], v2, off
global_store_dword v[6:7], v1, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel1
.amdhsa_group_segment_fixed_size 1824
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 67
.amdhsa_next_free_sgpr 12
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end29:
.size tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel1, .Lfunc_end29-tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel1
.globl tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel2
.p2align 8
.type tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel2,@function
tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel2:
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_lshl_add_u32 v0, s6, 5, v0
s_mov_b32 s2, 0x92800
s_mov_b32 s3, 0x125800
s_mov_b32 s6, 0x1b8800
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s3, v2
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, 0x24b800, v2
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v10, vcc_lo, 0x2de000, v2
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v3, vcc_lo
s_clause 0x4
global_load_ushort v14, v[2:3], off
global_load_ushort v15, v[4:5], off offset:1536
global_load_ushort v16, v[6:7], off offset:1024
global_load_ushort v17, v[8:9], off
global_load_ushort v18, v[10:11], off offset:1536
v_add_co_u32 v4, vcc_lo, 0x371000, v2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, 0x497000, v2
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, 0x529800, v2
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v10, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v12, vcc_lo, 0x404000, v2
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v3, vcc_lo
s_clause 0x4
global_load_ushort v19, v[4:5], off offset:1024
global_load_ushort v20, v[6:7], off
global_load_ushort v8, v[8:9], off offset:1536
global_load_ushort v9, v[10:11], off offset:512
global_load_ushort v10, v[12:13], off offset:512
v_add_co_u32 v4, vcc_lo, 0x5bc800, v2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, 0x64f800, v2
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
s_clause 0x1
global_load_ushort v11, v[4:5], off offset:1024
global_load_ushort v12, v[6:7], off offset:512
v_add_co_u32 v4, vcc_lo, 0x6e2800, v2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, 0x775000, v2
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
s_clause 0x1
global_load_ushort v13, v[4:5], off
global_load_ushort v6, v[6:7], off offset:1536
v_add_co_u32 v4, vcc_lo, 0x808000, v2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, 0x89b000, v2
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_ushort v21, v[4:5], off offset:1024
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_ushort v22, v[2:3], off offset:512
s_waitcnt vmcnt(15)
v_add_f16_e32 v2, 0, v14
s_waitcnt vmcnt(14)
v_sub_f16_e32 v3, 0, v15
s_waitcnt vmcnt(12)
v_sub_f16_e32 v4, 0, v17
s_waitcnt vmcnt(11)
v_add_f16_e32 v5, 0, v18
v_add_f16_e32 v2, v2, v15
v_add_f16_e32 v3, v3, v16
v_sub_f16_e32 v4, v4, v18
v_add_f16_e32 v2, v2, v16
v_add_f16_e32 v2, v2, v17
s_waitcnt vmcnt(10)
v_sub_f16_e32 v5, v5, v19
v_sub_f16_e32 v4, v4, v19
s_waitcnt vmcnt(7)
v_add_f16_e32 v3, v3, v9
v_add_f16_e32 v2, v2, v18
s_waitcnt vmcnt(6)
v_sub_f16_e32 v5, v5, v10
v_add_f16_e32 v4, v4, v20
v_sub_f16_e32 v3, v3, v18
v_add_f16_e32 v7, v2, v19
v_sub_f16_e32 v5, v5, v8
v_add_f16_e32 v4, v4, v8
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_f16_e32 v3, v19, v3
v_add_f16_e32 v7, v7, v20
s_waitcnt vmcnt(5)
v_add_f16_e32 v5, v11, v5
v_add_f16_e32 v4, v4, v11
v_add_f16_e32 v9, v10, v3
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
s_waitcnt vmcnt(4)
v_add_f16_e32 v5, v12, v5
v_sub_f16_e32 v9, v9, v8
s_waitcnt vmcnt(3)
v_add_f16_e32 v10, v4, v13
s_waitcnt vmcnt(2)
v_sub_f16_e32 v13, v5, v6
v_add_f16_e32 v8, v7, v8
v_add_co_u32 v4, vcc_lo, s3, v0
v_add_f16_e32 v9, v11, v9
v_add_f16_e32 v10, v10, v6
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v8, v8, v11
s_waitcnt vmcnt(1)
v_add_f16_e32 v13, v13, v21
v_add_co_u32 v6, vcc_lo, s6, v0
v_add_f16_e32 v9, v12, v9
v_add_f16_e32 v10, v10, v21
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f16_e32 v11, v13, v22
global_store_short v[0:1], v8, off
global_store_short v[2:3], v9, off offset:1536
global_store_short v[4:5], v10, off offset:1024
global_store_short v[6:7], v11, off offset:512
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel2
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end30:
.size tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel2, .Lfunc_end30-tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel2
.globl tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel3
.p2align 8
.type tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel3,@function
tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel3:
v_lshl_add_u32 v0, s6, 6, v0
v_mov_b32_e32 v5, 0x147b
v_mov_b32_e32 v6, 0x92e00
s_clause 0x1
s_load_dwordx2 s[0:1], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
v_mul_hi_i32 v1, 0x51eb851f, v0
v_bfe_u32 v7, v0, 7, 1
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v3, 13, v1
v_ashrrev_i32_e32 v1, 12, v1
v_add_nc_u32_e32 v3, v3, v2
v_add_nc_u32_e32 v1, v1, v2
v_mul_i32_i24_e32 v4, 0x6400, v3
v_mul_i32_i24_e32 v1, 0x3200, v1
v_mul_i32_i24_e32 v3, 0x1900, v3
v_sub_nc_u32_e32 v2, v0, v4
v_sub_nc_u32_e32 v1, v0, v1
v_and_b32_e32 v4, 0x7f, v0
v_mul_i32_i24_sdwa v2, sext(v2), v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
v_ashrrev_i32_e32 v1, 1, v1
v_or_b32_e32 v3, v3, v4
v_lshrrev_b32_e32 v5, 31, v2
v_ashrrev_i32_e32 v2, 26, v2
v_mad_u32_u24 v3, 0x49700, v7, v3
v_and_b32_e32 v1, 0xffffff80, v1
v_add_nc_u16 v2, v2, v5
v_mul_i32_i24_sdwa v2, sext(v2), v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
v_add3_u32 v1, v3, v1, v2
v_lshlrev_b32_e32 v3, 1, v4
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
global_load_ushort v3, v3, s[2:3]
global_load_ushort v2, v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f16_e32 v2, v3, v2
v_max_f16_e32 v2, 0, v2
global_store_short v[0:1], v2, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel3
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end31:
.size tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel3, .Lfunc_end31-tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel3
.globl tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel0
.p2align 8
.type tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel0,@function
tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel0:
v_lshl_add_u32 v0, s6, 6, v0
s_load_dwordx2 s[6:7], s[4:5], 0x0
v_mul_hi_i32 v1, 0x51eb851f, v0
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v1, 11, v1
v_add_nc_u32_e32 v1, v1, v2
v_mul_i32_i24_e32 v2, 0x1900, v1
v_mul_i32_i24_e32 v3, 0x6400, v1
v_lshlrev_b32_e32 v10, 1, v1
v_sub_nc_u32_e32 v2, v0, v2
v_and_or_b32 v3, 0xff, v0, v3
v_add_nc_u32_e32 v6, -1, v10
v_ashrrev_i32_e32 v2, 8, v2
v_cmp_gt_u32_e64 s2, 47, v6
v_lshlrev_b32_e32 v4, 9, v2
v_add3_u32 v4, v3, v4, 0xffffcd00
v_lshlrev_b32_e32 v3, 1, v2
v_ashrrev_i32_e32 v5, 31, v4
v_add_nc_u32_e32 v7, -1, v3
v_lshlrev_b64 v[1:2], 1, v[4:5]
v_cmp_gt_u32_e64 s1, 50, v7
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s6, v1
v_mov_b32_e32 v1, 0
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v2, vcc_lo
s_and_b32 s3, s2, s1
s_and_saveexec_b32 s0, s3
s_cbranch_execz BB32_2
global_load_ushort v1, v[7:8], off
s_waitcnt vmcnt(0)
v_add_f16_e32 v1, 0, v1
BB32_2:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_gt_u32_e64 s0, 50, v3
v_mov_b32_e32 v2, 0
s_and_b32 s3, s2, s0
s_and_saveexec_b32 s8, s3
s_cbranch_execz BB32_4
global_load_ushort v2, v[7:8], off offset:512
BB32_4:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v5, 0
s_and_saveexec_b32 s8, s3
s_cbranch_execz BB32_6
global_load_ushort v5, v[7:8], off offset:1024
BB32_6:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v3, 2, v3
v_mov_b32_e32 v6, 0
v_cmp_gt_u32_e32 vcc_lo, 50, v3
s_and_b32 s3, s2, vcc_lo
s_and_saveexec_b32 s2, s3
s_cbranch_execz BB32_8
global_load_ushort v6, v[7:8], off offset:1536
BB32_8:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_u32_e64 s2, 47, v10
v_mov_b32_e32 v3, 0
s_and_b32 s3, s2, s1
s_and_saveexec_b32 s8, s3
s_cbranch_execz BB32_10
v_add_nc_u32_e32 v7, 0x3200, v4
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 1, v[7:8]
v_add_co_u32 v7, s3, s6, v7
v_add_co_ci_u32_e64 v8, s3, s7, v8, s3
global_load_ushort v3, v[7:8], off
BB32_10:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v8, 0
s_and_b32 s8, s2, s0
s_and_saveexec_b32 s9, s8
s_cbranch_execz BB32_12
v_add_nc_u32_e32 v7, 0x3300, v4
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 1, v[7:8]
v_add_co_u32 v7, s3, s6, v7
v_add_co_ci_u32_e64 v8, s3, s7, v8, s3
global_load_ushort v8, v[7:8], off
BB32_12:
s_or_b32 exec_lo, exec_lo, s9
v_mov_b32_e32 v7, 0
s_and_saveexec_b32 s9, s8
s_cbranch_execz BB32_14
v_add_nc_u32_e32 v11, 0x3400, v4
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 1, v[11:12]
v_add_co_u32 v11, s3, s6, v11
v_add_co_ci_u32_e64 v12, s3, s7, v12, s3
global_load_ushort v7, v[11:12], off
BB32_14:
s_or_b32 exec_lo, exec_lo, s9
v_mov_b32_e32 v9, 0
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz BB32_16
v_add_nc_u32_e32 v11, 0x3500, v4
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 1, v[11:12]
v_add_co_u32 v11, s2, s6, v11
v_add_co_ci_u32_e64 v12, s2, s7, v12, s2
global_load_ushort v9, v[11:12], off
BB32_16:
s_or_b32 exec_lo, exec_lo, s3
v_or_b32_e32 v11, 1, v10
v_cmp_gt_u32_e64 s2, 47, v11
v_mov_b32_e32 v11, 0
s_and_b32 s3, s2, s1
s_and_saveexec_b32 s8, s3
s_cbranch_execz BB32_18
v_add_nc_u32_e32 v11, 0x6400, v4
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 1, v[11:12]
v_add_co_u32 v11, s3, s6, v11
v_add_co_ci_u32_e64 v12, s3, s7, v12, s3
global_load_ushort v11, v[11:12], off
BB32_18:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v12, 0
s_and_b32 s8, s2, s0
s_and_saveexec_b32 s9, s8
s_cbranch_execz BB32_20
v_add_nc_u32_e32 v12, 0x6500, v4
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 1, v[12:13]
v_add_co_u32 v12, s3, s6, v12
v_add_co_ci_u32_e64 v13, s3, s7, v13, s3
global_load_ushort v12, v[12:13], off
BB32_20:
s_or_b32 exec_lo, exec_lo, s9
v_mov_b32_e32 v13, 0
s_and_saveexec_b32 s9, s8
s_cbranch_execz BB32_22
v_add_nc_u32_e32 v13, 0x6600, v4
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 1, v[13:14]
v_add_co_u32 v13, s3, s6, v13
v_add_co_ci_u32_e64 v14, s3, s7, v14, s3
global_load_ushort v13, v[13:14], off
BB32_22:
s_or_b32 exec_lo, exec_lo, s9
v_mov_b32_e32 v14, 0
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz BB32_24
v_add_nc_u32_e32 v14, 0x6700, v4
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[14:15], 1, v[14:15]
v_add_co_u32 v14, s2, s6, v14
v_add_co_ci_u32_e64 v15, s2, s7, v15, s2
global_load_ushort v14, v[14:15], off
BB32_24:
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v10, 2, v10
v_cmp_gt_u32_e64 s2, 47, v10
v_mov_b32_e32 v10, 0
s_and_b32 s1, s2, s1
s_and_saveexec_b32 s3, s1
s_cbranch_execz BB32_26
v_add_nc_u32_e32 v15, 0x9600, v4
v_ashrrev_i32_e32 v16, 31, v15
v_lshlrev_b64 v[15:16], 1, v[15:16]
v_add_co_u32 v15, s1, s6, v15
v_add_co_ci_u32_e64 v16, s1, s7, v16, s1
global_load_ushort v10, v[15:16], off
BB32_26:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v15, 0
s_and_b32 s1, s2, s0
s_and_saveexec_b32 s3, s1
s_cbranch_execz BB32_28
v_add_nc_u32_e32 v15, 0x9700, v4
v_ashrrev_i32_e32 v16, 31, v15
v_lshlrev_b64 v[15:16], 1, v[15:16]
v_add_co_u32 v15, s0, s6, v15
v_add_co_ci_u32_e64 v16, s0, s7, v16, s0
global_load_ushort v15, v[15:16], off
BB32_28:
s_or_b32 exec_lo, exec_lo, s3
s_load_dwordx2 s[4:5], s[4:5], 0x8
v_mov_b32_e32 v16, 0
s_and_saveexec_b32 s3, s1
s_cbranch_execz BB32_30
v_add_nc_u32_e32 v16, 0x9800, v4
v_ashrrev_i32_e32 v17, 31, v16
v_lshlrev_b64 v[16:17], 1, v[16:17]
v_add_co_u32 v16, s0, s6, v16
v_add_co_ci_u32_e64 v17, s0, s7, v17, s0
global_load_ushort v16, v[16:17], off
BB32_30:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v17, 0
s_and_b32 s1, s2, vcc_lo
s_and_saveexec_b32 s0, s1
s_cbranch_execz BB32_32
v_add_nc_u32_e32 v17, 0x9900, v4
v_ashrrev_i32_e32 v18, 31, v17
v_lshlrev_b64 v[17:18], 1, v[17:18]
v_add_co_u32 v17, vcc_lo, s6, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s7, v18, vcc_lo
global_load_ushort v17, v[17:18], off
BB32_32:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt vmcnt(0)
v_sub_f16_e32 v4, v1, v5
v_ashrrev_i32_e32 v1, 31, v0
v_sub_f16_e32 v18, 0, v2
v_add_f16_e32 v2, 0, v2
v_add_f16_e32 v21, 0, v8
v_sub_f16_e32 v4, v4, v11
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_add_f16_e32 v19, v5, v18
v_add_f16_e32 v6, v18, v6
v_add_f16_e32 v2, v5, v2
v_add_f16_e32 v20, v4, v13
v_sub_f16_e32 v18, 0, v3
v_add_f16_e32 v4, v19, v12
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
v_sub_f16_e32 v2, v2, v12
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_add_f16_e32 v6, v6, v12
v_sub_f16_e32 v19, v4, v13
v_add_co_u32 v4, vcc_lo, 0x4b000, v0
v_sub_f16_e32 v2, v2, v13
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_sub_f16_e32 v23, v21, v7
v_sub_f16_e32 v8, 0, v8
v_sub_f16_e32 v6, v6, v14
global_store_short v[0:1], v20, off
global_store_short v[4:5], v19, off
v_add_f16_e32 v20, v18, v7
v_add_co_u32 v4, vcc_lo, 0x96000, v0
v_add_f16_e32 v27, 0, v3
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v18, vcc_lo, 0xe1000, v0
v_add_f16_e32 v22, v11, v20
v_add_co_ci_u32_e32 v19, vcc_lo, 0, v1, vcc_lo
v_sub_f16_e32 v27, v27, v7
v_sub_f16_e32 v26, v21, v9
global_store_short v[4:5], v2, off
global_store_short v[18:19], v6, off
v_sub_f16_e32 v6, v22, v13
v_sub_f16_e32 v2, v23, v12
v_sub_f16_e32 v22, v8, v7
v_add_co_u32 v4, vcc_lo, 0x12c000, v0
v_sub_f16_e32 v28, v26, v12
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v24, v13, v2
v_add_f16_e32 v2, v12, v22
v_add_co_u32 v18, vcc_lo, 0x177000, v0
v_add_co_ci_u32_e32 v19, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v25, v13, v2
v_add_co_u32 v2, vcc_lo, 0x1c2000, v0
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
global_store_short v[4:5], v6, off
global_store_short v[18:19], v24, off
global_store_short v[2:3], v25, off
v_add_f16_e32 v5, v7, v8
v_add_f16_e32 v4, v11, v27
v_add_f16_e32 v7, v7, v21
v_add_co_u32 v2, vcc_lo, 0x20d000, v0
v_add_f16_e32 v18, v14, v28
v_sub_f16_e32 v6, v5, v12
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
v_sub_f16_e32 v11, v4, v13
v_add_co_u32 v4, vcc_lo, 0x258000, v0
v_add_f16_e32 v21, v12, v7
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v19, v13, v6
v_add_co_u32 v6, vcc_lo, 0x2a3000, v0
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v13, v13, v21
v_add_f16_e32 v21, v8, v9
v_add_co_u32 v8, vcc_lo, 0x2ee000, v0
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo
global_store_short v[2:3], v18, off
global_store_short v[4:5], v11, off
global_store_short v[6:7], v19, off
global_store_short v[8:9], v13, off
v_add_f16_e32 v4, v20, v10
v_add_co_u32 v2, vcc_lo, 0x339000, v0
v_sub_f16_e32 v12, v21, v12
v_sub_f16_e32 v6, v23, v15
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
v_sub_f16_e32 v10, v4, v16
v_add_co_u32 v4, vcc_lo, 0x384000, v0
v_add_f16_e32 v8, v22, v15
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v11, v14, v12
v_add_f16_e32 v12, v16, v6
v_add_co_u32 v6, vcc_lo, 0x3cf000, v0
v_sub_f16_e32 v14, v26, v15
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v13, v16, v8
v_add_co_u32 v8, vcc_lo, 0x41a000, v0
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, 0x465000, v0
v_add_f16_e32 v14, v14, v17
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
global_store_short v[2:3], v11, off
global_store_short v[4:5], v10, off
global_store_short v[6:7], v12, off
global_store_short v[8:9], v13, off
global_store_short v[0:1], v14, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 29
.amdhsa_next_free_sgpr 10
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end32:
.size tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel0, .Lfunc_end32-tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel0
.globl tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel1
.p2align 8
.type tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel1,@function
tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel1:
s_clause 0x2
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_mul_hi_i32 s0, s6, 0x66666667
v_lshlrev_b32_e32 v1, 4, v0
v_lshlrev_b32_e32 v2, 6, v0
s_lshr_b32 s4, s0, 31
s_ashr_i32 s0, s0, 3
s_mul_i32 s1, s6, 0x1e00
s_add_i32 s0, s0, s4
v_and_b32_e32 v1, 0x3f00, v1
v_and_or_b32 v3, v0, 15, s1
v_perm_b32 v2, s0, v2, 0x504010c
v_lshlrev_b32_e32 v4, 2, v0
s_movk_i32 s4, 0x2000
v_cmp_gt_i32_e64 s0, 0x60, v0
v_add_nc_u32_e32 v31, v3, v1
v_lshl_or_b32 v32, v0, 1, s4
v_and_or_b32 v33, v4, 12, v2
v_lshlrev_b32_e32 v34, 3, v0
v_lshlrev_b32_e32 v35, 5, v0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v24, 0
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v28, 0
v_mov_b32_e32 v29, 0
v_mov_b32_e32 v30, 0
s_mov_b32 s5, 0
BB33_1:
s_lshl_b32 s6, s5, 4
v_add_nc_u32_e32 v36, s6, v31
v_ashrrev_i32_e32 v37, 31, v36
v_lshlrev_b64 v[36:37], 1, v[36:37]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v36, vcc_lo, s8, v36
v_add_co_ci_u32_e32 v37, vcc_lo, s9, v37, vcc_lo
v_add_co_u32 v38, vcc_lo, 0x1000, v36
v_add_co_ci_u32_e32 v39, vcc_lo, 0, v37, vcc_lo
v_add_co_u32 v40, vcc_lo, s4, v36
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v37, vcc_lo
s_clause 0x2
global_load_ushort v42, v[36:37], off
global_load_ushort v38, v[38:39], off
global_load_ushort v39, v[40:41], off
s_waitcnt vmcnt(0)
s_barrier
ds_write_b16 v32, v42
ds_write_b16 v32, v38 offset:256
ds_write_b16 v32, v39 offset:512
s_and_saveexec_b32 s7, s0
s_cbranch_execz BB33_3
v_add_co_u32 v36, vcc_lo, 0x3000, v36
v_add_co_ci_u32_e32 v37, vcc_lo, 0, v37, vcc_lo
global_load_ushort v36, v[36:37], off
s_waitcnt vmcnt(0)
ds_write_b16 v32, v36 offset:768
BB33_3:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v36, s6, v33
s_mov_b32 s7, 0
s_mov_b32 s6, -1
v_ashrrev_i32_e32 v37, 31, v36
v_lshlrev_b64 v[36:37], 1, v[36:37]
v_add_co_u32 v36, vcc_lo, s10, v36
v_add_co_ci_u32_e32 v37, vcc_lo, s11, v37, vcc_lo
v_add_co_u32 v38, vcc_lo, 0x4000, v36
v_add_co_ci_u32_e32 v39, vcc_lo, 0, v37, vcc_lo
v_add_co_u32 v40, vcc_lo, 0x8000, v36
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v37, vcc_lo
v_add_co_u32 v42, vcc_lo, 0xc000, v36
v_add_co_ci_u32_e32 v43, vcc_lo, 0, v37, vcc_lo
v_add_co_u32 v44, vcc_lo, 0x10000, v36
v_add_co_ci_u32_e32 v45, vcc_lo, 0, v37, vcc_lo
v_add_co_u32 v46, vcc_lo, 0x14000, v36
v_add_co_ci_u32_e32 v47, vcc_lo, 0, v37, vcc_lo
v_add_co_u32 v48, vcc_lo, 0x18000, v36
v_add_co_ci_u32_e32 v49, vcc_lo, 0, v37, vcc_lo
v_add_co_u32 v50, vcc_lo, 0x1c000, v36
v_add_co_ci_u32_e32 v51, vcc_lo, 0, v37, vcc_lo
s_clause 0x7
global_load_dwordx2 v[36:37], v[36:37], off
global_load_dwordx2 v[38:39], v[38:39], off
global_load_dwordx2 v[40:41], v[40:41], off
global_load_dwordx2 v[42:43], v[42:43], off
global_load_dwordx2 v[44:45], v[44:45], off
global_load_dwordx2 v[46:47], v[46:47], off
global_load_dwordx2 v[48:49], v[48:49], off
global_load_dwordx2 v[50:51], v[50:51], off
s_waitcnt vmcnt(6)
ds_write2st64_b64 v34, v[36:37], v[38:39] offset1:2
s_waitcnt vmcnt(4)
ds_write2st64_b64 v34, v[40:41], v[42:43] offset0:4 offset1:6
s_waitcnt vmcnt(2)
ds_write2st64_b64 v34, v[44:45], v[46:47] offset0:8 offset1:10
s_waitcnt vmcnt(0)
ds_write2st64_b64 v34, v[48:49], v[50:51] offset0:12 offset1:14
s_waitcnt lgkmcnt(0)
s_barrier
BB33_4:
v_or_b32_e32 v36, s7, v35
s_lshl_b32 s7, s7, 1
v_mov_b32_e32 v72, 0xffff
v_mov_b32_e32 v76, s7
s_and_b32 vcc_lo, exec_lo, s6
v_lshlrev_b32_e32 v68, 1, v36
s_mov_b32 s7, 8
s_mov_b32 s6, 0
ds_read_b128 v[36:39], v76 offset:8192
ds_read_b128 v[40:43], v76 offset:8224
ds_read_b128 v[44:47], v76 offset:8256
ds_read_b128 v[48:51], v76 offset:8288
ds_read_b128 v[52:55], v76 offset:8320
ds_read_b128 v[56:59], v76 offset:8352
ds_read_b128 v[60:63], v76 offset:8384
ds_read_b128 v[64:67], v68
ds_read_b128 v[68:71], v68 offset:32
s_waitcnt lgkmcnt(1)
v_and_b32_e32 v73, v72, v64
v_and_b32_sdwa v74, v72, v64 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
s_waitcnt lgkmcnt(0)
v_lshrrev_b32_e32 v78, 16, v68
v_and_b32_e32 v64, v72, v65
v_and_b32_sdwa v75, v72, v65 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v82, v68, 16, v73
v_lshrrev_b32_e32 v79, 16, v69
v_lshl_or_b32 v86, v78, 16, v74
v_lshl_or_b32 v83, v69, 16, v64
v_and_b32_e32 v65, v72, v66
v_pk_fma_f16 v30, v36, v82, v30 op_sel_hi:[0,1,1]
v_lshl_or_b32 v87, v79, 16, v75
v_and_b32_sdwa v77, v72, v66 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v80, 16, v70
v_lshl_or_b32 v84, v70, 16, v65
v_pk_fma_f16 v30, v36, v86, v30 op_sel:[1,0,0]
v_and_b32_e32 v66, v72, v67
v_and_b32_sdwa v72, v72, v67 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v80, v80, 16, v77
v_lshrrev_b32_e32 v81, 16, v71
v_pk_fma_f16 v30, v37, v83, v30 op_sel_hi:[0,1,1]
v_lshl_or_b32 v85, v71, 16, v66
ds_read_b128 v[64:67], v76 offset:8416
ds_read_b128 v[68:71], v76 offset:8448
v_lshl_or_b32 v81, v81, 16, v72
v_pk_fma_f16 v30, v37, v87, v30 op_sel:[1,0,0]
v_pk_fma_f16 v29, v40, v82, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v44, v82, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v48, v82, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v52, v82, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v38, v84, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v56, v82, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v60, v82, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v40, v86, v29 op_sel:[1,0,0]
v_pk_fma_f16 v28, v44, v86, v28 op_sel:[1,0,0]
v_pk_fma_f16 v30, v38, v80, v30 op_sel:[1,0,0]
v_pk_fma_f16 v27, v48, v86, v27 op_sel:[1,0,0]
v_pk_fma_f16 v26, v52, v86, v26 op_sel:[1,0,0]
v_pk_fma_f16 v25, v56, v86, v25 op_sel:[1,0,0]
v_pk_fma_f16 v24, v60, v86, v24 op_sel:[1,0,0]
v_pk_fma_f16 v30, v39, v85, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v41, v83, v29 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v23, v64, v82, v23 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v22, v68, v82, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v45, v83, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v39, v81, v30 op_sel:[1,0,0]
ds_read_b128 v[36:39], v76 offset:8480
v_pk_fma_f16 v23, v64, v86, v23 op_sel:[1,0,0]
v_pk_fma_f16 v22, v68, v86, v22 op_sel:[1,0,0]
v_pk_fma_f16 v27, v49, v83, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v53, v83, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v57, v83, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v61, v83, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v65, v83, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v69, v83, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v41, v87, v29 op_sel:[1,0,0]
v_pk_fma_f16 v28, v45, v87, v28 op_sel:[1,0,0]
v_pk_fma_f16 v27, v49, v87, v27 op_sel:[1,0,0]
v_pk_fma_f16 v26, v53, v87, v26 op_sel:[1,0,0]
v_pk_fma_f16 v25, v57, v87, v25 op_sel:[1,0,0]
v_pk_fma_f16 v24, v61, v87, v24 op_sel:[1,0,0]
v_pk_fma_f16 v23, v65, v87, v23 op_sel:[1,0,0]
v_pk_fma_f16 v22, v69, v87, v22 op_sel:[1,0,0]
v_pk_fma_f16 v29, v42, v84, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v46, v84, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v50, v84, v27 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v21, v36, v82, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v54, v84, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v58, v84, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v62, v84, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v66, v84, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v36, v86, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v70, v84, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v42, v80, v29 op_sel:[1,0,0]
v_pk_fma_f16 v28, v46, v80, v28 op_sel:[1,0,0]
v_pk_fma_f16 v27, v50, v80, v27 op_sel:[1,0,0]
v_pk_fma_f16 v21, v37, v83, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v54, v80, v26 op_sel:[1,0,0]
v_pk_fma_f16 v25, v58, v80, v25 op_sel:[1,0,0]
v_pk_fma_f16 v24, v62, v80, v24 op_sel:[1,0,0]
v_pk_fma_f16 v23, v66, v80, v23 op_sel:[1,0,0]
v_pk_fma_f16 v21, v37, v87, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v70, v80, v22 op_sel:[1,0,0]
v_pk_fma_f16 v29, v43, v85, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v47, v85, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v51, v85, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v38, v84, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v55, v85, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v59, v85, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v63, v85, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v67, v85, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v38, v80, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v71, v85, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v43, v81, v29 op_sel:[1,0,0]
ds_read_b128 v[40:43], v76 offset:8512
v_pk_fma_f16 v28, v47, v81, v28 op_sel:[1,0,0]
v_pk_fma_f16 v21, v39, v85, v21 op_sel_hi:[0,1,1]
ds_read_b128 v[44:47], v76 offset:8544
v_pk_fma_f16 v27, v51, v81, v27 op_sel:[1,0,0]
ds_read_b128 v[48:51], v76 offset:8576
v_pk_fma_f16 v26, v55, v81, v26 op_sel:[1,0,0]
ds_read_b128 v[52:55], v76 offset:8608
v_pk_fma_f16 v25, v59, v81, v25 op_sel:[1,0,0]
ds_read_b128 v[56:59], v76 offset:8640
v_pk_fma_f16 v24, v63, v81, v24 op_sel:[1,0,0]
ds_read_b128 v[60:63], v76 offset:8672
v_pk_fma_f16 v23, v67, v81, v23 op_sel:[1,0,0]
ds_read_b128 v[64:67], v76 offset:8704
v_pk_fma_f16 v22, v71, v81, v22 op_sel:[1,0,0]
ds_read_b128 v[68:71], v76 offset:8736
v_pk_fma_f16 v21, v39, v81, v21 op_sel:[1,0,0]
ds_read_b128 v[36:39], v76 offset:8768
s_waitcnt lgkmcnt(8)
v_pk_fma_f16 v20, v40, v82, v20 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(7)
v_pk_fma_f16 v19, v44, v82, v19 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(6)
v_pk_fma_f16 v18, v48, v82, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v40, v86, v20 op_sel:[1,0,0]
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v17, v52, v82, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v44, v86, v19 op_sel:[1,0,0]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v16, v56, v82, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v48, v86, v18 op_sel:[1,0,0]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v14, v60, v82, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v52, v86, v17 op_sel:[1,0,0]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v13, v64, v82, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v56, v86, v16 op_sel:[1,0,0]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v12, v68, v82, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v60, v86, v14 op_sel:[1,0,0]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v8, v36, v82, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v64, v86, v13 op_sel:[1,0,0]
v_pk_fma_f16 v20, v41, v83, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v68, v86, v12 op_sel:[1,0,0]
v_pk_fma_f16 v19, v45, v83, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v36, v86, v8 op_sel:[1,0,0]
v_pk_fma_f16 v18, v49, v83, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v53, v83, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v57, v83, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v61, v83, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v65, v83, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v69, v83, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v37, v83, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v41, v87, v20 op_sel:[1,0,0]
v_pk_fma_f16 v19, v45, v87, v19 op_sel:[1,0,0]
v_pk_fma_f16 v18, v49, v87, v18 op_sel:[1,0,0]
v_pk_fma_f16 v17, v53, v87, v17 op_sel:[1,0,0]
v_pk_fma_f16 v16, v57, v87, v16 op_sel:[1,0,0]
v_pk_fma_f16 v14, v61, v87, v14 op_sel:[1,0,0]
v_pk_fma_f16 v13, v65, v87, v13 op_sel:[1,0,0]
v_pk_fma_f16 v12, v69, v87, v12 op_sel:[1,0,0]
v_pk_fma_f16 v8, v37, v87, v8 op_sel:[1,0,0]
v_pk_fma_f16 v20, v42, v84, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v46, v84, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v50, v84, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v54, v84, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v58, v84, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v62, v84, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v66, v84, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v70, v84, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v38, v84, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v42, v80, v20 op_sel:[1,0,0]
v_pk_fma_f16 v19, v46, v80, v19 op_sel:[1,0,0]
v_pk_fma_f16 v18, v50, v80, v18 op_sel:[1,0,0]
v_pk_fma_f16 v17, v54, v80, v17 op_sel:[1,0,0]
v_pk_fma_f16 v16, v58, v80, v16 op_sel:[1,0,0]
v_pk_fma_f16 v14, v62, v80, v14 op_sel:[1,0,0]
v_pk_fma_f16 v13, v66, v80, v13 op_sel:[1,0,0]
v_pk_fma_f16 v12, v70, v80, v12 op_sel:[1,0,0]
v_pk_fma_f16 v8, v38, v80, v8 op_sel:[1,0,0]
v_pk_fma_f16 v20, v43, v85, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v47, v85, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v51, v85, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v55, v85, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v59, v85, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v63, v85, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v67, v85, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v71, v85, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v39, v85, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v43, v81, v20 op_sel:[1,0,0]
ds_read_b128 v[40:43], v76 offset:8800
v_pk_fma_f16 v19, v47, v81, v19 op_sel:[1,0,0]
ds_read_b128 v[44:47], v76 offset:8832
v_pk_fma_f16 v18, v51, v81, v18 op_sel:[1,0,0]
ds_read_b128 v[48:51], v76 offset:8864
v_pk_fma_f16 v17, v55, v81, v17 op_sel:[1,0,0]
ds_read_b128 v[52:55], v76 offset:8896
v_pk_fma_f16 v16, v59, v81, v16 op_sel:[1,0,0]
ds_read_b128 v[56:59], v76 offset:8928
v_pk_fma_f16 v14, v63, v81, v14 op_sel:[1,0,0]
ds_read_b128 v[60:63], v76 offset:8960
v_pk_fma_f16 v13, v67, v81, v13 op_sel:[1,0,0]
ds_read_b128 v[64:67], v76 offset:8992
v_pk_fma_f16 v12, v71, v81, v12 op_sel:[1,0,0]
ds_read_b128 v[68:71], v76 offset:9024
v_pk_fma_f16 v8, v39, v81, v8 op_sel:[1,0,0]
ds_read_b128 v[36:39], v76 offset:9056
ds_read_b128 v[72:75], v76 offset:9088
ds_read_b128 v[76:79], v76 offset:9120
s_waitcnt lgkmcnt(10)
v_pk_fma_f16 v15, v40, v82, v15 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(9)
v_pk_fma_f16 v11, v44, v82, v11 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(8)
v_pk_fma_f16 v10, v48, v82, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v40, v86, v15 op_sel:[1,0,0]
s_waitcnt lgkmcnt(7)
v_pk_fma_f16 v9, v52, v82, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v44, v86, v11 op_sel:[1,0,0]
s_waitcnt lgkmcnt(6)
v_pk_fma_f16 v7, v56, v82, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v48, v86, v10 op_sel:[1,0,0]
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v6, v60, v82, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v52, v86, v9 op_sel:[1,0,0]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v5, v64, v82, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v56, v86, v7 op_sel:[1,0,0]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v4, v68, v82, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v60, v86, v6 op_sel:[1,0,0]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v3, v36, v82, v3 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v2, v72, v82, v2 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v1, v76, v82, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v64, v86, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v68, v86, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v36, v86, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v72, v86, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v76, v86, v1 op_sel:[1,0,0]
v_pk_fma_f16 v15, v41, v83, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v45, v83, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v49, v83, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v53, v83, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v57, v83, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v61, v83, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v65, v83, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v69, v83, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v37, v83, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v73, v83, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v77, v83, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v41, v87, v15 op_sel:[1,0,0]
v_pk_fma_f16 v11, v45, v87, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v49, v87, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v53, v87, v9 op_sel:[1,0,0]
v_pk_fma_f16 v7, v57, v87, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v61, v87, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v65, v87, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v69, v87, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v37, v87, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v73, v87, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v77, v87, v1 op_sel:[1,0,0]
v_pk_fma_f16 v15, v42, v84, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v46, v84, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v50, v84, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v54, v84, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v58, v84, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v62, v84, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v66, v84, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v70, v84, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v38, v84, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v74, v84, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v78, v84, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v42, v80, v15 op_sel:[1,0,0]
v_pk_fma_f16 v11, v46, v80, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v50, v80, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v54, v80, v9 op_sel:[1,0,0]
v_pk_fma_f16 v7, v58, v80, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v62, v80, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v66, v80, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v70, v80, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v38, v80, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v74, v80, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v78, v80, v1 op_sel:[1,0,0]
v_pk_fma_f16 v15, v43, v85, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v47, v85, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v51, v85, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v55, v85, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v59, v85, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v63, v85, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v67, v85, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v71, v85, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v39, v85, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v75, v85, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v79, v85, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v43, v81, v15 op_sel:[1,0,0]
v_pk_fma_f16 v11, v47, v81, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v51, v81, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v55, v81, v9 op_sel:[1,0,0]
v_pk_fma_f16 v7, v59, v81, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v63, v81, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v67, v81, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v71, v81, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v39, v81, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v75, v81, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v79, v81, v1 op_sel:[1,0,0]
s_cbranch_vccnz BB33_4
s_add_i32 s5, s5, 1
s_cmp_eq_u32 s5, 16
s_cbranch_scc0 BB33_1
v_lshl_add_u32 v31, v0, 1, s1
v_add_nc_u32_e32 v33, 0x400, v31
v_ashrrev_i32_e32 v32, 31, v31
v_add_nc_u32_e32 v35, 0x500, v31
v_add_nc_u32_e32 v37, 0x600, v31
v_add_nc_u32_e32 v39, 0x700, v31
v_ashrrev_i32_e32 v34, 31, v33
v_lshlrev_b64 v[41:42], 1, v[31:32]
v_ashrrev_i32_e32 v36, 31, v35
v_ashrrev_i32_e32 v38, 31, v37
v_ashrrev_i32_e32 v40, 31, v39
v_lshlrev_b64 v[32:33], 1, v[33:34]
v_add_co_u32 v41, vcc_lo, s2, v41
v_lshlrev_b64 v[34:35], 1, v[35:36]
v_add_co_ci_u32_e32 v42, vcc_lo, s3, v42, vcc_lo
v_lshlrev_b64 v[36:37], 1, v[37:38]
v_add_co_u32 v32, vcc_lo, s2, v32
v_add_co_ci_u32_e32 v33, vcc_lo, s3, v33, vcc_lo
global_store_dword v[41:42], v30, off
global_store_dword v[41:42], v29, off offset:512
global_store_dword v[41:42], v28, off offset:1024
global_store_dword v[41:42], v27, off offset:1536
global_store_dword v[32:33], v26, off
v_add_co_u32 v26, vcc_lo, s2, v34
v_add_nc_u32_e32 v32, 0x800, v31
v_lshlrev_b64 v[28:29], 1, v[39:40]
v_add_co_ci_u32_e32 v27, vcc_lo, s3, v35, vcc_lo
v_add_co_u32 v34, vcc_lo, s2, v36
v_add_nc_u32_e32 v36, 0x900, v31
v_ashrrev_i32_e32 v33, 31, v32
v_add_co_ci_u32_e32 v35, vcc_lo, s3, v37, vcc_lo
v_add_co_u32 v28, vcc_lo, s2, v28
global_store_dword v[26:27], v25, off
v_ashrrev_i32_e32 v37, 31, v36
v_add_co_ci_u32_e32 v29, vcc_lo, s3, v29, vcc_lo
v_add_nc_u32_e32 v27, 0xa00, v31
v_lshlrev_b64 v[25:26], 1, v[32:33]
v_add_nc_u32_e32 v32, 0xc00, v31
global_store_dword v[34:35], v24, off
global_store_dword v[28:29], v23, off
v_lshlrev_b64 v[23:24], 1, v[36:37]
v_ashrrev_i32_e32 v28, 31, v27
v_add_nc_u32_e32 v29, 0xb00, v31
v_add_co_u32 v25, vcc_lo, s2, v25
v_ashrrev_i32_e32 v33, 31, v32
v_add_co_ci_u32_e32 v26, vcc_lo, s3, v26, vcc_lo
v_add_co_u32 v23, vcc_lo, s2, v23
v_lshlrev_b64 v[27:28], 1, v[27:28]
v_add_co_ci_u32_e32 v24, vcc_lo, s3, v24, vcc_lo
v_ashrrev_i32_e32 v30, 31, v29
global_store_dword v[25:26], v22, off
global_store_dword v[23:24], v21, off
v_add_co_u32 v23, vcc_lo, s2, v27
v_add_nc_u32_e32 v27, 0xd00, v31
v_lshlrev_b64 v[21:22], 1, v[29:30]
v_lshlrev_b64 v[25:26], 1, v[32:33]
v_add_co_ci_u32_e32 v24, vcc_lo, s3, v28, vcc_lo
v_add_nc_u32_e32 v29, 0xe00, v31
v_ashrrev_i32_e32 v28, 31, v27
v_add_co_u32 v21, vcc_lo, s2, v21
global_store_dword v[23:24], v20, off
v_add_co_ci_u32_e32 v22, vcc_lo, s3, v22, vcc_lo
v_add_co_u32 v25, vcc_lo, s2, v25
v_lshlrev_b64 v[23:24], 1, v[27:28]
v_ashrrev_i32_e32 v30, 31, v29
v_add_co_ci_u32_e32 v26, vcc_lo, s3, v26, vcc_lo
v_add_nc_u32_e32 v20, 0xf00, v31
global_store_dword v[21:22], v19, off
global_store_dword v[25:26], v18, off
v_add_co_u32 v22, vcc_lo, s2, v23
v_lshlrev_b64 v[18:19], 1, v[29:30]
v_add_co_ci_u32_e32 v23, vcc_lo, s3, v24, vcc_lo
v_ashrrev_i32_e32 v21, 31, v20
v_add_nc_u32_e32 v24, 0x1000, v31
v_add_nc_u32_e32 v26, 0x1100, v31
v_add_co_u32 v18, vcc_lo, s2, v18
v_lshlrev_b64 v[20:21], 1, v[20:21]
v_ashrrev_i32_e32 v25, 31, v24
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
v_ashrrev_i32_e32 v27, 31, v26
global_store_dword v[22:23], v17, off
global_store_dword v[18:19], v16, off
v_lshlrev_b64 v[16:17], 1, v[24:25]
v_add_co_u32 v18, vcc_lo, s2, v20
v_add_nc_u32_e32 v22, 0x1200, v31
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v21, vcc_lo
v_lshlrev_b64 v[20:21], 1, v[26:27]
v_add_nc_u32_e32 v24, 0x1300, v31
v_add_co_u32 v16, vcc_lo, s2, v16
v_ashrrev_i32_e32 v23, 31, v22
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
global_store_dword v[18:19], v14, off
v_add_co_u32 v20, vcc_lo, s2, v20
v_ashrrev_i32_e32 v25, 31, v24
v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo
v_lshlrev_b64 v[18:19], 1, v[22:23]
v_add_nc_u32_e32 v14, 0x1600, v31
global_store_dword v[16:17], v13, off
global_store_dword v[20:21], v12, off
v_lshlrev_b64 v[12:13], 1, v[24:25]
v_add_nc_u32_e32 v16, 0x1400, v31
v_add_co_u32 v18, vcc_lo, s2, v18
v_add_nc_u32_e32 v20, 0x1500, v31
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
v_ashrrev_i32_e32 v17, 31, v16
v_add_co_u32 v12, vcc_lo, s2, v12
v_ashrrev_i32_e32 v21, 31, v20
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
v_lshlrev_b64 v[16:17], 1, v[16:17]
global_store_dword v[18:19], v8, off
global_store_dword v[12:13], v15, off
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[12:13], 1, v[20:21]
v_add_nc_u32_e32 v18, 0x1700, v31
v_add_co_u32 v16, vcc_lo, s2, v16
v_add_nc_u32_e32 v20, 0x1800, v31
v_lshlrev_b64 v[14:15], 1, v[14:15]
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
v_add_co_u32 v12, vcc_lo, s2, v12
v_ashrrev_i32_e32 v19, 31, v18
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
v_ashrrev_i32_e32 v21, 31, v20
v_add_co_u32 v14, vcc_lo, s2, v14
global_store_dword v[16:17], v11, off
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
v_lshlrev_b64 v[16:17], 1, v[18:19]
global_store_dword v[12:13], v10, off
global_store_dword v[14:15], v9, off
v_lshlrev_b64 v[8:9], 1, v[20:21]
v_add_nc_u32_e32 v10, 0x1900, v31
v_add_co_u32 v12, vcc_lo, s2, v16
v_add_nc_u32_e32 v14, 0x1a00, v31
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v17, vcc_lo
v_add_nc_u32_e32 v16, 0x1b00, v31
v_add_co_u32 v8, vcc_lo, s2, v8
v_ashrrev_i32_e32 v11, 31, v10
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
v_ashrrev_i32_e32 v15, 31, v14
v_ashrrev_i32_e32 v17, 31, v16
global_store_dword v[12:13], v7, off
v_lshlrev_b64 v[10:11], 1, v[10:11]
global_store_dword v[8:9], v6, off
v_add_nc_u32_e32 v8, 0x1c00, v31
v_lshlrev_b64 v[6:7], 1, v[14:15]
v_add_nc_u32_e32 v14, 0x1d00, v31
v_lshlrev_b64 v[12:13], 1, v[16:17]
v_add_co_u32 v10, vcc_lo, s2, v10
v_ashrrev_i32_e32 v9, 31, v8
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
v_ashrrev_i32_e32 v15, 31, v14
v_add_co_u32 v6, vcc_lo, s2, v6
v_lshlrev_b64 v[8:9], 1, v[8:9]
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v12, vcc_lo, s2, v12
v_lshlrev_b64 v[14:15], 1, v[14:15]
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v14, vcc_lo, s2, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
global_store_dword v[10:11], v5, off
global_store_dword v[6:7], v4, off
global_store_dword v[12:13], v3, off
global_store_dword v[8:9], v2, off
global_store_dword v[14:15], v1, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel1
.amdhsa_group_segment_fixed_size 9152
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 88
.amdhsa_next_free_sgpr 12
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end33:
.size tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel1, .Lfunc_end33-tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel1
.globl tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel2
.p2align 8
.type tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel2,@function
tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel2:
s_lshl_b32 s2, s6, 3
s_lshl_b32 s3, s6, 8
s_lshl_b32 s6, s6, 5
s_and_b32 s3, s3, 0x300
s_and_b32 s6, s6, 0xfffffc00
s_load_dwordx2 s[0:1], s[4:5], 0x8
s_or_b32 s3, s6, s3
s_and_b32 s2, s2, 0xe0
s_mov_b32 s6, 0xe1000
s_or_b32 s2, s3, s2
s_mov_b32 s3, 0x96000
v_add_nc_u32_e32 v0, s2, v0
s_mov_b32 s2, 0x4b000
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s3, v2
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, 0x12c000, v2
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v10, vcc_lo, 0x177000, v2
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v3, vcc_lo
s_clause 0x4
global_load_ushort v14, v[2:3], off
global_load_ushort v15, v[4:5], off
global_load_ushort v16, v[6:7], off
global_load_ushort v17, v[8:9], off
global_load_ushort v18, v[10:11], off
v_add_co_u32 v4, vcc_lo, 0x1c2000, v2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, 0x258000, v2
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, 0x2a3000, v2
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v10, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v12, vcc_lo, 0x20d000, v2
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v3, vcc_lo
s_clause 0x4
global_load_ushort v19, v[4:5], off
global_load_ushort v20, v[6:7], off
global_load_ushort v8, v[8:9], off
global_load_ushort v9, v[10:11], off
global_load_ushort v10, v[12:13], off
v_add_co_u32 v4, vcc_lo, 0x2ee000, v2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, 0x339000, v2
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
s_clause 0x1
global_load_ushort v11, v[4:5], off
global_load_ushort v12, v[6:7], off
v_add_co_u32 v4, vcc_lo, 0x384000, v2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, 0x3cf000, v2
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
s_clause 0x1
global_load_ushort v13, v[4:5], off
global_load_ushort v6, v[6:7], off
v_add_co_u32 v4, vcc_lo, 0x41a000, v2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, 0x465000, v2
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_ushort v21, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_ushort v22, v[2:3], off
s_waitcnt vmcnt(15)
v_add_f16_e32 v2, 0, v14
s_waitcnt vmcnt(14)
v_sub_f16_e32 v3, 0, v15
s_waitcnt vmcnt(12)
v_sub_f16_e32 v4, 0, v17
s_waitcnt vmcnt(11)
v_add_f16_e32 v5, 0, v18
v_add_f16_e32 v2, v2, v15
v_add_f16_e32 v3, v3, v16
v_sub_f16_e32 v4, v4, v18
v_add_f16_e32 v2, v2, v16
v_add_f16_e32 v2, v2, v17
s_waitcnt vmcnt(10)
v_sub_f16_e32 v5, v5, v19
v_sub_f16_e32 v4, v4, v19
s_waitcnt vmcnt(7)
v_add_f16_e32 v3, v3, v9
v_add_f16_e32 v2, v2, v18
s_waitcnt vmcnt(6)
v_sub_f16_e32 v5, v5, v10
v_add_f16_e32 v4, v4, v20
v_sub_f16_e32 v3, v3, v18
v_add_f16_e32 v7, v2, v19
v_sub_f16_e32 v5, v5, v8
v_add_f16_e32 v4, v4, v8
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_f16_e32 v3, v19, v3
v_add_f16_e32 v7, v7, v20
s_waitcnt vmcnt(5)
v_add_f16_e32 v5, v11, v5
v_add_f16_e32 v4, v4, v11
v_add_f16_e32 v9, v10, v3
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
s_waitcnt vmcnt(4)
v_add_f16_e32 v5, v12, v5
v_sub_f16_e32 v9, v9, v8
s_waitcnt vmcnt(3)
v_add_f16_e32 v10, v4, v13
s_waitcnt vmcnt(2)
v_sub_f16_e32 v13, v5, v6
v_add_f16_e32 v8, v7, v8
v_add_co_u32 v4, vcc_lo, s3, v0
v_add_f16_e32 v9, v11, v9
v_add_f16_e32 v10, v10, v6
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v8, v8, v11
s_waitcnt vmcnt(1)
v_add_f16_e32 v13, v13, v21
v_add_co_u32 v6, vcc_lo, s6, v0
v_add_f16_e32 v9, v12, v9
v_add_f16_e32 v10, v10, v21
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f16_e32 v11, v13, v22
global_store_short v[0:1], v8, off
global_store_short v[2:3], v9, off
global_store_short v[4:5], v10, off
global_store_short v[6:7], v11, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel2
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end34:
.size tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel2, .Lfunc_end34-tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel2
.globl tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel3
.p2align 8
.type tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel3,@function
tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel3:
v_lshl_add_u32 v0, s6, 6, v0
v_mov_b32_e32 v5, 0x147b
v_mov_b32_e32 v6, 0x4b000
s_clause 0x1
s_load_dwordx2 s[0:1], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
v_mul_hi_i32 v1, 0x51eb851f, v0
v_bfe_u32 v7, v0, 8, 1
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v3, 13, v1
v_ashrrev_i32_e32 v1, 12, v1
v_add_nc_u32_e32 v3, v3, v2
v_add_nc_u32_e32 v1, v1, v2
v_mul_i32_i24_e32 v4, 0x6400, v3
v_mul_i32_i24_e32 v1, 0x3200, v1
v_mul_i32_i24_e32 v3, 0x1900, v3
v_sub_nc_u32_e32 v2, v0, v4
v_sub_nc_u32_e32 v1, v0, v1
v_and_b32_e32 v4, 0xff, v0
v_mul_i32_i24_sdwa v2, sext(v2), v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
v_ashrrev_i32_e32 v1, 1, v1
v_or_b32_e32 v3, v3, v4
v_lshrrev_b32_e32 v5, 31, v2
v_ashrrev_i32_e32 v2, 26, v2
v_mad_u32_u24 v3, 0x25800, v7, v3
v_and_b32_e32 v1, 0xffffff00, v1
v_add_nc_u16 v2, v2, v5
v_mul_i32_i24_sdwa v2, sext(v2), v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
v_add3_u32 v1, v3, v1, v2
v_lshlrev_b32_e32 v3, 1, v4
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
global_load_ushort v3, v3, s[2:3]
global_load_ushort v2, v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f16_e32 v2, v3, v2
v_max_f16_e32 v2, 0, v2
global_store_short v[0:1], v2, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel3
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end35:
.size tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel3, .Lfunc_end35-tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel3
.globl tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel0
.p2align 8
.type tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel0,@function
tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel0:
s_mul_hi_i32 s0, s6, 0x30c30c31
s_clause 0x1
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[4:5], s[4:5], 0x8
s_lshr_b32 s1, s0, 31
s_ashr_i32 s0, s0, 3
s_add_i32 s0, s0, s1
s_mul_i32 s1, s0, 42
s_lshl_b32 s7, s0, 5
s_sub_i32 s2, s6, s1
s_bfe_i32 s1, s2, 0x80000
v_mul_lo_u16 v1, 0xff93, s1
s_mul_hi_i32 s1, s6, 0x92492493
s_add_i32 s1, s1, s6
v_lshrrev_b16 v1, 8, v1
s_lshr_b32 s3, s1, 31
s_ashr_i32 s1, s1, 2
s_add_i32 s1, s1, s3
v_add_nc_u16 v1, v1, s2
s_mul_i32 s1, s1, 7
s_sub_i32 s0, s6, s1
v_lshrrev_b16 v2, 7, v1
v_bfe_i32 v1, v1, 0, 8
s_lshl_b32 s1, s0, 11
v_and_b32_e32 v2, 1, v2
v_ashrrev_i16 v1, 2, v1
v_add_nc_u16 v1, v1, v2
v_bfe_i32 v1, v1, 0, 16
v_mul_lo_u32 v2, 0xc800, v1
v_lshlrev_b32_e32 v23, 2, v1
v_add_nc_u32_e32 v2, s7, v2
v_add_nc_u32_e32 v1, s1, v2
v_add_nc_u32_e32 v2, -1, v23
s_lshl_b32 s1, s0, 2
s_add_i32 s3, s1, -1
v_add3_u32 v37, v0, v1, 0xffffcc00
v_cmp_lt_u32_e32 vcc_lo, 23, v2
s_and_b32 vcc_lo, exec_lo, vcc_lo
s_cbranch_vccnz BB36_68
v_ashrrev_i32_e32 v38, 31, v37
v_mov_b32_e32 v35, 0
v_mov_b32_e32 v36, 0
s_cmp_gt_u32 s3, 24
v_lshlrev_b64 v[1:2], 1, v[37:38]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
s_cbranch_scc1 BB36_3
global_load_ushort v36, v[1:2], off
BB36_3:
s_cmp_lt_u32 s1, 25
s_cbranch_scc0 BB36_5
global_load_ushort v35, v[1:2], off offset:1024
BB36_5:
v_mov_b32_e32 v31, 0
v_mov_b32_e32 v32, 0
s_or_b32 s0, s1, 1
s_cmp_gt_u32 s0, 24
s_cbranch_scc1 BB36_7
v_add_nc_u32_e32 v1, 0x400, v37
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_ushort v32, v[1:2], off
BB36_7:
s_or_b32 s0, s1, 2
s_cmp_gt_u32 s0, 24
s_cbranch_scc1 BB36_9
v_add_nc_u32_e32 v1, 0x600, v37
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_ushort v31, v[1:2], off
BB36_9:
v_mov_b32_e32 v33, 0
v_mov_b32_e32 v34, 0
s_or_b32 s0, s1, 3
s_cmp_gt_u32 s0, 24
s_cbranch_scc0 BB36_75
s_add_i32 s0, s1, 4
s_cmp_gt_u32 s0, 24
s_cbranch_scc0 BB36_76
BB36_11:
v_cmp_gt_u32_e64 s0, 24, v23
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz BB36_69
BB36_12:
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v16, 0
s_cmp_gt_u32 s3, 24
s_cbranch_scc1 BB36_14
v_add_nc_u32_e32 v1, 0x3200, v37
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_ushort v16, v[1:2], off
BB36_14:
s_cmp_gt_u32 s1, 24
s_cbranch_scc1 BB36_16
v_add_nc_u32_e32 v1, 0x3400, v37
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_ushort v15, v[1:2], off
BB36_16:
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v5, 0
s_or_b32 s6, s1, 1
s_cmp_gt_u32 s6, 24
s_cbranch_scc1 BB36_18
v_add_nc_u32_e32 v1, 0x3600, v37
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_ushort v5, v[1:2], off
BB36_18:
s_or_b32 s6, s1, 2
s_cmp_gt_u32 s6, 24
s_cbranch_scc1 BB36_20
v_add_nc_u32_e32 v1, 0x3800, v37
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_ushort v17, v[1:2], off
BB36_20:
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_or_b32 s6, s1, 3
s_cmp_gt_u32 s6, 24
s_cbranch_scc0 BB36_77
s_add_i32 s6, s1, 4
s_cmp_gt_u32 s6, 24
s_cbranch_scc0 BB36_78
BB36_22:
s_andn2_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz BB36_70
BB36_23:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v12, 0
s_cmp_gt_u32 s3, 24
s_cbranch_scc1 BB36_25
v_add_nc_u32_e32 v2, 0x6400, v37
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_ushort v12, v[2:3], off
BB36_25:
s_cmp_gt_u32 s1, 24
s_cbranch_scc1 BB36_27
v_add_nc_u32_e32 v1, 0x6600, v37
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_ushort v1, v[1:2], off
BB36_27:
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v2, 0
s_or_b32 s6, s1, 1
s_cmp_gt_u32 s6, 24
s_cbranch_scc1 BB36_29
v_add_nc_u32_e32 v2, 0x6800, v37
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_ushort v2, v[2:3], off
BB36_29:
s_or_b32 s6, s1, 2
s_cmp_gt_u32 s6, 24
s_cbranch_scc1 BB36_31
v_add_nc_u32_e32 v3, 0x6a00, v37
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 1, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
global_load_ushort v13, v[3:4], off
BB36_31:
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v3, 0
s_or_b32 s6, s1, 3
s_cmp_gt_u32 s6, 24
s_cbranch_scc0 BB36_79
s_add_i32 s6, s1, 4
s_cmp_gt_u32 s6, 24
s_cbranch_scc0 BB36_80
BB36_33:
s_andn2_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz BB36_71
BB36_34:
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v21, 0
s_cmp_gt_u32 s3, 24
s_cbranch_scc1 BB36_36
v_add_nc_u32_e32 v9, 0x9600, v37
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 1, v[9:10]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s8, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
global_load_ushort v21, v[9:10], off
BB36_36:
s_cmp_gt_u32 s1, 24
s_cbranch_scc1 BB36_38
v_add_nc_u32_e32 v8, 0x9800, v37
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 1, v[8:9]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_load_ushort v8, v[8:9], off
BB36_38:
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v9, 0
s_or_b32 s6, s1, 1
s_cmp_gt_u32 s6, 24
s_cbranch_scc1 BB36_40
v_add_nc_u32_e32 v9, 0x9a00, v37
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 1, v[9:10]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s8, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
global_load_ushort v9, v[9:10], off
BB36_40:
s_or_b32 s6, s1, 2
s_cmp_gt_u32 s6, 24
s_cbranch_scc1 BB36_42
v_add_nc_u32_e32 v10, 0x9c00, v37
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 1, v[10:11]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
global_load_ushort v22, v[10:11], off
BB36_42:
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_or_b32 s6, s1, 3
s_cmp_gt_u32 s6, 24
s_cbranch_scc0 BB36_81
s_add_i32 s6, s1, 4
s_cmp_gt_u32 s6, 24
s_cbranch_scc0 BB36_82
BB36_44:
s_andn2_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz BB36_72
BB36_45:
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v26, 0
s_cmp_gt_u32 s3, 24
s_cbranch_scc1 BB36_47
v_add_nc_u32_e32 v18, 0xc800, v37
v_ashrrev_i32_e32 v19, 31, v18
v_lshlrev_b64 v[18:19], 1, v[18:19]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v18, vcc_lo, s8, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s9, v19, vcc_lo
global_load_ushort v26, v[18:19], off
BB36_47:
s_cmp_gt_u32 s1, 24
s_cbranch_scc1 BB36_49
v_add_nc_u32_e32 v18, 0xca00, v37
v_ashrrev_i32_e32 v19, 31, v18
v_lshlrev_b64 v[18:19], 1, v[18:19]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v18, vcc_lo, s8, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s9, v19, vcc_lo
global_load_ushort v14, v[18:19], off
BB36_49:
v_mov_b32_e32 v29, 0
v_mov_b32_e32 v18, 0
s_or_b32 s0, s1, 1
s_cmp_gt_u32 s0, 24
s_cbranch_scc1 BB36_51
v_add_nc_u32_e32 v18, 0xcc00, v37
v_ashrrev_i32_e32 v19, 31, v18
v_lshlrev_b64 v[18:19], 1, v[18:19]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v18, vcc_lo, s8, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s9, v19, vcc_lo
global_load_ushort v18, v[18:19], off
BB36_51:
s_or_b32 s0, s1, 2
s_cmp_gt_u32 s0, 24
s_cbranch_scc1 BB36_53
v_add_nc_u32_e32 v19, 0xce00, v37
v_ashrrev_i32_e32 v20, 31, v19
v_lshlrev_b64 v[19:20], 1, v[19:20]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v19, vcc_lo, s8, v19
v_add_co_ci_u32_e32 v20, vcc_lo, s9, v20, vcc_lo
global_load_ushort v29, v[19:20], off
BB36_53:
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v20, 0
s_or_b32 s0, s1, 3
s_cmp_gt_u32 s0, 24
s_cbranch_scc0 BB36_83
s_add_i32 s0, s1, 4
s_cmp_gt_u32 s0, 24
s_cbranch_scc0 BB36_84
BB36_55:
v_add_nc_u32_e32 v23, 4, v23
v_cmp_lt_u32_e32 vcc_lo, 23, v23
s_and_b32 vcc_lo, exec_lo, vcc_lo
s_cbranch_vccnz BB36_73
BB36_56:
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v30, 0
s_cmp_gt_u32 s3, 24
s_cbranch_scc1 BB36_58
v_add_nc_u32_e32 v24, 0xfa00, v37
v_ashrrev_i32_e32 v25, 31, v24
v_lshlrev_b64 v[24:25], 1, v[24:25]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v24, vcc_lo, s8, v24
v_add_co_ci_u32_e32 v25, vcc_lo, s9, v25, vcc_lo
global_load_ushort v30, v[24:25], off
BB36_58:
s_cmp_gt_u32 s1, 24
s_cbranch_scc1 BB36_60
v_add_nc_u32_e32 v23, 0xfc00, v37
v_ashrrev_i32_e32 v24, 31, v23
v_lshlrev_b64 v[23:24], 1, v[23:24]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v23, vcc_lo, s8, v23
v_add_co_ci_u32_e32 v24, vcc_lo, s9, v24, vcc_lo
global_load_ushort v23, v[23:24], off
BB36_60:
v_mov_b32_e32 v24, 0
v_mov_b32_e32 v25, 0
s_or_b32 s0, s1, 1
s_cmp_gt_u32 s0, 24
s_cbranch_scc1 BB36_62
v_add_nc_u32_e32 v27, 0xfe00, v37
v_ashrrev_i32_e32 v28, 31, v27
v_lshlrev_b64 v[27:28], 1, v[27:28]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v27, vcc_lo, s8, v27
v_add_co_ci_u32_e32 v28, vcc_lo, s9, v28, vcc_lo
global_load_ushort v25, v[27:28], off
BB36_62:
s_or_b32 s0, s1, 2
s_cmp_gt_u32 s0, 24
s_cbranch_scc1 BB36_64
v_add_nc_u32_e32 v27, 0x10000, v37
v_ashrrev_i32_e32 v28, 31, v27
v_lshlrev_b64 v[27:28], 1, v[27:28]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v27, vcc_lo, s8, v27
v_add_co_ci_u32_e32 v28, vcc_lo, s9, v28, vcc_lo
global_load_ushort v24, v[27:28], off
BB36_64:
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v28, 0
s_or_b32 s0, s1, 3
s_cmp_gt_u32 s0, 24
s_cbranch_scc1 BB36_66
v_add_nc_u32_e32 v38, 0x10200, v37
v_ashrrev_i32_e32 v39, 31, v38
v_lshlrev_b64 v[38:39], 1, v[38:39]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v38, vcc_lo, s8, v38
v_add_co_ci_u32_e32 v39, vcc_lo, s9, v39, vcc_lo
global_load_ushort v28, v[38:39], off
BB36_66:
s_add_i32 s1, s1, 4
s_cmp_gt_u32 s1, 24
s_cbranch_scc1 BB36_74
v_add_nc_u32_e32 v37, 0x10400, v37
v_ashrrev_i32_e32 v38, 31, v37
v_lshlrev_b64 v[37:38], 1, v[37:38]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v37, vcc_lo, s8, v37
v_add_co_ci_u32_e32 v38, vcc_lo, s9, v38, vcc_lo
global_load_ushort v27, v[37:38], off
s_branch BB36_74
BB36_68:
v_mov_b32_e32 v33, 0
v_mov_b32_e32 v34, 0
v_mov_b32_e32 v31, 0
v_mov_b32_e32 v32, 0
v_mov_b32_e32 v35, 0
v_mov_b32_e32 v36, 0
v_cmp_gt_u32_e64 s0, 24, v23
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz BB36_12
BB36_69:
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v16, 0
s_andn2_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz BB36_23
BB36_70:
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v12, 0
s_andn2_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz BB36_34
BB36_71:
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v21, 0
s_andn2_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz BB36_45
BB36_72:
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v29, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v26, 0
v_add_nc_u32_e32 v23, 4, v23
v_cmp_lt_u32_e32 vcc_lo, 23, v23
s_and_b32 vcc_lo, exec_lo, vcc_lo
s_cbranch_vccz BB36_56
BB36_73:
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v28, 0
v_mov_b32_e32 v24, 0
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v30, 0
BB36_74:
s_waitcnt vmcnt(0)
v_add_f16_e32 v36, 0, v36
s_mov_b32 s1, 0xbe00
s_movk_i32 s0, 0x3e00
v_add_f16_e32 v37, 0, v35
v_mul_f16_e32 v45, s1, v15
v_fmac_f16_e32 v36, s1, v35
s_lshl_b32 s6, s2, 9
s_mov_b32 s2, 0xc100
v_mov_b32_e32 v46, v37
v_sub_f16_e32 v41, 0, v35
v_fmac_f16_e32 v36, -2.0, v32
v_fma_f16 v42, v35, -2.0, 0
v_mul_f16_e32 v47, s1, v17
v_fmac_f16_e32 v46, s2, v32
v_fmac_f16_e32 v41, 0.5, v32
v_fmac_f16_e32 v36, s0, v31
s_movk_i32 s3, 0x4100
v_mul_f16_e32 v38, -2.0, v1
v_fmac_f16_e32 v46, 0.5, v31
v_fmac_f16_e32 v41, s3, v31
v_add_f16_e32 v43, v36, v34
v_fma_f16 v36, v35, 0.5, 0
v_add3_u32 v35, s6, s7, v0
v_mul_f16_e32 v0, s1, v5
v_add_f16_e32 v46, v46, v34
v_fmac_f16_e32 v43, s1, v16
v_sub_f16_e32 v42, v42, v32
v_add_f16_e32 v41, v41, v34
v_mul_f16_e32 v39, -2.0, v2
v_fmac_f16_e32 v46, s1, v15
v_fmac_f16_e32 v43, s1, v45
v_sub_f16_e32 v52, v36, v32
v_fmac_f16_e32 v37, s1, v32
v_ashrrev_i32_e32 v36, 31, v35
v_fmac_f16_e32 v46, s2, v0
v_fmac_f16_e32 v43, -2.0, v0
v_fmac_f16_e32 v42, 2.0, v31
v_fmac_f16_e32 v41, s0, v15
v_mul_f16_e32 v40, -2.0, v13
v_fmac_f16_e32 v46, 0.5, v47
v_fmac_f16_e32 v43, s0, v47
v_fmac_f16_e32 v37, -2.0, v31
v_fmac_f16_e32 v52, -0.5, v31
v_lshlrev_b64 v[31:32], 1, v[35:36]
v_fmac_f16_e32 v46, s1, v7
v_fmac_f16_e32 v43, s1, v7
v_add_f16_e32 v35, v42, v34
v_fmac_f16_e32 v41, 0.5, v0
v_mul_f16_e32 v48, s0, v8
v_fmac_f16_e32 v46, -2.0, v1
v_fmac_f16_e32 v43, -2.0, v12
v_fmac_f16_e32 v35, -2.0, v45
v_fmac_f16_e32 v41, s3, v47
v_mul_f16_e32 v49, s0, v9
v_fmac_f16_e32 v46, s2, v39
v_fmac_f16_e32 v43, s1, v38
v_fmac_f16_e32 v35, s0, v5
v_fmac_f16_e32 v41, s1, v7
v_mul_f16_e32 v50, s0, v22
v_fmac_f16_e32 v46, 0.5, v40
v_fmac_f16_e32 v43, -2.0, v39
v_fmac_f16_e32 v35, 2.0, v47
v_fmac_f16_e32 v41, 2.0, v1
v_fmac_f16_e32 v37, s0, v34
v_fmac_f16_e32 v46, -2.0, v3
v_fmac_f16_e32 v43, s0, v40
v_fmac_f16_e32 v35, s1, v7
v_fmac_f16_e32 v41, 0.5, v39
v_add_f16_e32 v42, v37, v33
v_fmac_f16_e32 v46, s0, v8
v_fmac_f16_e32 v43, -2.0, v3
v_fmac_f16_e32 v35, -2.0, v38
v_fmac_f16_e32 v41, s3, v40
v_fmac_f16_e32 v42, s1, v15
v_fmac_f16_e32 v46, s2, v49
v_fmac_f16_e32 v43, s0, v21
v_fmac_f16_e32 v35, 2.0, v2
v_fmac_f16_e32 v41, -2.0, v3
v_add_f16_e32 v44, 0, v16
v_fmac_f16_e32 v46, 0.5, v50
v_fmac_f16_e32 v43, s1, v48
v_fmac_f16_e32 v35, 2.0, v40
v_fmac_f16_e32 v41, s1, v8
v_add_f16_e32 v36, v52, v34
v_fmac_f16_e32 v46, s0, v11
v_fmac_f16_e32 v43, -2.0, v49
v_fmac_f16_e32 v35, -2.0, v3
v_fmac_f16_e32 v41, 0.5, v49
v_fmac_f16_e32 v42, s1, v0
v_fmac_f16_e32 v36, 0.5, v45
v_fmac_f16_e32 v43, s0, v50
v_fmac_f16_e32 v35, -2.0, v48
v_fmac_f16_e32 v44, s1, v15
v_fmac_f16_e32 v41, s3, v50
v_mul_f16_e32 v51, s1, v7
v_fmac_f16_e32 v43, s0, v11
v_fmac_f16_e32 v42, -2.0, v47
s_waitcnt lgkmcnt(0)
v_add_co_u32 v31, vcc_lo, s4, v31
v_fmac_f16_e32 v35, s1, v9
v_fmac_f16_e32 v44, -2.0, v5
v_add_f16_e32 v37, v43, v26
v_add_f16_e32 v43, v46, v14
v_add_co_ci_u32_e32 v32, vcc_lo, s5, v32, vcc_lo
v_fmac_f16_e32 v36, s0, v5
v_fmac_f16_e32 v41, s0, v11
v_fmac_f16_e32 v37, s1, v14
v_fmac_f16_e32 v43, s2, v18
v_fmac_f16_e32 v42, s0, v51
v_add_co_u32 v33, vcc_lo, 0xa800, v31
v_fmac_f16_e32 v35, 2.0, v50
v_fmac_f16_e32 v37, -2.0, v18
v_fmac_f16_e32 v43, 0.5, v29
v_fmac_f16_e32 v36, -0.5, v47
v_sub_f16_e32 v0, v41, v14
v_fmac_f16_e32 v44, s0, v17
v_fmac_f16_e32 v37, s0, v29
v_add_f16_e32 v41, v43, v20
v_add_co_ci_u32_e32 v34, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v42, s1, v6
v_fmac_f16_e32 v35, s0, v11
v_add_f16_e32 v37, v37, v20
v_fmac_f16_e32 v36, s1, v7
v_fmac_f16_e32 v0, 0.5, v18
v_fmac_f16_e32 v42, -2.0, v1
global_store_short v[33:34], v41, off
global_store_short v[31:32], v37, off
v_add_f16_e32 v37, v44, v7
v_fmac_f16_e32 v35, -2.0, v14
v_fmac_f16_e32 v36, 0.5, v38
v_fmac_f16_e32 v42, s1, v39
v_fmac_f16_e32 v0, s3, v29
v_mov_b32_e32 v38, v37
v_sub_f16_e32 v35, v35, v18
v_mul_f16_e32 v43, s2, v1
v_add_co_u32 v33, vcc_lo, 0x15000, v31
v_fmac_f16_e32 v36, 2.0, v2
v_fmac_f16_e32 v38, s2, v12
v_fmac_f16_e32 v42, -2.0, v40
v_mul_f16_e32 v39, -2.0, v3
v_add_f16_e32 v0, v0, v20
v_add_co_ci_u32_e32 v34, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v35, 2.0, v29
v_add_f16_e32 v46, 0, v15
v_fmac_f16_e32 v38, s1, v43
v_mul_f16_e32 v44, s2, v2
v_fmac_f16_e32 v36, -0.5, v40
v_fmac_f16_e32 v42, s0, v39
global_store_short v[33:34], v0, off
v_add_f16_e32 v0, v35, v20
v_mov_b32_e32 v35, v46
v_fmac_f16_e32 v38, -2.0, v44
v_mul_f16_e32 v45, s2, v13
v_fmac_f16_e32 v36, -2.0, v3
v_fmac_f16_e32 v42, -2.0, v4
v_fmac_f16_e32 v35, s2, v5
v_add_co_u32 v33, vcc_lo, 0x1f800, v31
v_fmac_f16_e32 v38, s0, v45
v_fmac_f16_e32 v36, 0.5, v48
v_fmac_f16_e32 v42, s0, v8
v_add_co_ci_u32_e32 v34, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v35, 0.5, v17
v_fmac_f16_e32 v38, s2, v3
v_fmac_f16_e32 v36, s1, v9
v_fmac_f16_e32 v42, s1, v49
global_store_short v[33:34], v0, off
v_add_f16_e32 v0, v35, v7
v_fmac_f16_e32 v38, 0.5, v21
v_mul_f16_e32 v47, 0.5, v8
v_fmac_f16_e32 v36, -0.5, v50
v_fmac_f16_e32 v42, -2.0, v50
v_mul_f16_e32 v33, s0, v11
v_sub_f16_e32 v50, 0, v15
v_mov_b32_e32 v49, v0
v_fmac_f16_e32 v38, s1, v47
v_mul_f16_e32 v48, 0.5, v9
v_fmac_f16_e32 v42, s0, v33
v_mov_b32_e32 v33, v50
v_fmac_f16_e32 v36, s0, v11
v_fmac_f16_e32 v49, s2, v1
v_fmac_f16_e32 v38, -2.0, v48
v_mul_f16_e32 v51, 0.5, v22
v_fmac_f16_e32 v33, 0.5, v5
v_fmac_f16_e32 v36, 0.5, v14
v_fmac_f16_e32 v49, s2, v44
v_fmac_f16_e32 v42, s0, v10
v_fmac_f16_e32 v38, s0, v51
v_fmac_f16_e32 v33, s3, v17
v_sub_f16_e32 v34, v36, v18
v_fmac_f16_e32 v49, 0.5, v45
v_add_f16_e32 v36, v14, v42
v_fmac_f16_e32 v38, 0.5, v11
v_add_f16_e32 v33, v33, v7
v_fmac_f16_e32 v34, -0.5, v29
v_fmac_f16_e32 v49, s2, v3
v_fmac_f16_e32 v36, s1, v18
v_add_f16_e32 v38, v38, v26
v_mov_b32_e32 v42, v33
v_add_f16_e32 v39, v34, v20
v_add_co_u32 v34, vcc_lo, 0x2a000, v31
v_fmac_f16_e32 v49, 0.5, v8
v_fmac_f16_e32 v38, s1, v14
v_add_co_ci_u32_e32 v35, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v36, -2.0, v29
v_fmac_f16_e32 v42, s3, v1
v_fmac_f16_e32 v49, s2, v48
v_fmac_f16_e32 v38, -2.0, v18
global_store_short v[34:35], v39, off
v_fma_f16 v39, v15, -2.0, 0
v_fmac_f16_e32 v42, 0.5, v44
v_fmac_f16_e32 v36, s0, v20
v_fmac_f16_e32 v49, 0.5, v51
v_fmac_f16_e32 v38, s0, v29
v_sub_f16_e32 v34, v39, v5
v_add_co_u32 v35, vcc_lo, 0x34800, v31
v_fmac_f16_e32 v42, s3, v45
v_add_f16_e32 v52, v19, v36
v_add_co_ci_u32_e32 v36, vcc_lo, 0, v32, vcc_lo
v_add_co_u32 v40, vcc_lo, 0x3f000, v31
v_fmac_f16_e32 v49, 0.5, v11
v_fmac_f16_e32 v34, 2.0, v17
v_add_f16_e32 v38, v38, v20
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v42, s2, v3
v_add_f16_e32 v49, v49, v14
v_add_f16_e32 v34, v34, v7
global_store_short v[35:36], v52, off
global_store_short v[40:41], v38, off
v_mov_b32_e32 v36, v46
v_fmac_f16_e32 v42, -0.5, v8
v_fmac_f16_e32 v49, s2, v18
v_fma_f16 v38, v15, 0.5, 0
v_mov_b32_e32 v52, v34
v_fmac_f16_e32 v36, s1, v5
v_fmac_f16_e32 v42, 0.5, v48
v_fmac_f16_e32 v49, 0.5, v29
v_sub_f16_e32 v35, v38, v5
v_fmac_f16_e32 v52, -2.0, v43
v_fmac_f16_e32 v36, -2.0, v17
v_fmac_f16_e32 v42, s3, v51
v_add_co_u32 v40, vcc_lo, 0x49800, v31
v_fmac_f16_e32 v35, -0.5, v17
v_add_f16_e32 v49, v49, v20
v_fmac_f16_e32 v36, s0, v7
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v52, s3, v2
v_fmac_f16_e32 v42, 0.5, v11
v_add_f16_e32 v35, v35, v7
v_add_f16_e32 v36, v36, v6
global_store_short v[40:41], v49, off
v_sub_f16_e32 v41, 0, v16
v_fmac_f16_e32 v52, 2.0, v45
v_sub_f16_e32 v40, v42, v14
v_mov_b32_e32 v42, v36
v_mov_b32_e32 v49, v35
v_fmac_f16_e32 v41, s0, v15
v_fmac_f16_e32 v52, s2, v3
v_fmac_f16_e32 v40, 0.5, v18
v_fmac_f16_e32 v42, s2, v1
v_fmac_f16_e32 v49, 0.5, v43
v_fmac_f16_e32 v41, 2.0, v5
v_fmac_f16_e32 v52, -2.0, v47
v_fmac_f16_e32 v40, s3, v29
v_fmac_f16_e32 v42, s1, v44
v_fmac_f16_e32 v49, s3, v2
v_fmac_f16_e32 v41, s1, v17
v_fmac_f16_e32 v52, -0.5, v9
v_add_f16_e32 v43, v40, v20
v_add_co_u32 v40, vcc_lo, 0x54000, v31
v_fmac_f16_e32 v49, -0.5, v45
v_fmac_f16_e32 v42, -2.0, v45
v_sub_f16_e32 v45, v41, v7
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v52, 2.0, v51
v_mul_f16_e32 v44, s2, v3
v_fmac_f16_e32 v49, s2, v3
v_fmac_f16_e32 v45, 0.5, v12
global_store_short v[40:41], v43, off
v_mov_b32_e32 v43, v50
v_fmac_f16_e32 v42, s0, v44
v_fmac_f16_e32 v52, 0.5, v11
v_mul_f16_e32 v44, 0.5, v1
v_fmac_f16_e32 v49, 0.5, v47
v_fmac_f16_e32 v43, s3, v5
v_mul_f16_e32 v47, 0.5, v2
v_fmac_f16_e32 v52, -2.0, v14
v_fmac_f16_e32 v45, s1, v44
v_fmac_f16_e32 v42, s2, v4
v_fmac_f16_e32 v43, -0.5, v17
v_fmac_f16_e32 v49, -0.5, v9
v_sub_f16_e32 v40, v52, v18
v_fmac_f16_e32 v45, -2.0, v47
v_mul_f16_e32 v52, 0.5, v13
v_sub_f16_e32 v43, v43, v7
v_fmac_f16_e32 v42, 0.5, v8
v_fmac_f16_e32 v49, -0.5, v51
v_fmac_f16_e32 v40, 2.0, v29
v_fmac_f16_e32 v45, s0, v52
v_fmac_f16_e32 v43, 0.5, v1
v_fmac_f16_e32 v42, s1, v48
v_fmac_f16_e32 v46, -0.5, v5
v_fmac_f16_e32 v49, 0.5, v11
v_fmac_f16_e32 v45, 0.5, v3
v_fmac_f16_e32 v43, s2, v47
v_fmac_f16_e32 v42, -2.0, v51
v_mul_f16_e32 v48, 0.5, v11
v_mul_f16_e32 v51, s3, v8
v_fmac_f16_e32 v45, s3, v21
v_add_f16_e32 v53, v40, v20
v_add_co_u32 v40, vcc_lo, 0x5e800, v31
v_fmac_f16_e32 v43, 0.5, v52
v_fmac_f16_e32 v46, s2, v17
v_fmac_f16_e32 v42, s0, v48
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v49, 0.5, v14
v_fmac_f16_e32 v45, s1, v51
v_mul_f16_e32 v48, s3, v9
v_fmac_f16_e32 v43, 0.5, v3
v_sub_f16_e32 v46, v46, v7
global_store_short v[40:41], v53, off
v_sub_f16_e32 v40, v49, v18
v_fmac_f16_e32 v45, -2.0, v48
v_mul_f16_e32 v49, s3, v22
v_fmac_f16_e32 v42, 0.5, v10
v_fmac_f16_e32 v43, s3, v8
v_fmac_f16_e32 v46, -0.5, v1
v_fmac_f16_e32 v40, -0.5, v29
v_fmac_f16_e32 v45, s0, v49
v_add_f16_e32 v42, v14, v42
v_fmac_f16_e32 v43, s2, v48
v_fmac_f16_e32 v46, 0.5, v47
v_add_f16_e32 v53, v40, v20
v_add_co_u32 v40, vcc_lo, 0x69000, v31
v_fmac_f16_e32 v45, s3, v11
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v42, s1, v18
v_fmac_f16_e32 v43, 0.5, v49
v_fmac_f16_e32 v46, s3, v52
v_add_f16_e32 v45, v45, v26
global_store_short v[40:41], v53, off
v_fma_f16 v53, v15, 2.0, 0
v_fmac_f16_e32 v42, -2.0, v29
v_fmac_f16_e32 v43, s3, v11
v_fmac_f16_e32 v46, 0.5, v3
v_fmac_f16_e32 v45, s1, v14
v_add_f16_e32 v54, v53, v5
v_fmac_f16_e32 v42, s0, v20
v_add_f16_e32 v43, v43, v14
v_fmac_f16_e32 v46, s2, v8
v_fmac_f16_e32 v45, -2.0, v18
v_add_co_u32 v40, vcc_lo, 0x73800, v31
v_fmac_f16_e32 v54, -2.0, v17
v_add_f16_e32 v42, v19, v42
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v43, s2, v18
v_fmac_f16_e32 v46, 0.5, v48
v_fmac_f16_e32 v45, s0, v29
v_fmac_f16_e32 v50, s0, v5
v_sub_f16_e32 v54, v54, v7
global_store_short v[40:41], v42, off
v_add_co_u32 v40, vcc_lo, 0x7e000, v31
v_fmac_f16_e32 v46, s3, v49
v_fmac_f16_e32 v43, 0.5, v29
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v50, 2.0, v17
v_add_f16_e32 v45, v45, v20
v_fmac_f16_e32 v54, -2.0, v44
v_add_co_u32 v42, vcc_lo, 0x88800, v31
v_add_f16_e32 v55, v43, v20
v_add_co_ci_u32_e32 v43, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v46, s3, v11
global_store_short v[40:41], v45, off
v_fma_f16 v45, v15, -0.5, 0
v_fmac_f16_e32 v50, s1, v7
v_fmac_f16_e32 v54, -0.5, v2
global_store_short v[42:43], v55, off
v_sub_f16_e32 v40, v46, v14
v_fma_f16 v42, v16, -2.0, 0
v_mul_f16_e32 v46, -2.0, v15
v_sub_f16_e32 v43, v50, v6
v_add_f16_e32 v41, v45, v5
v_fmac_f16_e32 v54, 2.0, v52
v_mul_f16_e32 v50, -2.0, v5
v_fmac_f16_e32 v42, s1, v46
v_fmac_f16_e32 v43, 0.5, v1
v_fmac_f16_e32 v41, 0.5, v17
v_fmac_f16_e32 v54, 0.5, v3
v_mul_f16_e32 v55, -2.0, v17
v_fmac_f16_e32 v42, -2.0, v50
v_fmac_f16_e32 v43, s1, v47
v_sub_f16_e32 v56, v41, v7
v_fmac_f16_e32 v54, -2.0, v51
v_fmac_f16_e32 v40, 0.5, v18
v_fmac_f16_e32 v42, s0, v55
v_fmac_f16_e32 v43, -2.0, v52
v_fmac_f16_e32 v56, 0.5, v44
v_mul_f16_e32 v44, 0.5, v3
v_fmac_f16_e32 v54, s2, v9
v_fmac_f16_e32 v42, -2.0, v7
v_fmac_f16_e32 v40, s3, v29
v_fmac_f16_e32 v56, -0.5, v2
v_fmac_f16_e32 v43, s0, v44
v_mov_b32_e32 v44, v39
v_fmac_f16_e32 v54, 2.0, v49
v_sub_f16_e32 v42, v42, v12
v_add_f16_e32 v47, v40, v20
v_add_co_u32 v40, vcc_lo, 0x93000, v31
v_fmac_f16_e32 v44, s2, v50
v_fmac_f16_e32 v54, s3, v11
v_fmac_f16_e32 v42, s0, v1
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v56, -0.5, v52
v_fmac_f16_e32 v44, 0.5, v55
v_fmac_f16_e32 v54, -2.0, v14
v_fmac_f16_e32 v42, 2.0, v2
v_fmac_f16_e32 v43, 0.5, v4
global_store_short v[40:41], v47, off
v_fmac_f16_e32 v44, -2.0, v7
v_sub_f16_e32 v40, v54, v18
v_fmac_f16_e32 v42, s1, v13
v_fmac_f16_e32 v56, 0.5, v3
v_fmac_f16_e32 v43, s3, v8
v_sub_f16_e32 v44, v44, v1
v_fmac_f16_e32 v40, 2.0, v29
v_sub_f16_e32 v42, v42, v3
v_fmac_f16_e32 v53, 0.5, v50
v_fmac_f16_e32 v56, 0.5, v51
v_fmac_f16_e32 v44, s3, v2
v_fmac_f16_e32 v43, s1, v48
v_add_f16_e32 v47, v40, v20
v_add_co_u32 v40, vcc_lo, 0x9d800, v31
v_fmac_f16_e32 v53, s3, v55
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v42, 2.0, v21
v_add_f16_e32 v51, v8, v8
v_fmac_f16_e32 v44, -0.5, v13
v_fmac_f16_e32 v56, s2, v9
v_fmac_f16_e32 v43, -2.0, v49
v_mul_f16_e32 v48, s3, v11
global_store_short v[40:41], v47, off
v_fmac_f16_e32 v42, s1, v51
v_add_f16_e32 v47, v9, v9
v_fmac_f16_e32 v53, -2.0, v7
v_sub_f16_e32 v44, v44, v3
v_fmac_f16_e32 v56, -0.5, v49
v_fmac_f16_e32 v43, s0, v48
v_fmac_f16_e32 v42, -2.0, v47
v_add_f16_e32 v49, v53, v1
v_add_f16_e32 v48, v22, v22
v_fmac_f16_e32 v44, 2.0, v8
v_fmac_f16_e32 v56, s3, v11
v_fmac_f16_e32 v43, s3, v10
v_fmac_f16_e32 v49, -0.5, v2
v_fmac_f16_e32 v42, s0, v48
v_fmac_f16_e32 v44, s2, v47
v_fmac_f16_e32 v56, 0.5, v14
v_add_f16_e32 v43, v14, v43
v_fmac_f16_e32 v49, s2, v13
v_fmac_f16_e32 v42, 2.0, v11
v_fmac_f16_e32 v44, 0.5, v48
v_sub_f16_e32 v40, v56, v18
v_fmac_f16_e32 v43, s1, v18
v_sub_f16_e32 v49, v49, v3
v_add_f16_e32 v52, v42, v26
v_fmac_f16_e32 v44, 2.0, v11
v_fmac_f16_e32 v40, -0.5, v29
v_fmac_f16_e32 v43, -2.0, v29
v_fmac_f16_e32 v49, -2.0, v8
v_fmac_f16_e32 v52, s1, v14
v_add_f16_e32 v44, v44, v14
v_add_f16_e32 v53, v40, v20
v_add_co_u32 v40, vcc_lo, 0xa8000, v31
v_fmac_f16_e32 v43, s0, v20
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v52, -2.0, v18
v_fmac_f16_e32 v49, 0.5, v47
v_add_co_u32 v42, vcc_lo, 0xb2800, v31
v_fmac_f16_e32 v44, s2, v18
v_add_f16_e32 v54, v19, v43
v_add_co_ci_u32_e32 v43, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v52, s0, v29
v_fmac_f16_e32 v49, s3, v48
v_fmac_f16_e32 v44, 0.5, v29
global_store_short v[40:41], v53, off
global_store_short v[42:43], v54, off
v_add_co_u32 v40, vcc_lo, 0xbd000, v31
v_add_f16_e32 v52, v52, v20
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v32, vcc_lo
v_add_co_u32 v42, vcc_lo, 0xc7800, v31
v_fmac_f16_e32 v49, 2.0, v11
v_add_f16_e32 v44, v44, v20
v_add_co_ci_u32_e32 v43, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v39, s1, v50
v_fma_f16 v53, v46, -2.0, 0
v_mul_f16_e32 v17, 0.5, v17
global_store_short v[40:41], v52, off
global_store_short v[42:43], v44, off
v_sub_f16_e32 v40, v49, v14
v_mul_f16_e32 v49, 0.5, v15
v_fma_f16 v42, v16, 0.5, 0
v_fmac_f16_e32 v39, -2.0, v55
v_mul_f16_e32 v41, -2.0, v7
v_fma_f16 v43, v46, 0.5, 0
v_fmac_f16_e32 v53, 2.0, v5
v_mul_f16_e32 v46, 0.5, v5
v_fmac_f16_e32 v42, s1, v49
v_fmac_f16_e32 v40, 0.5, v18
v_fmac_f16_e32 v39, s0, v41
v_fmac_f16_e32 v53, 2.0, v55
v_fmac_f16_e32 v43, 2.0, v5
v_fmac_f16_e32 v42, -2.0, v46
v_fmac_f16_e32 v40, s3, v29
v_fmac_f16_e32 v39, -2.0, v6
v_fmac_f16_e32 v53, -2.0, v7
v_add_co_u32 v15, vcc_lo, 0xd2000, v31
v_fmac_f16_e32 v42, s0, v17
v_add_f16_e32 v40, v40, v20
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v32, vcc_lo
v_sub_f16_e32 v39, v39, v1
v_fmac_f16_e32 v43, -0.5, v55
v_fmac_f16_e32 v53, 2.0, v1
v_fmac_f16_e32 v42, 0.5, v7
global_store_short v[15:16], v40, off
v_mov_b32_e32 v40, v38
v_fmac_f16_e32 v39, s0, v2
v_add_f16_e32 v41, v53, v2
v_sub_f16_e32 v15, v42, v12
v_fmac_f16_e32 v43, -2.0, v7
v_fmac_f16_e32 v40, s2, v46
v_fmac_f16_e32 v39, 2.0, v13
v_fmac_f16_e32 v41, -2.0, v13
v_fmac_f16_e32 v15, s0, v1
v_fmac_f16_e32 v43, -0.5, v1
v_fmac_f16_e32 v40, 0.5, v17
v_fmac_f16_e32 v39, s1, v3
v_sub_f16_e32 v16, v41, v3
v_fmac_f16_e32 v15, 2.0, v2
v_add_f16_e32 v41, v43, v2
v_fmac_f16_e32 v40, 0.5, v7
v_sub_f16_e32 v39, v39, v4
v_fmac_f16_e32 v16, -2.0, v51
v_fmac_f16_e32 v15, s1, v13
v_fmac_f16_e32 v41, 0.5, v13
v_sub_f16_e32 v40, v40, v1
v_fmac_f16_e32 v39, 2.0, v8
v_fmac_f16_e32 v16, -2.0, v9
v_sub_f16_e32 v15, v15, v3
v_sub_f16_e32 v41, v41, v3
v_fmac_f16_e32 v40, s3, v2
v_fmac_f16_e32 v39, s1, v47
v_mul_f16_e32 v47, -0.5, v8
v_fmac_f16_e32 v15, -0.5, v21
v_fmac_f16_e32 v41, 0.5, v51
v_fmac_f16_e32 v40, -0.5, v13
v_fmac_f16_e32 v39, -2.0, v48
v_add_f16_e32 v42, v11, v11
v_fmac_f16_e32 v15, s1, v47
v_fmac_f16_e32 v41, -2.0, v9
v_mul_f16_e32 v50, -0.5, v9
v_fmac_f16_e32 v16, 2.0, v48
v_sub_f16_e32 v40, v40, v3
v_fmac_f16_e32 v39, s0, v42
v_fmac_f16_e32 v41, -0.5, v48
v_mul_f16_e32 v48, -0.5, v22
v_fmac_f16_e32 v15, -2.0, v50
v_fmac_f16_e32 v16, 2.0, v11
v_fmac_f16_e32 v40, -0.5, v8
v_fmac_f16_e32 v39, 2.0, v10
v_fmac_f16_e32 v41, 2.0, v11
v_fmac_f16_e32 v15, s0, v48
v_fmac_f16_e32 v16, -2.0, v14
v_fmac_f16_e32 v40, s2, v50
v_add_f16_e32 v39, v14, v39
v_fmac_f16_e32 v41, 0.5, v14
v_fmac_f16_e32 v15, -0.5, v11
v_sub_f16_e32 v16, v16, v18
v_fmac_f16_e32 v40, 0.5, v48
v_fmac_f16_e32 v39, s1, v18
v_sub_f16_e32 v41, v41, v18
v_add_f16_e32 v43, v15, v26
v_fmac_f16_e32 v16, 2.0, v29
v_fmac_f16_e32 v40, -0.5, v11
v_fmac_f16_e32 v39, -2.0, v29
v_add_co_u32 v15, vcc_lo, 0xdc800, v31
v_fmac_f16_e32 v43, s1, v14
v_add_f16_e32 v42, v16, v20
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v32, vcc_lo
v_add_f16_e32 v44, v40, v14
v_fmac_f16_e32 v39, s0, v20
v_fmac_f16_e32 v43, -2.0, v18
v_fmac_f16_e32 v41, -0.5, v29
global_store_short v[15:16], v42, off
v_add_co_u32 v15, vcc_lo, 0xe7000, v31
v_fmac_f16_e32 v44, s2, v18
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v32, vcc_lo
v_add_f16_e32 v52, v19, v39
v_add_co_u32 v39, vcc_lo, 0xf1800, v31
v_fmac_f16_e32 v43, s0, v29
v_add_co_ci_u32_e32 v40, vcc_lo, 0, v32, vcc_lo
v_add_f16_e32 v51, v41, v20
v_add_co_u32 v41, vcc_lo, 0xfc000, v31
v_fmac_f16_e32 v44, 0.5, v29
v_add_co_ci_u32_e32 v42, vcc_lo, 0, v32, vcc_lo
v_add_f16_e32 v53, v43, v20
v_add_co_u32 v43, vcc_lo, 0x106800, v31
v_fmac_f16_e32 v38, s1, v46
v_add_f16_e32 v54, v44, v20
v_add_co_ci_u32_e32 v44, vcc_lo, 0, v32, vcc_lo
global_store_short v[15:16], v51, off
v_fmac_f16_e32 v37, s1, v12
global_store_short v[39:40], v52, off
global_store_short v[41:42], v53, off
global_store_short v[43:44], v54, off
v_mul_f16_e32 v39, s1, v1
v_fma_f16 v15, v49, -2.0, 0
v_fma_f16 v12, v49, 0.5, 0
v_fmac_f16_e32 v38, -2.0, v17
v_mul_f16_e32 v16, 0.5, v7
v_fmac_f16_e32 v37, s1, v39
v_mul_f16_e32 v40, s1, v2
v_fmac_f16_e32 v45, 0.5, v46
v_fmac_f16_e32 v15, -0.5, v5
v_fmac_f16_e32 v12, -0.5, v5
v_fmac_f16_e32 v38, s0, v16
v_fmac_f16_e32 v37, -2.0, v40
v_mul_f16_e32 v42, s1, v13
v_fmac_f16_e32 v45, s3, v17
v_fmac_f16_e32 v15, 2.0, v17
v_fmac_f16_e32 v12, -0.5, v17
v_fmac_f16_e32 v36, s1, v1
v_fmac_f16_e32 v38, 0.5, v6
v_fmac_f16_e32 v37, s0, v42
v_fmac_f16_e32 v15, 0.5, v7
v_fmac_f16_e32 v12, 0.5, v7
v_fmac_f16_e32 v36, s1, v40
v_fmac_f16_e32 v45, 0.5, v7
v_sub_f16_e32 v5, v38, v1
v_fmac_f16_e32 v0, s1, v1
v_fmac_f16_e32 v37, s1, v3
v_fmac_f16_e32 v12, -0.5, v1
v_add_f16_e32 v41, v45, v1
v_fmac_f16_e32 v33, s0, v1
v_fmac_f16_e32 v15, 2.0, v1
v_fmac_f16_e32 v36, -2.0, v42
v_mul_f16_e32 v1, s1, v3
v_fmac_f16_e32 v5, s0, v2
v_fmac_f16_e32 v0, s2, v40
v_fmac_f16_e32 v34, -2.0, v39
v_fmac_f16_e32 v37, -2.0, v21
v_mul_f16_e32 v17, -2.0, v8
v_fmac_f16_e32 v36, s0, v1
v_fmac_f16_e32 v41, -0.5, v2
v_fmac_f16_e32 v33, 0.5, v40
v_fmac_f16_e32 v5, 2.0, v13
v_fmac_f16_e32 v35, 0.5, v39
v_fmac_f16_e32 v0, 0.5, v42
v_fmac_f16_e32 v34, s0, v2
v_fmac_f16_e32 v37, s1, v17
v_mul_f16_e32 v21, -2.0, v9
v_add_f16_e32 v12, v12, v2
v_fmac_f16_e32 v36, s1, v4
v_add_f16_e32 v7, v15, v2
v_fmac_f16_e32 v33, s3, v42
v_fmac_f16_e32 v41, s2, v13
v_fmac_f16_e32 v5, s1, v3
v_fmac_f16_e32 v35, s0, v2
v_fmac_f16_e32 v0, s1, v3
v_fmac_f16_e32 v34, 2.0, v42
v_fmac_f16_e32 v37, -2.0, v21
v_mul_f16_e32 v22, -2.0, v22
v_fmac_f16_e32 v12, 0.5, v13
v_fmac_f16_e32 v36, -2.0, v8
v_sub_f16_e32 v6, v41, v3
v_fmac_f16_e32 v7, -2.0, v13
v_fmac_f16_e32 v33, s1, v3
v_sub_f16_e32 v5, v5, v4
v_fmac_f16_e32 v35, -0.5, v42
v_fmac_f16_e32 v0, -2.0, v8
v_fmac_f16_e32 v37, s0, v22
v_fmac_f16_e32 v34, s1, v3
v_sub_f16_e32 v12, v12, v3
v_fmac_f16_e32 v36, s1, v21
v_fmac_f16_e32 v6, 0.5, v8
v_sub_f16_e32 v7, v7, v3
v_fmac_f16_e32 v33, 2.0, v8
v_fmac_f16_e32 v5, -0.5, v8
v_fmac_f16_e32 v35, s1, v3
v_fmac_f16_e32 v0, s2, v21
v_fmac_f16_e32 v37, -2.0, v11
v_fmac_f16_e32 v34, -2.0, v17
v_fmac_f16_e32 v12, 0.5, v47
v_fmac_f16_e32 v36, -2.0, v22
v_mul_f16_e32 v1, -2.0, v11
v_fmac_f16_e32 v6, 0.5, v50
v_fmac_f16_e32 v7, -2.0, v47
v_fmac_f16_e32 v33, 0.5, v21
v_fmac_f16_e32 v5, s1, v50
v_fmac_f16_e32 v35, 0.5, v17
v_fmac_f16_e32 v0, 0.5, v22
v_fmac_f16_e32 v34, 2.0, v9
v_fmac_f16_e32 v37, s0, v26
v_mul_f16_e32 v26, s0, v14
v_fmac_f16_e32 v36, s0, v1
v_fmac_f16_e32 v12, 0.5, v9
v_fmac_f16_e32 v6, s3, v48
v_fmac_f16_e32 v7, 0.5, v9
v_fmac_f16_e32 v33, s3, v22
v_fmac_f16_e32 v35, 2.0, v9
v_fmac_f16_e32 v5, -2.0, v48
v_mul_f16_e32 v13, -0.5, v11
v_fmac_f16_e32 v0, -2.0, v11
v_fmac_f16_e32 v34, 2.0, v22
v_fmac_f16_e32 v37, s1, v26
v_mul_f16_e32 v38, s0, v18
v_fmac_f16_e32 v12, -0.5, v48
v_fmac_f16_e32 v36, -2.0, v10
v_fmac_f16_e32 v6, -0.5, v11
v_fmac_f16_e32 v7, 2.0, v48
v_fmac_f16_e32 v33, -2.0, v11
v_fmac_f16_e32 v5, s0, v13
v_fmac_f16_e32 v35, -0.5, v22
v_fmac_f16_e32 v0, s0, v14
v_fmac_f16_e32 v34, -2.0, v11
v_fmac_f16_e32 v37, -2.0, v38
v_mul_f16_e32 v41, s0, v29
v_fmac_f16_e32 v12, -0.5, v11
v_fmac_f16_e32 v36, s0, v14
v_sub_f16_e32 v6, v6, v14
v_fmac_f16_e32 v7, -0.5, v11
v_fmac_f16_e32 v33, s1, v14
v_fmac_f16_e32 v35, -2.0, v11
v_fmac_f16_e32 v5, -0.5, v10
v_fmac_f16_e32 v0, s2, v38
v_fmac_f16_e32 v37, s0, v41
v_fmac_f16_e32 v34, -2.0, v26
v_fmac_f16_e32 v36, s1, v38
v_fmac_f16_e32 v12, 0.5, v14
v_fmac_f16_e32 v6, 0.5, v18
v_fmac_f16_e32 v7, -2.0, v14
v_fmac_f16_e32 v33, 0.5, v38
v_add_f16_e32 v44, v14, v5
v_fmac_f16_e32 v35, 0.5, v26
v_fmac_f16_e32 v0, 0.5, v41
v_fmac_f16_e32 v34, s1, v18
v_fmac_f16_e32 v37, s0, v20
v_sub_f16_e32 v15, v12, v18
v_fmac_f16_e32 v36, -2.0, v41
v_mul_f16_e32 v1, s0, v20
v_sub_f16_e32 v7, v7, v18
v_fmac_f16_e32 v33, s3, v41
v_fmac_f16_e32 v6, s3, v29
v_fmac_f16_e32 v44, s1, v18
v_fmac_f16_e32 v35, s1, v18
v_fmac_f16_e32 v0, s0, v20
v_add_f16_e32 v30, v30, v37
v_fmac_f16_e32 v34, 2.0, v41
v_add_co_u32 v5, vcc_lo, 0x111000, v31
v_fmac_f16_e32 v36, s0, v1
v_fmac_f16_e32 v15, -0.5, v29
v_fmac_f16_e32 v7, 2.0, v29
v_add_f16_e32 v43, v6, v20
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v33, s0, v20
v_add_co_u32 v12, vcc_lo, 0x11b800, v31
v_fmac_f16_e32 v44, -2.0, v29
v_fmac_f16_e32 v35, -0.5, v41
v_add_f16_e32 v0, v0, v23
v_fmac_f16_e32 v30, s1, v23
v_fmac_f16_e32 v34, s0, v20
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v32, vcc_lo
v_add_f16_e32 v37, v15, v20
v_add_co_u32 v15, vcc_lo, 0x126000, v31
v_fmac_f16_e32 v36, s0, v19
v_sub_f16_e32 v2, v33, v23
v_add_f16_e32 v7, v7, v20
v_fmac_f16_e32 v35, s0, v20
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v32, vcc_lo
v_fmac_f16_e32 v44, s0, v20
v_fmac_f16_e32 v0, s2, v25
v_fmac_f16_e32 v30, -2.0, v25
v_fmac_f16_e32 v34, -2.0, v23
global_store_short v[5:6], v43, off
global_store_short v[12:13], v7, off
global_store_short v[15:16], v37, off
v_add_co_u32 v5, vcc_lo, 0x130800, v31
v_add_f16_e32 v8, v23, v36
v_fmac_f16_e32 v2, 0.5, v25
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v32, vcc_lo
v_add_f16_e32 v7, v19, v44
v_fmac_f16_e32 v35, 0.5, v23
v_fmac_f16_e32 v0, 0.5, v24
v_sub_f16_e32 v4, v34, v25
v_fmac_f16_e32 v30, s0, v24
v_add_co_u32 v12, vcc_lo, 0x13b000, v31
v_fmac_f16_e32 v8, s1, v25
v_fmac_f16_e32 v2, s3, v24
global_store_short v[5:6], v7, off
v_sub_f16_e32 v6, v35, v25
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v32, vcc_lo
v_add_f16_e32 v10, v0, v28
v_add_co_u32 v0, vcc_lo, 0x145800, v31
v_add_f16_e32 v15, v28, v30
v_fmac_f16_e32 v4, 2.0, v24
v_fmac_f16_e32 v8, -2.0, v24
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v32, vcc_lo
v_add_f16_e32 v11, v2, v28
v_add_co_u32 v2, vcc_lo, 0x150000, v31
v_fmac_f16_e32 v6, -0.5, v24
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v32, vcc_lo
global_store_short v[12:13], v15, off
v_add_f16_e32 v12, v4, v28
v_add_co_u32 v4, vcc_lo, 0x15a800, v31
v_fmac_f16_e32 v8, s0, v28
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v32, vcc_lo
v_add_f16_e32 v13, v6, v28
v_add_co_u32 v6, vcc_lo, 0x165000, v31
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v32, vcc_lo
v_add_f16_e32 v14, v27, v8
v_add_co_u32 v8, vcc_lo, 0x16f800, v31
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v32, vcc_lo
global_store_short v[0:1], v10, off
global_store_short v[2:3], v11, off
global_store_short v[4:5], v12, off
global_store_short v[6:7], v13, off
global_store_short v[8:9], v14, off
s_endpgm
BB36_75:
v_add_nc_u32_e32 v1, 0x800, v37
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_ushort v34, v[1:2], off
s_add_i32 s0, s1, 4
s_cmp_gt_u32 s0, 24
s_cbranch_scc1 BB36_11
BB36_76:
v_add_nc_u32_e32 v1, 0xa00, v37
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_ushort v33, v[1:2], off
v_cmp_gt_u32_e64 s0, 24, v23
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz BB36_12
s_branch BB36_69
BB36_77:
v_add_nc_u32_e32 v1, 0x3a00, v37
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_ushort v7, v[1:2], off
s_add_i32 s6, s1, 4
s_cmp_gt_u32 s6, 24
s_cbranch_scc1 BB36_22
BB36_78:
v_add_nc_u32_e32 v1, 0x3c00, v37
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_ushort v6, v[1:2], off
s_andn2_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz BB36_23
s_branch BB36_70
BB36_79:
v_add_nc_u32_e32 v8, 0x6c00, v37
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 1, v[8:9]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_load_ushort v3, v[8:9], off
s_add_i32 s6, s1, 4
s_cmp_gt_u32 s6, 24
s_cbranch_scc1 BB36_33
BB36_80:
v_add_nc_u32_e32 v8, 0x6e00, v37
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 1, v[8:9]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_load_ushort v4, v[8:9], off
s_andn2_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz BB36_34
s_branch BB36_71
BB36_81:
v_add_nc_u32_e32 v18, 0x9e00, v37
v_ashrrev_i32_e32 v19, 31, v18
v_lshlrev_b64 v[18:19], 1, v[18:19]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v18, vcc_lo, s8, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s9, v19, vcc_lo
global_load_ushort v11, v[18:19], off
s_add_i32 s6, s1, 4
s_cmp_gt_u32 s6, 24
s_cbranch_scc1 BB36_44
BB36_82:
v_add_nc_u32_e32 v18, 0xa000, v37
v_ashrrev_i32_e32 v19, 31, v18
v_lshlrev_b64 v[18:19], 1, v[18:19]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v18, vcc_lo, s8, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s9, v19, vcc_lo
global_load_ushort v10, v[18:19], off
s_andn2_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz BB36_45
s_branch BB36_72
BB36_83:
v_add_nc_u32_e32 v24, 0xd000, v37
v_ashrrev_i32_e32 v25, 31, v24
v_lshlrev_b64 v[24:25], 1, v[24:25]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v24, vcc_lo, s8, v24
v_add_co_ci_u32_e32 v25, vcc_lo, s9, v25, vcc_lo
global_load_ushort v20, v[24:25], off
s_add_i32 s0, s1, 4
s_cmp_gt_u32 s0, 24
s_cbranch_scc1 BB36_55
BB36_84:
v_add_nc_u32_e32 v24, 0xd200, v37
v_ashrrev_i32_e32 v25, 31, v24
v_lshlrev_b64 v[24:25], 1, v[24:25]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v24, vcc_lo, s8, v24
v_add_co_ci_u32_e32 v25, vcc_lo, s9, v25, vcc_lo
global_load_ushort v19, v[24:25], off
v_add_nc_u32_e32 v23, 4, v23
v_cmp_lt_u32_e32 vcc_lo, 23, v23
s_and_b32 vcc_lo, exec_lo, vcc_lo
s_cbranch_vccz BB36_56
s_branch BB36_73
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 57
.amdhsa_next_free_sgpr 10
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end36:
.size tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel0, .Lfunc_end36-tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel0
.globl tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel1
.p2align 8
.type tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel1,@function
tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel1:
v_lshlrev_b32_e32 v2, 3, v0
s_mov_b32 s0, 0x30c30c31
s_mul_hi_i32 s1, s6, 0x2aaaaaab
v_mul_hi_i32 v1, v0, s0
s_lshr_b32 s2, s1, 31
v_or_b32_e32 v4, 1, v2
v_or_b32_e32 v7, 2, v2
s_ashr_i32 s1, s1, 1
s_movk_i32 s12, 0x540
s_add_i32 s13, s1, s2
v_mul_hi_i32 v6, v4, s0
v_lshrrev_b32_e32 v5, 31, v1
v_ashrrev_i32_e32 v1, 5, v1
v_mul_hi_i32 v9, v7, s0
s_clause 0x2
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_mul_i32 s4, s13, 12
s_mov_b32 s7, 0x1f800
v_add_nc_u32_e32 v1, v1, v5
v_lshrrev_b32_e32 v8, 31, v6
v_ashrrev_i32_e32 v6, 8, v6
s_sub_i32 s14, s6, s4
v_lshrrev_b32_e32 v11, 31, v9
v_mul_lo_u32 v5, 0xa8, v1
v_ashrrev_i32_e32 v9, 8, v9
v_add_nc_u32_e32 v6, v6, v8
v_mul_lo_u32 v1, v1, s7
v_or_b32_e32 v12, 3, v2
s_ashr_i32 s4, s14, 1
s_mul_i32 s1, s13, 0x3f000
v_mul_i32_i24_e32 v10, s12, v6
v_sub_nc_u32_e32 v5, v0, v5
s_mulk_i32 s4, 0x5400
v_add_nc_u32_e32 v9, v9, v11
v_mul_hi_i32 v11, v12, s0
v_sub_nc_u32_e32 v10, v4, v10
v_or_b32_e32 v14, 4, v2
s_add_i32 s5, s4, s1
v_lshlrev_b32_e32 v5, 7, v5
v_and_b32_e32 v4, 25, v4
v_mov_b32_e32 v3, 0xfffffe00
v_lshlrev_b32_e32 v10, 4, v10
v_and_b32_e32 v8, 24, v2
v_add_nc_u32_e32 v1, s5, v1
v_mul_hi_i32 v16, v14, s0
v_mul_i32_i24_e32 v13, s12, v9
v_lshrrev_b32_e32 v17, 31, v11
v_and_b32_e32 v5, 0xfffffe00, v5
v_or_b32_e32 v1, v1, v8
v_and_b32_e32 v10, v3, v10
v_mul_i32_i24_e32 v6, s7, v6
v_or_b32_e32 v15, s5, v4
v_ashrrev_i32_e32 v11, 8, v11
v_sub_nc_u32_e32 v13, v7, v13
v_add_nc_u32_e32 v24, v1, v5
v_and_b32_e32 v7, 26, v7
v_add3_u32 v28, v15, v6, v10
v_add_nc_u32_e32 v5, v11, v17
v_lshrrev_b32_e32 v6, 31, v16
v_ashrrev_i32_e32 v10, 8, v16
v_lshlrev_b32_e32 v1, 4, v13
v_or_b32_e32 v13, 5, v2
v_mul_i32_i24_e32 v11, s12, v5
v_mul_i32_i24_e32 v9, s7, v9
v_add_nc_u32_e32 v6, v10, v6
v_and_b32_e32 v1, v3, v1
v_or_b32_e32 v10, s5, v7
v_sub_nc_u32_e32 v11, v12, v11
v_mul_hi_i32 v15, v13, s0
v_mul_i32_i24_e32 v16, s12, v6
v_or_b32_e32 v17, 6, v2
v_add3_u32 v30, v10, v9, v1
v_lshlrev_b32_e32 v9, 4, v11
v_and_b32_e32 v1, 27, v12
v_sub_nc_u32_e32 v10, v14, v16
v_or_b32_e32 v16, 7, v2
v_mul_hi_i32 v11, v17, s0
v_lshrrev_b32_e32 v12, 31, v15
v_ashrrev_i32_e32 v15, 8, v15
v_lshlrev_b32_e32 v10, 4, v10
v_mul_hi_i32 v18, v16, s0
v_and_b32_e32 v14, 28, v14
v_and_b32_e32 v9, v3, v9
v_add_nc_u32_e32 v12, v15, v12
v_lshrrev_b32_e32 v15, 31, v11
v_ashrrev_i32_e32 v11, 8, v11
v_mul_i32_i24_e32 v5, s7, v5
v_or_b32_e32 v19, s5, v1
v_and_b32_e32 v10, v3, v10
v_mul_i32_i24_e32 v6, s7, v6
v_add_nc_u32_e32 v11, v11, v15
v_lshrrev_b32_e32 v15, 31, v18
v_ashrrev_i32_e32 v18, 8, v18
v_or_b32_e32 v22, s5, v14
v_add3_u32 v33, v19, v5, v9
v_mul_i32_i24_e32 v20, s12, v12
v_mul_i32_i24_e32 v21, s12, v11
v_add_nc_u32_e32 v5, v18, v15
v_add3_u32 v34, v22, v6, v10
v_add_nc_u32_e32 v18, 0x800, v2
v_sub_nc_u32_e32 v20, v13, v20
v_sub_nc_u32_e32 v15, v17, v21
v_mul_i32_i24_e32 v10, s12, v5
v_and_b32_e32 v6, 29, v13
v_lshrrev_b32_e32 v18, 6, v18
v_lshlrev_b32_e32 v9, 4, v20
v_lshlrev_b32_e32 v13, 4, v15
v_sub_nc_u32_e32 v10, v16, v10
v_and_b32_e32 v16, 31, v16
v_lshrrev_b32_e32 v20, 2, v0
v_and_b32_e32 v17, 30, v17
s_mov_b32 s0, 0xc30c30d
v_lshlrev_b32_e32 v10, 4, v10
v_and_b32_e32 v9, v3, v9
v_and_b32_e32 v13, v3, v13
v_mul_i32_i24_e32 v12, s7, v12
v_or_b32_e32 v15, s5, v6
v_and_b32_e32 v3, v3, v10
v_add_nc_u32_e32 v10, 22, v20
v_add_nc_u32_e32 v21, 0x801, v2
v_mul_i32_i24_e32 v5, s7, v5
v_or_b32_e32 v22, s5, v16
v_mul_hi_u32 v18, v18, s0
v_add3_u32 v38, v15, v12, v9
v_lshrrev_b32_e32 v9, 6, v21
v_mul_i32_i24_e32 v11, s7, v11
v_add3_u32 v40, v22, v5, v3
v_or_b32_e32 v19, s5, v17
v_lshlrev_b32_e32 v25, 5, v10
v_lshlrev_b32_e32 v5, 9, v10
v_add_nc_u32_e32 v10, 0x802, v2
v_mul_hi_u32 v9, v9, s0
v_add3_u32 v39, v19, v11, v13
v_mul_i32_i24_e32 v11, s7, v18
v_or_b32_e32 v13, s5, v8
v_lshrrev_b32_e32 v10, 6, v10
v_add_nc_u32_e32 v15, 0x803, v2
v_mad_i32_i24 v3, v18, s12, v25
v_add_nc_u32_e32 v12, s5, v5
v_add3_u32 v43, v13, v5, v11
v_mul_hi_u32 v10, v10, s0
v_lshrrev_b32_e32 v5, 6, v15
v_or_b32_e32 v3, v3, v8
v_or_b32_e32 v19, v12, v4
v_mad_i32_i24 v18, v9, s12, v25
s_mov_b32 s15, 0x8000
v_mul_hi_u32 v5, v5, s0
v_lshl_add_u32 v44, v3, 1, s15
v_mad_i32_i24 v45, v9, s7, v19
v_or_b32_e32 v3, v18, v4
v_or_b32_e32 v11, v12, v7
v_mad_i32_i24 v9, v10, s12, v25
v_add_nc_u32_e32 v4, 0x804, v2
s_mov_b32 s5, 0x300000
v_lshl_add_u32 v46, v3, 1, s15
v_mad_i32_i24 v47, v10, s7, v11
v_or_b32_e32 v7, v9, v7
v_lshrrev_b32_e32 v3, 6, v4
v_add_nc_u32_e32 v4, 0x805, v2
v_mad_i32_i24 v9, v5, s12, v25
v_add_nc_u32_e32 v10, 0x806, v2
v_lshl_add_u32 v48, v7, 1, s15
v_or_b32_e32 v7, v12, v1
v_lshrrev_b32_e32 v4, 6, v4
v_or_b32_e32 v1, v9, v1
v_lshrrev_b32_e32 v9, 6, v10
v_mul_hi_u32 v3, v3, s0
v_add_nc_u32_e32 v10, 0x807, v2
v_mad_i32_i24 v51, v5, s7, v7
v_mul_hi_u32 v4, v4, s0
v_lshl_add_u32 v52, v1, 1, s15
v_mul_hi_u32 v1, v9, s0
v_lshrrev_b32_e32 v7, 6, v10
v_or_b32_e32 v9, v12, v14
v_mad_i32_i24 v5, v3, s12, v25
v_or_b32_e32 v11, v12, v6
v_lshlrev_b32_e32 v23, 4, v0
v_mul_hi_u32 v7, v7, s0
v_mad_i32_i24 v10, v4, s12, v25
v_or_b32_e32 v5, v5, v14
v_mad_i32_i24 v54, v3, s7, v9
v_mad_i32_i24 v3, v1, s12, v25
v_mad_i32_i24 v56, v4, s7, v11
v_or_b32_e32 v4, v12, v17
v_lshl_add_u32 v55, v5, 1, s15
v_or_b32_e32 v5, v10, v6
v_mad_i32_i24 v6, v7, s12, v25
v_or_b32_e32 v3, v3, v17
v_mad_i32_i24 v58, v1, s7, v4
v_add_nc_u32_e32 v4, 0x2800, v2
v_or_b32_e32 v9, v12, v16
v_or_b32_e32 v1, v6, v16
s_movk_i32 s12, 0x6000
v_lshl_add_u32 v57, v5, 1, s15
v_lshl_add_u32 v59, v3, 1, s15
v_lshlrev_b32_e32 v3, 9, v20
v_lshl_add_u32 v63, v1, 1, s15
v_add_nc_u32_e32 v5, 64, v20
v_and_b32_e32 v6, s12, v4
v_lshrrev_b32_e32 v1, 13, v4
v_mad_i32_i24 v60, v7, s7, v9
s_lshl_b32 s0, s14, 17
s_mul_i32 s7, s13, s5
v_lshlrev_b32_e32 v4, 9, v5
s_add_i32 s7, s7, s0
s_mov_b32 s0, 0x180000
v_or3_b32 v64, s7, v3, v8
v_lshl_add_u32 v3, v5, 5, v6
v_add_nc_u32_e32 v5, 0x3000, v2
v_or_b32_e32 v6, s7, v8
v_mul_u32_u24_e32 v1, s0, v1
v_add_nc_u32_e32 v7, 0x80, v20
v_add_nc_u32_e32 v2, 0x3800, v2
v_and_b32_e32 v9, s12, v5
v_or_b32_e32 v3, v3, v8
v_add3_u32 v70, v6, v4, v1
v_lshrrev_b32_e32 v1, 13, v5
v_add_nc_u32_e32 v4, 0xc0, v20
v_and_b32_e32 v5, 0x6000, v2
v_lshl_add_u32 v9, v7, 5, v9
v_lshlrev_b32_e32 v7, 9, v7
v_mul_u32_u24_e32 v1, s0, v1
v_lshrrev_b32_e32 v2, 13, v2
v_lshlrev_b32_e32 v71, 1, v3
v_lshl_add_u32 v3, v4, 5, v5
v_or_b32_e32 v5, v9, v8
v_add3_u32 v72, v6, v7, v1
v_lshlrev_b32_e32 v1, 7, v0
v_lshrrev_b32_e32 v7, 6, v0
v_or_b32_e32 v3, v3, v8
v_lshlrev_b32_e32 v4, 9, v4
v_mul_u32_u24_e32 v2, s0, v2
v_and_b32_e32 v1, 0x1f80, v1
v_lshlrev_b32_e32 v8, 6, v0
v_lshlrev_b32_e32 v73, 1, v5
v_lshlrev_b32_e32 v75, 1, v3
v_add3_u32 v74, v6, v4, v2
v_mul_u32_u24_e32 v76, 0x2a0, v7
v_and_or_b32 v77, 0xe000, v8, v1
v_or_b32_e32 v26, s15, v23
v_cmp_gt_i32_e32 vcc_lo, 0x50, v0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v31, 0
v_mov_b32_e32 v29, 0
v_mov_b32_e32 v35, 0
v_mov_b32_e32 v32, 0
v_mov_b32_e32 v36, 0
v_mov_b32_e32 v37, 0
v_mov_b32_e32 v41, 0
v_mov_b32_e32 v42, 0
v_mov_b32_e32 v49, 0
v_mov_b32_e32 v50, 0
v_mov_b32_e32 v61, 0
v_mov_b32_e32 v53, 0
v_mov_b32_e32 v65, 0
v_mov_b32_e32 v62, 0
v_mov_b32_e32 v66, 0
v_mov_b32_e32 v67, 0
v_mov_b32_e32 v68, 0
v_mov_b32_e32 v69, 0
s_mov_b32 s7, 0
BB37_1:
s_lshl_b32 s12, s7, 5
v_add_nc_u32_e32 v78, s12, v24
v_add_nc_u32_e32 v80, s12, v30
v_add_nc_u32_e32 v82, s12, v34
v_add_nc_u32_e32 v84, s12, v39
v_add_nc_u32_e32 v86, s12, v38
v_ashrrev_i32_e32 v79, 31, v78
v_ashrrev_i32_e32 v81, 31, v80
v_ashrrev_i32_e32 v83, 31, v82
v_ashrrev_i32_e32 v85, 31, v84
v_add_nc_u32_e32 v88, s12, v40
v_lshlrev_b64 v[78:79], 1, v[78:79]
v_lshlrev_b64 v[80:81], 1, v[80:81]
v_lshlrev_b64 v[82:83], 1, v[82:83]
v_lshlrev_b64 v[84:85], 1, v[84:85]
v_ashrrev_i32_e32 v87, 31, v86
v_ashrrev_i32_e32 v89, 31, v88
s_waitcnt lgkmcnt(0)
v_add_co_u32 v78, s0, s8, v78
v_add_co_ci_u32_e64 v79, s0, s9, v79, s0
v_add_co_u32 v80, s0, s8, v80
v_lshlrev_b64 v[86:87], 1, v[86:87]
v_add_co_ci_u32_e64 v81, s0, s9, v81, s0
v_add_co_u32 v82, s0, s8, v82
v_lshlrev_b64 v[88:89], 1, v[88:89]
v_add_co_ci_u32_e64 v83, s0, s9, v83, s0
v_add_co_u32 v84, s0, s8, v84
v_add_co_ci_u32_e64 v85, s0, s9, v85, s0
s_clause 0x3
global_load_ushort v78, v[78:79], off
global_load_ushort v79, v[80:81], off
global_load_ushort v80, v[82:83], off
global_load_ushort v81, v[84:85], off
v_add_nc_u32_e32 v82, s12, v28
v_add_nc_u32_e32 v84, s12, v33
v_ashrrev_i32_e32 v83, 31, v82
v_ashrrev_i32_e32 v85, 31, v84
v_lshlrev_b64 v[82:83], 1, v[82:83]
v_lshlrev_b64 v[84:85], 1, v[84:85]
v_add_co_u32 v82, s0, s8, v82
v_add_co_ci_u32_e64 v83, s0, s9, v83, s0
v_add_co_u32 v84, s0, s8, v84
v_add_co_ci_u32_e64 v85, s0, s9, v85, s0
v_add_co_u32 v86, s0, s8, v86
v_add_co_ci_u32_e64 v87, s0, s9, v87, s0
v_add_co_u32 v88, s0, s8, v88
v_add_co_ci_u32_e64 v89, s0, s9, v89, s0
s_waitcnt vmcnt(3)
global_load_short_d16_hi v78, v[82:83], off
s_waitcnt vmcnt(3)
global_load_short_d16_hi v79, v[84:85], off
s_waitcnt vmcnt(3)
global_load_short_d16_hi v80, v[86:87], off
s_waitcnt vmcnt(3)
global_load_short_d16_hi v81, v[88:89], off
s_waitcnt vmcnt(0)
s_barrier
ds_write_b128 v26, v[78:81]
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz BB37_3
v_add_nc_u32_e32 v78, s12, v43
v_add_nc_u32_e32 v80, s12, v45
v_add_nc_u32_e32 v82, s12, v47
v_add_nc_u32_e32 v84, s12, v51
v_add_nc_u32_e32 v86, s12, v54
v_ashrrev_i32_e32 v79, 31, v78
v_ashrrev_i32_e32 v81, 31, v80
v_ashrrev_i32_e32 v83, 31, v82
v_ashrrev_i32_e32 v85, 31, v84
v_add_nc_u32_e32 v88, s12, v56
v_lshlrev_b64 v[78:79], 1, v[78:79]
v_lshlrev_b64 v[80:81], 1, v[80:81]
v_lshlrev_b64 v[82:83], 1, v[82:83]
v_ashrrev_i32_e32 v87, 31, v86
v_add_nc_u32_e32 v90, s12, v58
v_lshlrev_b64 v[84:85], 1, v[84:85]
v_add_co_u32 v78, s0, s8, v78
v_ashrrev_i32_e32 v89, 31, v88
v_add_co_ci_u32_e64 v79, s0, s9, v79, s0
v_add_co_u32 v80, s0, s8, v80
v_add_nc_u32_e32 v92, s12, v60
v_add_co_ci_u32_e64 v81, s0, s9, v81, s0
v_add_co_u32 v82, s0, s8, v82
v_lshlrev_b64 v[86:87], 1, v[86:87]
v_ashrrev_i32_e32 v91, 31, v90
v_add_co_ci_u32_e64 v83, s0, s9, v83, s0
v_add_co_u32 v84, s0, s8, v84
v_lshlrev_b64 v[88:89], 1, v[88:89]
v_ashrrev_i32_e32 v93, 31, v92
v_add_co_ci_u32_e64 v85, s0, s9, v85, s0
v_add_co_u32 v86, s0, s8, v86
v_lshlrev_b64 v[90:91], 1, v[90:91]
v_add_co_ci_u32_e64 v87, s0, s9, v87, s0
v_add_co_u32 v88, s0, s8, v88
v_lshlrev_b64 v[92:93], 1, v[92:93]
v_add_co_ci_u32_e64 v89, s0, s9, v89, s0
v_add_co_u32 v90, s0, s8, v90
v_add_co_ci_u32_e64 v91, s0, s9, v91, s0
v_add_co_u32 v92, s0, s8, v92
v_add_co_ci_u32_e64 v93, s0, s9, v93, s0
s_clause 0x7
global_load_ushort v78, v[78:79], off
global_load_ushort v79, v[80:81], off
global_load_ushort v80, v[82:83], off
global_load_ushort v81, v[84:85], off
global_load_ushort v82, v[86:87], off
global_load_ushort v83, v[88:89], off
global_load_ushort v84, v[90:91], off
global_load_ushort v85, v[92:93], off
s_waitcnt vmcnt(7)
ds_write_b16 v44, v78
s_waitcnt vmcnt(6)
ds_write_b16 v46, v79
s_waitcnt vmcnt(5)
ds_write_b16 v48, v80
s_waitcnt vmcnt(4)
ds_write_b16 v52, v81
s_waitcnt vmcnt(3)
ds_write_b16 v55, v82
s_waitcnt vmcnt(2)
ds_write_b16 v57, v83
s_waitcnt vmcnt(1)
ds_write_b16 v59, v84
s_waitcnt vmcnt(0)
ds_write_b16 v63, v85
BB37_3:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v78, s12, v64
v_add_nc_u32_e32 v80, s12, v70
v_add_nc_u32_e32 v86, s12, v72
v_add_nc_u32_e32 v88, s12, v74
v_ashrrev_i32_e32 v79, 31, v78
v_ashrrev_i32_e32 v81, 31, v80
v_ashrrev_i32_e32 v87, 31, v86
v_lshlrev_b64 v[78:79], 1, v[78:79]
v_lshlrev_b64 v[91:92], 1, v[80:81]
v_lshlrev_b64 v[86:87], 1, v[86:87]
v_add_co_u32 v89, s0, s10, v78
v_add_co_ci_u32_e64 v90, s0, s11, v79, s0
v_add_co_u32 v82, s0, 0x10000, v89
v_add_co_ci_u32_e64 v83, s0, 0, v90, s0
v_add_co_u32 v93, s0, 0x20000, v89
v_add_co_ci_u32_e64 v94, s0, 0, v90, s0
v_add_co_u32 v95, s0, 0x30000, v89
s_clause 0x1
global_load_dwordx4 v[78:81], v[89:90], off
global_load_dwordx4 v[82:85], v[82:83], off
v_add_co_ci_u32_e64 v96, s0, 0, v90, s0
v_add_co_u32 v97, s0, s5, v89
v_ashrrev_i32_e32 v89, 31, v88
v_add_co_ci_u32_e64 v98, s0, 0, v90, s0
v_add_co_u32 v99, s0, s10, v91
v_add_co_ci_u32_e64 v100, s0, s11, v92, s0
v_lshlrev_b64 v[88:89], 1, v[88:89]
v_add_co_u32 v102, s0, s10, v86
v_add_co_ci_u32_e64 v103, s0, s11, v87, s0
v_add_co_u32 v106, s0, s10, v88
v_add_co_ci_u32_e64 v107, s0, s11, v89, s0
s_clause 0x5
global_load_dwordx4 v[86:89], v[93:94], off
global_load_dwordx4 v[90:93], v[95:96], off
global_load_dwordx4 v[94:97], v[97:98], off
global_load_dwordx4 v[98:101], v[99:100], off
global_load_dwordx4 v[102:105], v[102:103], off
global_load_dwordx4 v[106:109], v[106:107], off
s_mov_b32 s0, 0
s_waitcnt vmcnt(7)
ds_write_b128 v23, v[78:81]
s_waitcnt vmcnt(6)
ds_write_b128 v23, v[82:85] offset:4096
s_waitcnt vmcnt(5)
ds_write_b128 v23, v[86:89] offset:8192
s_waitcnt vmcnt(4)
ds_write_b128 v23, v[90:93] offset:12288
s_waitcnt vmcnt(3)
ds_write_b128 v23, v[94:97] offset:16384
s_waitcnt vmcnt(2)
ds_write_b128 v71, v[98:101]
s_waitcnt vmcnt(1)
ds_write_b128 v73, v[102:105]
s_waitcnt vmcnt(0)
ds_write_b128 v75, v[106:109]
s_waitcnt lgkmcnt(0)
s_barrier
BB37_4:
s_lshl_b32 s12, s0, 3
v_mov_b32_e32 v82, 0xffff
v_add_lshl_u32 v83, v77, s12, 1
s_add_i32 s0, s0, 1
s_cmp_lg_u32 s0, 4
ds_read_b128 v[78:81], v83
ds_read_b128 v[90:93], v83 offset:64
s_waitcnt lgkmcnt(1)
v_and_b32_e32 v84, v82, v78
v_and_b32_e32 v85, v82, v79
v_and_b32_sdwa v86, v82, v78 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v87, v82, v79 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v88, v82, v80
v_and_b32_sdwa v98, v82, v80 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v99, v82, v81
v_and_b32_sdwa v100, v82, v81 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
ds_read_b128 v[78:81], v83 offset:128
ds_read_b128 v[94:97], v83 offset:192
s_waitcnt lgkmcnt(2)
v_lshl_or_b32 v89, v91, 16, v85
v_lshl_or_b32 v106, v90, 16, v84
v_lshl_or_b32 v85, v92, 16, v88
s_waitcnt lgkmcnt(1)
v_and_b32_e32 v83, v82, v78
v_and_b32_sdwa v101, v82, v78 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v78, v82, v79
v_and_b32_e32 v102, v82, v80
v_and_b32_sdwa v103, v82, v80 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v80, v93, 16, v99
v_lshrrev_b32_e32 v99, 16, v92
s_waitcnt lgkmcnt(0)
v_lshl_or_b32 v92, v94, 16, v83
v_and_b32_sdwa v79, v82, v79 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v104, v82, v81
v_and_b32_sdwa v105, v82, v81 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v82, 16, v90
v_lshrrev_b32_e32 v90, 16, v91
v_lshrrev_b32_e32 v94, 16, v94
v_lshl_or_b32 v88, v95, 16, v78
v_lshrrev_b32_e32 v93, 16, v93
v_lshl_or_b32 v84, v96, 16, v102
v_lshl_or_b32 v81, v97, 16, v104
v_lshl_or_b32 v87, v90, 16, v87
v_lshl_or_b32 v90, v94, 16, v101
v_lshrrev_b32_e32 v95, 16, v95
v_lshrrev_b32_e32 v96, 16, v96
v_lshrrev_b32_e32 v97, 16, v97
v_add_lshl_u32 v101, s12, v76, 1
v_lshl_or_b32 v91, v82, 16, v86
v_lshl_or_b32 v86, v95, 16, v79
v_lshl_or_b32 v83, v99, 16, v98
v_lshl_or_b32 v78, v93, 16, v100
v_lshl_or_b32 v82, v96, 16, v103
v_lshl_or_b32 v79, v97, 16, v105
ds_read_b128 v[93:96], v101 offset:32768
ds_read_b128 v[97:100], v101 offset:32832
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v68, v93, v106, v68 op_sel_hi:[0,1,1]
v_pk_fma_f16 v69, v93, v92, v69 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v66, v97, v106, v66 op_sel_hi:[0,1,1]
v_pk_fma_f16 v67, v97, v92, v67 op_sel_hi:[0,1,1]
v_pk_fma_f16 v68, v93, v91, v68 op_sel:[1,0,0]
v_pk_fma_f16 v69, v93, v90, v69 op_sel:[1,0,0]
v_pk_fma_f16 v66, v97, v91, v66 op_sel:[1,0,0]
v_pk_fma_f16 v67, v97, v90, v67 op_sel:[1,0,0]
v_pk_fma_f16 v68, v94, v89, v68 op_sel_hi:[0,1,1]
v_pk_fma_f16 v69, v94, v88, v69 op_sel_hi:[0,1,1]
v_pk_fma_f16 v66, v98, v89, v66 op_sel_hi:[0,1,1]
v_pk_fma_f16 v67, v98, v88, v67 op_sel_hi:[0,1,1]
v_pk_fma_f16 v68, v94, v87, v68 op_sel:[1,0,0]
v_pk_fma_f16 v69, v94, v86, v69 op_sel:[1,0,0]
v_pk_fma_f16 v66, v98, v87, v66 op_sel:[1,0,0]
v_pk_fma_f16 v67, v98, v86, v67 op_sel:[1,0,0]
v_pk_fma_f16 v68, v95, v85, v68 op_sel_hi:[0,1,1]
v_pk_fma_f16 v69, v95, v84, v69 op_sel_hi:[0,1,1]
v_pk_fma_f16 v66, v99, v85, v66 op_sel_hi:[0,1,1]
v_pk_fma_f16 v67, v99, v84, v67 op_sel_hi:[0,1,1]
v_pk_fma_f16 v68, v95, v83, v68 op_sel:[1,0,0]
v_pk_fma_f16 v69, v95, v82, v69 op_sel:[1,0,0]
v_pk_fma_f16 v66, v99, v83, v66 op_sel:[1,0,0]
v_pk_fma_f16 v67, v99, v82, v67 op_sel:[1,0,0]
v_pk_fma_f16 v68, v96, v80, v68 op_sel_hi:[0,1,1]
v_pk_fma_f16 v69, v96, v81, v69 op_sel_hi:[0,1,1]
v_pk_fma_f16 v66, v100, v80, v66 op_sel_hi:[0,1,1]
v_pk_fma_f16 v67, v100, v81, v67 op_sel_hi:[0,1,1]
v_pk_fma_f16 v68, v96, v78, v68 op_sel:[1,0,0]
v_pk_fma_f16 v69, v96, v79, v69 op_sel:[1,0,0]
v_pk_fma_f16 v66, v100, v78, v66 op_sel:[1,0,0]
v_pk_fma_f16 v67, v100, v79, v67 op_sel:[1,0,0]
ds_read_b128 v[93:96], v101 offset:32896
ds_read_b128 v[97:100], v101 offset:32960
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v65, v93, v106, v65 op_sel_hi:[0,1,1]
v_pk_fma_f16 v62, v93, v92, v62 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v61, v97, v106, v61 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v97, v92, v53 op_sel_hi:[0,1,1]
v_pk_fma_f16 v65, v93, v91, v65 op_sel:[1,0,0]
v_pk_fma_f16 v62, v93, v90, v62 op_sel:[1,0,0]
v_pk_fma_f16 v61, v97, v91, v61 op_sel:[1,0,0]
v_pk_fma_f16 v53, v97, v90, v53 op_sel:[1,0,0]
v_pk_fma_f16 v65, v94, v89, v65 op_sel_hi:[0,1,1]
v_pk_fma_f16 v62, v94, v88, v62 op_sel_hi:[0,1,1]
v_pk_fma_f16 v61, v98, v89, v61 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v98, v88, v53 op_sel_hi:[0,1,1]
v_pk_fma_f16 v65, v94, v87, v65 op_sel:[1,0,0]
v_pk_fma_f16 v62, v94, v86, v62 op_sel:[1,0,0]
v_pk_fma_f16 v61, v98, v87, v61 op_sel:[1,0,0]
v_pk_fma_f16 v53, v98, v86, v53 op_sel:[1,0,0]
v_pk_fma_f16 v65, v95, v85, v65 op_sel_hi:[0,1,1]
v_pk_fma_f16 v62, v95, v84, v62 op_sel_hi:[0,1,1]
v_pk_fma_f16 v61, v99, v85, v61 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v99, v84, v53 op_sel_hi:[0,1,1]
v_pk_fma_f16 v65, v95, v83, v65 op_sel:[1,0,0]
v_pk_fma_f16 v62, v95, v82, v62 op_sel:[1,0,0]
v_pk_fma_f16 v61, v99, v83, v61 op_sel:[1,0,0]
v_pk_fma_f16 v53, v99, v82, v53 op_sel:[1,0,0]
v_pk_fma_f16 v65, v96, v80, v65 op_sel_hi:[0,1,1]
v_pk_fma_f16 v62, v96, v81, v62 op_sel_hi:[0,1,1]
v_pk_fma_f16 v61, v100, v80, v61 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v100, v81, v53 op_sel_hi:[0,1,1]
v_pk_fma_f16 v65, v96, v78, v65 op_sel:[1,0,0]
v_pk_fma_f16 v62, v96, v79, v62 op_sel:[1,0,0]
v_pk_fma_f16 v61, v100, v78, v61 op_sel:[1,0,0]
v_pk_fma_f16 v53, v100, v79, v53 op_sel:[1,0,0]
ds_read_b128 v[93:96], v101 offset:33024
ds_read_b128 v[97:100], v101 offset:33088
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v49, v93, v106, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v93, v92, v50 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v41, v97, v106, v41 op_sel_hi:[0,1,1]
v_pk_fma_f16 v42, v97, v92, v42 op_sel_hi:[0,1,1]
v_pk_fma_f16 v49, v93, v91, v49 op_sel:[1,0,0]
v_pk_fma_f16 v50, v93, v90, v50 op_sel:[1,0,0]
v_pk_fma_f16 v41, v97, v91, v41 op_sel:[1,0,0]
v_pk_fma_f16 v42, v97, v90, v42 op_sel:[1,0,0]
v_pk_fma_f16 v49, v94, v89, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v94, v88, v50 op_sel_hi:[0,1,1]
v_pk_fma_f16 v41, v98, v89, v41 op_sel_hi:[0,1,1]
v_pk_fma_f16 v42, v98, v88, v42 op_sel_hi:[0,1,1]
v_pk_fma_f16 v49, v94, v87, v49 op_sel:[1,0,0]
v_pk_fma_f16 v50, v94, v86, v50 op_sel:[1,0,0]
v_pk_fma_f16 v41, v98, v87, v41 op_sel:[1,0,0]
v_pk_fma_f16 v42, v98, v86, v42 op_sel:[1,0,0]
v_pk_fma_f16 v49, v95, v85, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v95, v84, v50 op_sel_hi:[0,1,1]
v_pk_fma_f16 v41, v99, v85, v41 op_sel_hi:[0,1,1]
v_pk_fma_f16 v42, v99, v84, v42 op_sel_hi:[0,1,1]
v_pk_fma_f16 v49, v95, v83, v49 op_sel:[1,0,0]
v_pk_fma_f16 v50, v95, v82, v50 op_sel:[1,0,0]
v_pk_fma_f16 v41, v99, v83, v41 op_sel:[1,0,0]
v_pk_fma_f16 v42, v99, v82, v42 op_sel:[1,0,0]
v_pk_fma_f16 v49, v96, v80, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v96, v81, v50 op_sel_hi:[0,1,1]
v_pk_fma_f16 v41, v100, v80, v41 op_sel_hi:[0,1,1]
v_pk_fma_f16 v42, v100, v81, v42 op_sel_hi:[0,1,1]
v_pk_fma_f16 v49, v96, v78, v49 op_sel:[1,0,0]
v_pk_fma_f16 v50, v96, v79, v50 op_sel:[1,0,0]
v_pk_fma_f16 v41, v100, v78, v41 op_sel:[1,0,0]
v_pk_fma_f16 v42, v100, v79, v42 op_sel:[1,0,0]
ds_read_b128 v[93:96], v101 offset:33152
ds_read_b128 v[97:100], v101 offset:33216
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v36, v93, v106, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v93, v92, v37 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v35, v97, v106, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v97, v92, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v93, v91, v36 op_sel:[1,0,0]
v_pk_fma_f16 v37, v93, v90, v37 op_sel:[1,0,0]
v_pk_fma_f16 v35, v97, v91, v35 op_sel:[1,0,0]
v_pk_fma_f16 v32, v97, v90, v32 op_sel:[1,0,0]
v_pk_fma_f16 v36, v94, v89, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v94, v88, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v98, v89, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v98, v88, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v94, v87, v36 op_sel:[1,0,0]
v_pk_fma_f16 v37, v94, v86, v37 op_sel:[1,0,0]
v_pk_fma_f16 v35, v98, v87, v35 op_sel:[1,0,0]
v_pk_fma_f16 v32, v98, v86, v32 op_sel:[1,0,0]
v_pk_fma_f16 v36, v95, v85, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v95, v84, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v99, v85, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v99, v84, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v95, v83, v36 op_sel:[1,0,0]
v_pk_fma_f16 v37, v95, v82, v37 op_sel:[1,0,0]
v_pk_fma_f16 v35, v99, v83, v35 op_sel:[1,0,0]
v_pk_fma_f16 v32, v99, v82, v32 op_sel:[1,0,0]
v_pk_fma_f16 v36, v96, v80, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v96, v81, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v100, v80, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v100, v81, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v96, v78, v36 op_sel:[1,0,0]
v_pk_fma_f16 v37, v96, v79, v37 op_sel:[1,0,0]
v_pk_fma_f16 v35, v100, v78, v35 op_sel:[1,0,0]
v_pk_fma_f16 v32, v100, v79, v32 op_sel:[1,0,0]
ds_read_b128 v[93:96], v101 offset:33280
ds_read_b128 v[97:100], v101 offset:33344
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v31, v93, v106, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v93, v92, v29 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v25, v97, v106, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v97, v92, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v93, v91, v31 op_sel:[1,0,0]
v_pk_fma_f16 v29, v93, v90, v29 op_sel:[1,0,0]
v_pk_fma_f16 v25, v97, v91, v25 op_sel:[1,0,0]
v_pk_fma_f16 v27, v97, v90, v27 op_sel:[1,0,0]
v_pk_fma_f16 v31, v94, v89, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v94, v88, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v98, v89, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v98, v88, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v94, v87, v31 op_sel:[1,0,0]
v_pk_fma_f16 v29, v94, v86, v29 op_sel:[1,0,0]
v_pk_fma_f16 v25, v98, v87, v25 op_sel:[1,0,0]
v_pk_fma_f16 v27, v98, v86, v27 op_sel:[1,0,0]
v_pk_fma_f16 v31, v95, v85, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v95, v84, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v99, v85, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v99, v84, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v95, v83, v31 op_sel:[1,0,0]
v_pk_fma_f16 v29, v95, v82, v29 op_sel:[1,0,0]
v_pk_fma_f16 v25, v99, v83, v25 op_sel:[1,0,0]
v_pk_fma_f16 v27, v99, v82, v27 op_sel:[1,0,0]
v_pk_fma_f16 v31, v96, v80, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v96, v81, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v100, v80, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v100, v81, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v96, v78, v31 op_sel:[1,0,0]
v_pk_fma_f16 v29, v96, v79, v29 op_sel:[1,0,0]
v_pk_fma_f16 v25, v100, v78, v25 op_sel:[1,0,0]
v_pk_fma_f16 v27, v100, v79, v27 op_sel:[1,0,0]
ds_read_b128 v[93:96], v101 offset:33408
ds_read_b128 v[97:100], v101 offset:33472
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v21, v93, v106, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v93, v92, v22 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v19, v97, v106, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v97, v92, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v93, v91, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v93, v90, v22 op_sel:[1,0,0]
v_pk_fma_f16 v19, v97, v91, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v97, v90, v20 op_sel:[1,0,0]
v_pk_fma_f16 v21, v94, v89, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v94, v88, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v98, v89, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v98, v88, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v94, v87, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v94, v86, v22 op_sel:[1,0,0]
v_pk_fma_f16 v19, v98, v87, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v98, v86, v20 op_sel:[1,0,0]
v_pk_fma_f16 v21, v95, v85, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v95, v84, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v99, v85, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v99, v84, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v95, v83, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v95, v82, v22 op_sel:[1,0,0]
v_pk_fma_f16 v19, v99, v83, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v99, v82, v20 op_sel:[1,0,0]
v_pk_fma_f16 v21, v96, v80, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v96, v81, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v100, v80, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v100, v81, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v96, v78, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v96, v79, v22 op_sel:[1,0,0]
v_pk_fma_f16 v19, v100, v78, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v100, v79, v20 op_sel:[1,0,0]
ds_read_b128 v[93:96], v101 offset:33536
ds_read_b128 v[97:100], v101 offset:33600
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v18, v93, v106, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v93, v92, v16 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v15, v97, v106, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v97, v92, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v93, v91, v18 op_sel:[1,0,0]
v_pk_fma_f16 v16, v93, v90, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v97, v91, v15 op_sel:[1,0,0]
v_pk_fma_f16 v14, v97, v90, v14 op_sel:[1,0,0]
v_pk_fma_f16 v18, v94, v89, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v94, v88, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v98, v89, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v98, v88, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v94, v87, v18 op_sel:[1,0,0]
v_pk_fma_f16 v16, v94, v86, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v98, v87, v15 op_sel:[1,0,0]
v_pk_fma_f16 v14, v98, v86, v14 op_sel:[1,0,0]
v_pk_fma_f16 v18, v95, v85, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v95, v84, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v99, v85, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v99, v84, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v95, v83, v18 op_sel:[1,0,0]
v_pk_fma_f16 v16, v95, v82, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v99, v83, v15 op_sel:[1,0,0]
v_pk_fma_f16 v14, v99, v82, v14 op_sel:[1,0,0]
v_pk_fma_f16 v18, v96, v80, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v96, v81, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v100, v80, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v100, v81, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v96, v78, v18 op_sel:[1,0,0]
v_pk_fma_f16 v16, v96, v79, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v100, v78, v15 op_sel:[1,0,0]
v_pk_fma_f16 v14, v100, v79, v14 op_sel:[1,0,0]
ds_read_b128 v[93:96], v101 offset:33664
ds_read_b128 v[97:100], v101 offset:33728
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v11, v93, v106, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v93, v92, v12 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v5, v97, v106, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v97, v92, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v93, v91, v11 op_sel:[1,0,0]
v_pk_fma_f16 v12, v93, v90, v12 op_sel:[1,0,0]
v_pk_fma_f16 v5, v97, v91, v5 op_sel:[1,0,0]
v_pk_fma_f16 v6, v97, v90, v6 op_sel:[1,0,0]
v_pk_fma_f16 v11, v94, v89, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v94, v88, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v98, v89, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v98, v88, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v94, v87, v11 op_sel:[1,0,0]
v_pk_fma_f16 v12, v94, v86, v12 op_sel:[1,0,0]
v_pk_fma_f16 v5, v98, v87, v5 op_sel:[1,0,0]
v_pk_fma_f16 v6, v98, v86, v6 op_sel:[1,0,0]
v_pk_fma_f16 v11, v95, v85, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v95, v84, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v99, v85, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v99, v84, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v95, v83, v11 op_sel:[1,0,0]
v_pk_fma_f16 v12, v95, v82, v12 op_sel:[1,0,0]
v_pk_fma_f16 v5, v99, v83, v5 op_sel:[1,0,0]
v_pk_fma_f16 v6, v99, v82, v6 op_sel:[1,0,0]
v_pk_fma_f16 v11, v96, v80, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v96, v81, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v100, v80, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v100, v81, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v96, v78, v11 op_sel:[1,0,0]
v_pk_fma_f16 v12, v96, v79, v12 op_sel:[1,0,0]
v_pk_fma_f16 v5, v100, v78, v5 op_sel:[1,0,0]
v_pk_fma_f16 v6, v100, v79, v6 op_sel:[1,0,0]
ds_read_b128 v[93:96], v101 offset:33792
ds_read_b128 v[97:100], v101 offset:33856
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v3, v93, v106, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v93, v92, v4 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v2, v97, v106, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v97, v92, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v93, v91, v3 op_sel:[1,0,0]
v_pk_fma_f16 v4, v93, v90, v4 op_sel:[1,0,0]
v_pk_fma_f16 v2, v97, v91, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v97, v90, v1 op_sel:[1,0,0]
v_pk_fma_f16 v3, v94, v89, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v94, v88, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v98, v89, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v98, v88, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v94, v87, v3 op_sel:[1,0,0]
v_pk_fma_f16 v4, v94, v86, v4 op_sel:[1,0,0]
v_pk_fma_f16 v2, v98, v87, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v98, v86, v1 op_sel:[1,0,0]
v_pk_fma_f16 v3, v95, v85, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v95, v84, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v99, v85, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v99, v84, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v95, v83, v3 op_sel:[1,0,0]
v_pk_fma_f16 v4, v95, v82, v4 op_sel:[1,0,0]
v_pk_fma_f16 v2, v99, v83, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v99, v82, v1 op_sel:[1,0,0]
v_pk_fma_f16 v3, v96, v80, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v96, v81, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v100, v80, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v100, v81, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v96, v78, v3 op_sel:[1,0,0]
v_pk_fma_f16 v4, v96, v79, v4 op_sel:[1,0,0]
v_pk_fma_f16 v2, v100, v78, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v100, v79, v1 op_sel:[1,0,0]
ds_read_b128 v[93:96], v101 offset:33920
ds_read_b128 v[97:100], v101 offset:33984
ds_read_b128 v[101:104], v101 offset:34048
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v17, v93, v106, v17 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v13, v97, v106, v13 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v10, v101, v106, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v93, v92, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v97, v92, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v101, v92, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v93, v91, v17 op_sel:[1,0,0]
v_pk_fma_f16 v13, v97, v91, v13 op_sel:[1,0,0]
v_pk_fma_f16 v10, v101, v91, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v93, v90, v9 op_sel:[1,0,0]
v_pk_fma_f16 v8, v97, v90, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v101, v90, v7 op_sel:[1,0,0]
v_pk_fma_f16 v17, v94, v89, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v98, v89, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v102, v89, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v94, v88, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v98, v88, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v102, v88, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v94, v87, v17 op_sel:[1,0,0]
v_pk_fma_f16 v13, v98, v87, v13 op_sel:[1,0,0]
v_pk_fma_f16 v10, v102, v87, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v94, v86, v9 op_sel:[1,0,0]
v_pk_fma_f16 v8, v98, v86, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v102, v86, v7 op_sel:[1,0,0]
v_pk_fma_f16 v17, v95, v85, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v99, v85, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v103, v85, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v95, v84, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v99, v84, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v103, v84, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v95, v83, v17 op_sel:[1,0,0]
v_pk_fma_f16 v13, v99, v83, v13 op_sel:[1,0,0]
v_pk_fma_f16 v10, v103, v83, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v95, v82, v9 op_sel:[1,0,0]
v_pk_fma_f16 v8, v99, v82, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v103, v82, v7 op_sel:[1,0,0]
v_pk_fma_f16 v17, v96, v80, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v100, v80, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v96, v81, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v100, v81, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v104, v80, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v104, v81, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v96, v78, v17 op_sel:[1,0,0]
v_pk_fma_f16 v9, v96, v79, v9 op_sel:[1,0,0]
v_pk_fma_f16 v13, v100, v78, v13 op_sel:[1,0,0]
v_pk_fma_f16 v8, v100, v79, v8 op_sel:[1,0,0]
v_pk_fma_f16 v10, v104, v78, v10 op_sel:[1,0,0]
v_pk_fma_f16 v7, v104, v79, v7 op_sel:[1,0,0]
s_cbranch_scc1 BB37_4
s_add_i32 s7, s7, 1
s_cmp_eq_u32 s7, 16
s_cbranch_scc0 BB37_1
v_lshlrev_b32_e32 v23, 2, v0
v_lshrrev_b32_e32 v24, 7, v0
v_bfe_u32 v0, v0, 6, 1
s_lshl_b32 s0, s6, 8
v_and_b32_e32 v23, 0xfc, v23
v_mad_u32_u24 v24, 0x1f800, v24, s1
s_and_b32 s0, s0, 0x100
v_mul_u32_u24_e32 v0, 0x2a00, v0
v_or3_b32 v23, v24, s0, v23
v_add3_u32 v23, v23, s4, v0
v_add_nc_u32_e32 v33, 0x400, v23
v_ashrrev_i32_e32 v24, 31, v23
v_add_nc_u32_e32 v38, 0x402, v23
v_add_nc_u32_e32 v43, 0x600, v23
v_add_nc_u32_e32 v45, 0x602, v23
v_ashrrev_i32_e32 v34, 31, v33
v_lshlrev_b64 v[46:47], 1, v[23:24]
v_ashrrev_i32_e32 v39, 31, v38
v_ashrrev_i32_e32 v44, 31, v43
v_add_nc_u32_e32 v51, 0x800, v23
v_lshlrev_b64 v[33:34], 1, v[33:34]
v_add_nc_u32_e32 v40, 0xe00, v23
v_add_co_u32 v54, vcc_lo, s2, v46
v_lshlrev_b64 v[38:39], 1, v[38:39]
v_add_co_ci_u32_e32 v55, vcc_lo, s3, v47, vcc_lo
v_lshlrev_b64 v[43:44], 1, v[43:44]
v_add_co_u32 v33, vcc_lo, s2, v33
v_ashrrev_i32_e32 v46, 31, v45
v_add_co_ci_u32_e32 v34, vcc_lo, s3, v34, vcc_lo
v_add_co_u32 v38, vcc_lo, s2, v38
global_store_dword v[54:55], v68, off
global_store_dword v[54:55], v69, off offset:4
global_store_dword v[54:55], v66, off offset:1024
global_store_dword v[54:55], v67, off offset:1028
v_add_co_ci_u32_e32 v39, vcc_lo, s3, v39, vcc_lo
v_ashrrev_i32_e32 v52, 31, v51
global_store_dword v[33:34], v65, off
v_add_co_u32 v33, vcc_lo, s2, v43
v_add_nc_u32_e32 v43, 0x802, v23
v_add_co_ci_u32_e32 v34, vcc_lo, s3, v44, vcc_lo
v_lshlrev_b64 v[45:46], 1, v[45:46]
v_add_nc_u32_e32 v47, 0xa02, v23
v_add_nc_u32_e32 v30, 0x1202, v23
v_ashrrev_i32_e32 v44, 31, v43
global_store_dword v[38:39], v62, off
global_store_dword v[33:34], v61, off
v_lshlrev_b64 v[33:34], 1, v[51:52]
v_add_co_u32 v38, vcc_lo, s2, v45
v_add_nc_u32_e32 v45, 0xa00, v23
v_lshlrev_b64 v[43:44], 1, v[43:44]
v_add_co_ci_u32_e32 v39, vcc_lo, s3, v46, vcc_lo
v_ashrrev_i32_e32 v48, 31, v47
v_add_co_u32 v33, vcc_lo, s2, v33
v_ashrrev_i32_e32 v46, 31, v45
v_add_co_ci_u32_e32 v34, vcc_lo, s3, v34, vcc_lo
v_add_co_u32 v43, vcc_lo, s2, v43
global_store_dword v[38:39], v53, off
v_add_co_ci_u32_e32 v44, vcc_lo, s3, v44, vcc_lo
v_lshlrev_b64 v[38:39], 1, v[45:46]
v_add_nc_u32_e32 v45, 0xc02, v23
v_add_nc_u32_e32 v26, 0x1600, v23
global_store_dword v[33:34], v49, off
global_store_dword v[43:44], v50, off
v_lshlrev_b64 v[33:34], 1, v[47:48]
v_add_nc_u32_e32 v43, 0xc00, v23
v_add_co_u32 v38, vcc_lo, s2, v38
v_ashrrev_i32_e32 v46, 31, v45
v_add_co_ci_u32_e32 v39, vcc_lo, s3, v39, vcc_lo
v_add_nc_u32_e32 v0, 0x2602, v23
v_ashrrev_i32_e32 v44, 31, v43
v_add_co_u32 v33, vcc_lo, s2, v33
v_add_co_ci_u32_e32 v34, vcc_lo, s3, v34, vcc_lo
v_lshlrev_b64 v[43:44], 1, v[43:44]
global_store_dword v[38:39], v41, off
global_store_dword v[33:34], v42, off
v_ashrrev_i32_e32 v41, 31, v40
v_lshlrev_b64 v[33:34], 1, v[45:46]
v_add_nc_u32_e32 v42, 0xe02, v23
v_add_co_u32 v38, vcc_lo, s2, v43
v_lshlrev_b64 v[40:41], 1, v[40:41]
v_add_co_ci_u32_e32 v39, vcc_lo, s3, v44, vcc_lo
v_add_co_u32 v33, vcc_lo, s2, v33
v_add_nc_u32_e32 v44, 0x1000, v23
v_add_co_ci_u32_e32 v34, vcc_lo, s3, v34, vcc_lo
v_ashrrev_i32_e32 v43, 31, v42
v_add_co_u32 v40, vcc_lo, s2, v40
global_store_dword v[38:39], v36, off
v_add_co_ci_u32_e32 v41, vcc_lo, s3, v41, vcc_lo
v_ashrrev_i32_e32 v45, 31, v44
v_lshlrev_b64 v[38:39], 1, v[42:43]
global_store_dword v[33:34], v37, off
global_store_dword v[40:41], v35, off
v_add_nc_u32_e32 v35, 0x1002, v23
v_lshlrev_b64 v[33:34], 1, v[44:45]
v_add_co_u32 v37, vcc_lo, s2, v38
v_ashrrev_i32_e32 v36, 31, v35
v_add_co_ci_u32_e32 v38, vcc_lo, s3, v39, vcc_lo
v_add_nc_u32_e32 v39, 0x1200, v23
v_add_co_u32 v33, vcc_lo, s2, v33
v_add_co_ci_u32_e32 v34, vcc_lo, s3, v34, vcc_lo
v_lshlrev_b64 v[35:36], 1, v[35:36]
v_ashrrev_i32_e32 v40, 31, v39
global_store_dword v[37:38], v32, off
global_store_dword v[33:34], v31, off
v_ashrrev_i32_e32 v31, 31, v30
v_add_nc_u32_e32 v38, 0x1402, v23
v_add_co_u32 v34, vcc_lo, s2, v35
v_lshlrev_b64 v[32:33], 1, v[39:40]
v_add_co_ci_u32_e32 v35, vcc_lo, s3, v36, vcc_lo
v_add_nc_u32_e32 v36, 0x1400, v23
v_lshlrev_b64 v[30:31], 1, v[30:31]
v_ashrrev_i32_e32 v39, 31, v38
v_add_co_u32 v32, vcc_lo, s2, v32
v_ashrrev_i32_e32 v37, 31, v36
v_add_co_ci_u32_e32 v33, vcc_lo, s3, v33, vcc_lo
v_add_co_u32 v30, vcc_lo, s2, v30
global_store_dword v[34:35], v29, off
v_add_co_ci_u32_e32 v31, vcc_lo, s3, v31, vcc_lo
v_lshlrev_b64 v[28:29], 1, v[36:37]
global_store_dword v[32:33], v25, off
global_store_dword v[30:31], v27, off
v_lshlrev_b64 v[24:25], 1, v[38:39]
v_ashrrev_i32_e32 v27, 31, v26
v_add_nc_u32_e32 v30, 0x1602, v23
v_add_co_u32 v28, vcc_lo, s2, v28
v_add_nc_u32_e32 v32, 0x1800, v23
v_add_co_ci_u32_e32 v29, vcc_lo, s3, v29, vcc_lo
v_add_co_u32 v24, vcc_lo, s2, v24
v_ashrrev_i32_e32 v31, 31, v30
v_lshlrev_b64 v[26:27], 1, v[26:27]
v_add_co_ci_u32_e32 v25, vcc_lo, s3, v25, vcc_lo
v_ashrrev_i32_e32 v33, 31, v32
global_store_dword v[28:29], v21, off
global_store_dword v[24:25], v22, off
v_lshlrev_b64 v[21:22], 1, v[30:31]
v_add_co_u32 v24, vcc_lo, s2, v26
v_add_nc_u32_e32 v28, 0x1802, v23
v_add_co_ci_u32_e32 v25, vcc_lo, s3, v27, vcc_lo
v_lshlrev_b64 v[26:27], 1, v[32:33]
v_add_nc_u32_e32 v30, 0x1a00, v23
v_add_co_u32 v21, vcc_lo, s2, v21
v_ashrrev_i32_e32 v29, 31, v28
v_add_co_ci_u32_e32 v22, vcc_lo, s3, v22, vcc_lo
global_store_dword v[24:25], v19, off
v_add_co_u32 v26, vcc_lo, s2, v26
v_ashrrev_i32_e32 v31, 31, v30
v_add_co_ci_u32_e32 v27, vcc_lo, s3, v27, vcc_lo
v_lshlrev_b64 v[24:25], 1, v[28:29]
v_add_nc_u32_e32 v28, 0x1c02, v23
global_store_dword v[21:22], v20, off
global_store_dword v[26:27], v18, off
v_add_nc_u32_e32 v20, 0x1a02, v23
v_lshlrev_b64 v[18:19], 1, v[30:31]
v_add_nc_u32_e32 v26, 0x1c00, v23
v_add_co_u32 v24, vcc_lo, s2, v24
v_ashrrev_i32_e32 v29, 31, v28
v_ashrrev_i32_e32 v21, 31, v20
v_add_co_ci_u32_e32 v25, vcc_lo, s3, v25, vcc_lo
v_add_co_u32 v18, vcc_lo, s2, v18
v_ashrrev_i32_e32 v27, 31, v26
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
v_lshlrev_b64 v[20:21], 1, v[20:21]
global_store_dword v[24:25], v16, off
global_store_dword v[18:19], v15, off
v_lshlrev_b64 v[15:16], 1, v[26:27]
v_add_nc_u32_e32 v24, 0x1e00, v23
v_add_co_u32 v18, vcc_lo, s2, v20
v_add_nc_u32_e32 v26, 0x1e02, v23
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v21, vcc_lo
v_lshlrev_b64 v[20:21], 1, v[28:29]
v_add_co_u32 v15, vcc_lo, s2, v15
v_ashrrev_i32_e32 v25, 31, v24
v_add_co_ci_u32_e32 v16, vcc_lo, s3, v16, vcc_lo
v_ashrrev_i32_e32 v27, 31, v26
global_store_dword v[18:19], v14, off
v_add_co_u32 v20, vcc_lo, s2, v20
v_lshlrev_b64 v[18:19], 1, v[24:25]
v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo
v_add_nc_u32_e32 v14, 0x2000, v23
v_add_nc_u32_e32 v24, 0x2200, v23
global_store_dword v[15:16], v11, off
global_store_dword v[20:21], v12, off
v_lshlrev_b64 v[11:12], 1, v[26:27]
v_ashrrev_i32_e32 v15, 31, v14
v_add_nc_u32_e32 v20, 0x2002, v23
v_add_co_u32 v18, vcc_lo, s2, v18
v_ashrrev_i32_e32 v25, 31, v24
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
v_add_co_u32 v11, vcc_lo, s2, v11
v_ashrrev_i32_e32 v21, 31, v20
v_lshlrev_b64 v[14:15], 1, v[14:15]
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
global_store_dword v[18:19], v5, off
global_store_dword v[11:12], v6, off
v_lshlrev_b64 v[5:6], 1, v[20:21]
v_add_co_u32 v11, vcc_lo, s2, v14
v_add_nc_u32_e32 v18, 0x2202, v23
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v15, vcc_lo
v_lshlrev_b64 v[14:15], 1, v[24:25]
v_add_nc_u32_e32 v20, 0x2400, v23
v_add_co_u32 v5, vcc_lo, s2, v5
v_ashrrev_i32_e32 v19, 31, v18
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_store_dword v[11:12], v3, off
v_add_co_u32 v14, vcc_lo, s2, v14
v_ashrrev_i32_e32 v21, 31, v20
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
v_lshlrev_b64 v[11:12], 1, v[18:19]
global_store_dword v[5:6], v4, off
global_store_dword v[14:15], v2, off
v_lshlrev_b64 v[2:3], 1, v[20:21]
v_add_nc_u32_e32 v4, 0x2402, v23
v_add_co_u32 v11, vcc_lo, s2, v11
v_add_nc_u32_e32 v14, 0x2600, v23
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v2, vcc_lo, s2, v2
v_ashrrev_i32_e32 v15, 31, v14
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_dword v[11:12], v1, off
v_add_nc_u32_e32 v11, 0x2800, v23
v_lshlrev_b64 v[4:5], 1, v[4:5]
v_ashrrev_i32_e32 v1, 31, v0
global_store_dword v[2:3], v17, off
v_lshlrev_b64 v[2:3], 1, v[14:15]
v_add_nc_u32_e32 v14, 0x2802, v23
v_ashrrev_i32_e32 v12, 31, v11
v_add_co_u32 v4, vcc_lo, s2, v4
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_ashrrev_i32_e32 v15, 31, v14
v_add_co_u32 v2, vcc_lo, s2, v2
v_lshlrev_b64 v[11:12], 1, v[11:12]
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_lshlrev_b64 v[14:15], 1, v[14:15]
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v11, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
v_add_co_u32 v14, vcc_lo, s2, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
global_store_dword v[4:5], v9, off
global_store_dword v[2:3], v13, off
global_store_dword v[0:1], v8, off
global_store_dword v[11:12], v10, off
global_store_dword v[14:15], v7, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel1
.amdhsa_group_segment_fixed_size 38144
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 110
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end37:
.size tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel1, .Lfunc_end37-tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel1
.globl tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel2
.p2align 8
.type tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel2,@function
tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel2:
s_mul_i32 s6, s6, 28
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_add_nc_u32_e32 v0, s6, v0
s_mov_b32 s16, 0xa800
s_mov_b32 s17, 0x15000
s_mov_b32 s18, 0x1f800
s_mov_b32 s9, 0x3f000
v_lshrrev_b32_e32 v1, 1, v0
v_lshlrev_b32_e32 v2, 4, v0
v_and_b32_e32 v0, 0xfffffc1f, v0
s_mov_b32 s10, 0x49800
s_mov_b32 s19, 0x2a000
v_and_b32_e32 v1, 0x1e0, v1
v_and_b32_e32 v2, 0x200, v2
s_mov_b32 s12, 0x54000
s_mov_b32 s22, 0x34800
s_mov_b32 s7, 0x5e800
s_mov_b32 s8, 0x69000
v_or3_b32 v0, v0, v2, v1
s_mov_b32 s2, 0x7e000
s_mov_b32 s6, 0x73800
s_mov_b32 s3, 0x9d800
s_load_dwordx2 s[20:21], s[4:5], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_movk_i32 s11, 0x3000
s_movk_i32 s5, 0x3400
s_mov_b32 s4, 0xc800
s_mov_b32 s15, 0xb000
v_lshlrev_b64 v[26:27], 1, v[0:1]
s_movk_i32 s14, 0x4800
s_mov_b32 s13, 0xb400
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v26
s_mov_b32 s0, 0x93000
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v27, vcc_lo
s_mov_b32 s1, 0x88800
v_add_co_u32 v0, vcc_lo, s16, v3
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s17, v3
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v10, vcc_lo, s18, v3
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v13, vcc_lo, s9, v3
s_clause 0x2
global_load_ushort v12, v[3:4], off
global_load_ushort v6, v[0:1], off
global_load_ushort v5, v[7:8], off
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v15, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, 0xdc800, v3
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v17, vcc_lo, s19, v3
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v4, vcc_lo
s_clause 0x2
global_load_ushort v9, v[13:14], off
global_load_ushort v7, v[15:16], off
global_load_ushort v0, v[0:1], off
v_add_co_u32 v1, vcc_lo, 0xe7000, v3
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v19, vcc_lo, 0x11b800, v3
s_clause 0x1
global_load_ushort v15, v[10:11], off
global_load_ushort v13, v[17:18], off
v_add_co_ci_u32_e32 v20, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v10, vcc_lo, s12, v3
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v16, vcc_lo, s22, v3
s_clause 0x1
global_load_ushort v2, v[1:2], off
global_load_ushort v1, v[19:20], off
v_add_co_ci_u32_e32 v17, vcc_lo, 0, v4, vcc_lo
s_clause 0x1
global_load_ushort v44, v[10:11], off
global_load_ushort v45, v[16:17], off
v_add_co_u32 v10, vcc_lo, s7, v3
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
global_load_ushort v46, v[10:11], off
v_add_co_u32 v10, vcc_lo, 0x126000, v3
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
global_load_ushort v8, v[10:11], off
v_add_co_u32 v10, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
global_load_ushort v47, v[10:11], off
v_add_co_u32 v10, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v16, vcc_lo, s1, v3
v_add_co_ci_u32_e32 v17, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v18, vcc_lo, s6, v3
global_load_ushort v48, v[10:11], off
v_add_co_ci_u32_e32 v19, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v10, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
s_clause 0x2
global_load_ushort v25, v[16:17], off
global_load_ushort v49, v[18:19], off
global_load_ushort v24, v[10:11], off
v_add_co_u32 v10, vcc_lo, s3, v3
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
global_load_ushort v23, v[10:11], off
v_add_co_u32 v10, vcc_lo, 0xa8000, v3
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
global_load_ushort v22, v[10:11], off
v_add_co_u32 v10, vcc_lo, 0xb2800, v3
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
global_load_ushort v20, v[10:11], off
v_add_co_u32 v10, vcc_lo, 0xc7800, v3
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v17, vcc_lo, 0xd2000, v3
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v4, vcc_lo
s_clause 0x1
global_load_ushort v16, v[10:11], off
global_load_ushort v14, v[17:18], off
v_add_co_u32 v10, vcc_lo, 0xbd000, v3
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
global_load_ushort v21, v[10:11], off
v_add_co_u32 v10, vcc_lo, 0x106800, v3
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v17, vcc_lo, 0x111000, v3
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v4, vcc_lo
s_clause 0x1
global_load_ushort v11, v[10:11], off
global_load_ushort v10, v[17:18], off
v_add_co_u32 v17, vcc_lo, 0xf1800, v3
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v28, vcc_lo, 0xfc000, v3
v_add_co_ci_u32_e32 v29, vcc_lo, 0, v4, vcc_lo
s_clause 0x1
global_load_ushort v18, v[17:18], off
global_load_ushort v19, v[28:29], off
v_add_co_u32 v28, vcc_lo, 0x130800, v3
v_add_co_ci_u32_e32 v29, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v26, vcc_lo, s20, v26
v_add_co_ci_u32_e32 v27, vcc_lo, s21, v27, vcc_lo
global_load_ushort v17, v[28:29], off
v_add_co_u32 v28, vcc_lo, s16, v26
v_add_co_ci_u32_e32 v29, vcc_lo, 0, v27, vcc_lo
v_add_co_u32 v30, vcc_lo, s17, v26
v_add_co_ci_u32_e32 v31, vcc_lo, 0, v27, vcc_lo
v_add_co_u32 v32, vcc_lo, s18, v26
v_add_co_ci_u32_e32 v33, vcc_lo, 0, v27, vcc_lo
v_add_co_u32 v34, vcc_lo, s19, v26
v_add_co_ci_u32_e32 v35, vcc_lo, 0, v27, vcc_lo
v_add_co_u32 v36, vcc_lo, s22, v26
v_add_co_ci_u32_e32 v37, vcc_lo, 0, v27, vcc_lo
v_add_co_u32 v38, vcc_lo, 0x13b000, v3
v_add_co_ci_u32_e32 v39, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v40, vcc_lo, 0x145800, v3
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v4, vcc_lo
global_load_ushort v50, v[38:39], off
v_add_co_u32 v38, vcc_lo, 0x150000, v3
v_add_co_ci_u32_e32 v39, vcc_lo, 0, v4, vcc_lo
global_load_ushort v51, v[40:41], off
v_add_co_u32 v40, vcc_lo, 0x15a800, v3
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v4, vcc_lo
global_load_ushort v52, v[38:39], off
v_add_co_u32 v38, vcc_lo, s9, v26
v_add_co_ci_u32_e32 v39, vcc_lo, 0, v27, vcc_lo
global_load_ushort v53, v[40:41], off
v_add_co_u32 v40, vcc_lo, 0x165000, v3
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v42, vcc_lo, s10, v26
v_add_co_ci_u32_e32 v43, vcc_lo, 0, v27, vcc_lo
v_add_co_u32 v3, vcc_lo, 0x16f800, v3
global_load_ushort v54, v[40:41], off
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v40, vcc_lo, s12, v26
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v27, vcc_lo
global_load_ushort v55, v[3:4], off
s_waitcnt vmcnt(35)
v_add_f16_e32 v12, 0, v12
s_waitcnt vmcnt(34)
v_sub_f16_e32 v3, 0, v6
v_add_f16_e32 v4, 0, v6
v_add_f16_e32 v12, v12, v6
s_waitcnt vmcnt(33)
v_add_f16_e32 v3, v3, v5
v_add_f16_e32 v4, v4, v5
v_add_f16_e32 v6, v12, v5
v_mov_b32_e32 v58, v3
s_waitcnt vmcnt(31)
v_add_f16_e32 v56, 0, v7
v_sub_f16_e32 v12, 0, v9
s_waitcnt vmcnt(30)
v_mul_f16_e32 v57, 0.5, v0
s_waitcnt vmcnt(29)
v_add_f16_e32 v6, v6, v15
v_fmac_f16_e32 v3, s11, v15
v_fmac_f16_e32 v4, s5, v15
v_fmac_f16_e32 v58, 0.5, v15
v_sub_f16_e32 v12, v12, v7
s_waitcnt vmcnt(28)
v_add_f16_e32 v6, v6, v13
v_fmac_f16_e32 v3, s4, v13
v_fmac_f16_e32 v4, 4.0, v13
v_fmac_f16_e32 v58, -2.0, v13
v_sub_f16_e32 v15, 0, v7
v_add_f16_e32 v6, v6, v9
v_add_f16_e32 v9, 0, v9
s_waitcnt vmcnt(24)
v_add_f16_e32 v3, v3, v45
v_sub_f16_e32 v13, v56, v44
v_add_f16_e32 v4, v4, v7
v_add_f16_e32 v6, v6, v7
v_add_f16_e32 v9, v9, v7
v_sub_f16_e32 v58, v58, v7
v_sub_f16_e32 v3, v3, v7
v_mov_b32_e32 v7, v13
s_waitcnt vmcnt(23)
v_fmac_f16_e32 v13, s15, v46
v_sub_f16_e32 v45, v15, v44
v_sub_f16_e32 v12, v12, v44
v_add_f16_e32 v9, v9, v44
v_add_f16_e32 v6, v6, v44
v_add_f16_e32 v3, v44, v3
v_fmac_f16_e32 v45, s13, v46
v_fmac_f16_e32 v7, -0.5, v46
v_add_f16_e32 v15, v15, v44
v_add_f16_e32 v56, v56, v44
v_add_f16_e32 v4, v4, v44
v_add_f16_e32 v58, v58, v44
v_sub_f16_e32 v12, v12, v46
v_mov_b32_e32 v44, v15
v_fmac_f16_e32 v15, s11, v46
v_add_f16_e32 v9, v9, v46
s_waitcnt vmcnt(21)
v_fmac_f16_e32 v13, s14, v47
v_add_f16_e32 v6, v6, v46
v_fmac_f16_e32 v3, s11, v46
v_fmac_f16_e32 v45, -4.0, v47
v_fmac_f16_e32 v7, 2.0, v47
v_fmac_f16_e32 v56, s5, v46
v_fmac_f16_e32 v44, 0.5, v46
v_fmac_f16_e32 v4, s5, v46
v_fmac_f16_e32 v58, 0.5, v46
v_fmac_f16_e32 v15, s4, v47
v_sub_f16_e32 v12, v12, v47
v_add_f16_e32 v9, v9, v47
v_add_f16_e32 v6, v6, v47
s_waitcnt vmcnt(18)
v_sub_f16_e32 v13, v13, v49
v_fmac_f16_e32 v3, s4, v47
v_add_f16_e32 v45, v45, v25
v_sub_f16_e32 v7, v7, v25
v_fmac_f16_e32 v56, 4.0, v47
v_sub_f16_e32 v13, v13, v25
v_fmac_f16_e32 v44, -2.0, v47
v_fmac_f16_e32 v4, 4.0, v47
v_fmac_f16_e32 v58, -2.0, v47
v_add_f16_e32 v12, v12, v48
s_waitcnt vmcnt(17)
v_add_f16_e32 v13, v24, v13
v_add_f16_e32 v9, v9, v48
v_add_f16_e32 v6, v6, v48
v_add_f16_e32 v15, v15, v49
v_add_f16_e32 v3, v49, v3
v_add_f16_e32 v45, v45, v24
v_add_f16_e32 v7, v7, v24
s_waitcnt vmcnt(16)
v_fmac_f16_e32 v13, s11, v23
v_add_f16_e32 v56, v56, v25
v_sub_f16_e32 v44, v44, v25
v_sub_f16_e32 v15, v15, v25
v_add_f16_e32 v12, v12, v25
v_fmac_f16_e32 v45, s5, v23
v_add_f16_e32 v9, v9, v25
v_fmac_f16_e32 v7, 0.5, v23
v_add_f16_e32 v4, v4, v25
v_sub_f16_e32 v58, v58, v25
v_add_f16_e32 v6, v6, v25
v_sub_f16_e32 v3, v3, v25
s_waitcnt vmcnt(15)
v_fmac_f16_e32 v13, s4, v22
v_add_f16_e32 v56, v56, v24
v_add_f16_e32 v44, v44, v24
v_add_f16_e32 v15, v24, v15
v_add_f16_e32 v12, v12, v24
v_add_f16_e32 v9, v9, v24
v_add_f16_e32 v4, v4, v24
v_add_f16_e32 v58, v58, v24
v_add_f16_e32 v6, v6, v24
v_add_f16_e32 v3, v24, v3
v_fmac_f16_e32 v45, 4.0, v22
v_fmac_f16_e32 v7, -2.0, v22
s_waitcnt vmcnt(14)
v_add_f16_e32 v13, v20, v13
v_fmac_f16_e32 v56, s5, v23
v_fmac_f16_e32 v44, 0.5, v23
v_mov_b32_e32 v25, v45
v_mov_b32_e32 v24, v7
v_fmac_f16_e32 v15, s11, v23
v_add_f16_e32 v12, v12, v23
v_add_f16_e32 v9, v9, v23
v_fmac_f16_e32 v4, s5, v23
v_fmac_f16_e32 v58, 0.5, v23
v_add_f16_e32 v6, v6, v23
v_fmac_f16_e32 v3, s11, v23
v_mov_b32_e32 v23, v13
s_waitcnt vmcnt(13)
v_fmac_f16_e32 v25, 0.5, v16
v_fmac_f16_e32 v24, -0.5, v16
v_add_f16_e32 v12, v12, v22
v_add_f16_e32 v9, v9, v22
v_fmac_f16_e32 v23, -0.5, v16
s_waitcnt vmcnt(12)
v_fmac_f16_e32 v25, 0.5, v14
v_fmac_f16_e32 v24, 0.5, v14
v_add_f16_e32 v6, v6, v22
v_fmac_f16_e32 v3, s4, v22
v_fmac_f16_e32 v23, 0.5, v14
v_fmac_f16_e32 v25, s5, v57
v_fmac_f16_e32 v24, 0.5, v57
v_mul_f16_e32 v5, 0.5, v2
v_fmac_f16_e32 v4, 4.0, v22
v_fmac_f16_e32 v23, s11, v57
v_mov_b32_e32 v57, v12
v_fmac_f16_e32 v58, -2.0, v22
s_waitcnt vmcnt(11)
v_fmac_f16_e32 v9, s5, v21
v_fmac_f16_e32 v12, s11, v21
v_add_f16_e32 v3, v20, v3
v_fmac_f16_e32 v57, 0.5, v21
v_add_f16_e32 v6, v6, v21
v_fmac_f16_e32 v9, s5, v16
v_fmac_f16_e32 v12, s11, v16
v_add_f16_e32 v4, v4, v16
v_fmac_f16_e32 v57, 0.5, v16
v_fmac_f16_e32 v25, 4.0, v5
v_fmac_f16_e32 v24, -2.0, v5
v_fmac_f16_e32 v23, s4, v5
v_add_f16_e32 v5, v6, v16
v_sub_f16_e32 v3, v3, v16
v_sub_f16_e32 v58, v58, v16
v_fmac_f16_e32 v9, s5, v14
v_add_f16_e32 v4, v4, v14
v_fmac_f16_e32 v57, 0.5, v14
v_add_f16_e32 v5, v5, v14
v_add_f16_e32 v21, v58, v14
v_add_f16_e32 v3, v14, v3
v_fmac_f16_e32 v12, s11, v14
v_fmac_f16_e32 v13, s15, v16
v_fmac_f16_e32 v9, s5, v0
v_fmac_f16_e32 v4, s5, v0
v_fmac_f16_e32 v57, 0.5, v0
v_fmac_f16_e32 v21, 0.5, v0
v_add_f16_e32 v5, v5, v0
v_fmac_f16_e32 v3, s11, v0
v_fmac_f16_e32 v12, s11, v0
v_mul_f16_e32 v47, s5, v0
v_mul_f16_e32 v0, s11, v0
v_fmac_f16_e32 v13, s11, v14
v_fmac_f16_e32 v44, -2.0, v22
v_fmac_f16_e32 v9, s5, v2
v_fmac_f16_e32 v4, 4.0, v2
v_fmac_f16_e32 v57, 0.5, v2
v_fmac_f16_e32 v3, s4, v2
v_add_f16_e32 v5, v5, v2
v_fmac_f16_e32 v12, s11, v2
v_fmac_f16_e32 v21, -2.0, v2
v_mul_f16_e32 v48, s5, v2
v_mul_f16_e32 v2, s11, v2
v_fmac_f16_e32 v13, s11, v0
v_fmac_f16_e32 v44, s13, v16
v_fmac_f16_e32 v15, s4, v22
v_fmac_f16_e32 v7, s15, v16
s_waitcnt vmcnt(8)
v_fmac_f16_e32 v23, 0.5, v18
v_fmac_f16_e32 v13, s4, v2
v_fmac_f16_e32 v44, s5, v14
s_waitcnt vmcnt(7)
v_fmac_f16_e32 v12, s4, v19
v_fmac_f16_e32 v45, s11, v16
v_add_f16_e32 v15, v20, v15
v_add_f16_e32 v3, v18, v3
v_fmac_f16_e32 v57, -2.0, v19
v_fmac_f16_e32 v7, s11, v14
v_fmac_f16_e32 v13, s11, v18
v_fmac_f16_e32 v56, 4.0, v22
v_fmac_f16_e32 v44, 0.5, v47
v_fmac_f16_e32 v23, 2.0, v11
v_fmac_f16_e32 v12, s4, v11
v_fmac_f16_e32 v45, s11, v14
v_add_f16_e32 v4, v4, v11
v_add_f16_e32 v5, v5, v19
v_sub_f16_e32 v3, v3, v11
v_fmac_f16_e32 v15, s13, v16
v_fmac_f16_e32 v25, -2.0, v11
v_fmac_f16_e32 v24, 2.0, v11
v_sub_f16_e32 v6, v21, v11
v_fmac_f16_e32 v9, 4.0, v19
v_fmac_f16_e32 v57, -2.0, v11
v_fmac_f16_e32 v7, 0.5, v0
v_fmac_f16_e32 v13, s14, v11
v_fmac_f16_e32 v45, s5, v0
v_fmac_f16_e32 v56, s5, v16
v_fmac_f16_e32 v44, -2.0, v48
v_fmac_f16_e32 v12, s4, v10
v_mul_f16_e32 v59, -2.0, v1
v_fmac_f16_e32 v23, -2.0, v10
v_add_f16_e32 v4, v4, v10
v_add_f16_e32 v5, v5, v11
v_add_f16_e32 v3, v10, v3
v_fmac_f16_e32 v15, s5, v14
v_fmac_f16_e32 v25, -2.0, v10
v_fmac_f16_e32 v24, -2.0, v10
v_add_f16_e32 v6, v6, v10
v_fmac_f16_e32 v9, 4.0, v11
v_fmac_f16_e32 v57, -2.0, v10
v_fmac_f16_e32 v7, -2.0, v2
v_mul_f16_e32 v0, s4, v1
v_fmac_f16_e32 v13, s4, v10
v_fmac_f16_e32 v45, 4.0, v2
v_fmac_f16_e32 v56, s5, v14
v_fmac_f16_e32 v44, -4.0, v11
v_fmac_f16_e32 v12, s4, v1
v_mul_f16_e32 v46, -2.0, v8
v_fmac_f16_e32 v23, s11, v59
v_fmac_f16_e32 v4, s5, v1
v_add_f16_e32 v5, v5, v10
v_fmac_f16_e32 v3, s11, v1
v_fmac_f16_e32 v15, s11, v47
v_fmac_f16_e32 v25, s5, v59
v_fmac_f16_e32 v24, 0.5, v59
v_fmac_f16_e32 v6, 0.5, v1
v_fmac_f16_e32 v9, 4.0, v10
v_fmac_f16_e32 v57, -2.0, v1
v_fmac_f16_e32 v7, s14, v11
v_mul_f16_e32 v2, s4, v8
v_fmac_f16_e32 v13, s11, v0
v_fmac_f16_e32 v56, s5, v47
v_fmac_f16_e32 v23, s4, v46
v_fmac_f16_e32 v45, s4, v11
v_mul_f16_e32 v49, 4.0, v1
v_fmac_f16_e32 v44, 4.0, v10
v_fmac_f16_e32 v12, s4, v8
v_fmac_f16_e32 v4, 4.0, v8
v_add_f16_e32 v5, v5, v1
v_fmac_f16_e32 v3, s4, v8
v_fmac_f16_e32 v15, s4, v48
v_fmac_f16_e32 v25, 4.0, v46
v_fmac_f16_e32 v24, -2.0, v46
v_fmac_f16_e32 v6, -2.0, v8
v_fmac_f16_e32 v9, 4.0, v1
v_fmac_f16_e32 v7, s4, v10
v_fmac_f16_e32 v13, s4, v2
v_fmac_f16_e32 v57, -2.0, v8
v_fmac_f16_e32 v56, 4.0, v48
s_waitcnt vmcnt(5)
v_add_f16_e32 v1, v12, v50
v_fmac_f16_e32 v45, s4, v10
v_mul_f16_e32 v22, 4.0, v8
v_fmac_f16_e32 v44, 0.5, v49
v_fmac_f16_e32 v23, -2.0, v17
global_store_short v[30:31], v4, off
v_add_f16_e32 v4, v5, v8
v_fmac_f16_e32 v15, s5, v18
v_add_f16_e32 v3, v17, v3
global_store_short v[38:39], v25, off
global_store_short v[36:37], v24, off
global_store_short v[28:29], v6, off
global_store_short v[34:35], v57, off
global_store_short v[42:43], v23, off
global_store_short v[26:27], v4, off
global_store_short v[32:33], v3, off
v_add_co_u32 v3, vcc_lo, s7, v26
v_fmac_f16_e32 v7, 0.5, v0
v_fmac_f16_e32 v9, 4.0, v8
v_fmac_f16_e32 v13, s4, v17
v_fmac_f16_e32 v56, 4.0, v11
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v27, vcc_lo
v_fmac_f16_e32 v45, s5, v0
v_fmac_f16_e32 v44, -2.0, v22
s_waitcnt vmcnt(4)
v_add_f16_e32 v1, v1, v51
v_fmac_f16_e32 v15, -4.0, v11
v_fmac_f16_e32 v7, -2.0, v2
global_store_short v[40:41], v9, off
global_store_short v[3:4], v44, off
v_sub_f16_e32 v4, v13, v51
v_fmac_f16_e32 v56, 4.0, v10
s_waitcnt vmcnt(3)
v_add_f16_e32 v0, v1, v52
v_fmac_f16_e32 v45, 4.0, v2
v_fmac_f16_e32 v15, 4.0, v10
v_add_co_u32 v5, vcc_lo, s8, v26
v_add_f16_e32 v8, v4, v52
v_sub_f16_e32 v1, v7, v51
v_fmac_f16_e32 v56, s5, v49
s_waitcnt vmcnt(2)
v_add_f16_e32 v2, v0, v53
v_add_f16_e32 v3, v45, v51
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v27, vcc_lo
v_fmac_f16_e32 v15, s11, v49
v_add_co_u32 v0, vcc_lo, s6, v26
v_add_f16_e32 v10, v1, v52
v_fmac_f16_e32 v8, s11, v53
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v27, vcc_lo
v_add_f16_e32 v12, v3, v52
v_fmac_f16_e32 v56, 4.0, v22
s_waitcnt vmcnt(1)
v_add_f16_e32 v11, v2, v54
v_add_co_u32 v2, vcc_lo, s2, v26
v_fmac_f16_e32 v15, s4, v22
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v27, vcc_lo
v_add_co_u32 v4, vcc_lo, s1, v26
v_fmac_f16_e32 v10, 0.5, v53
v_fmac_f16_e32 v8, s4, v54
v_fmac_f16_e32 v12, s5, v53
global_store_short v[5:6], v56, off
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v27, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v26
v_fmac_f16_e32 v15, 4.0, v17
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v27, vcc_lo
s_waitcnt vmcnt(0)
v_add_f16_e32 v13, v8, v55
v_add_co_u32 v8, vcc_lo, s3, v26
v_fmac_f16_e32 v10, -2.0, v54
v_fmac_f16_e32 v12, 4.0, v54
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v27, vcc_lo
global_store_short v[0:1], v15, off
global_store_short v[2:3], v11, off
global_store_short v[4:5], v10, off
global_store_short v[6:7], v12, off
global_store_short v[8:9], v13, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel2
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 60
.amdhsa_next_free_sgpr 23
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end38:
.size tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel2, .Lfunc_end38-tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel2
.globl tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel3
.p2align 8
.type tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel3,@function
tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel3:
v_lshl_add_u32 v0, s6, 6, v0
s_mov_b32 s0, 0x51eb851f
s_load_dwordx2 s[2:3], s[4:5], 0x10
v_mul_hi_i32 v1, v0, s0
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v3, 14, v1
v_ashrrev_i32_e32 v1, 12, v1
v_add_nc_u32_e32 v3, v3, v2
v_add_nc_u32_e32 v1, v1, v2
v_mul_i32_i24_e32 v4, 0xc800, v3
v_mul_i32_i24_e32 v1, 0x3200, v1
v_mul_i32_i24_e32 v3, 0xe00, v3
v_sub_nc_u32_e32 v4, v0, v4
v_sub_nc_u32_e32 v1, v0, v1
v_mul_hi_i32 v2, v4, s0
v_and_b32_e32 v4, 0x1ff, v0
v_ashrrev_i32_e32 v6, 2, v1
v_bfe_u32 v1, v1, 9, 2
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_or_b32_e32 v3, v3, v4
v_lshrrev_b32_e32 v5, 31, v2
v_ashrrev_i32_e32 v2, 12, v2
v_mul_u32_u24_e32 v1, 0x5400, v1
v_add_nc_u32_e32 v2, v2, v5
v_and_b32_e32 v5, 0xfffffe00, v6
v_mad_i32_i24 v2, 0x15000, v2, v3
v_lshlrev_b32_e32 v3, 1, v4
v_add3_u32 v1, v2, v5, v1
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
global_load_ushort v3, v3, s[2:3]
global_load_ushort v2, v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f16_e32 v2, v3, v2
v_max_f16_e32 v2, 0, v2
global_store_short v[0:1], v2, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel3
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end39:
.size tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel3, .Lfunc_end39-tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel3
.globl tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel0
.p2align 8
.type tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel0,@function
tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel0:
v_lshrrev_b32_e32 v1, 4, v0
s_and_b32 s0, s6, -4
s_load_dwordx2 s[8:9], s[4:5], 0x0
v_add_nc_u32_e32 v2, s0, v1
s_lshl_b32 s0, s6, 4
s_and_b32 s7, s0, 48
s_movk_i32 s0, 0xc8
v_mul_hi_i32 v1, 0x51eb851f, v2
v_lshrrev_b32_e32 v3, 31, v1
v_ashrrev_i32_e32 v1, 5, v1
v_add_nc_u32_e32 v3, v1, v3
v_and_b32_e32 v1, 15, v0
v_mul_lo_u32 v4, 0x64, v3
v_mul_lo_u32 v5, 0x6400, v3
v_lshlrev_b32_e32 v13, 1, v3
v_sub_nc_u32_e32 v2, v2, v4
v_or3_b32 v4, v1, s7, v5
v_lshlrev_b32_e32 v5, 7, v2
v_lshlrev_b32_e32 v3, 1, v2
v_add_nc_u32_e32 v2, -1, v13
v_add3_u32 v7, v4, v5, 0xffffcdc0
v_add_nc_u32_e32 v6, -1, v3
v_cmp_gt_u32_e64 s2, 0xbc, v2
v_ashrrev_i32_e32 v8, 31, v7
v_cmp_gt_u32_e64 s1, s0, v6
v_lshlrev_b64 v[4:5], 1, v[7:8]
s_and_b32 s10, s2, s1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s8, v4
v_mov_b32_e32 v4, 0
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v5, vcc_lo
s_and_saveexec_b32 s3, s10
s_cbranch_execz BB40_2
global_load_ushort v2, v[8:9], off
s_waitcnt vmcnt(0)
v_add_f16_e32 v4, 0, v2
BB40_2:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_u32_e64 s0, s0, v3
v_mov_b32_e32 v5, 0
s_and_b32 s3, s2, s0
s_and_saveexec_b32 s10, s3
s_cbranch_execz BB40_4
global_load_ushort v5, v[8:9], off offset:128
BB40_4:
s_or_b32 exec_lo, exec_lo, s10
v_mov_b32_e32 v2, 0
s_and_saveexec_b32 s10, s3
s_cbranch_execz BB40_6
global_load_ushort v2, v[8:9], off offset:256
BB40_6:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v3, 2, v3
v_mov_b32_e32 v6, 0
v_cmp_gt_u32_e32 vcc_lo, 0xc8, v3
s_and_b32 s3, s2, vcc_lo
s_and_saveexec_b32 s2, s3
s_cbranch_execz BB40_8
global_load_ushort v6, v[8:9], off offset:384
BB40_8:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_u32_e64 s2, 0xbc, v13
v_mov_b32_e32 v3, 0
s_and_b32 s11, s2, s1
s_and_saveexec_b32 s10, s11
s_cbranch_execz BB40_10
v_add_nc_u32_e32 v8, 0x3200, v7
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 1, v[8:9]
v_add_co_u32 v8, s3, s8, v8
v_add_co_ci_u32_e64 v9, s3, s9, v9, s3
global_load_ushort v3, v[8:9], off
BB40_10:
s_or_b32 exec_lo, exec_lo, s10
v_mov_b32_e32 v9, 0
s_and_b32 s10, s2, s0
s_and_saveexec_b32 s12, s10
s_cbranch_execz BB40_12
v_add_nc_u32_e32 v8, 0x3240, v7
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 1, v[8:9]
v_add_co_u32 v8, s3, s8, v8
v_add_co_ci_u32_e64 v9, s3, s9, v9, s3
global_load_ushort v9, v[8:9], off
BB40_12:
s_or_b32 exec_lo, exec_lo, s12
v_mov_b32_e32 v8, 0
s_and_saveexec_b32 s12, s10
s_cbranch_execz BB40_14
v_add_nc_u32_e32 v10, 0x3280, v7
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 1, v[10:11]
v_add_co_u32 v10, s3, s8, v10
v_add_co_ci_u32_e64 v11, s3, s9, v11, s3
global_load_ushort v8, v[10:11], off
BB40_14:
s_or_b32 exec_lo, exec_lo, s12
v_mov_b32_e32 v10, 0
s_and_b32 s3, s2, vcc_lo
s_and_saveexec_b32 s12, s3
s_cbranch_execnz BB40_29
s_or_b32 exec_lo, exec_lo, s12
v_mov_b32_e32 v11, 0
s_and_saveexec_b32 s12, s11
s_cbranch_execnz BB40_30
BB40_16:
s_or_b32 exec_lo, exec_lo, s12
v_mov_b32_e32 v12, 0
s_and_saveexec_b32 s11, s10
s_cbranch_execnz BB40_31
BB40_17:
s_or_b32 exec_lo, exec_lo, s11
v_mov_b32_e32 v14, 0
s_and_saveexec_b32 s11, s10
s_cbranch_execnz BB40_32
BB40_18:
s_or_b32 exec_lo, exec_lo, s11
v_mov_b32_e32 v15, 0
s_and_saveexec_b32 s10, s3
s_cbranch_execz BB40_20
BB40_19:
v_add_nc_u32_e32 v15, 0x64c0, v7
v_ashrrev_i32_e32 v16, 31, v15
v_lshlrev_b64 v[15:16], 1, v[15:16]
v_add_co_u32 v15, s2, s8, v15
v_add_co_ci_u32_e64 v16, s2, s9, v16, s2
global_load_ushort v15, v[15:16], off
BB40_20:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v13, 2, v13
v_cmp_gt_u32_e64 s2, 0xbc, v13
v_mov_b32_e32 v13, 0
s_and_b32 s1, s2, s1
s_and_saveexec_b32 s3, s1
s_cbranch_execz BB40_22
v_add_nc_u32_e32 v16, 0x9600, v7
v_ashrrev_i32_e32 v17, 31, v16
v_lshlrev_b64 v[16:17], 1, v[16:17]
v_add_co_u32 v16, s1, s8, v16
v_add_co_ci_u32_e64 v17, s1, s9, v17, s1
global_load_ushort v13, v[16:17], off
BB40_22:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v16, 0
s_and_b32 s1, s2, s0
s_and_saveexec_b32 s3, s1
s_cbranch_execz BB40_24
v_add_nc_u32_e32 v16, 0x9640, v7
v_ashrrev_i32_e32 v17, 31, v16
v_lshlrev_b64 v[16:17], 1, v[16:17]
v_add_co_u32 v16, s0, s8, v16
v_add_co_ci_u32_e64 v17, s0, s9, v17, s0
global_load_ushort v16, v[16:17], off
BB40_24:
s_or_b32 exec_lo, exec_lo, s3
s_load_dwordx2 s[4:5], s[4:5], 0x8
v_mov_b32_e32 v17, 0
s_and_saveexec_b32 s3, s1
s_cbranch_execz BB40_26
v_add_nc_u32_e32 v17, 0x9680, v7
v_ashrrev_i32_e32 v18, 31, v17
v_lshlrev_b64 v[17:18], 1, v[17:18]
v_add_co_u32 v17, s0, s8, v17
v_add_co_ci_u32_e64 v18, s0, s9, v18, s0
global_load_ushort v17, v[17:18], off
BB40_26:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v18, 0
s_and_b32 s1, s2, vcc_lo
s_and_saveexec_b32 s0, s1
s_cbranch_execz BB40_28
v_add_nc_u32_e32 v18, 0x96c0, v7
v_ashrrev_i32_e32 v19, 31, v18
v_lshlrev_b64 v[18:19], 1, v[18:19]
v_add_co_u32 v18, vcc_lo, s8, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s9, v19, vcc_lo
global_load_ushort v18, v[18:19], off
BB40_28:
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b32 s0, s6, 6
s_waitcnt vmcnt(0)
v_sub_f16_e32 v4, v4, v2
s_and_b32 s0, s0, 0xffffff00
v_sub_f16_e32 v7, 0, v5
v_and_b32_e32 v0, 0xfc0, v0
v_add_f16_e32 v5, 0, v5
v_sub_f16_e32 v4, v4, v11
v_add_f16_e32 v20, 0, v9
v_add_f16_e32 v21, v2, v7
v_add_nc_u32_e32 v0, s0, v0
v_add_f16_e32 v2, v2, v5
v_add_f16_e32 v5, v7, v6
v_add_f16_e32 v4, v4, v14
v_add_f16_e32 v6, v21, v12
v_or3_b32 v0, v0, s7, v1
v_sub_f16_e32 v2, v2, v12
v_add_f16_e32 v5, v5, v12
v_sub_f16_e32 v19, 0, v3
v_sub_f16_e32 v21, v6, v14
v_ashrrev_i32_e32 v1, 31, v0
v_sub_f16_e32 v2, v2, v14
v_sub_f16_e32 v22, v5, v15
v_sub_f16_e32 v23, v20, v8
v_sub_f16_e32 v9, 0, v9
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_add_f16_e32 v19, v19, v8
v_add_f16_e32 v27, 0, v3
v_sub_f16_e32 v26, v20, v10
v_add_f16_e32 v10, v9, v10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
v_sub_f16_e32 v27, v27, v8
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_sub_f16_e32 v28, v26, v12
v_sub_f16_e32 v10, v10, v12
global_store_short v[0:1], v4, off
v_add_co_u32 v4, vcc_lo, 0x125800, v0
v_add_f16_e32 v10, v15, v10
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, 0x24b800, v0
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
global_store_short v[4:5], v21, off offset:1024
v_add_co_u32 v4, vcc_lo, 0x371000, v0
v_add_f16_e32 v21, v11, v19
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
global_store_short v[6:7], v2, off
global_store_short v[4:5], v22, off offset:1024
v_sub_f16_e32 v2, v23, v12
v_sub_f16_e32 v22, v9, v8
v_add_co_u32 v4, vcc_lo, 0x497000, v0
v_sub_f16_e32 v21, v21, v14
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v24, v14, v2
v_add_f16_e32 v2, v12, v22
v_add_co_u32 v6, vcc_lo, 0x5bc800, v0
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v25, v14, v2
v_add_co_u32 v2, vcc_lo, 0x6e2800, v0
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
global_store_short v[4:5], v21, off
global_store_short v[6:7], v24, off offset:1024
global_store_short v[2:3], v25, off
v_add_f16_e32 v5, v8, v9
v_add_f16_e32 v4, v11, v27
v_add_f16_e32 v7, v8, v20
v_add_co_u32 v2, vcc_lo, 0x808000, v0
v_add_f16_e32 v21, v15, v28
v_sub_f16_e32 v6, v5, v12
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
v_sub_f16_e32 v11, v4, v14
v_add_co_u32 v4, vcc_lo, 0x92e000, v0
v_add_f16_e32 v8, v12, v7
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v20, v14, v6
v_add_co_u32 v6, vcc_lo, 0xa53800, v0
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v14, v14, v8
v_add_co_u32 v8, vcc_lo, 0xb79800, v0
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo
global_store_short v[2:3], v21, off offset:1024
global_store_short v[4:5], v11, off
global_store_short v[6:7], v20, off offset:1024
global_store_short v[8:9], v14, off
v_add_f16_e32 v4, v19, v13
v_add_co_u32 v2, vcc_lo, 0xc9f000, v0
v_sub_f16_e32 v6, v23, v16
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v8, v22, v16
v_sub_f16_e32 v11, v4, v17
v_add_co_u32 v4, vcc_lo, 0xdc5000, v0
v_add_f16_e32 v12, v17, v6
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, 0xeea800, v0
v_sub_f16_e32 v14, v26, v16
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v13, v17, v8
v_add_co_u32 v8, vcc_lo, 0x1010800, v0
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, 0x1136000, v0
v_add_f16_e32 v14, v14, v18
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
global_store_short v[2:3], v10, off offset:1024
global_store_short v[4:5], v11, off
global_store_short v[6:7], v12, off offset:1024
global_store_short v[8:9], v13, off
global_store_short v[0:1], v14, off offset:1024
s_endpgm
BB40_29:
v_add_nc_u32_e32 v10, 0x32c0, v7
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 1, v[10:11]
v_add_co_u32 v10, s2, s8, v10
v_add_co_ci_u32_e64 v11, s2, s9, v11, s2
global_load_ushort v10, v[10:11], off
s_or_b32 exec_lo, exec_lo, s12
v_mov_b32_e32 v11, 0
s_and_saveexec_b32 s12, s11
s_cbranch_execz BB40_16
BB40_30:
v_add_nc_u32_e32 v11, 0x6400, v7
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 1, v[11:12]
v_add_co_u32 v11, s2, s8, v11
v_add_co_ci_u32_e64 v12, s2, s9, v12, s2
global_load_ushort v11, v[11:12], off
s_or_b32 exec_lo, exec_lo, s12
v_mov_b32_e32 v12, 0
s_and_saveexec_b32 s11, s10
s_cbranch_execz BB40_17
BB40_31:
v_add_nc_u32_e32 v14, 0x6440, v7
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[14:15], 1, v[14:15]
v_add_co_u32 v14, s2, s8, v14
v_add_co_ci_u32_e64 v15, s2, s9, v15, s2
global_load_ushort v12, v[14:15], off
s_or_b32 exec_lo, exec_lo, s11
v_mov_b32_e32 v14, 0
s_and_saveexec_b32 s11, s10
s_cbranch_execz BB40_18
BB40_32:
v_add_nc_u32_e32 v14, 0x6480, v7
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[14:15], 1, v[14:15]
v_add_co_u32 v14, s2, s8, v14
v_add_co_ci_u32_e64 v15, s2, s9, v15, s2
global_load_ushort v14, v[14:15], off
s_or_b32 exec_lo, exec_lo, s11
v_mov_b32_e32 v15, 0
s_and_saveexec_b32 s10, s3
s_cbranch_execnz BB40_19
s_branch BB40_20
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 29
.amdhsa_next_free_sgpr 13
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end40:
.size tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel0, .Lfunc_end40-tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel0
.globl tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel1
.p2align 8
.type tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel1,@function
tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel1:
s_clause 0x2
s_load_dwordx2 s[10:11], s[4:5], 0x0
s_load_dwordx2 s[8:9], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_mul_i32 s1, s6, 0xa00
v_lshlrev_b32_e32 v2, 4, v0
v_lshl_add_u32 v4, v0, 6, s1
s_mul_hi_i32 s0, s6, 0x8b70344b
v_lshrrev_b32_e32 v3, 5, v0
s_add_i32 s0, s0, s6
v_and_b32_e32 v6, 0x3fc0, v2
v_ashrrev_i32_e32 v5, 31, v4
s_lshr_b32 s5, s0, 31
s_lshr_b32 s0, s0, 7
s_movk_i32 s4, 0x400
s_add_i32 s0, s0, s5
v_lshlrev_b64 v[4:5], 1, v[4:5]
v_lshl_add_u32 v7, s0, 12, v6
v_mul_u32_u24_e32 v10, 0xa0, v3
v_lshlrev_b32_e32 v1, 1, v0
v_add_nc_u32_e32 v6, s4, v2
v_lshlrev_b32_e32 v2, 5, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v11, s0, s10, v4
v_lshl_add_u32 v10, v10, 1, s4
v_add_co_ci_u32_e64 v12, s0, s11, v5, s0
v_cmp_gt_i32_e32 vcc_lo, 40, v0
v_lshlrev_b32_e32 v8, 2, v0
v_and_b32_e32 v9, 0x3e0, v2
v_and_or_b32 v7, v1, 6, v7
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v24, 0
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v28, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v14, 0
s_mov_b32 s4, 0
s_branch BB41_2
BB41_1:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v29, s4, v7
v_mov_b32_e32 v71, 0xffff
s_add_i32 s4, s4, 8
s_cmp_eq_u32 s4, 64
v_ashrrev_i32_e32 v30, 31, v29
v_lshlrev_b64 v[29:30], 1, v[29:30]
v_add_co_u32 v29, s0, s8, v29
v_add_co_ci_u32_e64 v30, s0, s9, v30, s0
v_add_co_u32 v31, s0, v29, 0x1000
v_add_co_ci_u32_e64 v32, s0, 0, v30, s0
v_add_co_u32 v33, s0, 0x1800, v29
v_add_co_ci_u32_e64 v34, s0, 0, v30, s0
v_add_co_u32 v11, s0, v11, 16
s_clause 0x3
global_load_dword v29, v[29:30], off
global_load_dword v30, v[31:32], off
global_load_dword v31, v[31:32], off offset:-2048
global_load_dword v32, v[33:34], off
v_add_co_ci_u32_e64 v12, s0, 0, v12, s0
s_waitcnt vmcnt(1)
ds_write2st64_b32 v8, v29, v31 offset1:1
s_waitcnt vmcnt(0)
ds_write2st64_b32 v8, v30, v32 offset0:2 offset1:3
s_waitcnt lgkmcnt(0)
s_barrier
ds_read_b128 v[29:32], v9
ds_read_b128 v[33:36], v9 offset:16
ds_read_b64 v[37:38], v10 offset:64
ds_read_b64 v[39:40], v10 offset:96
ds_read2_b32 v[41:42], v10 offset0:22 offset1:23
ds_read_b64 v[43:44], v10 offset:80
ds_read2_b32 v[45:46], v10 offset0:18 offset1:19
ds_read_b64 v[47:48], v10 offset:128
ds_read2_b32 v[49:50], v10 offset0:30 offset1:31
ds_read_b64 v[51:52], v10 offset:112
ds_read2_b32 v[53:54], v10 offset0:26 offset1:27
ds_read_b64 v[55:56], v10 offset:160
ds_read2_b32 v[57:58], v10 offset0:38 offset1:39
ds_read_b64 v[59:60], v10 offset:144
ds_read2_b32 v[61:62], v10 offset0:34 offset1:35
ds_read2_b32 v[63:64], v10 offset0:46 offset1:47
ds_read_b64 v[65:66], v10 offset:176
ds_read2_b32 v[67:68], v10 offset0:42 offset1:43
ds_read2_b32 v[69:70], v10 offset0:48 offset1:51
s_waitcnt lgkmcnt(17)
v_lshrrev_b32_e32 v77, 16, v34
v_lshrrev_b32_e32 v78, 16, v35
v_lshrrev_b32_e32 v79, 16, v36
v_and_b32_e32 v72, v71, v29
v_and_b32_e32 v73, v71, v30
v_and_b32_e32 v74, v71, v31
v_and_b32_e32 v75, v71, v32
v_and_b32_sdwa v30, v71, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v80, v33, 16, v72
v_and_b32_sdwa v29, v71, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v31, v71, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v76, v71, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v71, 16, v33
s_waitcnt lgkmcnt(16)
v_pk_fma_f16 v28, v37, v80, v28 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(13)
v_pk_fma_f16 v27, v43, v80, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v39, v80, v26 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(9)
v_pk_fma_f16 v25, v51, v80, v25 op_sel_hi:[0,1,1]
v_lshl_or_b32 v81, v71, 16, v29
v_pk_fma_f16 v24, v47, v80, v24 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v23, v59, v80, v23 op_sel_hi:[0,1,1]
v_lshl_or_b32 v73, v34, 16, v73
v_lshl_or_b32 v74, v35, 16, v74
ds_read2_b32 v[32:33], v10 offset0:52 offset1:55
ds_read2_b32 v[34:35], v10 offset0:56 offset1:59
v_pk_fma_f16 v27, v43, v81, v27 op_sel:[1,0,0]
v_pk_fma_f16 v26, v39, v81, v26 op_sel:[1,0,0]
v_pk_fma_f16 v25, v51, v81, v25 op_sel:[1,0,0]
ds_read2_b32 v[71:72], v10 offset0:60 offset1:63
v_pk_fma_f16 v22, v55, v80, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v37, v81, v28 op_sel:[1,0,0]
v_lshl_or_b32 v77, v77, 16, v30
v_pk_fma_f16 v26, v40, v73, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v52, v73, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v55, v81, v22 op_sel:[1,0,0]
v_pk_fma_f16 v23, v59, v81, v23 op_sel:[1,0,0]
v_pk_fma_f16 v22, v38, v73, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v44, v73, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v47, v81, v24 op_sel:[1,0,0]
v_lshl_or_b32 v75, v36, 16, v75
v_pk_fma_f16 v39, v60, v73, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v51, v38, v77, v22 op_sel:[1,0,0]
v_pk_fma_f16 v55, v44, v77, v27 op_sel:[1,0,0]
v_pk_fma_f16 v36, v48, v73, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v40, v40, v77, v26 op_sel:[1,0,0]
v_pk_fma_f16 v52, v52, v77, v25 op_sel:[1,0,0]
ds_read2_b32 v[22:23], v10 offset0:49 offset1:50
ds_read2_b32 v[24:25], v10 offset0:53 offset1:54
ds_read2_b32 v[26:27], v10 offset0:57 offset1:58
ds_read2_b32 v[28:29], v10 offset0:61 offset1:62
s_waitcnt lgkmcnt(7)
v_pk_fma_f16 v20, v69, v80, v20 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(6)
v_pk_fma_f16 v19, v32, v80, v19 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v18, v34, v80, v18 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v17, v71, v80, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v65, v80, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v69, v81, v20 op_sel:[1,0,0]
v_pk_fma_f16 v19, v32, v81, v19 op_sel:[1,0,0]
v_pk_fma_f16 v18, v34, v81, v18 op_sel:[1,0,0]
v_pk_fma_f16 v17, v71, v81, v17 op_sel:[1,0,0]
v_pk_fma_f16 v21, v65, v81, v21 op_sel:[1,0,0]
v_pk_fma_f16 v59, v48, v77, v36 op_sel:[1,0,0]
ds_read2_b32 v[36:37], v10 offset0:64 offset1:67
v_pk_fma_f16 v60, v60, v77, v39 op_sel:[1,0,0]
ds_read2_b32 v[38:39], v10 offset0:68 offset1:71
ds_read2_b32 v[43:44], v10 offset0:72 offset1:75
ds_read2_b32 v[47:48], v10 offset0:76 offset1:79
s_waitcnt lgkmcnt(7)
v_pk_fma_f16 v20, v22, v73, v20 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(6)
v_pk_fma_f16 v19, v24, v73, v19 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v18, v26, v73, v18 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v17, v28, v73, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v66, v73, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v22, v77, v20 op_sel:[1,0,0]
v_pk_fma_f16 v19, v24, v77, v19 op_sel:[1,0,0]
v_pk_fma_f16 v18, v26, v77, v18 op_sel:[1,0,0]
v_pk_fma_f16 v17, v28, v77, v17 op_sel:[1,0,0]
v_lshl_or_b32 v65, v78, 16, v31
v_pk_fma_f16 v20, v23, v74, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v25, v74, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v27, v74, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v29, v74, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v66, v77, v21 op_sel:[1,0,0]
v_pk_fma_f16 v66, v23, v65, v20 op_sel:[1,0,0]
v_pk_fma_f16 v69, v25, v65, v19 op_sel:[1,0,0]
v_pk_fma_f16 v71, v27, v65, v18 op_sel:[1,0,0]
v_pk_fma_f16 v78, v29, v65, v17 op_sel:[1,0,0]
ds_read2_b32 v[17:18], v10 offset0:65 offset1:66
ds_read2_b32 v[19:20], v10 offset0:69 offset1:70
ds_read2_b32 v[21:22], v10 offset0:73 offset1:74
ds_read2_b32 v[23:24], v10 offset0:77 offset1:78
s_waitcnt lgkmcnt(7)
v_pk_fma_f16 v5, v36, v80, v5 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(6)
v_pk_fma_f16 v4, v38, v80, v4 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v2, v43, v80, v2 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v0, v47, v80, v0 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v56, v73, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v36, v81, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v38, v81, v4 op_sel:[1,0,0]
v_pk_fma_f16 v2, v43, v81, v2 op_sel:[1,0,0]
v_pk_fma_f16 v0, v47, v81, v0 op_sel:[1,0,0]
v_pk_fma_f16 v56, v56, v77, v30 op_sel:[1,0,0]
v_pk_fma_f16 v34, v63, v74, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v33, v75, v69 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v35, v75, v71 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v5, v17, v73, v5 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v4, v19, v73, v4 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v2, v21, v73, v2 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v0, v23, v73, v0 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v17, v77, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v19, v77, v4 op_sel:[1,0,0]
v_pk_fma_f16 v2, v21, v77, v2 op_sel:[1,0,0]
v_pk_fma_f16 v0, v23, v77, v0 op_sel:[1,0,0]
v_pk_fma_f16 v5, v18, v74, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v20, v74, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v22, v74, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v24, v74, v0 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v18, v65, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v20, v65, v4 op_sel:[1,0,0]
v_pk_fma_f16 v2, v22, v65, v2 op_sel:[1,0,0]
v_pk_fma_f16 v0, v24, v65, v0 op_sel:[1,0,0]
ds_read2_b64 v[17:20], v10 offset1:1
ds_read2_b64 v[21:24], v10 offset0:2 offset1:3
ds_read2_b64 v[25:28], v10 offset0:4 offset1:5
ds_read2_b64 v[29:32], v10 offset0:6 offset1:7
v_pk_fma_f16 v5, v37, v75, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v39, v75, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v44, v75, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v48, v75, v0 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v15, v17, v80, v15 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v16, v21, v80, v16 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v13, v25, v80, v13 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v14, v29, v80, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v17, v81, v15 op_sel:[1,0,0]
v_pk_fma_f16 v16, v21, v81, v16 op_sel:[1,0,0]
v_pk_fma_f16 v13, v25, v81, v13 op_sel:[1,0,0]
v_pk_fma_f16 v14, v29, v81, v14 op_sel:[1,0,0]
v_pk_fma_f16 v17, v45, v74, v51 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v18, v73, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v22, v73, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v26, v73, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v30, v73, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v53, v74, v40 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v18, v77, v15 op_sel:[1,0,0]
v_pk_fma_f16 v16, v22, v77, v16 op_sel:[1,0,0]
v_pk_fma_f16 v13, v26, v77, v13 op_sel:[1,0,0]
v_pk_fma_f16 v14, v30, v77, v14 op_sel:[1,0,0]
v_pk_fma_f16 v18, v41, v74, v55 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v19, v74, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v23, v74, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v27, v74, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v31, v74, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v49, v74, v52 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v61, v74, v59 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v57, v74, v60 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v67, v74, v56 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v19, v65, v15 op_sel:[1,0,0]
v_pk_fma_f16 v16, v23, v65, v16 op_sel:[1,0,0]
v_pk_fma_f16 v19, v53, v65, v21 op_sel:[1,0,0]
v_pk_fma_f16 v21, v49, v65, v22 op_sel:[1,0,0]
v_pk_fma_f16 v22, v61, v65, v25 op_sel:[1,0,0]
v_pk_fma_f16 v23, v57, v65, v26 op_sel:[1,0,0]
v_pk_fma_f16 v13, v27, v65, v13 op_sel:[1,0,0]
v_pk_fma_f16 v14, v31, v65, v14 op_sel:[1,0,0]
v_pk_fma_f16 v17, v45, v65, v17 op_sel:[1,0,0]
v_pk_fma_f16 v18, v41, v65, v18 op_sel:[1,0,0]
v_pk_fma_f16 v25, v67, v65, v30 op_sel:[1,0,0]
v_pk_fma_f16 v26, v63, v65, v34 op_sel:[1,0,0]
v_lshl_or_b32 v29, v79, 16, v76
v_pk_fma_f16 v15, v20, v75, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v24, v75, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v28, v75, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v32, v75, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v58, v75, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v42, v75, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v46, v75, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v54, v75, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v64, v75, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v50, v75, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v68, v75, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v62, v75, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v70, v75, v66 op_sel_hi:[0,1,1]
v_pk_fma_f16 v40, v72, v75, v78 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v20, v29, v15 op_sel:[1,0,0]
v_pk_fma_f16 v16, v24, v29, v16 op_sel:[1,0,0]
v_pk_fma_f16 v13, v28, v29, v13 op_sel:[1,0,0]
v_pk_fma_f16 v28, v46, v29, v17 op_sel:[1,0,0]
v_pk_fma_f16 v27, v42, v29, v18 op_sel:[1,0,0]
v_pk_fma_f16 v26, v54, v29, v19 op_sel:[1,0,0]
v_pk_fma_f16 v25, v50, v29, v21 op_sel:[1,0,0]
v_pk_fma_f16 v24, v62, v29, v22 op_sel:[1,0,0]
v_pk_fma_f16 v14, v32, v29, v14 op_sel:[1,0,0]
v_pk_fma_f16 v23, v58, v29, v23 op_sel:[1,0,0]
v_pk_fma_f16 v22, v68, v29, v30 op_sel:[1,0,0]
v_pk_fma_f16 v21, v64, v29, v31 op_sel:[1,0,0]
v_pk_fma_f16 v20, v70, v29, v34 op_sel:[1,0,0]
v_pk_fma_f16 v19, v33, v29, v36 op_sel:[1,0,0]
v_pk_fma_f16 v18, v35, v29, v38 op_sel:[1,0,0]
v_pk_fma_f16 v17, v72, v29, v40 op_sel:[1,0,0]
v_pk_fma_f16 v5, v37, v29, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v39, v29, v4 op_sel:[1,0,0]
v_pk_fma_f16 v2, v44, v29, v2 op_sel:[1,0,0]
v_pk_fma_f16 v0, v48, v29, v0 op_sel:[1,0,0]
s_cbranch_scc1 BB41_4
BB41_2:
s_barrier
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB41_1
global_load_dwordx4 v[29:32], v[11:12], off
s_waitcnt vmcnt(0)
ds_write_b128 v6, v[29:32]
s_branch BB41_1
BB41_4:
v_mad_u32_u24 v3, 0x500, v3, s1
v_and_or_b32 v6, v1, 62, v3
v_ashrrev_i32_e32 v7, 31, v6
v_add_nc_u32_e32 v9, 0x400, v6
v_add_nc_u32_e32 v11, 0x440, v6
v_lshlrev_b64 v[7:8], 1, v[6:7]
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
v_add_co_u32 v7, vcc_lo, s2, v7
v_lshlrev_b64 v[9:10], 1, v[9:10]
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
v_lshlrev_b64 v[11:12], 1, v[11:12]
global_store_dword v[7:8], v15, off
global_store_short v[7:8], v16, off offset:128
global_store_short_d16_hi v[7:8], v16, off offset:130
global_store_short v[7:8], v13, off offset:256
global_store_short_d16_hi v[7:8], v13, off offset:258
global_store_short v[7:8], v14, off offset:384
global_store_short_d16_hi v[7:8], v14, off offset:386
global_store_dword v[7:8], v28, off offset:512
global_store_dword v[7:8], v27, off offset:640
global_store_dword v[7:8], v26, off offset:768
global_store_dword v[7:8], v25, off offset:896
global_store_dword v[7:8], v24, off offset:1024
global_store_dword v[7:8], v23, off offset:1152
global_store_dword v[7:8], v22, off offset:1280
global_store_dword v[7:8], v21, off offset:1408
global_store_dword v[7:8], v20, off offset:1536
v_add_nc_u32_e32 v13, 0x480, v6
v_add_nc_u32_e32 v15, 0x4c0, v6
v_add_co_u32 v9, vcc_lo, s2, v9
global_store_dword v[7:8], v19, off offset:1664
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
v_ashrrev_i32_e32 v14, 31, v13
v_ashrrev_i32_e32 v16, 31, v15
v_add_co_u32 v11, vcc_lo, s2, v11
global_store_dword v[7:8], v18, off offset:1792
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
v_lshlrev_b64 v[13:14], 1, v[13:14]
v_lshlrev_b64 v[15:16], 1, v[15:16]
v_add_co_u32 v13, vcc_lo, s2, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
v_add_co_u32 v15, vcc_lo, s2, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s3, v16, vcc_lo
global_store_dword v[7:8], v17, off offset:1920
global_store_dword v[9:10], v5, off
global_store_dword v[11:12], v4, off
global_store_dword v[13:14], v2, off
global_store_dword v[15:16], v0, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel1
.amdhsa_group_segment_fixed_size 1664
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 82
.amdhsa_next_free_sgpr 12
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end41:
.size tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel1, .Lfunc_end41-tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel1
.globl tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel2
.p2align 8
.type tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel2,@function
tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel2:
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_lshl_add_u32 v0, s6, 6, v0
s_mov_b32 s2, 0x125800
s_mov_b32 s3, 0x24b800
s_mov_b32 s6, 0x371000
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s3, v2
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, 0x497000, v2
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v10, vcc_lo, 0x5bc800, v2
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v3, vcc_lo
s_clause 0x4
global_load_ushort v14, v[2:3], off
global_load_ushort v15, v[4:5], off offset:1024
global_load_ushort v16, v[6:7], off
global_load_ushort v17, v[8:9], off
global_load_ushort v18, v[10:11], off offset:1024
v_add_co_u32 v4, vcc_lo, 0x6e2800, v2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, 0x92e000, v2
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, 0xa53800, v2
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v10, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v12, vcc_lo, 0x808000, v2
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v3, vcc_lo
s_clause 0x4
global_load_ushort v19, v[4:5], off
global_load_ushort v20, v[6:7], off
global_load_ushort v8, v[8:9], off offset:1024
global_load_ushort v9, v[10:11], off offset:1024
global_load_ushort v10, v[12:13], off offset:1024
v_add_co_u32 v4, vcc_lo, 0xb79800, v2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, 0xc9f000, v2
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
s_clause 0x1
global_load_ushort v11, v[4:5], off
global_load_ushort v12, v[6:7], off offset:1024
v_add_co_u32 v4, vcc_lo, 0xdc5000, v2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, 0xeea800, v2
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
s_clause 0x1
global_load_ushort v13, v[4:5], off
global_load_ushort v6, v[6:7], off offset:1024
v_add_co_u32 v4, vcc_lo, 0x1010800, v2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, 0x1136000, v2
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_ushort v21, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_ushort v22, v[2:3], off offset:1024
s_waitcnt vmcnt(15)
v_add_f16_e32 v2, 0, v14
s_waitcnt vmcnt(14)
v_sub_f16_e32 v3, 0, v15
s_waitcnt vmcnt(12)
v_sub_f16_e32 v4, 0, v17
s_waitcnt vmcnt(11)
v_add_f16_e32 v5, 0, v18
v_add_f16_e32 v2, v2, v15
v_add_f16_e32 v3, v3, v16
v_sub_f16_e32 v4, v4, v18
v_add_f16_e32 v2, v2, v16
v_add_f16_e32 v2, v2, v17
s_waitcnt vmcnt(10)
v_sub_f16_e32 v5, v5, v19
v_sub_f16_e32 v4, v4, v19
s_waitcnt vmcnt(7)
v_add_f16_e32 v3, v3, v9
v_add_f16_e32 v2, v2, v18
s_waitcnt vmcnt(6)
v_sub_f16_e32 v5, v5, v10
v_add_f16_e32 v4, v4, v20
v_sub_f16_e32 v3, v3, v18
v_add_f16_e32 v7, v2, v19
v_sub_f16_e32 v5, v5, v8
v_add_f16_e32 v4, v4, v8
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_f16_e32 v3, v19, v3
v_add_f16_e32 v7, v7, v20
s_waitcnt vmcnt(5)
v_add_f16_e32 v5, v11, v5
v_add_f16_e32 v4, v4, v11
v_add_f16_e32 v9, v10, v3
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
s_waitcnt vmcnt(4)
v_add_f16_e32 v5, v12, v5
v_sub_f16_e32 v9, v9, v8
s_waitcnt vmcnt(3)
v_add_f16_e32 v10, v4, v13
s_waitcnt vmcnt(2)
v_sub_f16_e32 v13, v5, v6
v_add_f16_e32 v8, v7, v8
v_add_co_u32 v4, vcc_lo, s3, v0
v_add_f16_e32 v9, v11, v9
v_add_f16_e32 v10, v10, v6
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_f16_e32 v8, v8, v11
s_waitcnt vmcnt(1)
v_add_f16_e32 v13, v13, v21
v_add_co_u32 v6, vcc_lo, s6, v0
v_add_f16_e32 v9, v12, v9
v_add_f16_e32 v10, v10, v21
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f16_e32 v11, v13, v22
global_store_short v[0:1], v8, off
global_store_short v[2:3], v9, off offset:1024
global_store_short v[4:5], v10, off
global_store_short v[6:7], v11, off offset:1024
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel2
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end42:
.size tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel2, .Lfunc_end42-tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel2
.globl tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel3
.p2align 8
.type tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel3,@function
tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel3:
s_mul_hi_i32 s0, s6, 0x51eb851f
v_lshlrev_b32_e32 v3, 1, v0
s_lshr_b32 s1, s0, 31
s_ashr_i32 s2, s0, 7
s_ashr_i32 s0, s0, 6
s_add_i32 s2, s2, s1
s_add_i32 s0, s0, s1
s_mul_i32 s3, s2, 0x190
s_mulk_i32 s0, 0xc8
s_sub_i32 s3, s6, s3
s_sub_i32 s0, s6, s0
s_sext_i32_i16 s3, s3
s_lshl_b32 s0, s0, 5
s_mulk_i32 s3, 0x147b
s_andn2_b32 s0, s0, 63
s_lshr_b32 s7, s3, 31
s_ashr_i32 s3, s3, 20
s_mulk_i32 s2, 0x1900
v_add_nc_u16 v1, s3, s7
s_and_b32 s3, s6, 1
s_mul_i32 s3, s3, 0x92e00
v_bfe_i32 v1, v1, 0, 16
v_mul_lo_u32 v1, 0x125c00, v1
v_add_nc_u32_e32 v1, s0, v1
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_add_nc_u32_e32 v1, s2, v1
v_add3_u32 v1, v1, s3, v0
s_load_dwordx2 s[2:3], s[4:5], 0x10
v_lshl_add_u32 v0, s6, 6, v0
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
global_load_ushort v3, v3, s[2:3]
global_load_ushort v2, v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f16_e32 v2, v3, v2
v_max_f16_e32 v2, 0, v2
global_store_short v[0:1], v2, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel3
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end43:
.size tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel3, .Lfunc_end43-tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel3
.globl tvmgen_default_fused_nn_conv2d_add_1_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_1_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_1_kernel0:
v_lshrrev_b32_e32 v1, 5, v0
s_mov_b32 s0, 0x5397829d
v_add_nc_u32_e32 v4, 0x500, v0
v_add_nc_u32_e32 v5, 0x640, v0
v_add_nc_u32_e32 v6, 0x780, v0
v_add_nc_u32_e32 v2, 40, v1
s_clause 0x3
s_load_dwordx2 s[10:11], s[4:5], 0x0
s_load_dwordx2 s[12:13], s[4:5], 0x8
s_load_dwordx2 s[8:9], s[4:5], 0x10
s_load_dwordx2 s[2:3], s[4:5], 0x18
v_mul_hi_u32 v4, v4, s0
v_mul_hi_u32 v5, v5, s0
s_and_b32 s4, s6, 3
v_mul_hi_u32 v3, v2, s0
s_ashr_i32 s5, s6, 2
v_add_nc_u32_e32 v7, 0x8c0, v0
s_mulk_i32 s4, 0x3200
s_mul_i32 s6, s5, 0x32000
v_mul_hi_u32 v6, v6, s0
s_add_i32 s6, s6, s4
v_mul_hi_u32 v7, v7, s0
v_lshrrev_b32_e32 v3, 4, v3
v_and_or_b32 v9, v0, 31, s6
v_add_nc_u32_e32 v8, 0xa00, v0
v_lshrrev_b32_e32 v4, 9, v4
v_lshrrev_b32_e32 v5, 9, v5
v_mul_u32_u24_e32 v3, 49, v3
s_mov_b32 s7, 0xc800
v_lshl_add_u32 v41, v1, 8, v9
v_lshrrev_b32_e32 v7, 9, v7
s_movk_i32 s6, 0x100
v_sub_nc_u32_e32 v2, v2, v3
v_add_nc_u32_e32 v3, 41, v1
v_mul_i32_i24_e32 v1, s7, v4
v_mul_i32_i24_e32 v4, s7, v5
v_lshrrev_b32_e32 v5, 9, v6
v_mul_hi_u32 v6, v8, s0
v_mul_hi_u32 v8, v3, s0
v_lshlrev_b32_e32 v2, 8, v2
v_add3_u32 v43, v41, v4, s6
v_lshrrev_b32_e32 v46, 6, v0
v_lshlrev_b32_e32 v54, 2, v0
s_mov_b32 s1, 0x8000
v_add3_u32 v42, v9, v1, v2
v_mul_i32_i24_e32 v1, s7, v5
v_mul_i32_i24_e32 v2, s7, v7
v_lshrrev_b32_e32 v4, 9, v6
v_lshrrev_b32_e32 v5, 4, v8
v_add_nc_u32_e32 v6, 0xb40, v0
v_add3_u32 v44, v41, v1, 0xb00
v_add3_u32 v45, v41, v2, 0x1500
v_mul_i32_i24_e32 v1, s7, v4
v_mul_u32_u24_e32 v2, 49, v5
v_mul_hi_u32 v4, v6, s0
v_add_nc_u32_e32 v5, 0xc80, v0
v_add_nc_u32_e32 v6, 0xdc0, v0
v_add3_u32 v48, v41, v1, 0x1f00
v_sub_nc_u32_e32 v1, v3, v2
v_add_nc_u32_e32 v2, 0xf00, v0
v_mul_hi_u32 v3, v5, s0
v_mul_hi_u32 v5, v6, s0
v_add_nc_u32_e32 v6, 0x1040, v0
v_lshrrev_b32_e32 v4, 9, v4
v_mul_hi_u32 v2, v2, s0
v_add_nc_u32_e32 v7, 0x1180, v0
v_lshlrev_b32_e32 v1, 8, v1
v_mul_hi_u32 v6, v6, s0
v_lshrrev_b32_e32 v3, 9, v3
v_mul_i32_i24_e32 v4, s7, v4
v_mul_hi_u32 v7, v7, s0
v_lshrrev_b32_e32 v5, 9, v5
v_lshrrev_b32_e32 v2, 9, v2
v_mul_i32_i24_e32 v3, s7, v3
v_add3_u32 v49, v9, v4, v1
v_lshrrev_b32_e32 v1, 9, v6
v_mul_i32_i24_e32 v4, s7, v5
v_mul_i32_i24_e32 v2, s7, v2
v_add3_u32 v50, v41, v3, 0x200
v_lshrrev_b32_e32 v3, 9, v7
v_mul_i32_i24_e32 v1, s7, v1
v_add3_u32 v51, v41, v4, 0xc00
v_add3_u32 v52, v41, v2, 0x1600
v_cmp_gt_i32_e64 s0, s6, v0
v_mul_i32_i24_e32 v2, s7, v3
v_add3_u32 v53, v41, v1, 0x2000
v_mul_u32_u24_e32 v1, 0x140, v46
v_lshl_or_b32 v40, v0, 1, s1
v_cmp_gt_i32_e32 vcc_lo, 0xe0, v0
v_add3_u32 v55, v41, v2, 0x2a00
v_lshlrev_b32_e32 v56, 3, v0
v_lshl_or_b32 v57, v1, 1, s1
v_and_b32_e32 v47, 0xfc, v54
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v24, 0
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v28, 0
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v34, 0
v_mov_b32_e32 v30, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v33, 0
v_mov_b32_e32 v29, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v35, 0
v_mov_b32_e32 v32, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v38, 0
v_mov_b32_e32 v36, 0
v_mov_b32_e32 v39, 0
v_mov_b32_e32 v37, 0
v_mov_b32_e32 v31, 0
v_mov_b32_e32 v15, 0
s_mov_b32 s6, 0
s_movk_i32 s7, 0x1000
s_movk_i32 s14, 0x2800
s_movk_i32 s15, 0x3800
s_movk_i32 s16, 0x800
s_movk_i32 s17, 0x4000
BB44_1:
s_lshl_b32 s18, s6, 5
v_add_nc_u32_e32 v58, s18, v41
v_add_nc_u32_e32 v60, s18, v42
v_add_nc_u32_e32 v62, s18, v43
v_add_nc_u32_e32 v64, s18, v44
v_add_nc_u32_e32 v70, s18, v45
v_ashrrev_i32_e32 v59, 31, v58
v_ashrrev_i32_e32 v61, 31, v60
v_ashrrev_i32_e32 v63, 31, v62
v_ashrrev_i32_e32 v65, 31, v64
v_add_nc_u32_e32 v72, s18, v48
v_lshlrev_b64 v[58:59], 1, v[58:59]
v_lshlrev_b64 v[60:61], 1, v[60:61]
v_lshlrev_b64 v[62:63], 1, v[62:63]
v_ashrrev_i32_e32 v71, 31, v70
v_add_nc_u32_e32 v74, s18, v49
v_lshlrev_b64 v[64:65], 1, v[64:65]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v58, s1, s10, v58
v_ashrrev_i32_e32 v73, 31, v72
v_add_co_ci_u32_e64 v59, s1, s11, v59, s1
v_add_nc_u32_e32 v76, s18, v50
v_lshlrev_b64 v[70:71], 1, v[70:71]
v_add_co_u32 v66, s1, s7, v58
v_ashrrev_i32_e32 v75, 31, v74
v_add_co_ci_u32_e64 v67, s1, 0, v59, s1
v_add_co_u32 v68, s1, s14, v58
global_load_ushort v84, v[58:59], off
v_add_co_ci_u32_e64 v69, s1, 0, v59, s1
v_add_co_u32 v58, s1, s15, v58
v_add_nc_u32_e32 v78, s18, v51
v_add_co_ci_u32_e64 v59, s1, 0, v59, s1
v_add_co_u32 v60, s1, s10, v60
v_lshlrev_b64 v[72:73], 1, v[72:73]
v_add_co_ci_u32_e64 v61, s1, s11, v61, s1
v_add_co_u32 v62, s1, s10, v62
v_ashrrev_i32_e32 v77, 31, v76
v_add_co_ci_u32_e64 v63, s1, s11, v63, s1
v_add_co_u32 v64, s1, s10, v64
v_add_nc_u32_e32 v80, s18, v52
v_add_co_ci_u32_e64 v65, s1, s11, v65, s1
v_add_co_u32 v70, s1, s10, v70
v_lshlrev_b64 v[74:75], 1, v[74:75]
v_ashrrev_i32_e32 v79, 31, v78
v_add_co_ci_u32_e64 v71, s1, s11, v71, s1
v_add_nc_u32_e32 v82, s18, v53
v_add_co_u32 v72, s1, s10, v72
v_lshlrev_b64 v[76:77], 1, v[76:77]
v_ashrrev_i32_e32 v81, 31, v80
v_add_co_ci_u32_e64 v73, s1, s11, v73, s1
v_add_co_u32 v74, s1, s10, v74
v_lshlrev_b64 v[78:79], 1, v[78:79]
v_ashrrev_i32_e32 v83, 31, v82
v_add_co_ci_u32_e64 v75, s1, s11, v75, s1
v_add_co_u32 v76, s1, s10, v76
v_lshlrev_b64 v[80:81], 1, v[80:81]
v_add_co_ci_u32_e64 v77, s1, s11, v77, s1
v_add_co_u32 v78, s1, s10, v78
v_lshlrev_b64 v[82:83], 1, v[82:83]
v_add_co_ci_u32_e64 v79, s1, s11, v79, s1
v_add_co_u32 v80, s1, s10, v80
v_add_co_ci_u32_e64 v81, s1, s11, v81, s1
s_clause 0x4
global_load_ushort v85, v[72:73], off
global_load_ushort v74, v[74:75], off
global_load_ushort v75, v[76:77], off
global_load_ushort v76, v[78:79], off
global_load_ushort v77, v[80:81], off
v_add_co_u32 v72, s1, s10, v82
v_add_co_ci_u32_e64 v73, s1, s11, v83, s1
s_clause 0x7
global_load_ushort v66, v[66:67], off offset:1024
global_load_ushort v67, v[68:69], off
global_load_ushort v58, v[58:59], off offset:1024
global_load_ushort v59, v[60:61], off
global_load_ushort v60, v[62:63], off
global_load_ushort v61, v[64:65], off
global_load_ushort v62, v[70:71], off
global_load_ushort v63, v[72:73], off
s_waitcnt vmcnt(0)
s_barrier
ds_write_b16 v40, v84
ds_write_b16 v40, v85 offset:5120
ds_write_b16 v40, v74 offset:5760
ds_write_b16 v40, v75 offset:6400
ds_write_b16 v40, v76 offset:7040
ds_write_b16 v40, v77 offset:7680
ds_write_b16 v40, v66 offset:640
ds_write_b16 v40, v67 offset:1280
ds_write_b16 v40, v58 offset:1920
ds_write_b16 v40, v59 offset:2560
ds_write_b16 v40, v60 offset:3200
ds_write_b16 v40, v61 offset:3840
ds_write_b16 v40, v62 offset:4480
ds_write_b16 v40, v63 offset:8320
s_and_saveexec_b32 s19, vcc_lo
s_cbranch_execz BB44_3
v_add_nc_u32_e32 v58, s18, v55
v_ashrrev_i32_e32 v59, 31, v58
v_lshlrev_b64 v[58:59], 1, v[58:59]
v_add_co_u32 v58, s1, s10, v58
v_add_co_ci_u32_e64 v59, s1, s11, v59, s1
global_load_ushort v58, v[58:59], off
s_waitcnt vmcnt(0)
ds_write_b16 v40, v58 offset:8960
BB44_3:
s_or_b32 exec_lo, exec_lo, s19
v_lshl_or_b32 v58, s6, 14, v54
v_ashrrev_i32_e32 v59, 31, v58
v_lshlrev_b64 v[58:59], 1, v[58:59]
v_add_co_u32 v58, s1, s12, v58
v_add_co_ci_u32_e64 v59, s1, s13, v59, s1
v_add_co_u32 v60, s1, s16, v58
v_add_co_ci_u32_e64 v61, s1, 0, v59, s1
v_add_co_u32 v62, s1, s7, v58
v_add_co_ci_u32_e64 v63, s1, 0, v59, s1
v_add_co_u32 v64, s1, 0x1800, v58
v_add_co_ci_u32_e64 v65, s1, 0, v59, s1
v_add_co_u32 v74, s1, s14, v58
s_clause 0x7
global_load_ushort v66, v[58:59], off
global_load_ushort v67, v[58:59], off offset:4
global_load_ushort v68, v[60:61], off offset:512
global_load_ushort v69, v[60:61], off offset:516
global_load_ushort v70, v[62:63], off offset:1024
global_load_ushort v71, v[62:63], off offset:1028
global_load_ushort v72, v[64:65], off offset:1536
global_load_ushort v73, v[64:65], off offset:1540
v_add_co_ci_u32_e64 v75, s1, 0, v59, s1
v_add_co_u32 v76, s1, 0x3000, v58
v_add_co_ci_u32_e64 v77, s1, 0, v59, s1
v_add_co_u32 v78, s1, s15, v58
v_add_co_ci_u32_e64 v79, s1, 0, v59, s1
v_add_co_u32 v80, s1, s17, v58
v_add_co_ci_u32_e64 v81, s1, 0, v59, s1
s_clause 0x7
global_load_ushort v82, v[74:75], off
global_load_ushort v83, v[74:75], off offset:4
global_load_ushort v84, v[76:77], off offset:512
global_load_ushort v85, v[76:77], off offset:516
global_load_ushort v86, v[78:79], off offset:1024
global_load_ushort v87, v[78:79], off offset:1028
global_load_ushort v88, v[80:81], off offset:1536
global_load_ushort v89, v[80:81], off offset:1540
v_add_co_u32 v90, s1, 0x5000, v58
v_add_co_ci_u32_e64 v91, s1, 0, v59, s1
v_add_co_u32 v92, s1, 0x5800, v58
v_add_co_ci_u32_e64 v93, s1, 0, v59, s1
v_add_co_u32 v94, s1, 0x6000, v58
v_add_co_ci_u32_e64 v95, s1, 0, v59, s1
v_add_co_u32 v96, s1, 0x6800, v58
v_add_co_ci_u32_e64 v97, s1, 0, v59, s1
s_clause 0x7
global_load_ushort v98, v[90:91], off
global_load_ushort v99, v[90:91], off offset:4
global_load_ushort v100, v[92:93], off offset:512
global_load_ushort v101, v[92:93], off offset:516
global_load_ushort v102, v[94:95], off offset:1024
global_load_ushort v103, v[94:95], off offset:1028
global_load_ushort v104, v[96:97], off offset:1536
global_load_ushort v105, v[96:97], off offset:1540
s_waitcnt vmcnt(23)
global_load_short_d16_hi v66, v[58:59], off offset:2
s_waitcnt vmcnt(23)
global_load_short_d16_hi v67, v[58:59], off offset:6
s_waitcnt vmcnt(23)
global_load_short_d16_hi v68, v[60:61], off offset:514
s_waitcnt vmcnt(23)
global_load_short_d16_hi v69, v[60:61], off offset:518
s_waitcnt vmcnt(23)
global_load_short_d16_hi v70, v[62:63], off offset:1026
s_waitcnt vmcnt(23)
global_load_short_d16_hi v71, v[62:63], off offset:1030
s_waitcnt vmcnt(23)
global_load_short_d16_hi v72, v[64:65], off offset:1538
s_waitcnt vmcnt(23)
global_load_short_d16_hi v73, v[64:65], off offset:1542
s_waitcnt vmcnt(23)
global_load_short_d16_hi v82, v[74:75], off offset:2
s_waitcnt vmcnt(23)
global_load_short_d16_hi v83, v[74:75], off offset:6
s_waitcnt vmcnt(23)
global_load_short_d16_hi v84, v[76:77], off offset:514
s_waitcnt vmcnt(23)
global_load_short_d16_hi v85, v[76:77], off offset:518
s_waitcnt vmcnt(23)
global_load_short_d16_hi v86, v[78:79], off offset:1026
s_waitcnt vmcnt(23)
global_load_short_d16_hi v87, v[78:79], off offset:1030
s_waitcnt vmcnt(23)
global_load_short_d16_hi v88, v[80:81], off offset:1538
s_waitcnt vmcnt(23)
global_load_short_d16_hi v89, v[80:81], off offset:1542
s_waitcnt vmcnt(23)
global_load_short_d16_hi v98, v[90:91], off offset:2
s_waitcnt vmcnt(23)
global_load_short_d16_hi v99, v[90:91], off offset:6
s_waitcnt vmcnt(23)
global_load_short_d16_hi v100, v[92:93], off offset:514
s_waitcnt vmcnt(23)
global_load_short_d16_hi v101, v[92:93], off offset:518
s_waitcnt vmcnt(23)
global_load_short_d16_hi v102, v[94:95], off offset:1026
s_waitcnt vmcnt(23)
global_load_short_d16_hi v103, v[94:95], off offset:1030
s_waitcnt vmcnt(23)
global_load_short_d16_hi v104, v[96:97], off offset:1538
s_waitcnt vmcnt(23)
global_load_short_d16_hi v105, v[96:97], off offset:1542
s_waitcnt vmcnt(20)
ds_write2st64_b64 v56, v[66:67], v[68:69] offset1:5
s_waitcnt vmcnt(16)
ds_write2st64_b64 v56, v[70:71], v[72:73] offset0:10 offset1:15
s_waitcnt vmcnt(12)
ds_write2st64_b64 v56, v[82:83], v[84:85] offset0:20 offset1:25
s_waitcnt vmcnt(8)
ds_write2st64_b64 v56, v[86:87], v[88:89] offset0:30 offset1:35
s_waitcnt vmcnt(4)
ds_write2st64_b64 v56, v[98:99], v[100:101] offset0:40 offset1:45
s_waitcnt vmcnt(0)
ds_write2st64_b64 v56, v[102:103], v[104:105] offset0:50 offset1:55
s_and_saveexec_b32 s18, s0
s_cbranch_execz BB44_5
v_add_co_u32 v58, s1, 0x7800, v58
v_add_co_ci_u32_e64 v59, s1, 0, v59, s1
s_clause 0x1
global_load_ushort v60, v[58:59], off
global_load_ushort v61, v[58:59], off offset:4
s_waitcnt vmcnt(1)
global_load_short_d16_hi v60, v[58:59], off offset:2
s_waitcnt vmcnt(1)
global_load_short_d16_hi v61, v[58:59], off offset:6
s_waitcnt vmcnt(0)
ds_write_b64 v56, v[60:61] offset:30720
BB44_5:
s_or_b32 exec_lo, exec_lo, s18
v_mov_b32_e32 v58, v57
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_barrier
BB44_6:
v_or_b32_e32 v67, s1, v47
v_add_nc_u32_e32 v71, 0x1800, v58
ds_read2_b64 v[59:62], v58 offset1:16
ds_read2_b64 v[63:66], v58 offset0:32 offset1:48
ds_read_b64 v[87:88], v58 offset:512
ds_read_b64 v[89:90], v58 offset:6784
v_mov_b32_e32 v95, 0xffff
v_lshlrev_b32_e32 v93, 1, v67
v_add_nc_u32_e32 v58, 8, v58
s_add_i32 s1, s1, s16
ds_read2_b64 v[67:70], v71 offset0:16 offset1:32
ds_read2_b64 v[71:74], v71 offset0:48 offset1:64
ds_read2_b32 v[91:92], v93 offset1:1
ds_read2st64_b64 v[75:78], v93 offset0:1 offset1:2
ds_read2st64_b64 v[79:82], v93 offset0:3 offset1:4
ds_read2st64_b64 v[83:86], v93 offset0:5 offset1:6
ds_read_b64 v[93:94], v93 offset:3584
s_cmp_lg_u32 s1, s17
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v39, v59, v91, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v61, v91, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v63, v91, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v65, v91, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v87, v91, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v67, v91, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v69, v91, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v71, v91, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v73, v91, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v89, v91, v20 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_and_b32_sdwa v91, v95, v75 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_fma_f16 v31, v59, v76, v31 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v18, v61, v75, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v61, v76, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v63, v75, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v63, v76, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v65, v75, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v65, v76, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v87, v75, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v87, v76, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v67, v75, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v67, v76, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v69, v75, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v69, v76, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v71, v75, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v71, v76, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v73, v75, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v89, v75, v0 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v73, v76, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v89, v76, v1 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_and_b32_sdwa v76, v95, v79 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v75, v75, 16, v91
v_pk_fma_f16 v37, v59, v92, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v61, v92, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v63, v92, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v65, v92, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v87, v92, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v67, v92, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v69, v92, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v71, v92, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v73, v92, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v89, v92, v17 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_and_b32_sdwa v92, v95, v83 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v76, v79, 16, v76
v_pk_fma_f16 v15, v59, v75, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v39, v59, v77, v39 op_sel:[1,0,0]
v_pk_fma_f16 v37, v59, v78, v37 op_sel:[1,0,0]
v_pk_fma_f16 v38, v61, v77, v38 op_sel:[1,0,0]
v_pk_fma_f16 v36, v61, v78, v36 op_sel:[1,0,0]
v_pk_fma_f16 v35, v63, v77, v35 op_sel:[1,0,0]
v_pk_fma_f16 v32, v63, v78, v32 op_sel:[1,0,0]
v_pk_fma_f16 v33, v65, v77, v33 op_sel:[1,0,0]
v_pk_fma_f16 v29, v65, v78, v29 op_sel:[1,0,0]
v_pk_fma_f16 v34, v87, v77, v34 op_sel:[1,0,0]
v_pk_fma_f16 v30, v87, v78, v30 op_sel:[1,0,0]
v_pk_fma_f16 v28, v67, v77, v28 op_sel:[1,0,0]
v_pk_fma_f16 v25, v67, v78, v25 op_sel:[1,0,0]
v_pk_fma_f16 v26, v69, v77, v26 op_sel:[1,0,0]
v_pk_fma_f16 v22, v69, v78, v22 op_sel:[1,0,0]
v_pk_fma_f16 v27, v71, v77, v27 op_sel:[1,0,0]
v_pk_fma_f16 v23, v71, v78, v23 op_sel:[1,0,0]
v_pk_fma_f16 v24, v73, v77, v24 op_sel:[1,0,0]
v_pk_fma_f16 v21, v73, v78, v21 op_sel:[1,0,0]
v_pk_fma_f16 v20, v89, v77, v20 op_sel:[1,0,0]
v_pk_fma_f16 v17, v89, v78, v17 op_sel:[1,0,0]
v_pk_fma_f16 v31, v59, v80, v31 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v18, v61, v79, v18 op_sel:[1,0,0]
v_pk_fma_f16 v19, v61, v80, v19 op_sel:[1,0,0]
v_pk_fma_f16 v14, v63, v79, v14 op_sel:[1,0,0]
v_pk_fma_f16 v16, v63, v80, v16 op_sel:[1,0,0]
v_pk_fma_f16 v11, v65, v79, v11 op_sel:[1,0,0]
v_pk_fma_f16 v13, v65, v80, v13 op_sel:[1,0,0]
v_pk_fma_f16 v10, v87, v79, v10 op_sel:[1,0,0]
v_pk_fma_f16 v12, v87, v80, v12 op_sel:[1,0,0]
v_pk_fma_f16 v8, v67, v79, v8 op_sel:[1,0,0]
v_pk_fma_f16 v9, v67, v80, v9 op_sel:[1,0,0]
v_pk_fma_f16 v4, v69, v79, v4 op_sel:[1,0,0]
v_pk_fma_f16 v5, v69, v80, v5 op_sel:[1,0,0]
v_pk_fma_f16 v6, v71, v79, v6 op_sel:[1,0,0]
v_pk_fma_f16 v7, v71, v80, v7 op_sel:[1,0,0]
v_pk_fma_f16 v2, v73, v79, v2 op_sel:[1,0,0]
v_pk_fma_f16 v3, v73, v80, v3 op_sel:[1,0,0]
v_pk_fma_f16 v0, v89, v79, v0 op_sel:[1,0,0]
v_pk_fma_f16 v1, v89, v80, v1 op_sel:[1,0,0]
s_waitcnt lgkmcnt(0)
v_and_b32_sdwa v95, v95, v93 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v61, v83, 16, v92
v_pk_fma_f16 v15, v59, v76, v15 op_sel:[1,0,0]
v_pk_fma_f16 v39, v60, v81, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v60, v82, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v62, v81, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v62, v82, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v64, v81, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v64, v82, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v66, v81, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v66, v82, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v88, v81, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v88, v82, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v68, v81, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v68, v82, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v70, v81, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v70, v82, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v72, v81, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v72, v82, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v74, v81, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v74, v82, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v90, v81, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v90, v82, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v64, v83, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v64, v84, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v66, v83, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v66, v84, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v68, v83, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v68, v84, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v70, v83, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v70, v84, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v88, v83, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v88, v84, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v60, v84, v31 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v18, v62, v83, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v62, v84, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v72, v83, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v72, v84, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v74, v83, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v74, v84, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v90, v83, v0 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v90, v84, v1 op_sel_hi:[0,1,1]
v_lshl_or_b32 v63, v93, 16, v95
v_pk_fma_f16 v15, v60, v61, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v64, v85, v35 op_sel:[1,0,0]
v_pk_fma_f16 v14, v64, v93, v14 op_sel:[1,0,0]
v_pk_fma_f16 v32, v64, v86, v32 op_sel:[1,0,0]
v_pk_fma_f16 v16, v64, v94, v16 op_sel:[1,0,0]
v_pk_fma_f16 v33, v66, v85, v33 op_sel:[1,0,0]
v_pk_fma_f16 v11, v66, v93, v11 op_sel:[1,0,0]
v_pk_fma_f16 v29, v66, v86, v29 op_sel:[1,0,0]
v_pk_fma_f16 v13, v66, v94, v13 op_sel:[1,0,0]
v_pk_fma_f16 v28, v68, v85, v28 op_sel:[1,0,0]
v_pk_fma_f16 v8, v68, v93, v8 op_sel:[1,0,0]
v_pk_fma_f16 v25, v68, v86, v25 op_sel:[1,0,0]
v_pk_fma_f16 v9, v68, v94, v9 op_sel:[1,0,0]
v_pk_fma_f16 v26, v70, v85, v26 op_sel:[1,0,0]
v_pk_fma_f16 v4, v70, v93, v4 op_sel:[1,0,0]
v_pk_fma_f16 v22, v70, v86, v22 op_sel:[1,0,0]
v_pk_fma_f16 v5, v70, v94, v5 op_sel:[1,0,0]
v_pk_fma_f16 v34, v88, v85, v34 op_sel:[1,0,0]
v_pk_fma_f16 v10, v88, v93, v10 op_sel:[1,0,0]
v_pk_fma_f16 v30, v88, v86, v30 op_sel:[1,0,0]
v_pk_fma_f16 v12, v88, v94, v12 op_sel:[1,0,0]
v_pk_fma_f16 v39, v60, v85, v39 op_sel:[1,0,0]
v_pk_fma_f16 v37, v60, v86, v37 op_sel:[1,0,0]
v_pk_fma_f16 v31, v60, v94, v31 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v38, v62, v85, v38 op_sel:[1,0,0]
v_pk_fma_f16 v18, v62, v93, v18 op_sel:[1,0,0]
v_pk_fma_f16 v36, v62, v86, v36 op_sel:[1,0,0]
v_pk_fma_f16 v19, v62, v94, v19 op_sel:[1,0,0]
v_pk_fma_f16 v27, v72, v85, v27 op_sel:[1,0,0]
v_pk_fma_f16 v6, v72, v93, v6 op_sel:[1,0,0]
v_pk_fma_f16 v23, v72, v86, v23 op_sel:[1,0,0]
v_pk_fma_f16 v7, v72, v94, v7 op_sel:[1,0,0]
v_pk_fma_f16 v24, v74, v85, v24 op_sel:[1,0,0]
v_pk_fma_f16 v2, v74, v93, v2 op_sel:[1,0,0]
v_pk_fma_f16 v21, v74, v86, v21 op_sel:[1,0,0]
v_pk_fma_f16 v3, v74, v94, v3 op_sel:[1,0,0]
v_pk_fma_f16 v20, v90, v85, v20 op_sel:[1,0,0]
v_pk_fma_f16 v0, v90, v93, v0 op_sel:[1,0,0]
v_pk_fma_f16 v17, v90, v86, v17 op_sel:[1,0,0]
v_pk_fma_f16 v1, v90, v94, v1 op_sel:[1,0,0]
v_pk_fma_f16 v15, v60, v63, v15 op_sel:[1,0,0]
s_cbranch_scc1 BB44_6
s_add_i32 s6, s6, 1
s_cmp_eq_u32 s6, 8
s_cbranch_scc0 BB44_1
v_lshlrev_b32_e32 v106, 1, v47
v_mul_u32_u24_e32 v40, 0xa00, v46
s_mul_i32 s5, s5, 0x19000
global_load_dword v107, v106, s[2:3]
v_add3_u32 v40, s4, s5, v40
s_clause 0x1
global_load_ushort v108, v106, s[2:3] offset:516
global_load_ushort v109, v106, s[2:3] offset:518
v_or_b32_e32 v40, v40, v47
v_add_nc_u32_e32 v42, 0x400, v40
v_ashrrev_i32_e32 v41, 31, v40
v_add_nc_u32_e32 v44, 0x402, v40
v_add_nc_u32_e32 v50, 0x600, v40
v_add_nc_u32_e32 v52, 0x602, v40
v_ashrrev_i32_e32 v43, 31, v42
v_lshlrev_b64 v[100:101], 1, v[40:41]
v_ashrrev_i32_e32 v45, 31, v44
v_ashrrev_i32_e32 v51, 31, v50
v_add_nc_u32_e32 v46, 0x500, v40
v_lshlrev_b64 v[41:42], 1, v[42:43]
v_add_nc_u32_e32 v48, 0x502, v40
v_add_nc_u32_e32 v54, 0x800, v40
v_add_co_u32 v100, vcc_lo, s8, v100
v_lshlrev_b64 v[43:44], 1, v[44:45]
v_ashrrev_i32_e32 v53, 31, v52
v_add_co_ci_u32_e32 v101, vcc_lo, s9, v101, vcc_lo
v_add_nc_u32_e32 v56, 0x802, v40
v_add_co_u32 v41, vcc_lo, s8, v41
v_lshlrev_b64 v[50:51], 1, v[50:51]
v_ashrrev_i32_e32 v55, 31, v54
v_ashrrev_i32_e32 v47, 31, v46
v_ashrrev_i32_e32 v49, 31, v48
v_add_co_ci_u32_e32 v42, vcc_lo, s9, v42, vcc_lo
v_add_nc_u32_e32 v62, 0xc800, v40
v_add_co_u32 v43, vcc_lo, s8, v43
v_lshlrev_b64 v[52:53], 1, v[52:53]
v_ashrrev_i32_e32 v57, 31, v56
v_add_nc_u32_e32 v64, 0xc802, v40
v_add_co_ci_u32_e32 v44, vcc_lo, s9, v44, vcc_lo
v_lshlrev_b64 v[45:46], 1, v[46:47]
v_lshlrev_b64 v[47:48], 1, v[48:49]
v_add_co_u32 v49, vcc_lo, s8, v50
v_lshlrev_b64 v[54:55], 1, v[54:55]
v_ashrrev_i32_e32 v63, 31, v62
v_add_co_ci_u32_e32 v50, vcc_lo, s9, v51, vcc_lo
v_add_nc_u32_e32 v66, 0xca00, v40
v_add_co_u32 v51, vcc_lo, s8, v52
v_lshlrev_b64 v[56:57], 1, v[56:57]
v_ashrrev_i32_e32 v65, 31, v64
v_add_co_ci_u32_e32 v52, vcc_lo, s9, v53, vcc_lo
v_add_nc_u32_e32 v68, 0xca02, v40
v_add_co_u32 v53, vcc_lo, s8, v54
v_lshlrev_b64 v[62:63], 1, v[62:63]
v_ashrrev_i32_e32 v67, 31, v66
v_add_co_ci_u32_e32 v54, vcc_lo, s9, v55, vcc_lo
v_add_nc_u32_e32 v72, 0xcc00, v40
v_add_co_u32 v55, vcc_lo, s8, v56
v_lshlrev_b64 v[64:65], 1, v[64:65]
v_ashrrev_i32_e32 v69, 31, v68
v_add_co_ci_u32_e32 v56, vcc_lo, s9, v57, vcc_lo
v_add_nc_u32_e32 v74, 0xcc02, v40
v_add_co_u32 v62, vcc_lo, s8, v62
v_lshlrev_b64 v[66:67], 1, v[66:67]
v_ashrrev_i32_e32 v73, 31, v72
v_add_co_ci_u32_e32 v63, vcc_lo, s9, v63, vcc_lo
v_add_nc_u32_e32 v76, 0xce00, v40
v_add_co_u32 v64, vcc_lo, s8, v64
v_lshlrev_b64 v[68:69], 1, v[68:69]
v_ashrrev_i32_e32 v75, 31, v74
v_add_co_ci_u32_e32 v65, vcc_lo, s9, v65, vcc_lo
v_add_nc_u32_e32 v78, 0xce02, v40
v_add_co_u32 v66, vcc_lo, s8, v66
v_lshlrev_b64 v[72:73], 1, v[72:73]
v_ashrrev_i32_e32 v77, 31, v76
v_add_co_ci_u32_e32 v67, vcc_lo, s9, v67, vcc_lo
v_add_co_u32 v68, vcc_lo, s8, v68
v_lshlrev_b64 v[74:75], 1, v[74:75]
v_ashrrev_i32_e32 v79, 31, v78
v_add_co_ci_u32_e32 v69, vcc_lo, s9, v69, vcc_lo
v_add_co_u32 v72, vcc_lo, s8, v72
v_lshlrev_b64 v[76:77], 1, v[76:77]
v_add_co_ci_u32_e32 v73, vcc_lo, s9, v73, vcc_lo
v_add_nc_u32_e32 v58, 0x700, v40
v_add_co_u32 v74, vcc_lo, s8, v74
v_lshlrev_b64 v[78:79], 1, v[78:79]
v_add_co_ci_u32_e32 v75, vcc_lo, s9, v75, vcc_lo
v_add_nc_u32_e32 v60, 0x702, v40
v_add_co_u32 v76, vcc_lo, s8, v76
v_ashrrev_i32_e32 v59, 31, v58
v_add_co_ci_u32_e32 v77, vcc_lo, s9, v77, vcc_lo
v_add_co_u32 v78, vcc_lo, s8, v78
v_ashrrev_i32_e32 v61, 31, v60
v_add_co_ci_u32_e32 v79, vcc_lo, s9, v79, vcc_lo
v_add_co_u32 v45, vcc_lo, s8, v45
v_lshlrev_b64 v[58:59], 1, v[58:59]
v_add_co_ci_u32_e32 v46, vcc_lo, s9, v46, vcc_lo
v_add_co_u32 v47, vcc_lo, s8, v47
v_lshlrev_b64 v[60:61], 1, v[60:61]
v_add_co_ci_u32_e32 v48, vcc_lo, s9, v48, vcc_lo
v_add_nc_u32_e32 v70, 0x900, v40
v_add_co_u32 v57, vcc_lo, s8, v58
v_add_nc_u32_e32 v80, 0x902, v40
v_add_co_ci_u32_e32 v58, vcc_lo, s9, v59, vcc_lo
v_add_co_u32 v59, vcc_lo, s8, v60
v_ashrrev_i32_e32 v71, 31, v70
v_add_co_ci_u32_e32 v60, vcc_lo, s9, v61, vcc_lo
s_clause 0x1
global_load_dword v61, v106, s[2:3] offset:4
global_load_ushort v110, v106, s[2:3] offset:512
v_add_nc_u32_e32 v82, 0xc900, v40
v_ashrrev_i32_e32 v81, 31, v80
v_add_nc_u32_e32 v84, 0xc902, v40
v_lshlrev_b64 v[70:71], 1, v[70:71]
v_add_nc_u32_e32 v86, 0xcb00, v40
v_ashrrev_i32_e32 v83, 31, v82
v_lshlrev_b64 v[80:81], 1, v[80:81]
v_ashrrev_i32_e32 v85, 31, v84
v_add_nc_u32_e32 v88, 0xcb02, v40
v_add_co_u32 v70, vcc_lo, s8, v70
v_lshlrev_b64 v[82:83], 1, v[82:83]
v_ashrrev_i32_e32 v87, 31, v86
v_add_co_ci_u32_e32 v71, vcc_lo, s9, v71, vcc_lo
v_add_nc_u32_e32 v90, 0xcd00, v40
v_add_co_u32 v80, vcc_lo, s8, v80
v_lshlrev_b64 v[84:85], 1, v[84:85]
v_ashrrev_i32_e32 v89, 31, v88
v_add_co_ci_u32_e32 v81, vcc_lo, s9, v81, vcc_lo
v_add_nc_u32_e32 v92, 0xcd02, v40
v_add_co_u32 v82, vcc_lo, s8, v82
v_lshlrev_b64 v[86:87], 1, v[86:87]
v_ashrrev_i32_e32 v91, 31, v90
v_add_co_ci_u32_e32 v83, vcc_lo, s9, v83, vcc_lo
v_add_nc_u32_e32 v94, 0xcf00, v40
v_add_co_u32 v84, vcc_lo, s8, v84
v_lshlrev_b64 v[88:89], 1, v[88:89]
v_ashrrev_i32_e32 v93, 31, v92
v_add_co_ci_u32_e32 v85, vcc_lo, s9, v85, vcc_lo
v_add_nc_u32_e32 v96, 0xcf02, v40
v_add_co_u32 v86, vcc_lo, s8, v86
v_lshlrev_b64 v[90:91], 1, v[90:91]
v_ashrrev_i32_e32 v95, 31, v94
v_add_co_ci_u32_e32 v87, vcc_lo, s9, v87, vcc_lo
v_add_nc_u32_e32 v98, 0xd000, v40
v_add_co_u32 v88, vcc_lo, s8, v88
v_lshlrev_b64 v[92:93], 1, v[92:93]
v_ashrrev_i32_e32 v97, 31, v96
v_add_co_ci_u32_e32 v89, vcc_lo, s9, v89, vcc_lo
v_add_co_u32 v90, vcc_lo, s8, v90
v_lshlrev_b64 v[94:95], 1, v[94:95]
v_ashrrev_i32_e32 v99, 31, v98
v_add_co_ci_u32_e32 v91, vcc_lo, s9, v91, vcc_lo
v_add_nc_u32_e32 v102, 0xd002, v40
v_add_co_u32 v92, vcc_lo, s8, v92
v_lshlrev_b64 v[96:97], 1, v[96:97]
v_add_co_ci_u32_e32 v93, vcc_lo, s9, v93, vcc_lo
v_add_co_u32 v94, vcc_lo, s8, v94
v_lshlrev_b64 v[98:99], 1, v[98:99]
v_ashrrev_i32_e32 v103, 31, v102
v_add_co_ci_u32_e32 v95, vcc_lo, s9, v95, vcc_lo
v_add_nc_u32_e32 v104, 0xd102, v40
v_add_co_u32 v96, vcc_lo, s8, v96
v_add_co_ci_u32_e32 v97, vcc_lo, s9, v97, vcc_lo
v_add_co_u32 v98, vcc_lo, s8, v98
v_lshlrev_b64 v[102:103], 1, v[102:103]
v_add_co_ci_u32_e32 v99, vcc_lo, s9, v99, vcc_lo
v_ashrrev_i32_e32 v105, 31, v104
v_lshlrev_b64 v[104:105], 1, v[104:105]
s_waitcnt vmcnt(4)
v_pk_add_f16 v35, v107, v35
v_pk_add_f16 v33, v107, v33
v_pk_add_f16 v34, v107, v34
v_pk_add_f16 v28, v107, v28
v_pk_add_f16 v26, v107, v26
global_store_dword v[41:42], v35, off
v_pk_add_f16 v35, v107, v39
global_load_ushort v39, v106, s[2:3] offset:514
v_add_nc_u32_e32 v41, 0xd100, v40
v_mov_b32_e32 v40, 0xffff
v_pk_add_f16 v27, v107, v27
v_pk_add_f16 v24, v107, v24
v_pk_add_f16 v38, v107, v38
v_ashrrev_i32_e32 v42, 31, v41
v_pk_add_f16 v20, v107, v20
v_lshlrev_b64 v[41:42], 1, v[41:42]
v_add_co_u32 v41, vcc_lo, s8, v41
v_add_co_ci_u32_e32 v42, vcc_lo, s9, v42, vcc_lo
v_add_co_u32 v102, vcc_lo, s8, v102
v_add_co_ci_u32_e32 v103, vcc_lo, s9, v103, vcc_lo
v_add_co_u32 v104, vcc_lo, s8, v104
v_add_co_ci_u32_e32 v105, vcc_lo, s9, v105, vcc_lo
s_waitcnt vmcnt(2)
v_pk_add_f16 v32, v61, v32
v_pk_add_f16 v29, v61, v29
v_pk_add_f16 v30, v61, v30
v_pk_add_f16 v25, v61, v25
v_pk_add_f16 v22, v61, v22
global_store_dword v[43:44], v32, off
s_waitcnt vmcnt(1)
v_and_b32_e32 v43, v40, v110
v_and_b32_e32 v40, v40, v108
v_add_f16_sdwa v32, v110, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_add_f16_sdwa v44, v108, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_add_f16 v23, v61, v23
v_pk_add_f16 v21, v61, v21
v_pk_add_f16 v37, v61, v37
v_pk_add_f16 v36, v61, v36
v_add_f16_e32 v31, v109, v31
v_pk_add_f16 v17, v61, v17
s_waitcnt vmcnt(0)
v_add_f16_e32 v15, v39, v15
global_store_dword v[49:50], v33, off
global_store_dword v[51:52], v29, off
global_store_dword v[53:54], v34, off
global_store_dword v[55:56], v30, off
global_store_dword v[62:63], v28, off
global_store_dword v[64:65], v25, off
global_store_dword v[66:67], v26, off
global_store_dword v[68:69], v22, off
global_store_dword v[72:73], v27, off
global_store_dword v[74:75], v23, off
global_store_dword v[76:77], v24, off
global_store_dword v[78:79], v21, off
global_store_short v[100:101], v32, off offset:512
global_store_dword v[100:101], v35, off
global_store_short v[100:101], v15, off offset:514
global_store_short v[100:101], v44, off offset:516
global_store_dword v[100:101], v37, off offset:4
global_store_short v[100:101], v31, off offset:518
global_store_dword v[100:101], v38, off offset:1024
v_lshl_or_b32 v15, v39, 16, v43
v_lshl_or_b32 v21, v109, 16, v40
global_store_dword v[100:101], v36, off offset:1028
global_store_dword v[98:99], v20, off
global_store_dword v[102:103], v17, off
v_pk_add_f16 v17, v15, v18
v_pk_add_f16 v18, v21, v19
v_pk_add_f16 v14, v15, v14
v_pk_add_f16 v16, v21, v16
v_pk_add_f16 v11, v15, v11
v_pk_add_f16 v13, v21, v13
v_pk_add_f16 v10, v15, v10
v_pk_add_f16 v12, v21, v12
v_pk_add_f16 v8, v15, v8
v_pk_add_f16 v9, v21, v9
v_pk_add_f16 v4, v15, v4
v_pk_add_f16 v5, v21, v5
v_pk_add_f16 v6, v15, v6
v_pk_add_f16 v7, v21, v7
v_pk_add_f16 v2, v15, v2
v_pk_add_f16 v3, v21, v3
v_pk_add_f16 v0, v15, v0
v_pk_add_f16 v1, v21, v1
global_store_dword v[100:101], v17, off offset:1536
global_store_dword v[100:101], v18, off offset:1540
global_store_dword v[45:46], v14, off
global_store_dword v[47:48], v16, off
global_store_dword v[57:58], v11, off
global_store_dword v[59:60], v13, off
global_store_dword v[70:71], v10, off
global_store_dword v[80:81], v12, off
global_store_dword v[82:83], v8, off
global_store_dword v[84:85], v9, off
global_store_dword v[86:87], v4, off
global_store_dword v[88:89], v5, off
global_store_dword v[90:91], v6, off
global_store_dword v[92:93], v7, off
global_store_dword v[94:95], v2, off
global_store_dword v[96:97], v3, off
global_store_dword v[41:42], v0, off
global_store_dword v[104:105], v1, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_1_kernel0
.amdhsa_group_segment_fixed_size 42176
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 111
.amdhsa_next_free_sgpr 20
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end44:
.size tvmgen_default_fused_nn_conv2d_add_1_kernel0, .Lfunc_end44-tvmgen_default_fused_nn_conv2d_add_1_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_2_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_2_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_2_kernel0:
s_clause 0x3
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[4:5], s[4:5], 0x18
v_lshlrev_b32_e32 v1, 5, v0
s_and_b32 s0, s6, 1
v_lshrrev_b32_e32 v40, 6, v0
s_mulk_i32 s0, 0x6400
s_ashr_i32 s1, s6, 1
v_and_or_b32 v2, v0, 15, s0
v_and_b32_e32 v1, 0x7e00, v1
s_mul_i32 s1, s1, 0x19000
v_lshlrev_b32_e32 v3, 1, v0
s_mov_b32 s7, 0x8000
v_cmp_gt_i32_e32 vcc_lo, 0x90, v0
v_add3_u32 v42, v2, s1, v1
v_mul_u32_u24_e32 v1, 0xa0, v40
v_or_b32_e32 v43, s7, v3
v_and_b32_e32 v41, 0x7e, v3
v_lshlrev_b32_e32 v44, 2, v0
v_lshlrev_b32_e32 v45, 3, v0
v_lshl_or_b32 v46, v1, 1, s7
v_cmp_gt_i32_e64 s0, 0x100, v0
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v24, 0
v_mov_b32_e32 v29, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v30, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v28, 0
v_mov_b32_e32 v34, 0
v_mov_b32_e32 v38, 0
v_mov_b32_e32 v31, 0
v_mov_b32_e32 v32, 0
v_mov_b32_e32 v33, 0
v_mov_b32_e32 v35, 0
v_mov_b32_e32 v36, 0
v_mov_b32_e32 v37, 0
v_mov_b32_e32 v39, 0
s_mov_b32 s7, 0
s_movk_i32 s12, 0x5000
s_movk_i32 s13, 0x800
s_movk_i32 s14, 0x4000
BB45_1:
v_lshl_add_u32 v47, s7, 4, v42
v_ashrrev_i32_e32 v48, 31, v47
v_lshlrev_b64 v[47:48], 1, v[47:48]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v47, s1, s8, v47
v_add_co_ci_u32_e64 v48, s1, s9, v48, s1
v_add_co_u32 v49, s1, s12, v47
v_add_co_ci_u32_e64 v50, s1, 0, v48, s1
s_clause 0x1
global_load_ushort v51, v[47:48], off
global_load_ushort v49, v[49:50], off
s_waitcnt vmcnt(0)
s_barrier
ds_write_b16 v43, v51
ds_write_b16 v43, v49 offset:640
s_and_saveexec_b32 s15, vcc_lo
s_cbranch_execz BB45_3
v_add_co_u32 v47, s1, 0xa000, v47
v_add_co_ci_u32_e64 v48, s1, 0, v48, s1
global_load_ushort v47, v[47:48], off
s_waitcnt vmcnt(0)
ds_write_b16 v43, v47 offset:1280
BB45_3:
s_or_b32 exec_lo, exec_lo, s15
v_lshl_or_b32 v47, s7, 14, v44
v_ashrrev_i32_e32 v48, 31, v47
v_lshlrev_b64 v[47:48], 1, v[47:48]
v_add_co_u32 v47, s1, s10, v47
v_add_co_ci_u32_e64 v48, s1, s11, v48, s1
v_add_co_u32 v49, s1, s13, v47
v_add_co_ci_u32_e64 v50, s1, 0, v48, s1
v_add_co_u32 v51, s1, 0x1000, v47
v_add_co_ci_u32_e64 v52, s1, 0, v48, s1
v_add_co_u32 v53, s1, 0x1800, v47
v_add_co_ci_u32_e64 v54, s1, 0, v48, s1
v_add_co_u32 v63, s1, 0x2800, v47
s_clause 0x7
global_load_ushort v55, v[47:48], off
global_load_ushort v56, v[47:48], off offset:4
global_load_ushort v57, v[49:50], off offset:512
global_load_ushort v58, v[49:50], off offset:516
global_load_ushort v59, v[51:52], off offset:1024
global_load_ushort v60, v[51:52], off offset:1028
global_load_ushort v61, v[53:54], off offset:1536
global_load_ushort v62, v[53:54], off offset:1540
v_add_co_ci_u32_e64 v64, s1, 0, v48, s1
v_add_co_u32 v65, s1, 0x3000, v47
v_add_co_ci_u32_e64 v66, s1, 0, v48, s1
v_add_co_u32 v67, s1, 0x3800, v47
v_add_co_ci_u32_e64 v68, s1, 0, v48, s1
v_add_co_u32 v69, s1, s14, v47
v_add_co_ci_u32_e64 v70, s1, 0, v48, s1
s_clause 0x7
global_load_ushort v71, v[63:64], off
global_load_ushort v72, v[63:64], off offset:4
global_load_ushort v73, v[65:66], off offset:512
global_load_ushort v74, v[65:66], off offset:516
global_load_ushort v75, v[67:68], off offset:1024
global_load_ushort v76, v[67:68], off offset:1028
global_load_ushort v77, v[69:70], off offset:1536
global_load_ushort v78, v[69:70], off offset:1540
v_add_co_u32 v79, s1, s12, v47
v_add_co_ci_u32_e64 v80, s1, 0, v48, s1
v_add_co_u32 v81, s1, 0x5800, v47
v_add_co_ci_u32_e64 v82, s1, 0, v48, s1
v_add_co_u32 v83, s1, 0x6000, v47
v_add_co_ci_u32_e64 v84, s1, 0, v48, s1
v_add_co_u32 v85, s1, 0x6800, v47
v_add_co_ci_u32_e64 v86, s1, 0, v48, s1
s_clause 0x7
global_load_ushort v87, v[79:80], off
global_load_ushort v88, v[79:80], off offset:4
global_load_ushort v89, v[81:82], off offset:512
global_load_ushort v90, v[81:82], off offset:516
global_load_ushort v91, v[83:84], off offset:1024
global_load_ushort v92, v[83:84], off offset:1028
global_load_ushort v93, v[85:86], off offset:1536
global_load_ushort v94, v[85:86], off offset:1540
s_waitcnt vmcnt(23)
global_load_short_d16_hi v55, v[47:48], off offset:2
s_waitcnt vmcnt(23)
global_load_short_d16_hi v56, v[47:48], off offset:6
s_waitcnt vmcnt(23)
global_load_short_d16_hi v57, v[49:50], off offset:514
s_waitcnt vmcnt(23)
global_load_short_d16_hi v58, v[49:50], off offset:518
s_waitcnt vmcnt(23)
global_load_short_d16_hi v59, v[51:52], off offset:1026
s_waitcnt vmcnt(23)
global_load_short_d16_hi v60, v[51:52], off offset:1030
s_waitcnt vmcnt(23)
global_load_short_d16_hi v61, v[53:54], off offset:1538
s_waitcnt vmcnt(23)
global_load_short_d16_hi v62, v[53:54], off offset:1542
s_waitcnt vmcnt(23)
global_load_short_d16_hi v71, v[63:64], off offset:2
s_waitcnt vmcnt(23)
global_load_short_d16_hi v72, v[63:64], off offset:6
s_waitcnt vmcnt(23)
global_load_short_d16_hi v73, v[65:66], off offset:514
s_waitcnt vmcnt(23)
global_load_short_d16_hi v74, v[65:66], off offset:518
s_waitcnt vmcnt(23)
global_load_short_d16_hi v75, v[67:68], off offset:1026
s_waitcnt vmcnt(23)
global_load_short_d16_hi v76, v[67:68], off offset:1030
s_waitcnt vmcnt(23)
global_load_short_d16_hi v77, v[69:70], off offset:1538
s_waitcnt vmcnt(23)
global_load_short_d16_hi v78, v[69:70], off offset:1542
s_waitcnt vmcnt(23)
global_load_short_d16_hi v87, v[79:80], off offset:2
s_waitcnt vmcnt(23)
global_load_short_d16_hi v88, v[79:80], off offset:6
s_waitcnt vmcnt(23)
global_load_short_d16_hi v89, v[81:82], off offset:514
s_waitcnt vmcnt(23)
global_load_short_d16_hi v90, v[81:82], off offset:518
s_waitcnt vmcnt(23)
global_load_short_d16_hi v91, v[83:84], off offset:1026
s_waitcnt vmcnt(23)
global_load_short_d16_hi v92, v[83:84], off offset:1030
s_waitcnt vmcnt(23)
global_load_short_d16_hi v93, v[85:86], off offset:1538
s_waitcnt vmcnt(23)
global_load_short_d16_hi v94, v[85:86], off offset:1542
s_waitcnt vmcnt(20)
ds_write2st64_b64 v45, v[55:56], v[57:58] offset1:5
s_waitcnt vmcnt(16)
ds_write2st64_b64 v45, v[59:60], v[61:62] offset0:10 offset1:15
s_waitcnt vmcnt(12)
ds_write2st64_b64 v45, v[71:72], v[73:74] offset0:20 offset1:25
s_waitcnt vmcnt(8)
ds_write2st64_b64 v45, v[75:76], v[77:78] offset0:30 offset1:35
s_waitcnt vmcnt(4)
ds_write2st64_b64 v45, v[87:88], v[89:90] offset0:40 offset1:45
s_waitcnt vmcnt(0)
ds_write2st64_b64 v45, v[91:92], v[93:94] offset0:50 offset1:55
s_and_saveexec_b32 s15, s0
s_cbranch_execz BB45_5
v_add_co_u32 v47, s1, 0x7800, v47
v_add_co_ci_u32_e64 v48, s1, 0, v48, s1
s_clause 0x1
global_load_ushort v49, v[47:48], off
global_load_ushort v50, v[47:48], off offset:4
s_waitcnt vmcnt(1)
global_load_short_d16_hi v49, v[47:48], off offset:2
s_waitcnt vmcnt(1)
global_load_short_d16_hi v50, v[47:48], off offset:6
s_waitcnt vmcnt(0)
ds_write_b64 v45, v[49:50] offset:30720
BB45_5:
s_or_b32 exec_lo, exec_lo, s15
v_mov_b32_e32 v47, v46
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_barrier
BB45_6:
v_or_b32_e32 v52, s1, v41
ds_read2_b32 v[48:49], v47 offset1:16
ds_read2_b32 v[50:51], v47 offset0:32 offset1:48
ds_read_b32 v68, v47 offset:256
v_add_nc_u32_e32 v47, 4, v47
s_add_i32 s1, s1, s13
v_lshlrev_b32_e32 v66, 1, v52
s_cmp_lg_u32 s1, s14
ds_read2st64_b32 v[52:53], v66 offset1:1
ds_read2st64_b32 v[54:55], v66 offset0:2 offset1:3
ds_read2st64_b32 v[56:57], v66 offset0:4 offset1:5
ds_read2st64_b32 v[58:59], v66 offset0:6 offset1:7
ds_read2st64_b32 v[60:61], v66 offset0:8 offset1:9
ds_read2st64_b32 v[62:63], v66 offset0:10 offset1:11
ds_read2st64_b32 v[64:65], v66 offset0:12 offset1:13
ds_read2st64_b32 v[66:67], v66 offset0:14 offset1:15
s_waitcnt lgkmcnt(7)
v_pk_fma_f16 v38, v48, v52, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v39, v48, v53, v39 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v34, v49, v52, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v49, v53, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v50, v52, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v50, v53, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v51, v52, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v51, v53, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v68, v52, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v68, v53, v22 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(6)
v_pk_fma_f16 v37, v48, v54, v37 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v36, v48, v55, v36 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v26, v49, v54, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v49, v55, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v50, v54, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v50, v55, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v51, v54, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v51, v55, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v68, v54, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v68, v55, v4 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v35, v48, v56, v35 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v33, v48, v57, v33 op_sel:[0,1,0] op_sel_hi:[0,0,1]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v32, v48, v58, v32 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v31, v48, v59, v31 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v19, v49, v56, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v49, v57, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v49, v58, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v49, v59, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v50, v56, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v50, v57, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v50, v58, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v50, v59, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v51, v56, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v51, v57, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v51, v58, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v51, v59, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v68, v56, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v68, v57, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v68, v58, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v68, v59, v0 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v38, v48, v60, v38 op_sel:[1,0,0]
v_pk_fma_f16 v39, v48, v61, v39 op_sel:[1,1,0] op_sel_hi:[1,0,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v37, v48, v62, v37 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v36, v48, v63, v36 op_sel:[1,1,0] op_sel_hi:[1,0,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v35, v48, v64, v35 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v33, v48, v65, v33 op_sel:[1,1,0] op_sel_hi:[1,0,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v32, v48, v66, v32 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v31, v48, v67, v31 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v34, v49, v60, v34 op_sel:[1,0,0]
v_pk_fma_f16 v28, v49, v61, v28 op_sel:[1,0,0]
v_pk_fma_f16 v26, v49, v62, v26 op_sel:[1,0,0]
v_pk_fma_f16 v21, v49, v63, v21 op_sel:[1,0,0]
v_pk_fma_f16 v19, v49, v64, v19 op_sel:[1,0,0]
v_pk_fma_f16 v17, v49, v65, v17 op_sel:[1,0,0]
v_pk_fma_f16 v16, v49, v66, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v49, v67, v15 op_sel:[1,0,0]
v_pk_fma_f16 v30, v50, v60, v30 op_sel:[1,0,0]
v_pk_fma_f16 v27, v50, v61, v27 op_sel:[1,0,0]
v_pk_fma_f16 v23, v50, v62, v23 op_sel:[1,0,0]
v_pk_fma_f16 v18, v50, v63, v18 op_sel:[1,0,0]
v_pk_fma_f16 v13, v50, v64, v13 op_sel:[1,0,0]
v_pk_fma_f16 v11, v50, v65, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v50, v66, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v50, v67, v9 op_sel:[1,0,0]
v_pk_fma_f16 v29, v51, v60, v29 op_sel:[1,0,0]
v_pk_fma_f16 v24, v51, v61, v24 op_sel:[1,0,0]
v_pk_fma_f16 v20, v51, v62, v20 op_sel:[1,0,0]
v_pk_fma_f16 v12, v51, v63, v12 op_sel:[1,0,0]
v_pk_fma_f16 v8, v51, v64, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v51, v65, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v51, v66, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v51, v67, v5 op_sel:[1,0,0]
v_pk_fma_f16 v25, v68, v60, v25 op_sel:[1,0,0]
v_pk_fma_f16 v22, v68, v61, v22 op_sel:[1,0,0]
v_pk_fma_f16 v14, v68, v62, v14 op_sel:[1,0,0]
v_pk_fma_f16 v4, v68, v63, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v68, v64, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v68, v65, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v68, v66, v1 op_sel:[1,0,0]
v_pk_fma_f16 v0, v68, v67, v0 op_sel:[1,0,0]
s_cbranch_scc1 BB45_6
s_add_i32 s7, s7, 1
s_cmp_eq_u32 s7, 32
s_cbranch_scc0 BB45_1
v_lshlrev_b32_e32 v42, 1, v41
s_mulk_i32 s6, 0x6400
v_mad_u32_u24 v40, 0x1400, v40, s6
s_clause 0xe
global_load_ushort v87, v42, s[4:5] offset:256
global_load_ushort v88, v42, s[4:5] offset:512
global_load_ushort v89, v42, s[4:5] offset:768
global_load_ushort v90, v42, s[4:5] offset:1024
global_load_ushort v91, v42, s[4:5] offset:1280
global_load_ushort v92, v42, s[4:5] offset:1536
global_load_ushort v93, v42, s[4:5] offset:1792
global_load_ushort v94, v42, s[4:5] offset:770
global_load_ushort v95, v42, s[4:5] offset:514
global_load_ushort v96, v42, s[4:5] offset:258
global_load_dword v97, v42, s[4:5]
global_load_ushort v98, v42, s[4:5] offset:1794
global_load_ushort v99, v42, s[4:5] offset:1538
global_load_ushort v100, v42, s[4:5] offset:1282
global_load_ushort v101, v42, s[4:5] offset:1026
v_or_b32_e32 v40, v40, v41
v_ashrrev_i32_e32 v41, 31, v40
v_add_nc_u32_e32 v42, 0x400, v40
v_add_nc_u32_e32 v44, 0x800, v40
v_add_nc_u32_e32 v51, 0xc00, v40
v_add_nc_u32_e32 v46, 0x480, v40
v_lshlrev_b64 v[66:67], 1, v[40:41]
v_ashrrev_i32_e32 v43, 31, v42
v_ashrrev_i32_e32 v45, 31, v44
v_ashrrev_i32_e32 v52, 31, v51
v_add_nc_u32_e32 v48, 0x500, v40
v_add_nc_u32_e32 v50, 0x580, v40
v_add_co_u32 v66, vcc_lo, s2, v66
v_lshlrev_b64 v[42:43], 1, v[42:43]
v_add_co_ci_u32_e32 v67, vcc_lo, s3, v67, vcc_lo
v_lshlrev_b64 v[44:45], 1, v[44:45]
v_lshlrev_b64 v[51:52], 1, v[51:52]
v_add_nc_u32_e32 v53, 0x600, v40
v_add_nc_u32_e32 v55, 0x680, v40
v_add_co_u32 v42, vcc_lo, s2, v42
v_add_nc_u32_e32 v57, 0x700, v40
v_add_co_ci_u32_e32 v43, vcc_lo, s3, v43, vcc_lo
v_add_co_u32 v44, vcc_lo, s2, v44
v_add_nc_u32_e32 v59, 0x780, v40
v_add_co_ci_u32_e32 v45, vcc_lo, s3, v45, vcc_lo
v_add_co_u32 v51, vcc_lo, s2, v51
v_ashrrev_i32_e32 v58, 31, v57
v_add_co_ci_u32_e32 v52, vcc_lo, s3, v52, vcc_lo
v_add_nc_u32_e32 v61, 0x880, v40
v_ashrrev_i32_e32 v60, 31, v59
v_add_nc_u32_e32 v63, 0x900, v40
v_add_nc_u32_e32 v65, 0x980, v40
v_add_nc_u32_e32 v41, 0xa00, v40
v_ashrrev_i32_e32 v62, 31, v61
v_add_nc_u32_e32 v68, 0xa80, v40
v_ashrrev_i32_e32 v64, 31, v63
v_add_nc_u32_e32 v70, 0xb80, v40
v_add_nc_u32_e32 v72, 0xd80, v40
v_add_nc_u32_e32 v74, 0xe00, v40
v_ashrrev_i32_e32 v69, 31, v68
v_add_nc_u32_e32 v76, 0xf80, v40
v_ashrrev_i32_e32 v71, 31, v70
v_ashrrev_i32_e32 v73, 31, v72
v_ashrrev_i32_e32 v75, 31, v74
v_add_nc_u32_e32 v78, 0x1000, v40
v_ashrrev_i32_e32 v77, 31, v76
v_add_nc_u32_e32 v81, 0x1200, v40
v_add_nc_u32_e32 v83, 0x1280, v40
v_add_nc_u32_e32 v85, 0x1300, v40
v_ashrrev_i32_e32 v79, 31, v78
v_ashrrev_i32_e32 v82, 31, v81
v_ashrrev_i32_e32 v84, 31, v83
v_ashrrev_i32_e32 v86, 31, v85
v_lshlrev_b64 v[81:82], 1, v[81:82]
v_lshlrev_b64 v[83:84], 1, v[83:84]
v_lshlrev_b64 v[85:86], 1, v[85:86]
s_waitcnt vmcnt(14)
v_add_f16_sdwa v47, v87, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
s_waitcnt vmcnt(13)
v_add_f16_sdwa v49, v88, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
s_waitcnt vmcnt(12)
v_add_f16_sdwa v54, v89, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
global_store_short v[66:67], v47, off offset:256
s_waitcnt vmcnt(11)
v_add_f16_sdwa v47, v90, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
global_store_short v[66:67], v49, off offset:512
s_waitcnt vmcnt(10)
v_add_f16_sdwa v49, v91, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
global_store_short v[66:67], v54, off offset:768
s_waitcnt vmcnt(4)
v_pk_add_f16 v56, v97, v38
global_store_short v[66:67], v47, off offset:1024
v_add_f16_sdwa v47, v93, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_add_f16_sdwa v54, v92, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_add_f16_e32 v39, v96, v39
v_add_f16_e32 v37, v95, v37
v_add_f16_e32 v36, v94, v36
global_store_short v[66:67], v49, off offset:1280
global_store_short v[66:67], v54, off offset:1536
global_store_short v[66:67], v47, off offset:1792
global_store_dword v[66:67], v56, off
s_waitcnt vmcnt(0)
v_add_f16_e32 v47, v101, v35
v_add_f16_e32 v33, v100, v33
v_add_f16_e32 v31, v98, v31
global_store_short v[66:67], v39, off offset:258
global_store_short v[66:67], v37, off offset:514
v_add_f16_e32 v37, v99, v32
global_store_short v[66:67], v36, off offset:770
global_store_short v[66:67], v47, off offset:1026
v_pk_add_f16 v30, v97, v30
v_ashrrev_i32_e32 v47, 31, v46
global_store_short v[66:67], v33, off offset:1282
global_store_short v[66:67], v37, off offset:1538
global_store_short v[66:67], v31, off offset:1794
v_pk_add_f16 v31, v97, v29
v_ashrrev_i32_e32 v49, 31, v48
global_store_dword v[44:45], v30, off
v_lshlrev_b64 v[45:46], 1, v[46:47]
v_ashrrev_i32_e32 v54, 31, v53
global_store_dword v[51:52], v31, off
v_ashrrev_i32_e32 v51, 31, v50
v_lshlrev_b64 v[47:48], 1, v[48:49]
v_ashrrev_i32_e32 v56, 31, v55
v_add_co_u32 v45, vcc_lo, s2, v45
v_pk_add_f16 v33, v97, v34
v_lshlrev_b64 v[49:50], 1, v[50:51]
v_add_co_ci_u32_e32 v46, vcc_lo, s3, v46, vcc_lo
v_add_co_u32 v47, vcc_lo, s2, v47
v_lshlrev_b64 v[51:52], 1, v[53:54]
v_add_co_ci_u32_e32 v48, vcc_lo, s3, v48, vcc_lo
v_lshlrev_b64 v[53:54], 1, v[55:56]
v_add_co_u32 v49, vcc_lo, s2, v49
v_lshlrev_b64 v[55:56], 1, v[57:58]
v_add_co_ci_u32_e32 v50, vcc_lo, s3, v50, vcc_lo
v_add_co_u32 v51, vcc_lo, s2, v51
v_lshlrev_b64 v[57:58], 1, v[59:60]
v_add_co_ci_u32_e32 v52, vcc_lo, s3, v52, vcc_lo
v_add_co_u32 v53, vcc_lo, s2, v53
v_lshlrev_b64 v[59:60], 1, v[61:62]
v_add_co_ci_u32_e32 v54, vcc_lo, s3, v54, vcc_lo
v_add_co_u32 v55, vcc_lo, s2, v55
v_ashrrev_i32_e32 v66, 31, v65
v_add_co_ci_u32_e32 v56, vcc_lo, s3, v56, vcc_lo
v_add_co_u32 v57, vcc_lo, s2, v57
v_lshlrev_b64 v[61:62], 1, v[63:64]
global_store_dword v[42:43], v33, off
v_ashrrev_i32_e32 v42, 31, v41
v_add_co_ci_u32_e32 v58, vcc_lo, s3, v58, vcc_lo
v_add_nc_u32_e32 v38, 0xb00, v40
v_add_co_u32 v59, vcc_lo, s2, v59
v_lshlrev_b64 v[63:64], 1, v[65:66]
v_add_co_ci_u32_e32 v60, vcc_lo, s3, v60, vcc_lo
v_add_co_u32 v61, vcc_lo, s2, v61
v_lshlrev_b64 v[41:42], 1, v[41:42]
v_ashrrev_i32_e32 v39, 31, v38
v_add_co_ci_u32_e32 v62, vcc_lo, s3, v62, vcc_lo
v_add_nc_u32_e32 v35, 0xc80, v40
v_add_co_u32 v63, vcc_lo, s2, v63
v_lshlrev_b64 v[65:66], 1, v[68:69]
v_add_co_ci_u32_e32 v64, vcc_lo, s3, v64, vcc_lo
v_add_nc_u32_e32 v32, 0xd00, v40
v_add_co_u32 v41, vcc_lo, s2, v41
v_lshlrev_b64 v[37:38], 1, v[38:39]
v_ashrrev_i32_e32 v36, 31, v35
v_add_co_ci_u32_e32 v42, vcc_lo, s3, v42, vcc_lo
v_add_co_u32 v65, vcc_lo, s2, v65
v_lshlrev_b64 v[67:68], 1, v[70:71]
v_ashrrev_i32_e32 v33, 31, v32
v_add_co_ci_u32_e32 v66, vcc_lo, s3, v66, vcc_lo
v_lshlrev_b64 v[34:35], 1, v[35:36]
v_add_co_u32 v36, vcc_lo, s2, v37
v_add_nc_u32_e32 v29, 0xe80, v40
v_add_co_ci_u32_e32 v37, vcc_lo, s3, v38, vcc_lo
v_add_co_u32 v38, vcc_lo, s2, v67
v_lshlrev_b64 v[31:32], 1, v[32:33]
v_add_co_ci_u32_e32 v39, vcc_lo, s3, v68, vcc_lo
v_add_nc_u32_e32 v43, 0xf00, v40
v_add_co_u32 v33, vcc_lo, s2, v34
v_lshlrev_b64 v[69:70], 1, v[72:73]
v_ashrrev_i32_e32 v30, 31, v29
v_add_co_ci_u32_e32 v34, vcc_lo, s3, v35, vcc_lo
v_add_co_u32 v31, vcc_lo, s2, v31
v_lshlrev_b64 v[71:72], 1, v[74:75]
v_ashrrev_i32_e32 v44, 31, v43
v_add_co_ci_u32_e32 v32, vcc_lo, s3, v32, vcc_lo
v_add_co_u32 v67, vcc_lo, s2, v69
v_lshlrev_b64 v[29:30], 1, v[29:30]
v_add_co_ci_u32_e32 v68, vcc_lo, s3, v70, vcc_lo
v_add_co_u32 v69, vcc_lo, s2, v71
v_lshlrev_b64 v[43:44], 1, v[43:44]
v_add_co_ci_u32_e32 v70, vcc_lo, s3, v72, vcc_lo
v_lshlrev_b64 v[73:74], 1, v[76:77]
v_add_co_u32 v29, vcc_lo, s2, v29
v_lshlrev_b64 v[75:76], 1, v[78:79]
v_add_co_ci_u32_e32 v30, vcc_lo, s3, v30, vcc_lo
v_add_co_u32 v43, vcc_lo, s2, v43
v_mov_b32_e32 v35, 0xffff
v_add_co_ci_u32_e32 v44, vcc_lo, s3, v44, vcc_lo
v_add_co_u32 v71, vcc_lo, s2, v73
v_add_nc_u32_e32 v77, 0x1100, v40
v_add_co_ci_u32_e32 v72, vcc_lo, s3, v74, vcc_lo
v_add_co_u32 v73, vcc_lo, s2, v75
v_add_nc_u32_e32 v75, 0x1080, v40
v_add_co_ci_u32_e32 v74, vcc_lo, s3, v76, vcc_lo
v_add_nc_u32_e32 v79, 0x1180, v40
v_ashrrev_i32_e32 v78, 31, v77
v_and_b32_e32 v87, v35, v87
v_ashrrev_i32_e32 v76, 31, v75
v_and_b32_e32 v88, v35, v88
v_ashrrev_i32_e32 v80, 31, v79
v_lshlrev_b64 v[77:78], 1, v[77:78]
v_lshl_or_b32 v87, v96, 16, v87
v_lshlrev_b64 v[75:76], 1, v[75:76]
v_lshl_or_b32 v88, v95, 16, v88
v_lshlrev_b64 v[79:80], 1, v[79:80]
v_and_b32_e32 v89, v35, v89
v_pk_add_f16 v28, v87, v28
v_pk_add_f16 v27, v87, v27
v_add_co_u32 v75, vcc_lo, s2, v75
v_pk_add_f16 v24, v87, v24
v_add_co_ci_u32_e32 v76, vcc_lo, s3, v76, vcc_lo
v_pk_add_f16 v87, v87, v22
v_add_nc_u32_e32 v22, 0x1380, v40
v_add_co_u32 v77, vcc_lo, s2, v77
v_and_b32_e32 v90, v35, v90
v_add_co_ci_u32_e32 v78, vcc_lo, s3, v78, vcc_lo
v_add_co_u32 v79, vcc_lo, s2, v79
v_and_b32_e32 v91, v35, v91
v_and_b32_e32 v92, v35, v92
v_and_b32_e32 v35, v35, v93
v_pk_add_f16 v93, v88, v23
v_ashrrev_i32_e32 v23, 31, v22
v_add_co_ci_u32_e32 v80, vcc_lo, s3, v80, vcc_lo
v_add_co_u32 v81, vcc_lo, s2, v81
v_lshl_or_b32 v89, v94, 16, v89
v_lshl_or_b32 v90, v101, 16, v90
v_add_co_ci_u32_e32 v82, vcc_lo, s3, v82, vcc_lo
v_lshl_or_b32 v91, v100, 16, v91
v_lshl_or_b32 v35, v98, 16, v35
v_add_co_u32 v83, vcc_lo, s2, v83
v_lshlrev_b64 v[22:23], 1, v[22:23]
v_lshl_or_b32 v92, v99, 16, v92
v_add_co_ci_u32_e32 v84, vcc_lo, s3, v84, vcc_lo
v_pk_add_f16 v26, v88, v26
v_add_co_u32 v85, vcc_lo, s2, v85
v_pk_add_f16 v21, v89, v21
v_pk_add_f16 v25, v97, v25
v_pk_add_f16 v19, v90, v19
v_pk_add_f16 v4, v89, v4
v_add_co_ci_u32_e32 v86, vcc_lo, s3, v86, vcc_lo
v_pk_add_f16 v17, v91, v17
v_pk_add_f16 v5, v35, v5
v_pk_add_f16 v3, v90, v3
v_pk_add_f16 v20, v88, v20
v_pk_add_f16 v14, v88, v14
v_pk_add_f16 v16, v92, v16
v_pk_add_f16 v15, v35, v15
v_pk_add_f16 v18, v89, v18
v_pk_add_f16 v13, v90, v13
v_pk_add_f16 v11, v91, v11
v_pk_add_f16 v10, v92, v10
v_pk_add_f16 v9, v35, v9
v_pk_add_f16 v12, v89, v12
v_pk_add_f16 v8, v90, v8
v_pk_add_f16 v7, v91, v7
v_pk_add_f16 v6, v92, v6
global_store_dword v[45:46], v28, off
global_store_dword v[47:48], v26, off
global_store_dword v[49:50], v21, off
global_store_dword v[51:52], v19, off
global_store_dword v[53:54], v17, off
global_store_dword v[55:56], v16, off
global_store_dword v[57:58], v15, off
global_store_dword v[59:60], v27, off
global_store_dword v[61:62], v93, off
global_store_dword v[63:64], v18, off
global_store_dword v[41:42], v13, off
global_store_dword v[65:66], v11, off
global_store_dword v[36:37], v10, off
global_store_dword v[38:39], v9, off
global_store_dword v[33:34], v24, off
global_store_dword v[31:32], v20, off
global_store_dword v[67:68], v12, off
global_store_dword v[69:70], v8, off
global_store_dword v[29:30], v7, off
global_store_dword v[43:44], v6, off
global_store_dword v[71:72], v5, off
v_add_co_u32 v5, vcc_lo, s2, v22
v_pk_add_f16 v2, v91, v2
v_pk_add_f16 v1, v92, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v23, vcc_lo
v_pk_add_f16 v0, v35, v0
global_store_dword v[73:74], v25, off
global_store_dword v[75:76], v87, off
global_store_dword v[77:78], v14, off
global_store_dword v[79:80], v4, off
global_store_dword v[81:82], v3, off
global_store_dword v[83:84], v2, off
global_store_dword v[85:86], v1, off
global_store_dword v[5:6], v0, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_2_kernel0
.amdhsa_group_segment_fixed_size 34336
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 102
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end45:
.size tvmgen_default_fused_nn_conv2d_add_2_kernel0, .Lfunc_end45-tvmgen_default_fused_nn_conv2d_add_2_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_3_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_3_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_3_kernel0:
v_lshrrev_b32_e32 v1, 4, v0
s_mov_b32 s0, 0x5397829d
v_add_nc_u32_e32 v6, 0x280, v0
v_add_nc_u32_e32 v8, 0x500, v0
v_add_nc_u32_e32 v9, 0x780, v0
v_add_nc_u32_e32 v2, 40, v1
v_add_nc_u32_e32 v3, 31, v1
v_mul_hi_u32 v6, v6, s0
v_mul_hi_u32 v8, v8, s0
v_lshlrev_b32_e32 v22, 10, v1
v_mul_hi_u32 v4, v2, s0
v_mul_hi_u32 v5, v3, s0
s_clause 0x3
s_load_dwordx2 s[10:11], s[4:5], 0x0
s_load_dwordx2 s[12:13], s[4:5], 0x8
s_load_dwordx2 s[8:9], s[4:5], 0x10
s_load_dwordx2 s[2:3], s[4:5], 0x18
s_mov_b32 s14, 0xc800
v_lshlrev_b32_e32 v10, 3, v0
v_lshrrev_b32_e32 v1, 8, v6
v_mul_hi_u32 v9, v9, s0
v_lshrrev_b32_e32 v35, 7, v0
v_lshrrev_b32_e32 v4, 4, v4
v_lshrrev_b32_e32 v5, 4, v5
v_mul_i32_i24_e32 v24, s14, v1
v_lshlrev_b32_e32 v1, 5, v0
v_lshlrev_b32_e32 v7, 1, v0
v_mul_u32_u24_e32 v4, 49, v4
v_mul_u32_u24_e32 v5, 49, v5
s_movk_i32 s1, 0x4000
v_and_b32_e32 v30, 0x7800, v1
v_or_b32_e32 v1, 4, v10
v_sub_nc_u32_e32 v2, v2, v4
v_sub_nc_u32_e32 v3, v3, v5
v_lshrrev_b32_e32 v4, 8, v8
v_lshrrev_b32_e32 v5, 8, v9
v_and_b32_e32 v36, 0x1fc, v1
v_lshlrev_b32_e32 v25, 10, v2
v_lshlrev_b32_e32 v26, 10, v3
v_mul_i32_i24_e32 v27, s14, v4
v_or_b32_e32 v2, 1, v10
v_or_b32_e32 v3, 2, v10
v_or_b32_e32 v4, 3, v10
v_mul_u32_u24_e32 v1, 0xa0, v35
v_mul_i32_i24_e32 v28, s14, v5
v_and_b32_e32 v32, 0x1f9, v2
v_and_b32_e32 v33, 0x1fa, v3
v_and_b32_e32 v34, 0x1fb, v4
v_or_b32_e32 v2, 5, v10
v_or_b32_e32 v3, 6, v10
v_or_b32_e32 v4, 7, v10
v_and_b32_e32 v29, 0x1f8, v10
v_lshl_or_b32 v40, v1, 1, s1
v_and_b32_e32 v37, 0x1fd, v2
v_and_b32_e32 v38, 0x1fe, v3
v_and_b32_e32 v39, 0x1ff, v4
v_and_b32_e32 v21, 15, v0
v_or_b32_e32 v23, s1, v7
v_and_b32_e32 v3, 0xfe, v7
v_cmp_gt_i32_e32 vcc_lo, 0x1b0, v0
v_lshlrev_b32_e32 v31, 4, v0
v_cmp_gt_i32_e64 s0, 0x180, v0
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v17, 0
s_lshl_b32 s4, s6, 9
s_ashr_i32 s7, s6, 2
s_and_b32 s4, s4, 0x600
s_mul_i32 s5, s7, 0x32000
s_mov_b32 s6, 0
s_mov_b32 s14, 0xa000
BB46_1:
s_lshl_b32 s15, s6, 4
s_add_i32 s15, s15, s5
v_or_b32_e32 v42, s15, v21
v_add_nc_u32_e32 v41, v42, v22
v_add3_u32 v43, v42, v24, v25
v_add3_u32 v45, v42, v27, v26
v_ashrrev_i32_e32 v42, 31, v41
v_ashrrev_i32_e32 v44, 31, v43
v_ashrrev_i32_e32 v46, 31, v45
v_lshlrev_b64 v[41:42], 1, v[41:42]
v_lshlrev_b64 v[43:44], 1, v[43:44]
v_lshlrev_b64 v[45:46], 1, v[45:46]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v41, s1, s10, v41
v_add_co_ci_u32_e64 v42, s1, s11, v42, s1
v_add_co_u32 v43, s1, s10, v43
v_add_co_ci_u32_e64 v44, s1, s11, v44, s1
v_add_co_u32 v45, s1, s10, v45
v_add_co_ci_u32_e64 v46, s1, s11, v46, s1
s_clause 0x2
global_load_ushort v41, v[41:42], off
global_load_ushort v42, v[43:44], off
global_load_ushort v43, v[45:46], off
s_waitcnt vmcnt(0)
s_barrier
ds_write_b16 v23, v41
ds_write_b16 v23, v42 offset:1280
ds_write_b16 v23, v43 offset:2560
s_and_saveexec_b32 s16, vcc_lo
s_cbranch_execz BB46_3
s_addk_i32 s15, 0x5800
v_or_b32_e32 v41, s15, v21
v_add3_u32 v41, v41, v22, v28
v_ashrrev_i32_e32 v42, 31, v41
v_lshlrev_b64 v[41:42], 1, v[41:42]
v_add_co_u32 v41, s1, s10, v41
v_add_co_ci_u32_e64 v42, s1, s11, v42, s1
global_load_ushort v41, v[41:42], off
s_waitcnt vmcnt(0)
ds_write_b16 v23, v41 offset:3840
BB46_3:
s_or_b32 exec_lo, exec_lo, s16
s_lshl_b32 s1, s6, 15
v_or3_b32 v49, s1, v30, s4
v_or_b32_e32 v41, v49, v29
v_or_b32_e32 v43, v49, v33
v_or_b32_e32 v45, v49, v36
v_or_b32_e32 v47, v49, v38
v_ashrrev_i32_e32 v42, 31, v41
v_ashrrev_i32_e32 v44, 31, v43
v_ashrrev_i32_e32 v46, 31, v45
v_ashrrev_i32_e32 v48, 31, v47
v_lshlrev_b64 v[41:42], 1, v[41:42]
v_lshlrev_b64 v[43:44], 1, v[43:44]
v_lshlrev_b64 v[45:46], 1, v[45:46]
v_lshlrev_b64 v[47:48], 1, v[47:48]
v_add_co_u32 v55, s1, s12, v41
v_add_co_ci_u32_e64 v56, s1, s13, v42, s1
v_add_co_u32 v53, s1, s12, v43
v_or_b32_e32 v43, v49, v32
v_add_co_ci_u32_e64 v54, s1, s13, v44, s1
v_add_co_u32 v51, s1, s12, v45
v_or_b32_e32 v45, v49, v34
v_add_co_ci_u32_e64 v52, s1, s13, v46, s1
v_add_co_u32 v41, s1, s12, v47
v_ashrrev_i32_e32 v44, 31, v43
v_add_co_ci_u32_e64 v42, s1, s13, v48, s1
v_or_b32_e32 v47, v49, v37
s_clause 0x3
global_load_ushort v57, v[55:56], off
global_load_ushort v58, v[53:54], off
global_load_ushort v59, v[51:52], off
global_load_ushort v60, v[41:42], off
v_ashrrev_i32_e32 v46, 31, v45
v_or_b32_e32 v49, v49, v39
v_lshlrev_b64 v[43:44], 1, v[43:44]
v_ashrrev_i32_e32 v48, 31, v47
v_lshlrev_b64 v[45:46], 1, v[45:46]
v_ashrrev_i32_e32 v50, 31, v49
v_add_co_u32 v43, s1, s12, v43
v_lshlrev_b64 v[47:48], 1, v[47:48]
v_add_co_ci_u32_e64 v44, s1, s13, v44, s1
v_add_co_u32 v45, s1, s12, v45
v_lshlrev_b64 v[49:50], 1, v[49:50]
v_add_co_ci_u32_e64 v46, s1, s13, v46, s1
v_add_co_u32 v47, s1, s12, v47
v_add_co_ci_u32_e64 v48, s1, s13, v48, s1
v_add_co_u32 v49, s1, s12, v49
v_add_co_ci_u32_e64 v50, s1, s13, v50, s1
s_waitcnt vmcnt(3)
global_load_short_d16_hi v57, v[43:44], off
s_waitcnt vmcnt(3)
global_load_short_d16_hi v58, v[45:46], off
s_waitcnt vmcnt(3)
global_load_short_d16_hi v59, v[47:48], off
s_waitcnt vmcnt(3)
global_load_short_d16_hi v60, v[49:50], off
s_waitcnt vmcnt(0)
ds_write_b128 v31, v[57:60]
s_and_saveexec_b32 s15, s0
s_cbranch_execz BB46_5
v_add_co_u32 v55, s1, s14, v55
v_add_co_ci_u32_e64 v56, s1, 0, v56, s1
v_add_co_u32 v53, s1, s14, v53
v_add_co_ci_u32_e64 v54, s1, 0, v54, s1
v_add_co_u32 v57, s1, s14, v51
v_add_co_ci_u32_e64 v58, s1, 0, v52, s1
v_add_co_u32 v41, s1, s14, v41
v_add_co_ci_u32_e64 v42, s1, 0, v42, s1
s_clause 0x3
global_load_ushort v51, v[55:56], off
global_load_ushort v52, v[53:54], off
global_load_ushort v53, v[57:58], off
global_load_ushort v54, v[41:42], off
v_add_co_u32 v41, s1, s14, v43
v_add_co_ci_u32_e64 v42, s1, 0, v44, s1
v_add_co_u32 v43, s1, s14, v45
v_add_co_ci_u32_e64 v44, s1, 0, v46, s1
v_add_co_u32 v45, s1, s14, v47
v_add_co_ci_u32_e64 v46, s1, 0, v48, s1
v_add_co_u32 v47, s1, s14, v49
v_add_co_ci_u32_e64 v48, s1, 0, v50, s1
s_waitcnt vmcnt(3)
global_load_short_d16_hi v51, v[41:42], off
s_waitcnt vmcnt(3)
global_load_short_d16_hi v52, v[43:44], off
s_waitcnt vmcnt(3)
global_load_short_d16_hi v53, v[45:46], off
s_waitcnt vmcnt(3)
global_load_short_d16_hi v54, v[47:48], off
s_waitcnt vmcnt(0)
ds_write_b128 v31, v[51:54] offset:10240
BB46_5:
s_or_b32 exec_lo, exec_lo, s15
v_mov_b32_e32 v41, v40
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_barrier
BB46_6:
v_or_b32_e32 v46, s1, v3
v_add_nc_u32_e32 v48, 0xc00, v41
ds_read2_b32 v[42:43], v41 offset1:16
ds_read2_b32 v[44:45], v41 offset0:32 offset1:48
ds_read_b32 v54, v41 offset:256
ds_read_b32 v55, v41 offset:3392
v_add_nc_u32_e32 v41, 4, v41
v_lshlrev_b32_e32 v52, 1, v46
s_addk_i32 s1, 0x400
ds_read2_b32 v[46:47], v48 offset0:16 offset1:32
ds_read2_b32 v[48:49], v48 offset0:48 offset1:64
ds_read2st64_b32 v[50:51], v52 offset1:2
ds_read2st64_b32 v[52:53], v52 offset0:4 offset1:6
s_cmpk_lg_i32 s1, 0x2000
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v20, v42, v50, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v42, v51, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v43, v50, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v43, v51, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v44, v50, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v44, v51, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v45, v50, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v45, v51, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v54, v50, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v54, v51, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v46, v50, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v46, v51, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v47, v50, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v47, v51, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v48, v50, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v48, v51, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v49, v50, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v49, v51, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v55, v50, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v55, v51, v0 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v20, v42, v52, v20 op_sel:[1,0,0]
v_pk_fma_f16 v17, v42, v53, v17 op_sel:[1,0,0]
v_pk_fma_f16 v19, v43, v52, v19 op_sel:[1,0,0]
v_pk_fma_f16 v12, v43, v53, v12 op_sel:[1,0,0]
v_pk_fma_f16 v18, v44, v52, v18 op_sel:[1,0,0]
v_pk_fma_f16 v10, v44, v53, v10 op_sel:[1,0,0]
v_pk_fma_f16 v16, v45, v52, v16 op_sel:[1,0,0]
v_pk_fma_f16 v8, v45, v53, v8 op_sel:[1,0,0]
v_pk_fma_f16 v15, v54, v52, v15 op_sel:[1,0,0]
v_pk_fma_f16 v6, v54, v53, v6 op_sel:[1,0,0]
v_pk_fma_f16 v14, v46, v52, v14 op_sel:[1,0,0]
v_pk_fma_f16 v5, v46, v53, v5 op_sel:[1,0,0]
v_pk_fma_f16 v13, v47, v52, v13 op_sel:[1,0,0]
v_pk_fma_f16 v4, v47, v53, v4 op_sel:[1,0,0]
v_pk_fma_f16 v11, v48, v52, v11 op_sel:[1,0,0]
v_pk_fma_f16 v2, v48, v53, v2 op_sel:[1,0,0]
v_pk_fma_f16 v9, v49, v52, v9 op_sel:[1,0,0]
v_pk_fma_f16 v1, v49, v53, v1 op_sel:[1,0,0]
v_pk_fma_f16 v7, v55, v52, v7 op_sel:[1,0,0]
v_pk_fma_f16 v0, v55, v53, v0 op_sel:[1,0,0]
s_cbranch_scc1 BB46_6
s_add_i32 s6, s6, 1
s_cmp_eq_u32 s6, 64
s_cbranch_scc0 BB46_1
s_mul_i32 s7, s7, 0x19000
v_mad_u32_u24 v21, 0x2800, v35, s7
v_or3_b32 v21, v21, s4, v3
v_or_b32_e32 v3, s4, v3
v_add_nc_u32_e32 v23, 0x800, v21
v_add_nc_u32_e32 v25, 0x900, v21
v_add_nc_u32_e32 v27, 0x1000, v21
v_add_nc_u32_e32 v29, 0x1100, v21
v_ashrrev_i32_e32 v22, 31, v21
v_ashrrev_i32_e32 v24, 31, v23
v_ashrrev_i32_e32 v26, 31, v25
v_ashrrev_i32_e32 v28, 31, v27
v_ashrrev_i32_e32 v30, 31, v29
v_lshlrev_b32_e32 v3, 1, v3
v_lshlrev_b64 v[32:33], 1, v[21:22]
v_lshlrev_b64 v[22:23], 1, v[23:24]
v_lshlrev_b64 v[24:25], 1, v[25:26]
v_lshlrev_b64 v[26:27], 1, v[27:28]
v_lshlrev_b64 v[28:29], 1, v[29:30]
v_add_nc_u32_e32 v36, 0x2000, v21
v_add_nc_u32_e32 v38, 0x2100, v21
v_add_nc_u32_e32 v40, 0xc800, v21
v_add_nc_u32_e32 v42, 0xc900, v21
v_add_nc_u32_e32 v44, 0xd000, v21
v_add_nc_u32_e32 v46, 0xd100, v21
v_add_nc_u32_e32 v48, 0xd800, v21
v_add_nc_u32_e32 v50, 0xd900, v21
v_add_nc_u32_e32 v52, 0xe000, v21
v_add_nc_u32_e32 v54, 0xe100, v21
v_add_nc_u32_e32 v56, 0xe800, v21
v_add_nc_u32_e32 v58, 0xe900, v21
v_add_nc_u32_e32 v31, 0x1800, v21
v_add_nc_u32_e32 v30, 0x1900, v21
s_clause 0x2
global_load_dword v21, v3, s[2:3]
global_load_ushort v60, v3, s[2:3] offset:512
global_load_ushort v3, v3, s[2:3] offset:514
v_add_co_u32 v34, vcc_lo, s8, v32
v_ashrrev_i32_e32 v37, 31, v36
v_add_co_ci_u32_e32 v35, vcc_lo, s9, v33, vcc_lo
v_ashrrev_i32_e32 v32, 31, v31
v_add_co_u32 v22, vcc_lo, s8, v22
v_ashrrev_i32_e32 v39, 31, v38
v_add_co_ci_u32_e32 v23, vcc_lo, s9, v23, vcc_lo
v_add_co_u32 v24, vcc_lo, s8, v24
v_lshlrev_b64 v[32:33], 1, v[31:32]
v_ashrrev_i32_e32 v31, 31, v30
v_add_co_ci_u32_e32 v25, vcc_lo, s9, v25, vcc_lo
v_add_co_u32 v26, vcc_lo, s8, v26
v_lshlrev_b64 v[36:37], 1, v[36:37]
v_add_co_ci_u32_e32 v27, vcc_lo, s9, v27, vcc_lo
v_add_co_u32 v28, vcc_lo, s8, v28
v_lshlrev_b64 v[30:31], 1, v[30:31]
v_add_co_ci_u32_e32 v29, vcc_lo, s9, v29, vcc_lo
v_add_co_u32 v32, vcc_lo, s8, v32
v_ashrrev_i32_e32 v41, 31, v40
v_add_co_ci_u32_e32 v33, vcc_lo, s9, v33, vcc_lo
v_lshlrev_b64 v[38:39], 1, v[38:39]
v_add_co_u32 v30, vcc_lo, s8, v30
v_ashrrev_i32_e32 v43, 31, v42
v_add_co_ci_u32_e32 v31, vcc_lo, s9, v31, vcc_lo
v_add_co_u32 v36, vcc_lo, s8, v36
v_lshlrev_b64 v[40:41], 1, v[40:41]
v_ashrrev_i32_e32 v45, 31, v44
v_add_co_ci_u32_e32 v37, vcc_lo, s9, v37, vcc_lo
v_add_co_u32 v38, vcc_lo, s8, v38
v_lshlrev_b64 v[42:43], 1, v[42:43]
v_ashrrev_i32_e32 v47, 31, v46
v_add_co_ci_u32_e32 v39, vcc_lo, s9, v39, vcc_lo
v_add_co_u32 v40, vcc_lo, s8, v40
v_lshlrev_b64 v[44:45], 1, v[44:45]
v_ashrrev_i32_e32 v49, 31, v48
v_add_co_ci_u32_e32 v41, vcc_lo, s9, v41, vcc_lo
v_add_co_u32 v42, vcc_lo, s8, v42
v_lshlrev_b64 v[46:47], 1, v[46:47]
v_ashrrev_i32_e32 v51, 31, v50
v_add_co_ci_u32_e32 v43, vcc_lo, s9, v43, vcc_lo
v_add_co_u32 v44, vcc_lo, s8, v44
v_lshlrev_b64 v[48:49], 1, v[48:49]
v_ashrrev_i32_e32 v53, 31, v52
v_add_co_ci_u32_e32 v45, vcc_lo, s9, v45, vcc_lo
v_add_co_u32 v46, vcc_lo, s8, v46
v_lshlrev_b64 v[50:51], 1, v[50:51]
v_ashrrev_i32_e32 v55, 31, v54
v_add_co_ci_u32_e32 v47, vcc_lo, s9, v47, vcc_lo
v_add_co_u32 v48, vcc_lo, s8, v48
v_lshlrev_b64 v[52:53], 1, v[52:53]
v_ashrrev_i32_e32 v57, 31, v56
v_add_co_ci_u32_e32 v49, vcc_lo, s9, v49, vcc_lo
v_add_co_u32 v50, vcc_lo, s8, v50
v_lshlrev_b64 v[54:55], 1, v[54:55]
v_add_co_ci_u32_e32 v51, vcc_lo, s9, v51, vcc_lo
v_ashrrev_i32_e32 v59, 31, v58
v_add_co_u32 v52, vcc_lo, s8, v52
v_lshlrev_b64 v[56:57], 1, v[56:57]
v_add_co_ci_u32_e32 v53, vcc_lo, s9, v53, vcc_lo
v_add_co_u32 v54, vcc_lo, s8, v54
v_lshlrev_b64 v[58:59], 1, v[58:59]
v_add_co_ci_u32_e32 v55, vcc_lo, s9, v55, vcc_lo
v_add_co_u32 v56, vcc_lo, s8, v56
v_add_co_ci_u32_e32 v57, vcc_lo, s9, v57, vcc_lo
v_add_co_u32 v58, vcc_lo, s8, v58
v_add_co_ci_u32_e32 v59, vcc_lo, s9, v59, vcc_lo
s_waitcnt vmcnt(2)
v_pk_add_f16 v20, v21, v20
v_pk_add_f16 v19, v21, v19
v_pk_add_f16 v18, v21, v18
v_pk_add_f16 v16, v21, v16
v_pk_add_f16 v15, v21, v15
v_pk_add_f16 v14, v21, v14
v_pk_add_f16 v13, v21, v13
v_pk_add_f16 v11, v21, v11
v_pk_add_f16 v9, v21, v9
v_pk_add_f16 v7, v21, v7
s_waitcnt vmcnt(1)
v_add_f16_e32 v21, v60, v17
s_waitcnt vmcnt(0)
v_add_f16_sdwa v17, v3, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
global_store_short v[34:35], v21, off offset:512
v_and_b32_e32 v21, 0xffff, v60
global_store_dword v[34:35], v20, off
global_store_short v[34:35], v17, off offset:514
global_store_dword v[22:23], v19, off
global_store_dword v[26:27], v18, off
global_store_dword v[32:33], v16, off
global_store_dword v[36:37], v15, off
global_store_dword v[40:41], v14, off
global_store_dword v[44:45], v13, off
global_store_dword v[48:49], v11, off
global_store_dword v[52:53], v9, off
global_store_dword v[56:57], v7, off
v_lshl_or_b32 v3, v3, 16, v21
v_pk_add_f16 v7, v3, v12
v_pk_add_f16 v9, v3, v10
v_pk_add_f16 v8, v3, v8
v_pk_add_f16 v6, v3, v6
v_pk_add_f16 v5, v3, v5
v_pk_add_f16 v4, v3, v4
v_pk_add_f16 v2, v3, v2
v_pk_add_f16 v1, v3, v1
v_pk_add_f16 v0, v3, v0
global_store_dword v[24:25], v7, off
global_store_dword v[28:29], v9, off
global_store_dword v[30:31], v8, off
global_store_dword v[38:39], v6, off
global_store_dword v[42:43], v5, off
global_store_dword v[46:47], v4, off
global_store_dword v[50:51], v2, off
global_store_dword v[54:55], v1, off
global_store_dword v[58:59], v0, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_3_kernel0
.amdhsa_group_segment_fixed_size 21088
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 61
.amdhsa_next_free_sgpr 17
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end46:
.size tvmgen_default_fused_nn_conv2d_add_3_kernel0, .Lfunc_end46-tvmgen_default_fused_nn_conv2d_add_3_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_4_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_4_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_4_kernel0:
s_clause 0x3
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[14:15], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[4:5], s[4:5], 0x18
s_mul_hi_i32 s0, s6, 0x66666667
v_lshlrev_b32_e32 v1, 5, v0
s_lshr_b32 s1, s0, 31
s_ashr_i32 s0, s0, 1
v_and_b32_e32 v4, 63, v0
s_add_i32 s1, s0, s1
s_movk_i32 s10, 0x2800
s_mul_i32 s0, s1, 5
s_movk_i32 s7, 0x7800
s_sub_i32 s6, s6, s0
v_lshlrev_b32_e32 v2, 2, v0
s_mul_i32 s0, s6, s10
v_and_b32_e32 v8, s7, v1
v_or_b32_e32 v9, s0, v4
v_lshlrev_b32_e32 v5, 1, v0
v_and_b32_e32 v3, 0x3c0, v0
s_mov_b32 s12, 0x32000
s_mov_b32 s11, 0x8000
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, s13, s14, v2
s_mul_i32 s0, s1, s12
v_or_b32_e32 v1, s11, v5
v_add_co_ci_u32_e64 v7, s13, s15, 0, s13
v_cmp_gt_i32_e32 vcc_lo, 0xc0, v0
v_lshl_or_b32 v3, v3, 1, s11
v_lshlrev_b32_e32 v4, 3, v4
v_or_b32_e32 v5, 0x807e, v5
v_add3_u32 v8, v9, s0, v8
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v12, 0
s_mov_b64 s[14:15], 0
s_branch BB47_2
BB47_1:
s_or_b32 exec_lo, exec_lo, s13
s_waitcnt lgkmcnt(0)
s_barrier
ds_read_b128 v[18:21], v3
ds_read2_b32 v[62:63], v4 offset1:1
ds_read_b128 v[22:25], v3 offset:640
ds_read_b128 v[26:29], v3 offset:1280
ds_read_b128 v[30:33], v3 offset:1920
ds_read2st64_b64 v[34:37], v4 offset0:1 offset1:2
ds_read_b128 v[38:41], v3 offset:16
ds_read2st64_b64 v[42:45], v4 offset0:3 offset1:4
ds_read2st64_b64 v[46:49], v4 offset0:5 offset1:6
ds_read_b128 v[50:53], v3 offset:656
ds_read_b128 v[54:57], v3 offset:1296
ds_read_b128 v[58:61], v3 offset:1936
v_add_nc_u32_e32 v8, 64, v8
s_add_u32 s14, s14, s11
s_addc_u32 s15, s15, 0
s_cmp_eq_u32 s14, 0x100000
s_waitcnt lgkmcnt(10)
v_pk_fma_f16 v9, v18, v62, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v18, v63, v11 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(9)
v_pk_fma_f16 v12, v22, v62, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v22, v63, v17 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(8)
v_pk_fma_f16 v15, v26, v62, v15 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(6)
v_pk_fma_f16 v9, v18, v34, v9 op_sel:[1,0,0]
v_pk_fma_f16 v11, v18, v35, v11 op_sel:[1,0,0]
v_pk_fma_f16 v14, v26, v63, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v30, v63, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v22, v34, v12 op_sel:[1,0,0]
v_pk_fma_f16 v9, v19, v36, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v19, v37, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v30, v62, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v22, v35, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v26, v34, v15 op_sel:[1,0,0]
v_pk_fma_f16 v14, v26, v35, v14 op_sel:[1,0,0]
v_pk_fma_f16 v12, v23, v36, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v30, v35, v10 op_sel:[1,0,0]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v9, v19, v42, v9 op_sel:[1,0,0]
v_pk_fma_f16 v11, v19, v43, v11 op_sel:[1,0,0]
v_pk_fma_f16 v13, v30, v34, v13 op_sel:[1,0,0]
v_pk_fma_f16 v16, v23, v37, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v27, v36, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v27, v37, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v31, v37, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v23, v42, v12 op_sel:[1,0,0]
v_pk_fma_f16 v9, v20, v44, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v20, v45, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v31, v36, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v23, v43, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v27, v42, v15 op_sel:[1,0,0]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v18, v20, v46, v9 op_sel:[1,0,0]
v_pk_fma_f16 v14, v27, v43, v14 op_sel:[1,0,0]
v_pk_fma_f16 v17, v31, v43, v10 op_sel:[1,0,0]
v_pk_fma_f16 v19, v24, v44, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v20, v47, v11 op_sel:[1,0,0]
ds_read2st64_b64 v[9:12], v4 offset0:7 offset1:8
v_pk_fma_f16 v16, v24, v45, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v28, v44, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v24, v46, v19 op_sel:[1,0,0]
v_pk_fma_f16 v13, v31, v42, v13 op_sel:[1,0,0]
v_pk_fma_f16 v14, v28, v45, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v24, v47, v16 op_sel:[1,0,0]
v_pk_fma_f16 v23, v28, v46, v15 op_sel:[1,0,0]
v_pk_fma_f16 v26, v25, v48, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v32, v44, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v28, v47, v14 op_sel:[1,0,0]
ds_read2st64_b64 v[13:16], v4 offset0:9 offset1:10
v_pk_fma_f16 v18, v21, v48, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v21, v49, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v32, v45, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v32, v46, v19 op_sel:[1,0,0]
v_pk_fma_f16 v27, v25, v49, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v29, v48, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v29, v49, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v32, v47, v17 op_sel:[1,0,0]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v34, v21, v9, v18 op_sel:[1,0,0]
v_pk_fma_f16 v35, v21, v10, v20 op_sel:[1,0,0]
v_pk_fma_f16 v36, v25, v10, v27 op_sel:[1,0,0]
v_pk_fma_f16 v26, v25, v9, v26 op_sel:[1,0,0]
v_pk_fma_f16 v31, v33, v48, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v38, v11, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v38, v12, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v29, v9, v28 op_sel:[1,0,0]
v_pk_fma_f16 v32, v33, v49, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v33, v9, v31 op_sel:[1,0,0]
v_pk_fma_f16 v29, v29, v10, v30 op_sel:[1,0,0]
v_pk_fma_f16 v30, v50, v11, v26 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v34, v38, v14, v27 op_sel:[1,0,0]
v_pk_fma_f16 v31, v38, v13, v25 op_sel:[1,0,0]
ds_read_b128 v[17:20], v3 offset:32
ds_read_b128 v[21:24], v3 offset:48
ds_read2st64_b64 v[25:28], v4 offset0:11 offset1:12
v_pk_fma_f16 v30, v50, v13, v30 op_sel:[1,0,0]
v_pk_fma_f16 v35, v50, v12, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v33, v10, v32 op_sel:[1,0,0]
v_pk_fma_f16 v33, v39, v15, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v54, v12, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v51, v15, v30 op_sel_hi:[0,1,1]
ds_read2st64_b64 v[29:32], v4 offset0:13 offset1:14
v_pk_fma_f16 v37, v54, v11, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v58, v11, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v58, v12, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v39, v16, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v54, v14, v38 op_sel:[1,0,0]
v_pk_fma_f16 v11, v54, v13, v37 op_sel:[1,0,0]
v_pk_fma_f16 v9, v58, v13, v9 op_sel:[1,0,0]
v_pk_fma_f16 v35, v50, v14, v35 op_sel:[1,0,0]
v_pk_fma_f16 v10, v58, v14, v10 op_sel:[1,0,0]
v_pk_fma_f16 v12, v55, v16, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v55, v15, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v59, v15, v9 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v13, v39, v25, v33 op_sel:[1,0,0]
v_pk_fma_f16 v14, v39, v26, v34 op_sel:[1,0,0]
v_pk_fma_f16 v15, v51, v25, v36 op_sel:[1,0,0]
v_pk_fma_f16 v33, v55, v25, v11 op_sel:[1,0,0]
v_pk_fma_f16 v35, v51, v16, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v40, v27, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v59, v16, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v40, v28, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v55, v26, v12 op_sel:[1,0,0]
v_pk_fma_f16 v16, v51, v26, v35 op_sel:[1,0,0]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v12, v40, v29, v13 op_sel:[1,0,0]
v_pk_fma_f16 v13, v59, v25, v9 op_sel:[1,0,0]
v_pk_fma_f16 v25, v59, v26, v10 op_sel:[1,0,0]
v_pk_fma_f16 v15, v52, v27, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v40, v30, v11 op_sel:[1,0,0]
v_pk_fma_f16 v34, v41, v31, v12 op_sel_hi:[0,1,1]
ds_read2st64_b64 v[9:12], v4 offset0:15 offset1:16
v_pk_fma_f16 v14, v56, v28, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v52, v29, v15 op_sel:[1,0,0]
v_pk_fma_f16 v35, v41, v32, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v56, v27, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v52, v28, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v60, v27, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v53, v31, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v60, v28, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v56, v29, v26 op_sel:[1,0,0]
v_pk_fma_f16 v33, v52, v30, v16 op_sel:[1,0,0]
v_pk_fma_f16 v39, v56, v30, v14 op_sel:[1,0,0]
v_pk_fma_f16 v29, v60, v29, v13 op_sel:[1,0,0]
ds_read_b128 v[13:16], v3 offset:672
ds_read2st64_b64 v[25:28], v4 offset0:17 offset1:18
v_pk_fma_f16 v30, v60, v30, v38 op_sel:[1,0,0]
v_pk_fma_f16 v33, v53, v32, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v57, v32, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v57, v31, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v39, v61, v31, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v42, v61, v32, v30 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v40, v41, v9, v34 op_sel:[1,0,0]
v_pk_fma_f16 v41, v41, v10, v35 op_sel:[1,0,0]
v_pk_fma_f16 v43, v53, v9, v36 op_sel:[1,0,0]
v_pk_fma_f16 v44, v53, v10, v33 op_sel:[1,0,0]
ds_read_b128 v[29:32], v3 offset:1312
ds_read_b128 v[33:36], v3 offset:1952
v_pk_fma_f16 v45, v17, v11, v40 op_sel_hi:[0,1,1]
v_pk_fma_f16 v41, v17, v12, v41 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v57, v10, v38 op_sel:[1,0,0]
v_pk_fma_f16 v10, v61, v10, v42 op_sel:[1,0,0]
v_pk_fma_f16 v49, v57, v9, v37 op_sel:[1,0,0]
v_pk_fma_f16 v9, v61, v9, v39 op_sel:[1,0,0]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v43, v13, v11, v43 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v45, v17, v25, v45 op_sel:[1,0,0]
v_pk_fma_f16 v17, v17, v26, v41 op_sel:[1,0,0]
v_pk_fma_f16 v46, v13, v12, v44 op_sel_hi:[0,1,1]
ds_read_b128 v[37:40], v3 offset:688
v_pk_fma_f16 v47, v13, v25, v43 op_sel:[1,0,0]
ds_read2st64_b64 v[41:44], v4 offset0:19 offset1:20
v_pk_fma_f16 v53, v18, v27, v45 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v13, v26, v46 op_sel:[1,0,0]
v_pk_fma_f16 v17, v18, v28, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v54, v14, v27, v47 op_sel_hi:[0,1,1]
ds_read_b128 v[45:48], v3 offset:1328
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v55, v29, v11, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v56, v29, v12, v50 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v57, v33, v11, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v58, v33, v12, v10 op_sel_hi:[0,1,1]
ds_read2st64_b64 v[9:12], v4 offset0:21 offset1:22
v_pk_fma_f16 v55, v29, v25, v55 op_sel:[1,0,0]
v_pk_fma_f16 v29, v29, v26, v56 op_sel:[1,0,0]
v_pk_fma_f16 v25, v33, v25, v57 op_sel:[1,0,0]
v_pk_fma_f16 v26, v33, v26, v58 op_sel:[1,0,0]
v_pk_fma_f16 v13, v14, v28, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v30, v27, v55 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v30, v28, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v34, v27, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v55, v34, v28, v26 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v26, v18, v41, v53 op_sel:[1,0,0]
v_pk_fma_f16 v17, v18, v42, v17 op_sel:[1,0,0]
v_pk_fma_f16 v18, v14, v41, v54 op_sel:[1,0,0]
v_pk_fma_f16 v13, v14, v42, v13 op_sel:[1,0,0]
v_pk_fma_f16 v14, v30, v41, v33 op_sel:[1,0,0]
v_pk_fma_f16 v26, v19, v43, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v19, v44, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v15, v43, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v30, v42, v29 op_sel:[1,0,0]
v_pk_fma_f16 v30, v34, v41, v25 op_sel:[1,0,0]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v33, v19, v9, v26 op_sel:[1,0,0]
ds_read2st64_b64 v[25:28], v4 offset0:23 offset1:24
v_pk_fma_f16 v17, v19, v10, v17 op_sel:[1,0,0]
v_pk_fma_f16 v13, v15, v44, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v34, v42, v55 op_sel:[1,0,0]
v_pk_fma_f16 v18, v15, v9, v18 op_sel:[1,0,0]
v_pk_fma_f16 v14, v31, v43, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v20, v11, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v15, v10, v13 op_sel:[1,0,0]
v_pk_fma_f16 v19, v35, v44, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v16, v11, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v31, v44, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v35, v43, v30 op_sel_hi:[0,1,1]
ds_read2st64_b64 v[41:44], v4 offset0:25 offset1:26
v_pk_fma_f16 v14, v31, v9, v14 op_sel:[1,0,0]
v_pk_fma_f16 v17, v20, v12, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v31, v10, v18 op_sel:[1,0,0]
v_pk_fma_f16 v9, v35, v9, v29 op_sel:[1,0,0]
v_pk_fma_f16 v10, v35, v10, v19 op_sel:[1,0,0]
v_pk_fma_f16 v14, v32, v11, v14 op_sel_hi:[0,1,1]
ds_read_b128 v[49:52], v3 offset:1968
v_pk_fma_f16 v13, v16, v12, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v36, v11, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v36, v12, v10 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v10, v20, v25, v33 op_sel:[1,0,0]
v_pk_fma_f16 v11, v20, v26, v17 op_sel:[1,0,0]
v_pk_fma_f16 v18, v32, v12, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v16, v25, v15 op_sel:[1,0,0]
v_pk_fma_f16 v13, v16, v26, v13 op_sel:[1,0,0]
v_pk_fma_f16 v10, v21, v27, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v21, v28, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v32, v26, v18 op_sel:[1,0,0]
v_pk_fma_f16 v17, v37, v27, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v36, v25, v9 op_sel:[1,0,0]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v18, v21, v41, v10 op_sel:[1,0,0]
v_pk_fma_f16 v20, v21, v42, v11 op_sel:[1,0,0]
ds_read2st64_b64 v[9:12], v4 offset0:27 offset1:28
v_pk_fma_f16 v14, v32, v25, v14 op_sel:[1,0,0]
v_pk_fma_f16 v13, v37, v28, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v36, v26, v19 op_sel:[1,0,0]
v_pk_fma_f16 v26, v45, v28, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v37, v41, v17 op_sel:[1,0,0]
v_pk_fma_f16 v25, v45, v27, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v37, v42, v13 op_sel:[1,0,0]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v27, v49, v27, v16 op_sel_hi:[0,1,1]
ds_read2st64_b64 v[13:16], v4 offset0:29 offset1:30
v_pk_fma_f16 v18, v22, v43, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v22, v44, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v38, v43, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v49, v28, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v45, v41, v25 op_sel:[1,0,0]
v_pk_fma_f16 v26, v45, v42, v26 op_sel:[1,0,0]
v_pk_fma_f16 v27, v49, v41, v27 op_sel:[1,0,0]
v_pk_fma_f16 v21, v38, v44, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v49, v42, v19 op_sel:[1,0,0]
v_pk_fma_f16 v25, v46, v43, v25 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v18, v22, v9, v18 op_sel:[1,0,0]
v_pk_fma_f16 v20, v22, v10, v20 op_sel:[1,0,0]
v_pk_fma_f16 v17, v38, v9, v17 op_sel:[1,0,0]
v_pk_fma_f16 v26, v46, v44, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v50, v43, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v23, v11, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v50, v44, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v23, v12, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v39, v11, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v46, v9, v25 op_sel:[1,0,0]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v18, v23, v13, v18 op_sel:[1,0,0]
v_pk_fma_f16 v25, v46, v10, v26 op_sel:[1,0,0]
v_pk_fma_f16 v21, v38, v10, v21 op_sel:[1,0,0]
v_pk_fma_f16 v23, v23, v14, v20 op_sel:[1,0,0]
v_pk_fma_f16 v26, v39, v13, v17 op_sel:[1,0,0]
v_pk_fma_f16 v9, v50, v9, v27 op_sel:[1,0,0]
v_pk_fma_f16 v10, v50, v10, v19 op_sel:[1,0,0]
v_pk_fma_f16 v33, v24, v15, v18 op_sel_hi:[0,1,1]
ds_read2st64_b64 v[17:20], v4 offset0:31 offset1:32
v_pk_fma_f16 v21, v39, v12, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v47, v11, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v40, v15, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v47, v12, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v51, v11, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v51, v12, v10 op_sel_hi:[0,1,1]
ds_read_b128 v[9:12], v3 offset:64
v_pk_fma_f16 v22, v47, v13, v22 op_sel:[1,0,0]
v_pk_fma_f16 v21, v39, v14, v21 op_sel:[1,0,0]
v_pk_fma_f16 v35, v47, v14, v25 op_sel:[1,0,0]
v_pk_fma_f16 v13, v51, v13, v26 op_sel:[1,0,0]
v_pk_fma_f16 v14, v51, v14, v27 op_sel:[1,0,0]
ds_read_b128 v[25:28], v3 offset:704
ds_read2st64_b64 v[29:32], v4 offset0:33 offset1:34
v_pk_fma_f16 v23, v24, v16, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v40, v16, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v48, v15, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v48, v16, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v52, v15, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v41, v52, v16, v14 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v38, v24, v17, v33 op_sel:[1,0,0]
v_pk_fma_f16 v42, v40, v17, v34 op_sel:[1,0,0]
v_pk_fma_f16 v39, v24, v18, v23 op_sel:[1,0,0]
ds_read_b128 v[13:16], v3 offset:1344
v_pk_fma_f16 v49, v48, v17, v22 op_sel:[1,0,0]
v_pk_fma_f16 v50, v48, v18, v35 op_sel:[1,0,0]
v_pk_fma_f16 v43, v40, v18, v21 op_sel:[1,0,0]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v44, v9, v19, v38 op_sel_hi:[0,1,1]
ds_read_b128 v[21:24], v3 offset:1984
ds_read_b128 v[33:36], v3 offset:80
v_pk_fma_f16 v45, v9, v20, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v52, v18, v41 op_sel:[1,0,0]
v_pk_fma_f16 v17, v52, v17, v37 op_sel:[1,0,0]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v42, v25, v19, v42 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v44, v9, v29, v44 op_sel:[1,0,0]
v_pk_fma_f16 v9, v9, v30, v45 op_sel:[1,0,0]
v_pk_fma_f16 v45, v25, v20, v43 op_sel_hi:[0,1,1]
ds_read_b128 v[37:40], v3 offset:720
v_pk_fma_f16 v46, v25, v29, v42 op_sel:[1,0,0]
v_pk_fma_f16 v53, v10, v31, v44 op_sel_hi:[0,1,1]
ds_read2st64_b64 v[41:44], v4 offset0:35 offset1:36
v_pk_fma_f16 v25, v25, v30, v45 op_sel:[1,0,0]
v_pk_fma_f16 v9, v10, v32, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v54, v26, v31, v46 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v55, v13, v19, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v56, v13, v20, v50 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v26, v32, v25 op_sel_hi:[0,1,1]
ds_read_b128 v[45:48], v3 offset:1360
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v57, v21, v19, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v58, v21, v20, v18 op_sel_hi:[0,1,1]
ds_read2st64_b64 v[17:20], v4 offset0:37 offset1:38
v_pk_fma_f16 v55, v13, v29, v55 op_sel:[1,0,0]
v_pk_fma_f16 v13, v13, v30, v56 op_sel:[1,0,0]
v_pk_fma_f16 v29, v21, v29, v57 op_sel:[1,0,0]
v_pk_fma_f16 v21, v21, v30, v58 op_sel:[1,0,0]
ds_read_b128 v[49:52], v3 offset:2000
v_pk_fma_f16 v30, v14, v31, v55 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v14, v32, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v22, v31, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v22, v32, v21 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v31, v10, v41, v53 op_sel:[1,0,0]
v_pk_fma_f16 v9, v10, v42, v9 op_sel:[1,0,0]
v_pk_fma_f16 v10, v26, v41, v54 op_sel:[1,0,0]
v_pk_fma_f16 v25, v26, v42, v25 op_sel:[1,0,0]
v_pk_fma_f16 v26, v14, v41, v30 op_sel:[1,0,0]
v_pk_fma_f16 v30, v11, v43, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v14, v42, v13 op_sel:[1,0,0]
v_pk_fma_f16 v14, v22, v41, v29 op_sel:[1,0,0]
v_pk_fma_f16 v9, v11, v44, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v22, v42, v21 op_sel:[1,0,0]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v41, v11, v17, v30 op_sel:[1,0,0]
ds_read2st64_b64 v[29:32], v4 offset0:39 offset1:40
v_pk_fma_f16 v10, v27, v43, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v11, v18, v9 op_sel:[1,0,0]
v_pk_fma_f16 v11, v27, v44, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v15, v43, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v15, v44, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v23, v43, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v12, v19, v41 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v23, v44, v21 op_sel_hi:[0,1,1]
ds_read2st64_b64 v[41:44], v4 offset0:41 offset1:42
v_pk_fma_f16 v10, v27, v17, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v12, v20, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v27, v18, v11 op_sel:[1,0,0]
v_pk_fma_f16 v13, v15, v18, v13 op_sel:[1,0,0]
v_pk_fma_f16 v25, v15, v17, v25 op_sel:[1,0,0]
v_pk_fma_f16 v15, v23, v18, v21 op_sel:[1,0,0]
v_pk_fma_f16 v10, v28, v19, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v28, v20, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v23, v17, v14 op_sel:[1,0,0]
v_pk_fma_f16 v17, v16, v19, v25 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v9, v12, v30, v9 op_sel:[1,0,0]
v_pk_fma_f16 v18, v12, v29, v22 op_sel:[1,0,0]
v_pk_fma_f16 v13, v16, v20, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v28, v29, v10 op_sel:[1,0,0]
v_pk_fma_f16 v11, v28, v30, v11 op_sel:[1,0,0]
v_pk_fma_f16 v9, v33, v32, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v33, v31, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v24, v19, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v24, v20, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v16, v29, v17 op_sel:[1,0,0]
v_pk_fma_f16 v13, v16, v30, v13 op_sel:[1,0,0]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v16, v33, v41, v12 op_sel:[1,0,0]
v_pk_fma_f16 v18, v37, v31, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v33, v42, v9 op_sel:[1,0,0]
v_pk_fma_f16 v20, v37, v32, v11 op_sel_hi:[0,1,1]
ds_read2st64_b64 v[9:12], v4 offset0:43 offset1:44
v_pk_fma_f16 v21, v34, v43, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v24, v29, v14 op_sel:[1,0,0]
v_pk_fma_f16 v15, v24, v30, v15 op_sel:[1,0,0]
v_pk_fma_f16 v16, v37, v41, v18 op_sel:[1,0,0]
v_pk_fma_f16 v13, v45, v32, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v34, v44, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v37, v42, v20 op_sel:[1,0,0]
v_pk_fma_f16 v17, v45, v31, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v38, v43, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v49, v31, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v49, v32, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v45, v42, v13 op_sel:[1,0,0]
ds_read2st64_b64 v[13:16], v4 offset0:45 offset1:46
v_pk_fma_f16 v17, v45, v41, v17 op_sel:[1,0,0]
v_pk_fma_f16 v19, v38, v44, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v49, v41, v22 op_sel:[1,0,0]
v_pk_fma_f16 v23, v49, v42, v23 op_sel:[1,0,0]
v_pk_fma_f16 v24, v46, v44, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v46, v43, v17 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v18, v34, v10, v18 op_sel:[1,0,0]
v_pk_fma_f16 v20, v38, v9, v20 op_sel:[1,0,0]
v_pk_fma_f16 v19, v38, v10, v19 op_sel:[1,0,0]
v_pk_fma_f16 v21, v34, v9, v21 op_sel:[1,0,0]
v_pk_fma_f16 v25, v46, v9, v17 op_sel:[1,0,0]
v_pk_fma_f16 v22, v50, v43, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v50, v44, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v39, v12, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v35, v11, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v35, v12, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v39, v11, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v50, v9, v22 op_sel:[1,0,0]
v_pk_fma_f16 v24, v46, v10, v24 op_sel:[1,0,0]
v_pk_fma_f16 v10, v50, v10, v23 op_sel:[1,0,0]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v21, v35, v13, v17 op_sel:[1,0,0]
v_pk_fma_f16 v22, v35, v14, v18 op_sel:[1,0,0]
v_pk_fma_f16 v23, v39, v13, v20 op_sel:[1,0,0]
v_pk_fma_f16 v26, v39, v14, v19 op_sel:[1,0,0]
ds_read2st64_b64 v[17:20], v4 offset0:47 offset1:48
v_pk_fma_f16 v25, v47, v11, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v36, v15, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v36, v16, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v40, v16, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v40, v15, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v47, v12, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v51, v11, v9 op_sel_hi:[0,1,1]
ds_read_b128 v[21:24], v3 offset:96
v_pk_fma_f16 v25, v47, v13, v25 op_sel:[1,0,0]
v_pk_fma_f16 v27, v51, v12, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v47, v14, v26 op_sel:[1,0,0]
v_pk_fma_f16 v13, v51, v13, v9 op_sel:[1,0,0]
ds_read2st64_b64 v[9:12], v4 offset0:49 offset1:50
v_pk_fma_f16 v34, v48, v15, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v51, v14, v27 op_sel:[1,0,0]
ds_read_b128 v[25:28], v3 offset:736
v_pk_fma_f16 v37, v48, v16, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v52, v15, v13 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v41, v36, v17, v29 op_sel:[1,0,0]
v_pk_fma_f16 v39, v52, v16, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v43, v40, v17, v31 op_sel:[1,0,0]
v_pk_fma_f16 v44, v40, v18, v32 op_sel:[1,0,0]
v_pk_fma_f16 v42, v36, v18, v30 op_sel:[1,0,0]
ds_read_b128 v[13:16], v3 offset:1376
v_pk_fma_f16 v49, v48, v17, v34 op_sel:[1,0,0]
ds_read_b128 v[29:32], v3 offset:2016
ds_read2_b64 v[33:36], v3 offset0:14 offset1:15
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v40, v21, v19, v41 op_sel_hi:[0,1,1]
v_pk_fma_f16 v41, v21, v20, v42 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v48, v18, v37 op_sel:[1,0,0]
v_pk_fma_f16 v17, v52, v17, v38 op_sel:[1,0,0]
v_pk_fma_f16 v18, v52, v18, v39 op_sel:[1,0,0]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v42, v21, v9, v40 op_sel:[1,0,0]
v_pk_fma_f16 v21, v21, v10, v41 op_sel:[1,0,0]
ds_read_b128 v[37:40], v3 offset:752
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v45, v25, v19, v43 op_sel_hi:[0,1,1]
v_pk_fma_f16 v46, v25, v20, v44 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v22, v11, v42 op_sel_hi:[0,1,1]
ds_read2st64_b64 v[41:44], v4 offset0:51 offset1:52
v_pk_fma_f16 v21, v22, v12, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v54, v25, v9, v45 op_sel:[1,0,0]
v_pk_fma_f16 v25, v25, v10, v46 op_sel:[1,0,0]
ds_read_b128 v[45:48], v3 offset:1392
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v55, v13, v19, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v56, v13, v20, v50 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v57, v29, v19, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v58, v29, v20, v18 op_sel_hi:[0,1,1]
ds_read2st64_b64 v[17:20], v4 offset0:53 offset1:54
v_pk_fma_f16 v55, v13, v9, v55 op_sel:[1,0,0]
v_pk_fma_f16 v13, v13, v10, v56 op_sel:[1,0,0]
v_pk_fma_f16 v9, v29, v9, v57 op_sel:[1,0,0]
v_pk_fma_f16 v54, v26, v11, v54 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v26, v12, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v55, v14, v11, v55 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v29, v10, v58 op_sel:[1,0,0]
v_pk_fma_f16 v9, v30, v11, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v14, v12, v13 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v11, v22, v41, v53 op_sel:[1,0,0]
v_pk_fma_f16 v21, v22, v42, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v30, v12, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v26, v42, v25 op_sel:[1,0,0]
v_pk_fma_f16 v10, v26, v41, v54 op_sel:[1,0,0]
v_pk_fma_f16 v11, v23, v43, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v23, v44, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v14, v41, v55 op_sel:[1,0,0]
v_pk_fma_f16 v13, v14, v42, v13 op_sel:[1,0,0]
v_pk_fma_f16 v14, v30, v41, v9 op_sel:[1,0,0]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v26, v23, v17, v11 op_sel:[1,0,0]
v_pk_fma_f16 v21, v23, v18, v21 op_sel:[1,0,0]
v_pk_fma_f16 v23, v27, v43, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v27, v44, v12 op_sel_hi:[0,1,1]
ds_read2st64_b64 v[9:12], v4 offset0:55 offset1:56
v_pk_fma_f16 v22, v30, v42, v22 op_sel:[1,0,0]
v_pk_fma_f16 v25, v15, v43, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v15, v44, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v31, v43, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v27, v17, v23 op_sel:[1,0,0]
v_pk_fma_f16 v22, v31, v44, v22 op_sel_hi:[0,1,1]
ds_read2st64_b64 v[41:44], v4 offset0:57 offset1:58
v_pk_fma_f16 v26, v24, v19, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v31, v17, v14 op_sel:[1,0,0]
v_pk_fma_f16 v25, v15, v17, v25 op_sel:[1,0,0]
v_pk_fma_f16 v27, v27, v18, v29 op_sel:[1,0,0]
v_pk_fma_f16 v13, v15, v18, v13 op_sel:[1,0,0]
v_pk_fma_f16 v17, v31, v18, v22 op_sel:[1,0,0]
v_pk_fma_f16 v21, v24, v20, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v16, v19, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v28, v20, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v28, v19, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v32, v19, v14 op_sel_hi:[0,1,1]
ds_read_b128 v[49:52], v3 offset:2032
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v19, v24, v9, v26 op_sel:[1,0,0]
v_pk_fma_f16 v22, v28, v10, v15 op_sel:[1,0,0]
v_pk_fma_f16 v13, v16, v20, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v32, v20, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v24, v10, v21 op_sel:[1,0,0]
v_pk_fma_f16 v15, v33, v11, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v28, v9, v23 op_sel:[1,0,0]
v_pk_fma_f16 v18, v16, v9, v18 op_sel:[1,0,0]
v_pk_fma_f16 v19, v16, v10, v13 op_sel:[1,0,0]
v_pk_fma_f16 v9, v32, v9, v14 op_sel:[1,0,0]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v23, v33, v41, v15 op_sel:[1,0,0]
v_pk_fma_f16 v20, v33, v12, v20 op_sel_hi:[0,1,1]
ds_read2st64_b64 v[13:16], v4 offset0:59 offset1:60
v_pk_fma_f16 v10, v32, v10, v17 op_sel:[1,0,0]
v_pk_fma_f16 v18, v45, v11, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v45, v12, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v33, v42, v20 op_sel:[1,0,0]
v_pk_fma_f16 v20, v37, v12, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v34, v43, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v45, v41, v18 op_sel:[1,0,0]
v_pk_fma_f16 v21, v37, v11, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v34, v44, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v37, v42, v20 op_sel:[1,0,0]
ds_read2st64_b64 v[17:20], v4 offset0:61 offset1:62
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v9, v49, v11, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v49, v12, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v45, v42, v25 op_sel:[1,0,0]
v_pk_fma_f16 v11, v38, v44, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v46, v43, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v37, v41, v21 op_sel:[1,0,0]
v_pk_fma_f16 v25, v49, v41, v9 op_sel:[1,0,0]
v_pk_fma_f16 v26, v49, v42, v10 op_sel:[1,0,0]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v22, v34, v13, v22 op_sel:[1,0,0]
v_pk_fma_f16 v23, v34, v14, v23 op_sel:[1,0,0]
ds_read_u16 v27, v5
ds_read_b64 v[9:10], v4 offset:32256
v_pk_fma_f16 v21, v38, v43, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v46, v44, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v35, v15, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v35, v16, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v50, v43, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v50, v44, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v38, v13, v21 op_sel:[1,0,0]
v_pk_fma_f16 v11, v38, v14, v11 op_sel:[1,0,0]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v22, v35, v17, v22 op_sel:[1,0,0]
v_pk_fma_f16 v23, v35, v18, v23 op_sel:[1,0,0]
v_pk_fma_f16 v28, v46, v14, v12 op_sel:[1,0,0]
v_pk_fma_f16 v14, v50, v14, v26 op_sel:[1,0,0]
v_pk_fma_f16 v24, v46, v13, v24 op_sel:[1,0,0]
v_pk_fma_f16 v13, v50, v13, v25 op_sel:[1,0,0]
v_pk_fma_f16 v12, v39, v15, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v36, v19, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v36, v20, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v39, v16, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v51, v15, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v51, v16, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v39, v17, v12 op_sel:[1,0,0]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v12, v27, v9, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v39, v18, v23 op_sel:[1,0,0]
v_pk_fma_f16 v23, v47, v15, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v47, v16, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v51, v17, v13 op_sel:[1,0,0]
v_pk_fma_f16 v14, v51, v18, v14 op_sel:[1,0,0]
v_pk_fma_f16 v15, v40, v20, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v47, v17, v23 op_sel:[1,0,0]
v_pk_fma_f16 v23, v47, v18, v24 op_sel:[1,0,0]
v_pk_fma_f16 v13, v52, v19, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v27, v10, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v40, v19, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v48, v19, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v48, v20, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v52, v20, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v40, v10, v15 op_sel:[1,0,0]
v_pk_fma_f16 v16, v40, v9, v22 op_sel:[1,0,0]
v_pk_fma_f16 v15, v48, v9, v18 op_sel:[1,0,0]
v_pk_fma_f16 v14, v48, v10, v21 op_sel:[1,0,0]
v_pk_fma_f16 v13, v52, v9, v13 op_sel:[1,0,0]
v_pk_fma_f16 v10, v52, v10, v19 op_sel:[1,0,0]
s_cbranch_scc1 BB47_4
BB47_2:
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[18:19], 1, v[8:9]
v_add_co_u32 v20, s0, s8, v18
v_add_co_ci_u32_e64 v21, s0, s9, v19, s0
v_add_co_u32 v22, s0, 0x19000, v20
v_add_co_ci_u32_e64 v23, s0, 0, v21, s0
v_add_co_u32 v24, s0, s12, v20
v_add_co_ci_u32_e64 v25, s0, 0, v21, s0
v_add_co_u32 v18, s0, v6, s14
v_add_co_ci_u32_e64 v19, s0, s15, v7, s0
v_add_co_u32 v26, s0, 0x4b000, v20
v_add_co_ci_u32_e64 v27, s0, 0, v21, s0
v_add_co_u32 v28, s0, 0x800, v18
s_clause 0x1
global_load_dword v9, v[18:19], off
global_load_dword v38, v[18:19], off offset:1280
v_add_co_ci_u32_e64 v29, s0, 0, v19, s0
v_add_co_u32 v30, s0, 0x1000, v18
v_add_co_ci_u32_e64 v31, s0, 0, v19, s0
v_add_co_u32 v32, s0, 0x1800, v18
v_add_co_ci_u32_e64 v33, s0, 0, v19, s0
v_add_co_u32 v34, s0, 0x2000, v18
v_add_co_ci_u32_e64 v35, s0, 0, v19, s0
v_add_co_u32 v36, s0, s10, v18
v_add_co_ci_u32_e64 v37, s0, 0, v19, s0
s_clause 0x7
global_load_dword v39, v[28:29], off offset:512
global_load_dword v40, v[28:29], off offset:1792
global_load_dword v41, v[30:31], off offset:1024
global_load_dword v42, v[32:33], off offset:256
global_load_dword v43, v[32:33], off offset:1536
global_load_dword v44, v[34:35], off offset:768
global_load_dword v45, v[36:37], off
global_load_dword v46, v[36:37], off offset:1280
v_add_co_u32 v28, s0, 0x3000, v18
v_add_co_ci_u32_e64 v29, s0, 0, v19, s0
v_add_co_u32 v30, s0, 0x3800, v18
v_add_co_ci_u32_e64 v31, s0, 0, v19, s0
v_add_co_u32 v32, s0, 0x4000, v18
v_add_co_ci_u32_e64 v33, s0, 0, v19, s0
v_add_co_u32 v34, s0, 0x4800, v18
v_add_co_ci_u32_e64 v35, s0, 0, v19, s0
v_add_co_u32 v36, s0, 0x5000, v18
v_add_co_ci_u32_e64 v37, s0, 0, v19, s0
s_clause 0x7
global_load_dword v47, v[28:29], off offset:512
global_load_dword v48, v[28:29], off offset:1792
global_load_dword v49, v[30:31], off offset:1024
global_load_dword v50, v[32:33], off offset:256
global_load_dword v51, v[32:33], off offset:1536
global_load_dword v52, v[34:35], off offset:768
global_load_dword v53, v[36:37], off
global_load_dword v36, v[36:37], off offset:1280
v_add_co_u32 v28, s0, 0x5800, v18
v_add_co_ci_u32_e64 v29, s0, 0, v19, s0
v_add_co_u32 v30, s0, 0x6000, v18
v_add_co_ci_u32_e64 v31, s0, 0, v19, s0
v_add_co_u32 v32, s0, 0x6800, v18
v_add_co_ci_u32_e64 v33, s0, 0, v19, s0
v_add_co_u32 v34, s0, 0x7000, v18
v_add_co_ci_u32_e64 v35, s0, 0, v19, s0
s_clause 0x5
global_load_dword v37, v[28:29], off offset:512
global_load_dword v54, v[28:29], off offset:1792
global_load_dword v30, v[30:31], off offset:1024
global_load_dword v31, v[32:33], off offset:256
global_load_dword v32, v[32:33], off offset:1536
global_load_dword v33, v[34:35], off offset:768
v_add_co_u32 v28, s0, s7, v18
v_add_co_ci_u32_e64 v29, s0, 0, v19, s0
s_clause 0x3
global_load_ushort v20, v[20:21], off
global_load_ushort v21, v[22:23], off
global_load_ushort v22, v[24:25], off
global_load_ushort v23, v[26:27], off
global_load_dword v24, v[28:29], off
s_waitcnt vmcnt(0)
s_barrier
ds_write2st64_b32 v2, v9, v38 offset1:5
ds_write2st64_b32 v2, v39, v40 offset0:10 offset1:15
ds_write2st64_b32 v2, v41, v42 offset0:20 offset1:25
ds_write2st64_b32 v2, v43, v44 offset0:30 offset1:35
ds_write2st64_b32 v2, v45, v46 offset0:40 offset1:45
ds_write2st64_b32 v2, v47, v48 offset0:50 offset1:55
ds_write2st64_b32 v2, v49, v50 offset0:60 offset1:65
ds_write2st64_b32 v2, v51, v52 offset0:70 offset1:75
ds_write2st64_b32 v2, v53, v36 offset0:80 offset1:85
ds_write2st64_b32 v2, v37, v54 offset0:90 offset1:95
ds_write2st64_b32 v2, v30, v31 offset0:100 offset1:105
ds_write2st64_b32 v2, v32, v33 offset0:110 offset1:115
ds_write_b16 v1, v20
ds_write_b16 v1, v21 offset:640
ds_write_b16 v1, v22 offset:1280
ds_write_b16 v1, v23 offset:1920
ds_write_b32 v2, v24 offset:30720
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz BB47_1
v_add_co_u32 v18, s0, s7, v18
v_add_co_ci_u32_e64 v19, s0, 0, v19, s0
global_load_ushort v9, v[18:19], off offset:1280
s_waitcnt vmcnt(0)
global_load_short_d16_hi v9, v[18:19], off offset:1282
s_waitcnt vmcnt(0)
ds_write_b32 v2, v9 offset:32000
s_branch BB47_1
BB47_4:
v_lshlrev_b32_e32 v1, 3, v0
v_lshlrev_b32_e32 v0, 2, v0
s_mulk_i32 s6, 0x500
s_mulk_i32 s1, 0x6400
v_and_b32_e32 v1, 0x1f8, v1
v_add3_u32 v0, s6, s1, v0
s_clause 0x1
global_load_dword v22, v1, s[4:5]
global_load_dword v23, v1, s[4:5] offset:4
v_add_nc_u32_e32 v2, 0x1900, v0
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v4, 0x1902, v0
v_add_nc_u32_e32 v6, 0x3200, v0
v_add_nc_u32_e32 v8, 0x3202, v0
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v18, 0x4b00, v0
v_add_nc_u32_e32 v20, 0x4b02, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 1, v[2:3]
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v19, 31, v18
v_add_co_u32 v0, vcc_lo, s2, v0
v_lshlrev_b64 v[4:5], 1, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_lshlrev_b64 v[6:7], 1, v[6:7]
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_lshlrev_b64 v[8:9], 1, v[8:9]
v_add_co_u32 v4, vcc_lo, s2, v4
v_ashrrev_i32_e32 v21, 31, v20
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
v_lshlrev_b64 v[18:19], 1, v[18:19]
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s2, v8
v_lshlrev_b64 v[20:21], 1, v[20:21]
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v18, vcc_lo, s2, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
v_add_co_u32 v20, vcc_lo, s2, v20
v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo
s_waitcnt vmcnt(1)
v_pk_add_f16 v12, v22, v12
s_waitcnt vmcnt(0)
v_pk_add_f16 v11, v23, v11
v_pk_add_f16 v16, v22, v16
v_pk_add_f16 v17, v23, v17
v_pk_add_f16 v15, v22, v15
v_pk_add_f16 v14, v23, v14
v_pk_add_f16 v13, v22, v13
v_pk_add_f16 v10, v23, v10
global_store_dword v[0:1], v12, off
global_store_dword v[0:1], v11, off offset:4
global_store_dword v[2:3], v16, off
global_store_dword v[4:5], v17, off
global_store_dword v[6:7], v15, off
global_store_dword v[8:9], v14, off
global_store_dword v[18:19], v13, off
global_store_dword v[20:21], v10, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_4_kernel0
.amdhsa_group_segment_fixed_size 35328
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 64
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end47:
.size tvmgen_default_fused_nn_conv2d_add_4_kernel0, .Lfunc_end47-tvmgen_default_fused_nn_conv2d_add_4_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_add_nn_relu_1_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_add_nn_relu_1_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_add_nn_relu_1_kernel0:
v_lshlrev_b32_e32 v1, 4, v0
s_ashr_i32 s7, s6, 2
s_clause 0x3
s_load_dwordx2 s[10:11], s[4:5], 0x0
s_load_dwordx2 s[12:13], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[8:9], s[4:5], 0x18
s_mul_i32 s0, s7, 0x3200
v_lshlrev_b32_e32 v3, 2, v0
v_and_b32_e32 v2, 0x3f80, v1
s_load_dwordx2 s[4:5], s[4:5], 0x20
v_lshlrev_b32_e32 v41, 3, v0
v_lshrrev_b32_e32 v42, 5, v0
v_or_b32_e32 v4, 2, v3
v_add_nc_u32_e32 v2, s0, v2
v_and_b32_e32 v40, 0x7c, v3
s_lshl_b32 s0, s6, 7
s_movk_i32 s14, 0x4000
s_and_b32 s1, s0, 0x180
v_and_or_b32 v44, v41, 56, v2
v_or_b32_e32 v2, 1, v3
v_or_b32_e32 v3, 3, v3
v_and_b32_e32 v48, 0x7e, v4
v_cmp_gt_i32_e64 s0, 0x80, v0
v_or_b32_e32 v43, s14, v1
v_and_b32_e32 v46, 0x7d, v2
v_mul_u32_u24_e32 v2, 0x500, v42
v_and_b32_e32 v47, 0x3e00, v1
v_and_b32_e32 v49, 0x7f, v3
v_lshlrev_b32_e32 v45, 9, v42
v_mov_b32_e32 v0, 0
v_lshl_add_u32 v50, v2, 1, s14
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v24, 0
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v29, 0
v_mov_b32_e32 v28, 0
v_mov_b32_e32 v31, 0
v_mov_b32_e32 v30, 0
v_mov_b32_e32 v39, 0
v_mov_b32_e32 v37, 0
v_mov_b32_e32 v38, 0
v_mov_b32_e32 v36, 0
v_mov_b32_e32 v35, 0
v_mov_b32_e32 v32, 0
v_mov_b32_e32 v33, 0
v_mov_b32_e32 v34, 0
s_mov_b32 s27, 0
s_mov_b32 s26, -1
s_movk_i32 s6, 0x1000
s_movk_i32 s14, 0x2800
s_movk_i32 s15, 0x3800
s_movk_i32 s16, 0x5000
s_movk_i32 s17, 0x6000
s_movk_i32 s18, 0x7800
s_mov_b32 s19, 0x8800
s_mov_b32 s20, 0xa000
s_mov_b32 s21, 0xb000
s_mov_b32 s22, 0xc800
s_mov_b32 s23, 0xd800
s_mov_b32 s24, 0xf000
s_movk_i32 s25, 0x800
BB48_1:
v_lshl_or_b32 v51, s27, 6, v44
s_lshl_b32 s27, s27, 15
v_or_b32_e32 v53, s27, v45
v_or3_b32 v71, s27, v47, s1
v_ashrrev_i32_e32 v52, 31, v51
v_or3_b32 v53, v53, s1, v40
v_or_b32_e32 v55, v71, v48
v_lshlrev_b64 v[51:52], 1, v[51:52]
v_ashrrev_i32_e32 v54, 31, v53
v_ashrrev_i32_e32 v56, 31, v55
s_waitcnt lgkmcnt(0)
v_add_co_u32 v57, vcc_lo, s10, v51
v_add_co_ci_u32_e32 v58, vcc_lo, s11, v52, vcc_lo
v_lshlrev_b64 v[51:52], 1, v[53:54]
v_lshlrev_b64 v[55:56], 1, v[55:56]
global_load_dwordx4 v[59:62], v[57:58], off
v_add_co_u32 v53, vcc_lo, s12, v51
v_add_co_ci_u32_e32 v54, vcc_lo, s13, v52, vcc_lo
v_add_co_u32 v51, vcc_lo, s12, v55
v_add_co_ci_u32_e32 v52, vcc_lo, s13, v56, vcc_lo
v_add_co_u32 v55, vcc_lo, s6, v53
v_add_co_ci_u32_e32 v56, vcc_lo, 0, v54, vcc_lo
v_add_co_u32 v63, vcc_lo, s6, v51
v_add_co_ci_u32_e32 v64, vcc_lo, 0, v52, vcc_lo
v_add_co_u32 v65, vcc_lo, s14, v53
v_add_co_ci_u32_e32 v66, vcc_lo, 0, v54, vcc_lo
v_add_co_u32 v67, vcc_lo, s14, v51
v_add_co_ci_u32_e32 v68, vcc_lo, 0, v52, vcc_lo
v_add_co_u32 v69, vcc_lo, s15, v53
v_add_co_ci_u32_e32 v70, vcc_lo, 0, v54, vcc_lo
s_clause 0x4
global_load_ushort v75, v[55:56], off offset:1024
global_load_ushort v76, v[63:64], off offset:1024
global_load_ushort v77, v[65:66], off
global_load_ushort v78, v[67:68], off
global_load_ushort v79, v[69:70], off offset:1024
v_add_co_u32 v55, vcc_lo, s15, v51
v_add_co_ci_u32_e32 v56, vcc_lo, 0, v52, vcc_lo
v_add_co_u32 v63, vcc_lo, s16, v53
v_add_co_ci_u32_e32 v64, vcc_lo, 0, v54, vcc_lo
v_add_co_u32 v65, vcc_lo, s16, v51
v_add_co_ci_u32_e32 v66, vcc_lo, 0, v52, vcc_lo
v_add_co_u32 v67, vcc_lo, s17, v53
v_add_co_ci_u32_e32 v68, vcc_lo, 0, v54, vcc_lo
s_clause 0x3
global_load_ushort v80, v[55:56], off offset:1024
global_load_ushort v81, v[63:64], off
global_load_ushort v82, v[65:66], off
global_load_ushort v83, v[67:68], off offset:1024
v_add_co_u32 v55, vcc_lo, s17, v51
v_add_co_ci_u32_e32 v56, vcc_lo, 0, v52, vcc_lo
v_add_co_u32 v63, vcc_lo, s18, v53
v_add_co_ci_u32_e32 v64, vcc_lo, 0, v54, vcc_lo
v_add_co_u32 v65, vcc_lo, s18, v51
v_add_co_ci_u32_e32 v66, vcc_lo, 0, v52, vcc_lo
v_add_co_u32 v67, vcc_lo, s19, v53
v_add_co_ci_u32_e32 v68, vcc_lo, 0, v54, vcc_lo
s_clause 0x3
global_load_ushort v84, v[55:56], off offset:1024
global_load_ushort v85, v[63:64], off
global_load_ushort v86, v[65:66], off
global_load_ushort v87, v[67:68], off offset:1024
v_add_co_u32 v55, vcc_lo, s19, v51
v_add_co_ci_u32_e32 v56, vcc_lo, 0, v52, vcc_lo
v_add_co_u32 v63, vcc_lo, s20, v53
v_add_co_ci_u32_e32 v64, vcc_lo, 0, v54, vcc_lo
v_add_co_u32 v65, vcc_lo, s20, v51
v_add_co_ci_u32_e32 v66, vcc_lo, 0, v52, vcc_lo
v_add_co_u32 v67, vcc_lo, s21, v53
v_add_co_ci_u32_e32 v68, vcc_lo, 0, v54, vcc_lo
s_clause 0x3
global_load_ushort v88, v[55:56], off offset:1024
global_load_ushort v89, v[63:64], off
global_load_ushort v90, v[65:66], off
global_load_ushort v91, v[67:68], off offset:1024
v_add_co_u32 v55, vcc_lo, s21, v51
v_add_co_ci_u32_e32 v56, vcc_lo, 0, v52, vcc_lo
v_add_co_u32 v63, vcc_lo, s22, v53
v_add_co_ci_u32_e32 v64, vcc_lo, 0, v54, vcc_lo
v_add_co_u32 v65, vcc_lo, s22, v51
v_add_co_ci_u32_e32 v66, vcc_lo, 0, v52, vcc_lo
v_add_co_u32 v67, vcc_lo, s23, v53
v_add_co_ci_u32_e32 v68, vcc_lo, 0, v54, vcc_lo
s_clause 0x5
global_load_ushort v92, v[55:56], off offset:1024
global_load_ushort v93, v[63:64], off
global_load_ushort v94, v[65:66], off
global_load_ushort v95, v[67:68], off offset:1024
global_load_ushort v97, v[53:54], off
global_load_ushort v98, v[51:52], off
v_add_co_u32 v55, vcc_lo, s23, v51
v_or_b32_e32 v63, v71, v49
v_add_co_ci_u32_e32 v56, vcc_lo, 0, v52, vcc_lo
v_add_co_u32 v65, vcc_lo, s6, v57
s_waitcnt vmcnt(0)
s_barrier
v_add_co_ci_u32_e32 v66, vcc_lo, 0, v58, vcc_lo
v_add_co_u32 v67, vcc_lo, s14, v57
global_load_ushort v96, v[55:56], off offset:1024
v_or_b32_e32 v55, v71, v46
v_ashrrev_i32_e32 v64, 31, v63
v_add_co_ci_u32_e32 v68, vcc_lo, 0, v58, vcc_lo
v_add_co_u32 v69, vcc_lo, s15, v57
v_ashrrev_i32_e32 v56, 31, v55
v_add_co_ci_u32_e32 v70, vcc_lo, 0, v58, vcc_lo
v_add_co_u32 v71, vcc_lo, s16, v57
v_lshlrev_b64 v[63:64], 1, v[63:64]
v_add_co_ci_u32_e32 v72, vcc_lo, 0, v58, vcc_lo
v_lshlrev_b64 v[55:56], 1, v[55:56]
v_add_co_u32 v55, vcc_lo, s12, v55
v_add_co_ci_u32_e32 v56, vcc_lo, s13, v56, vcc_lo
v_add_co_u32 v57, vcc_lo, s12, v63
v_add_co_ci_u32_e32 v58, vcc_lo, s13, v64, vcc_lo
v_add_co_u32 v73, vcc_lo, s6, v55
global_load_dwordx4 v[63:66], v[65:66], off offset:1024
v_add_co_ci_u32_e32 v74, vcc_lo, 0, v56, vcc_lo
v_add_co_u32 v99, vcc_lo, s6, v57
v_add_co_ci_u32_e32 v100, vcc_lo, 0, v58, vcc_lo
ds_write_b128 v43, v[59:62]
v_add_co_u32 v59, vcc_lo, s14, v55
v_add_co_ci_u32_e32 v60, vcc_lo, 0, v56, vcc_lo
v_add_co_u32 v61, vcc_lo, s14, v57
v_add_co_ci_u32_e32 v62, vcc_lo, 0, v58, vcc_lo
global_load_short_d16_hi v75, v[73:74], off offset:1024
v_add_co_u32 v73, vcc_lo, s15, v55
global_load_short_d16_hi v76, v[99:100], off offset:1024
v_add_co_ci_u32_e32 v74, vcc_lo, 0, v56, vcc_lo
v_add_co_u32 v99, vcc_lo, s15, v57
global_load_short_d16_hi v77, v[59:60], off
v_add_co_ci_u32_e32 v100, vcc_lo, 0, v58, vcc_lo
v_add_co_u32 v59, vcc_lo, s16, v55
global_load_short_d16_hi v78, v[61:62], off
v_add_co_ci_u32_e32 v60, vcc_lo, 0, v56, vcc_lo
v_add_co_u32 v61, vcc_lo, s16, v57
global_load_short_d16_hi v79, v[73:74], off offset:1024
v_add_co_ci_u32_e32 v62, vcc_lo, 0, v58, vcc_lo
v_add_co_u32 v73, vcc_lo, s17, v55
v_add_co_ci_u32_e32 v74, vcc_lo, 0, v56, vcc_lo
global_load_short_d16_hi v80, v[99:100], off offset:1024
v_add_co_u32 v99, vcc_lo, s17, v57
global_load_short_d16_hi v81, v[59:60], off
v_add_co_ci_u32_e32 v100, vcc_lo, 0, v58, vcc_lo
v_add_co_u32 v59, vcc_lo, s18, v55
global_load_short_d16_hi v82, v[61:62], off
v_add_co_ci_u32_e32 v60, vcc_lo, 0, v56, vcc_lo
v_add_co_u32 v61, vcc_lo, s18, v57
global_load_short_d16_hi v83, v[73:74], off offset:1024
v_add_co_ci_u32_e32 v62, vcc_lo, 0, v58, vcc_lo
v_add_co_u32 v73, vcc_lo, s19, v55
v_add_co_ci_u32_e32 v74, vcc_lo, 0, v56, vcc_lo
global_load_short_d16_hi v84, v[99:100], off offset:1024
v_add_co_u32 v99, vcc_lo, s19, v57
global_load_short_d16_hi v85, v[59:60], off
v_add_co_ci_u32_e32 v100, vcc_lo, 0, v58, vcc_lo
v_add_co_u32 v59, vcc_lo, s20, v55
global_load_short_d16_hi v86, v[61:62], off
v_add_co_ci_u32_e32 v60, vcc_lo, 0, v56, vcc_lo
v_add_co_u32 v61, vcc_lo, s20, v57
global_load_short_d16_hi v87, v[73:74], off offset:1024
v_add_co_ci_u32_e32 v62, vcc_lo, 0, v58, vcc_lo
v_add_co_u32 v73, vcc_lo, s21, v55
v_add_co_ci_u32_e32 v74, vcc_lo, 0, v56, vcc_lo
global_load_short_d16_hi v88, v[99:100], off offset:1024
v_add_co_u32 v99, vcc_lo, s21, v57
global_load_short_d16_hi v89, v[59:60], off
v_add_co_ci_u32_e32 v100, vcc_lo, 0, v58, vcc_lo
v_add_co_u32 v59, vcc_lo, s22, v55
global_load_short_d16_hi v90, v[61:62], off
v_add_co_ci_u32_e32 v60, vcc_lo, 0, v56, vcc_lo
v_add_co_u32 v101, vcc_lo, s22, v57
global_load_short_d16_hi v91, v[73:74], off offset:1024
v_add_co_ci_u32_e32 v102, vcc_lo, 0, v58, vcc_lo
v_add_co_u32 v103, vcc_lo, s23, v55
v_add_co_ci_u32_e32 v104, vcc_lo, 0, v56, vcc_lo
s_clause 0x1
global_load_short_d16_hi v92, v[99:100], off offset:1024
global_load_short_d16_hi v93, v[59:60], off
s_clause 0x1
global_load_dwordx4 v[59:62], v[67:68], off
global_load_dwordx4 v[67:70], v[69:70], off offset:1024
global_load_short_d16_hi v94, v[101:102], off
global_load_dwordx4 v[71:74], v[71:72], off
global_load_short_d16_hi v95, v[103:104], off offset:1024
v_add_co_u32 v99, vcc_lo, s23, v57
v_add_nc_u32_e32 v101, 0x1c00, v41
v_add_co_ci_u32_e32 v100, vcc_lo, 0, v58, vcc_lo
s_clause 0x1
global_load_short_d16_hi v97, v[55:56], off
global_load_short_d16_hi v98, v[57:58], off
s_waitcnt vmcnt(27)
global_load_short_d16_hi v96, v[99:100], off offset:1024
v_add_nc_u32_e32 v99, s25, v41
v_add_nc_u32_e32 v100, 0x1400, v41
s_waitcnt vmcnt(27)
ds_write_b128 v43, v[63:66] offset:2560
v_add_nc_u32_e32 v63, s14, v41
v_add_nc_u32_e32 v64, 0x3000, v41
s_waitcnt vmcnt(7)
ds_write_b128 v43, v[59:62] offset:5120
s_waitcnt vmcnt(6)
ds_write_b128 v43, v[67:70] offset:7680
s_waitcnt vmcnt(4)
ds_write_b128 v43, v[71:74] offset:10240
s_waitcnt vmcnt(1)
ds_write2_b64 v41, v[97:98], v[75:76] offset1:160
ds_write2_b64 v99, v[77:78], v[79:80] offset0:64 offset1:224
ds_write2_b64 v100, v[81:82], v[83:84] offset1:160
ds_write2_b64 v101, v[85:86], v[87:88] offset0:64 offset1:224
ds_write2_b64 v63, v[89:90], v[91:92] offset1:160
s_waitcnt vmcnt(0)
ds_write2_b64 v64, v[93:94], v[95:96] offset0:64 offset1:224
s_and_saveexec_b32 s27, s0
s_cbranch_execz BB48_3
v_add_co_u32 v53, vcc_lo, s24, v53
v_add_co_ci_u32_e32 v54, vcc_lo, 0, v54, vcc_lo
v_add_co_u32 v51, vcc_lo, s24, v51
v_add_co_ci_u32_e32 v52, vcc_lo, 0, v52, vcc_lo
s_clause 0x1
global_load_ushort v53, v[53:54], off
global_load_ushort v54, v[51:52], off
v_add_co_u32 v51, vcc_lo, s24, v55
v_add_co_ci_u32_e32 v52, vcc_lo, 0, v56, vcc_lo
v_add_co_u32 v55, vcc_lo, s24, v57
v_add_co_ci_u32_e32 v56, vcc_lo, 0, v58, vcc_lo
s_waitcnt vmcnt(1)
global_load_short_d16_hi v53, v[51:52], off
s_waitcnt vmcnt(1)
global_load_short_d16_hi v54, v[55:56], off
s_waitcnt vmcnt(0)
ds_write_b64 v41, v[53:54] offset:15360
BB48_3:
s_or_b32 exec_lo, exec_lo, s27
v_mov_b32_e32 v51, v50
s_xor_b32 s26, s26, -1
s_mov_b32 s27, 0
s_waitcnt lgkmcnt(0)
s_barrier
BB48_4:
v_or_b32_e32 v84, s27, v40
v_add_nc_u32_e32 v88, s25, v51
ds_read2_b64 v[52:55], v51 offset1:16
ds_read2_b64 v[56:59], v51 offset0:32 offset1:48
ds_read2_b64 v[60:63], v51 offset0:64 offset1:80
ds_read2_b64 v[64:67], v51 offset0:96 offset1:112
ds_read2_b64 v[68:71], v51 offset0:128 offset1:144
ds_read2_b64 v[72:75], v51 offset0:160 offset1:176
ds_read2_b64 v[76:79], v51 offset0:192 offset1:208
ds_read2_b64 v[80:83], v51 offset0:224 offset1:240
v_add_nc_u32_e32 v51, 8, v51
s_addk_i32 s27, 0x200
v_lshlrev_b32_e32 v92, 1, v84
s_cmpk_lg_i32 s27, 0x2000
ds_read2_b64 v[84:87], v88 offset1:16
ds_read2_b64 v[88:91], v88 offset0:32 offset1:48
ds_read2_b32 v[96:97], v92 offset1:1
ds_read_b64 v[98:99], v92 offset:768
ds_read2_b64 v[92:95], v92 offset0:32 offset1:64
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v39, v52, v96, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v52, v97, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v54, v96, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v54, v97, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v56, v96, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v56, v97, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v58, v96, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v58, v97, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v60, v96, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v60, v97, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v62, v96, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v62, v97, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v64, v96, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v64, v97, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v66, v96, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v66, v97, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v68, v96, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v68, v97, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v70, v96, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v70, v97, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v72, v96, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v72, v97, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v74, v96, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v74, v97, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v76, v96, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v76, v97, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v78, v96, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v78, v97, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v80, v96, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v80, v97, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v82, v96, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v82, v97, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v84, v96, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v84, v97, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v86, v96, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v86, v97, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v88, v96, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v88, v97, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v90, v96, v0 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v90, v97, v1 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v39, v52, v92, v39 op_sel:[1,0,0]
v_pk_fma_f16 v37, v52, v93, v37 op_sel:[1,0,0]
v_pk_fma_f16 v38, v54, v92, v38 op_sel:[1,0,0]
v_pk_fma_f16 v36, v54, v93, v36 op_sel:[1,0,0]
v_pk_fma_f16 v35, v56, v92, v35 op_sel:[1,0,0]
v_pk_fma_f16 v32, v56, v93, v32 op_sel:[1,0,0]
v_pk_fma_f16 v33, v58, v92, v33 op_sel:[1,0,0]
v_pk_fma_f16 v34, v58, v93, v34 op_sel:[1,0,0]
v_pk_fma_f16 v31, v60, v92, v31 op_sel:[1,0,0]
v_pk_fma_f16 v30, v60, v93, v30 op_sel:[1,0,0]
v_pk_fma_f16 v29, v62, v92, v29 op_sel:[1,0,0]
v_pk_fma_f16 v28, v62, v93, v28 op_sel:[1,0,0]
v_pk_fma_f16 v27, v64, v92, v27 op_sel:[1,0,0]
v_pk_fma_f16 v26, v64, v93, v26 op_sel:[1,0,0]
v_pk_fma_f16 v24, v66, v92, v24 op_sel:[1,0,0]
v_pk_fma_f16 v25, v66, v93, v25 op_sel:[1,0,0]
v_pk_fma_f16 v23, v68, v92, v23 op_sel:[1,0,0]
v_pk_fma_f16 v22, v68, v93, v22 op_sel:[1,0,0]
v_pk_fma_f16 v21, v70, v92, v21 op_sel:[1,0,0]
v_pk_fma_f16 v20, v70, v93, v20 op_sel:[1,0,0]
v_pk_fma_f16 v19, v72, v92, v19 op_sel:[1,0,0]
v_pk_fma_f16 v18, v72, v93, v18 op_sel:[1,0,0]
v_pk_fma_f16 v17, v74, v92, v17 op_sel:[1,0,0]
v_pk_fma_f16 v16, v74, v93, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v76, v92, v15 op_sel:[1,0,0]
v_pk_fma_f16 v14, v76, v93, v14 op_sel:[1,0,0]
v_pk_fma_f16 v13, v78, v92, v13 op_sel:[1,0,0]
v_pk_fma_f16 v12, v78, v93, v12 op_sel:[1,0,0]
v_pk_fma_f16 v11, v80, v92, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v80, v93, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v82, v92, v9 op_sel:[1,0,0]
v_pk_fma_f16 v8, v82, v93, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v84, v92, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v84, v93, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v86, v92, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v86, v93, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v88, v92, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v88, v93, v2 op_sel:[1,0,0]
v_pk_fma_f16 v0, v90, v92, v0 op_sel:[1,0,0]
v_pk_fma_f16 v1, v90, v93, v1 op_sel:[1,0,0]
v_pk_fma_f16 v39, v53, v94, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v53, v95, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v55, v94, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v55, v95, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v57, v94, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v57, v95, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v59, v94, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v59, v95, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v61, v94, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v61, v95, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v63, v94, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v63, v95, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v65, v94, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v65, v95, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v67, v94, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v67, v95, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v69, v94, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v69, v95, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v71, v94, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v71, v95, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v73, v94, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v73, v95, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v75, v94, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v75, v95, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v77, v94, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v77, v95, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v79, v94, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v79, v95, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v81, v94, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v81, v95, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v83, v94, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v83, v95, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v85, v94, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v85, v95, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v87, v94, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v87, v95, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v89, v94, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v89, v95, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v91, v94, v0 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v91, v95, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v39, v53, v98, v39 op_sel:[1,0,0]
v_pk_fma_f16 v37, v53, v99, v37 op_sel:[1,0,0]
v_pk_fma_f16 v38, v55, v98, v38 op_sel:[1,0,0]
v_pk_fma_f16 v36, v55, v99, v36 op_sel:[1,0,0]
v_pk_fma_f16 v35, v57, v98, v35 op_sel:[1,0,0]
v_pk_fma_f16 v32, v57, v99, v32 op_sel:[1,0,0]
v_pk_fma_f16 v33, v59, v98, v33 op_sel:[1,0,0]
v_pk_fma_f16 v34, v59, v99, v34 op_sel:[1,0,0]
v_pk_fma_f16 v31, v61, v98, v31 op_sel:[1,0,0]
v_pk_fma_f16 v30, v61, v99, v30 op_sel:[1,0,0]
v_pk_fma_f16 v29, v63, v98, v29 op_sel:[1,0,0]
v_pk_fma_f16 v28, v63, v99, v28 op_sel:[1,0,0]
v_pk_fma_f16 v27, v65, v98, v27 op_sel:[1,0,0]
v_pk_fma_f16 v26, v65, v99, v26 op_sel:[1,0,0]
v_pk_fma_f16 v24, v67, v98, v24 op_sel:[1,0,0]
v_pk_fma_f16 v25, v67, v99, v25 op_sel:[1,0,0]
v_pk_fma_f16 v23, v69, v98, v23 op_sel:[1,0,0]
v_pk_fma_f16 v22, v69, v99, v22 op_sel:[1,0,0]
v_pk_fma_f16 v21, v71, v98, v21 op_sel:[1,0,0]
v_pk_fma_f16 v20, v71, v99, v20 op_sel:[1,0,0]
v_pk_fma_f16 v19, v73, v98, v19 op_sel:[1,0,0]
v_pk_fma_f16 v18, v73, v99, v18 op_sel:[1,0,0]
v_pk_fma_f16 v17, v75, v98, v17 op_sel:[1,0,0]
v_pk_fma_f16 v16, v75, v99, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v77, v98, v15 op_sel:[1,0,0]
v_pk_fma_f16 v14, v77, v99, v14 op_sel:[1,0,0]
v_pk_fma_f16 v13, v79, v98, v13 op_sel:[1,0,0]
v_pk_fma_f16 v12, v79, v99, v12 op_sel:[1,0,0]
v_pk_fma_f16 v11, v81, v98, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v81, v99, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v83, v98, v9 op_sel:[1,0,0]
v_pk_fma_f16 v8, v83, v99, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v85, v98, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v85, v99, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v87, v98, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v87, v99, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v89, v98, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v89, v99, v2 op_sel:[1,0,0]
v_pk_fma_f16 v0, v91, v98, v0 op_sel:[1,0,0]
v_pk_fma_f16 v1, v91, v99, v1 op_sel:[1,0,0]
s_cbranch_scc1 BB48_4
s_and_b32 vcc_lo, exec_lo, s26
s_mov_b32 s27, 1
s_mov_b32 s26, 0
s_cbranch_vccz BB48_1
s_mul_i32 s7, s7, 0xc800
v_mad_u32_u24 v41, 0x2800, v42, s7
v_or3_b32 v41, v41, s1, v40
v_or_b32_e32 v40, s1, v40
v_ashrrev_i32_e32 v42, 31, v41
v_or_b32_e32 v47, 0x400, v41
v_lshlrev_b32_e32 v40, 1, v40
v_or_b32_e32 v49, 0x401, v41
v_or_b32_e32 v53, 0x600, v41
v_lshlrev_b64 v[43:44], 1, v[41:42]
v_ashrrev_i32_e32 v48, 31, v47
global_load_dword v42, v40, s[8:9]
v_ashrrev_i32_e32 v50, 31, v49
v_or_b32_e32 v55, 0x601, v41
v_ashrrev_i32_e32 v54, 31, v53
v_add_co_u32 v45, vcc_lo, s4, v43
v_or_b32_e32 v57, 0x602, v41
v_add_co_ci_u32_e32 v46, vcc_lo, s5, v44, vcc_lo
v_ashrrev_i32_e32 v56, 31, v55
v_or_b32_e32 v59, 0x603, v41
v_lshlrev_b64 v[53:54], 1, v[53:54]
global_load_dword v40, v40, s[8:9] offset:4
s_clause 0x5
global_load_dword v87, v[45:46], off
global_load_dword v88, v[45:46], off offset:4
global_load_ushort v89, v[45:46], off offset:1024
global_load_ushort v90, v[45:46], off offset:1026
global_load_ushort v91, v[45:46], off offset:1028
global_load_ushort v92, v[45:46], off offset:1030
v_lshlrev_b64 v[45:46], 1, v[47:48]
v_lshlrev_b64 v[47:48], 1, v[49:50]
v_ashrrev_i32_e32 v58, 31, v57
v_add_nc_u32_e32 v61, 0x800, v41
v_lshlrev_b64 v[55:56], 1, v[55:56]
v_ashrrev_i32_e32 v60, 31, v59
v_add_co_u32 v49, vcc_lo, s4, v45
v_add_nc_u32_e32 v63, 0x802, v41
v_add_co_ci_u32_e32 v50, vcc_lo, s5, v46, vcc_lo
v_add_co_u32 v51, vcc_lo, s4, v47
v_lshlrev_b64 v[57:58], 1, v[57:58]
v_add_co_ci_u32_e32 v52, vcc_lo, s5, v48, vcc_lo
v_ashrrev_i32_e32 v62, 31, v61
v_add_nc_u32_e32 v65, 0xa00, v41
v_lshlrev_b64 v[59:60], 1, v[59:60]
s_clause 0x1
global_load_ushort v93, v[49:50], off
global_load_ushort v94, v[51:52], off
v_or_b32_e32 v49, 0x402, v41
v_or_b32_e32 v51, 0x403, v41
v_ashrrev_i32_e32 v64, 31, v63
v_add_nc_u32_e32 v67, 0xa02, v41
v_lshlrev_b64 v[61:62], 1, v[61:62]
v_ashrrev_i32_e32 v50, 31, v49
v_ashrrev_i32_e32 v52, 31, v51
v_ashrrev_i32_e32 v66, 31, v65
v_add_nc_u32_e32 v69, 0xc00, v41
v_lshlrev_b64 v[63:64], 1, v[63:64]
v_lshlrev_b64 v[49:50], 1, v[49:50]
v_lshlrev_b64 v[51:52], 1, v[51:52]
v_ashrrev_i32_e32 v68, 31, v67
v_lshlrev_b64 v[65:66], 1, v[65:66]
v_ashrrev_i32_e32 v70, 31, v69
v_add_co_u32 v71, vcc_lo, s4, v49
v_lshlrev_b64 v[67:68], 1, v[67:68]
v_add_co_ci_u32_e32 v72, vcc_lo, s5, v50, vcc_lo
v_add_co_u32 v73, vcc_lo, s4, v51
v_lshlrev_b64 v[69:70], 1, v[69:70]
v_add_co_ci_u32_e32 v74, vcc_lo, s5, v52, vcc_lo
v_add_co_u32 v75, vcc_lo, s4, v53
v_add_co_ci_u32_e32 v76, vcc_lo, s5, v54, vcc_lo
v_add_co_u32 v77, vcc_lo, s4, v55
v_add_co_ci_u32_e32 v78, vcc_lo, s5, v56, vcc_lo
v_add_co_u32 v79, vcc_lo, s4, v57
s_clause 0x3
global_load_ushort v96, v[71:72], off
global_load_ushort v97, v[73:74], off
global_load_ushort v98, v[75:76], off
global_load_ushort v99, v[77:78], off
v_add_co_ci_u32_e32 v80, vcc_lo, s5, v58, vcc_lo
v_add_co_u32 v81, vcc_lo, s4, v59
v_add_nc_u32_e32 v77, 0x1000, v41
v_add_co_ci_u32_e32 v82, vcc_lo, s5, v60, vcc_lo
v_add_co_u32 v83, vcc_lo, s4, v61
v_add_co_ci_u32_e32 v84, vcc_lo, s5, v62, vcc_lo
v_add_co_u32 v85, vcc_lo, s4, v63
v_add_co_ci_u32_e32 v86, vcc_lo, s5, v64, vcc_lo
v_add_co_u32 v71, vcc_lo, s4, v65
s_clause 0x2
global_load_ushort v100, v[79:80], off
global_load_ushort v101, v[81:82], off
global_load_dword v102, v[83:84], off
v_add_co_ci_u32_e32 v72, vcc_lo, s5, v66, vcc_lo
v_add_co_u32 v73, vcc_lo, s4, v67
v_add_co_ci_u32_e32 v74, vcc_lo, s5, v68, vcc_lo
v_add_co_u32 v75, vcc_lo, s4, v69
v_add_co_ci_u32_e32 v76, vcc_lo, s5, v70, vcc_lo
v_add_co_u32 v43, vcc_lo, s2, v43
s_clause 0x3
global_load_dword v103, v[85:86], off
global_load_dword v104, v[71:72], off
global_load_dword v105, v[73:74], off
global_load_dword v106, v[75:76], off
v_add_co_ci_u32_e32 v44, vcc_lo, s3, v44, vcc_lo
v_add_co_u32 v45, vcc_lo, s2, v45
v_add_nc_u32_e32 v71, 0xc02, v41
v_add_co_ci_u32_e32 v46, vcc_lo, s3, v46, vcc_lo
v_add_co_u32 v47, vcc_lo, s2, v47
v_add_nc_u32_e32 v73, 0xe00, v41
v_add_co_ci_u32_e32 v48, vcc_lo, s3, v48, vcc_lo
v_add_co_u32 v49, vcc_lo, s2, v49
v_ashrrev_i32_e32 v72, 31, v71
v_add_co_ci_u32_e32 v50, vcc_lo, s3, v50, vcc_lo
v_add_co_u32 v51, vcc_lo, s2, v51
v_add_nc_u32_e32 v75, 0xe02, v41
v_add_co_ci_u32_e32 v52, vcc_lo, s3, v52, vcc_lo
v_add_co_u32 v53, vcc_lo, s2, v53
v_lshlrev_b64 v[71:72], 1, v[71:72]
v_add_co_ci_u32_e32 v54, vcc_lo, s3, v54, vcc_lo
v_add_co_u32 v55, vcc_lo, s2, v55
v_ashrrev_i32_e32 v74, 31, v73
v_add_co_ci_u32_e32 v56, vcc_lo, s3, v56, vcc_lo
v_add_co_u32 v57, vcc_lo, s2, v57
v_ashrrev_i32_e32 v76, 31, v75
v_add_co_ci_u32_e32 v58, vcc_lo, s3, v58, vcc_lo
v_add_co_u32 v59, vcc_lo, s2, v59
v_lshlrev_b64 v[73:74], 1, v[73:74]
v_add_co_ci_u32_e32 v60, vcc_lo, s3, v60, vcc_lo
v_add_co_u32 v79, vcc_lo, s4, v71
v_lshlrev_b64 v[75:76], 1, v[75:76]
v_add_co_ci_u32_e32 v80, vcc_lo, s5, v72, vcc_lo
v_add_co_u32 v61, vcc_lo, s2, v61
v_add_nc_u32_e32 v85, 0x1002, v41
v_add_co_ci_u32_e32 v62, vcc_lo, s3, v62, vcc_lo
v_add_co_u32 v81, vcc_lo, s4, v73
v_add_co_ci_u32_e32 v82, vcc_lo, s5, v74, vcc_lo
v_add_co_u32 v83, vcc_lo, s4, v75
v_add_co_ci_u32_e32 v84, vcc_lo, s5, v76, vcc_lo
v_add_co_u32 v63, vcc_lo, s2, v63
v_add_co_ci_u32_e32 v64, vcc_lo, s3, v64, vcc_lo
v_add_co_u32 v65, vcc_lo, s2, v65
v_add_co_ci_u32_e32 v66, vcc_lo, s3, v66, vcc_lo
v_add_co_u32 v67, vcc_lo, s2, v67
v_add_co_ci_u32_e32 v68, vcc_lo, s3, v68, vcc_lo
v_add_co_u32 v69, vcc_lo, s2, v69
v_add_co_ci_u32_e32 v70, vcc_lo, s3, v70, vcc_lo
v_add_co_u32 v71, vcc_lo, s2, v71
v_add_co_ci_u32_e32 v72, vcc_lo, s3, v72, vcc_lo
v_add_co_u32 v73, vcc_lo, s2, v73
v_add_co_ci_u32_e32 v74, vcc_lo, s3, v74, vcc_lo
v_add_co_u32 v75, vcc_lo, s2, v75
v_add_co_ci_u32_e32 v76, vcc_lo, s3, v76, vcc_lo
s_waitcnt vmcnt(20)
v_pk_add_f16 v39, v42, v39
v_pk_add_f16 v38, v42, v38
v_pk_add_f16 v33, v42, v33
v_pk_add_f16 v29, v42, v29
v_pk_add_f16 v24, v42, v24
v_pk_add_f16 v23, v42, v23
v_pk_add_f16 v0, v42, v0
s_waitcnt vmcnt(19)
v_pk_add_f16 v78, v40, v37
s_waitcnt vmcnt(18)
v_pk_add_f16 v39, v87, v39
s_waitcnt vmcnt(16)
v_add_f16_e32 v86, v89, v38
v_pk_add_f16 v36, v40, v36
s_waitcnt vmcnt(15)
v_add_f16_sdwa v38, v90, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_add_f16 v78, v88, v78
v_pk_max_f16 v39, v39, 0
v_max_f16_e32 v86, 0, v86
s_waitcnt vmcnt(14)
v_add_f16_e32 v88, v91, v36
v_max_f16_e32 v38, 0, v38
v_pk_max_f16 v78, v78, 0
global_store_dword v[43:44], v39, off
s_waitcnt vmcnt(13)
v_add_f16_sdwa v36, v92, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_max_f16_e32 v39, 0, v88
v_add_nc_u32_e32 v37, 0x1200, v41
global_store_dword v[43:44], v78, off offset:4
global_store_short v[43:44], v86, off offset:1024
v_pk_add_f16 v78, v42, v35
global_store_short v[43:44], v38, off offset:1026
global_store_short v[43:44], v39, off offset:1028
v_ashrrev_i32_e32 v86, 31, v85
v_add_nc_u32_e32 v87, 0x1202, v41
v_ashrrev_i32_e32 v38, 31, v37
s_waitcnt vmcnt(12)
v_add_f16_e32 v39, v93, v78
s_waitcnt vmcnt(11)
v_add_f16_sdwa v94, v94, v78 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_ashrrev_i32_e32 v78, 31, v77
v_max_f16_e32 v36, 0, v36
v_add_nc_u32_e32 v89, 0x1400, v41
v_max_f16_e32 v39, 0, v39
v_lshlrev_b64 v[85:86], 1, v[85:86]
v_lshlrev_b64 v[77:78], 1, v[77:78]
v_ashrrev_i32_e32 v88, 31, v87
v_max_f16_e32 v94, 0, v94
v_add_nc_u32_e32 v91, 0x1402, v41
global_store_short v[43:44], v36, off offset:1030
global_store_short v[45:46], v39, off
v_add_co_u32 v45, vcc_lo, s4, v77
v_lshlrev_b64 v[37:38], 1, v[37:38]
v_ashrrev_i32_e32 v90, 31, v89
v_add_nc_u32_e32 v35, 0x1600, v41
v_add_co_ci_u32_e32 v46, vcc_lo, s5, v78, vcc_lo
global_store_short v[47:48], v94, off
v_add_co_u32 v47, vcc_lo, s4, v85
v_lshlrev_b64 v[87:88], 1, v[87:88]
v_ashrrev_i32_e32 v92, 31, v91
v_add_co_ci_u32_e32 v48, vcc_lo, s5, v86, vcc_lo
v_add_co_u32 v94, vcc_lo, s4, v37
v_lshlrev_b64 v[89:90], 1, v[89:90]
v_ashrrev_i32_e32 v36, 31, v35
v_add_nc_u32_e32 v43, 0x1602, v41
v_add_co_ci_u32_e32 v95, vcc_lo, s5, v38, vcc_lo
s_clause 0x1
global_load_dword v39, v[79:80], off
global_load_dword v81, v[81:82], off
v_add_co_u32 v79, vcc_lo, s4, v87
v_lshlrev_b64 v[91:92], 1, v[91:92]
v_add_co_ci_u32_e32 v80, vcc_lo, s5, v88, vcc_lo
s_clause 0x1
global_load_dword v82, v[83:84], off
global_load_dword v83, v[45:46], off
v_add_co_u32 v45, vcc_lo, s4, v89
v_lshlrev_b64 v[35:36], 1, v[35:36]
v_ashrrev_i32_e32 v44, 31, v43
v_add_co_ci_u32_e32 v46, vcc_lo, s5, v90, vcc_lo
s_clause 0x1
global_load_dword v84, v[47:48], off
global_load_dword v95, v[94:95], off
v_add_co_u32 v47, vcc_lo, s4, v91
v_add_nc_u32_e32 v93, 0x1800, v41
v_add_co_ci_u32_e32 v48, vcc_lo, s5, v92, vcc_lo
s_clause 0x1
global_load_dword v107, v[79:80], off
global_load_dword v108, v[45:46], off
v_add_co_u32 v45, vcc_lo, s4, v35
v_lshlrev_b64 v[43:44], 1, v[43:44]
v_add_co_ci_u32_e32 v46, vcc_lo, s5, v36, vcc_lo
v_ashrrev_i32_e32 v94, 31, v93
v_pk_add_f16 v32, v40, v32
v_pk_add_f16 v34, v40, v34
s_clause 0x1
global_load_dword v109, v[47:48], off
global_load_dword v110, v[45:46], off
v_add_co_u32 v45, vcc_lo, s4, v43
v_lshlrev_b64 v[47:48], 1, v[93:94]
v_add_co_ci_u32_e32 v46, vcc_lo, s5, v44, vcc_lo
s_waitcnt vmcnt(18)
v_add_f16_e32 v80, v98, v33
v_add_f16_sdwa v79, v97, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
s_waitcnt vmcnt(15)
v_add_f16_sdwa v98, v101, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_add_f16_e32 v97, v100, v34
global_load_dword v93, v[45:46], off
v_add_co_u32 v45, vcc_lo, s4, v47
v_pk_add_f16 v30, v40, v30
v_add_co_ci_u32_e32 v46, vcc_lo, s5, v48, vcc_lo
v_pk_add_f16 v28, v40, v28
s_waitcnt vmcnt(13)
v_pk_add_f16 v101, v104, v29
v_pk_add_f16 v26, v40, v26
v_pk_add_f16 v100, v103, v30
global_load_dword v94, v[45:46], off
v_pk_add_f16 v45, v42, v31
v_add_f16_e32 v46, v96, v32
v_add_f16_sdwa v96, v99, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_add_nc_u32_e32 v31, 0x1802, v41
v_add_nc_u32_e32 v33, 0x1a00, v41
v_pk_add_f16 v99, v42, v27
v_pk_add_f16 v45, v102, v45
s_waitcnt vmcnt(13)
v_pk_add_f16 v28, v105, v28
v_ashrrev_i32_e32 v32, 31, v31
v_ashrrev_i32_e32 v34, 31, v33
v_add_nc_u32_e32 v27, 0x1a02, v41
v_pk_max_f16 v45, v45, 0
v_pk_max_f16 v28, v28, 0
v_lshlrev_b64 v[29:30], 1, v[31:32]
v_lshlrev_b64 v[31:32], 1, v[33:34]
s_waitcnt vmcnt(12)
v_pk_add_f16 v33, v106, v99
v_max_f16_e32 v34, 0, v46
v_max_f16_e32 v46, 0, v79
v_max_f16_e32 v79, 0, v80
v_max_f16_e32 v80, 0, v96
v_max_f16_e32 v96, 0, v97
v_pk_max_f16 v33, v33, 0
v_max_f16_e32 v97, 0, v98
v_pk_max_f16 v98, v100, 0
v_pk_max_f16 v99, v101, 0
global_store_short v[49:50], v34, off
global_store_short v[51:52], v46, off
global_store_short v[53:54], v79, off
global_store_short v[55:56], v80, off
global_store_short v[57:58], v96, off
global_store_short v[59:60], v97, off
global_store_dword v[61:62], v45, off
global_store_dword v[63:64], v98, off
global_store_dword v[65:66], v99, off
global_store_dword v[67:68], v28, off
global_store_dword v[69:70], v33, off
v_add_nc_u32_e32 v33, 0x1c00, v41
v_ashrrev_i32_e32 v28, 31, v27
v_add_nc_u32_e32 v49, 0x1c02, v41
v_add_nc_u32_e32 v53, 0x1e00, v41
v_add_co_u32 v45, vcc_lo, s4, v29
v_ashrrev_i32_e32 v34, 31, v33
v_lshlrev_b64 v[27:28], 1, v[27:28]
v_ashrrev_i32_e32 v50, 31, v49
v_add_co_ci_u32_e32 v46, vcc_lo, s5, v30, vcc_lo
v_add_nc_u32_e32 v57, 0x1e02, v41
v_add_co_u32 v51, vcc_lo, s4, v31
v_lshlrev_b64 v[33:34], 1, v[33:34]
v_ashrrev_i32_e32 v54, 31, v53
v_add_co_ci_u32_e32 v52, vcc_lo, s5, v32, vcc_lo
v_add_co_u32 v55, vcc_lo, s4, v27
v_lshlrev_b64 v[49:50], 1, v[49:50]
v_ashrrev_i32_e32 v58, 31, v57
v_add_co_ci_u32_e32 v56, vcc_lo, s5, v28, vcc_lo
v_add_co_u32 v59, vcc_lo, s4, v33
v_lshlrev_b64 v[53:54], 1, v[53:54]
v_add_co_ci_u32_e32 v60, vcc_lo, s5, v34, vcc_lo
v_add_co_u32 v61, vcc_lo, s4, v49
v_add_nc_u32_e32 v63, 0x2000, v41
v_lshlrev_b64 v[57:58], 1, v[57:58]
v_add_co_ci_u32_e32 v62, vcc_lo, s5, v50, vcc_lo
v_add_co_u32 v65, vcc_lo, s4, v53
s_clause 0x1
global_load_dword v96, v[45:46], off
global_load_dword v97, v[51:52], off
v_add_nc_u32_e32 v45, 0x2002, v41
v_ashrrev_i32_e32 v64, 31, v63
v_add_co_ci_u32_e32 v66, vcc_lo, s5, v54, vcc_lo
v_add_co_u32 v51, vcc_lo, s4, v57
v_add_nc_u32_e32 v67, 0x2200, v41
v_ashrrev_i32_e32 v46, 31, v45
v_add_co_ci_u32_e32 v52, vcc_lo, s5, v58, vcc_lo
s_clause 0x4
global_load_dword v98, v[55:56], off
global_load_dword v99, v[59:60], off
global_load_dword v100, v[61:62], off
global_load_dword v101, v[65:66], off
global_load_dword v102, v[51:52], off
v_add_nc_u32_e32 v51, 0x2202, v41
v_lshlrev_b64 v[63:64], 1, v[63:64]
v_ashrrev_i32_e32 v68, 31, v67
v_lshlrev_b64 v[45:46], 1, v[45:46]
v_add_nc_u32_e32 v65, 0x2400, v41
v_ashrrev_i32_e32 v52, 31, v51
v_add_nc_u32_e32 v69, 0x2402, v41
v_add_co_u32 v55, vcc_lo, s4, v63
v_lshlrev_b64 v[59:60], 1, v[67:68]
v_add_co_ci_u32_e32 v56, vcc_lo, s5, v64, vcc_lo
v_add_co_u32 v61, vcc_lo, s4, v45
v_lshlrev_b64 v[51:52], 1, v[51:52]
v_ashrrev_i32_e32 v66, 31, v65
v_add_co_ci_u32_e32 v62, vcc_lo, s5, v46, vcc_lo
v_add_co_u32 v67, vcc_lo, s4, v59
v_ashrrev_i32_e32 v70, 31, v69
v_add_co_ci_u32_e32 v68, vcc_lo, s5, v60, vcc_lo
v_add_co_u32 v79, vcc_lo, s4, v51
v_lshlrev_b64 v[65:66], 1, v[65:66]
v_add_co_ci_u32_e32 v80, vcc_lo, s5, v52, vcc_lo
v_pk_add_f16 v22, v40, v22
s_clause 0x3
global_load_dword v103, v[55:56], off
global_load_dword v104, v[61:62], off
global_load_dword v105, v[67:68], off
global_load_dword v79, v[79:80], off
v_lshlrev_b64 v[55:56], 1, v[69:70]
v_pk_add_f16 v20, v40, v20
v_add_co_u32 v61, vcc_lo, s4, v65
v_pk_add_f16 v18, v40, v18
v_add_co_ci_u32_e32 v62, vcc_lo, s5, v66, vcc_lo
v_pk_add_f16 v16, v40, v16
v_add_co_u32 v67, vcc_lo, s4, v55
v_pk_add_f16 v12, v40, v12
v_add_co_ci_u32_e32 v68, vcc_lo, s5, v56, vcc_lo
v_pk_add_f16 v10, v40, v10
v_pk_add_f16 v8, v40, v8
v_pk_add_f16 v6, v40, v6
s_clause 0x1
global_load_dword v80, v[61:62], off
global_load_dword v106, v[67:68], off
v_add_nc_u32_e32 v61, 0x2600, v41
v_pk_add_f16 v4, v40, v4
v_pk_add_f16 v2, v40, v2
v_ashrrev_i32_e32 v62, 31, v61
v_lshlrev_b64 v[61:62], 1, v[61:62]
v_add_co_u32 v67, vcc_lo, s4, v61
v_add_co_ci_u32_e32 v68, vcc_lo, s5, v62, vcc_lo
global_load_dword v111, v[67:68], off
v_add_nc_u32_e32 v67, 0x2602, v41
v_ashrrev_i32_e32 v68, 31, v67
v_lshlrev_b64 v[67:68], 1, v[67:68]
v_add_co_u32 v69, vcc_lo, s4, v67
v_add_co_ci_u32_e32 v70, vcc_lo, s5, v68, vcc_lo
global_load_dword v41, v[69:70], off
s_waitcnt vmcnt(26)
v_pk_add_f16 v26, v39, v26
s_waitcnt vmcnt(25)
v_pk_add_f16 v39, v81, v24
v_pk_add_f16 v24, v40, v25
s_waitcnt vmcnt(23)
v_pk_add_f16 v69, v83, v23
v_pk_max_f16 v26, v26, 0
v_pk_add_f16 v25, v82, v24
v_add_co_u32 v23, vcc_lo, s2, v77
v_pk_max_f16 v39, v39, 0
v_add_co_ci_u32_e32 v24, vcc_lo, s3, v78, vcc_lo
v_pk_max_f16 v69, v69, 0
v_pk_max_f16 v25, v25, 0
global_store_dword v[71:72], v26, off
global_store_dword v[73:74], v39, off
global_store_dword v[75:76], v25, off
global_store_dword v[23:24], v69, off
v_pk_add_f16 v24, v42, v21
s_waitcnt vmcnt(22)
v_pk_add_f16 v23, v84, v22
v_add_co_u32 v21, vcc_lo, s2, v85
v_pk_add_f16 v26, v42, v19
v_add_co_ci_u32_e32 v22, vcc_lo, s3, v86, vcc_lo
s_waitcnt vmcnt(21)
v_pk_add_f16 v25, v95, v24
v_pk_max_f16 v39, v23, 0
v_add_co_u32 v23, vcc_lo, s2, v37
s_waitcnt vmcnt(19)
v_pk_add_f16 v69, v108, v26
v_add_co_ci_u32_e32 v24, vcc_lo, s3, v38, vcc_lo
v_pk_max_f16 v37, v25, 0
v_pk_add_f16 v25, v107, v20
v_add_co_u32 v19, vcc_lo, s2, v87
v_pk_max_f16 v69, v69, 0
v_add_co_ci_u32_e32 v20, vcc_lo, s3, v88, vcc_lo
v_pk_max_f16 v38, v25, 0
v_add_co_u32 v25, vcc_lo, s2, v89
v_add_co_ci_u32_e32 v26, vcc_lo, s3, v90, vcc_lo
global_store_dword v[21:22], v39, off
global_store_dword v[23:24], v37, off
global_store_dword v[19:20], v38, off
global_store_dword v[25:26], v69, off
v_pk_add_f16 v20, v42, v17
s_waitcnt vmcnt(18)
v_pk_add_f16 v19, v109, v18
v_add_co_u32 v17, vcc_lo, s2, v91
v_pk_add_f16 v22, v42, v15
v_add_co_ci_u32_e32 v18, vcc_lo, s3, v92, vcc_lo
s_waitcnt vmcnt(17)
v_pk_add_f16 v21, v110, v20
v_pk_max_f16 v23, v19, 0
v_add_co_u32 v19, vcc_lo, s2, v35
s_waitcnt vmcnt(15)
v_pk_add_f16 v26, v94, v22
v_add_co_ci_u32_e32 v20, vcc_lo, s3, v36, vcc_lo
v_pk_max_f16 v24, v21, 0
v_pk_add_f16 v21, v93, v16
v_add_co_u32 v15, vcc_lo, s2, v43
v_pk_max_f16 v26, v26, 0
global_store_dword v[17:18], v23, off
global_store_dword v[19:20], v24, off
v_pk_add_f16 v17, v40, v14
v_pk_add_f16 v18, v42, v13
v_add_co_ci_u32_e32 v16, vcc_lo, s3, v44, vcc_lo
v_pk_max_f16 v25, v21, 0
v_add_co_u32 v21, vcc_lo, s2, v47
v_add_co_ci_u32_e32 v22, vcc_lo, s3, v48, vcc_lo
v_add_co_u32 v13, vcc_lo, s2, v29
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v30, vcc_lo
s_waitcnt vmcnt(14)
v_pk_add_f16 v19, v96, v17
s_waitcnt vmcnt(13)
v_pk_add_f16 v20, v97, v18
v_add_co_u32 v17, vcc_lo, s2, v31
v_add_co_ci_u32_e32 v18, vcc_lo, s3, v32, vcc_lo
v_pk_max_f16 v19, v19, 0
v_pk_max_f16 v20, v20, 0
global_store_dword v[15:16], v25, off
global_store_dword v[21:22], v26, off
global_store_dword v[13:14], v19, off
global_store_dword v[17:18], v20, off
v_pk_add_f16 v14, v42, v11
s_waitcnt vmcnt(12)
v_pk_add_f16 v13, v98, v12
v_add_co_u32 v11, vcc_lo, s2, v27
v_pk_add_f16 v16, v42, v9
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v28, vcc_lo
s_waitcnt vmcnt(11)
v_pk_add_f16 v15, v99, v14
v_pk_max_f16 v17, v13, 0
v_add_co_u32 v13, vcc_lo, s2, v33
s_waitcnt vmcnt(9)
v_pk_add_f16 v20, v101, v16
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v34, vcc_lo
v_pk_max_f16 v18, v15, 0
v_pk_add_f16 v15, v100, v10
v_add_co_u32 v9, vcc_lo, s2, v49
v_pk_max_f16 v20, v20, 0
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v50, vcc_lo
v_pk_max_f16 v19, v15, 0
v_add_co_u32 v15, vcc_lo, s2, v53
v_add_co_ci_u32_e32 v16, vcc_lo, s3, v54, vcc_lo
global_store_dword v[11:12], v17, off
global_store_dword v[13:14], v18, off
global_store_dword v[9:10], v19, off
global_store_dword v[15:16], v20, off
v_pk_add_f16 v10, v42, v7
s_waitcnt vmcnt(8)
v_pk_add_f16 v9, v102, v8
v_add_co_u32 v7, vcc_lo, s2, v57
v_pk_add_f16 v12, v42, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v58, vcc_lo
s_waitcnt vmcnt(7)
v_pk_add_f16 v11, v103, v10
v_pk_max_f16 v13, v9, 0
v_add_co_u32 v9, vcc_lo, s2, v63
s_waitcnt vmcnt(5)
v_pk_add_f16 v16, v105, v12
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v64, vcc_lo
v_pk_max_f16 v14, v11, 0
v_pk_add_f16 v11, v104, v6
v_add_co_u32 v5, vcc_lo, s2, v45
v_pk_max_f16 v16, v16, 0
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v46, vcc_lo
s_waitcnt vmcnt(2)
v_pk_add_f16 v2, v106, v2
v_pk_max_f16 v15, v11, 0
v_add_co_u32 v11, vcc_lo, s2, v59
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v60, vcc_lo
v_pk_max_f16 v2, v2, 0
global_store_dword v[7:8], v13, off
global_store_dword v[9:10], v14, off
global_store_dword v[5:6], v15, off
global_store_dword v[11:12], v16, off
v_pk_add_f16 v6, v42, v3
v_pk_add_f16 v5, v79, v4
v_add_co_u32 v3, vcc_lo, s2, v51
v_pk_add_f16 v10, v40, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v52, vcc_lo
v_pk_add_f16 v7, v80, v6
v_pk_max_f16 v11, v5, 0
v_add_co_u32 v5, vcc_lo, s2, v65
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v66, vcc_lo
v_pk_max_f16 v12, v7, 0
v_add_co_u32 v7, vcc_lo, s2, v55
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v56, vcc_lo
s_waitcnt vmcnt(1)
v_pk_add_f16 v9, v111, v0
v_add_co_u32 v0, vcc_lo, s2, v61
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v62, vcc_lo
v_pk_max_f16 v13, v9, 0
v_add_co_u32 v9, vcc_lo, s2, v67
s_waitcnt vmcnt(0)
v_pk_add_f16 v14, v41, v10
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v68, vcc_lo
v_pk_max_f16 v14, v14, 0
global_store_dword v[3:4], v11, off
global_store_dword v[5:6], v12, off
global_store_dword v[7:8], v2, off
global_store_dword v[0:1], v13, off
global_store_dword v[9:10], v14, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_add_nn_relu_1_kernel0
.amdhsa_group_segment_fixed_size 29184
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 112
.amdhsa_next_free_sgpr 28
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end48:
.size tvmgen_default_fused_nn_conv2d_add_add_nn_relu_1_kernel0, .Lfunc_end48-tvmgen_default_fused_nn_conv2d_add_add_nn_relu_1_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_add_nn_relu_2_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_add_nn_relu_2_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_add_nn_relu_2_kernel0:
s_clause 0x3
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[8:9], s[4:5], 0x18
s_load_dwordx2 s[12:13], s[4:5], 0x0
s_mul_i32 s0, s6, 0xa00
s_load_dwordx2 s[4:5], s[4:5], 0x20
v_lshl_add_u32 v1, v0, 8, s0
s_movk_i32 s1, 0x2000
v_lshlrev_b32_e32 v31, 4, v0
v_mul_i32_i24_e32 v3, -6, v0
v_cmp_gt_i32_e32 vcc_lo, 10, v0
v_ashrrev_i32_e32 v2, 31, v1
v_lshl_or_b32 v32, v0, 3, s1
v_lshlrev_b32_e32 v42, 1, v0
v_lshl_add_u32 v43, v3, 1, v31
v_mov_b32_e32 v3, 0
v_lshlrev_b64 v[0:1], 1, v[1:2]
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v44, s0, s10, v31
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e64 v45, s0, s11, 0, s0
v_add_co_u32 v46, s0, s12, v0
v_mov_b32_e32 v0, 0
v_add_co_ci_u32_e64 v47, s0, s13, v1, s0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v24, 0
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v28, 0
v_mov_b32_e32 v29, 0
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v30, 0
v_mov_b32_e32 v34, 0
v_mov_b32_e32 v33, 0
v_mov_b32_e32 v35, 0
v_mov_b32_e32 v36, 0
v_mov_b32_e32 v37, 0
v_mov_b32_e32 v38, 0
v_mov_b32_e32 v39, 0
v_mov_b32_e32 v40, 0
v_mov_b32_e32 v41, 0
s_mov_b64 s[10:11], 0
s_branch BB49_2
BB49_1:
s_or_b32 exec_lo, exec_lo, s7
v_add_co_u32 v56, s0, v44, 0x1000
v_mov_b32_e32 v64, 0
v_add_co_ci_u32_e64 v57, s0, 0, v45, s0
v_add_co_u32 v60, s0, 0x1800, v44
s_add_u32 s10, s10, 8
v_add_co_ci_u32_e64 v61, s0, 0, v45, s0
s_addc_u32 s11, s11, 0
s_clause 0x3
global_load_dwordx4 v[48:51], v[44:45], off
global_load_dwordx4 v[52:55], v[56:57], off offset:-2048
global_load_dwordx4 v[56:59], v[56:57], off
global_load_dwordx4 v[60:63], v[60:61], off
v_add_co_u32 v44, s0, v44, s1
s_cmpk_eq_i32 s10, 0x200
v_add_co_ci_u32_e64 v45, s0, 0, v45, s0
s_waitcnt vmcnt(3)
ds_write_b128 v31, v[48:51]
s_waitcnt vmcnt(2)
ds_write_b128 v31, v[52:55] offset:2048
s_waitcnt vmcnt(1)
ds_write_b128 v31, v[56:59] offset:4096
s_waitcnt vmcnt(0)
ds_write_b128 v31, v[60:63] offset:6144
s_waitcnt lgkmcnt(0)
s_barrier
ds_read2st64_b32 v[68:69], v43 offset1:2
ds_read_b128 v[48:51], v64 offset:8192
ds_read_b128 v[52:55], v64 offset:8208
ds_read_b128 v[56:59], v64 offset:8224
ds_read_b128 v[60:63], v64 offset:8240
ds_read2st64_b32 v[70:71], v43 offset0:4 offset1:6
ds_read2st64_b32 v[72:73], v43 offset0:8 offset1:10
ds_read_b128 v[64:67], v64 offset:8256
ds_read2st64_b32 v[74:75], v43 offset0:12 offset1:14
ds_read2st64_b32 v[76:77], v43 offset0:16 offset1:18
ds_read2st64_b32 v[78:79], v43 offset0:20 offset1:22
s_waitcnt lgkmcnt(9)
v_pk_fma_f16 v41, v48, v68, v41 op_sel_hi:[0,1,1]
v_pk_fma_f16 v40, v48, v69, v40 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v50, v68, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v50, v69, v36 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(8)
v_pk_fma_f16 v34, v52, v68, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v52, v69, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v54, v68, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v54, v69, v28 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(7)
v_pk_fma_f16 v26, v56, v68, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v56, v69, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v58, v68, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v58, v69, v18 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(6)
v_pk_fma_f16 v17, v60, v68, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v60, v69, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v62, v68, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v62, v69, v11 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v7, v64, v68, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v64, v69, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v66, v68, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v66, v69, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v39, v48, v70, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v48, v71, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v50, v70, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v50, v71, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v52, v70, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v52, v71, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v54, v70, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v54, v71, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v56, v70, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v56, v71, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v58, v70, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v58, v71, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v60, v70, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v60, v71, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v62, v70, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v62, v71, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v64, v70, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v64, v71, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v66, v70, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v66, v71, v0 op_sel_hi:[0,1,1]
ds_read2st64_b32 v[68:69], v43 offset0:24 offset1:26
ds_read2st64_b32 v[70:71], v43 offset0:28 offset1:30
v_pk_fma_f16 v41, v48, v72, v41 op_sel:[1,0,0]
v_pk_fma_f16 v40, v48, v73, v40 op_sel:[1,0,0]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v39, v48, v74, v39 op_sel:[1,0,0]
v_pk_fma_f16 v38, v48, v75, v38 op_sel:[1,0,0]
v_pk_fma_f16 v37, v50, v72, v37 op_sel:[1,0,0]
v_pk_fma_f16 v36, v50, v73, v36 op_sel:[1,0,0]
v_pk_fma_f16 v35, v50, v74, v35 op_sel:[1,0,0]
v_pk_fma_f16 v33, v50, v75, v33 op_sel:[1,0,0]
v_pk_fma_f16 v34, v52, v72, v34 op_sel:[1,0,0]
v_pk_fma_f16 v30, v52, v73, v30 op_sel:[1,0,0]
v_pk_fma_f16 v27, v52, v74, v27 op_sel:[1,0,0]
v_pk_fma_f16 v25, v52, v75, v25 op_sel:[1,0,0]
v_pk_fma_f16 v29, v54, v72, v29 op_sel:[1,0,0]
v_pk_fma_f16 v28, v54, v73, v28 op_sel:[1,0,0]
v_pk_fma_f16 v23, v54, v74, v23 op_sel:[1,0,0]
v_pk_fma_f16 v22, v54, v75, v22 op_sel:[1,0,0]
v_pk_fma_f16 v26, v56, v72, v26 op_sel:[1,0,0]
v_pk_fma_f16 v24, v56, v73, v24 op_sel:[1,0,0]
v_pk_fma_f16 v19, v58, v72, v19 op_sel:[1,0,0]
v_pk_fma_f16 v18, v58, v73, v18 op_sel:[1,0,0]
v_pk_fma_f16 v17, v60, v72, v17 op_sel:[1,0,0]
v_pk_fma_f16 v16, v60, v73, v16 op_sel:[1,0,0]
v_pk_fma_f16 v12, v62, v72, v12 op_sel:[1,0,0]
v_pk_fma_f16 v11, v62, v73, v11 op_sel:[1,0,0]
v_pk_fma_f16 v7, v64, v72, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v64, v73, v6 op_sel:[1,0,0]
v_pk_fma_f16 v4, v66, v72, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v66, v73, v3 op_sel:[1,0,0]
v_pk_fma_f16 v21, v56, v74, v21 op_sel:[1,0,0]
v_pk_fma_f16 v20, v56, v75, v20 op_sel:[1,0,0]
v_pk_fma_f16 v15, v58, v74, v15 op_sel:[1,0,0]
v_pk_fma_f16 v14, v58, v75, v14 op_sel:[1,0,0]
v_pk_fma_f16 v13, v60, v74, v13 op_sel:[1,0,0]
v_pk_fma_f16 v10, v60, v75, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v62, v74, v9 op_sel:[1,0,0]
v_pk_fma_f16 v8, v62, v75, v8 op_sel:[1,0,0]
v_pk_fma_f16 v5, v64, v74, v5 op_sel:[1,0,0]
v_pk_fma_f16 v2, v64, v75, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v66, v74, v1 op_sel:[1,0,0]
v_pk_fma_f16 v0, v66, v75, v0 op_sel:[1,0,0]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v41, v49, v76, v41 op_sel_hi:[0,1,1]
v_pk_fma_f16 v40, v49, v77, v40 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v39, v49, v78, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v49, v79, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v51, v76, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v51, v77, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v51, v78, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v51, v79, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v53, v76, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v53, v77, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v53, v78, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v53, v79, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v55, v76, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v55, v77, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v55, v78, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v55, v79, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v57, v76, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v57, v77, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v59, v76, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v59, v77, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v61, v76, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v61, v77, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v63, v76, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v63, v77, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v65, v76, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v65, v77, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v67, v76, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v67, v77, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v57, v78, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v57, v79, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v59, v78, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v59, v79, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v61, v78, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v61, v79, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v63, v78, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v63, v79, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v65, v78, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v65, v79, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v67, v78, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v67, v79, v0 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v41, v49, v68, v41 op_sel:[1,0,0]
v_pk_fma_f16 v40, v49, v69, v40 op_sel:[1,0,0]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v39, v49, v70, v39 op_sel:[1,0,0]
v_pk_fma_f16 v38, v49, v71, v38 op_sel:[1,0,0]
v_pk_fma_f16 v37, v51, v68, v37 op_sel:[1,0,0]
v_pk_fma_f16 v36, v51, v69, v36 op_sel:[1,0,0]
v_pk_fma_f16 v35, v51, v70, v35 op_sel:[1,0,0]
v_pk_fma_f16 v33, v51, v71, v33 op_sel:[1,0,0]
v_pk_fma_f16 v34, v53, v68, v34 op_sel:[1,0,0]
v_pk_fma_f16 v30, v53, v69, v30 op_sel:[1,0,0]
v_pk_fma_f16 v27, v53, v70, v27 op_sel:[1,0,0]
v_pk_fma_f16 v25, v53, v71, v25 op_sel:[1,0,0]
v_pk_fma_f16 v29, v55, v68, v29 op_sel:[1,0,0]
v_pk_fma_f16 v28, v55, v69, v28 op_sel:[1,0,0]
v_pk_fma_f16 v23, v55, v70, v23 op_sel:[1,0,0]
v_pk_fma_f16 v22, v55, v71, v22 op_sel:[1,0,0]
v_pk_fma_f16 v26, v57, v68, v26 op_sel:[1,0,0]
v_pk_fma_f16 v24, v57, v69, v24 op_sel:[1,0,0]
v_pk_fma_f16 v21, v57, v70, v21 op_sel:[1,0,0]
v_pk_fma_f16 v20, v57, v71, v20 op_sel:[1,0,0]
v_pk_fma_f16 v19, v59, v68, v19 op_sel:[1,0,0]
v_pk_fma_f16 v18, v59, v69, v18 op_sel:[1,0,0]
v_pk_fma_f16 v15, v59, v70, v15 op_sel:[1,0,0]
v_pk_fma_f16 v14, v59, v71, v14 op_sel:[1,0,0]
v_pk_fma_f16 v17, v61, v68, v17 op_sel:[1,0,0]
v_pk_fma_f16 v16, v61, v69, v16 op_sel:[1,0,0]
v_pk_fma_f16 v13, v61, v70, v13 op_sel:[1,0,0]
v_pk_fma_f16 v10, v61, v71, v10 op_sel:[1,0,0]
v_pk_fma_f16 v12, v63, v68, v12 op_sel:[1,0,0]
v_pk_fma_f16 v11, v63, v69, v11 op_sel:[1,0,0]
v_pk_fma_f16 v9, v63, v70, v9 op_sel:[1,0,0]
v_pk_fma_f16 v8, v63, v71, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v65, v68, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v65, v69, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v65, v70, v5 op_sel:[1,0,0]
v_pk_fma_f16 v2, v65, v71, v2 op_sel:[1,0,0]
v_pk_fma_f16 v4, v67, v68, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v67, v69, v3 op_sel:[1,0,0]
v_pk_fma_f16 v1, v67, v70, v1 op_sel:[1,0,0]
v_pk_fma_f16 v0, v67, v71, v0 op_sel:[1,0,0]
s_cbranch_scc1 BB49_4
BB49_2:
s_barrier
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz BB49_1
v_add_co_u32 v48, s0, v46, s10
v_add_co_ci_u32_e64 v49, s0, s11, v47, s0
global_load_dwordx2 v[48:49], v[48:49], off
s_waitcnt vmcnt(0)
ds_write_b64 v32, v[48:49]
s_branch BB49_1
BB49_4:
s_mulk_i32 s6, 0x2800
v_lshlrev_b32_e32 v68, 1, v42
v_or_b32_e32 v31, s6, v42
global_load_ushort v69, v68, s[8:9]
v_ashrrev_i32_e32 v32, 31, v31
v_or_b32_e32 v46, 1, v31
v_add_nc_u32_e32 v48, 0x400, v31
v_add_nc_u32_e32 v50, 0x500, v31
v_add_nc_u32_e32 v52, 0x600, v31
v_lshlrev_b64 v[42:43], 1, v[31:32]
v_ashrrev_i32_e32 v47, 31, v46
v_ashrrev_i32_e32 v49, 31, v48
v_ashrrev_i32_e32 v51, 31, v50
v_add_nc_u32_e32 v54, 0x700, v31
v_ashrrev_i32_e32 v53, 31, v52
v_add_co_u32 v44, vcc_lo, s4, v42
v_lshlrev_b64 v[46:47], 1, v[46:47]
v_add_co_ci_u32_e32 v45, vcc_lo, s5, v43, vcc_lo
v_add_co_u32 v42, vcc_lo, s2, v42
v_lshlrev_b64 v[48:49], 1, v[48:49]
v_add_co_ci_u32_e32 v43, vcc_lo, s3, v43, vcc_lo
v_add_nc_u32_e32 v56, 0x800, v31
global_load_ushort v70, v[44:45], off
v_add_co_u32 v60, vcc_lo, s4, v46
v_lshlrev_b64 v[50:51], 1, v[50:51]
v_add_co_ci_u32_e32 v61, vcc_lo, s5, v47, vcc_lo
v_add_co_u32 v46, vcc_lo, s2, v46
v_ashrrev_i32_e32 v55, 31, v54
v_add_co_ci_u32_e32 v47, vcc_lo, s3, v47, vcc_lo
v_add_nc_u32_e32 v58, 0x900, v31
v_add_co_u32 v62, vcc_lo, s4, v48
v_lshlrev_b64 v[52:53], 1, v[52:53]
v_ashrrev_i32_e32 v57, 31, v56
v_add_co_ci_u32_e32 v63, vcc_lo, s5, v49, vcc_lo
v_add_co_u32 v64, vcc_lo, s4, v50
v_lshlrev_b64 v[54:55], 1, v[54:55]
v_ashrrev_i32_e32 v59, 31, v58
v_add_co_ci_u32_e32 v65, vcc_lo, s5, v51, vcc_lo
s_clause 0x2
global_load_ushort v71, v[44:45], off offset:512
global_load_ushort v72, v[44:45], off offset:1024
global_load_dword v73, v[44:45], off offset:1536
v_add_co_u32 v44, vcc_lo, s4, v52
v_lshlrev_b64 v[56:57], 1, v[56:57]
v_add_co_ci_u32_e32 v45, vcc_lo, s5, v53, vcc_lo
v_add_co_u32 v66, vcc_lo, s4, v54
v_lshlrev_b64 v[58:59], 1, v[58:59]
v_add_co_ci_u32_e32 v67, vcc_lo, s5, v55, vcc_lo
s_clause 0x3
global_load_ushort v74, v[60:61], off
global_load_ushort v75, v[60:61], off offset:512
global_load_ushort v76, v[60:61], off offset:1024
global_load_dword v63, v[62:63], off
v_add_co_u32 v60, vcc_lo, s4, v56
s_clause 0x1
global_load_dword v64, v[64:65], off
global_load_dword v77, v[44:45], off
v_add_co_ci_u32_e32 v61, vcc_lo, s5, v57, vcc_lo
v_add_co_u32 v44, vcc_lo, s4, v58
v_add_co_ci_u32_e32 v45, vcc_lo, s5, v59, vcc_lo
global_load_dword v78, v[66:67], off
global_load_ushort v62, v68, s[8:9] offset:512
global_load_dword v79, v[60:61], off
global_load_dword v32, v68, s[8:9] offset:1024
global_load_dword v80, v[44:45], off
global_load_dword v81, v68, s[8:9]
v_add_co_u32 v48, vcc_lo, s2, v48
v_add_co_ci_u32_e32 v49, vcc_lo, s3, v49, vcc_lo
v_add_co_u32 v50, vcc_lo, s2, v50
v_add_co_ci_u32_e32 v51, vcc_lo, s3, v51, vcc_lo
v_add_co_u32 v52, vcc_lo, s2, v52
v_add_co_ci_u32_e32 v53, vcc_lo, s3, v53, vcc_lo
v_add_co_u32 v54, vcc_lo, s2, v54
v_add_co_ci_u32_e32 v55, vcc_lo, s3, v55, vcc_lo
s_waitcnt vmcnt(16)
v_add_f16_e32 v44, v69, v41
s_waitcnt vmcnt(15)
v_add_f16_e32 v44, v70, v44
s_clause 0x1
global_load_dword v70, v68, s[8:9] offset:1536
global_load_dword v82, v68, s[8:9] offset:512
v_max_f16_e32 v44, 0, v44
global_store_short v[42:43], v44, off
v_add_nc_u32_e32 v44, 0xc00, v31
s_waitcnt vmcnt(6)
v_add_f16_e32 v45, v62, v40
s_waitcnt vmcnt(4)
v_pk_add_f16 v39, v32, v39
v_pk_add_f16 v35, v32, v35
s_waitcnt vmcnt(2)
v_add_f16_sdwa v41, v81, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
v_add_f16_e32 v45, v71, v45
v_pk_add_f16 v34, v81, v34
v_add_f16_e32 v61, v72, v39
v_add_f16_sdwa v39, v76, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_add_f16_e32 v41, v74, v41
v_max_f16_e32 v45, 0, v45
v_pk_add_f16 v35, v77, v35
v_max_f16_e32 v61, 0, v61
v_max_f16_e32 v39, 0, v39
v_max_f16_e32 v41, 0, v41
v_pk_add_f16 v34, v79, v34
global_store_short v[42:43], v45, off offset:512
global_store_short v[42:43], v61, off offset:1024
v_ashrrev_i32_e32 v45, 31, v44
v_pk_max_f16 v35, v35, 0
v_pk_add_f16 v27, v32, v27
v_pk_max_f16 v34, v34, 0
v_pk_add_f16 v29, v81, v29
v_lshlrev_b64 v[44:45], 1, v[44:45]
v_pk_add_f16 v23, v32, v23
v_pk_add_f16 v26, v81, v26
v_pk_add_f16 v21, v32, v21
v_pk_add_f16 v19, v81, v19
v_pk_add_f16 v15, v32, v15
v_pk_add_f16 v17, v81, v17
v_pk_add_f16 v13, v32, v13
v_pk_add_f16 v7, v81, v7
s_waitcnt vmcnt(1)
v_pk_add_f16 v38, v70, v38
s_waitcnt vmcnt(0)
v_add_f16_sdwa v40, v82, v40 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
v_pk_add_f16 v33, v70, v33
v_pk_add_f16 v30, v82, v30
v_pk_add_f16 v25, v70, v25
v_pk_add_f16 v60, v73, v38
v_add_f16_e32 v62, v75, v40
v_add_nc_u32_e32 v38, 0xa00, v31
v_add_nc_u32_e32 v40, 0xb00, v31
v_pk_add_f16 v33, v78, v33
v_pk_max_f16 v65, v60, 0
v_add_nc_u32_e32 v60, 0xd00, v31
v_pk_add_f16 v30, v80, v30
v_pk_add_f16 v28, v82, v28
v_pk_max_f16 v33, v33, 0
global_store_dword v[42:43], v65, off offset:1536
v_max_f16_e32 v43, 0, v62
global_store_short v[46:47], v41, off
v_pk_add_f16 v41, v82, v36
v_add_nc_u32_e32 v42, 0xe00, v31
v_add_co_u32 v36, vcc_lo, s2, v56
global_store_short v[46:47], v43, off offset:512
global_store_short v[46:47], v39, off offset:1024
v_pk_add_f16 v39, v81, v37
v_pk_add_f16 v67, v64, v41
v_ashrrev_i32_e32 v41, 31, v40
v_ashrrev_i32_e32 v61, 31, v60
v_add_nc_u32_e32 v62, 0xf00, v31
v_pk_add_f16 v66, v63, v39
v_ashrrev_i32_e32 v39, 31, v38
v_lshlrev_b64 v[40:41], 1, v[40:41]
v_add_co_ci_u32_e32 v37, vcc_lo, s3, v57, vcc_lo
v_ashrrev_i32_e32 v43, 31, v42
v_pk_max_f16 v66, v66, 0
v_lshlrev_b64 v[38:39], 1, v[38:39]
v_pk_max_f16 v68, v67, 0
v_add_nc_u32_e32 v46, 0x1000, v31
v_lshlrev_b64 v[60:61], 1, v[60:61]
global_store_dword v[48:49], v66, off
v_ashrrev_i32_e32 v63, 31, v62
v_add_co_u32 v48, vcc_lo, s4, v38
v_add_nc_u32_e32 v56, 0x1100, v31
v_add_co_ci_u32_e32 v49, vcc_lo, s5, v39, vcc_lo
v_add_co_u32 v66, vcc_lo, s4, v40
v_lshlrev_b64 v[42:43], 1, v[42:43]
v_add_co_ci_u32_e32 v67, vcc_lo, s5, v41, vcc_lo
global_store_dword v[50:51], v68, off
v_add_co_u32 v50, vcc_lo, s4, v44
v_ashrrev_i32_e32 v47, 31, v46
v_add_co_ci_u32_e32 v51, vcc_lo, s5, v45, vcc_lo
global_store_dword v[52:53], v35, off
v_add_co_u32 v52, vcc_lo, s4, v60
v_lshlrev_b64 v[62:63], 1, v[62:63]
v_ashrrev_i32_e32 v57, 31, v56
v_add_co_ci_u32_e32 v53, vcc_lo, s5, v61, vcc_lo
v_add_nc_u32_e32 v64, 0x1200, v31
v_add_co_u32 v68, vcc_lo, s4, v42
v_lshlrev_b64 v[46:47], 1, v[46:47]
v_add_co_ci_u32_e32 v69, vcc_lo, s5, v43, vcc_lo
s_clause 0x1
global_load_dword v71, v[48:49], off
global_load_dword v72, v[66:67], off
v_add_co_u32 v48, vcc_lo, s4, v62
v_lshlrev_b64 v[56:57], 1, v[56:57]
v_ashrrev_i32_e32 v65, 31, v64
v_add_co_ci_u32_e32 v49, vcc_lo, s5, v63, vcc_lo
s_clause 0x1
global_load_dword v73, v[50:51], off
global_load_dword v74, v[52:53], off
v_add_co_u32 v50, vcc_lo, s4, v46
v_add_nc_u32_e32 v35, 0x1500, v31
v_add_co_ci_u32_e32 v51, vcc_lo, s5, v47, vcc_lo
s_clause 0x1
global_load_dword v68, v[68:69], off
global_load_dword v69, v[48:49], off
v_add_co_u32 v48, vcc_lo, s4, v56
v_lshlrev_b64 v[52:53], 1, v[64:65]
v_add_co_ci_u32_e32 v49, vcc_lo, s5, v57, vcc_lo
v_pk_max_f16 v30, v30, 0
v_pk_add_f16 v22, v70, v22
v_pk_add_f16 v24, v82, v24
s_clause 0x1
global_load_dword v75, v[50:51], off
global_load_dword v76, v[48:49], off
v_add_co_u32 v48, vcc_lo, s4, v52
global_store_dword v[54:55], v33, off
v_add_co_ci_u32_e32 v49, vcc_lo, s5, v53, vcc_lo
v_add_nc_u32_e32 v33, 0x1400, v31
global_store_dword v[36:37], v34, off
v_ashrrev_i32_e32 v36, 31, v35
v_pk_add_f16 v20, v70, v20
global_load_dword v77, v[48:49], off
v_add_nc_u32_e32 v48, 0x1300, v31
v_ashrrev_i32_e32 v34, 31, v33
v_lshlrev_b64 v[35:36], 1, v[35:36]
v_pk_add_f16 v14, v70, v14
v_pk_add_f16 v16, v82, v16
v_ashrrev_i32_e32 v49, 31, v48
v_lshlrev_b64 v[33:34], 1, v[33:34]
v_pk_add_f16 v10, v70, v10
v_pk_add_f16 v11, v82, v11
v_pk_add_f16 v2, v70, v2
v_lshlrev_b64 v[48:49], 1, v[48:49]
v_pk_add_f16 v3, v82, v3
v_add_co_u32 v50, vcc_lo, s4, v48
v_add_co_ci_u32_e32 v51, vcc_lo, s5, v49, vcc_lo
global_load_dword v83, v[50:51], off
v_add_co_u32 v50, vcc_lo, s2, v58
v_add_co_ci_u32_e32 v51, vcc_lo, s3, v59, vcc_lo
v_add_co_u32 v54, vcc_lo, s4, v33
v_add_co_ci_u32_e32 v55, vcc_lo, s5, v34, vcc_lo
global_store_dword v[50:51], v30, off
v_add_nc_u32_e32 v50, 0x1600, v31
global_load_dword v78, v[54:55], off
v_add_co_u32 v54, vcc_lo, s4, v35
v_add_co_ci_u32_e32 v55, vcc_lo, s5, v36, vcc_lo
v_add_co_u32 v37, vcc_lo, s2, v38
v_ashrrev_i32_e32 v51, 31, v50
v_add_co_ci_u32_e32 v38, vcc_lo, s3, v39, vcc_lo
v_add_co_u32 v39, vcc_lo, s2, v40
global_load_dword v79, v[54:55], off
v_add_co_ci_u32_e32 v40, vcc_lo, s3, v41, vcc_lo
v_add_co_u32 v44, vcc_lo, s2, v44
v_lshlrev_b64 v[50:51], 1, v[50:51]
v_add_co_ci_u32_e32 v45, vcc_lo, s3, v45, vcc_lo
v_add_co_u32 v54, vcc_lo, s2, v60
v_add_co_ci_u32_e32 v55, vcc_lo, s3, v61, vcc_lo
v_add_co_u32 v41, vcc_lo, s2, v42
v_add_co_ci_u32_e32 v42, vcc_lo, s3, v43, vcc_lo
v_add_co_u32 v58, vcc_lo, s2, v62
v_add_co_ci_u32_e32 v59, vcc_lo, s3, v63, vcc_lo
v_add_co_u32 v46, vcc_lo, s2, v46
v_add_co_ci_u32_e32 v47, vcc_lo, s3, v47, vcc_lo
v_add_co_u32 v56, vcc_lo, s2, v56
v_add_co_ci_u32_e32 v57, vcc_lo, s3, v57, vcc_lo
v_add_co_u32 v52, vcc_lo, s2, v52
v_add_co_ci_u32_e32 v53, vcc_lo, s3, v53, vcc_lo
v_add_co_u32 v48, vcc_lo, s2, v48
v_add_co_ci_u32_e32 v49, vcc_lo, s3, v49, vcc_lo
v_add_co_u32 v60, vcc_lo, s4, v50
v_add_co_ci_u32_e32 v61, vcc_lo, s5, v51, vcc_lo
global_load_dword v80, v[60:61], off
v_add_nc_u32_e32 v60, 0x1700, v31
v_ashrrev_i32_e32 v61, 31, v60
v_lshlrev_b64 v[60:61], 1, v[60:61]
v_add_co_u32 v62, vcc_lo, s4, v60
v_add_co_ci_u32_e32 v63, vcc_lo, s5, v61, vcc_lo
global_load_dword v84, v[62:63], off
v_add_nc_u32_e32 v62, 0x1800, v31
v_ashrrev_i32_e32 v63, 31, v62
v_lshlrev_b64 v[62:63], 1, v[62:63]
v_add_co_u32 v64, vcc_lo, s4, v62
v_add_co_ci_u32_e32 v65, vcc_lo, s5, v63, vcc_lo
global_load_dword v85, v[64:65], off
v_add_nc_u32_e32 v64, 0x1900, v31
v_ashrrev_i32_e32 v65, 31, v64
v_lshlrev_b64 v[64:65], 1, v[64:65]
v_add_co_u32 v66, vcc_lo, s4, v64
v_add_co_ci_u32_e32 v67, vcc_lo, s5, v65, vcc_lo
global_load_dword v66, v[66:67], off
s_waitcnt vmcnt(15)
v_pk_add_f16 v27, v71, v27
s_waitcnt vmcnt(14)
v_pk_add_f16 v25, v72, v25
s_waitcnt vmcnt(13)
v_pk_add_f16 v29, v73, v29
s_waitcnt vmcnt(12)
v_pk_add_f16 v28, v74, v28
v_pk_max_f16 v27, v27, 0
v_pk_max_f16 v25, v25, 0
s_waitcnt vmcnt(11)
v_pk_add_f16 v23, v68, v23
s_waitcnt vmcnt(10)
v_pk_add_f16 v22, v69, v22
v_pk_max_f16 v29, v29, 0
v_pk_max_f16 v28, v28, 0
v_pk_max_f16 v23, v23, 0
v_pk_max_f16 v22, v22, 0
s_waitcnt vmcnt(9)
v_pk_add_f16 v26, v75, v26
s_waitcnt vmcnt(8)
v_pk_add_f16 v24, v76, v24
global_store_dword v[37:38], v27, off
global_store_dword v[39:40], v25, off
global_store_dword v[44:45], v29, off
global_store_dword v[54:55], v28, off
global_store_dword v[41:42], v23, off
v_add_nc_u32_e32 v39, 0x1e00, v31
v_add_nc_u32_e32 v41, 0x2000, v31
v_pk_max_f16 v23, v26, 0
v_pk_max_f16 v24, v24, 0
v_ashrrev_i32_e32 v40, 31, v39
s_waitcnt vmcnt(7)
v_pk_add_f16 v21, v77, v21
v_ashrrev_i32_e32 v42, 31, v41
v_lshlrev_b64 v[39:40], 1, v[39:40]
v_pk_max_f16 v21, v21, 0
v_lshlrev_b64 v[41:42], 1, v[41:42]
s_waitcnt vmcnt(6)
v_pk_add_f16 v20, v83, v20
v_pk_max_f16 v20, v20, 0
global_store_dword v[58:59], v22, off
global_store_dword v[46:47], v23, off
global_store_dword v[56:57], v24, off
global_store_dword v[52:53], v21, off
global_store_dword v[48:49], v20, off
v_pk_add_f16 v23, v82, v18
v_add_nc_u32_e32 v18, 0x1a00, v31
v_add_nc_u32_e32 v22, 0x1b00, v31
v_add_co_u32 v20, vcc_lo, s2, v33
s_waitcnt vmcnt(5)
v_pk_add_f16 v28, v78, v19
v_add_co_ci_u32_e32 v21, vcc_lo, s3, v34, vcc_lo
v_ashrrev_i32_e32 v19, 31, v18
v_add_co_u32 v24, vcc_lo, s2, v35
v_add_nc_u32_e32 v35, 0x1d00, v31
v_add_co_ci_u32_e32 v25, vcc_lo, s3, v36, vcc_lo
v_add_co_u32 v26, vcc_lo, s2, v50
v_lshlrev_b64 v[18:19], 1, v[18:19]
s_waitcnt vmcnt(4)
v_pk_add_f16 v29, v79, v23
v_ashrrev_i32_e32 v23, 31, v22
v_add_co_ci_u32_e32 v27, vcc_lo, s3, v51, vcc_lo
v_pk_max_f16 v30, v28, 0
v_add_nc_u32_e32 v28, 0x1c00, v31
v_add_co_u32 v33, vcc_lo, s4, v18
v_lshlrev_b64 v[22:23], 1, v[22:23]
v_add_co_ci_u32_e32 v34, vcc_lo, s5, v19, vcc_lo
v_ashrrev_i32_e32 v36, 31, v35
v_pk_max_f16 v55, v29, 0
v_ashrrev_i32_e32 v29, 31, v28
v_add_nc_u32_e32 v49, 0x2100, v31
v_add_co_u32 v37, vcc_lo, s4, v22
v_add_nc_u32_e32 v53, 0x2200, v31
v_add_co_ci_u32_e32 v38, vcc_lo, s5, v23, vcc_lo
v_lshlrev_b64 v[28:29], 1, v[28:29]
v_ashrrev_i32_e32 v50, 31, v49
s_clause 0x1
global_load_dword v56, v[33:34], off
global_load_dword v57, v[37:38], off
v_lshlrev_b64 v[33:34], 1, v[35:36]
v_add_nc_u32_e32 v35, 0x1f00, v31
v_add_co_u32 v37, vcc_lo, s4, v28
v_ashrrev_i32_e32 v54, 31, v53
v_add_co_ci_u32_e32 v38, vcc_lo, s5, v29, vcc_lo
v_ashrrev_i32_e32 v36, 31, v35
v_add_co_u32 v43, vcc_lo, s4, v33
v_add_co_ci_u32_e32 v44, vcc_lo, s5, v34, vcc_lo
v_add_co_u32 v45, vcc_lo, s4, v39
v_lshlrev_b64 v[35:36], 1, v[35:36]
v_add_co_ci_u32_e32 v46, vcc_lo, s5, v40, vcc_lo
v_add_co_u32 v47, vcc_lo, s4, v35
v_add_co_ci_u32_e32 v48, vcc_lo, s5, v36, vcc_lo
v_add_co_u32 v51, vcc_lo, s4, v41
s_clause 0x3
global_load_dword v58, v[37:38], off
global_load_dword v59, v[43:44], off
global_load_dword v67, v[45:46], off
global_load_dword v68, v[47:48], off
v_lshlrev_b64 v[43:44], 1, v[49:50]
global_store_dword v[20:21], v30, off
v_add_nc_u32_e32 v37, 0x2300, v31
v_lshlrev_b64 v[20:21], 1, v[53:54]
v_add_co_ci_u32_e32 v52, vcc_lo, s5, v42, vcc_lo
v_add_nc_u32_e32 v47, 0x2400, v31
v_add_co_u32 v45, vcc_lo, s4, v43
v_ashrrev_i32_e32 v38, 31, v37
v_add_co_ci_u32_e32 v46, vcc_lo, s5, v44, vcc_lo
global_load_dword v69, v[51:52], off
v_add_co_u32 v49, vcc_lo, s4, v20
v_add_nc_u32_e32 v51, 0x2500, v31
v_ashrrev_i32_e32 v48, 31, v47
v_add_co_ci_u32_e32 v50, vcc_lo, s5, v21, vcc_lo
v_lshlrev_b64 v[37:38], 1, v[37:38]
v_add_nc_u32_e32 v30, 0x2700, v31
v_ashrrev_i32_e32 v52, 31, v51
s_clause 0x1
global_load_dword v71, v[45:46], off
global_load_dword v72, v[49:50], off
v_add_nc_u32_e32 v45, 0x2600, v31
v_lshlrev_b64 v[47:48], 1, v[47:48]
v_add_co_u32 v53, vcc_lo, s4, v37
global_store_dword v[24:25], v55, off
v_lshlrev_b64 v[24:25], 1, v[51:52]
v_ashrrev_i32_e32 v46, 31, v45
v_add_co_ci_u32_e32 v54, vcc_lo, s5, v38, vcc_lo
v_add_co_u32 v49, vcc_lo, s4, v47
v_ashrrev_i32_e32 v31, 31, v30
v_add_co_ci_u32_e32 v50, vcc_lo, s5, v48, vcc_lo
v_add_co_u32 v51, vcc_lo, s4, v24
v_lshlrev_b64 v[45:46], 1, v[45:46]
v_add_co_ci_u32_e32 v52, vcc_lo, s5, v25, vcc_lo
global_load_dword v53, v[53:54], off
v_lshlrev_b64 v[30:31], 1, v[30:31]
s_waitcnt vmcnt(12)
v_pk_add_f16 v55, v84, v14
s_clause 0x1
global_load_dword v54, v[49:50], off
global_load_dword v51, v[51:52], off
v_add_co_u32 v49, vcc_lo, s4, v45
v_add_co_ci_u32_e32 v50, vcc_lo, s5, v46, vcc_lo
v_pk_max_f16 v55, v55, 0
global_load_dword v52, v[49:50], off
v_add_co_u32 v49, vcc_lo, s4, v30
v_add_co_ci_u32_e32 v50, vcc_lo, s5, v31, vcc_lo
v_add_co_u32 v14, vcc_lo, s2, v60
global_load_dword v49, v[49:50], off
v_pk_add_f16 v50, v80, v15
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v61, vcc_lo
v_pk_max_f16 v50, v50, 0
global_store_dword v[26:27], v50, off
global_store_dword v[14:15], v55, off
s_waitcnt vmcnt(15)
v_pk_add_f16 v26, v85, v17
v_add_co_u32 v14, vcc_lo, s2, v62
s_waitcnt vmcnt(14)
v_pk_add_f16 v27, v66, v16
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v63, vcc_lo
v_add_co_u32 v16, vcc_lo, s2, v64
v_pk_max_f16 v26, v26, 0
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v65, vcc_lo
v_pk_max_f16 v27, v27, 0
v_add_co_u32 v18, vcc_lo, s2, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
global_store_dword v[14:15], v26, off
global_store_dword v[16:17], v27, off
s_waitcnt vmcnt(13)
v_pk_add_f16 v13, v56, v13
s_waitcnt vmcnt(12)
v_pk_add_f16 v10, v57, v10
v_pk_max_f16 v15, v13, 0
v_add_co_u32 v13, vcc_lo, s2, v22
v_pk_add_f16 v22, v70, v8
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v23, vcc_lo
global_store_dword v[18:19], v15, off
v_pk_max_f16 v19, v10, 0
v_pk_add_f16 v10, v81, v12
v_add_co_u32 v15, vcc_lo, s2, v28
v_pk_add_f16 v12, v32, v9
v_add_co_ci_u32_e32 v16, vcc_lo, s3, v29, vcc_lo
v_add_co_u32 v17, vcc_lo, s2, v33
v_add_co_ci_u32_e32 v18, vcc_lo, s3, v34, vcc_lo
v_add_co_u32 v8, vcc_lo, s2, v39
s_waitcnt vmcnt(11)
v_pk_add_f16 v23, v58, v10
s_waitcnt vmcnt(10)
v_pk_add_f16 v26, v59, v11
s_waitcnt vmcnt(9)
v_pk_add_f16 v12, v67, v12
s_waitcnt vmcnt(8)
v_pk_add_f16 v22, v68, v22
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v40, vcc_lo
v_pk_max_f16 v23, v23, 0
v_add_co_u32 v10, vcc_lo, s2, v35
v_pk_max_f16 v26, v26, 0
v_pk_max_f16 v12, v12, 0
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v36, vcc_lo
v_pk_max_f16 v22, v22, 0
global_store_dword v[13:14], v19, off
global_store_dword v[15:16], v23, off
global_store_dword v[17:18], v26, off
global_store_dword v[8:9], v12, off
global_store_dword v[10:11], v22, off
v_pk_add_f16 v10, v82, v6
v_pk_add_f16 v11, v32, v5
v_add_co_u32 v8, vcc_lo, s2, v41
s_waitcnt vmcnt(7)
v_pk_add_f16 v7, v69, v7
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v42, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v43
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v44, vcc_lo
s_waitcnt vmcnt(6)
v_pk_add_f16 v12, v71, v10
s_waitcnt vmcnt(5)
v_pk_add_f16 v13, v72, v11
v_add_co_u32 v10, vcc_lo, s2, v20
v_pk_max_f16 v7, v7, 0
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v21, vcc_lo
v_pk_max_f16 v14, v12, 0
v_pk_max_f16 v15, v13, 0
v_add_co_u32 v12, vcc_lo, s2, v37
global_store_dword v[8:9], v7, off
global_store_dword v[5:6], v14, off
global_store_dword v[10:11], v15, off
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v38, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v47
v_pk_add_f16 v10, v70, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v48, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v24
s_waitcnt vmcnt(4)
v_pk_add_f16 v2, v53, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v25, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v45
s_waitcnt vmcnt(2)
v_pk_add_f16 v14, v51, v3
v_pk_max_f16 v9, v2, 0
v_pk_add_f16 v2, v81, v4
v_pk_add_f16 v4, v32, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v46, vcc_lo
v_pk_max_f16 v14, v14, 0
v_pk_add_f16 v11, v54, v2
s_waitcnt vmcnt(1)
v_pk_add_f16 v4, v52, v4
v_add_co_u32 v2, vcc_lo, s2, v30
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v31, vcc_lo
v_pk_max_f16 v11, v11, 0
v_pk_max_f16 v4, v4, 0
s_waitcnt vmcnt(0)
v_pk_add_f16 v10, v49, v10
v_pk_max_f16 v10, v10, 0
global_store_dword v[12:13], v9, off
global_store_dword v[5:6], v11, off
global_store_dword v[7:8], v14, off
global_store_dword v[0:1], v4, off
global_store_dword v[2:3], v10, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_add_nn_relu_2_kernel0
.amdhsa_group_segment_fixed_size 8272
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 86
.amdhsa_next_free_sgpr 14
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end49:
.size tvmgen_default_fused_nn_conv2d_add_add_nn_relu_2_kernel0, .Lfunc_end49-tvmgen_default_fused_nn_conv2d_add_add_nn_relu_2_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_add_nn_relu_3_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_add_nn_relu_3_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_add_nn_relu_3_kernel0:
v_and_b32_e32 v1, 15, v0
s_lshl_b32 s0, s6, 5
v_lshrrev_b32_e32 v25, 4, v0
s_movk_i32 s7, 0x1000
v_lshlrev_b32_e32 v30, 4, v0
v_and_or_b32 v2, 0xfffffe00, s0, v1
s_clause 0x4
s_load_dwordx2 s[10:11], s[4:5], 0x0
s_load_dwordx2 s[12:13], s[4:5], 0x8
s_load_dwordx2 s[0:1], s[4:5], 0x10
s_load_dwordx2 s[8:9], s[4:5], 0x18
s_load_dwordx2 s[2:3], s[4:5], 0x20
v_lshl_or_b32 v26, v0, 1, s7
v_lshlrev_b32_e32 v27, 3, v1
v_lshlrev_b32_e32 v31, 2, v1
v_mad_u32_u24 v28, 0x3200, v25, v2
v_mul_u32_u24_e32 v2, 0x60, v25
v_lshlrev_b32_e32 v29, 11, v25
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v5, 0
v_lshl_add_u32 v32, v2, 1, s7
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v24, 0
s_lshl_b32 s5, s6, 7
s_mov_b32 s6, 0
s_and_b32 s4, s5, 0x780
BB50_1:
v_lshl_add_u32 v33, s6, 4, v28
v_lshl_add_u32 v35, s6, 15, v29
s_mov_b32 s7, 0
v_ashrrev_i32_e32 v34, 31, v33
v_or3_b32 v35, v35, s4, v27
v_lshlrev_b64 v[33:34], 1, v[33:34]
v_ashrrev_i32_e32 v36, 31, v35
s_waitcnt lgkmcnt(0)
v_add_co_u32 v33, vcc_lo, s10, v33
v_lshlrev_b64 v[35:36], 1, v[35:36]
v_add_co_ci_u32_e32 v34, vcc_lo, s11, v34, vcc_lo
v_add_co_u32 v37, vcc_lo, 0x19000, v33
v_add_co_ci_u32_e32 v38, vcc_lo, 0, v34, vcc_lo
v_add_co_u32 v39, vcc_lo, 0x32000, v33
v_add_co_ci_u32_e32 v40, vcc_lo, 0, v34, vcc_lo
v_add_co_u32 v41, vcc_lo, 0x4b000, v33
v_add_co_ci_u32_e32 v42, vcc_lo, 0, v34, vcc_lo
v_add_co_u32 v43, vcc_lo, 0x64000, v33
v_add_co_ci_u32_e32 v44, vcc_lo, 0, v34, vcc_lo
v_add_co_u32 v35, vcc_lo, s12, v35
v_add_co_ci_u32_e32 v36, vcc_lo, s13, v36, vcc_lo
v_add_co_u32 v45, vcc_lo, 0x7d000, v33
v_add_co_ci_u32_e32 v46, vcc_lo, 0, v34, vcc_lo
v_add_co_u32 v47, vcc_lo, 0x4000, v35
v_add_co_ci_u32_e32 v48, vcc_lo, 0, v36, vcc_lo
v_add_co_u32 v49, vcc_lo, 0x8000, v35
v_add_co_ci_u32_e32 v50, vcc_lo, 0, v36, vcc_lo
v_add_co_u32 v51, vcc_lo, 0xc000, v35
v_add_co_ci_u32_e32 v52, vcc_lo, 0, v36, vcc_lo
s_clause 0x5
global_load_ushort v53, v[33:34], off
global_load_ushort v54, v[37:38], off
global_load_ushort v55, v[39:40], off
global_load_ushort v56, v[41:42], off
global_load_ushort v57, v[43:44], off
global_load_ushort v58, v[45:46], off
s_clause 0x3
global_load_dwordx4 v[34:37], v[35:36], off
global_load_dwordx4 v[38:41], v[47:48], off
global_load_dwordx4 v[42:45], v[49:50], off
global_load_dwordx4 v[46:49], v[51:52], off
v_mov_b32_e32 v33, v32
s_waitcnt vmcnt(0)
s_barrier
ds_write_b16 v26, v53
ds_write_b16 v26, v54 offset:128
ds_write_b16 v26, v55 offset:256
ds_write_b16 v26, v56 offset:384
ds_write_b16 v26, v57 offset:512
ds_write_b16 v26, v58 offset:640
ds_write_b128 v30, v[34:37]
ds_write_b128 v30, v[38:41] offset:1024
ds_write_b128 v30, v[42:45] offset:2048
ds_write_b128 v30, v[46:49] offset:3072
s_waitcnt lgkmcnt(0)
s_barrier
BB50_2:
v_or_b32_e32 v46, s7, v31
ds_read2_b64 v[34:37], v33 offset1:4
ds_read2_b64 v[38:41], v33 offset0:8 offset1:12
ds_read2_b64 v[42:45], v33 offset0:16 offset1:20
v_add_nc_u32_e32 v33, 8, v33
s_addk_i32 s7, 0x200
v_lshlrev_b32_e32 v60, 1, v46
s_cmpk_lg_i32 s7, 0x800
ds_read2_b32 v[58:59], v60 offset1:1
ds_read2_b64 v[46:49], v60 offset0:16 offset1:32
ds_read2_b64 v[50:53], v60 offset0:48 offset1:64
ds_read2_b64 v[54:57], v60 offset0:80 offset1:96
ds_read_b64 v[60:61], v60 offset:896
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v21, v34, v58, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v34, v59, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v36, v58, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v36, v59, v19 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v23, v34, v46, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v34, v47, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v36, v46, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v36, v47, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v38, v58, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v38, v59, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v38, v46, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v38, v47, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v40, v58, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v40, v46, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v40, v59, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v40, v47, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v42, v58, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v42, v46, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v42, v59, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v42, v47, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v44, v58, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v44, v46, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v44, v59, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v44, v47, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v34, v48, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v34, v49, v22 op_sel:[1,0,0]
v_pk_fma_f16 v20, v36, v48, v20 op_sel:[1,0,0]
v_pk_fma_f16 v19, v36, v49, v19 op_sel:[1,0,0]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v23, v34, v50, v23 op_sel:[1,0,0]
v_pk_fma_f16 v24, v34, v51, v24 op_sel:[1,0,0]
v_pk_fma_f16 v16, v36, v50, v16 op_sel:[1,0,0]
v_pk_fma_f16 v14, v36, v51, v14 op_sel:[1,0,0]
v_pk_fma_f16 v18, v38, v48, v18 op_sel:[1,0,0]
v_pk_fma_f16 v17, v38, v49, v17 op_sel:[1,0,0]
v_pk_fma_f16 v12, v38, v50, v12 op_sel:[1,0,0]
v_pk_fma_f16 v10, v38, v51, v10 op_sel:[1,0,0]
v_pk_fma_f16 v15, v40, v48, v15 op_sel:[1,0,0]
v_pk_fma_f16 v8, v40, v50, v8 op_sel:[1,0,0]
v_pk_fma_f16 v13, v40, v49, v13 op_sel:[1,0,0]
v_pk_fma_f16 v6, v40, v51, v6 op_sel:[1,0,0]
v_pk_fma_f16 v11, v42, v48, v11 op_sel:[1,0,0]
v_pk_fma_f16 v4, v42, v50, v4 op_sel:[1,0,0]
v_pk_fma_f16 v9, v42, v49, v9 op_sel:[1,0,0]
v_pk_fma_f16 v3, v42, v51, v3 op_sel:[1,0,0]
v_pk_fma_f16 v7, v44, v48, v7 op_sel:[1,0,0]
v_pk_fma_f16 v1, v44, v50, v1 op_sel:[1,0,0]
v_pk_fma_f16 v5, v44, v49, v5 op_sel:[1,0,0]
v_pk_fma_f16 v2, v44, v51, v2 op_sel:[1,0,0]
v_pk_fma_f16 v21, v35, v52, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v35, v53, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v37, v52, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v37, v53, v19 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v23, v35, v54, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v35, v55, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v37, v54, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v37, v55, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v39, v52, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v39, v53, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v39, v54, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v39, v55, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v41, v52, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v41, v54, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v41, v53, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v41, v55, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v43, v52, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v43, v54, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v43, v53, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v43, v55, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v45, v52, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v45, v54, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v45, v53, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v45, v55, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v35, v56, v21 op_sel:[1,0,0]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v23, v35, v60, v23 op_sel:[1,0,0]
v_pk_fma_f16 v22, v35, v57, v22 op_sel:[1,0,0]
v_pk_fma_f16 v24, v35, v61, v24 op_sel:[1,0,0]
v_pk_fma_f16 v20, v37, v56, v20 op_sel:[1,0,0]
v_pk_fma_f16 v16, v37, v60, v16 op_sel:[1,0,0]
v_pk_fma_f16 v19, v37, v57, v19 op_sel:[1,0,0]
v_pk_fma_f16 v14, v37, v61, v14 op_sel:[1,0,0]
v_pk_fma_f16 v18, v39, v56, v18 op_sel:[1,0,0]
v_pk_fma_f16 v12, v39, v60, v12 op_sel:[1,0,0]
v_pk_fma_f16 v17, v39, v57, v17 op_sel:[1,0,0]
v_pk_fma_f16 v10, v39, v61, v10 op_sel:[1,0,0]
v_pk_fma_f16 v15, v41, v56, v15 op_sel:[1,0,0]
v_pk_fma_f16 v8, v41, v60, v8 op_sel:[1,0,0]
v_pk_fma_f16 v13, v41, v57, v13 op_sel:[1,0,0]
v_pk_fma_f16 v6, v41, v61, v6 op_sel:[1,0,0]
v_pk_fma_f16 v11, v43, v56, v11 op_sel:[1,0,0]
v_pk_fma_f16 v4, v43, v60, v4 op_sel:[1,0,0]
v_pk_fma_f16 v9, v43, v57, v9 op_sel:[1,0,0]
v_pk_fma_f16 v3, v43, v61, v3 op_sel:[1,0,0]
v_pk_fma_f16 v7, v45, v56, v7 op_sel:[1,0,0]
v_pk_fma_f16 v1, v45, v60, v1 op_sel:[1,0,0]
v_pk_fma_f16 v5, v45, v57, v5 op_sel:[1,0,0]
v_pk_fma_f16 v2, v45, v61, v2 op_sel:[1,0,0]
s_cbranch_scc1 BB50_2
s_add_i32 s6, s6, 1
s_cmp_eq_u32 s6, 32
s_cbranch_scc0 BB50_1
v_lshlrev_b32_e32 v0, 2, v0
v_mad_u32_u24 v25, 0x4b000, v25, s5
v_and_b32_e32 v0, 60, v0
v_or_b32_e32 v25, v25, v0
v_or_b32_e32 v0, s4, v0
v_add_nc_u32_e32 v27, 0xc800, v25
v_ashrrev_i32_e32 v26, 31, v25
v_add_nc_u32_e32 v29, 0xc840, v25
v_add_nc_u32_e32 v31, 0xc802, v25
v_add_nc_u32_e32 v33, 0xc842, v25
v_ashrrev_i32_e32 v28, 31, v27
v_lshlrev_b64 v[35:36], 1, v[25:26]
v_ashrrev_i32_e32 v30, 31, v29
v_ashrrev_i32_e32 v32, 31, v31
v_add_nc_u32_e32 v26, 0x19000, v25
v_lshlrev_b64 v[39:40], 1, v[27:28]
v_ashrrev_i32_e32 v34, 31, v33
v_add_co_u32 v37, vcc_lo, s2, v35
v_lshlrev_b64 v[28:29], 1, v[29:30]
v_add_co_ci_u32_e32 v38, vcc_lo, s3, v36, vcc_lo
v_add_nc_u32_e32 v45, 0x19040, v25
v_add_co_u32 v41, vcc_lo, s2, v39
v_lshlrev_b64 v[30:31], 1, v[31:32]
v_ashrrev_i32_e32 v27, 31, v26
v_add_co_ci_u32_e32 v42, vcc_lo, s3, v40, vcc_lo
v_add_nc_u32_e32 v55, 0x19002, v25
v_add_co_u32 v43, vcc_lo, s2, v28
v_lshlrev_b64 v[32:33], 1, v[33:34]
v_ashrrev_i32_e32 v46, 31, v45
v_add_co_ci_u32_e32 v44, vcc_lo, s3, v29, vcc_lo
s_clause 0x5
global_load_ushort v98, v[37:38], off offset:132
global_load_ushort v99, v[37:38], off offset:134
global_load_dword v97, v[37:38], off
global_load_ushort v100, v[37:38], off offset:130
global_load_ushort v101, v[37:38], off offset:128
global_load_dword v102, v[37:38], off offset:4
v_add_nc_u32_e32 v37, 0x19042, v25
v_add_co_u32 v47, vcc_lo, s2, v30
v_lshlrev_b64 v[26:27], 1, v[26:27]
v_ashrrev_i32_e32 v56, 31, v55
v_add_co_ci_u32_e32 v48, vcc_lo, s3, v31, vcc_lo
v_add_nc_u32_e32 v57, 0x25800, v25
v_add_co_u32 v49, vcc_lo, s2, v32
v_lshlrev_b64 v[45:46], 1, v[45:46]
v_ashrrev_i32_e32 v38, 31, v37
v_add_co_ci_u32_e32 v50, vcc_lo, s3, v33, vcc_lo
v_add_nc_u32_e32 v59, 0x25840, v25
v_add_co_u32 v51, vcc_lo, s2, v26
v_lshlrev_b64 v[55:56], 1, v[55:56]
v_ashrrev_i32_e32 v58, 31, v57
v_add_co_ci_u32_e32 v52, vcc_lo, s3, v27, vcc_lo
v_add_nc_u32_e32 v63, 0x25802, v25
v_add_co_u32 v53, vcc_lo, s2, v45
v_lshlrev_b64 v[37:38], 1, v[37:38]
v_ashrrev_i32_e32 v60, 31, v59
v_add_co_ci_u32_e32 v54, vcc_lo, s3, v46, vcc_lo
v_add_nc_u32_e32 v67, 0x25842, v25
v_add_co_u32 v61, vcc_lo, s2, v55
v_lshlrev_b64 v[57:58], 1, v[57:58]
v_ashrrev_i32_e32 v64, 31, v63
v_add_co_ci_u32_e32 v62, vcc_lo, s3, v56, vcc_lo
v_add_nc_u32_e32 v71, 0x32000, v25
v_add_co_u32 v65, vcc_lo, s2, v37
v_lshlrev_b64 v[59:60], 1, v[59:60]
v_ashrrev_i32_e32 v68, 31, v67
v_add_co_ci_u32_e32 v66, vcc_lo, s3, v38, vcc_lo
v_add_nc_u32_e32 v75, 0x32040, v25
v_add_co_u32 v69, vcc_lo, s2, v57
v_lshlrev_b64 v[63:64], 1, v[63:64]
v_ashrrev_i32_e32 v72, 31, v71
v_add_co_ci_u32_e32 v70, vcc_lo, s3, v58, vcc_lo
v_add_nc_u32_e32 v79, 0x32002, v25
v_add_co_u32 v73, vcc_lo, s2, v59
v_lshlrev_b64 v[67:68], 1, v[67:68]
v_ashrrev_i32_e32 v76, 31, v75
v_add_co_ci_u32_e32 v74, vcc_lo, s3, v60, vcc_lo
v_add_nc_u32_e32 v85, 0x32042, v25
v_add_co_u32 v77, vcc_lo, s2, v63
v_lshlrev_b64 v[71:72], 1, v[71:72]
v_ashrrev_i32_e32 v80, 31, v79
v_add_co_ci_u32_e32 v78, vcc_lo, s3, v64, vcc_lo
v_add_nc_u32_e32 v89, 0x3e800, v25
v_add_co_u32 v81, vcc_lo, s2, v67
v_lshlrev_b64 v[75:76], 1, v[75:76]
v_ashrrev_i32_e32 v86, 31, v85
v_add_co_ci_u32_e32 v82, vcc_lo, s3, v68, vcc_lo
v_lshlrev_b32_e32 v0, 1, v0
v_add_nc_u32_e32 v93, 0x3e840, v25
v_add_co_u32 v83, vcc_lo, s2, v71
v_lshlrev_b64 v[79:80], 1, v[79:80]
v_ashrrev_i32_e32 v90, 31, v89
v_add_co_ci_u32_e32 v84, vcc_lo, s3, v72, vcc_lo
v_add_nc_u32_e32 v95, 0x3e802, v25
v_add_co_u32 v87, vcc_lo, s2, v75
v_lshlrev_b64 v[85:86], 1, v[85:86]
s_clause 0x5
global_load_ushort v103, v0, s[8:9] offset:130
global_load_ushort v104, v0, s[8:9] offset:132
global_load_ushort v105, v0, s[8:9] offset:134
global_load_ushort v106, v0, s[8:9] offset:128
global_load_dword v107, v0, s[8:9] offset:4
global_load_dword v0, v0, s[8:9]
v_ashrrev_i32_e32 v94, 31, v93
v_add_co_ci_u32_e32 v88, vcc_lo, s3, v76, vcc_lo
s_clause 0x3
global_load_dword v108, v[41:42], off
global_load_dword v109, v[43:44], off
global_load_dword v110, v[47:48], off
global_load_dword v111, v[49:50], off
v_add_nc_u32_e32 v49, 0x3e842, v25
v_add_co_u32 v91, vcc_lo, s2, v79
v_lshlrev_b64 v[43:44], 1, v[89:90]
v_ashrrev_i32_e32 v96, 31, v95
v_add_co_ci_u32_e32 v92, vcc_lo, s3, v80, vcc_lo
v_add_co_u32 v41, vcc_lo, s2, v85
v_lshlrev_b64 v[89:90], 1, v[93:94]
v_ashrrev_i32_e32 v50, 31, v49
v_add_co_ci_u32_e32 v42, vcc_lo, s3, v86, vcc_lo
v_lshlrev_b64 v[93:94], 1, v[95:96]
v_add_co_u32 v47, vcc_lo, s2, v43
s_clause 0x1
global_load_dword v95, v[51:52], off
global_load_dword v96, v[53:54], off
v_add_co_ci_u32_e32 v48, vcc_lo, s3, v44, vcc_lo
v_add_co_u32 v51, vcc_lo, s2, v89
v_lshlrev_b64 v[49:50], 1, v[49:50]
v_add_co_ci_u32_e32 v52, vcc_lo, s3, v90, vcc_lo
v_add_co_u32 v53, vcc_lo, s2, v93
s_clause 0x1
global_load_dword v112, v[61:62], off
global_load_dword v113, v[65:66], off
v_add_co_ci_u32_e32 v54, vcc_lo, s3, v94, vcc_lo
s_clause 0x1
global_load_dword v69, v[69:70], off
global_load_dword v70, v[73:74], off
v_add_co_u32 v61, vcc_lo, s2, v49
v_add_co_ci_u32_e32 v62, vcc_lo, s3, v50, vcc_lo
s_clause 0x9
global_load_dword v73, v[77:78], off
global_load_dword v74, v[81:82], off
global_load_dword v77, v[83:84], off
global_load_dword v78, v[87:88], off
global_load_dword v81, v[91:92], off
global_load_dword v82, v[41:42], off
global_load_dword v83, v[47:48], off
global_load_dword v84, v[51:52], off
global_load_dword v87, v[53:54], off
global_load_dword v88, v[61:62], off
v_add_co_u32 v34, vcc_lo, s0, v35
v_mov_b32_e32 v91, 0xffff
v_add_co_ci_u32_e32 v35, vcc_lo, s1, v36, vcc_lo
v_add_co_u32 v39, vcc_lo, s0, v39
v_add_co_ci_u32_e32 v40, vcc_lo, s1, v40, vcc_lo
v_add_co_u32 v28, vcc_lo, s0, v28
v_add_co_ci_u32_e32 v29, vcc_lo, s1, v29, vcc_lo
v_add_co_u32 v30, vcc_lo, s0, v30
v_add_co_ci_u32_e32 v31, vcc_lo, s1, v31, vcc_lo
v_add_co_u32 v32, vcc_lo, s0, v32
v_add_co_ci_u32_e32 v33, vcc_lo, s1, v33, vcc_lo
v_add_co_u32 v25, vcc_lo, s0, v26
v_add_co_ci_u32_e32 v26, vcc_lo, s1, v27, vcc_lo
v_add_co_u32 v41, vcc_lo, s0, v45
v_add_co_ci_u32_e32 v42, vcc_lo, s1, v46, vcc_lo
v_add_co_u32 v45, vcc_lo, s0, v55
v_add_co_ci_u32_e32 v46, vcc_lo, s1, v56, vcc_lo
v_add_co_u32 v36, vcc_lo, s0, v37
v_add_co_ci_u32_e32 v37, vcc_lo, s1, v38, vcc_lo
v_add_co_u32 v47, vcc_lo, s0, v57
v_add_co_ci_u32_e32 v48, vcc_lo, s1, v58, vcc_lo
v_add_co_u32 v51, vcc_lo, s0, v59
v_add_co_ci_u32_e32 v52, vcc_lo, s1, v60, vcc_lo
v_add_co_u32 v53, vcc_lo, s0, v63
v_add_co_ci_u32_e32 v54, vcc_lo, s1, v64, vcc_lo
v_add_co_u32 v55, vcc_lo, s0, v67
v_add_co_ci_u32_e32 v56, vcc_lo, s1, v68, vcc_lo
v_add_co_u32 v57, vcc_lo, s0, v71
v_add_co_ci_u32_e32 v58, vcc_lo, s1, v72, vcc_lo
v_add_co_u32 v59, vcc_lo, s0, v75
v_add_co_ci_u32_e32 v60, vcc_lo, s1, v76, vcc_lo
v_add_co_u32 v61, vcc_lo, s0, v79
v_add_co_ci_u32_e32 v62, vcc_lo, s1, v80, vcc_lo
v_add_co_u32 v63, vcc_lo, s0, v85
v_add_co_ci_u32_e32 v64, vcc_lo, s1, v86, vcc_lo
v_add_co_u32 v43, vcc_lo, s0, v43
v_add_co_ci_u32_e32 v44, vcc_lo, s1, v44, vcc_lo
v_add_co_u32 v65, vcc_lo, s0, v89
v_add_co_ci_u32_e32 v66, vcc_lo, s1, v90, vcc_lo
v_add_co_u32 v67, vcc_lo, s0, v93
v_add_co_ci_u32_e32 v68, vcc_lo, s1, v94, vcc_lo
s_waitcnt vmcnt(22)
v_and_b32_e32 v71, v91, v106
v_and_b32_e32 v72, v91, v104
s_waitcnt vmcnt(20)
v_pk_add_f16 v21, v0, v21
v_pk_add_f16 v20, v0, v20
v_pk_add_f16 v18, v0, v18
v_pk_add_f16 v15, v0, v15
v_pk_add_f16 v11, v0, v11
v_pk_add_f16 v0, v0, v7
v_pk_add_f16 v7, v107, v19
v_lshl_or_b32 v19, v103, 16, v71
v_add_f16_e32 v27, v106, v23
v_lshl_or_b32 v71, v105, 16, v72
v_add_f16_sdwa v23, v103, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_add_f16_e32 v38, v104, v24
v_pk_add_f16 v22, v107, v22
v_add_f16_sdwa v24, v105, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_add_f16 v16, v19, v16
v_pk_add_f16 v12, v19, v12
v_pk_add_f16 v8, v19, v8
v_pk_add_f16 v4, v19, v4
v_pk_add_f16 v1, v19, v1
v_add_f16_e32 v19, v101, v27
v_pk_add_f16 v21, v97, v21
v_pk_add_f16 v3, v71, v3
v_add_f16_e32 v23, v100, v23
v_pk_add_f16 v14, v71, v14
v_add_f16_e32 v27, v98, v38
v_pk_add_f16 v22, v102, v22
v_pk_add_f16 v17, v107, v17
v_pk_add_f16 v13, v107, v13
v_pk_add_f16 v9, v107, v9
v_pk_add_f16 v5, v107, v5
v_pk_add_f16 v10, v71, v10
v_pk_add_f16 v6, v71, v6
v_add_f16_e32 v24, v99, v24
v_max_f16_e32 v19, 0, v19
s_waitcnt vmcnt(19)
v_pk_add_f16 v20, v108, v20
v_pk_add_f16 v2, v71, v2
s_waitcnt vmcnt(18)
v_pk_add_f16 v16, v109, v16
v_pk_max_f16 v21, v21, 0
s_waitcnt vmcnt(17)
v_pk_add_f16 v7, v110, v7
s_waitcnt vmcnt(4)
v_pk_add_f16 v3, v82, v3
v_max_f16_e32 v23, 0, v23
v_pk_add_f16 v14, v111, v14
v_max_f16_e32 v27, 0, v27
s_waitcnt vmcnt(3)
v_pk_add_f16 v0, v83, v0
v_pk_add_f16 v18, v95, v18
v_pk_add_f16 v4, v78, v4
v_pk_max_f16 v22, v22, 0
s_waitcnt vmcnt(2)
v_pk_add_f16 v1, v84, v1
v_pk_add_f16 v12, v96, v12
v_pk_add_f16 v17, v112, v17
v_pk_add_f16 v10, v113, v10
v_pk_add_f16 v15, v69, v15
v_pk_add_f16 v8, v70, v8
v_pk_add_f16 v13, v73, v13
v_pk_add_f16 v6, v74, v6
v_pk_add_f16 v11, v77, v11
v_pk_add_f16 v9, v81, v9
v_max_f16_e32 v24, 0, v24
global_store_short v[34:35], v19, off offset:128
global_store_dword v[34:35], v21, off
global_store_short v[34:35], v23, off offset:130
global_store_short v[34:35], v27, off offset:132
global_store_dword v[34:35], v22, off offset:4
global_store_short v[34:35], v24, off offset:134
v_pk_max_f16 v19, v20, 0
s_waitcnt vmcnt(1)
v_pk_add_f16 v5, v87, v5
s_waitcnt vmcnt(0)
v_pk_add_f16 v2, v88, v2
v_pk_max_f16 v16, v16, 0
v_pk_max_f16 v7, v7, 0
v_pk_max_f16 v3, v3, 0
v_pk_max_f16 v20, v0, 0
v_pk_max_f16 v14, v14, 0
v_pk_max_f16 v18, v18, 0
v_pk_max_f16 v4, v4, 0
v_pk_max_f16 v21, v1, 0
v_add_co_u32 v0, vcc_lo, s0, v49
v_pk_max_f16 v12, v12, 0
v_pk_max_f16 v17, v17, 0
v_pk_max_f16 v10, v10, 0
v_pk_max_f16 v15, v15, 0
v_pk_max_f16 v8, v8, 0
v_pk_max_f16 v13, v13, 0
v_pk_max_f16 v6, v6, 0
v_pk_max_f16 v11, v11, 0
v_pk_max_f16 v9, v9, 0
global_store_dword v[39:40], v19, off
global_store_dword v[28:29], v16, off
global_store_dword v[30:31], v7, off
global_store_dword v[32:33], v14, off
global_store_dword v[25:26], v18, off
global_store_dword v[41:42], v12, off
global_store_dword v[45:46], v17, off
global_store_dword v[36:37], v10, off
global_store_dword v[47:48], v15, off
global_store_dword v[51:52], v8, off
global_store_dword v[53:54], v13, off
global_store_dword v[55:56], v6, off
global_store_dword v[57:58], v11, off
global_store_dword v[59:60], v4, off
global_store_dword v[61:62], v9, off
v_pk_max_f16 v4, v5, 0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v50, vcc_lo
v_pk_max_f16 v2, v2, 0
global_store_dword v[63:64], v3, off
global_store_dword v[43:44], v20, off
global_store_dword v[65:66], v21, off
global_store_dword v[67:68], v4, off
global_store_dword v[0:1], v2, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_add_nn_relu_3_kernel0
.amdhsa_group_segment_fixed_size 4864
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 114
.amdhsa_next_free_sgpr 14
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end50:
.size tvmgen_default_fused_nn_conv2d_add_add_nn_relu_3_kernel0, .Lfunc_end50-tvmgen_default_fused_nn_conv2d_add_add_nn_relu_3_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_add_nn_relu_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_add_nn_relu_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_add_nn_relu_kernel0:
s_mul_hi_i32 s0, s6, 0x51eb851f
v_lshrrev_b32_e32 v3, 6, v0
s_lshr_b32 s1, s0, 31
s_ashr_i32 s7, s0, 5
s_mov_b32 s9, 0xc800
s_add_i32 s7, s7, s1
v_and_b32_e32 v1, 15, v0
v_lshlrev_b32_e32 v2, 2, v0
s_mul_i32 s0, s7, s9
s_mul_i32 s8, s7, 0x64
v_mad_u32_u24 v3, 0x3200, v3, s0
s_clause 0x3
s_load_dwordx2 s[10:11], s[4:5], 0x0
s_load_dwordx2 s[12:13], s[4:5], 0x8
s_load_dwordx2 s[0:1], s[4:5], 0x10
s_load_dwordx2 s[2:3], s[4:5], 0x18
v_lshlrev_b32_e32 v4, 1, v1
v_and_b32_e32 v5, 0xc0, v2
s_load_dwordx2 s[4:5], s[4:5], 0x20
s_sub_i32 s8, s6, s8
v_lshlrev_b32_e32 v12, 4, v0
s_lshl_b32 s14, s8, 7
v_or3_b32 v3, v3, v5, v4
s_and_b32 s15, s14, 0xffffff00
s_movk_i32 s14, 0x2000
v_lshlrev_b32_e32 v13, 3, v1
v_or_b32_e32 v11, s14, v2
v_add_nc_u32_e32 v10, s15, v3
v_lshlrev_b32_e32 v3, 3, v0
v_and_b32_e32 v9, 0x7c, v2
v_and_b32_e32 v14, 0x3f00, v12
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
v_and_or_b32 v15, 0x1f00, v3, s14
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v8, 0
s_lshl_b32 s6, s6, 7
s_mov_b32 s17, 0
s_and_b32 s6, s6, 0x80
s_mov_b32 s16, -1
s_movk_i32 s15, 0x1000
BB51_1:
v_lshl_add_u32 v17, s17, 13, v14
v_lshl_or_b32 v16, s17, 5, v10
s_xor_b32 s16, s16, -1
s_mov_b32 s17, 0
v_or3_b32 v18, v17, s6, v13
v_ashrrev_i32_e32 v17, 31, v16
v_ashrrev_i32_e32 v19, 31, v18
v_lshlrev_b64 v[16:17], 1, v[16:17]
v_lshlrev_b64 v[18:19], 1, v[18:19]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v16, vcc_lo, s10, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s11, v17, vcc_lo
v_add_co_u32 v18, vcc_lo, s12, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s13, v19, vcc_lo
v_add_co_u32 v20, vcc_lo, s9, v16
v_add_co_ci_u32_e32 v21, vcc_lo, 0, v17, vcc_lo
v_add_co_u32 v22, vcc_lo, s15, v18
v_add_co_ci_u32_e32 v23, vcc_lo, 0, v19, vcc_lo
v_add_co_u32 v25, vcc_lo, s14, v18
v_add_co_ci_u32_e32 v26, vcc_lo, 0, v19, vcc_lo
v_add_co_u32 v29, vcc_lo, 0x3000, v18
v_add_co_ci_u32_e32 v30, vcc_lo, 0, v19, vcc_lo
s_clause 0x1
global_load_dword v33, v[16:17], off
global_load_dword v34, v[20:21], off
s_clause 0x3
global_load_dwordx4 v[17:20], v[18:19], off
global_load_dwordx4 v[21:24], v[22:23], off
global_load_dwordx4 v[25:28], v[25:26], off
global_load_dwordx4 v[29:32], v[29:30], off
v_mov_b32_e32 v16, v15
s_waitcnt vmcnt(0)
s_barrier
ds_write2st64_b32 v11, v33, v34 offset1:2
ds_write_b128 v12, v[17:20]
ds_write_b128 v12, v[21:24] offset:2048
ds_write_b128 v12, v[25:28] offset:4096
ds_write_b128 v12, v[29:32] offset:6144
s_waitcnt lgkmcnt(0)
s_barrier
BB51_2:
v_or_b32_e32 v33, s17, v9
ds_read_b128 v[17:20], v16
ds_read_b128 v[21:24], v16 offset:64
ds_read_b128 v[25:28], v16 offset:128
ds_read_b128 v[29:32], v16 offset:192
v_add_nc_u32_e32 v16, 16, v16
s_addk_i32 s17, 0x400
v_lshlrev_b32_e32 v41, 1, v33
s_cmp_lg_u32 s17, s15
ds_read2_b32 v[45:46], v41 offset1:1
ds_read2_b64 v[33:36], v41 offset0:32 offset1:64
ds_read_b64 v[47:48], v41 offset:1792
ds_read2_b64 v[37:40], v41 offset0:96 offset1:128
ds_read2_b64 v[41:44], v41 offset0:160 offset1:192
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v8, v17, v45, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v17, v46, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v21, v45, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v21, v46, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v25, v45, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v25, v46, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v29, v45, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v29, v46, v1 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v8, v17, v33, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v17, v34, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v21, v33, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v21, v34, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v25, v33, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v25, v34, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v29, v33, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v29, v34, v1 op_sel:[1,0,0]
v_pk_fma_f16 v8, v18, v35, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v18, v36, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v22, v35, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v22, v36, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v26, v35, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v26, v36, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v30, v35, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v30, v36, v1 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v8, v18, v37, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v18, v38, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v22, v37, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v22, v38, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v26, v37, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v26, v38, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v30, v37, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v30, v38, v1 op_sel:[1,0,0]
v_pk_fma_f16 v8, v19, v39, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v19, v40, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v23, v39, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v23, v40, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v27, v39, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v27, v40, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v31, v39, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v31, v40, v1 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v8, v19, v41, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v19, v42, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v23, v41, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v23, v42, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v27, v41, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v27, v42, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v31, v41, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v31, v42, v1 op_sel:[1,0,0]
v_pk_fma_f16 v8, v20, v43, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v20, v44, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v24, v43, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v24, v44, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v28, v43, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v28, v44, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v32, v43, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v32, v44, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v20, v47, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v20, v48, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v24, v47, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v24, v48, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v28, v47, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v28, v48, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v32, v47, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v32, v48, v1 op_sel:[1,0,0]
s_cbranch_scc1 BB51_2
s_and_b32 vcc_lo, exec_lo, s16
s_mov_b32 s17, 1
s_mov_b32 s16, 0
s_cbranch_vccz BB51_1
v_lshrrev_b32_e32 v0, 5, v0
s_mul_i32 s7, s7, 0x32000
v_mad_u32_u24 v0, 0xc800, v0, s7
s_lshl_b32 s7, s8, 9
s_and_b32 s7, s7, 0xfffffc00
v_or3_b32 v0, v0, s6, v9
v_add_nc_u32_e32 v10, s7, v0
v_or_b32_e32 v0, s6, v9
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b32_e32 v0, 1, v0
v_lshlrev_b64 v[9:10], 1, v[10:11]
s_clause 0x1
global_load_dword v13, v0, s[2:3]
global_load_dword v14, v0, s[2:3] offset:4
v_add_co_u32 v11, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s0, v9
s_clause 0x1
global_load_ushort v15, v0, s[2:3] offset:6
global_load_ushort v0, v0, s[2:3] offset:2
s_clause 0xd
global_load_dword v16, v[11:12], off
global_load_dword v17, v[11:12], off offset:4
global_load_ushort v18, v[11:12], off offset:512
global_load_ushort v19, v[11:12], off offset:514
global_load_ushort v20, v[11:12], off offset:516
global_load_ushort v21, v[11:12], off offset:518
global_load_ushort v22, v[11:12], off offset:1024
global_load_ushort v23, v[11:12], off offset:1026
global_load_ushort v24, v[11:12], off offset:1028
global_load_ushort v25, v[11:12], off offset:1030
global_load_ushort v26, v[11:12], off offset:1536
global_load_ushort v27, v[11:12], off offset:1538
global_load_ushort v28, v[11:12], off offset:1540
global_load_ushort v11, v[11:12], off offset:1542
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
s_waitcnt vmcnt(14)
v_add_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_add_f16 v8, v13, v8
v_pk_add_f16 v7, v14, v7
v_pk_add_f16 v6, v13, v6
v_pk_add_f16 v5, v14, v5
v_add_f16_e32 v12, v13, v2
v_add_f16_e32 v2, v14, v1
v_add_f16_sdwa v1, v15, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_add_f16 v4, v13, v4
s_waitcnt vmcnt(13)
v_pk_add_f16 v8, v16, v8
v_pk_add_f16 v3, v14, v3
s_waitcnt vmcnt(12)
v_pk_add_f16 v7, v17, v7
s_waitcnt vmcnt(11)
v_add_f16_e32 v13, v18, v6
s_waitcnt vmcnt(10)
v_add_f16_sdwa v6, v19, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
s_waitcnt vmcnt(9)
v_add_f16_e32 v14, v20, v5
s_waitcnt vmcnt(0)
v_add_f16_e32 v1, v11, v1
v_add_f16_sdwa v5, v21, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_add_f16_e32 v12, v26, v12
v_add_f16_e32 v0, v27, v0
v_add_f16_e32 v2, v28, v2
v_add_f16_e32 v15, v22, v4
v_add_f16_sdwa v4, v23, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_add_f16_e32 v16, v24, v3
v_add_f16_sdwa v3, v25, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_max_f16 v8, v8, 0
v_pk_max_f16 v7, v7, 0
v_max_f16_e32 v11, 0, v13
v_max_f16_e32 v6, 0, v6
v_max_f16_e32 v13, 0, v14
v_max_f16_e32 v14, 0, v15
v_max_f16_e32 v5, 0, v5
v_max_f16_e32 v4, 0, v4
v_max_f16_e32 v15, 0, v16
v_max_f16_e32 v3, 0, v3
v_max_f16_e32 v12, 0, v12
v_max_f16_e32 v0, 0, v0
v_max_f16_e32 v2, 0, v2
v_max_f16_e32 v1, 0, v1
global_store_dword v[9:10], v8, off
global_store_dword v[9:10], v7, off offset:4
global_store_short v[9:10], v11, off offset:512
global_store_short v[9:10], v6, off offset:514
global_store_short v[9:10], v13, off offset:516
global_store_short v[9:10], v5, off offset:518
global_store_short v[9:10], v14, off offset:1024
global_store_short v[9:10], v4, off offset:1026
global_store_short v[9:10], v15, off offset:1028
global_store_short v[9:10], v3, off offset:1030
global_store_short v[9:10], v12, off offset:1536
global_store_short v[9:10], v0, off offset:1538
global_store_short v[9:10], v2, off offset:1540
global_store_short v[9:10], v1, off offset:1542
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_add_nn_relu_kernel0
.amdhsa_group_segment_fixed_size 9216
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 49
.amdhsa_next_free_sgpr 18
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end51:
.size tvmgen_default_fused_nn_conv2d_add_add_nn_relu_kernel0, .Lfunc_end51-tvmgen_default_fused_nn_conv2d_add_add_nn_relu_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_kernel0:
v_lshlrev_b32_e32 v1, 1, v0
s_movk_i32 s0, 0x780
s_movk_i32 s12, 0xa00
s_and_b32 s1, s6, 3
v_add_nc_u32_e32 v4, s0, v0
v_and_b32_e32 v2, 0x7c0, v1
v_add_nc_u32_e32 v6, 0x8c0, v0
v_add_nc_u32_e32 v7, s12, v0
v_add_nc_u32_e32 v8, 0xb40, v0
s_mul_i32 s13, s1, 0xc80
s_mov_b32 s7, 0x51eb851f
v_and_b32_e32 v3, 31, v0
v_add_nc_u32_e32 v5, s13, v2
s_ashr_i32 s6, s6, 2
v_mul_hi_u32 v4, v4, s7
v_mul_hi_u32 v6, v6, s7
v_mul_hi_u32 v7, v7, s7
v_mul_hi_u32 v8, v8, s7
s_mul_i32 s14, s6, 0x6400
v_or_b32_e32 v5, v5, v3
v_add_nc_u32_e32 v2, s14, v2
s_clause 0x3
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[4:5], s[4:5], 0x18
v_lshrrev_b32_e32 v4, 9, v4
s_movk_i32 s7, 0x3200
v_add_nc_u32_e32 v42, s14, v5
v_or_b32_e32 v2, v2, v3
v_lshrrev_b32_e32 v3, 9, v6
v_lshrrev_b32_e32 v5, 9, v7
v_lshrrev_b32_e32 v6, 9, v8
v_mul_i32_i24_e32 v4, s7, v4
v_add_nc_u32_e32 v2, s13, v2
v_mul_i32_i24_e32 v3, s7, v3
v_mul_i32_i24_e32 v5, s7, v5
v_mul_i32_i24_e32 v6, s7, v6
v_lshrrev_b32_e32 v40, 6, v0
v_add3_u32 v44, v2, v4, 0x280
v_add3_u32 v45, v2, v3, 0x500
v_add3_u32 v46, v2, v5, s0
v_add3_u32 v47, v2, v6, s12
v_mul_u32_u24_e32 v2, 0xa0, v40
s_movk_i32 s15, 0x4000
v_lshlrev_b32_e32 v48, 3, v0
v_or_b32_e32 v43, s15, v1
v_and_b32_e32 v41, 0x7e, v1
v_lshl_or_b32 v50, v2, 1, s15
v_lshlrev_b32_e32 v49, 4, v0
v_cmp_gt_i32_e64 s0, 64, v0
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v24, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v35, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v36, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v37, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v29, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v38, 0
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v30, 0
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v39, 0
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v31, 0
v_mov_b32_e32 v28, 0
v_mov_b32_e32 v33, 0
v_mov_b32_e32 v34, 0
v_mov_b32_e32 v32, 0
s_mov_b32 s13, 0
s_mov_b32 s12, -1
s_movk_i32 s7, 0x1000
BB52_1:
s_lshl_b32 s14, s13, 5
v_or_b32_e32 v51, s14, v42
v_or_b32_e32 v53, s14, v44
v_or_b32_e32 v55, s14, v46
v_or_b32_e32 v59, s14, v47
v_or_b32_e32 v57, s14, v45
v_ashrrev_i32_e32 v52, 31, v51
v_ashrrev_i32_e32 v54, 31, v53
v_ashrrev_i32_e32 v56, 31, v55
v_ashrrev_i32_e32 v60, 31, v59
v_ashrrev_i32_e32 v58, 31, v57
v_lshlrev_b64 v[51:52], 1, v[51:52]
v_lshlrev_b64 v[57:58], 1, v[57:58]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v51, vcc_lo, s8, v51
v_add_co_ci_u32_e32 v52, vcc_lo, s9, v52, vcc_lo
v_add_co_u32 v65, vcc_lo, 0x800, v51
v_add_co_ci_u32_e32 v66, vcc_lo, 0, v52, vcc_lo
v_add_co_u32 v67, vcc_lo, s7, v51
s_clause 0x1
global_load_ushort v79, v[51:52], off
global_load_ushort v80, v[51:52], off offset:1280
v_add_co_ci_u32_e32 v68, vcc_lo, 0, v52, vcc_lo
v_add_co_u32 v69, vcc_lo, 0x6000, v51
v_add_co_ci_u32_e32 v70, vcc_lo, 0, v52, vcc_lo
v_lshlrev_b64 v[51:52], 1, v[53:54]
v_lshlrev_b64 v[53:54], 1, v[55:56]
v_lshl_or_b32 v55, s13, 13, v48
v_add_co_u32 v71, vcc_lo, s8, v51
v_ashrrev_i32_e32 v56, 31, v55
v_add_co_ci_u32_e32 v72, vcc_lo, s9, v52, vcc_lo
v_lshlrev_b64 v[51:52], 1, v[59:60]
v_add_co_u32 v53, vcc_lo, s8, v53
v_lshlrev_b64 v[55:56], 1, v[55:56]
v_add_co_ci_u32_e32 v54, vcc_lo, s9, v54, vcc_lo
v_add_co_u32 v59, vcc_lo, s8, v51
v_add_co_ci_u32_e32 v60, vcc_lo, s9, v52, vcc_lo
v_add_co_u32 v51, vcc_lo, s10, v55
v_add_co_ci_u32_e32 v52, vcc_lo, s11, v56, vcc_lo
v_add_co_u32 v73, vcc_lo, s8, v57
v_add_co_ci_u32_e32 v74, vcc_lo, s9, v58, vcc_lo
s_clause 0x1
global_load_ushort v81, v[53:54], off
global_load_ushort v82, v[59:60], off
s_clause 0x3
global_load_dword v53, v[51:52], off
global_load_dword v54, v[51:52], off offset:4
global_load_dword v55, v[51:52], off offset:8
global_load_dword v56, v[51:52], off offset:12
v_add_co_u32 v60, vcc_lo, 0x1400, v51
v_add_co_ci_u32_e32 v61, vcc_lo, 0, v52, vcc_lo
v_add_co_u32 v75, vcc_lo, v51, 0x2800
v_add_co_ci_u32_e32 v76, vcc_lo, 0, v52, vcc_lo
v_add_co_u32 v77, vcc_lo, s7, v51
v_add_co_ci_u32_e32 v78, vcc_lo, 0, v52, vcc_lo
s_clause 0x6
global_load_dword v58, v[60:61], off offset:4
global_load_dword v59, v[60:61], off offset:8
global_load_dword v62, v[75:76], off offset:4
global_load_dword v63, v[75:76], off offset:8
global_load_dword v64, v[75:76], off offset:12
global_load_dword v57, v[77:78], off offset:1024
global_load_dword v60, v[60:61], off offset:12
s_clause 0x5
global_load_ushort v77, v[65:66], off offset:512
global_load_ushort v65, v[65:66], off offset:1792
global_load_ushort v66, v[67:68], off offset:1024
global_load_ushort v67, v[69:70], off offset:1024
global_load_ushort v68, v[71:72], off
global_load_ushort v69, v[73:74], off
global_load_dword v61, v[75:76], off
s_waitcnt vmcnt(0)
s_barrier
ds_write_b128 v49, v[53:56]
ds_write_b16 v43, v79
ds_write_b16 v43, v80 offset:640
ds_write_b16 v43, v81 offset:5120
ds_write_b16 v43, v82 offset:5760
ds_write_b128 v49, v[57:60] offset:5120
ds_write_b16 v43, v77 offset:1280
ds_write_b16 v43, v65 offset:1920
ds_write_b16 v43, v66 offset:2560
ds_write_b16 v43, v67 offset:3200
ds_write_b16 v43, v68 offset:3840
ds_write_b16 v43, v69 offset:4480
ds_write_b128 v49, v[61:64] offset:10240
s_and_saveexec_b32 s13, s0
s_cbranch_execz BB52_3
v_add_co_u32 v54, vcc_lo, 0x3c00, v51
v_add_co_ci_u32_e32 v55, vcc_lo, 0, v52, vcc_lo
v_add_co_u32 v56, vcc_lo, 0x3800, v51
v_add_co_ci_u32_e32 v57, vcc_lo, 0, v52, vcc_lo
s_clause 0x3
global_load_dword v52, v[54:55], off offset:4
global_load_dword v53, v[54:55], off offset:8
global_load_dword v51, v[56:57], off offset:1024
global_load_dword v54, v[54:55], off offset:12
s_waitcnt vmcnt(0)
ds_write_b128 v49, v[51:54] offset:15360
BB52_3:
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v51, v50
s_xor_b32 s12, s12, -1
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
s_barrier
BB52_4:
v_or_b32_e32 v72, s13, v41
v_add_nc_u32_e32 v80, 0x800, v51
v_add_nc_u32_e32 v88, s7, v51
ds_read2_b64 v[52:55], v51 offset1:8
ds_read2_b64 v[56:59], v51 offset0:208 offset1:216
ds_read2_b64 v[60:63], v51 offset0:16 offset1:24
ds_read2_b64 v[64:67], v51 offset0:32 offset1:200
ds_read2_b64 v[68:71], v51 offset0:224 offset1:232
v_add_nc_u32_e32 v84, 0xc00, v51
v_lshlrev_b32_e32 v98, 1, v72
ds_read2_b64 v[72:75], v80 offset0:144 offset1:152
ds_read2_b64 v[76:79], v88 offset0:96 offset1:104
ds_read2_b64 v[80:83], v80 offset0:160 offset1:168
ds_read2_b64 v[84:87], v84 offset0:48 offset1:216
ds_read2_b64 v[88:91], v88 offset0:112 offset1:120
ds_read2st64_b32 v[92:93], v98 offset1:1
ds_read2st64_b32 v[94:95], v98 offset0:2 offset1:3
ds_read2st64_b32 v[96:97], v98 offset0:4 offset1:5
ds_read2st64_b32 v[98:99], v98 offset0:6 offset1:7
v_add_nc_u32_e32 v51, 8, v51
s_addk_i32 s13, 0x400
s_cmpk_lg_i32 s13, 0x2000
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v34, v52, v92, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v52, v93, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v54, v92, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v54, v93, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v39, v56, v92, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v56, v93, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v58, v92, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v58, v93, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v60, v92, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v60, v93, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v62, v92, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v62, v93, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v66, v92, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v66, v93, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v64, v92, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v64, v93, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v68, v92, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v68, v93, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v70, v92, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v70, v93, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v72, v92, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v72, v93, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v74, v92, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v74, v93, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v76, v92, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v76, v93, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v78, v92, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v78, v93, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v80, v92, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v80, v93, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v82, v92, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v82, v93, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v86, v92, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v86, v93, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v88, v92, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v88, v93, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v84, v92, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v84, v93, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v90, v92, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v90, v93, v0 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v34, v52, v94, v34 op_sel:[1,0,0]
v_pk_fma_f16 v32, v52, v95, v32 op_sel:[1,0,0]
v_pk_fma_f16 v31, v54, v94, v31 op_sel:[1,0,0]
v_pk_fma_f16 v25, v54, v95, v25 op_sel:[1,0,0]
v_pk_fma_f16 v39, v56, v94, v39 op_sel:[1,0,0]
v_pk_fma_f16 v23, v56, v95, v23 op_sel:[1,0,0]
v_pk_fma_f16 v38, v58, v94, v38 op_sel:[1,0,0]
v_pk_fma_f16 v18, v58, v95, v18 op_sel:[1,0,0]
v_pk_fma_f16 v30, v60, v94, v30 op_sel:[1,0,0]
v_pk_fma_f16 v21, v60, v95, v21 op_sel:[1,0,0]
v_pk_fma_f16 v29, v62, v94, v29 op_sel:[1,0,0]
v_pk_fma_f16 v16, v62, v95, v16 op_sel:[1,0,0]
v_pk_fma_f16 v33, v66, v94, v33 op_sel:[1,0,0]
v_pk_fma_f16 v28, v66, v95, v28 op_sel:[1,0,0]
v_pk_fma_f16 v26, v64, v94, v26 op_sel:[1,0,0]
v_pk_fma_f16 v12, v64, v95, v12 op_sel:[1,0,0]
v_pk_fma_f16 v37, v68, v94, v37 op_sel:[1,0,0]
v_pk_fma_f16 v13, v68, v95, v13 op_sel:[1,0,0]
v_pk_fma_f16 v36, v70, v94, v36 op_sel:[1,0,0]
v_pk_fma_f16 v10, v70, v95, v10 op_sel:[1,0,0]
v_pk_fma_f16 v35, v72, v94, v35 op_sel:[1,0,0]
v_pk_fma_f16 v9, v72, v95, v9 op_sel:[1,0,0]
v_pk_fma_f16 v24, v74, v94, v24 op_sel:[1,0,0]
v_pk_fma_f16 v7, v74, v95, v7 op_sel:[1,0,0]
v_pk_fma_f16 v22, v76, v94, v22 op_sel:[1,0,0]
v_pk_fma_f16 v6, v76, v95, v6 op_sel:[1,0,0]
v_pk_fma_f16 v19, v78, v94, v19 op_sel:[1,0,0]
v_pk_fma_f16 v4, v78, v95, v4 op_sel:[1,0,0]
v_pk_fma_f16 v20, v80, v94, v20 op_sel:[1,0,0]
v_pk_fma_f16 v5, v80, v95, v5 op_sel:[1,0,0]
v_pk_fma_f16 v17, v82, v94, v17 op_sel:[1,0,0]
v_pk_fma_f16 v3, v82, v95, v3 op_sel:[1,0,0]
v_pk_fma_f16 v27, v86, v94, v27 op_sel:[1,0,0]
v_pk_fma_f16 v8, v86, v95, v8 op_sel:[1,0,0]
v_pk_fma_f16 v15, v88, v94, v15 op_sel:[1,0,0]
v_pk_fma_f16 v2, v88, v95, v2 op_sel:[1,0,0]
v_pk_fma_f16 v14, v84, v94, v14 op_sel:[1,0,0]
v_pk_fma_f16 v1, v84, v95, v1 op_sel:[1,0,0]
v_pk_fma_f16 v11, v90, v94, v11 op_sel:[1,0,0]
v_pk_fma_f16 v0, v90, v95, v0 op_sel:[1,0,0]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v34, v53, v96, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v53, v97, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v55, v96, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v55, v97, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v39, v57, v96, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v57, v97, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v59, v96, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v59, v97, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v61, v96, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v61, v97, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v63, v96, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v63, v97, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v67, v96, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v67, v97, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v65, v96, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v65, v97, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v69, v96, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v69, v97, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v71, v96, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v71, v97, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v73, v96, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v73, v97, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v75, v96, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v75, v97, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v77, v96, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v77, v97, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v79, v96, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v79, v97, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v81, v96, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v81, v97, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v83, v96, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v83, v97, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v87, v96, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v87, v97, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v89, v96, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v89, v97, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v85, v96, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v85, v97, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v91, v96, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v91, v97, v0 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v34, v53, v98, v34 op_sel:[1,0,0]
v_pk_fma_f16 v32, v53, v99, v32 op_sel:[1,0,0]
v_pk_fma_f16 v31, v55, v98, v31 op_sel:[1,0,0]
v_pk_fma_f16 v25, v55, v99, v25 op_sel:[1,0,0]
v_pk_fma_f16 v39, v57, v98, v39 op_sel:[1,0,0]
v_pk_fma_f16 v23, v57, v99, v23 op_sel:[1,0,0]
v_pk_fma_f16 v38, v59, v98, v38 op_sel:[1,0,0]
v_pk_fma_f16 v18, v59, v99, v18 op_sel:[1,0,0]
v_pk_fma_f16 v30, v61, v98, v30 op_sel:[1,0,0]
v_pk_fma_f16 v21, v61, v99, v21 op_sel:[1,0,0]
v_pk_fma_f16 v29, v63, v98, v29 op_sel:[1,0,0]
v_pk_fma_f16 v16, v63, v99, v16 op_sel:[1,0,0]
v_pk_fma_f16 v33, v67, v98, v33 op_sel:[1,0,0]
v_pk_fma_f16 v28, v67, v99, v28 op_sel:[1,0,0]
v_pk_fma_f16 v26, v65, v98, v26 op_sel:[1,0,0]
v_pk_fma_f16 v12, v65, v99, v12 op_sel:[1,0,0]
v_pk_fma_f16 v37, v69, v98, v37 op_sel:[1,0,0]
v_pk_fma_f16 v13, v69, v99, v13 op_sel:[1,0,0]
v_pk_fma_f16 v36, v71, v98, v36 op_sel:[1,0,0]
v_pk_fma_f16 v10, v71, v99, v10 op_sel:[1,0,0]
v_pk_fma_f16 v35, v73, v98, v35 op_sel:[1,0,0]
v_pk_fma_f16 v9, v73, v99, v9 op_sel:[1,0,0]
v_pk_fma_f16 v24, v75, v98, v24 op_sel:[1,0,0]
v_pk_fma_f16 v7, v75, v99, v7 op_sel:[1,0,0]
v_pk_fma_f16 v22, v77, v98, v22 op_sel:[1,0,0]
v_pk_fma_f16 v6, v77, v99, v6 op_sel:[1,0,0]
v_pk_fma_f16 v19, v79, v98, v19 op_sel:[1,0,0]
v_pk_fma_f16 v4, v79, v99, v4 op_sel:[1,0,0]
v_pk_fma_f16 v20, v81, v98, v20 op_sel:[1,0,0]
v_pk_fma_f16 v5, v81, v99, v5 op_sel:[1,0,0]
v_pk_fma_f16 v17, v83, v98, v17 op_sel:[1,0,0]
v_pk_fma_f16 v3, v83, v99, v3 op_sel:[1,0,0]
v_pk_fma_f16 v27, v87, v98, v27 op_sel:[1,0,0]
v_pk_fma_f16 v8, v87, v99, v8 op_sel:[1,0,0]
v_pk_fma_f16 v15, v89, v98, v15 op_sel:[1,0,0]
v_pk_fma_f16 v2, v89, v99, v2 op_sel:[1,0,0]
v_pk_fma_f16 v14, v85, v98, v14 op_sel:[1,0,0]
v_pk_fma_f16 v1, v85, v99, v1 op_sel:[1,0,0]
v_pk_fma_f16 v11, v91, v98, v11 op_sel:[1,0,0]
v_pk_fma_f16 v0, v91, v99, v0 op_sel:[1,0,0]
s_cbranch_scc1 BB52_4
s_and_b32 vcc_lo, exec_lo, s12
s_mov_b32 s13, 1
s_mov_b32 s12, 0
s_cbranch_vccz BB52_1
v_lshlrev_b32_e32 v42, 1, v41
v_mul_u32_u24_e32 v40, 0x500, v40
s_mulk_i32 s1, 0x3200
s_mul_i32 s6, s6, 0x19000
s_clause 0x2
global_load_dword v90, v42, s[4:5]
global_load_ushort v91, v42, s[4:5] offset:256
global_load_ushort v92, v42, s[4:5] offset:258
v_add3_u32 v40, s1, s6, v40
v_or_b32_e32 v40, v40, v41
v_add_nc_u32_e32 v42, 0x1a00, v40
v_add_nc_u32_e32 v44, 0x1b00, v40
v_add_nc_u32_e32 v49, 0x1c00, v40
v_add_nc_u32_e32 v52, 0x1d00, v40
v_add_nc_u32_e32 v54, 0xc800, v40
v_ashrrev_i32_e32 v43, 31, v42
v_ashrrev_i32_e32 v45, 31, v44
v_ashrrev_i32_e32 v50, 31, v49
v_ashrrev_i32_e32 v53, 31, v52
v_ashrrev_i32_e32 v55, 31, v54
v_lshlrev_b64 v[42:43], 1, v[42:43]
v_lshlrev_b64 v[44:45], 1, v[44:45]
v_add_nc_u32_e32 v60, 0xe100, v40
v_ashrrev_i32_e32 v41, 31, v40
v_add_nc_u32_e32 v56, 0x400, v40
v_add_nc_u32_e32 v58, 0x480, v40
v_add_co_u32 v42, vcc_lo, s2, v42
v_add_nc_u32_e32 v62, 0xc900, v40
v_add_co_ci_u32_e32 v43, vcc_lo, s3, v43, vcc_lo
v_add_co_u32 v44, vcc_lo, s2, v44
v_add_nc_u32_e32 v68, 0x1d80, v40
v_add_co_ci_u32_e32 v45, vcc_lo, s3, v45, vcc_lo
v_add_nc_u32_e32 v78, 0xc880, v40
v_add_nc_u32_e32 v80, 0xe180, v40
v_add_nc_u32_e32 v82, 0xc980, v40
v_add_nc_u32_e32 v84, 0xe280, v40
v_add_nc_u32_e32 v86, 0xe580, v40
v_add_nc_u32_e32 v51, 0x1c80, v40
v_ashrrev_i32_e32 v61, 31, v60
v_add_nc_u32_e32 v64, 0xe200, v40
v_lshlrev_b64 v[88:89], 1, v[40:41]
v_ashrrev_i32_e32 v63, 31, v62
v_ashrrev_i32_e32 v57, 31, v56
v_ashrrev_i32_e32 v59, 31, v58
v_ashrrev_i32_e32 v69, 31, v68
v_ashrrev_i32_e32 v79, 31, v78
v_ashrrev_i32_e32 v81, 31, v80
v_ashrrev_i32_e32 v83, 31, v82
v_ashrrev_i32_e32 v85, 31, v84
v_ashrrev_i32_e32 v87, 31, v86
v_add_nc_u32_e32 v66, 0xca00, v40
v_lshlrev_b64 v[60:61], 1, v[60:61]
v_ashrrev_i32_e32 v65, 31, v64
v_add_nc_u32_e32 v70, 0xe300, v40
v_lshlrev_b64 v[62:63], 1, v[62:63]
v_ashrrev_i32_e32 v67, 31, v66
v_add_nc_u32_e32 v72, 0xcb00, v40
v_lshlrev_b64 v[64:65], 1, v[64:65]
v_ashrrev_i32_e32 v71, 31, v70
v_add_nc_u32_e32 v74, 0xe400, v40
v_lshlrev_b64 v[66:67], 1, v[66:67]
v_ashrrev_i32_e32 v73, 31, v72
v_add_nc_u32_e32 v76, 0xcc00, v40
v_lshlrev_b64 v[70:71], 1, v[70:71]
v_ashrrev_i32_e32 v75, 31, v74
v_add_nc_u32_e32 v46, 0x1a80, v40
v_lshlrev_b64 v[72:73], 1, v[72:73]
v_ashrrev_i32_e32 v77, 31, v76
v_add_nc_u32_e32 v48, 0x1b80, v40
v_lshlrev_b64 v[74:75], 1, v[74:75]
v_lshlrev_b64 v[76:77], 1, v[76:77]
s_waitcnt vmcnt(2)
v_pk_add_f16 v39, v90, v39
v_pk_add_f16 v38, v90, v38
v_pk_add_f16 v36, v90, v36
v_pk_add_f16 v47, v90, v37
v_add_nc_u32_e32 v37, 0xcb80, v40
global_store_dword v[42:43], v39, off
v_lshlrev_b64 v[42:43], 1, v[49:50]
v_lshlrev_b64 v[49:50], 1, v[52:53]
v_lshlrev_b64 v[52:53], 1, v[54:55]
global_store_dword v[44:45], v38, off
v_pk_add_f16 v38, v90, v35
v_add_nc_u32_e32 v44, 0xe500, v40
v_add_co_u32 v42, vcc_lo, s2, v42
v_add_nc_u32_e32 v39, 0xca80, v40
v_add_co_ci_u32_e32 v43, vcc_lo, s3, v43, vcc_lo
v_add_co_u32 v49, vcc_lo, s2, v49
v_ashrrev_i32_e32 v45, 31, v44
v_add_co_ci_u32_e32 v50, vcc_lo, s3, v50, vcc_lo
v_add_co_u32 v52, vcc_lo, s2, v52
global_store_dword v[42:43], v47, off
v_add_co_ci_u32_e32 v53, vcc_lo, s3, v53, vcc_lo
v_ashrrev_i32_e32 v47, 31, v46
global_store_dword v[49:50], v36, off
v_add_nc_u32_e32 v42, 0xcc80, v40
v_ashrrev_i32_e32 v49, 31, v48
global_store_dword v[52:53], v38, off
v_ashrrev_i32_e32 v52, 31, v51
v_lshlrev_b64 v[46:47], 1, v[46:47]
v_ashrrev_i32_e32 v43, 31, v42
v_lshlrev_b64 v[48:49], 1, v[48:49]
v_add_nc_u32_e32 v54, 0xe380, v40
v_lshlrev_b64 v[50:51], 1, v[51:52]
v_lshlrev_b64 v[52:53], 1, v[56:57]
v_lshlrev_b64 v[56:57], 1, v[58:59]
v_lshlrev_b64 v[58:59], 1, v[68:69]
v_lshlrev_b64 v[68:69], 1, v[78:79]
v_lshlrev_b64 v[78:79], 1, v[80:81]
v_lshlrev_b64 v[80:81], 1, v[82:83]
v_lshlrev_b64 v[82:83], 1, v[84:85]
v_lshlrev_b64 v[84:85], 1, v[86:87]
v_add_co_u32 v86, vcc_lo, s2, v88
v_lshlrev_b64 v[41:42], 1, v[42:43]
v_add_co_ci_u32_e32 v87, vcc_lo, s3, v89, vcc_lo
v_add_co_u32 v60, vcc_lo, s2, v60
v_lshlrev_b64 v[43:44], 1, v[44:45]
v_add_co_ci_u32_e32 v61, vcc_lo, s3, v61, vcc_lo
v_add_co_u32 v62, vcc_lo, s2, v62
v_add_nc_u32_e32 v35, 0xe480, v40
v_add_co_ci_u32_e32 v63, vcc_lo, s3, v63, vcc_lo
v_add_co_u32 v64, vcc_lo, s2, v64
v_ashrrev_i32_e32 v40, 31, v39
v_add_co_ci_u32_e32 v65, vcc_lo, s3, v65, vcc_lo
v_add_co_u32 v66, vcc_lo, s2, v66
v_ashrrev_i32_e32 v55, 31, v54
v_add_co_ci_u32_e32 v67, vcc_lo, s3, v67, vcc_lo
v_add_co_u32 v70, vcc_lo, s2, v70
v_lshlrev_b64 v[39:40], 1, v[39:40]
v_add_co_ci_u32_e32 v71, vcc_lo, s3, v71, vcc_lo
v_add_co_u32 v72, vcc_lo, s2, v72
v_ashrrev_i32_e32 v38, 31, v37
v_add_co_ci_u32_e32 v73, vcc_lo, s3, v73, vcc_lo
v_add_co_u32 v74, vcc_lo, s2, v74
v_lshlrev_b64 v[54:55], 1, v[54:55]
v_add_co_ci_u32_e32 v75, vcc_lo, s3, v75, vcc_lo
v_add_co_u32 v76, vcc_lo, s2, v76
v_ashrrev_i32_e32 v36, 31, v35
v_add_co_ci_u32_e32 v77, vcc_lo, s3, v77, vcc_lo
v_add_co_u32 v45, vcc_lo, s2, v46
v_lshlrev_b64 v[37:38], 1, v[37:38]
v_add_co_ci_u32_e32 v46, vcc_lo, s3, v47, vcc_lo
v_add_co_u32 v47, vcc_lo, s2, v48
v_lshlrev_b64 v[35:36], 1, v[35:36]
v_add_co_ci_u32_e32 v48, vcc_lo, s3, v49, vcc_lo
v_add_co_u32 v49, vcc_lo, s2, v50
v_pk_add_f16 v27, v90, v27
v_add_co_ci_u32_e32 v50, vcc_lo, s3, v51, vcc_lo
v_add_co_u32 v51, vcc_lo, s2, v52
v_pk_add_f16 v24, v90, v24
v_add_co_ci_u32_e32 v52, vcc_lo, s3, v53, vcc_lo
v_add_co_u32 v56, vcc_lo, s2, v56
v_pk_add_f16 v22, v90, v22
v_add_co_ci_u32_e32 v57, vcc_lo, s3, v57, vcc_lo
v_add_co_u32 v58, vcc_lo, s2, v58
v_pk_add_f16 v20, v90, v20
v_add_co_ci_u32_e32 v59, vcc_lo, s3, v59, vcc_lo
v_add_co_u32 v68, vcc_lo, s2, v68
v_pk_add_f16 v19, v90, v19
v_add_co_ci_u32_e32 v69, vcc_lo, s3, v69, vcc_lo
v_add_co_u32 v78, vcc_lo, s2, v78
v_pk_add_f16 v17, v90, v17
v_add_co_ci_u32_e32 v79, vcc_lo, s3, v79, vcc_lo
v_add_co_u32 v80, vcc_lo, s2, v80
v_pk_add_f16 v15, v90, v15
v_add_co_ci_u32_e32 v81, vcc_lo, s3, v81, vcc_lo
v_add_co_u32 v82, vcc_lo, s2, v82
v_pk_add_f16 v14, v90, v14
v_add_co_ci_u32_e32 v83, vcc_lo, s3, v83, vcc_lo
v_add_co_u32 v39, vcc_lo, s2, v39
v_pk_add_f16 v34, v90, v34
v_add_co_ci_u32_e32 v40, vcc_lo, s3, v40, vcc_lo
v_add_co_u32 v53, vcc_lo, s2, v54
v_pk_add_f16 v33, v90, v33
v_add_co_ci_u32_e32 v54, vcc_lo, s3, v55, vcc_lo
v_add_co_u32 v37, vcc_lo, s2, v37
v_pk_add_f16 v31, v90, v31
v_add_co_ci_u32_e32 v38, vcc_lo, s3, v38, vcc_lo
v_add_co_u32 v35, vcc_lo, s2, v35
v_pk_add_f16 v30, v90, v30
v_add_co_ci_u32_e32 v36, vcc_lo, s3, v36, vcc_lo
v_add_co_u32 v41, vcc_lo, s2, v41
v_pk_add_f16 v29, v90, v29
v_add_co_ci_u32_e32 v42, vcc_lo, s3, v42, vcc_lo
v_add_co_u32 v43, vcc_lo, s2, v43
v_pk_add_f16 v26, v90, v26
v_add_co_ci_u32_e32 v44, vcc_lo, s3, v44, vcc_lo
v_add_co_u32 v84, vcc_lo, s2, v84
v_pk_add_f16 v11, v90, v11
s_waitcnt vmcnt(1)
v_and_b32_e32 v90, 0xffff, v91
v_add_co_ci_u32_e32 v85, vcc_lo, s3, v85, vcc_lo
v_add_co_u32 v88, vcc_lo, 0x3000, v86
v_add_f16_e32 v55, v91, v32
s_waitcnt vmcnt(0)
v_add_f16_sdwa v32, v92, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
global_store_dword v[60:61], v27, off
global_store_dword v[62:63], v24, off
global_store_dword v[64:65], v22, off
global_store_dword v[66:67], v20, off
global_store_dword v[70:71], v19, off
global_store_dword v[72:73], v17, off
global_store_dword v[74:75], v15, off
global_store_dword v[76:77], v14, off
global_store_short v[86:87], v55, off offset:256
global_store_dword v[86:87], v34, off
global_store_short v[86:87], v32, off offset:258
v_lshl_or_b32 v14, v92, 16, v90
v_add_co_ci_u32_e32 v89, vcc_lo, 0, v87, vcc_lo
v_pk_add_f16 v15, v14, v25
global_store_dword v[88:89], v33, off offset:512
global_store_dword v[86:87], v31, off offset:512
global_store_dword v[86:87], v30, off offset:1024
global_store_dword v[86:87], v29, off offset:1536
global_store_dword v[43:44], v11, off
v_pk_add_f16 v11, v14, v28
v_pk_add_f16 v17, v14, v23
v_pk_add_f16 v19, v14, v21
v_pk_add_f16 v18, v14, v18
v_pk_add_f16 v16, v14, v16
v_pk_add_f16 v13, v14, v13
v_pk_add_f16 v12, v14, v12
v_pk_add_f16 v10, v14, v10
v_pk_add_f16 v9, v14, v9
v_pk_add_f16 v8, v14, v8
v_pk_add_f16 v7, v14, v7
v_pk_add_f16 v6, v14, v6
v_pk_add_f16 v5, v14, v5
v_pk_add_f16 v4, v14, v4
v_pk_add_f16 v3, v14, v3
v_pk_add_f16 v2, v14, v2
v_pk_add_f16 v1, v14, v1
v_pk_add_f16 v0, v14, v0
global_store_dword v[88:89], v11, off offset:768
global_store_dword v[86:87], v15, off offset:768
global_store_dword v[45:46], v17, off
global_store_dword v[86:87], v19, off offset:1280
global_store_dword v[47:48], v18, off
global_store_dword v[86:87], v16, off offset:1792
global_store_dword v[49:50], v13, off
global_store_dword v[51:52], v26, off
global_store_dword v[56:57], v12, off
global_store_dword v[58:59], v10, off
global_store_dword v[68:69], v9, off
global_store_dword v[78:79], v8, off
global_store_dword v[80:81], v7, off
global_store_dword v[82:83], v6, off
global_store_dword v[39:40], v5, off
global_store_dword v[53:54], v4, off
global_store_dword v[37:38], v3, off
global_store_dword v[35:36], v2, off
global_store_dword v[41:42], v1, off
global_store_dword v[84:85], v0, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_kernel0
.amdhsa_group_segment_fixed_size 22784
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 100
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end52:
.size tvmgen_default_fused_nn_conv2d_add_kernel0, .Lfunc_end52-tvmgen_default_fused_nn_conv2d_add_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_nn_relu_10_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_nn_relu_10_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_nn_relu_10_kernel0:
v_mul_hi_i32 v1, 0x2e8ba2e9, v0
v_lshrrev_b32_e32 v5, 2, v0
s_mov_b32 s1, 0x66666667
s_mov_b32 s13, 0xba2e8ba3
s_mul_hi_i32 s2, s6, s1
s_movk_i32 s0, 0x6400
v_add_nc_u32_e32 v8, 3, v5
v_add_nc_u32_e32 v5, 6, v5
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v1, 3, v1
s_lshr_b32 s3, s2, 31
v_mul_hi_u32 v10, v8, s13
s_ashr_i32 s7, s2, 2
v_mul_hi_u32 v11, v5, s13
v_add_nc_u32_e32 v2, v1, v2
s_add_i32 s7, s7, s3
s_clause 0x3
s_load_dwordx2 s[14:15], s[4:5], 0x0
s_load_dwordx2 s[16:17], s[4:5], 0x8
s_load_dwordx2 s[8:9], s[4:5], 0x10
s_load_dwordx2 s[10:11], s[4:5], 0x18
s_mul_i32 s2, s7, 10
s_lshl_b32 s4, s7, 4
v_mul_lo_u32 v6, v2, 44
s_sub_i32 s2, s6, s2
v_lshrrev_b32_e32 v10, 3, v10
s_ashr_i32 s12, s2, 1
v_add_nc_u32_e32 v12, s4, v2
v_add_nc_u32_e32 v7, 0x280, v0
v_add_nc_u32_e32 v4, 0x140, v0
v_mul_lo_u32 v2, v2, s0
v_sub_nc_u32_e32 v6, v0, v6
s_mul_i32 s19, s12, 10
v_and_or_b32 v3, v0, 3, 0xffff9a00
v_mul_u32_u24_e32 v10, 11, v10
v_lshrrev_b32_e32 v11, 3, v11
v_ashrrev_i32_e32 v6, 2, v6
v_cmp_lt_i32_e64 s2, 0, v12
v_mul_hi_u32 v9, v7, s13
v_mul_hi_u32 v12, v4, s13
s_mov_b32 s18, 0x64000
v_add_nc_u32_e32 v13, s19, v6
v_add_nc_u32_e32 v2, v3, v2
v_lshlrev_b32_e32 v6, 9, v6
v_sub_nc_u32_e32 v8, v8, v10
s_mul_i32 s5, s7, s18
v_cmp_lt_i32_e64 s3, 0, v13
v_mul_u32_u24_e32 v13, 11, v11
s_mul_i32 s20, s12, 0x1400
v_add_nc_u32_e32 v3, s5, v3
s_add_i32 s21, s20, s5
s_movk_i32 s13, 0x80
v_add3_u32 v10, s21, v2, v6
v_sub_nc_u32_e32 v2, v5, v13
v_lshrrev_b32_e32 v5, 5, v9
v_add_nc_u32_e32 v6, s19, v8
v_lshrrev_b32_e32 v9, 5, v12
s_movk_i32 s23, 0xe00
v_add_nc_u32_e32 v12, s19, v2
v_lshlrev_b32_e32 v2, 9, v2
v_cmp_lt_i32_e32 vcc_lo, 0, v6
v_lshlrev_b32_e32 v6, 9, v8
v_mad_i32_i24 v8, v9, s0, v3
v_mad_i32_i24 v3, v5, s0, v3
v_lshlrev_b32_e32 v1, 1, v0
v_lshlrev_b32_e32 v9, 8, v0
s_movk_i32 s19, 0xff
v_add3_u32 v15, v8, s20, v6
v_lshlrev_b32_e32 v6, 1, v7
v_add_nc_u32_e32 v7, 0x3c0, v0
v_add3_u32 v19, v3, s20, v2
v_lshlrev_b32_e32 v3, 1, v4
v_add_nc_u32_e32 v4, s13, v0
v_and_b32_e32 v29, s23, v6
v_lshlrev_b32_e32 v6, 1, v7
v_lshlrev_b32_e32 v7, 8, v7
v_add_nc_u32_e32 v13, s4, v5
v_and_b32_e32 v28, s19, v4
v_mov_b32_e32 v5, 0xe00
v_lshlrev_b32_e32 v4, 1, v4
v_and_b32_e32 v32, 0x40000, v7
v_add_nc_u32_e32 v7, 0x480, v1
s_movk_i32 s21, 0x600
v_add_nc_u32_e32 v2, 64, v0
v_and_b32_e32 v31, s21, v6
v_add_nc_u32_e32 v6, 0x50000, v9
v_cmp_lt_i32_e64 s4, 0, v12
v_add_nc_u32_e32 v8, 0x200, v1
v_and_b32_e32 v35, v5, v7
v_add_nc_u32_e32 v7, 0x700, v1
v_and_b32_e32 v45, v5, v4
v_add_nc_u32_e32 v4, 0x380, v1
v_add_nc_u32_e32 v12, 0x78000, v9
v_and_b32_e32 v26, s19, v2
v_and_b32_e32 v21, s19, v0
s_mov_b32 s19, 0xc0000
v_cmp_gt_i32_e64 s5, 48, v13
v_and_b32_e32 v34, s19, v6
v_add_nc_u32_e32 v6, s18, v9
v_add_nc_u32_e32 v13, 0x8c000, v9
v_lshlrev_b32_e32 v2, 1, v2
v_and_b32_e32 v33, s23, v8
v_and_b32_e32 v37, s21, v7
v_and_b32_e32 v38, s19, v12
v_add_nc_u32_e32 v7, 0x680, v1
v_and_b32_e32 v47, v5, v4
v_mov_b32_e32 v8, 0xc0000
v_add_nc_u32_e32 v12, 0xb4000, v9
v_add_nc_u32_e32 v4, 0x104000, v9
s_lshl_b32 s6, s6, 8
s_movk_i32 s20, 0x100
v_mul_hi_i32 v18, v0, s1
s_and_b32 s6, s6, s20
v_and_b32_e32 v36, s19, v6
v_and_b32_e32 v40, s19, v13
s_mov_b32 s19, 0x140000
v_and_b32_e32 v43, s21, v7
v_add_nc_u32_e32 v7, 0x300, v1
v_and_b32_e32 v44, v8, v12
v_add_nc_u32_e32 v12, 0x118000, v9
v_and_b32_e32 v2, v5, v2
v_and_b32_e32 v4, s19, v4
v_or_b32_e32 v13, s6, v26
v_and_b32_e32 v27, s23, v3
v_add_nc_u32_e32 v3, 0xc0, v0
v_add_nc_u32_e32 v6, 0xa0000, v9
v_and_b32_e32 v7, v5, v7
v_or3_b32 v51, v13, v4, v2
v_and_b32_e32 v12, s19, v12
v_or_b32_e32 v17, s6, v28
v_lshrrev_b32_e32 v2, 31, v18
v_ashrrev_i32_e32 v4, 6, v18
v_and_b32_e32 v30, 0xff, v3
v_and_b32_e32 v42, v8, v6
v_add_nc_u32_e32 v14, 0x580, v1
v_add_nc_u32_e32 v16, 0x12c000, v9
v_add_nc_u32_e32 v6, 0xdc000, v9
v_or3_b32 v52, v17, v12, v7
v_add_nc_u32_e32 v7, v4, v2
s_mov_b32 s18, 0x1c0000
v_lshlrev_b32_e32 v3, 1, v3
v_and_b32_e32 v48, s18, v6
v_add_nc_u32_e32 v6, 0xf0000, v9
v_and_b32_e32 v16, s19, v16
v_and_b32_e32 v14, v5, v14
v_or_b32_e32 v20, s6, v30
v_mul_lo_u32 v2, 0xa0, v7
v_and_b32_e32 v39, v5, v3
v_add_nc_u32_e32 v3, 0x400, v1
v_and_b32_e32 v50, s18, v6
v_or3_b32 v53, v20, v16, v14
v_mov_b32_e32 v8, 0x1c0000
v_add_nc_u32_e32 v22, 0x154000, v9
v_add_nc_u32_e32 v6, 0x168000, v9
v_add_nc_u32_e32 v12, 0x17c000, v9
v_add_nc_u32_e32 v13, 0x190000, v9
v_add_nc_u32_e32 v14, 0x1a4000, v9
v_add_nc_u32_e32 v4, 0x1b8000, v9
v_and_b32_e32 v41, v5, v3
v_add_nc_u32_e32 v3, 0xc8000, v9
v_and_b32_e32 v54, v8, v22
v_and_b32_e32 v55, v8, v6
v_and_b32_e32 v56, v8, v12
v_and_b32_e32 v57, v8, v13
v_and_b32_e32 v58, v8, v14
v_and_b32_e32 v59, v8, v4
v_sub_nc_u32_e32 v8, v0, v2
v_add_nc_u32_e32 v12, 0x1e0000, v9
v_add_nc_u32_e32 v6, 0x1cc000, v9
v_add_nc_u32_e32 v13, 0x1f4000, v9
s_mov_b32 s1, 0x3c0000
v_and_b32_e32 v46, s18, v3
v_add_nc_u32_e32 v2, 0x208000, v9
v_ashrrev_i32_e32 v4, 2, v8
s_movk_i32 s18, 0x58
v_and_b32_e32 v61, s1, v12
v_mul_lo_u32 v12, v7, s18
v_and_b32_e32 v60, s1, v6
v_and_b32_e32 v62, s1, v13
s_mov_b32 s1, 0x240000
v_add_nc_u32_e32 v3, s21, v1
v_and_b32_e32 v63, s1, v2
v_and_b32_e32 v2, 0x7ffffff8, v4
v_add_nc_u32_e32 v6, 0x230000, v9
v_add_nc_u32_e32 v13, s6, v0
v_add_nc_u32_e32 v4, 0x21c000, v9
v_and_b32_e32 v49, s21, v3
v_and_b32_e32 v3, v5, v3
v_add_nc_u32_e32 v2, v12, v2
v_and_or_b32 v5, v6, s1, v13
v_lshlrev_b32_e32 v6, 2, v0
s_movk_i32 s22, 0x4800
v_and_b32_e32 v64, s1, v4
v_lshl_add_u32 v66, v2, 1, s22
v_add_nc_u32_e32 v65, v5, v3
v_and_b32_e32 v13, 0x7c, v6
v_or_b32_e32 v11, s22, v1
v_cmp_gt_i32_e64 s0, 0x6c, v0
v_cmp_gt_i32_e64 s1, s20, v0
v_and_b32_e32 v25, s21, v1
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v24, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v20, 0
s_mov_b32 s19, 0
s_and_b32 s3, s2, s3
s_and_b32 s4, s5, s4
BB53_1:
v_mov_b32_e32 v67, 0
s_lshl_b32 s5, s19, 2
s_waitcnt lgkmcnt(0)
s_barrier
s_and_saveexec_b32 s20, s3
s_cbranch_execz BB53_3
v_add_nc_u32_e32 v67, s5, v10
v_ashrrev_i32_e32 v68, 31, v67
v_lshlrev_b64 v[67:68], 1, v[67:68]
v_add_co_u32 v67, s2, s14, v67
v_add_co_ci_u32_e64 v68, s2, s15, v68, s2
global_load_ushort v67, v[67:68], off
BB53_3:
s_or_b32 exec_lo, exec_lo, s20
v_mov_b32_e32 v68, 0
s_waitcnt vmcnt(0)
ds_write_b16 v11, v67
s_and_saveexec_b32 s20, vcc_lo
s_cbranch_execz BB53_5
v_add_nc_u32_e32 v67, s5, v15
v_ashrrev_i32_e32 v68, 31, v67
v_lshlrev_b64 v[67:68], 1, v[67:68]
v_add_co_u32 v67, s2, s14, v67
v_add_co_ci_u32_e64 v68, s2, s15, v68, s2
global_load_ushort v68, v[67:68], off
BB53_5:
s_or_b32 exec_lo, exec_lo, s20
s_waitcnt vmcnt(0)
ds_write_b16 v11, v68 offset:640
s_and_saveexec_b32 s20, s0
s_cbranch_execz BB53_9
v_mov_b32_e32 v67, 0
s_and_saveexec_b32 s21, s4
s_cbranch_execz BB53_8
v_add_nc_u32_e32 v67, s5, v19
v_ashrrev_i32_e32 v68, 31, v67
v_lshlrev_b64 v[67:68], 1, v[67:68]
v_add_co_u32 v67, s2, s14, v67
v_add_co_ci_u32_e64 v68, s2, s15, v68, s2
global_load_ushort v67, v[67:68], off
BB53_8:
s_or_b32 exec_lo, exec_lo, s21
s_waitcnt vmcnt(0)
ds_write_b16 v11, v67 offset:1280
BB53_9:
s_or_b32 exec_lo, exec_lo, s20
s_lshl_b32 s5, s19, 11
v_add_nc_u32_e32 v68, s5, v27
v_or_b32_e32 v67, s5, v25
v_add_nc_u32_e32 v70, s5, v29
v_add_nc_u32_e32 v72, s5, v32
v_add_nc_u32_e32 v73, s5, v33
v_or3_b32 v69, v68, s6, v26
v_or3_b32 v67, v67, s6, v21
v_or3_b32 v71, v70, s6, v28
v_or_b32_e32 v74, v72, v31
v_or3_b32 v108, v73, v21, s6
v_ashrrev_i32_e32 v70, 31, v69
v_ashrrev_i32_e32 v68, 31, v67
v_ashrrev_i32_e32 v72, 31, v71
v_or3_b32 v73, v74, s6, v30
v_add_nc_u32_e32 v75, v108, v34
v_lshlrev_b64 v[76:77], 1, v[69:70]
v_add_nc_u32_e32 v70, s5, v35
v_lshlrev_b64 v[67:68], 1, v[67:68]
v_lshlrev_b64 v[78:79], 1, v[71:72]
v_ashrrev_i32_e32 v74, 31, v73
v_add_nc_u32_e32 v98, s5, v51
v_or3_b32 v110, v70, s6, v26
v_add_nc_u32_e32 v70, s5, v38
v_add_co_u32 v67, s2, s16, v67
v_lshlrev_b64 v[72:73], 1, v[73:74]
v_add_co_ci_u32_e64 v68, s2, s17, v68, s2
v_add_co_u32 v80, s2, s16, v76
v_ashrrev_i32_e32 v76, 31, v75
v_or_b32_e32 v70, v70, v37
v_add_co_ci_u32_e64 v81, s2, s17, v77, s2
v_add_co_u32 v77, s2, s16, v78
v_add_nc_u32_e32 v82, v110, v36
v_add_co_ci_u32_e64 v78, s2, s17, v79, s2
v_or3_b32 v84, v70, s6, v28
v_lshlrev_b64 v[74:75], 1, v[75:76]
v_add_nc_u32_e32 v76, s5, v39
v_add_nc_u32_e32 v70, s5, v41
v_add_nc_u32_e32 v79, s5, v44
v_ashrrev_i32_e32 v83, 31, v82
v_ashrrev_i32_e32 v85, 31, v84
v_or3_b32 v76, v76, s6, v30
v_or3_b32 v116, v70, v21, s6
v_or_b32_e32 v70, v79, v43
v_add_nc_u32_e32 v79, s5, v45
v_add_co_u32 v72, s2, s16, v72
v_add_nc_u32_e32 v86, v76, v40
v_add_nc_u32_e32 v88, v116, v42
v_or3_b32 v90, v70, s6, v26
v_add_nc_u32_e32 v70, s5, v47
v_or3_b32 v79, v79, s6, v28
v_lshlrev_b64 v[82:83], 1, v[82:83]
v_ashrrev_i32_e32 v87, 31, v86
v_add_co_ci_u32_e64 v73, s2, s17, v73, s2
v_or3_b32 v122, v70, s6, v30
v_add_nc_u32_e32 v70, s5, v50
v_add_co_u32 v74, s2, s16, v74
v_lshlrev_b64 v[84:85], 1, v[84:85]
v_ashrrev_i32_e32 v89, 31, v88
v_add_co_ci_u32_e64 v75, s2, s17, v75, s2
v_add_nc_u32_e32 v92, v79, v46
v_add_co_u32 v82, s2, s16, v82
v_or_b32_e32 v70, v70, v49
v_lshlrev_b64 v[86:87], 1, v[86:87]
v_ashrrev_i32_e32 v91, 31, v90
v_add_co_ci_u32_e64 v83, s2, s17, v83, s2
v_add_nc_u32_e32 v94, v122, v48
v_add_co_u32 v84, s2, s16, v84
v_lshlrev_b64 v[88:89], 1, v[88:89]
v_ashrrev_i32_e32 v93, 31, v92
v_add_co_ci_u32_e64 v85, s2, s17, v85, s2
v_or3_b32 v96, v70, s6, v21
v_add_co_u32 v86, s2, s16, v86
v_lshlrev_b64 v[90:91], 1, v[90:91]
v_ashrrev_i32_e32 v95, 31, v94
v_add_co_ci_u32_e64 v87, s2, s17, v87, s2
v_add_co_u32 v88, s2, s16, v88
v_lshlrev_b64 v[92:93], 1, v[92:93]
v_ashrrev_i32_e32 v97, 31, v96
v_add_co_ci_u32_e64 v89, s2, s17, v89, s2
v_add_nc_u32_e32 v100, s5, v52
v_add_nc_u32_e32 v70, s5, v56
v_add_co_u32 v90, s2, s16, v90
v_lshlrev_b64 v[94:95], 1, v[94:95]
v_ashrrev_i32_e32 v99, 31, v98
v_add_co_ci_u32_e64 v91, s2, s17, v91, s2
v_add_nc_u32_e32 v102, s5, v53
v_add_co_u32 v92, s2, s16, v92
v_lshlrev_b64 v[96:97], 1, v[96:97]
v_ashrrev_i32_e32 v101, 31, v100
v_add_nc_u32_e32 v104, v71, v55
v_or_b32_e32 v71, v70, v31
v_add_co_ci_u32_e64 v93, s2, s17, v93, s2
v_add_nc_u32_e32 v69, v69, v54
v_add_co_u32 v94, s2, s16, v94
v_lshlrev_b64 v[98:99], 1, v[98:99]
v_ashrrev_i32_e32 v103, 31, v102
v_add_co_ci_u32_e64 v95, s2, s17, v95, s2
v_add_co_u32 v96, s2, s16, v96
v_or3_b32 v106, v71, s6, v30
v_add_nc_u32_e32 v71, s5, v59
v_lshlrev_b64 v[100:101], 1, v[100:101]
v_ashrrev_i32_e32 v70, 31, v69
v_add_co_ci_u32_e64 v97, s2, s17, v97, s2
v_add_co_u32 v98, s2, s16, v98
v_lshlrev_b64 v[102:103], 1, v[102:103]
v_ashrrev_i32_e32 v105, 31, v104
v_add_co_ci_u32_e64 v99, s2, s17, v99, s2
v_add_nc_u32_e32 v108, v108, v57
v_or_b32_e32 v71, v71, v37
v_add_co_u32 v100, s2, s16, v100
v_lshlrev_b64 v[69:70], 1, v[69:70]
v_ashrrev_i32_e32 v107, 31, v106
v_add_co_ci_u32_e64 v101, s2, s17, v101, s2
v_add_nc_u32_e32 v110, v110, v58
v_add_co_u32 v102, s2, s16, v102
v_lshlrev_b64 v[104:105], 1, v[104:105]
v_ashrrev_i32_e32 v109, 31, v108
v_or3_b32 v112, v71, s6, v28
v_add_nc_u32_e32 v71, s5, v62
v_add_co_ci_u32_e64 v103, s2, s17, v103, s2
v_add_co_u32 v69, s2, s16, v69
v_lshlrev_b64 v[106:107], 1, v[106:107]
v_ashrrev_i32_e32 v111, 31, v110
v_add_co_ci_u32_e64 v70, s2, s17, v70, s2
v_add_nc_u32_e32 v114, v76, v60
v_add_co_u32 v104, s2, s16, v104
v_or_b32_e32 v71, v71, v43
v_lshlrev_b64 v[108:109], 1, v[108:109]
v_ashrrev_i32_e32 v113, 31, v112
v_add_co_ci_u32_e64 v105, s2, s17, v105, s2
v_add_nc_u32_e32 v116, v116, v61
v_add_co_u32 v106, s2, s16, v106
v_lshlrev_b64 v[110:111], 1, v[110:111]
v_ashrrev_i32_e32 v115, 31, v114
v_add_co_ci_u32_e64 v107, s2, s17, v107, s2
v_or3_b32 v118, v71, s6, v26
v_add_co_u32 v108, s2, s16, v108
v_lshlrev_b64 v[112:113], 1, v[112:113]
v_ashrrev_i32_e32 v117, 31, v116
v_add_co_ci_u32_e64 v109, s2, s17, v109, s2
v_add_nc_u32_e32 v120, v79, v63
v_add_co_u32 v110, s2, s16, v110
v_lshlrev_b64 v[114:115], 1, v[114:115]
v_ashrrev_i32_e32 v119, 31, v118
v_add_co_ci_u32_e64 v111, s2, s17, v111, s2
v_add_nc_u32_e32 v122, v122, v64
v_add_co_u32 v112, s2, s16, v112
v_lshlrev_b64 v[116:117], 1, v[116:117]
v_ashrrev_i32_e32 v121, 31, v120
v_add_co_ci_u32_e64 v113, s2, s17, v113, s2
v_add_co_u32 v114, s2, s16, v114
v_lshlrev_b64 v[118:119], 1, v[118:119]
v_ashrrev_i32_e32 v123, 31, v122
v_add_co_ci_u32_e64 v115, s2, s17, v115, s2
v_add_co_u32 v116, s2, s16, v116
v_lshlrev_b64 v[120:121], 1, v[120:121]
v_add_co_ci_u32_e64 v117, s2, s17, v117, s2
v_add_co_u32 v118, s2, s16, v118
v_lshlrev_b64 v[122:123], 1, v[122:123]
v_add_co_ci_u32_e64 v119, s2, s17, v119, s2
v_add_co_u32 v120, s2, s16, v120
v_add_co_ci_u32_e64 v121, s2, s17, v121, s2
v_add_co_u32 v122, s2, s16, v122
v_add_co_ci_u32_e64 v123, s2, s17, v123, s2
v_add_co_u32 v124, s2, 0x280000, v67
v_add_co_ci_u32_e64 v125, s2, 0, v68, s2
s_clause 0x1b
global_load_ushort v67, v[67:68], off
global_load_ushort v68, v[80:81], off
global_load_ushort v71, v[77:78], off
global_load_ushort v72, v[72:73], off
global_load_ushort v73, v[74:75], off
global_load_ushort v74, v[82:83], off
global_load_ushort v75, v[84:85], off
global_load_ushort v76, v[86:87], off
global_load_ushort v77, v[88:89], off
global_load_ushort v78, v[90:91], off
global_load_ushort v79, v[92:93], off
global_load_ushort v80, v[94:95], off
global_load_ushort v81, v[96:97], off
global_load_ushort v82, v[98:99], off
global_load_ushort v83, v[100:101], off
global_load_ushort v84, v[102:103], off
global_load_ushort v85, v[124:125], off
global_load_ushort v69, v[69:70], off
global_load_ushort v70, v[104:105], off
global_load_ushort v86, v[106:107], off
global_load_ushort v87, v[108:109], off
global_load_ushort v88, v[110:111], off
global_load_ushort v89, v[112:113], off
global_load_ushort v90, v[114:115], off
global_load_ushort v91, v[116:117], off
global_load_ushort v92, v[118:119], off
global_load_ushort v93, v[120:121], off
global_load_ushort v94, v[122:123], off
s_waitcnt vmcnt(27)
ds_write_b16 v1, v67
s_waitcnt vmcnt(26)
ds_write_b16 v1, v68 offset:640
s_waitcnt vmcnt(25)
ds_write_b16 v1, v71 offset:1280
s_waitcnt vmcnt(24)
ds_write_b16 v1, v72 offset:1920
s_waitcnt vmcnt(23)
ds_write_b16 v1, v73 offset:2560
s_waitcnt vmcnt(22)
ds_write_b16 v1, v74 offset:3200
s_waitcnt vmcnt(21)
ds_write_b16 v1, v75 offset:3840
s_waitcnt vmcnt(20)
ds_write_b16 v1, v76 offset:4480
s_waitcnt vmcnt(19)
ds_write_b16 v1, v77 offset:5120
s_waitcnt vmcnt(18)
ds_write_b16 v1, v78 offset:5760
s_waitcnt vmcnt(17)
ds_write_b16 v1, v79 offset:6400
s_waitcnt vmcnt(16)
ds_write_b16 v1, v80 offset:7040
s_waitcnt vmcnt(15)
ds_write_b16 v1, v81 offset:7680
s_waitcnt vmcnt(14)
ds_write_b16 v1, v82 offset:8320
s_waitcnt vmcnt(13)
ds_write_b16 v1, v83 offset:8960
s_waitcnt vmcnt(12)
ds_write_b16 v1, v84 offset:9600
s_waitcnt vmcnt(11)
ds_write_b16 v1, v85 offset:10240
s_waitcnt vmcnt(10)
ds_write_b16 v1, v69 offset:10880
s_waitcnt vmcnt(9)
ds_write_b16 v1, v70 offset:11520
s_waitcnt vmcnt(8)
ds_write_b16 v1, v86 offset:12160
s_waitcnt vmcnt(7)
ds_write_b16 v1, v87 offset:12800
s_waitcnt vmcnt(6)
ds_write_b16 v1, v88 offset:13440
s_waitcnt vmcnt(5)
ds_write_b16 v1, v89 offset:14080
s_waitcnt vmcnt(4)
ds_write_b16 v1, v90 offset:14720
s_waitcnt vmcnt(3)
ds_write_b16 v1, v91 offset:15360
s_waitcnt vmcnt(2)
ds_write_b16 v1, v92 offset:16000
s_waitcnt vmcnt(1)
ds_write_b16 v1, v93 offset:16640
s_waitcnt vmcnt(0)
ds_write_b16 v1, v94 offset:17280
s_and_saveexec_b32 s20, s1
s_cbranch_execz BB53_11
v_add_nc_u32_e32 v67, s5, v65
v_ashrrev_i32_e32 v68, 31, v67
v_lshlrev_b64 v[67:68], 1, v[67:68]
v_add_co_u32 v67, s2, s16, v67
v_add_co_ci_u32_e64 v68, s2, s17, v68, s2
global_load_ushort v67, v[67:68], off
s_waitcnt vmcnt(0)
ds_write_b16 v1, v67 offset:17920
BB53_11:
s_or_b32 exec_lo, exec_lo, s20
v_mov_b32_e32 v67, v66
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
BB53_12:
s_mul_i32 s5, s2, 0xc00
v_or_b32_e32 v68, s5, v13
s_mov_b32 s5, 0
v_lshlrev_b32_e32 v68, 1, v68
BB53_13:
v_add_nc_u32_e32 v81, s5, v67
v_add_nc_u32_e32 v91, 0x400, v68
ds_read2_b64 v[69:72], v68 offset0:32 offset1:64
ds_read2_b64 v[73:76], v68 offset0:160 offset1:192
ds_read2_b32 v[85:86], v68 offset1:1
ds_read_b64 v[87:88], v68 offset:768
ds_read_b64 v[89:90], v68 offset:1792
v_add_nc_u32_e32 v68, 0x800, v68
s_add_i32 s5, s5, 8
ds_read2_b64 v[77:80], v81 offset1:44
ds_read2_b64 v[81:84], v81 offset0:88 offset1:132
ds_read2_b32 v[91:92], v91 offset1:1
s_cmp_lg_u32 s5, 24
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v24, v77, v85, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v79, v85, v23 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v17, v81, v85, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v83, v85, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v77, v69, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v79, v69, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v81, v69, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v83, v69, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v77, v86, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v77, v70, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v79, v86, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v79, v70, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v81, v86, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v81, v70, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v83, v86, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v83, v70, v0 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v77, v71, v24 op_sel:[1,0,0]
v_pk_fma_f16 v22, v77, v87, v22 op_sel:[1,0,0]
v_pk_fma_f16 v23, v79, v71, v23 op_sel:[1,0,0]
v_pk_fma_f16 v5, v79, v87, v5 op_sel:[1,0,0]
v_pk_fma_f16 v17, v81, v71, v17 op_sel:[1,0,0]
v_pk_fma_f16 v4, v81, v87, v4 op_sel:[1,0,0]
v_pk_fma_f16 v16, v83, v71, v16 op_sel:[1,0,0]
v_pk_fma_f16 v2, v83, v87, v2 op_sel:[1,0,0]
v_pk_fma_f16 v18, v77, v72, v18 op_sel:[1,0,0]
v_pk_fma_f16 v20, v77, v88, v20 op_sel:[1,0,0]
v_pk_fma_f16 v14, v79, v72, v14 op_sel:[1,0,0]
v_pk_fma_f16 v6, v79, v88, v6 op_sel:[1,0,0]
v_pk_fma_f16 v12, v81, v72, v12 op_sel:[1,0,0]
v_pk_fma_f16 v3, v81, v88, v3 op_sel:[1,0,0]
v_pk_fma_f16 v9, v83, v72, v9 op_sel:[1,0,0]
v_pk_fma_f16 v0, v83, v88, v0 op_sel:[1,0,0]
v_pk_fma_f16 v22, v78, v73, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v80, v73, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v82, v73, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v84, v73, v2 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v24, v78, v91, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v80, v91, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v82, v91, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v84, v91, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v78, v92, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v78, v74, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v80, v92, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v80, v74, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v82, v92, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v82, v74, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v84, v92, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v84, v74, v0 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v78, v89, v22 op_sel:[1,0,0]
v_pk_fma_f16 v5, v80, v89, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v82, v89, v4 op_sel:[1,0,0]
v_pk_fma_f16 v2, v84, v89, v2 op_sel:[1,0,0]
v_pk_fma_f16 v24, v78, v75, v24 op_sel:[1,0,0]
v_pk_fma_f16 v23, v80, v75, v23 op_sel:[1,0,0]
v_pk_fma_f16 v17, v82, v75, v17 op_sel:[1,0,0]
v_pk_fma_f16 v16, v84, v75, v16 op_sel:[1,0,0]
v_pk_fma_f16 v18, v78, v76, v18 op_sel:[1,0,0]
v_pk_fma_f16 v20, v78, v90, v20 op_sel:[1,0,0]
v_pk_fma_f16 v14, v80, v76, v14 op_sel:[1,0,0]
v_pk_fma_f16 v6, v80, v90, v6 op_sel:[1,0,0]
v_pk_fma_f16 v12, v82, v76, v12 op_sel:[1,0,0]
v_pk_fma_f16 v3, v82, v90, v3 op_sel:[1,0,0]
v_pk_fma_f16 v9, v84, v76, v9 op_sel:[1,0,0]
v_pk_fma_f16 v0, v84, v90, v0 op_sel:[1,0,0]
s_cbranch_scc1 BB53_13
v_add_nc_u32_e32 v67, s18, v67
s_add_i32 s2, s2, 1
s_cmp_eq_u32 s2, 3
s_cbranch_scc0 BB53_12
s_add_i32 s19, s19, 1
s_cmp_eq_u32 s19, s13
s_cbranch_scc0 BB53_1
v_or_b32_e32 v1, s6, v13
v_mul_lo_u32 v7, 0x3200, v7
s_mov_b32 s0, 0x19000
v_lshlrev_b32_e32 v8, 4, v8
s_mul_i32 s7, s7, s0
v_lshlrev_b32_e32 v1, 1, v1
s_mulk_i32 s12, 0xa00
v_and_b32_e32 v8, 0xfffffe00, v8
v_add_nc_u32_e32 v7, s7, v7
s_clause 0x5
global_load_ushort v15, v1, s[10:11] offset:256
global_load_dword v19, v1, s[10:11]
global_load_ushort v21, v1, s[10:11] offset:258
global_load_ushort v41, v1, s[10:11] offset:260
global_load_ushort v42, v1, s[10:11] offset:262
global_load_dword v1, v1, s[10:11] offset:4
v_or3_b32 v7, v7, s6, v13
v_mov_b32_e32 v13, 0xffff
v_add3_u32 v7, v7, s12, v8
v_ashrrev_i32_e32 v8, 31, v7
v_add_nc_u32_e32 v10, 0x6402, v7
v_add_nc_u32_e32 v25, 0x6482, v7
v_add_nc_u32_e32 v27, 0xc802, v7
v_add_nc_u32_e32 v29, 0xc882, v7
v_add_nc_u32_e32 v31, 0x12c02, v7
v_add_nc_u32_e32 v33, 0x12c82, v7
v_lshlrev_b64 v[7:8], 1, v[7:8]
v_ashrrev_i32_e32 v11, 31, v10
v_ashrrev_i32_e32 v26, 31, v25
v_ashrrev_i32_e32 v28, 31, v27
v_ashrrev_i32_e32 v30, 31, v29
v_ashrrev_i32_e32 v32, 31, v31
v_add_co_u32 v7, vcc_lo, s8, v7
v_lshlrev_b64 v[10:11], 1, v[10:11]
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
v_lshlrev_b64 v[25:26], 1, v[25:26]
v_lshlrev_b64 v[27:28], 1, v[27:28]
v_add_co_u32 v35, vcc_lo, 0x25800, v7
v_lshlrev_b64 v[29:30], 1, v[29:30]
v_add_co_ci_u32_e32 v36, vcc_lo, 0, v8, vcc_lo
v_add_co_u32 v37, vcc_lo, s0, v7
v_ashrrev_i32_e32 v34, 31, v33
v_add_co_ci_u32_e32 v38, vcc_lo, 0, v8, vcc_lo
v_add_co_u32 v39, vcc_lo, 0xc800, v7
v_lshlrev_b64 v[31:32], 1, v[31:32]
v_add_co_ci_u32_e32 v40, vcc_lo, 0, v8, vcc_lo
v_add_co_u32 v10, vcc_lo, s8, v10
v_lshlrev_b64 v[33:34], 1, v[33:34]
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
v_add_co_u32 v25, vcc_lo, s8, v25
v_add_co_ci_u32_e32 v26, vcc_lo, s9, v26, vcc_lo
v_add_co_u32 v27, vcc_lo, s8, v27
v_add_co_ci_u32_e32 v28, vcc_lo, s9, v28, vcc_lo
v_add_co_u32 v29, vcc_lo, s8, v29
v_add_co_ci_u32_e32 v30, vcc_lo, s9, v30, vcc_lo
v_add_co_u32 v31, vcc_lo, s8, v31
v_add_co_ci_u32_e32 v32, vcc_lo, s9, v32, vcc_lo
v_add_co_u32 v33, vcc_lo, s8, v33
v_add_co_ci_u32_e32 v34, vcc_lo, s9, v34, vcc_lo
s_waitcnt vmcnt(5)
v_add_f16_e32 v43, v15, v22
v_and_b32_e32 v15, v13, v15
s_waitcnt vmcnt(4)
v_pk_add_f16 v23, v19, v23
s_waitcnt vmcnt(2)
v_and_b32_e32 v13, v13, v41
v_pk_add_f16 v16, v19, v16
v_pk_add_f16 v17, v19, v17
v_lshl_or_b32 v15, v21, 16, v15
v_pk_add_f16 v24, v19, v24
s_waitcnt vmcnt(1)
v_lshl_or_b32 v13, v42, 16, v13
v_add_f16_e32 v19, v41, v20
v_add_f16_sdwa v22, v21, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_add_f16 v2, v15, v2
v_pk_add_f16 v4, v15, v4
s_waitcnt vmcnt(0)
v_pk_add_f16 v18, v1, v18
v_pk_add_f16 v5, v15, v5
v_add_f16_sdwa v20, v42, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_add_f16 v14, v1, v14
v_pk_add_f16 v6, v13, v6
v_pk_add_f16 v12, v1, v12
v_pk_add_f16 v1, v1, v9
v_pk_add_f16 v3, v13, v3
v_pk_add_f16 v0, v13, v0
v_max_f16_e32 v9, 0, v43
v_pk_max_f16 v23, v23, 0
v_pk_max_f16 v16, v16, 0
v_pk_max_f16 v17, v17, 0
v_pk_max_f16 v2, v2, 0
v_pk_max_f16 v24, v24, 0
v_max_f16_e32 v19, 0, v19
v_pk_max_f16 v4, v4, 0
v_max_f16_e32 v22, 0, v22
v_pk_max_f16 v18, v18, 0
v_pk_max_f16 v5, v5, 0
v_max_f16_e32 v20, 0, v20
v_pk_max_f16 v14, v14, 0
v_pk_max_f16 v6, v6, 0
global_store_short v[7:8], v9, off offset:256
global_store_dword v[7:8], v24, off
global_store_short v[7:8], v22, off offset:258
v_pk_max_f16 v12, v12, 0
v_pk_max_f16 v1, v1, 0
global_store_dword v[35:36], v16, off
global_store_dword v[37:38], v17, off
global_store_dword v[39:40], v23, off
global_store_short v[7:8], v19, off offset:260
global_store_dword v[7:8], v18, off offset:4
global_store_short v[7:8], v20, off offset:262
v_pk_max_f16 v3, v3, 0
v_pk_max_f16 v0, v0, 0
global_store_dword v[35:36], v2, off offset:256
global_store_dword v[37:38], v4, off offset:256
global_store_dword v[39:40], v5, off offset:256
global_store_dword v[10:11], v14, off
global_store_dword v[25:26], v6, off
global_store_dword v[27:28], v12, off
global_store_dword v[29:30], v3, off
global_store_dword v[31:32], v1, off
global_store_dword v[33:34], v0, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_nn_relu_10_kernel0
.amdhsa_group_segment_fixed_size 19928
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 126
.amdhsa_next_free_sgpr 24
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end53:
.size tvmgen_default_fused_nn_conv2d_add_nn_relu_10_kernel0, .Lfunc_end53-tvmgen_default_fused_nn_conv2d_add_nn_relu_10_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_nn_relu_11_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_nn_relu_11_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_nn_relu_11_kernel0:
s_mov_b32 s0, 0x66666667
s_mov_b32 s9, 0xc800
v_mul_hi_i32 v1, v0, s0
s_mul_hi_i32 s0, s6, s0
s_mov_b32 s10, 0x64000
s_lshr_b32 s7, s0, 31
s_ashr_i32 s0, s0, 2
s_clause 0x3
s_load_dwordx2 s[12:13], s[4:5], 0x0
s_load_dwordx2 s[14:15], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[4:5], s[4:5], 0x18
s_add_i32 s7, s0, s7
v_lshlrev_b32_e32 v19, 3, v0
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v1, 6, v1
s_mul_i32 s16, s7, s10
s_mul_i32 s0, s7, 10
s_lshl_b32 s1, s6, 8
s_sub_i32 s0, s6, s0
v_add_nc_u32_e32 v16, v1, v2
v_and_b32_e32 v1, 31, v0
s_movk_i32 s8, 0x2800
s_ashr_i32 s6, s0, 1
v_lshlrev_b32_e32 v20, 4, v0
v_mul_lo_u32 v2, 0xa0, v16
v_mul_lo_u32 v3, v16, s9
v_mul_lo_u32 v8, 0x280, v16
v_lshlrev_b32_e32 v21, 3, v1
s_mul_i32 s0, s6, s8
v_or_b32_e32 v5, 2, v19
v_or_b32_e32 v6, 3, v19
v_or_b32_e32 v7, 4, v19
v_sub_nc_u32_e32 v17, v0, v2
v_add_nc_u32_e32 v3, s16, v3
v_or_b32_e32 v2, 1, v19
s_mov_b32 s11, 0x8000
v_and_b32_e32 v25, 0xfa, v5
v_ashrrev_i32_e32 v4, 5, v17
v_lshl_or_b32 v1, v1, 1, v3
v_and_b32_e32 v23, 0xf9, v2
v_or_b32_e32 v2, 6, v19
v_and_b32_e32 v26, 0xfb, v6
v_lshlrev_b32_e32 v3, 11, v4
v_and_b32_e32 v27, 0xfc, v7
v_lshl_or_b32 v18, v0, 2, s11
v_and_b32_e32 v29, 0xfe, v2
v_cmp_gt_i32_e32 vcc_lo, 0x80, v0
v_add3_u32 v24, v1, s0, v3
v_lshl_add_u32 v3, v4, 6, v8
v_or_b32_e32 v1, 5, v19
v_and_b32_e32 v22, 0x3e00, v20
v_or_b32_e32 v30, 7, v19
v_mov_b32_e32 v0, 0
v_lshl_add_u32 v31, v3, 1, s11
v_and_b32_e32 v28, 0xfd, v1
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_and_b32 s1, s1, 0x100
s_mov_b32 s11, 0
s_movk_i32 s16, 0x5000
s_movk_i32 s17, 0x7800
s_mov_b32 s18, 0xa000
s_mov_b32 s19, 0xf000
BB54_1:
s_lshl_b32 s0, s11, 15
v_or3_b32 v79, s0, v22, s1
v_or_b32_e32 v32, v79, v21
v_or_b32_e32 v34, v79, v25
v_or_b32_e32 v36, v79, v27
v_or_b32_e32 v38, v79, v29
v_ashrrev_i32_e32 v33, 31, v32
v_ashrrev_i32_e32 v35, 31, v34
v_ashrrev_i32_e32 v37, 31, v36
v_ashrrev_i32_e32 v39, 31, v38
v_lshlrev_b64 v[32:33], 1, v[32:33]
v_lshlrev_b64 v[34:35], 1, v[34:35]
v_lshlrev_b64 v[40:41], 1, v[36:37]
v_lshlrev_b64 v[38:39], 1, v[38:39]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v36, s0, s14, v32
v_add_co_ci_u32_e64 v37, s0, s15, v33, s0
v_add_co_u32 v34, s0, s14, v34
v_add_co_ci_u32_e64 v35, s0, s15, v35, s0
v_add_co_u32 v32, s0, s14, v40
v_add_co_ci_u32_e64 v33, s0, s15, v41, s0
v_add_co_u32 v40, s0, s8, v36
v_add_co_ci_u32_e64 v41, s0, 0, v37, s0
v_add_co_u32 v38, s0, s14, v38
v_add_co_ci_u32_e64 v39, s0, s15, v39, s0
v_add_co_u32 v42, s0, s8, v34
v_add_co_ci_u32_e64 v43, s0, 0, v35, s0
v_add_co_u32 v44, s0, s8, v32
v_add_co_ci_u32_e64 v45, s0, 0, v33, s0
v_add_co_u32 v46, s0, s8, v38
v_add_co_ci_u32_e64 v47, s0, 0, v39, s0
v_add_co_u32 v52, s0, s16, v36
v_add_co_ci_u32_e64 v53, s0, 0, v37, s0
v_add_co_u32 v54, s0, s16, v34
v_add_co_ci_u32_e64 v55, s0, 0, v35, s0
v_add_co_u32 v56, s0, s16, v32
v_add_co_ci_u32_e64 v57, s0, 0, v33, s0
v_add_co_u32 v58, s0, s16, v38
v_add_co_ci_u32_e64 v59, s0, 0, v39, s0
v_add_co_u32 v60, s0, s17, v36
s_clause 0x7
global_load_ushort v48, v[40:41], off
global_load_ushort v49, v[42:43], off
global_load_ushort v50, v[44:45], off
global_load_ushort v51, v[46:47], off
global_load_ushort v52, v[52:53], off
global_load_ushort v53, v[54:55], off
global_load_ushort v54, v[56:57], off
global_load_ushort v55, v[58:59], off
v_add_co_ci_u32_e64 v61, s0, 0, v37, s0
v_add_co_u32 v40, s0, s17, v34
s_clause 0x3
global_load_ushort v56, v[36:37], off
global_load_ushort v57, v[34:35], off
global_load_ushort v58, v[32:33], off
global_load_ushort v59, v[38:39], off
v_add_co_ci_u32_e64 v41, s0, 0, v35, s0
v_add_co_u32 v42, s0, s17, v32
v_add_co_ci_u32_e64 v43, s0, 0, v33, s0
v_add_co_u32 v44, s0, s17, v38
v_add_co_ci_u32_e64 v45, s0, 0, v39, s0
v_add_co_u32 v46, s0, s18, v36
v_add_co_ci_u32_e64 v47, s0, 0, v37, s0
v_add_co_u32 v65, s0, s18, v34
v_add_co_ci_u32_e64 v66, s0, 0, v35, s0
v_add_co_u32 v67, s0, s18, v32
v_add_co_ci_u32_e64 v68, s0, 0, v33, s0
v_add_co_u32 v69, s0, s18, v38
v_add_co_ci_u32_e64 v70, s0, 0, v39, s0
v_add_co_u32 v71, s0, s9, v36
v_add_co_ci_u32_e64 v72, s0, 0, v37, s0
v_add_co_u32 v73, s0, s9, v34
v_add_co_ci_u32_e64 v74, s0, 0, v35, s0
v_add_co_u32 v75, s0, s9, v32
v_add_co_ci_u32_e64 v76, s0, 0, v33, s0
v_add_co_u32 v77, s0, s9, v38
v_add_co_ci_u32_e64 v78, s0, 0, v39, s0
s_clause 0xb
global_load_ushort v60, v[60:61], off
global_load_ushort v61, v[40:41], off
global_load_ushort v62, v[42:43], off
global_load_ushort v63, v[44:45], off
global_load_ushort v64, v[46:47], off
global_load_ushort v65, v[65:66], off
global_load_ushort v66, v[67:68], off
global_load_ushort v67, v[69:70], off
global_load_ushort v68, v[71:72], off
global_load_ushort v69, v[73:74], off
global_load_ushort v70, v[75:76], off
global_load_ushort v71, v[77:78], off
v_lshl_add_u32 v40, s11, 6, v24
v_or_b32_e32 v42, v79, v23
v_or_b32_e32 v44, v79, v26
v_or_b32_e32 v46, v79, v28
v_or_b32_sdwa v72, v79, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
v_ashrrev_i32_e32 v41, 31, v40
v_ashrrev_i32_e32 v43, 31, v42
v_ashrrev_i32_e32 v45, 31, v44
v_ashrrev_i32_e32 v47, 31, v46
v_ashrrev_i32_e32 v73, 31, v72
v_lshlrev_b64 v[40:41], 1, v[40:41]
v_add_co_u32 v74, s0, s12, v40
v_add_co_ci_u32_e64 v75, s0, s13, v41, s0
v_lshlrev_b64 v[40:41], 1, v[42:43]
v_lshlrev_b64 v[42:43], 1, v[44:45]
v_lshlrev_b64 v[44:45], 1, v[46:47]
v_lshlrev_b64 v[46:47], 1, v[72:73]
v_add_co_u32 v72, s0, 0x32000, v74
v_add_co_ci_u32_e64 v73, s0, 0, v75, s0
v_add_co_u32 v76, s0, s10, v74
v_add_co_ci_u32_e64 v77, s0, 0, v75, s0
v_add_co_u32 v78, s0, 0x96000, v74
v_add_co_ci_u32_e64 v79, s0, 0, v75, s0
v_add_co_u32 v40, s0, s14, v40
s_clause 0x3
global_load_dword v108, v[74:75], off
global_load_dword v109, v[72:73], off
global_load_dword v110, v[76:77], off
global_load_dword v111, v[78:79], off
v_add_co_ci_u32_e64 v41, s0, s15, v41, s0
v_add_co_u32 v42, s0, s14, v42
v_add_co_ci_u32_e64 v43, s0, s15, v43, s0
v_add_co_u32 v44, s0, s14, v44
v_add_co_ci_u32_e64 v45, s0, s15, v45, s0
v_add_co_u32 v46, s0, s14, v46
v_add_co_ci_u32_e64 v47, s0, s15, v47, s0
v_add_co_u32 v72, s0, s8, v40
v_add_co_ci_u32_e64 v73, s0, 0, v41, s0
v_add_co_u32 v74, s0, s8, v42
v_add_co_ci_u32_e64 v75, s0, 0, v43, s0
v_add_co_u32 v76, s0, s8, v44
v_add_co_ci_u32_e64 v77, s0, 0, v45, s0
v_add_co_u32 v78, s0, s8, v46
v_add_co_ci_u32_e64 v79, s0, 0, v47, s0
v_add_co_u32 v80, s0, s16, v40
v_add_co_ci_u32_e64 v81, s0, 0, v41, s0
v_add_co_u32 v82, s0, s16, v42
v_add_co_ci_u32_e64 v83, s0, 0, v43, s0
v_add_co_u32 v84, s0, s16, v44
v_add_co_ci_u32_e64 v85, s0, 0, v45, s0
v_add_co_u32 v86, s0, s16, v46
v_add_co_ci_u32_e64 v87, s0, 0, v47, s0
v_add_co_u32 v88, s0, s17, v40
v_add_co_ci_u32_e64 v89, s0, 0, v41, s0
v_add_co_u32 v90, s0, s17, v42
v_add_co_ci_u32_e64 v91, s0, 0, v43, s0
v_add_co_u32 v92, s0, s17, v44
v_add_co_ci_u32_e64 v93, s0, 0, v45, s0
v_add_co_u32 v94, s0, s17, v46
v_add_co_ci_u32_e64 v95, s0, 0, v47, s0
v_add_co_u32 v96, s0, s18, v40
v_add_co_ci_u32_e64 v97, s0, 0, v41, s0
v_add_co_u32 v98, s0, s18, v42
v_add_co_ci_u32_e64 v99, s0, 0, v43, s0
v_add_co_u32 v100, s0, s18, v44
v_add_co_ci_u32_e64 v101, s0, 0, v45, s0
v_add_co_u32 v102, s0, s18, v46
v_add_co_ci_u32_e64 v103, s0, 0, v47, s0
v_add_co_u32 v104, s0, s9, v40
v_add_co_ci_u32_e64 v105, s0, 0, v41, s0
v_add_co_u32 v106, s0, s9, v42
v_add_co_ci_u32_e64 v107, s0, 0, v43, s0
s_waitcnt vmcnt(27)
global_load_short_d16_hi v48, v[72:73], off
v_add_co_u32 v72, s0, s9, v44
s_waitcnt vmcnt(27)
global_load_short_d16_hi v49, v[74:75], off
v_add_co_ci_u32_e64 v73, s0, 0, v45, s0
v_add_co_u32 v74, s0, s9, v46
v_add_co_ci_u32_e64 v75, s0, 0, v47, s0
s_waitcnt vmcnt(21)
global_load_short_d16_hi v56, v[40:41], off
s_waitcnt vmcnt(21)
global_load_short_d16_hi v57, v[42:43], off
s_waitcnt vmcnt(21)
global_load_short_d16_hi v58, v[44:45], off
s_waitcnt vmcnt(21)
s_clause 0x6
global_load_short_d16_hi v59, v[46:47], off
global_load_short_d16_hi v50, v[76:77], off
global_load_short_d16_hi v51, v[78:79], off
global_load_short_d16_hi v52, v[80:81], off
global_load_short_d16_hi v53, v[82:83], off
global_load_short_d16_hi v54, v[84:85], off
global_load_short_d16_hi v55, v[86:87], off
s_waitcnt vmcnt(27)
global_load_short_d16_hi v60, v[88:89], off
s_waitcnt vmcnt(27)
global_load_short_d16_hi v61, v[90:91], off
s_waitcnt vmcnt(27)
global_load_short_d16_hi v62, v[92:93], off
s_waitcnt vmcnt(27)
global_load_short_d16_hi v63, v[94:95], off
s_waitcnt vmcnt(27)
global_load_short_d16_hi v64, v[96:97], off
s_waitcnt vmcnt(27)
global_load_short_d16_hi v65, v[98:99], off
s_waitcnt vmcnt(27)
global_load_short_d16_hi v66, v[100:101], off
s_waitcnt vmcnt(27)
global_load_short_d16_hi v67, v[102:103], off
s_waitcnt vmcnt(27)
global_load_short_d16_hi v68, v[104:105], off
s_waitcnt vmcnt(27)
global_load_short_d16_hi v69, v[106:107], off
s_waitcnt vmcnt(27)
global_load_short_d16_hi v70, v[72:73], off
s_waitcnt vmcnt(27)
global_load_short_d16_hi v71, v[74:75], off
s_waitcnt vmcnt(0)
s_barrier
ds_write2st64_b32 v18, v108, v109 offset1:5
ds_write2st64_b32 v18, v110, v111 offset0:10 offset1:15
ds_write_b128 v20, v[56:59]
ds_write_b128 v20, v[48:51] offset:5120
ds_write_b128 v20, v[52:55] offset:10240
ds_write_b128 v20, v[60:63] offset:15360
ds_write_b128 v20, v[64:67] offset:20480
ds_write_b128 v20, v[68:71] offset:25600
s_and_saveexec_b32 s20, vcc_lo
s_cbranch_execz BB54_3
v_add_co_u32 v36, s0, s19, v36
v_add_co_ci_u32_e64 v37, s0, 0, v37, s0
v_add_co_u32 v34, s0, s19, v34
v_add_co_ci_u32_e64 v35, s0, 0, v35, s0
v_add_co_u32 v48, s0, s19, v32
v_add_co_ci_u32_e64 v49, s0, 0, v33, s0
v_add_co_u32 v38, s0, s19, v38
v_add_co_ci_u32_e64 v39, s0, 0, v39, s0
s_clause 0x3
global_load_ushort v32, v[36:37], off
global_load_ushort v33, v[34:35], off
global_load_ushort v34, v[48:49], off
global_load_ushort v35, v[38:39], off
v_add_co_u32 v36, s0, s19, v40
v_add_co_ci_u32_e64 v37, s0, 0, v41, s0
v_add_co_u32 v38, s0, s19, v42
v_add_co_ci_u32_e64 v39, s0, 0, v43, s0
v_add_co_u32 v40, s0, s19, v44
v_add_co_ci_u32_e64 v41, s0, 0, v45, s0
v_add_co_u32 v42, s0, s19, v46
v_add_co_ci_u32_e64 v43, s0, 0, v47, s0
s_waitcnt vmcnt(3)
global_load_short_d16_hi v32, v[36:37], off
s_waitcnt vmcnt(3)
global_load_short_d16_hi v33, v[38:39], off
s_waitcnt vmcnt(3)
global_load_short_d16_hi v34, v[40:41], off
s_waitcnt vmcnt(3)
global_load_short_d16_hi v35, v[42:43], off
s_waitcnt vmcnt(0)
ds_write_b128 v20, v[32:35] offset:30720
BB54_3:
s_or_b32 exec_lo, exec_lo, s20
v_mov_b32_e32 v32, v31
s_mov_b32 s0, 0
s_waitcnt lgkmcnt(0)
s_barrier
BB54_4:
v_or_b32_e32 v49, s0, v21
ds_read_b128 v[33:36], v32
ds_read_b128 v[37:40], v32 offset:640
ds_read_b128 v[41:44], v32 offset:2560
ds_read_b128 v[45:48], v32 offset:3200
v_add_nc_u32_e32 v32, 16, v32
s_addk_i32 s0, 0x800
v_lshlrev_b32_e32 v77, 1, v49
s_cmpk_lg_i32 s0, 0x4000
ds_read_b128 v[49:52], v77
ds_read_b128 v[53:56], v77 offset:512
ds_read_b128 v[57:60], v77 offset:1024
ds_read_b128 v[61:64], v77 offset:1536
ds_read_b128 v[65:68], v77 offset:2048
ds_read_b128 v[69:72], v77 offset:2560
ds_read_b128 v[73:76], v77 offset:3072
ds_read_b128 v[77:80], v77 offset:3584
s_waitcnt lgkmcnt(7)
v_pk_fma_f16 v15, v33, v49, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v41, v49, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v33, v50, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v41, v50, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v33, v51, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v41, v51, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v33, v52, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v41, v52, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v37, v49, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v45, v49, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v37, v50, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v45, v50, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v37, v51, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v45, v51, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v37, v52, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v45, v52, v0 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(6)
v_pk_fma_f16 v15, v33, v53, v15 op_sel:[1,0,0]
v_pk_fma_f16 v14, v41, v53, v14 op_sel:[1,0,0]
v_pk_fma_f16 v13, v33, v54, v13 op_sel:[1,0,0]
v_pk_fma_f16 v12, v41, v54, v12 op_sel:[1,0,0]
v_pk_fma_f16 v11, v33, v55, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v41, v55, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v33, v56, v9 op_sel:[1,0,0]
v_pk_fma_f16 v8, v41, v56, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v37, v53, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v45, v53, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v37, v54, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v45, v54, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v37, v55, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v45, v55, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v37, v56, v1 op_sel:[1,0,0]
v_pk_fma_f16 v0, v45, v56, v0 op_sel:[1,0,0]
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v15, v34, v57, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v42, v57, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v34, v58, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v42, v58, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v34, v59, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v42, v59, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v34, v60, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v42, v60, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v38, v57, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v46, v57, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v38, v58, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v46, v58, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v38, v59, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v46, v59, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v38, v60, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v46, v60, v0 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v15, v34, v61, v15 op_sel:[1,0,0]
v_pk_fma_f16 v14, v42, v61, v14 op_sel:[1,0,0]
v_pk_fma_f16 v13, v34, v62, v13 op_sel:[1,0,0]
v_pk_fma_f16 v12, v42, v62, v12 op_sel:[1,0,0]
v_pk_fma_f16 v11, v34, v63, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v42, v63, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v34, v64, v9 op_sel:[1,0,0]
v_pk_fma_f16 v8, v42, v64, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v38, v61, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v46, v61, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v38, v62, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v46, v62, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v38, v63, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v46, v63, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v38, v64, v1 op_sel:[1,0,0]
v_pk_fma_f16 v0, v46, v64, v0 op_sel:[1,0,0]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v15, v35, v65, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v43, v65, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v35, v66, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v43, v66, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v35, v67, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v43, v67, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v35, v68, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v43, v68, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v39, v65, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v47, v65, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v39, v66, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v47, v66, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v39, v67, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v47, v67, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v39, v68, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v47, v68, v0 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v15, v35, v69, v15 op_sel:[1,0,0]
v_pk_fma_f16 v14, v43, v69, v14 op_sel:[1,0,0]
v_pk_fma_f16 v13, v35, v70, v13 op_sel:[1,0,0]
v_pk_fma_f16 v12, v43, v70, v12 op_sel:[1,0,0]
v_pk_fma_f16 v11, v35, v71, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v43, v71, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v35, v72, v9 op_sel:[1,0,0]
v_pk_fma_f16 v8, v43, v72, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v39, v69, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v47, v69, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v39, v70, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v47, v70, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v39, v71, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v47, v71, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v39, v72, v1 op_sel:[1,0,0]
v_pk_fma_f16 v0, v47, v72, v0 op_sel:[1,0,0]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v15, v36, v73, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v44, v73, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v36, v74, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v44, v74, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v36, v75, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v44, v75, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v36, v76, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v44, v76, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v40, v73, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v48, v73, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v40, v74, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v48, v74, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v40, v75, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v48, v75, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v40, v76, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v48, v76, v0 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v15, v36, v77, v15 op_sel:[1,0,0]
v_pk_fma_f16 v14, v44, v77, v14 op_sel:[1,0,0]
v_pk_fma_f16 v13, v36, v78, v13 op_sel:[1,0,0]
v_pk_fma_f16 v12, v44, v78, v12 op_sel:[1,0,0]
v_pk_fma_f16 v11, v36, v79, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v44, v79, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v36, v80, v9 op_sel:[1,0,0]
v_pk_fma_f16 v8, v44, v80, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v40, v77, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v48, v77, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v40, v78, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v48, v78, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v40, v79, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v48, v79, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v40, v80, v1 op_sel:[1,0,0]
v_pk_fma_f16 v0, v48, v80, v0 op_sel:[1,0,0]
s_cbranch_scc1 BB54_4
s_add_i32 s11, s11, 1
s_cmp_eq_u32 s11, 32
s_cbranch_scc0 BB54_1
v_and_b32_e32 v18, 0xf8, v19
v_mul_lo_u32 v16, 0x6400, v16
s_mov_b32 s0, 0x19000
v_lshlrev_b32_e32 v17, 4, v17
s_mul_i32 s7, s7, s0
v_or_b32_e32 v19, s1, v18
s_mulk_i32 s6, 0xa00
v_and_b32_e32 v17, 0xfffffe00, v17
v_add_nc_u32_e32 v16, s7, v16
v_lshlrev_b32_e32 v19, 1, v19
v_or3_b32 v16, v16, s1, v18
s_clause 0x3
global_load_dword v42, v19, s[4:5]
global_load_dword v43, v19, s[4:5] offset:4
global_load_dword v44, v19, s[4:5] offset:8
global_load_dword v45, v19, s[4:5] offset:12
v_add3_u32 v16, v16, s6, v17
v_ashrrev_i32_e32 v17, 31, v16
v_add_nc_u32_e32 v18, 0xc802, v16
v_add_nc_u32_e32 v20, 0xc804, v16
v_add_nc_u32_e32 v22, 0xc806, v16
v_add_nc_u32_e32 v24, 0x3200, v16
v_add_nc_u32_e32 v26, 0xfa00, v16
v_add_nc_u32_e32 v28, 0x3202, v16
v_add_nc_u32_e32 v30, 0xfa02, v16
v_add_nc_u32_e32 v32, 0x3204, v16
v_add_nc_u32_e32 v34, 0xfa04, v16
v_add_nc_u32_e32 v36, 0x3206, v16
v_add_nc_u32_e32 v38, 0xfa06, v16
v_lshlrev_b64 v[16:17], 1, v[16:17]
v_ashrrev_i32_e32 v19, 31, v18
v_ashrrev_i32_e32 v21, 31, v20
v_ashrrev_i32_e32 v23, 31, v22
v_ashrrev_i32_e32 v25, 31, v24
v_ashrrev_i32_e32 v27, 31, v26
v_add_co_u32 v16, vcc_lo, s2, v16
v_lshlrev_b64 v[18:19], 1, v[18:19]
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
v_lshlrev_b64 v[20:21], 1, v[20:21]
v_lshlrev_b64 v[22:23], 1, v[22:23]
v_add_co_u32 v40, vcc_lo, s0, v16
v_lshlrev_b64 v[24:25], 1, v[24:25]
v_add_co_ci_u32_e32 v41, vcc_lo, 0, v17, vcc_lo
v_add_co_u32 v18, vcc_lo, s2, v18
v_ashrrev_i32_e32 v29, 31, v28
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
v_add_co_u32 v20, vcc_lo, s2, v20
v_lshlrev_b64 v[26:27], 1, v[26:27]
v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo
v_add_co_u32 v22, vcc_lo, s2, v22
v_ashrrev_i32_e32 v31, 31, v30
v_add_co_ci_u32_e32 v23, vcc_lo, s3, v23, vcc_lo
v_add_co_u32 v24, vcc_lo, s2, v24
v_lshlrev_b64 v[28:29], 1, v[28:29]
v_ashrrev_i32_e32 v33, 31, v32
v_add_co_ci_u32_e32 v25, vcc_lo, s3, v25, vcc_lo
v_add_co_u32 v26, vcc_lo, s2, v26
v_lshlrev_b64 v[30:31], 1, v[30:31]
v_ashrrev_i32_e32 v35, 31, v34
v_add_co_ci_u32_e32 v27, vcc_lo, s3, v27, vcc_lo
v_add_co_u32 v28, vcc_lo, s2, v28
v_lshlrev_b64 v[32:33], 1, v[32:33]
v_ashrrev_i32_e32 v37, 31, v36
v_add_co_ci_u32_e32 v29, vcc_lo, s3, v29, vcc_lo
v_add_co_u32 v30, vcc_lo, s2, v30
v_lshlrev_b64 v[34:35], 1, v[34:35]
v_ashrrev_i32_e32 v39, 31, v38
v_add_co_ci_u32_e32 v31, vcc_lo, s3, v31, vcc_lo
v_add_co_u32 v32, vcc_lo, s2, v32
v_lshlrev_b64 v[36:37], 1, v[36:37]
v_add_co_ci_u32_e32 v33, vcc_lo, s3, v33, vcc_lo
v_add_co_u32 v34, vcc_lo, s2, v34
v_lshlrev_b64 v[38:39], 1, v[38:39]
v_add_co_ci_u32_e32 v35, vcc_lo, s3, v35, vcc_lo
v_add_co_u32 v36, vcc_lo, s2, v36
v_add_co_ci_u32_e32 v37, vcc_lo, s3, v37, vcc_lo
v_add_co_u32 v38, vcc_lo, s2, v38
v_add_co_ci_u32_e32 v39, vcc_lo, s3, v39, vcc_lo
s_waitcnt vmcnt(3)
v_pk_add_f16 v15, v42, v15
v_pk_add_f16 v14, v42, v14
s_waitcnt vmcnt(2)
v_pk_add_f16 v13, v43, v13
v_pk_add_f16 v12, v43, v12
s_waitcnt vmcnt(1)
v_pk_add_f16 v11, v44, v11
v_pk_add_f16 v10, v44, v10
s_waitcnt vmcnt(0)
v_pk_add_f16 v9, v45, v9
v_pk_add_f16 v8, v45, v8
v_pk_add_f16 v7, v42, v7
v_pk_add_f16 v6, v42, v6
v_pk_add_f16 v5, v43, v5
v_pk_add_f16 v4, v43, v4
v_pk_add_f16 v3, v44, v3
v_pk_add_f16 v2, v44, v2
v_pk_add_f16 v1, v45, v1
v_pk_add_f16 v0, v45, v0
v_pk_max_f16 v15, v15, 0
v_pk_max_f16 v14, v14, 0
v_pk_max_f16 v13, v13, 0
v_pk_max_f16 v12, v12, 0
v_pk_max_f16 v11, v11, 0
v_pk_max_f16 v10, v10, 0
v_pk_max_f16 v9, v9, 0
v_pk_max_f16 v8, v8, 0
v_pk_max_f16 v7, v7, 0
v_pk_max_f16 v6, v6, 0
v_pk_max_f16 v5, v5, 0
v_pk_max_f16 v4, v4, 0
v_pk_max_f16 v3, v3, 0
v_pk_max_f16 v2, v2, 0
v_pk_max_f16 v1, v1, 0
v_pk_max_f16 v0, v0, 0
global_store_dword v[16:17], v15, off
global_store_dword v[40:41], v14, off
global_store_dword v[16:17], v13, off offset:4
global_store_dword v[18:19], v12, off
global_store_dword v[16:17], v11, off offset:8
global_store_dword v[20:21], v10, off
global_store_dword v[16:17], v9, off offset:12
global_store_dword v[22:23], v8, off
global_store_dword v[24:25], v7, off
global_store_dword v[26:27], v6, off
global_store_dword v[28:29], v5, off
global_store_dword v[30:31], v4, off
global_store_dword v[32:33], v3, off
global_store_dword v[34:35], v2, off
global_store_dword v[36:37], v1, off
global_store_dword v[38:39], v0, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_nn_relu_11_kernel0
.amdhsa_group_segment_fixed_size 37888
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 112
.amdhsa_next_free_sgpr 21
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end54:
.size tvmgen_default_fused_nn_conv2d_add_nn_relu_11_kernel0, .Lfunc_end54-tvmgen_default_fused_nn_conv2d_add_nn_relu_11_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_nn_relu_1_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_nn_relu_1_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_nn_relu_1_kernel0:
s_clause 0x3
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[4:5], s[4:5], 0x18
v_and_b32_e32 v1, 7, v0
v_lshrrev_b32_e32 v2, 3, v0
v_lshlrev_b32_e32 v17, 1, v0
s_ashr_i32 s1, s6, 1
s_movk_i32 s7, 0x200
s_mulk_i32 s1, 0x6400
v_lshl_or_b32 v3, v2, 6, v1
v_lshl_add_u32 v21, v2, 5, s7
v_lshlrev_b32_e32 v22, 3, v1
v_add_nc_u32_e32 v18, s7, v17
v_cmp_gt_i32_e32 vcc_lo, 0x100, v0
v_add_nc_u32_e32 v23, s1, v3
v_and_b32_e32 v19, 31, v0
v_and_b32_e32 v20, 0x7c0, v17
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v15, 0
s_lshl_b32 s0, s6, 5
s_mov_b32 s12, 0
s_and_b32 s6, s0, 32
s_branch BB55_2
BB55_1:
s_or_b32 exec_lo, exec_lo, s13
s_waitcnt lgkmcnt(0)
s_barrier
ds_read2_b32 v[60:61], v22 offset1:1
ds_read_b128 v[24:27], v21
ds_read_b128 v[28:31], v21 offset:1600
ds_read_b128 v[32:35], v21 offset:3200
ds_read_b128 v[36:39], v21 offset:4800
ds_read_b128 v[40:43], v21 offset:16
ds_read_b128 v[44:47], v21 offset:1616
ds_read_b128 v[48:51], v21 offset:3216
ds_read_b128 v[52:55], v21 offset:4816
ds_read2_b64 v[56:59], v22 offset0:8 offset1:16
ds_read_b64 v[62:63], v22 offset:448
v_add_nc_u32_e32 v20, s7, v20
s_add_i32 s12, s12, 8
s_cmp_eq_u32 s12, 64
s_waitcnt lgkmcnt(9)
v_pk_fma_f16 v14, v24, v60, v14 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(8)
v_pk_fma_f16 v13, v28, v60, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v24, v61, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v28, v61, v11 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(7)
v_pk_fma_f16 v8, v32, v60, v8 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(6)
v_pk_fma_f16 v10, v36, v60, v10 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v3, v48, v60, v3 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v4, v52, v60, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v32, v61, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v36, v61, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v40, v60, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v44, v60, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v40, v61, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v44, v61, v7 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v14, v24, v56, v14 op_sel:[1,0,0]
v_pk_fma_f16 v12, v24, v57, v12 op_sel:[1,0,0]
v_pk_fma_f16 v13, v28, v56, v13 op_sel:[1,0,0]
v_pk_fma_f16 v11, v28, v57, v11 op_sel:[1,0,0]
v_pk_fma_f16 v24, v48, v56, v3 op_sel:[1,0,0]
v_pk_fma_f16 v28, v52, v56, v4 op_sel:[1,0,0]
v_pk_fma_f16 v60, v48, v61, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v61, v52, v61, v1 op_sel_hi:[0,1,1]
ds_read2_b64 v[1:4], v22 offset0:24 offset1:32
v_pk_fma_f16 v8, v32, v56, v8 op_sel:[1,0,0]
v_pk_fma_f16 v10, v36, v56, v10 op_sel:[1,0,0]
v_pk_fma_f16 v15, v40, v56, v15 op_sel:[1,0,0]
v_pk_fma_f16 v9, v44, v56, v9 op_sel:[1,0,0]
v_pk_fma_f16 v16, v40, v57, v16 op_sel:[1,0,0]
v_pk_fma_f16 v8, v33, v58, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v37, v58, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v25, v59, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v45, v58, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v49, v58, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v25, v58, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v29, v58, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v41, v58, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v53, v58, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v41, v59, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v44, v57, v7 op_sel:[1,0,0]
v_pk_fma_f16 v5, v32, v57, v5 op_sel:[1,0,0]
v_pk_fma_f16 v6, v36, v57, v6 op_sel:[1,0,0]
v_pk_fma_f16 v32, v48, v57, v60 op_sel:[1,0,0]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v8, v33, v1, v8 op_sel:[1,0,0]
v_pk_fma_f16 v10, v37, v1, v10 op_sel:[1,0,0]
v_pk_fma_f16 v12, v25, v2, v12 op_sel:[1,0,0]
v_pk_fma_f16 v9, v45, v1, v9 op_sel:[1,0,0]
v_pk_fma_f16 v24, v49, v1, v24 op_sel:[1,0,0]
v_pk_fma_f16 v40, v25, v1, v14 op_sel:[1,0,0]
v_pk_fma_f16 v25, v41, v1, v15 op_sel:[1,0,0]
v_pk_fma_f16 v44, v29, v1, v13 op_sel:[1,0,0]
v_pk_fma_f16 v1, v53, v1, v28 op_sel:[1,0,0]
v_pk_fma_f16 v28, v41, v2, v16 op_sel:[1,0,0]
ds_read2_b64 v[13:16], v22 offset0:40 offset1:48
v_pk_fma_f16 v36, v52, v57, v61 op_sel:[1,0,0]
v_pk_fma_f16 v11, v29, v59, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v33, v59, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v37, v59, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v45, v59, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v49, v59, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v53, v59, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v29, v2, v11 op_sel:[1,0,0]
v_pk_fma_f16 v5, v33, v2, v5 op_sel:[1,0,0]
v_pk_fma_f16 v6, v37, v2, v6 op_sel:[1,0,0]
v_pk_fma_f16 v7, v45, v2, v7 op_sel:[1,0,0]
v_pk_fma_f16 v29, v49, v2, v32 op_sel:[1,0,0]
v_pk_fma_f16 v2, v53, v2, v36 op_sel:[1,0,0]
v_pk_fma_f16 v32, v26, v3, v40 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v34, v3, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v38, v3, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v26, v4, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v30, v4, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v34, v4, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v38, v4, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v42, v3, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v46, v3, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v50, v3, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v54, v3, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v46, v4, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v54, v4, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v30, v3, v44 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v42, v4, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v50, v4, v29 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v4, v26, v13, v32 op_sel:[1,0,0]
v_pk_fma_f16 v12, v26, v14, v12 op_sel:[1,0,0]
v_pk_fma_f16 v29, v30, v13, v33 op_sel:[1,0,0]
v_pk_fma_f16 v26, v42, v14, v3 op_sel:[1,0,0]
v_pk_fma_f16 v5, v34, v14, v5 op_sel:[1,0,0]
v_pk_fma_f16 v3, v27, v15, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v38, v14, v6 op_sel:[1,0,0]
v_pk_fma_f16 v24, v50, v13, v24 op_sel:[1,0,0]
v_pk_fma_f16 v7, v46, v14, v7 op_sel:[1,0,0]
v_pk_fma_f16 v11, v30, v14, v11 op_sel:[1,0,0]
v_pk_fma_f16 v25, v42, v13, v25 op_sel:[1,0,0]
v_pk_fma_f16 v28, v50, v14, v28 op_sel:[1,0,0]
v_pk_fma_f16 v2, v54, v14, v2 op_sel:[1,0,0]
v_pk_fma_f16 v14, v27, v62, v3 op_sel:[1,0,0]
v_pk_fma_f16 v3, v27, v16, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v31, v15, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v34, v13, v8 op_sel:[1,0,0]
v_pk_fma_f16 v10, v38, v13, v10 op_sel:[1,0,0]
v_pk_fma_f16 v1, v54, v13, v1 op_sel:[1,0,0]
v_pk_fma_f16 v9, v46, v13, v9 op_sel:[1,0,0]
v_pk_fma_f16 v13, v31, v62, v4 op_sel:[1,0,0]
v_pk_fma_f16 v4, v31, v16, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v27, v63, v3 op_sel:[1,0,0]
v_pk_fma_f16 v3, v43, v15, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v51, v15, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v35, v15, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v39, v15, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v35, v16, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v39, v16, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v47, v16, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v31, v63, v4 op_sel:[1,0,0]
v_pk_fma_f16 v4, v47, v15, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v55, v15, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v43, v62, v3 op_sel:[1,0,0]
v_pk_fma_f16 v3, v51, v62, v24 op_sel:[1,0,0]
v_pk_fma_f16 v24, v43, v16, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v51, v16, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v55, v16, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v47, v62, v4 op_sel:[1,0,0]
v_pk_fma_f16 v4, v55, v62, v1 op_sel:[1,0,0]
v_pk_fma_f16 v8, v35, v62, v8 op_sel:[1,0,0]
v_pk_fma_f16 v10, v39, v62, v10 op_sel:[1,0,0]
v_pk_fma_f16 v5, v35, v63, v5 op_sel:[1,0,0]
v_pk_fma_f16 v6, v39, v63, v6 op_sel:[1,0,0]
v_pk_fma_f16 v16, v43, v63, v24 op_sel:[1,0,0]
v_pk_fma_f16 v7, v47, v63, v7 op_sel:[1,0,0]
v_pk_fma_f16 v2, v51, v63, v25 op_sel:[1,0,0]
v_pk_fma_f16 v1, v55, v63, v26 op_sel:[1,0,0]
s_cbranch_scc1 BB55_4
BB55_2:
v_add_nc_u32_e32 v24, s12, v23
v_ashrrev_i32_e32 v25, 31, v24
v_lshlrev_b64 v[24:25], 1, v[24:25]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v24, s0, s8, v24
v_add_co_ci_u32_e64 v25, s0, s9, v25, s0
v_add_co_u32 v26, s0, 0x1800, v24
v_add_co_ci_u32_e64 v27, s0, 0, v25, s0
v_add_co_u32 v28, s0, 0x3000, v24
v_add_co_ci_u32_e64 v29, s0, 0, v25, s0
v_add_co_u32 v30, s0, 0x4800, v24
v_add_co_ci_u32_e64 v31, s0, 0, v25, s0
v_add_co_u32 v32, s0, 0x6000, v24
v_add_co_ci_u32_e64 v33, s0, 0, v25, s0
v_add_co_u32 v34, s0, 0x7800, v24
v_add_co_ci_u32_e64 v35, s0, 0, v25, s0
v_add_co_u32 v36, s0, 0x9000, v24
v_add_co_ci_u32_e64 v37, s0, 0, v25, s0
v_add_co_u32 v38, s0, 0xa800, v24
v_add_co_ci_u32_e64 v39, s0, 0, v25, s0
s_clause 0x7
global_load_ushort v24, v[24:25], off
global_load_ushort v25, v[26:27], off offset:256
global_load_ushort v26, v[28:29], off offset:512
global_load_ushort v27, v[30:31], off offset:768
global_load_ushort v28, v[32:33], off offset:1024
global_load_ushort v29, v[34:35], off offset:1280
global_load_ushort v30, v[36:37], off offset:1536
global_load_ushort v31, v[38:39], off offset:1792
s_waitcnt vmcnt(0)
s_barrier
ds_write_b16 v18, v24
ds_write_b16 v18, v25 offset:800
ds_write_b16 v18, v26 offset:1600
ds_write_b16 v18, v27 offset:2400
ds_write_b16 v18, v28 offset:3200
ds_write_b16 v18, v29 offset:4000
ds_write_b16 v18, v30 offset:4800
ds_write_b16 v18, v31 offset:5600
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz BB55_1
v_or3_b32 v24, v20, s6, v19
v_ashrrev_i32_e32 v25, 31, v24
v_lshlrev_b64 v[24:25], 1, v[24:25]
v_add_co_u32 v24, s0, s10, v24
v_add_co_ci_u32_e64 v25, s0, s11, v25, s0
global_load_ushort v24, v[24:25], off
s_waitcnt vmcnt(0)
ds_write_b16 v17, v24
s_branch BB55_1
BB55_4:
v_lshlrev_b32_e32 v17, 2, v0
v_lshlrev_b32_e32 v0, 4, v0
v_and_b32_e32 v17, 28, v17
v_and_b32_e32 v0, 0x3f80, v0
v_or_b32_e32 v18, s6, v17
v_add_nc_u32_e32 v0, s1, v0
v_lshlrev_b32_e32 v18, 1, v18
v_or3_b32 v17, v0, s6, v17
v_mov_b32_e32 v0, 0
s_clause 0x1
global_load_dword v43, v18, s[4:5]
global_load_dword v44, v18, s[4:5] offset:4
v_ashrrev_i32_e32 v18, 31, v17
v_add_nc_u32_e32 v19, 0x1902, v17
v_add_nc_u32_e32 v21, 0x1940, v17
v_add_nc_u32_e32 v23, 0x1942, v17
v_add_nc_u32_e32 v25, 0x3200, v17
v_add_nc_u32_e32 v27, 0x4b00, v17
v_add_nc_u32_e32 v29, 0x3202, v17
v_add_nc_u32_e32 v31, 0x4b02, v17
v_add_nc_u32_e32 v33, 0x3240, v17
v_add_nc_u32_e32 v35, 0x4b40, v17
v_add_nc_u32_e32 v37, 0x3242, v17
v_add_nc_u32_e32 v39, 0x4b42, v17
v_lshlrev_b64 v[17:18], 1, v[17:18]
v_ashrrev_i32_e32 v20, 31, v19
v_ashrrev_i32_e32 v22, 31, v21
v_ashrrev_i32_e32 v24, 31, v23
v_ashrrev_i32_e32 v26, 31, v25
v_ashrrev_i32_e32 v28, 31, v27
v_add_co_u32 v17, vcc_lo, s2, v17
v_lshlrev_b64 v[19:20], 1, v[19:20]
v_add_co_ci_u32_e32 v18, vcc_lo, s3, v18, vcc_lo
v_lshlrev_b64 v[21:22], 1, v[21:22]
v_lshlrev_b64 v[23:24], 1, v[23:24]
v_add_co_u32 v41, vcc_lo, 0x3000, v17
v_lshlrev_b64 v[25:26], 1, v[25:26]
v_add_co_ci_u32_e32 v42, vcc_lo, 0, v18, vcc_lo
v_add_co_u32 v19, vcc_lo, s2, v19
v_ashrrev_i32_e32 v30, 31, v29
v_add_co_ci_u32_e32 v20, vcc_lo, s3, v20, vcc_lo
v_add_co_u32 v21, vcc_lo, s2, v21
v_lshlrev_b64 v[27:28], 1, v[27:28]
v_add_co_ci_u32_e32 v22, vcc_lo, s3, v22, vcc_lo
v_add_co_u32 v23, vcc_lo, s2, v23
v_ashrrev_i32_e32 v32, 31, v31
v_add_co_ci_u32_e32 v24, vcc_lo, s3, v24, vcc_lo
v_add_co_u32 v25, vcc_lo, s2, v25
v_lshlrev_b64 v[29:30], 1, v[29:30]
v_ashrrev_i32_e32 v34, 31, v33
v_add_co_ci_u32_e32 v26, vcc_lo, s3, v26, vcc_lo
v_add_co_u32 v27, vcc_lo, s2, v27
v_lshlrev_b64 v[31:32], 1, v[31:32]
v_ashrrev_i32_e32 v36, 31, v35
v_add_co_ci_u32_e32 v28, vcc_lo, s3, v28, vcc_lo
v_add_co_u32 v29, vcc_lo, s2, v29
v_lshlrev_b64 v[33:34], 1, v[33:34]
v_ashrrev_i32_e32 v38, 31, v37
v_add_co_ci_u32_e32 v30, vcc_lo, s3, v30, vcc_lo
v_add_co_u32 v31, vcc_lo, s2, v31
v_lshlrev_b64 v[35:36], 1, v[35:36]
v_ashrrev_i32_e32 v40, 31, v39
v_add_co_ci_u32_e32 v32, vcc_lo, s3, v32, vcc_lo
v_add_co_u32 v33, vcc_lo, s2, v33
v_lshlrev_b64 v[37:38], 1, v[37:38]
v_add_co_ci_u32_e32 v34, vcc_lo, s3, v34, vcc_lo
v_add_co_u32 v35, vcc_lo, s2, v35
v_lshlrev_b64 v[39:40], 1, v[39:40]
v_add_co_ci_u32_e32 v36, vcc_lo, s3, v36, vcc_lo
v_add_co_u32 v37, vcc_lo, s2, v37
v_add_co_ci_u32_e32 v38, vcc_lo, s3, v38, vcc_lo
v_add_co_u32 v39, vcc_lo, s2, v39
v_add_co_ci_u32_e32 v40, vcc_lo, s3, v40, vcc_lo
s_waitcnt vmcnt(1)
v_pk_add_f16 v14, v43, v14
v_pk_add_f16 v13, v43, v13
s_waitcnt vmcnt(0)
v_pk_add_f16 v12, v44, v12
v_pk_add_f16 v11, v44, v11
v_pk_add_f16 v15, v43, v15
v_pk_add_f16 v9, v43, v9
v_pk_add_f16 v7, v44, v7
v_pk_add_f16 v8, v43, v8
v_pk_add_f16 v10, v43, v10
v_pk_add_f16 v5, v44, v5
v_pk_add_f16 v6, v44, v6
v_pk_add_f16 v3, v43, v3
v_pk_add_f16 v4, v43, v4
v_pk_add_f16 v2, v44, v2
v_pk_add_f16 v1, v44, v1
v_pk_add_f16 v16, v44, v16
v_pk_max_f16 v14, v14, 0
v_pk_max_f16 v13, v13, 0
v_pk_max_f16 v12, v12, 0
v_pk_max_f16 v11, v11, 0
v_max_f16_e32 v43, 0, v15
v_max_f16_sdwa v15, v15, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
v_pk_max_f16 v9, v9, 0
v_max_f16_e32 v44, 0, v16
v_max_f16_sdwa v0, v16, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
v_pk_max_f16 v7, v7, 0
v_pk_max_f16 v8, v8, 0
v_pk_max_f16 v10, v10, 0
v_pk_max_f16 v5, v5, 0
v_pk_max_f16 v6, v6, 0
v_pk_max_f16 v3, v3, 0
v_pk_max_f16 v4, v4, 0
v_pk_max_f16 v2, v2, 0
v_pk_max_f16 v1, v1, 0
global_store_dword v[17:18], v14, off
global_store_dword v[41:42], v13, off offset:512
global_store_dword v[17:18], v12, off offset:4
global_store_dword v[19:20], v11, off
global_store_short v[17:18], v43, off offset:128
global_store_short v[17:18], v15, off offset:130
global_store_dword v[21:22], v9, off
global_store_short v[17:18], v44, off offset:132
global_store_short v[17:18], v0, off offset:134
global_store_dword v[23:24], v7, off
global_store_dword v[25:26], v8, off
global_store_dword v[27:28], v10, off
global_store_dword v[29:30], v5, off
global_store_dword v[31:32], v6, off
global_store_dword v[33:34], v3, off
global_store_dword v[35:36], v4, off
global_store_dword v[37:38], v2, off
global_store_dword v[39:40], v1, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_nn_relu_1_kernel0
.amdhsa_group_segment_fixed_size 6912
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 64
.amdhsa_next_free_sgpr 14
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end55:
.size tvmgen_default_fused_nn_conv2d_add_nn_relu_1_kernel0, .Lfunc_end55-tvmgen_default_fused_nn_conv2d_add_nn_relu_1_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_nn_relu_2_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_nn_relu_2_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_nn_relu_2_kernel0:
v_lshrrev_b32_e32 v2, 3, v0
s_mov_b32 s14, 0xcccccccd
v_lshlrev_b32_e32 v11, 3, v0
s_mul_hi_i32 s7, s6, 0x66666667
s_movk_i32 s15, 0xa00
v_add_nc_u32_e32 v3, 32, v2
s_lshr_b32 s9, s7, 31
v_add_nc_u32_e32 v5, 0x800, v11
s_ashr_i32 s7, s7, 1
v_add_nc_u32_e32 v6, 0xc00, v11
v_mul_hi_u32 v1, v3, s14
s_add_i32 s7, s7, s9
v_mul_hi_u32 v5, v5, s14
s_mul_i32 s9, s7, 5
s_mov_b32 s16, 0xc800
s_sub_i32 s6, s6, s9
s_mov_b32 s0, 0x32000
v_mul_hi_u32 v6, v6, s14
v_lshrrev_b32_e32 v4, 5, v1
v_and_b32_e32 v1, 56, v11
v_lshrrev_b32_e32 v5, 11, v5
s_mul_i32 s17, s7, s0
s_mul_i32 s9, s6, 0x2800
v_mul_u32_u24_e32 v4, 40, v4
s_add_i32 s17, s17, s9
v_mul_i32_i24_e32 v12, s16, v5
s_movk_i32 s8, 0x1000
v_or_b32_e32 v10, s17, v1
v_sub_nc_u32_e32 v3, v3, v4
v_add_nc_u32_e32 v4, 8, v2
v_add_nc_u32_e32 v15, s8, v11
s_movk_i32 s1, 0x2000
v_lshl_add_u32 v9, v2, 8, s17
v_lshlrev_b32_e32 v7, 6, v3
v_lshlrev_b32_e32 v3, 8, v3
v_lshlrev_b32_e32 v8, 6, v4
v_lshrrev_b32_e32 v6, 11, v6
s_movk_i32 s9, 0x1800
v_mad_i32_i24 v5, v5, s15, v7
v_add3_u32 v20, v10, v12, v3
v_mul_hi_u32 v12, v15, s14
v_or_b32_e32 v19, v9, v1
v_mad_i32_i24 v9, v6, s15, v8
v_or_b32_e32 v5, v5, v1
v_add_nc_u32_e32 v15, 24, v2
v_lshl_add_u32 v4, v4, 8, v10
v_add_nc_u32_e32 v17, 0x1c00, v11
v_or_b32_e32 v9, v9, v1
v_lshl_add_u32 v21, v5, 1, s1
v_add_nc_u32_e32 v5, s9, v11
v_lshlrev_b32_e32 v16, 6, v15
v_mad_i32_i24 v24, v6, s16, v4
v_add_nc_u32_e32 v6, 16, v2
v_lshrrev_b32_e32 v12, 11, v12
v_mul_hi_u32 v5, v5, s14
v_lshl_add_u32 v15, v15, 8, v10
v_or_b32_e32 v22, s1, v11
v_add_nc_u32_e32 v23, 0x2400, v11
v_lshl_add_u32 v26, v9, 1, s1
v_mad_i32_i24 v9, v12, s15, v16
v_lshlrev_b32_e32 v18, 6, v6
v_mad_i32_i24 v32, v12, s16, v15
v_lshrrev_b32_e32 v5, 11, v5
v_mul_hi_u32 v12, v22, s14
v_mul_hi_u32 v22, v23, s14
v_mul_hi_u32 v17, v17, s14
v_or_b32_e32 v9, v9, v1
v_mad_i32_i24 v18, v5, s15, v18
s_clause 0x3
s_load_dwordx2 s[10:11], s[4:5], 0x0
s_load_dwordx2 s[12:13], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[4:5], s[4:5], 0x18
v_lshlrev_b32_e32 v6, 8, v6
v_mul_i32_i24_e32 v5, s16, v5
v_lshl_add_u32 v33, v9, 1, s1
v_lshrrev_b32_e32 v12, 11, v12
v_lshrrev_b32_e32 v9, 11, v17
v_or_b32_e32 v17, v18, v1
v_lshrrev_b32_e32 v18, 11, v22
v_add3_u32 v34, v10, v6, v5
v_mad_i32_i24 v6, v12, s15, v8
v_mad_i32_i24 v7, v9, s15, v7
v_mul_i32_i24_e32 v5, s16, v9
v_mad_i32_i24 v8, v18, s15, v16
v_lshlrev_b32_e32 v13, 4, v0
v_mul_u32_u24_e32 v2, 0x280, v2
v_or_b32_e32 v7, v7, v1
v_add3_u32 v38, v10, v5, v3
v_or_b32_e32 v3, v6, v1
v_or_b32_e32 v5, v8, v1
v_mad_i32_i24 v42, v12, s16, v4
v_mad_i32_i24 v44, v18, s16, v15
v_lshl_add_u32 v36, v17, 1, s1
v_lshl_add_u32 v39, v7, 1, s1
v_lshl_add_u32 v43, v3, 1, s1
v_lshl_add_u32 v45, v5, 1, s1
v_lshl_add_u32 v46, v2, 1, s1
v_add_nc_u32_e32 v14, s1, v13
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v31, 0
v_mov_b32_e32 v29, 0
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v41, 0
v_mov_b32_e32 v37, 0
v_mov_b32_e32 v30, 0
v_mov_b32_e32 v28, 0
v_mov_b32_e32 v49, 0
v_mov_b32_e32 v47, 0
v_mov_b32_e32 v40, 0
v_mov_b32_e32 v35, 0
v_mov_b32_e32 v52, 0
v_mov_b32_e32 v51, 0
v_mov_b32_e32 v50, 0
v_mov_b32_e32 v48, 0
v_mov_b32_e32 v57, 0
v_mov_b32_e32 v58, 0
v_mov_b32_e32 v55, 0
v_mov_b32_e32 v56, 0
v_mov_b32_e32 v53, 0
v_mov_b32_e32 v54, 0
v_mov_b32_e32 v59, 0
v_mov_b32_e32 v60, 0
s_mov_b32 s14, 0
BB56_1:
v_lshl_add_u32 v61, s14, 12, v11
s_lshl_b32 s15, s14, 6
v_add_nc_u32_e32 v63, s15, v19
v_add_nc_u32_e32 v78, s15, v20
v_ashrrev_i32_e32 v62, 31, v61
v_add_nc_u32_e32 v80, s15, v24
v_add_nc_u32_e32 v86, s15, v32
v_ashrrev_i32_e32 v64, 31, v63
v_ashrrev_i32_e32 v79, 31, v78
v_lshlrev_b64 v[61:62], 1, v[61:62]
v_ashrrev_i32_e32 v81, 31, v80
v_add_nc_u32_e32 v88, s15, v34
v_lshlrev_b64 v[63:64], 1, v[63:64]
v_lshlrev_b64 v[78:79], 1, v[78:79]
v_ashrrev_i32_e32 v87, 31, v86
s_waitcnt lgkmcnt(0)
v_add_co_u32 v82, vcc_lo, s12, v61
v_add_nc_u32_e32 v90, s15, v38
v_add_co_ci_u32_e32 v83, vcc_lo, s13, v62, vcc_lo
v_add_co_u32 v84, vcc_lo, s10, v63
v_lshlrev_b64 v[80:81], 1, v[80:81]
v_add_co_ci_u32_e32 v85, vcc_lo, s11, v64, vcc_lo
v_add_co_u32 v74, vcc_lo, v82, s8
v_ashrrev_i32_e32 v89, 31, v88
v_add_co_ci_u32_e32 v75, vcc_lo, 0, v83, vcc_lo
v_add_nc_u32_e32 v92, s15, v42
v_add_co_u32 v96, vcc_lo, s10, v78
v_lshlrev_b64 v[86:87], 1, v[86:87]
v_ashrrev_i32_e32 v91, 31, v90
v_add_nc_u32_e32 v94, s15, v44
v_add_co_ci_u32_e32 v97, vcc_lo, s11, v79, vcc_lo
v_add_co_u32 v98, vcc_lo, s10, v80
v_lshlrev_b64 v[88:89], 1, v[88:89]
v_ashrrev_i32_e32 v93, 31, v92
v_add_co_ci_u32_e32 v99, vcc_lo, s11, v81, vcc_lo
v_add_co_u32 v100, vcc_lo, s10, v86
v_lshlrev_b64 v[90:91], 1, v[90:91]
v_ashrrev_i32_e32 v95, 31, v94
v_add_co_ci_u32_e32 v101, vcc_lo, s11, v87, vcc_lo
v_add_co_u32 v102, vcc_lo, s10, v88
v_lshlrev_b64 v[92:93], 1, v[92:93]
v_add_co_ci_u32_e32 v103, vcc_lo, s11, v89, vcc_lo
v_add_co_u32 v106, vcc_lo, s10, v90
v_lshlrev_b64 v[94:95], 1, v[94:95]
v_add_co_ci_u32_e32 v107, vcc_lo, s11, v91, vcc_lo
global_load_dwordx4 v[62:65], v[82:83], off
global_load_dwordx4 v[66:69], v[84:85], off
s_clause 0x1
global_load_dwordx4 v[70:73], v[74:75], off offset:-2048
global_load_dwordx4 v[74:77], v[74:75], off
v_add_co_u32 v110, vcc_lo, s10, v92
v_mov_b32_e32 v61, v46
v_add_co_ci_u32_e32 v111, vcc_lo, s11, v93, vcc_lo
v_add_co_u32 v114, vcc_lo, s10, v94
s_mov_b32 s15, 0
v_add_co_ci_u32_e32 v115, vcc_lo, s11, v95, vcc_lo
v_add_co_u32 v78, vcc_lo, s9, v82
v_add_co_ci_u32_e32 v79, vcc_lo, 0, v83, vcc_lo
v_add_co_u32 v82, vcc_lo, s1, v84
v_add_co_ci_u32_e32 v83, vcc_lo, 0, v85, vcc_lo
v_add_co_u32 v104, vcc_lo, s0, v84
v_add_co_ci_u32_e32 v105, vcc_lo, 0, v85, vcc_lo
global_load_dwordx4 v[78:81], v[78:79], off
s_clause 0x8
global_load_dwordx4 v[82:85], v[82:83], off
global_load_dwordx4 v[86:89], v[96:97], off
global_load_dwordx4 v[90:93], v[98:99], off
global_load_dwordx4 v[94:97], v[100:101], off
global_load_dwordx4 v[98:101], v[104:105], off
global_load_dwordx4 v[102:105], v[102:103], off
global_load_dwordx4 v[106:109], v[106:107], off
global_load_dwordx4 v[110:113], v[110:111], off
global_load_dwordx4 v[114:117], v[114:115], off
s_waitcnt vmcnt(0)
s_barrier
ds_write_b128 v13, v[62:65]
ds_write_b128 v14, v[66:69]
ds_write_b128 v13, v[70:73] offset:2048
ds_write_b128 v13, v[74:77] offset:4096
ds_write_b128 v13, v[78:81] offset:6144
ds_write_b128 v14, v[82:85] offset:2048
ds_write_b128 v21, v[86:89]
ds_write_b128 v26, v[90:93]
ds_write_b128 v33, v[94:97]
ds_write_b128 v14, v[98:101] offset:10240
ds_write_b128 v36, v[102:105]
ds_write_b128 v39, v[106:109]
ds_write_b128 v43, v[110:113]
ds_write_b128 v45, v[114:117]
s_waitcnt lgkmcnt(0)
s_barrier
BB56_2:
v_or_b32_e32 v82, s15, v1
ds_read2_b64 v[62:65], v61 offset1:16
ds_read2_b64 v[66:69], v61 offset0:32 offset1:48
ds_read2_b64 v[70:73], v61 offset0:64 offset1:80
ds_read2_b64 v[74:77], v61 offset0:96 offset1:112
ds_read2_b64 v[78:81], v61 offset0:128 offset1:144
v_add_nc_u32_e32 v61, 8, v61
s_addk_i32 s15, 0x100
v_lshlrev_b32_e32 v90, 1, v82
s_cmp_lg_u32 s15, s8
ds_read2_b32 v[94:95], v90 offset1:1
ds_read2_b32 v[96:97], v90 offset0:2 offset1:3
ds_read_b128 v[82:85], v90 offset:128
ds_read_b128 v[86:89], v90 offset:256
ds_read_b128 v[90:93], v90 offset:384
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v57, v62, v94, v57 op_sel_hi:[0,1,1]
v_pk_fma_f16 v58, v62, v95, v58 op_sel_hi:[0,1,1]
v_pk_fma_f16 v60, v64, v94, v60 op_sel_hi:[0,1,1]
v_pk_fma_f16 v59, v64, v95, v59 op_sel_hi:[0,1,1]
v_pk_fma_f16 v52, v66, v94, v52 op_sel_hi:[0,1,1]
v_pk_fma_f16 v51, v66, v95, v51 op_sel_hi:[0,1,1]
v_pk_fma_f16 v49, v68, v94, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v47, v68, v95, v47 op_sel_hi:[0,1,1]
v_pk_fma_f16 v41, v70, v94, v41 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v70, v95, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v72, v94, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v72, v95, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v74, v94, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v74, v95, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v76, v94, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v76, v95, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v78, v94, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v78, v95, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v80, v94, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v80, v95, v5 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v55, v62, v96, v55 op_sel_hi:[0,1,1]
v_pk_fma_f16 v56, v62, v97, v56 op_sel_hi:[0,1,1]
v_pk_fma_f16 v54, v64, v96, v54 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v64, v97, v53 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v66, v96, v50 op_sel_hi:[0,1,1]
v_pk_fma_f16 v48, v66, v97, v48 op_sel_hi:[0,1,1]
v_pk_fma_f16 v40, v68, v96, v40 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v68, v97, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v70, v96, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v70, v97, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v72, v96, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v72, v97, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v74, v96, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v74, v97, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v76, v96, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v76, v97, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v78, v96, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v78, v97, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v80, v96, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v80, v97, v2 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v57, v62, v82, v57 op_sel:[1,0,0]
v_pk_fma_f16 v58, v62, v83, v58 op_sel:[1,0,0]
v_pk_fma_f16 v55, v62, v84, v55 op_sel:[1,0,0]
v_pk_fma_f16 v56, v62, v85, v56 op_sel:[1,0,0]
v_pk_fma_f16 v60, v64, v82, v60 op_sel:[1,0,0]
v_pk_fma_f16 v59, v64, v83, v59 op_sel:[1,0,0]
v_pk_fma_f16 v54, v64, v84, v54 op_sel:[1,0,0]
v_pk_fma_f16 v53, v64, v85, v53 op_sel:[1,0,0]
v_pk_fma_f16 v52, v66, v82, v52 op_sel:[1,0,0]
v_pk_fma_f16 v51, v66, v83, v51 op_sel:[1,0,0]
v_pk_fma_f16 v50, v66, v84, v50 op_sel:[1,0,0]
v_pk_fma_f16 v48, v66, v85, v48 op_sel:[1,0,0]
v_pk_fma_f16 v49, v68, v82, v49 op_sel:[1,0,0]
v_pk_fma_f16 v47, v68, v83, v47 op_sel:[1,0,0]
v_pk_fma_f16 v40, v68, v84, v40 op_sel:[1,0,0]
v_pk_fma_f16 v35, v68, v85, v35 op_sel:[1,0,0]
v_pk_fma_f16 v41, v70, v82, v41 op_sel:[1,0,0]
v_pk_fma_f16 v37, v70, v83, v37 op_sel:[1,0,0]
v_pk_fma_f16 v30, v70, v84, v30 op_sel:[1,0,0]
v_pk_fma_f16 v28, v70, v85, v28 op_sel:[1,0,0]
v_pk_fma_f16 v31, v72, v82, v31 op_sel:[1,0,0]
v_pk_fma_f16 v29, v72, v83, v29 op_sel:[1,0,0]
v_pk_fma_f16 v25, v72, v84, v25 op_sel:[1,0,0]
v_pk_fma_f16 v22, v72, v85, v22 op_sel:[1,0,0]
v_pk_fma_f16 v27, v74, v82, v27 op_sel:[1,0,0]
v_pk_fma_f16 v23, v74, v83, v23 op_sel:[1,0,0]
v_pk_fma_f16 v17, v74, v84, v17 op_sel:[1,0,0]
v_pk_fma_f16 v15, v74, v85, v15 op_sel:[1,0,0]
v_pk_fma_f16 v18, v76, v82, v18 op_sel:[1,0,0]
v_pk_fma_f16 v16, v76, v83, v16 op_sel:[1,0,0]
v_pk_fma_f16 v10, v76, v84, v10 op_sel:[1,0,0]
v_pk_fma_f16 v8, v76, v85, v8 op_sel:[1,0,0]
v_pk_fma_f16 v12, v78, v82, v12 op_sel:[1,0,0]
v_pk_fma_f16 v9, v78, v83, v9 op_sel:[1,0,0]
v_pk_fma_f16 v7, v78, v84, v7 op_sel:[1,0,0]
v_pk_fma_f16 v4, v78, v85, v4 op_sel:[1,0,0]
v_pk_fma_f16 v6, v80, v82, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v80, v83, v5 op_sel:[1,0,0]
v_pk_fma_f16 v3, v80, v84, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v80, v85, v2 op_sel:[1,0,0]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v57, v63, v86, v57 op_sel_hi:[0,1,1]
v_pk_fma_f16 v58, v63, v87, v58 op_sel_hi:[0,1,1]
v_pk_fma_f16 v55, v63, v88, v55 op_sel_hi:[0,1,1]
v_pk_fma_f16 v56, v63, v89, v56 op_sel_hi:[0,1,1]
v_pk_fma_f16 v60, v65, v86, v60 op_sel_hi:[0,1,1]
v_pk_fma_f16 v59, v65, v87, v59 op_sel_hi:[0,1,1]
v_pk_fma_f16 v54, v65, v88, v54 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v65, v89, v53 op_sel_hi:[0,1,1]
v_pk_fma_f16 v52, v67, v86, v52 op_sel_hi:[0,1,1]
v_pk_fma_f16 v51, v67, v87, v51 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v67, v88, v50 op_sel_hi:[0,1,1]
v_pk_fma_f16 v48, v67, v89, v48 op_sel_hi:[0,1,1]
v_pk_fma_f16 v49, v69, v86, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v47, v69, v87, v47 op_sel_hi:[0,1,1]
v_pk_fma_f16 v40, v69, v88, v40 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v69, v89, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v41, v71, v86, v41 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v71, v87, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v71, v88, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v71, v89, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v73, v86, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v73, v87, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v73, v88, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v73, v89, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v75, v86, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v75, v87, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v75, v88, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v75, v89, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v77, v86, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v77, v87, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v77, v88, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v77, v89, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v79, v86, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v79, v87, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v79, v88, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v79, v89, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v81, v86, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v81, v87, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v81, v88, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v81, v89, v2 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v57, v63, v90, v57 op_sel:[1,0,0]
v_pk_fma_f16 v58, v63, v91, v58 op_sel:[1,0,0]
v_pk_fma_f16 v55, v63, v92, v55 op_sel:[1,0,0]
v_pk_fma_f16 v56, v63, v93, v56 op_sel:[1,0,0]
v_pk_fma_f16 v60, v65, v90, v60 op_sel:[1,0,0]
v_pk_fma_f16 v59, v65, v91, v59 op_sel:[1,0,0]
v_pk_fma_f16 v54, v65, v92, v54 op_sel:[1,0,0]
v_pk_fma_f16 v53, v65, v93, v53 op_sel:[1,0,0]
v_pk_fma_f16 v52, v67, v90, v52 op_sel:[1,0,0]
v_pk_fma_f16 v51, v67, v91, v51 op_sel:[1,0,0]
v_pk_fma_f16 v50, v67, v92, v50 op_sel:[1,0,0]
v_pk_fma_f16 v48, v67, v93, v48 op_sel:[1,0,0]
v_pk_fma_f16 v49, v69, v90, v49 op_sel:[1,0,0]
v_pk_fma_f16 v47, v69, v91, v47 op_sel:[1,0,0]
v_pk_fma_f16 v40, v69, v92, v40 op_sel:[1,0,0]
v_pk_fma_f16 v35, v69, v93, v35 op_sel:[1,0,0]
v_pk_fma_f16 v41, v71, v90, v41 op_sel:[1,0,0]
v_pk_fma_f16 v37, v71, v91, v37 op_sel:[1,0,0]
v_pk_fma_f16 v30, v71, v92, v30 op_sel:[1,0,0]
v_pk_fma_f16 v28, v71, v93, v28 op_sel:[1,0,0]
v_pk_fma_f16 v31, v73, v90, v31 op_sel:[1,0,0]
v_pk_fma_f16 v29, v73, v91, v29 op_sel:[1,0,0]
v_pk_fma_f16 v25, v73, v92, v25 op_sel:[1,0,0]
v_pk_fma_f16 v22, v73, v93, v22 op_sel:[1,0,0]
v_pk_fma_f16 v27, v75, v90, v27 op_sel:[1,0,0]
v_pk_fma_f16 v23, v75, v91, v23 op_sel:[1,0,0]
v_pk_fma_f16 v17, v75, v92, v17 op_sel:[1,0,0]
v_pk_fma_f16 v15, v75, v93, v15 op_sel:[1,0,0]
v_pk_fma_f16 v18, v77, v90, v18 op_sel:[1,0,0]
v_pk_fma_f16 v16, v77, v91, v16 op_sel:[1,0,0]
v_pk_fma_f16 v10, v77, v92, v10 op_sel:[1,0,0]
v_pk_fma_f16 v8, v77, v93, v8 op_sel:[1,0,0]
v_pk_fma_f16 v12, v79, v90, v12 op_sel:[1,0,0]
v_pk_fma_f16 v9, v79, v91, v9 op_sel:[1,0,0]
v_pk_fma_f16 v7, v79, v92, v7 op_sel:[1,0,0]
v_pk_fma_f16 v4, v79, v93, v4 op_sel:[1,0,0]
v_pk_fma_f16 v6, v81, v90, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v81, v91, v5 op_sel:[1,0,0]
v_pk_fma_f16 v3, v81, v92, v3 op_sel:[1,0,0]
v_pk_fma_f16 v2, v81, v93, v2 op_sel:[1,0,0]
s_cbranch_scc1 BB56_2
s_add_i32 s14, s14, 1
s_cmp_eq_u32 s14, 4
s_cbranch_scc0 BB56_1
v_lshlrev_b32_e32 v11, 1, v1
v_lshrrev_b32_e32 v20, 5, v0
s_mulk_i32 s6, 0xa00
s_mul_i32 s7, s7, 0xc800
v_bfe_u32 v0, v0, 3, 2
s_clause 0x3
global_load_dword v13, v11, s[4:5]
global_load_dword v14, v11, s[4:5] offset:4
global_load_dword v19, v11, s[4:5] offset:8
global_load_dword v11, v11, s[4:5] offset:12
v_mul_u32_u24_e32 v20, 0x3200, v20
v_add3_u32 v20, s6, s7, v20
v_or_b32_e32 v1, v20, v1
v_mov_b32_e32 v20, 0
v_mad_u32_u24 v0, 0x280, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(3)
v_pk_add_f16 v21, v13, v57
s_waitcnt vmcnt(2)
v_pk_add_f16 v24, v14, v58
s_waitcnt vmcnt(1)
v_pk_add_f16 v26, v19, v55
s_waitcnt vmcnt(0)
v_pk_add_f16 v32, v11, v56
v_pk_add_f16 v33, v13, v60
v_pk_add_f16 v40, v19, v40
v_pk_add_f16 v35, v11, v35
v_pk_add_f16 v41, v13, v41
v_pk_add_f16 v37, v14, v37
v_pk_add_f16 v30, v19, v30
v_pk_add_f16 v28, v11, v28
v_pk_add_f16 v31, v13, v31
v_pk_add_f16 v29, v14, v29
v_pk_add_f16 v25, v19, v25
v_pk_add_f16 v22, v11, v22
v_pk_add_f16 v27, v13, v27
v_pk_add_f16 v23, v14, v23
v_pk_add_f16 v17, v19, v17
v_pk_add_f16 v15, v11, v15
v_pk_add_f16 v18, v13, v18
v_pk_add_f16 v16, v14, v16
v_pk_add_f16 v10, v19, v10
v_pk_add_f16 v8, v11, v8
v_pk_add_f16 v12, v13, v12
v_pk_add_f16 v9, v14, v9
v_pk_add_f16 v7, v19, v7
v_pk_add_f16 v4, v11, v4
v_pk_add_f16 v6, v13, v6
v_pk_add_f16 v5, v14, v5
v_pk_add_f16 v3, v19, v3
v_pk_add_f16 v2, v11, v2
v_pk_add_f16 v34, v14, v59
v_pk_add_f16 v36, v19, v54
v_pk_add_f16 v43, v19, v50
v_pk_add_f16 v38, v11, v53
v_pk_add_f16 v44, v11, v48
v_pk_max_f16 v11, v21, 0
v_pk_add_f16 v39, v13, v52
v_pk_add_f16 v45, v13, v49
v_pk_add_f16 v42, v14, v51
v_pk_add_f16 v46, v14, v47
v_pk_max_f16 v13, v24, 0
v_pk_max_f16 v14, v26, 0
v_pk_max_f16 v19, v32, 0
v_max_f16_e32 v21, 0, v33
v_max_f16_sdwa v24, v33, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
v_max_f16_e32 v26, 0, v34
v_max_f16_sdwa v32, v34, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
v_max_f16_sdwa v34, v36, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
v_max_f16_e32 v33, 0, v36
v_max_f16_e32 v36, 0, v38
v_max_f16_sdwa v20, v38, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
v_pk_max_f16 v38, v39, 0
v_pk_max_f16 v39, v42, 0
v_pk_max_f16 v42, v43, 0
v_pk_max_f16 v43, v44, 0
v_pk_max_f16 v44, v45, 0
v_pk_max_f16 v45, v46, 0
v_pk_max_f16 v40, v40, 0
v_pk_max_f16 v35, v35, 0
v_pk_max_f16 v41, v41, 0
v_pk_max_f16 v37, v37, 0
v_pk_max_f16 v30, v30, 0
v_pk_max_f16 v28, v28, 0
v_pk_max_f16 v31, v31, 0
v_pk_max_f16 v29, v29, 0
v_pk_max_f16 v25, v25, 0
v_pk_max_f16 v22, v22, 0
v_pk_max_f16 v27, v27, 0
v_pk_max_f16 v23, v23, 0
v_pk_max_f16 v17, v17, 0
v_pk_max_f16 v15, v15, 0
v_pk_max_f16 v18, v18, 0
v_pk_max_f16 v16, v16, 0
v_pk_max_f16 v10, v10, 0
v_pk_max_f16 v8, v8, 0
v_pk_max_f16 v12, v12, 0
v_pk_max_f16 v9, v9, 0
v_pk_max_f16 v7, v7, 0
v_pk_max_f16 v4, v4, 0
v_pk_max_f16 v6, v6, 0
v_pk_max_f16 v5, v5, 0
v_pk_max_f16 v3, v3, 0
v_pk_max_f16 v2, v2, 0
global_store_dword v[0:1], v11, off
global_store_dword v[0:1], v13, off offset:4
global_store_dword v[0:1], v14, off offset:8
global_store_dword v[0:1], v19, off offset:12
global_store_short v[0:1], v21, off offset:128
global_store_short v[0:1], v24, off offset:130
global_store_short v[0:1], v26, off offset:132
global_store_short v[0:1], v32, off offset:134
global_store_short v[0:1], v33, off offset:136
global_store_short v[0:1], v34, off offset:138
global_store_short v[0:1], v36, off offset:140
global_store_short v[0:1], v20, off offset:142
global_store_dword v[0:1], v38, off offset:256
global_store_dword v[0:1], v39, off offset:260
global_store_dword v[0:1], v42, off offset:264
global_store_dword v[0:1], v43, off offset:268
global_store_dword v[0:1], v44, off offset:384
global_store_dword v[0:1], v45, off offset:388
global_store_dword v[0:1], v40, off offset:392
global_store_dword v[0:1], v35, off offset:396
global_store_dword v[0:1], v41, off offset:512
global_store_dword v[0:1], v37, off offset:516
global_store_dword v[0:1], v30, off offset:520
global_store_dword v[0:1], v28, off offset:524
global_store_dword v[0:1], v31, off offset:640
global_store_dword v[0:1], v29, off offset:644
global_store_dword v[0:1], v25, off offset:648
global_store_dword v[0:1], v22, off offset:652
global_store_dword v[0:1], v27, off offset:768
global_store_dword v[0:1], v23, off offset:772
global_store_dword v[0:1], v17, off offset:776
global_store_dword v[0:1], v15, off offset:780
global_store_dword v[0:1], v18, off offset:896
global_store_dword v[0:1], v16, off offset:900
global_store_dword v[0:1], v10, off offset:904
global_store_dword v[0:1], v8, off offset:908
global_store_dword v[0:1], v12, off offset:1024
global_store_dword v[0:1], v9, off offset:1028
global_store_dword v[0:1], v7, off offset:1032
global_store_dword v[0:1], v4, off offset:1036
global_store_dword v[0:1], v6, off offset:1152
global_store_dword v[0:1], v5, off offset:1156
global_store_dword v[0:1], v3, off offset:1160
global_store_dword v[0:1], v2, off offset:1164
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_nn_relu_2_kernel0
.amdhsa_group_segment_fixed_size 28672
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 118
.amdhsa_next_free_sgpr 18
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end56:
.size tvmgen_default_fused_nn_conv2d_add_nn_relu_2_kernel0, .Lfunc_end56-tvmgen_default_fused_nn_conv2d_add_nn_relu_2_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_nn_relu_3_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_nn_relu_3_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_nn_relu_3_kernel0:
v_lshrrev_b32_e32 v1, 4, v0
s_mov_b32 s12, 0xcccccccd
v_lshlrev_b32_e32 v21, 2, v0
s_mul_hi_i32 s15, s6, 0x66666667
s_clause 0x3
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[0:1], s[4:5], 0x10
s_load_dwordx2 s[2:3], s[4:5], 0x18
v_add_nc_u32_e32 v2, 16, v1
v_add_nc_u32_e32 v4, 12, v1
v_add_nc_u32_e32 v5, 0x400, v21
v_add_nc_u32_e32 v8, 8, v1
s_lshr_b32 s4, s15, 31
v_mul_hi_u32 v3, v2, s12
v_mul_hi_u32 v7, v4, s12
v_mul_hi_u32 v5, v5, s12
s_ashr_i32 s5, s15, 2
s_movk_i32 s13, 0x500
s_add_i32 s4, s5, s4
v_add_nc_u32_e32 v9, 0x800, v21
s_mul_i32 s5, s4, 10
v_lshrrev_b32_e32 v3, 4, v3
v_lshrrev_b32_e32 v7, 4, v7
v_lshrrev_b32_e32 v5, 10, v5
v_and_b32_e32 v6, 60, v21
s_sub_i32 s5, s6, s5
v_mul_u32_u24_e32 v3, 20, v3
v_mul_u32_u24_e32 v7, 20, v7
s_mul_i32 s15, s4, 0x32000
s_mul_i32 s6, s5, 0x1400
v_mul_hi_u32 v9, v9, s12
v_sub_nc_u32_e32 v2, v2, v3
v_mul_hi_u32 v3, v8, s12
v_sub_nc_u32_e32 v4, v4, v7
s_add_i32 s15, s15, s6
s_movk_i32 s6, 0x1000
v_lshlrev_b32_e32 v10, 6, v2
v_lshl_add_u32 v11, v1, 8, s15
s_mov_b32 s14, 0xc800
v_lshlrev_b32_e32 v12, 6, v4
v_lshrrev_b32_e32 v3, 4, v3
v_mad_i32_i24 v10, v5, s13, v10
v_or_b32_e32 v24, v11, v6
s_movk_i32 s7, 0x4000
v_lshlrev_b32_e32 v2, 8, v2
v_mul_u32_u24_e32 v3, 20, v3
v_or_b32_e32 v7, v10, v6
v_add_nc_u32_e32 v10, 0xc00, v21
v_mul_i32_i24_e32 v5, s14, v5
v_or_b32_e32 v11, s15, v6
v_sub_nc_u32_e32 v3, v8, v3
v_or_b32_e32 v8, s6, v21
v_mul_hi_u32 v10, v10, s12
v_lshrrev_b32_e32 v9, 10, v9
v_lshl_add_u32 v27, v7, 1, s7
v_add3_u32 v26, v11, v5, v2
v_mul_hi_u32 v7, v8, s12
v_lshlrev_b32_e32 v5, 6, v3
v_mad_i32_i24 v2, v9, s13, v12
v_add_nc_u32_e32 v1, 4, v1
v_lshrrev_b32_e32 v8, 10, v10
v_lshlrev_b32_e32 v4, 8, v4
v_mul_i32_i24_e32 v9, s14, v9
v_or_b32_e32 v2, v2, v6
v_lshlrev_b32_e32 v10, 6, v1
v_mad_i32_i24 v5, v8, s13, v5
v_lshrrev_b32_e32 v7, 10, v7
v_add3_u32 v28, v11, v9, v4
v_lshl_add_u32 v29, v2, 1, s7
v_lshlrev_b32_e32 v3, 8, v3
v_or_b32_e32 v2, v5, v6
v_mad_i32_i24 v4, v7, s13, v10
v_mul_i32_i24_e32 v5, s14, v8
v_lshrrev_b32_e32 v8, 5, v0
v_lshlrev_b32_e32 v22, 3, v0
v_lshlrev_b32_e32 v1, 8, v1
v_or_b32_e32 v4, v4, v6
v_add3_u32 v30, v11, v5, v3
v_mul_u32_u24_e32 v3, 0x280, v8
v_mul_i32_i24_e32 v7, s14, v7
v_lshl_add_u32 v31, v2, 1, s7
v_lshl_add_u32 v33, v4, 1, s7
v_or_b32_e32 v23, s7, v22
v_lshl_add_u32 v34, v3, 1, s7
v_add3_u32 v32, v11, v1, v7
v_and_b32_e32 v25, 0x7c, v21
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v20, 0
s_mov_b32 s7, 0
s_movk_i32 s12, 0x2000
BB57_1:
s_lshl_b32 s13, s7, 6
v_lshl_or_b32 v43, s7, 13, v21
v_add_nc_u32_e32 v35, s13, v24
v_add_nc_u32_e32 v37, s13, v26
v_add_nc_u32_e32 v39, s13, v28
v_add_nc_u32_e32 v41, s13, v30
v_add_nc_u32_e32 v45, s13, v32
v_ashrrev_i32_e32 v36, 31, v35
v_ashrrev_i32_e32 v38, 31, v37
v_ashrrev_i32_e32 v40, 31, v39
v_ashrrev_i32_e32 v42, 31, v41
v_ashrrev_i32_e32 v44, 31, v43
v_lshlrev_b64 v[35:36], 1, v[35:36]
v_lshlrev_b64 v[37:38], 1, v[37:38]
v_lshlrev_b64 v[39:40], 1, v[39:40]
v_lshlrev_b64 v[41:42], 1, v[41:42]
v_ashrrev_i32_e32 v46, 31, v45
v_lshlrev_b64 v[43:44], 1, v[43:44]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v35, vcc_lo, s8, v35
s_mov_b32 s13, 0
v_add_co_ci_u32_e32 v36, vcc_lo, s9, v36, vcc_lo
v_add_co_u32 v37, vcc_lo, s8, v37
v_lshlrev_b64 v[45:46], 1, v[45:46]
v_add_co_ci_u32_e32 v38, vcc_lo, s9, v38, vcc_lo
v_add_co_u32 v39, vcc_lo, s8, v39
v_add_co_ci_u32_e32 v40, vcc_lo, s9, v40, vcc_lo
v_add_co_u32 v41, vcc_lo, s8, v41
v_add_co_ci_u32_e32 v42, vcc_lo, s9, v42, vcc_lo
v_add_co_u32 v43, vcc_lo, s10, v43
v_add_co_ci_u32_e32 v44, vcc_lo, s11, v44, vcc_lo
v_add_co_u32 v45, vcc_lo, s8, v45
v_add_co_ci_u32_e32 v46, vcc_lo, s9, v46, vcc_lo
v_add_co_u32 v47, vcc_lo, v43, s6
v_add_co_ci_u32_e32 v48, vcc_lo, 0, v44, vcc_lo
v_add_co_u32 v55, vcc_lo, v43, s12
s_clause 0x4
global_load_dwordx2 v[49:50], v[35:36], off
global_load_dwordx2 v[36:37], v[37:38], off
global_load_dwordx2 v[38:39], v[39:40], off
global_load_dwordx2 v[40:41], v[41:42], off
global_load_dwordx2 v[45:46], v[45:46], off
s_clause 0x2
global_load_dwordx2 v[51:52], v[43:44], off
global_load_dwordx2 v[53:54], v[47:48], off offset:-2048
global_load_dwordx2 v[47:48], v[47:48], off
v_add_co_ci_u32_e32 v56, vcc_lo, 0, v44, vcc_lo
v_add_co_u32 v57, vcc_lo, v43, 0x3000
v_mov_b32_e32 v35, v34
v_add_co_ci_u32_e32 v58, vcc_lo, 0, v44, vcc_lo
v_add_co_u32 v42, vcc_lo, 0x3800, v43
v_add_co_ci_u32_e32 v43, vcc_lo, 0, v44, vcc_lo
s_clause 0x4
global_load_dwordx2 v[59:60], v[55:56], off offset:-2048
global_load_dwordx2 v[55:56], v[55:56], off
global_load_dwordx2 v[61:62], v[57:58], off offset:-2048
global_load_dwordx2 v[57:58], v[57:58], off
global_load_dwordx2 v[42:43], v[42:43], off
s_waitcnt vmcnt(0)
s_barrier
ds_write_b64 v23, v[49:50]
ds_write_b64 v27, v[36:37]
ds_write_b64 v29, v[38:39]
ds_write_b64 v31, v[40:41]
ds_write_b64 v33, v[45:46]
ds_write2st64_b64 v22, v[51:52], v[53:54] offset1:4
ds_write2st64_b64 v22, v[47:48], v[59:60] offset0:8 offset1:12
ds_write2st64_b64 v22, v[55:56], v[61:62] offset0:16 offset1:20
ds_write2st64_b64 v22, v[57:58], v[42:43] offset0:24 offset1:28
s_waitcnt lgkmcnt(0)
s_barrier
BB57_2:
v_or_b32_e32 v56, s13, v25
ds_read2_b64 v[36:39], v35 offset1:16
ds_read2_b64 v[40:43], v35 offset0:32 offset1:48
ds_read2_b64 v[44:47], v35 offset0:64 offset1:80
ds_read2_b64 v[48:51], v35 offset0:96 offset1:112
ds_read2_b64 v[52:55], v35 offset0:128 offset1:144
v_add_nc_u32_e32 v35, 8, v35
s_addk_i32 s13, 0x200
v_lshlrev_b32_e32 v56, 1, v56
s_cmp_lg_u32 s13, s12
ds_read2_b32 v[60:61], v56 offset1:1
ds_read_b64 v[62:63], v56 offset:768
ds_read2_b64 v[56:59], v56 offset0:32 offset1:64
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v17, v36, v60, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v36, v61, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v38, v60, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v38, v61, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v40, v60, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v40, v61, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v42, v60, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v42, v61, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v44, v60, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v44, v61, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v46, v60, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v46, v61, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v48, v60, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v48, v61, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v50, v60, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v50, v61, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v52, v60, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v52, v61, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v54, v60, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v54, v61, v2 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v17, v36, v56, v17 op_sel:[1,0,0]
v_pk_fma_f16 v18, v36, v57, v18 op_sel:[1,0,0]
v_pk_fma_f16 v19, v38, v56, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v38, v57, v20 op_sel:[1,0,0]
v_pk_fma_f16 v15, v40, v56, v15 op_sel:[1,0,0]
v_pk_fma_f16 v16, v40, v57, v16 op_sel:[1,0,0]
v_pk_fma_f16 v13, v42, v56, v13 op_sel:[1,0,0]
v_pk_fma_f16 v14, v42, v57, v14 op_sel:[1,0,0]
v_pk_fma_f16 v11, v44, v56, v11 op_sel:[1,0,0]
v_pk_fma_f16 v12, v44, v57, v12 op_sel:[1,0,0]
v_pk_fma_f16 v9, v46, v56, v9 op_sel:[1,0,0]
v_pk_fma_f16 v10, v46, v57, v10 op_sel:[1,0,0]
v_pk_fma_f16 v7, v48, v56, v7 op_sel:[1,0,0]
v_pk_fma_f16 v8, v48, v57, v8 op_sel:[1,0,0]
v_pk_fma_f16 v5, v50, v56, v5 op_sel:[1,0,0]
v_pk_fma_f16 v6, v50, v57, v6 op_sel:[1,0,0]
v_pk_fma_f16 v3, v52, v56, v3 op_sel:[1,0,0]
v_pk_fma_f16 v4, v52, v57, v4 op_sel:[1,0,0]
v_pk_fma_f16 v1, v54, v56, v1 op_sel:[1,0,0]
v_pk_fma_f16 v2, v54, v57, v2 op_sel:[1,0,0]
v_pk_fma_f16 v17, v37, v58, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v37, v59, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v39, v58, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v39, v59, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v41, v58, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v41, v59, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v43, v58, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v43, v59, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v45, v58, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v45, v59, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v47, v58, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v47, v59, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v49, v58, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v49, v59, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v51, v58, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v51, v59, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v53, v58, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v53, v59, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v55, v58, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v55, v59, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v37, v62, v17 op_sel:[1,0,0]
v_pk_fma_f16 v18, v37, v63, v18 op_sel:[1,0,0]
v_pk_fma_f16 v19, v39, v62, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v39, v63, v20 op_sel:[1,0,0]
v_pk_fma_f16 v15, v41, v62, v15 op_sel:[1,0,0]
v_pk_fma_f16 v16, v41, v63, v16 op_sel:[1,0,0]
v_pk_fma_f16 v13, v43, v62, v13 op_sel:[1,0,0]
v_pk_fma_f16 v14, v43, v63, v14 op_sel:[1,0,0]
v_pk_fma_f16 v11, v45, v62, v11 op_sel:[1,0,0]
v_pk_fma_f16 v12, v45, v63, v12 op_sel:[1,0,0]
v_pk_fma_f16 v9, v47, v62, v9 op_sel:[1,0,0]
v_pk_fma_f16 v10, v47, v63, v10 op_sel:[1,0,0]
v_pk_fma_f16 v7, v49, v62, v7 op_sel:[1,0,0]
v_pk_fma_f16 v8, v49, v63, v8 op_sel:[1,0,0]
v_pk_fma_f16 v5, v51, v62, v5 op_sel:[1,0,0]
v_pk_fma_f16 v6, v51, v63, v6 op_sel:[1,0,0]
v_pk_fma_f16 v3, v53, v62, v3 op_sel:[1,0,0]
v_pk_fma_f16 v4, v53, v63, v4 op_sel:[1,0,0]
v_pk_fma_f16 v1, v55, v62, v1 op_sel:[1,0,0]
v_pk_fma_f16 v2, v55, v63, v2 op_sel:[1,0,0]
s_cbranch_scc1 BB57_2
s_add_i32 s7, s7, 1
s_cmp_eq_u32 s7, 4
s_cbranch_scc0 BB57_1
v_lshlrev_b32_e32 v21, 1, v25
s_mulk_i32 s5, 0xa00
s_mul_i32 s4, s4, 0x19000
s_clause 0x1
global_load_dword v31, v21, s[2:3]
global_load_dword v32, v21, s[2:3] offset:4
v_lshrrev_b32_e32 v21, 6, v0
v_bfe_u32 v0, v0, 5, 1
v_mul_u32_u24_e32 v21, 0x6400, v21
v_add3_u32 v21, s5, s4, v21
v_or_b32_e32 v21, v21, v25
v_mad_u32_u24 v21, 0x500, v0, v21
v_mov_b32_e32 v0, 0
v_add_nc_u32_e32 v23, 0x400, v21
v_ashrrev_i32_e32 v22, 31, v21
v_add_nc_u32_e32 v25, 0x402, v21
v_add_nc_u32_e32 v27, 0x480, v21
v_add_nc_u32_e32 v29, 0x482, v21
v_ashrrev_i32_e32 v24, 31, v23
v_lshlrev_b64 v[21:22], 1, v[21:22]
v_ashrrev_i32_e32 v26, 31, v25
v_ashrrev_i32_e32 v28, 31, v27
v_ashrrev_i32_e32 v30, 31, v29
v_lshlrev_b64 v[23:24], 1, v[23:24]
v_add_co_u32 v21, vcc_lo, s0, v21
v_lshlrev_b64 v[25:26], 1, v[25:26]
v_add_co_ci_u32_e32 v22, vcc_lo, s1, v22, vcc_lo
v_lshlrev_b64 v[27:28], 1, v[27:28]
v_add_co_u32 v23, vcc_lo, s0, v23
v_lshlrev_b64 v[29:30], 1, v[29:30]
v_add_co_ci_u32_e32 v24, vcc_lo, s1, v24, vcc_lo
v_add_co_u32 v25, vcc_lo, s0, v25
v_add_co_ci_u32_e32 v26, vcc_lo, s1, v26, vcc_lo
v_add_co_u32 v27, vcc_lo, s0, v27
v_add_co_ci_u32_e32 v28, vcc_lo, s1, v28, vcc_lo
v_add_co_u32 v29, vcc_lo, s0, v29
v_add_co_ci_u32_e32 v30, vcc_lo, s1, v30, vcc_lo
s_waitcnt vmcnt(1)
v_pk_add_f16 v17, v31, v17
s_waitcnt vmcnt(0)
v_pk_add_f16 v18, v32, v18
v_pk_add_f16 v19, v31, v19
v_pk_add_f16 v20, v32, v20
v_pk_add_f16 v15, v31, v15
v_pk_add_f16 v16, v32, v16
v_pk_add_f16 v13, v31, v13
v_pk_add_f16 v14, v32, v14
v_pk_add_f16 v11, v31, v11
v_pk_add_f16 v12, v32, v12
v_pk_add_f16 v9, v31, v9
v_pk_add_f16 v10, v32, v10
v_pk_add_f16 v7, v31, v7
v_pk_add_f16 v8, v32, v8
v_pk_add_f16 v5, v31, v5
v_pk_add_f16 v6, v32, v6
v_pk_add_f16 v3, v31, v3
v_pk_add_f16 v1, v31, v1
v_pk_add_f16 v4, v32, v4
v_pk_add_f16 v2, v32, v2
v_pk_max_f16 v17, v17, 0
v_pk_max_f16 v18, v18, 0
v_max_f16_e32 v31, 0, v19
v_max_f16_sdwa v19, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
v_max_f16_e32 v32, 0, v20
v_max_f16_sdwa v0, v20, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
v_pk_max_f16 v15, v15, 0
v_pk_max_f16 v16, v16, 0
v_pk_max_f16 v13, v13, 0
v_pk_max_f16 v14, v14, 0
v_pk_max_f16 v11, v11, 0
v_pk_max_f16 v12, v12, 0
v_pk_max_f16 v9, v9, 0
v_pk_max_f16 v10, v10, 0
v_pk_max_f16 v7, v7, 0
v_pk_max_f16 v8, v8, 0
v_pk_max_f16 v5, v5, 0
v_pk_max_f16 v6, v6, 0
v_pk_max_f16 v3, v3, 0
v_pk_max_f16 v4, v4, 0
v_pk_max_f16 v1, v1, 0
v_pk_max_f16 v2, v2, 0
global_store_dword v[21:22], v17, off
global_store_dword v[21:22], v18, off offset:4
global_store_short v[21:22], v31, off offset:256
global_store_short v[21:22], v19, off offset:258
global_store_short v[21:22], v32, off offset:260
global_store_short v[21:22], v0, off offset:262
global_store_dword v[21:22], v15, off offset:512
global_store_dword v[21:22], v16, off offset:516
global_store_dword v[21:22], v13, off offset:768
global_store_dword v[21:22], v14, off offset:772
global_store_dword v[21:22], v11, off offset:1024
global_store_dword v[21:22], v12, off offset:1028
global_store_dword v[21:22], v9, off offset:1280
global_store_dword v[21:22], v10, off offset:1284
global_store_dword v[21:22], v7, off offset:1536
global_store_dword v[21:22], v8, off offset:1540
global_store_dword v[21:22], v5, off offset:1792
global_store_dword v[21:22], v6, off offset:1796
global_store_dword v[23:24], v3, off
global_store_dword v[25:26], v4, off
global_store_dword v[27:28], v1, off
global_store_dword v[29:30], v2, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_nn_relu_3_kernel0
.amdhsa_group_segment_fixed_size 26624
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 64
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end57:
.size tvmgen_default_fused_nn_conv2d_add_nn_relu_3_kernel0, .Lfunc_end57-tvmgen_default_fused_nn_conv2d_add_nn_relu_3_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_nn_relu_4_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_nn_relu_4_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_nn_relu_4_kernel0:
v_mul_hi_i32 v1, 0x30c30c31, v0
s_mul_hi_i32 s0, s6, 0x66666667
v_lshlrev_b32_e32 v5, 2, v0
s_lshr_b32 s1, s0, 31
s_ashr_i32 s7, s0, 2
s_movk_i32 s13, 0x1c00
s_add_i32 s7, s7, s1
v_add_nc_u32_e32 v11, 0x500, v5
v_lshrrev_b32_e32 v3, 31, v1
v_ashrrev_i32_e32 v1, 2, v1
s_mul_i32 s1, s7, 10
v_add_nc_u32_e32 v13, 0x600, v5
s_sub_i32 s6, s6, s1
s_movk_i32 s12, 0xa00
v_add_nc_u32_e32 v3, v1, v3
v_lshrrev_b32_e32 v1, 5, v0
s_mul_i32 s15, s6, 20
v_and_b32_e32 v7, 31, v0
v_and_b32_e32 v15, s13, v11
v_mul_lo_u32 v8, v3, 21
v_lshlrev_b32_e32 v9, 7, v1
v_and_b32_e32 v16, s13, v13
v_lshlrev_b32_e32 v11, 4, v11
s_mul_i32 s14, s7, 0x19000
s_mul_i32 s1, s6, s12
s_mov_b32 s13, 0x1c000
s_add_i32 s14, s14, s1
v_sub_nc_u32_e32 v8, v0, v8
v_add_nc_u32_e32 v18, v16, v9
v_lshlrev_b32_e32 v6, 2, v7
v_add_nc_u32_e32 v15, v15, v9
v_and_b32_e32 v16, s13, v11
v_add_nc_u32_e32 v12, s15, v8
v_lshlrev_b32_e32 v14, 7, v8
v_lshlrev_b32_e32 v11, 4, v13
v_add_nc_u32_e32 v13, 0x700, v5
v_or_b32_e32 v15, v15, v6
v_cmp_lt_i32_e64 s1, 0, v12
v_add3_u32 v12, s14, v14, 0xffff9b80
v_mov_b32_e32 v14, 0x1c00
v_or_b32_e32 v18, v18, v6
v_and_b32_e32 v21, s13, v11
v_mov_b32_e32 v17, 0x1c000
v_lshlrev_b32_e32 v19, 1, v15
v_and_b32_e32 v11, v14, v13
v_lshlrev_b32_e32 v13, 4, v13
v_lshlrev_b32_e32 v22, 1, v18
v_add_nc_u32_e32 v18, s12, v5
v_add_nc_u32_e32 v15, 0x900, v5
v_add_nc_u32_e32 v11, v11, v9
v_and_b32_e32 v24, v17, v13
v_add_nc_u32_e32 v13, 0xb00, v5
s_clause 0x3
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[4:5], s[4:5], 0x18
v_and_b32_e32 v25, v14, v15
v_or_b32_e32 v11, v11, v6
v_and_b32_e32 v26, v14, v18
v_and_b32_e32 v14, v14, v13
v_lshlrev_b32_e32 v15, 4, v15
v_add_nc_u32_e32 v8, 0x100, v9
v_lshlrev_b32_e32 v33, 1, v11
v_add_nc_u32_e32 v11, v26, v9
v_add_nc_u32_e32 v20, 0x200, v9
v_add_nc_u32_e32 v23, 0x300, v9
v_add_nc_u32_e32 v25, v25, v9
v_add_nc_u32_e32 v9, v14, v9
v_and_b32_e32 v35, v17, v15
v_lshlrev_b32_e32 v15, 4, v18
v_or_b32_e32 v11, v11, v6
v_or_b32_e32 v14, v25, v6
v_lshlrev_b32_e32 v13, 4, v13
v_or_b32_e32 v9, v9, v6
v_and_b32_e32 v39, v17, v15
v_lshlrev_b32_e32 v40, 1, v11
v_lshlrev_b32_e32 v38, 1, v14
v_and_b32_e32 v41, v17, v13
v_lshlrev_b32_e32 v42, 1, v9
v_lshlrev_b32_e32 v45, 1, v7
v_cmp_gt_i32_e64 s0, 63, v0
v_lshlrev_b32_e32 v2, 3, v0
v_lshl_add_u32 v4, v0, 4, 0x1800
v_lshl_add_u32 v10, s7, 2, v3
v_mul_u32_u24_e32 v43, 0x150, v1
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v29, 0
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v28, 0
v_mov_b32_e32 v30, 0
v_mov_b32_e32 v31, 0
v_mov_b32_e32 v32, 0
v_mov_b32_e32 v34, 0
v_mov_b32_e32 v36, 0
v_mov_b32_e32 v37, 0
v_mov_b32_e32 v44, 0
s_mov_b32 s12, 0
s_mov_b32 s14, 0
BB58_1:
v_add_nc_u32_e32 v46, s14, v3
v_add_nc_u32_e32 v47, s14, v10
s_mul_i32 s16, s14, 0xc000
s_mov_b32 s17, 0
v_mul_lo_u32 v46, 0x6400, v46
v_cmp_lt_i32_e32 vcc_lo, 0, v47
s_and_b32 s15, s1, vcc_lo
v_add_nc_u32_e32 v46, v12, v46
BB58_2:
s_waitcnt lgkmcnt(0)
s_barrier
s_and_saveexec_b32 s18, s0
s_cbranch_execz BB58_6
s_mov_b32 s13, s12
v_mov_b32_e32 v48, s13
v_mov_b32_e32 v50, s13
v_mov_b32_e32 v47, s12
v_mov_b32_e32 v49, s12
s_and_saveexec_b32 s13, s15
s_cbranch_execz BB58_5
v_lshl_add_u32 v47, s17, 3, v46
v_ashrrev_i32_e32 v48, 31, v47
v_lshlrev_b64 v[47:48], 1, v[47:48]
v_add_co_u32 v47, vcc_lo, s8, v47
v_add_co_ci_u32_e32 v48, vcc_lo, s9, v48, vcc_lo
global_load_dwordx4 v[47:50], v[47:48], off
BB58_5:
s_or_b32 exec_lo, exec_lo, s13
s_waitcnt vmcnt(0)
ds_write_b128 v4, v[47:50]
BB58_6:
s_or_b32 exec_lo, exec_lo, s18
s_lshl_b32 s13, s17, 10
s_mov_b32 s18, 0
s_add_i32 s13, s13, s16
v_or_b32_e32 v49, s13, v6
v_add_nc_u32_e32 v47, s13, v5
s_mov_b32 s13, -1
v_add_nc_u32_e32 v65, v49, v8
v_ashrrev_i32_e32 v48, 31, v47
v_add_nc_u32_e32 v67, v49, v20
v_add_nc_u32_e32 v69, v49, v23
v_add_nc_u32_e32 v49, v65, v16
v_lshlrev_b64 v[47:48], 1, v[47:48]
v_add_nc_u32_e32 v51, v67, v21
v_add_nc_u32_e32 v53, v69, v24
v_add_nc_u32_e32 v65, v65, v35
v_ashrrev_i32_e32 v50, 31, v49
v_add_nc_u32_e32 v67, v67, v39
v_ashrrev_i32_e32 v52, 31, v51
v_add_co_u32 v47, vcc_lo, s10, v47
v_ashrrev_i32_e32 v54, 31, v53
v_add_co_ci_u32_e32 v48, vcc_lo, s11, v48, vcc_lo
v_lshlrev_b64 v[49:50], 1, v[49:50]
v_lshlrev_b64 v[51:52], 1, v[51:52]
v_add_co_u32 v63, vcc_lo, 0x8000, v47
v_lshlrev_b64 v[53:54], 1, v[53:54]
v_add_co_ci_u32_e32 v64, vcc_lo, 0, v48, vcc_lo
v_ashrrev_i32_e32 v66, 31, v65
v_add_co_u32 v49, vcc_lo, s10, v49
v_add_nc_u32_e32 v69, v69, v41
v_add_co_ci_u32_e32 v50, vcc_lo, s11, v50, vcc_lo
v_add_co_u32 v51, vcc_lo, s10, v51
v_ashrrev_i32_e32 v68, 31, v67
v_add_co_ci_u32_e32 v52, vcc_lo, s11, v52, vcc_lo
v_add_co_u32 v53, vcc_lo, s10, v53
v_lshlrev_b64 v[65:66], 1, v[65:66]
v_ashrrev_i32_e32 v70, 31, v69
v_add_co_ci_u32_e32 v54, vcc_lo, s11, v54, vcc_lo
s_clause 0x3
global_load_dwordx2 v[55:56], v[47:48], off
global_load_dwordx2 v[57:58], v[47:48], off offset:512
global_load_dwordx2 v[59:60], v[47:48], off offset:1024
global_load_dwordx2 v[61:62], v[47:48], off offset:1536
v_add_co_u32 v47, vcc_lo, 0x10000, v47
v_lshlrev_b64 v[67:68], 1, v[67:68]
v_add_co_ci_u32_e32 v48, vcc_lo, 0, v48, vcc_lo
v_add_co_u32 v65, vcc_lo, s10, v65
v_lshlrev_b64 v[69:70], 1, v[69:70]
v_add_co_ci_u32_e32 v66, vcc_lo, s11, v66, vcc_lo
v_add_co_u32 v67, vcc_lo, s10, v67
v_add_co_ci_u32_e32 v68, vcc_lo, s11, v68, vcc_lo
v_add_co_u32 v69, vcc_lo, s10, v69
v_add_co_ci_u32_e32 v70, vcc_lo, s11, v70, vcc_lo
s_clause 0x7
global_load_dwordx2 v[63:64], v[63:64], off
global_load_dwordx2 v[49:50], v[49:50], off
global_load_dwordx2 v[51:52], v[51:52], off
global_load_dwordx2 v[53:54], v[53:54], off
global_load_dwordx2 v[47:48], v[47:48], off
global_load_dwordx2 v[65:66], v[65:66], off
global_load_dwordx2 v[67:68], v[67:68], off
global_load_dwordx2 v[69:70], v[69:70], off
s_waitcnt vmcnt(10)
ds_write2st64_b64 v2, v[55:56], v[57:58] offset1:1
s_waitcnt vmcnt(8)
ds_write2st64_b64 v2, v[59:60], v[61:62] offset0:2 offset1:3
s_waitcnt vmcnt(7)
ds_write_b64 v2, v[63:64] offset:2048
s_waitcnt vmcnt(6)
ds_write_b64 v19, v[49:50] offset:512
s_waitcnt vmcnt(5)
ds_write_b64 v22, v[51:52] offset:1024
s_waitcnt vmcnt(4)
ds_write_b64 v33, v[53:54] offset:1536
s_waitcnt vmcnt(3)
ds_write_b64 v2, v[47:48] offset:4096
s_waitcnt vmcnt(2)
ds_write_b64 v38, v[65:66] offset:512
s_waitcnt vmcnt(1)
ds_write_b64 v40, v[67:68] offset:1024
s_waitcnt vmcnt(0)
ds_write_b64 v42, v[69:70] offset:1536
s_waitcnt lgkmcnt(0)
s_barrier
BB58_7:
v_lshlrev_b32_e32 v47, 1, v43
v_lshlrev_b32_e32 v48, 1, v45
s_and_b32 vcc_lo, exec_lo, s13
s_mov_b32 s13, 0
v_lshl_or_b32 v47, s18, 3, v47
v_lshl_or_b32 v48, s18, 10, v48
s_mov_b32 s18, 1
v_add_nc_u32_e32 v83, 0x1800, v47
v_add_nc_u32_e32 v71, 0x800, v48
v_add_nc_u32_e32 v111, 0x1000, v48
ds_read2_b32 v[87:88], v48 offset1:32
ds_read2_b32 v[89:90], v48 offset0:64 offset1:96
ds_read2_b32 v[91:92], v48 offset0:128 offset1:160
ds_read2_b32 v[93:94], v48 offset0:192 offset1:224
ds_read_b64 v[95:96], v47 offset:6464
ds_read2_b64 v[47:50], v83 offset1:2
ds_read2_b64 v[51:54], v83 offset0:4 offset1:6
ds_read2_b64 v[55:58], v83 offset0:8 offset1:10
ds_read2_b32 v[97:98], v71 offset1:32
ds_read2_b64 v[59:62], v83 offset0:12 offset1:14
ds_read2_b32 v[99:100], v71 offset0:64 offset1:96
ds_read2_b64 v[63:66], v83 offset0:16 offset1:18
ds_read2_b32 v[101:102], v71 offset0:128 offset1:160
ds_read2_b64 v[67:70], v83 offset0:20 offset1:22
ds_read2_b32 v[103:104], v71 offset0:192 offset1:224
ds_read2_b64 v[71:74], v83 offset0:24 offset1:26
ds_read2_b32 v[105:106], v111 offset1:32
ds_read2_b64 v[75:78], v83 offset0:28 offset1:30
ds_read2_b32 v[107:108], v111 offset0:64 offset1:96
ds_read2_b64 v[79:82], v83 offset0:32 offset1:34
ds_read2_b32 v[109:110], v111 offset0:128 offset1:160
ds_read2_b64 v[83:86], v83 offset0:36 offset1:38
ds_read2_b32 v[111:112], v111 offset0:192 offset1:224
s_waitcnt lgkmcnt(17)
v_pk_fma_f16 v44, v47, v87, v44 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v47, v88, v29 op_sel:[0,1,0] op_sel_hi:[0,0,1]
s_waitcnt lgkmcnt(16)
v_pk_fma_f16 v27, v51, v87, v27 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v25, v51, v88, v25 op_sel:[0,1,0] op_sel_hi:[0,0,1]
s_waitcnt lgkmcnt(15)
v_pk_fma_f16 v37, v55, v87, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v55, v88, v18 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(13)
v_pk_fma_f16 v36, v59, v87, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v59, v88, v17 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(11)
v_pk_fma_f16 v34, v63, v87, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v63, v88, v15 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(9)
v_pk_fma_f16 v32, v67, v87, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v67, v88, v14 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(7)
v_pk_fma_f16 v31, v71, v87, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v71, v88, v13 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v30, v75, v87, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v75, v88, v11 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v28, v79, v87, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v79, v88, v9 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v26, v83, v87, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v83, v88, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v44, v47, v89, v44 op_sel:[1,0,0]
v_pk_fma_f16 v29, v47, v90, v29 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v27, v51, v89, v27 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v25, v51, v90, v25 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v37, v55, v89, v37 op_sel:[1,0,0]
v_pk_fma_f16 v18, v55, v90, v18 op_sel:[1,0,0]
v_pk_fma_f16 v36, v59, v89, v36 op_sel:[1,0,0]
v_pk_fma_f16 v17, v59, v90, v17 op_sel:[1,0,0]
v_pk_fma_f16 v34, v63, v89, v34 op_sel:[1,0,0]
v_pk_fma_f16 v15, v63, v90, v15 op_sel:[1,0,0]
v_pk_fma_f16 v32, v67, v89, v32 op_sel:[1,0,0]
v_pk_fma_f16 v14, v67, v90, v14 op_sel:[1,0,0]
v_pk_fma_f16 v31, v71, v89, v31 op_sel:[1,0,0]
v_pk_fma_f16 v13, v71, v90, v13 op_sel:[1,0,0]
v_pk_fma_f16 v30, v75, v89, v30 op_sel:[1,0,0]
v_pk_fma_f16 v11, v75, v90, v11 op_sel:[1,0,0]
v_pk_fma_f16 v28, v79, v89, v28 op_sel:[1,0,0]
v_pk_fma_f16 v9, v79, v90, v9 op_sel:[1,0,0]
v_pk_fma_f16 v26, v83, v89, v26 op_sel:[1,0,0]
v_pk_fma_f16 v7, v83, v90, v7 op_sel:[1,0,0]
v_pk_fma_f16 v44, v48, v91, v44 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v48, v92, v29 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v27, v52, v91, v27 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v25, v52, v92, v25 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v37, v56, v91, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v56, v92, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v60, v91, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v60, v92, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v64, v91, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v64, v92, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v68, v91, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v68, v92, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v72, v91, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v72, v92, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v76, v91, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v76, v92, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v80, v91, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v80, v92, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v84, v91, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v84, v92, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v44, v48, v93, v44 op_sel:[1,0,0]
v_pk_fma_f16 v29, v48, v94, v29 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v27, v52, v93, v27 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v25, v52, v94, v25 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v37, v56, v93, v37 op_sel:[1,0,0]
v_pk_fma_f16 v18, v56, v94, v18 op_sel:[1,0,0]
v_pk_fma_f16 v36, v60, v93, v36 op_sel:[1,0,0]
v_pk_fma_f16 v17, v60, v94, v17 op_sel:[1,0,0]
v_pk_fma_f16 v34, v64, v93, v34 op_sel:[1,0,0]
v_pk_fma_f16 v15, v64, v94, v15 op_sel:[1,0,0]
v_pk_fma_f16 v32, v68, v93, v32 op_sel:[1,0,0]
v_pk_fma_f16 v14, v68, v94, v14 op_sel:[1,0,0]
v_pk_fma_f16 v31, v72, v93, v31 op_sel:[1,0,0]
v_pk_fma_f16 v13, v72, v94, v13 op_sel:[1,0,0]
v_pk_fma_f16 v30, v76, v93, v30 op_sel:[1,0,0]
v_pk_fma_f16 v11, v76, v94, v11 op_sel:[1,0,0]
v_pk_fma_f16 v28, v80, v93, v28 op_sel:[1,0,0]
v_pk_fma_f16 v9, v80, v94, v9 op_sel:[1,0,0]
v_pk_fma_f16 v26, v84, v93, v26 op_sel:[1,0,0]
v_pk_fma_f16 v7, v84, v94, v7 op_sel:[1,0,0]
v_pk_fma_f16 v44, v49, v97, v44 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v49, v98, v29 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v27, v53, v97, v27 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v25, v53, v98, v25 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v37, v57, v97, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v57, v98, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v61, v97, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v61, v98, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v65, v97, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v65, v98, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v69, v97, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v69, v98, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v73, v97, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v73, v98, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v77, v97, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v77, v98, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v81, v97, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v81, v98, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v85, v97, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v85, v98, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v44, v49, v99, v44 op_sel:[1,0,0]
v_pk_fma_f16 v29, v49, v100, v29 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v27, v53, v99, v27 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v25, v53, v100, v25 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v37, v57, v99, v37 op_sel:[1,0,0]
v_pk_fma_f16 v18, v57, v100, v18 op_sel:[1,0,0]
v_pk_fma_f16 v36, v61, v99, v36 op_sel:[1,0,0]
v_pk_fma_f16 v17, v61, v100, v17 op_sel:[1,0,0]
v_pk_fma_f16 v34, v65, v99, v34 op_sel:[1,0,0]
v_pk_fma_f16 v15, v65, v100, v15 op_sel:[1,0,0]
v_pk_fma_f16 v32, v69, v99, v32 op_sel:[1,0,0]
v_pk_fma_f16 v14, v69, v100, v14 op_sel:[1,0,0]
v_pk_fma_f16 v31, v73, v99, v31 op_sel:[1,0,0]
v_pk_fma_f16 v13, v73, v100, v13 op_sel:[1,0,0]
v_pk_fma_f16 v30, v77, v99, v30 op_sel:[1,0,0]
v_pk_fma_f16 v11, v77, v100, v11 op_sel:[1,0,0]
v_pk_fma_f16 v28, v81, v99, v28 op_sel:[1,0,0]
v_pk_fma_f16 v9, v81, v100, v9 op_sel:[1,0,0]
v_pk_fma_f16 v26, v85, v99, v26 op_sel:[1,0,0]
v_pk_fma_f16 v7, v85, v100, v7 op_sel:[1,0,0]
v_pk_fma_f16 v44, v50, v101, v44 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v50, v102, v29 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v27, v54, v101, v27 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v25, v54, v102, v25 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v37, v58, v101, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v58, v102, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v62, v101, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v62, v102, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v66, v101, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v66, v102, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v70, v101, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v70, v102, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v74, v101, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v74, v102, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v78, v101, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v78, v102, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v82, v101, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v82, v102, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v86, v101, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v86, v102, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v44, v50, v103, v44 op_sel:[1,0,0]
v_pk_fma_f16 v29, v50, v104, v29 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v27, v54, v103, v27 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v25, v54, v104, v25 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v37, v58, v103, v37 op_sel:[1,0,0]
v_pk_fma_f16 v18, v58, v104, v18 op_sel:[1,0,0]
v_pk_fma_f16 v36, v62, v103, v36 op_sel:[1,0,0]
v_pk_fma_f16 v17, v62, v104, v17 op_sel:[1,0,0]
v_pk_fma_f16 v34, v66, v103, v34 op_sel:[1,0,0]
v_pk_fma_f16 v15, v66, v104, v15 op_sel:[1,0,0]
v_pk_fma_f16 v32, v70, v103, v32 op_sel:[1,0,0]
v_pk_fma_f16 v14, v70, v104, v14 op_sel:[1,0,0]
v_pk_fma_f16 v31, v74, v103, v31 op_sel:[1,0,0]
v_pk_fma_f16 v13, v74, v104, v13 op_sel:[1,0,0]
v_pk_fma_f16 v30, v78, v103, v30 op_sel:[1,0,0]
v_pk_fma_f16 v11, v78, v104, v11 op_sel:[1,0,0]
v_pk_fma_f16 v28, v82, v103, v28 op_sel:[1,0,0]
v_pk_fma_f16 v9, v82, v104, v9 op_sel:[1,0,0]
v_pk_fma_f16 v26, v86, v103, v26 op_sel:[1,0,0]
v_pk_fma_f16 v7, v86, v104, v7 op_sel:[1,0,0]
v_pk_fma_f16 v44, v51, v105, v44 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v51, v106, v29 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v27, v55, v105, v27 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v25, v55, v106, v25 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v37, v59, v105, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v59, v106, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v63, v105, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v63, v106, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v67, v105, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v67, v106, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v71, v105, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v71, v106, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v75, v105, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v75, v106, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v79, v105, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v79, v106, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v83, v105, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v83, v106, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v95, v105, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v95, v106, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v44, v51, v107, v44 op_sel:[1,0,0]
v_pk_fma_f16 v29, v51, v108, v29 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v27, v55, v107, v27 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v25, v55, v108, v25 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v37, v59, v107, v37 op_sel:[1,0,0]
v_pk_fma_f16 v18, v59, v108, v18 op_sel:[1,0,0]
v_pk_fma_f16 v36, v63, v107, v36 op_sel:[1,0,0]
v_pk_fma_f16 v17, v63, v108, v17 op_sel:[1,0,0]
v_pk_fma_f16 v34, v67, v107, v34 op_sel:[1,0,0]
v_pk_fma_f16 v15, v67, v108, v15 op_sel:[1,0,0]
v_pk_fma_f16 v32, v71, v107, v32 op_sel:[1,0,0]
v_pk_fma_f16 v14, v71, v108, v14 op_sel:[1,0,0]
v_pk_fma_f16 v31, v75, v107, v31 op_sel:[1,0,0]
v_pk_fma_f16 v13, v75, v108, v13 op_sel:[1,0,0]
v_pk_fma_f16 v30, v79, v107, v30 op_sel:[1,0,0]
v_pk_fma_f16 v11, v79, v108, v11 op_sel:[1,0,0]
v_pk_fma_f16 v28, v83, v107, v28 op_sel:[1,0,0]
v_pk_fma_f16 v9, v83, v108, v9 op_sel:[1,0,0]
v_pk_fma_f16 v26, v95, v107, v26 op_sel:[1,0,0]
v_pk_fma_f16 v7, v95, v108, v7 op_sel:[1,0,0]
v_pk_fma_f16 v44, v52, v109, v44 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v52, v110, v29 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v27, v56, v109, v27 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v25, v56, v110, v25 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v37, v60, v109, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v60, v110, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v64, v109, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v64, v110, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v68, v109, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v68, v110, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v72, v109, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v72, v110, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v76, v109, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v76, v110, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v80, v109, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v80, v110, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v84, v109, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v84, v110, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v96, v109, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v96, v110, v7 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v44, v52, v111, v44 op_sel:[1,0,0]
v_pk_fma_f16 v29, v52, v112, v29 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v27, v56, v111, v27 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v25, v56, v112, v25 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v37, v60, v111, v37 op_sel:[1,0,0]
v_pk_fma_f16 v18, v60, v112, v18 op_sel:[1,0,0]
v_pk_fma_f16 v36, v64, v111, v36 op_sel:[1,0,0]
v_pk_fma_f16 v17, v64, v112, v17 op_sel:[1,0,0]
v_pk_fma_f16 v34, v68, v111, v34 op_sel:[1,0,0]
v_pk_fma_f16 v15, v68, v112, v15 op_sel:[1,0,0]
v_pk_fma_f16 v32, v72, v111, v32 op_sel:[1,0,0]
v_pk_fma_f16 v14, v72, v112, v14 op_sel:[1,0,0]
v_pk_fma_f16 v31, v76, v111, v31 op_sel:[1,0,0]
v_pk_fma_f16 v13, v76, v112, v13 op_sel:[1,0,0]
v_pk_fma_f16 v30, v80, v111, v30 op_sel:[1,0,0]
v_pk_fma_f16 v11, v80, v112, v11 op_sel:[1,0,0]
v_pk_fma_f16 v28, v84, v111, v28 op_sel:[1,0,0]
v_pk_fma_f16 v9, v84, v112, v9 op_sel:[1,0,0]
v_pk_fma_f16 v26, v96, v111, v26 op_sel:[1,0,0]
v_pk_fma_f16 v7, v96, v112, v7 op_sel:[1,0,0]
s_cbranch_vccnz BB58_7
s_add_i32 s17, s17, 1
s_cmp_eq_u32 s17, 16
s_cbranch_scc0 BB58_2
s_add_i32 s14, s14, 1
s_cmp_eq_u32 s14, 3
s_cbranch_scc0 BB58_1
v_lshlrev_b32_e32 v0, 1, v0
v_mul_u32_u24_e32 v1, 0x3200, v1
s_mulk_i32 s6, 0x500
s_mulk_i32 s7, 0x6400
v_and_b32_e32 v0, 62, v0
v_add3_u32 v1, s6, s7, v1
v_lshlrev_b32_e32 v2, 1, v0
v_or_b32_e32 v0, v1, v0
s_clause 0x2
global_load_ushort v6, v2, s[4:5] offset:130
global_load_ushort v8, v2, s[4:5] offset:128
global_load_dword v10, v2, s[4:5]
v_add_nc_u32_e32 v2, 0x400, v0
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v4, 0x440, v0
v_add_nc_u32_e32 v19, 0x480, v0
v_add_nc_u32_e32 v21, 0x4c0, v0
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v20, 31, v19
v_ashrrev_i32_e32 v22, 31, v21
v_lshlrev_b64 v[2:3], 1, v[2:3]
v_add_co_u32 v0, vcc_lo, s2, v0
v_lshlrev_b64 v[4:5], 1, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_lshlrev_b64 v[19:20], 1, v[19:20]
v_add_co_u32 v2, vcc_lo, s2, v2
v_lshlrev_b64 v[21:22], 1, v[21:22]
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v19, vcc_lo, s2, v19
v_add_co_ci_u32_e32 v20, vcc_lo, s3, v20, vcc_lo
v_add_co_u32 v21, vcc_lo, s2, v21
v_add_co_ci_u32_e32 v22, vcc_lo, s3, v22, vcc_lo
s_waitcnt vmcnt(2)
v_add_f16_e32 v23, v6, v29
s_waitcnt vmcnt(1)
v_add_f16_sdwa v12, v8, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_add_f16_sdwa v29, v8, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v8, 0xffff, v8
s_waitcnt vmcnt(0)
v_pk_add_f16 v16, v10, v44
v_pk_add_f16 v35, v10, v36
v_add_f16_sdwa v24, v10, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_add_f16_e32 v25, v6, v25
v_lshl_or_b32 v6, v6, 16, v8
v_add_f16_sdwa v27, v10, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
v_pk_add_f16 v28, v10, v28
v_pk_add_f16 v33, v10, v37
v_max_f16_e32 v12, 0, v12
v_pk_max_f16 v16, v16, 0
v_pk_max_f16 v8, v35, 0
v_max_f16_e32 v23, 0, v23
v_max_f16_e32 v24, 0, v24
v_pk_add_f16 v32, v10, v32
v_pk_add_f16 v31, v10, v31
v_pk_add_f16 v30, v10, v30
v_pk_add_f16 v34, v10, v34
v_pk_add_f16 v10, v10, v26
v_max_f16_e32 v26, 0, v29
v_pk_max_f16 v29, v33, 0
v_max_f16_e32 v27, 0, v27
v_max_f16_e32 v25, 0, v25
global_store_short v[0:1], v12, off offset:128
global_store_dword v[0:1], v16, off
global_store_short v[0:1], v23, off offset:130
global_store_short v[0:1], v24, off offset:256
global_store_short v[0:1], v26, off offset:384
global_store_short v[0:1], v27, off offset:258
global_store_short v[0:1], v25, off offset:386
global_store_dword v[0:1], v29, off offset:512
v_pk_max_f16 v28, v28, 0
v_pk_add_f16 v12, v6, v18
global_store_dword v[0:1], v8, off offset:768
v_pk_add_f16 v8, v6, v17
v_pk_add_f16 v15, v6, v15
v_pk_add_f16 v14, v6, v14
v_pk_max_f16 v10, v10, 0
v_pk_add_f16 v13, v6, v13
v_pk_add_f16 v11, v6, v11
global_store_dword v[2:3], v28, off
v_pk_add_f16 v2, v6, v9
v_pk_add_f16 v3, v6, v7
v_pk_max_f16 v33, v34, 0
v_pk_max_f16 v32, v32, 0
v_pk_max_f16 v31, v31, 0
v_pk_max_f16 v30, v30, 0
v_pk_max_f16 v6, v12, 0
v_pk_max_f16 v7, v8, 0
v_pk_max_f16 v8, v15, 0
v_pk_max_f16 v9, v14, 0
global_store_dword v[19:20], v10, off
v_pk_max_f16 v10, v13, 0
global_store_dword v[0:1], v33, off offset:1024
global_store_dword v[0:1], v32, off offset:1280
global_store_dword v[0:1], v31, off offset:1536
global_store_dword v[0:1], v30, off offset:1792
v_pk_max_f16 v11, v11, 0
v_pk_max_f16 v2, v2, 0
v_pk_max_f16 v3, v3, 0
global_store_dword v[0:1], v6, off offset:640
global_store_dword v[0:1], v7, off offset:896
global_store_dword v[0:1], v8, off offset:1152
global_store_dword v[0:1], v9, off offset:1408
global_store_dword v[0:1], v10, off offset:1664
global_store_dword v[0:1], v11, off offset:1920
global_store_dword v[4:5], v2, off
global_store_dword v[21:22], v3, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_nn_relu_4_kernel0
.amdhsa_group_segment_fixed_size 7152
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 113
.amdhsa_next_free_sgpr 19
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end58:
.size tvmgen_default_fused_nn_conv2d_add_nn_relu_4_kernel0, .Lfunc_end58-tvmgen_default_fused_nn_conv2d_add_nn_relu_4_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_nn_relu_5_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_nn_relu_5_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_nn_relu_5_kernel0:
s_mul_hi_i32 s0, s6, 0x66666667
v_lshrrev_b32_e32 v4, 4, v0
v_add_nc_u32_e32 v1, 0x100, v0
s_lshr_b32 s1, s0, 31
s_ashr_i32 s2, s0, 2
s_mov_b32 s15, 0xcccccccd
s_add_i32 s2, s2, s1
v_mul_hi_u32 v6, v1, s15
v_add_nc_u32_e32 v7, 16, v4
s_mul_i32 s3, s2, 10
s_movk_i32 s7, 0x200
s_sub_i32 s3, s6, s3
v_add_nc_u32_e32 v2, 0x180, v0
v_add_nc_u32_e32 v3, s7, v0
v_mul_hi_u32 v7, v7, s15
s_ashr_i32 s3, s3, 1
s_movk_i32 s13, 0x2800
v_and_b32_e32 v5, 15, v0
s_mul_i32 s12, s3, s13
s_mul_i32 s14, s2, 0x19000
v_lshrrev_b32_e32 v6, 8, v6
s_add_i32 s14, s12, s14
v_mul_hi_u32 v2, v2, s15
v_mul_hi_u32 v3, v3, s15
v_or_b32_e32 v11, s14, v5
s_mov_b32 s14, 0xc800
s_clause 0x3
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[0:1], s[4:5], 0x10
s_load_dwordx2 s[4:5], s[4:5], 0x18
v_lshrrev_b32_e32 v7, 4, v7
v_lshlrev_b32_e32 v10, 9, v4
v_mul_i32_i24_e32 v6, s14, v6
v_lshrrev_b32_e32 v2, 8, v2
v_lshrrev_b32_e32 v3, 8, v3
v_mul_u32_u24_e32 v7, s13, v7
v_lshlrev_b32_e32 v8, 3, v0
v_add3_u32 v6, v6, v11, v10
v_mad_i32_i24 v9, v2, s14, v11
v_mad_i32_i24 v12, v3, s14, v11
v_lshlrev_b32_e32 v3, 4, v0
v_and_b32_e32 v2, 56, v8
v_mul_u32_u24_e32 v8, 0x50, v4
v_sub_nc_u32_e32 v13, v6, v7
v_lshlrev_b32_e32 v5, 3, v5
s_movk_i32 s12, 0x800
s_movk_i32 s13, 0x2000
v_lshl_add_u32 v6, v8, 1, s12
v_add3_u32 v7, v12, v10, 0x1800
v_add3_u32 v8, v9, v10, s12
v_add_nc_u32_e32 v9, s13, v13
v_add_nc_u32_e32 v10, v11, v10
v_lshl_or_b32 v1, v0, 1, s12
v_and_b32_e32 v4, 0x3f80, v3
v_mov_b32_e32 v13, 0
v_add_nc_u32_e32 v11, 0x400, v5
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v21, 0
s_lshl_b32 s6, s6, 6
s_mov_b32 s14, 0
s_and_b32 s6, s6, 64
BB59_1:
v_add_nc_u32_e32 v22, s14, v10
v_add_nc_u32_e32 v24, s14, v9
v_add_nc_u32_e32 v26, s14, v8
v_add_nc_u32_e32 v28, s14, v7
v_or3_b32 v30, v4, s6, v2
v_ashrrev_i32_e32 v23, 31, v22
v_ashrrev_i32_e32 v25, 31, v24
v_ashrrev_i32_e32 v27, 31, v26
v_ashrrev_i32_e32 v29, 31, v28
v_ashrrev_i32_e32 v31, 31, v30
v_lshlrev_b64 v[22:23], 1, v[22:23]
v_lshlrev_b64 v[24:25], 1, v[24:25]
v_lshlrev_b64 v[26:27], 1, v[26:27]
v_lshlrev_b64 v[28:29], 1, v[28:29]
v_lshlrev_b64 v[30:31], 1, v[30:31]
v_add_nc_u32_e32 v4, s12, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v22, vcc_lo, s8, v22
s_add_i32 s14, s14, 16
v_add_co_ci_u32_e32 v23, vcc_lo, s9, v23, vcc_lo
v_add_co_u32 v32, vcc_lo, s8, v24
s_cmp_eq_u32 s14, s7
v_add_co_ci_u32_e32 v33, vcc_lo, s9, v25, vcc_lo
v_add_co_u32 v26, vcc_lo, s8, v26
v_add_co_ci_u32_e32 v27, vcc_lo, s9, v27, vcc_lo
v_add_co_u32 v28, vcc_lo, s8, v28
v_add_co_ci_u32_e32 v29, vcc_lo, s9, v29, vcc_lo
v_add_co_u32 v24, vcc_lo, s10, v30
v_add_co_ci_u32_e32 v25, vcc_lo, s11, v31, vcc_lo
v_add_co_u32 v30, vcc_lo, s13, v22
v_add_co_ci_u32_e32 v31, vcc_lo, 0, v23, vcc_lo
global_load_ushort v34, v[22:23], off
global_load_dwordx4 v[22:25], v[24:25], off
s_clause 0x3
global_load_ushort v30, v[30:31], off
global_load_ushort v31, v[32:33], off
global_load_ushort v26, v[26:27], off
global_load_ushort v27, v[28:29], off
s_waitcnt vmcnt(0)
s_barrier
ds_write_b16 v1, v34
ds_write_b128 v3, v[22:25]
ds_write_b16 v1, v30 offset:256
ds_write_b16 v1, v31 offset:512
ds_write_b16 v1, v26 offset:768
ds_write_b16 v1, v27 offset:1024
s_waitcnt lgkmcnt(0)
s_barrier
ds_read2_b32 v[66:67], v5 offset1:1
ds_read_b128 v[22:25], v6
ds_read_b128 v[26:29], v6 offset:32
ds_read_b128 v[30:33], v6 offset:64
ds_read_b128 v[34:37], v6 offset:96
ds_read_b128 v[38:41], v6 offset:128
ds_read2_b64 v[42:45], v5 offset0:16 offset1:32
ds_read_b128 v[46:49], v6 offset:16
ds_read2_b64 v[50:53], v6 offset0:6 offset1:7
ds_read2_b64 v[54:57], v6 offset0:10 offset1:11
ds_read2_b64 v[58:61], v6 offset0:14 offset1:15
ds_read2_b64 v[62:65], v6 offset0:18 offset1:19
ds_read_b64 v[68:69], v5 offset:896
ds_read2_b32 v[70:71], v5 offset0:128 offset1:129
ds_read_b64 v[72:73], v5 offset:384
s_waitcnt lgkmcnt(13)
v_pk_fma_f16 v20, v22, v66, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v22, v67, v21 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(12)
v_pk_fma_f16 v19, v26, v66, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v26, v67, v18 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(11)
v_pk_fma_f16 v17, v30, v66, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v30, v67, v16 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(10)
v_pk_fma_f16 v74, v34, v66, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v75, v34, v67, v14 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(9)
v_pk_fma_f16 v66, v38, v66, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v67, v38, v67, v12 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(8)
v_pk_fma_f16 v19, v26, v42, v19 op_sel:[1,0,0]
v_pk_fma_f16 v18, v26, v43, v18 op_sel:[1,0,0]
v_pk_fma_f16 v17, v30, v42, v17 op_sel:[1,0,0]
v_pk_fma_f16 v16, v30, v43, v16 op_sel:[1,0,0]
v_pk_fma_f16 v26, v34, v43, v75 op_sel:[1,0,0]
v_pk_fma_f16 v30, v38, v42, v66 op_sel:[1,0,0]
ds_read2_b64 v[12:15], v5 offset0:80 offset1:96
v_pk_fma_f16 v20, v22, v42, v20 op_sel:[1,0,0]
v_pk_fma_f16 v21, v22, v43, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v34, v42, v74 op_sel:[1,0,0]
v_pk_fma_f16 v34, v38, v43, v67 op_sel:[1,0,0]
v_pk_fma_f16 v26, v35, v45, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v23, v44, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v39, v44, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v35, v44, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v39, v45, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v42, v23, v45, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v31, v44, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v27, v44, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v27, v45, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v31, v45, v16 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v22, v35, v72, v22 op_sel:[1,0,0]
v_pk_fma_f16 v26, v35, v73, v26 op_sel:[1,0,0]
v_pk_fma_f16 v38, v23, v72, v38 op_sel:[1,0,0]
v_pk_fma_f16 v23, v23, v73, v42 op_sel:[1,0,0]
v_pk_fma_f16 v30, v39, v72, v30 op_sel:[1,0,0]
v_pk_fma_f16 v34, v39, v73, v34 op_sel:[1,0,0]
v_pk_fma_f16 v43, v31, v72, v17 op_sel:[1,0,0]
v_pk_fma_f16 v31, v31, v73, v16 op_sel:[1,0,0]
v_pk_fma_f16 v42, v27, v72, v19 op_sel:[1,0,0]
v_pk_fma_f16 v27, v27, v73, v18 op_sel:[1,0,0]
v_pk_fma_f16 v35, v24, v70, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v24, v71, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v32, v71, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v36, v70, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v28, v71, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v36, v71, v26 op_sel_hi:[0,1,1]
ds_read2_b32 v[20:21], v11 offset1:1
v_pk_fma_f16 v38, v28, v70, v42 op_sel_hi:[0,1,1]
v_pk_fma_f16 v39, v32, v70, v43 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v40, v70, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v40, v71, v34 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v31, v32, v13, v31 op_sel:[1,0,0]
ds_read2_b64 v[16:19], v5 offset0:144 offset1:160
v_pk_fma_f16 v35, v24, v12, v35 op_sel:[1,0,0]
v_pk_fma_f16 v23, v24, v13, v23 op_sel:[1,0,0]
v_pk_fma_f16 v24, v28, v12, v38 op_sel:[1,0,0]
v_pk_fma_f16 v27, v28, v13, v27 op_sel:[1,0,0]
v_pk_fma_f16 v28, v32, v12, v39 op_sel:[1,0,0]
v_pk_fma_f16 v26, v36, v13, v26 op_sel:[1,0,0]
v_pk_fma_f16 v22, v36, v12, v22 op_sel:[1,0,0]
v_pk_fma_f16 v12, v40, v12, v30 op_sel:[1,0,0]
v_pk_fma_f16 v13, v40, v13, v34 op_sel:[1,0,0]
v_pk_fma_f16 v30, v25, v14, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v25, v15, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v29, v14, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v33, v14, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v33, v15, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v29, v15, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v37, v14, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v37, v15, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v39, v41, v14, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v40, v41, v15, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v29, v68, v34 op_sel:[1,0,0]
v_pk_fma_f16 v29, v29, v69, v35 op_sel:[1,0,0]
v_pk_fma_f16 v30, v25, v68, v30 op_sel:[1,0,0]
v_pk_fma_f16 v32, v25, v69, v32 op_sel:[1,0,0]
v_pk_fma_f16 v28, v33, v68, v28 op_sel:[1,0,0]
v_pk_fma_f16 v31, v33, v69, v31 op_sel:[1,0,0]
v_pk_fma_f16 v33, v37, v68, v36 op_sel:[1,0,0]
v_pk_fma_f16 v35, v37, v69, v38 op_sel:[1,0,0]
ds_read2_b64 v[12:15], v5 offset0:208 offset1:224
ds_read_b64 v[22:23], v5 offset:1408
v_pk_fma_f16 v36, v41, v68, v39 op_sel:[1,0,0]
v_pk_fma_f16 v37, v41, v69, v40 op_sel:[1,0,0]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v30, v46, v20, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v46, v21, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v50, v20, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v50, v21, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v54, v20, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v58, v20, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v54, v21, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v58, v21, v35 op_sel_hi:[0,1,1]
ds_read_b64 v[24:25], v5 offset:1920
ds_read2_b32 v[26:27], v11 offset0:128 offset1:129
v_pk_fma_f16 v20, v62, v20, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v62, v21, v37 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v29, v50, v17, v29 op_sel:[1,0,0]
v_pk_fma_f16 v28, v54, v16, v28 op_sel:[1,0,0]
v_pk_fma_f16 v31, v54, v17, v31 op_sel:[1,0,0]
v_pk_fma_f16 v30, v46, v16, v30 op_sel:[1,0,0]
v_pk_fma_f16 v32, v46, v17, v32 op_sel:[1,0,0]
v_pk_fma_f16 v35, v58, v17, v35 op_sel:[1,0,0]
v_pk_fma_f16 v17, v62, v17, v21 op_sel:[1,0,0]
v_pk_fma_f16 v34, v50, v16, v34 op_sel:[1,0,0]
v_pk_fma_f16 v33, v58, v16, v33 op_sel:[1,0,0]
v_pk_fma_f16 v16, v62, v16, v20 op_sel:[1,0,0]
v_pk_fma_f16 v28, v55, v18, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v63, v19, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v47, v18, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v47, v19, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v63, v18, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v59, v18, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v51, v18, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v51, v19, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v55, v19, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v59, v19, v35 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v18, v47, v22, v20 op_sel:[1,0,0]
v_pk_fma_f16 v19, v47, v23, v21 op_sel:[1,0,0]
v_pk_fma_f16 v20, v51, v22, v30 op_sel:[1,0,0]
v_pk_fma_f16 v21, v51, v23, v29 op_sel:[1,0,0]
v_pk_fma_f16 v16, v63, v22, v16 op_sel:[1,0,0]
v_pk_fma_f16 v17, v63, v23, v17 op_sel:[1,0,0]
v_pk_fma_f16 v29, v55, v23, v31 op_sel:[1,0,0]
v_pk_fma_f16 v31, v59, v23, v33 op_sel:[1,0,0]
v_pk_fma_f16 v28, v55, v22, v28 op_sel:[1,0,0]
v_pk_fma_f16 v30, v59, v22, v32 op_sel:[1,0,0]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v18, v48, v26, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v56, v27, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v48, v27, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v56, v26, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v52, v26, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v52, v27, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v60, v26, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v64, v26, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v60, v27, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v64, v27, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v56, v12, v22 op_sel:[1,0,0]
v_pk_fma_f16 v23, v56, v13, v23 op_sel:[1,0,0]
v_pk_fma_f16 v26, v60, v12, v28 op_sel:[1,0,0]
v_pk_fma_f16 v27, v60, v13, v29 op_sel:[1,0,0]
v_pk_fma_f16 v21, v52, v13, v21 op_sel:[1,0,0]
v_pk_fma_f16 v19, v48, v13, v19 op_sel:[1,0,0]
v_pk_fma_f16 v13, v64, v13, v17 op_sel:[1,0,0]
v_pk_fma_f16 v18, v48, v12, v18 op_sel:[1,0,0]
v_pk_fma_f16 v20, v52, v12, v20 op_sel:[1,0,0]
v_pk_fma_f16 v12, v64, v12, v16 op_sel:[1,0,0]
v_pk_fma_f16 v17, v49, v15, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v53, v15, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v49, v14, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v53, v14, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v57, v14, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v57, v15, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v61, v14, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v61, v15, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v65, v14, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v65, v15, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v49, v24, v16 op_sel:[1,0,0]
v_pk_fma_f16 v21, v49, v25, v17 op_sel:[1,0,0]
v_pk_fma_f16 v19, v53, v24, v18 op_sel:[1,0,0]
v_pk_fma_f16 v13, v65, v24, v12 op_sel:[1,0,0]
v_pk_fma_f16 v18, v53, v25, v28 op_sel:[1,0,0]
v_pk_fma_f16 v17, v57, v24, v22 op_sel:[1,0,0]
v_pk_fma_f16 v16, v57, v25, v23 op_sel:[1,0,0]
v_pk_fma_f16 v15, v61, v24, v26 op_sel:[1,0,0]
v_pk_fma_f16 v14, v61, v25, v27 op_sel:[1,0,0]
v_pk_fma_f16 v12, v65, v25, v29 op_sel:[1,0,0]
s_cbranch_scc0 BB59_1
v_lshlrev_b32_e32 v1, 2, v0
v_lshrrev_b32_e32 v4, 6, v0
s_mulk_i32 s2, 0x6400
v_bfe_u32 v0, v0, 4, 2
s_mulk_i32 s3, 0xa00
v_and_b32_e32 v1, 60, v1
v_mad_u32_u24 v4, 0x3200, v4, s2
v_mul_u32_u24_e32 v0, 0x280, v0
v_or_b32_e32 v2, s6, v1
v_or3_b32 v1, v4, s6, v1
v_lshlrev_b32_e32 v2, 1, v2
v_add3_u32 v0, v1, s3, v0
s_clause 0x1
global_load_dword v3, v2, s[4:5]
global_load_dword v2, v2, s[4:5] offset:4
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(1)
v_pk_add_f16 v4, v3, v20
s_waitcnt vmcnt(0)
v_pk_add_f16 v5, v2, v21
v_pk_add_f16 v6, v3, v19
v_pk_add_f16 v7, v2, v18
v_pk_add_f16 v8, v3, v17
v_pk_add_f16 v10, v3, v15
v_pk_add_f16 v9, v2, v16
v_pk_add_f16 v11, v2, v14
v_pk_add_f16 v3, v3, v13
v_pk_add_f16 v2, v2, v12
v_pk_max_f16 v4, v4, 0
v_pk_max_f16 v5, v5, 0
v_pk_max_f16 v6, v6, 0
v_pk_max_f16 v7, v7, 0
v_pk_max_f16 v8, v8, 0
v_pk_max_f16 v9, v9, 0
v_pk_max_f16 v10, v10, 0
v_pk_max_f16 v11, v11, 0
v_pk_max_f16 v3, v3, 0
v_pk_max_f16 v2, v2, 0
global_store_dword v[0:1], v4, off
global_store_dword v[0:1], v5, off offset:4
global_store_dword v[0:1], v6, off offset:256
global_store_dword v[0:1], v7, off offset:260
global_store_dword v[0:1], v8, off offset:512
global_store_dword v[0:1], v9, off offset:516
global_store_dword v[0:1], v10, off offset:768
global_store_dword v[0:1], v11, off offset:772
global_store_dword v[0:1], v3, off offset:1024
global_store_dword v[0:1], v2, off offset:1028
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_nn_relu_5_kernel0
.amdhsa_group_segment_fixed_size 3328
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 76
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end59:
.size tvmgen_default_fused_nn_conv2d_add_nn_relu_5_kernel0, .Lfunc_end59-tvmgen_default_fused_nn_conv2d_add_nn_relu_5_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_nn_relu_6_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_nn_relu_6_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_nn_relu_6_kernel0:
v_lshrrev_b32_e32 v1, 4, v0
s_mov_b32 s9, 0xcccccccd
v_add_nc_u32_e32 v4, 0x100, v0
s_mul_hi_i32 s15, s6, 0x66666667
v_add_nc_u32_e32 v5, 0x180, v0
v_add_nc_u32_e32 v2, 16, v1
v_add_nc_u32_e32 v6, 0x200, v0
v_mul_hi_u32 v4, v4, s9
s_clause 0x3
s_load_dwordx2 s[10:11], s[4:5], 0x0
s_load_dwordx2 s[12:13], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[0:1], s[4:5], 0x18
s_lshr_b32 s4, s15, 31
v_mul_hi_u32 v3, v2, s9
s_ashr_i32 s5, s15, 1
v_mul_hi_u32 v5, v5, s9
s_add_i32 s4, s5, s4
v_mul_hi_u32 v6, v6, s9
s_mul_i32 s5, s4, 5
v_lshrrev_b32_e32 v4, 8, v4
s_sub_i32 s5, s6, s5
v_lshrrev_b32_e32 v3, 4, v3
s_mul_i32 s15, s4, 0x19000
s_mul_i32 s6, s5, 0x2800
s_mov_b32 s14, 0xc800
s_add_i32 s15, s15, s6
v_mul_u32_u24_e32 v3, 20, v3
v_lshrrev_b32_e32 v41, 5, v0
v_lshrrev_b32_e32 v5, 8, v5
v_mul_i32_i24_e32 v4, s14, v4
v_lshrrev_b32_e32 v6, 8, v6
v_sub_nc_u32_e32 v2, v2, v3
v_and_or_b32 v3, v0, 15, s15
v_lshlrev_b32_e32 v43, 1, v0
s_movk_i32 s7, 0x2000
s_movk_i32 s8, 0x800
v_lshlrev_b32_e32 v2, 9, v2
v_lshl_add_u32 v45, v1, 9, v3
v_mul_i32_i24_e32 v1, s14, v5
s_movk_i32 s6, 0x1800
v_or_b32_e32 v44, s7, v43
v_add3_u32 v46, v3, v4, v2
v_mul_i32_i24_e32 v2, s14, v6
v_lshlrev_b32_e32 v3, 2, v0
v_mul_u32_u24_e32 v4, 0x50, v41
v_add3_u32 v47, v45, v1, s8
v_mov_b32_e32 v1, 0
v_add3_u32 v48, v45, v2, s6
v_and_b32_e32 v42, 0x7c, v3
v_lshl_or_b32 v49, v4, 1, s7
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v28, 0
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v31, 0
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v32, 0
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v40, 0
v_mov_b32_e32 v30, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v34, 0
v_mov_b32_e32 v29, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v36, 0
v_mov_b32_e32 v33, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v38, 0
v_mov_b32_e32 v35, 0
v_mov_b32_e32 v39, 0
v_mov_b32_e32 v37, 0
v_mov_b32_e32 v24, 0
v_mov_b32_e32 v22, 0
s_mov_b32 s9, 0
s_movk_i32 s14, 0x1000
BB60_1:
s_lshl_b32 s15, s9, 4
v_lshl_or_b32 v56, s9, 12, v0
v_add_nc_u32_e32 v50, s15, v45
v_add_nc_u32_e32 v52, s15, v46
v_add_nc_u32_e32 v54, s15, v47
v_add_nc_u32_e32 v58, s15, v48
v_ashrrev_i32_e32 v57, 31, v56
v_ashrrev_i32_e32 v51, 31, v50
v_ashrrev_i32_e32 v53, 31, v52
v_ashrrev_i32_e32 v55, 31, v54
v_ashrrev_i32_e32 v59, 31, v58
v_lshlrev_b64 v[56:57], 1, v[56:57]
v_lshlrev_b64 v[50:51], 1, v[50:51]
v_lshlrev_b64 v[52:53], 1, v[52:53]
v_lshlrev_b64 v[54:55], 1, v[54:55]
v_lshlrev_b64 v[58:59], 1, v[58:59]
s_mov_b32 s15, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v50, vcc_lo, s10, v50
v_add_co_ci_u32_e32 v51, vcc_lo, s11, v51, vcc_lo
global_load_ushort v64, v[50:51], off
v_add_co_u32 v50, vcc_lo, s7, v50
v_add_co_ci_u32_e32 v51, vcc_lo, 0, v51, vcc_lo
v_add_co_u32 v52, vcc_lo, s10, v52
v_add_co_ci_u32_e32 v53, vcc_lo, s11, v53, vcc_lo
v_add_co_u32 v54, vcc_lo, s10, v54
v_add_co_ci_u32_e32 v55, vcc_lo, s11, v55, vcc_lo
v_add_co_u32 v56, vcc_lo, s12, v56
v_add_co_ci_u32_e32 v57, vcc_lo, s13, v57, vcc_lo
v_add_co_u32 v58, vcc_lo, s10, v58
v_add_co_ci_u32_e32 v59, vcc_lo, s11, v59, vcc_lo
v_add_co_u32 v60, vcc_lo, s8, v56
v_add_co_ci_u32_e32 v61, vcc_lo, 0, v57, vcc_lo
v_add_co_u32 v62, vcc_lo, v56, s14
v_add_co_ci_u32_e32 v63, vcc_lo, 0, v57, vcc_lo
s_clause 0xf
global_load_ushort v65, v[56:57], off
global_load_ushort v66, v[56:57], off offset:256
global_load_ushort v67, v[56:57], off offset:512
global_load_ushort v68, v[56:57], off offset:768
global_load_ushort v69, v[56:57], off offset:1024
global_load_ushort v70, v[56:57], off offset:1280
global_load_ushort v71, v[56:57], off offset:1536
global_load_ushort v72, v[56:57], off offset:1792
global_load_ushort v73, v[62:63], off offset:-2048
global_load_ushort v74, v[60:61], off offset:256
global_load_ushort v75, v[60:61], off offset:512
global_load_ushort v76, v[60:61], off offset:768
global_load_ushort v77, v[60:61], off offset:1024
global_load_ushort v78, v[60:61], off offset:1280
global_load_ushort v79, v[60:61], off offset:1536
global_load_ushort v60, v[60:61], off offset:1792
v_add_co_u32 v56, vcc_lo, s6, v56
v_add_co_ci_u32_e32 v57, vcc_lo, 0, v57, vcc_lo
s_clause 0xf
global_load_ushort v61, v[62:63], off
global_load_ushort v80, v[62:63], off offset:256
global_load_ushort v81, v[62:63], off offset:512
global_load_ushort v82, v[62:63], off offset:768
global_load_ushort v83, v[62:63], off offset:1024
global_load_ushort v84, v[62:63], off offset:1280
global_load_ushort v85, v[62:63], off offset:1536
global_load_ushort v62, v[62:63], off offset:1792
global_load_ushort v63, v[56:57], off
global_load_ushort v86, v[56:57], off offset:256
global_load_ushort v87, v[56:57], off offset:512
global_load_ushort v88, v[56:57], off offset:768
global_load_ushort v89, v[56:57], off offset:1024
global_load_ushort v90, v[56:57], off offset:1280
global_load_ushort v91, v[56:57], off offset:1536
global_load_ushort v56, v[56:57], off offset:1792
s_clause 0x3
global_load_ushort v51, v[50:51], off
global_load_ushort v52, v[52:53], off
global_load_ushort v53, v[54:55], off
global_load_ushort v54, v[58:59], off
v_mov_b32_e32 v50, v49
s_waitcnt vmcnt(0)
s_barrier
ds_write_b16 v43, v65
ds_write_b16 v43, v66 offset:256
ds_write_b16 v43, v67 offset:512
ds_write_b16 v43, v68 offset:768
ds_write_b16 v43, v69 offset:1024
ds_write_b16 v43, v70 offset:1280
ds_write_b16 v43, v71 offset:1536
ds_write_b16 v43, v72 offset:1792
ds_write_b16 v44, v64
ds_write_b16 v43, v73 offset:2048
ds_write_b16 v43, v74 offset:2304
ds_write_b16 v43, v75 offset:2560
ds_write_b16 v43, v76 offset:2816
ds_write_b16 v43, v77 offset:3072
ds_write_b16 v43, v78 offset:3328
ds_write_b16 v43, v79 offset:3584
ds_write_b16 v43, v60 offset:3840
ds_write_b16 v43, v61 offset:4096
ds_write_b16 v43, v80 offset:4352
ds_write_b16 v43, v81 offset:4608
ds_write_b16 v43, v82 offset:4864
ds_write_b16 v43, v83 offset:5120
ds_write_b16 v43, v84 offset:5376
ds_write_b16 v43, v85 offset:5632
ds_write_b16 v43, v62 offset:5888
ds_write_b16 v43, v63 offset:6144
ds_write_b16 v43, v86 offset:6400
ds_write_b16 v43, v87 offset:6656
ds_write_b16 v43, v88 offset:6912
ds_write_b16 v43, v89 offset:7168
ds_write_b16 v43, v90 offset:7424
ds_write_b16 v43, v91 offset:7680
ds_write_b16 v43, v56 offset:7936
ds_write_b16 v44, v51 offset:256
ds_write_b16 v44, v52 offset:512
ds_write_b16 v44, v53 offset:768
ds_write_b16 v44, v54 offset:1024
s_waitcnt lgkmcnt(0)
s_barrier
BB60_2:
v_or_b32_e32 v71, s15, v42
ds_read2_b64 v[51:54], v50 offset1:4
ds_read2_b64 v[55:58], v50 offset0:8 offset1:12
ds_read2_b64 v[59:62], v50 offset0:16 offset1:80
ds_read2_b64 v[63:66], v50 offset0:84 offset1:88
ds_read2_b64 v[67:70], v50 offset0:92 offset1:96
v_add_nc_u32_e32 v50, 8, v50
s_addk_i32 s15, 0x400
v_lshlrev_b32_e32 v85, 1, v71
s_cmp_lg_u32 s15, s14
ds_read2_b32 v[83:84], v85 offset1:1
ds_read2_b64 v[71:74], v85 offset0:32 offset1:64
ds_read2_b64 v[75:78], v85 offset0:96 offset1:128
ds_read2_b64 v[79:82], v85 offset0:160 offset1:192
ds_read_b64 v[85:86], v85 offset:1792
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v39, v51, v83, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v51, v84, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v53, v83, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v53, v84, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v55, v83, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v55, v84, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v57, v83, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v57, v84, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v40, v59, v83, v40 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v59, v84, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v61, v83, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v61, v84, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v63, v83, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v63, v84, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v65, v83, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v65, v84, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v67, v83, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v67, v84, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v69, v83, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v69, v84, v19 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v24, v51, v71, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v51, v72, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v53, v71, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v53, v72, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v55, v71, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v55, v72, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v57, v71, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v57, v72, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v59, v71, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v59, v72, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v61, v71, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v61, v72, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v63, v71, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v63, v72, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v65, v71, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v65, v72, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v67, v71, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v67, v72, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v69, v71, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v69, v72, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v39, v51, v73, v39 op_sel:[1,0,0]
v_pk_fma_f16 v37, v51, v74, v37 op_sel:[1,0,0]
v_pk_fma_f16 v38, v53, v73, v38 op_sel:[1,0,0]
v_pk_fma_f16 v35, v53, v74, v35 op_sel:[1,0,0]
v_pk_fma_f16 v36, v55, v73, v36 op_sel:[1,0,0]
v_pk_fma_f16 v33, v55, v74, v33 op_sel:[1,0,0]
v_pk_fma_f16 v34, v57, v73, v34 op_sel:[1,0,0]
v_pk_fma_f16 v29, v57, v74, v29 op_sel:[1,0,0]
v_pk_fma_f16 v40, v59, v73, v40 op_sel:[1,0,0]
v_pk_fma_f16 v30, v59, v74, v30 op_sel:[1,0,0]
v_pk_fma_f16 v32, v61, v73, v32 op_sel:[1,0,0]
v_pk_fma_f16 v27, v61, v74, v27 op_sel:[1,0,0]
v_pk_fma_f16 v31, v63, v73, v31 op_sel:[1,0,0]
v_pk_fma_f16 v26, v63, v74, v26 op_sel:[1,0,0]
v_pk_fma_f16 v28, v65, v73, v28 op_sel:[1,0,0]
v_pk_fma_f16 v23, v65, v74, v23 op_sel:[1,0,0]
v_pk_fma_f16 v25, v67, v73, v25 op_sel:[1,0,0]
v_pk_fma_f16 v20, v67, v74, v20 op_sel:[1,0,0]
v_pk_fma_f16 v21, v69, v73, v21 op_sel:[1,0,0]
v_pk_fma_f16 v19, v69, v74, v19 op_sel:[1,0,0]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v24, v51, v75, v24 op_sel:[1,0,0]
v_pk_fma_f16 v22, v51, v76, v22 op_sel:[1,0,0]
v_pk_fma_f16 v17, v53, v75, v17 op_sel:[1,0,0]
v_pk_fma_f16 v18, v53, v76, v18 op_sel:[1,0,0]
v_pk_fma_f16 v15, v55, v75, v15 op_sel:[1,0,0]
v_pk_fma_f16 v16, v55, v76, v16 op_sel:[1,0,0]
v_pk_fma_f16 v13, v57, v75, v13 op_sel:[1,0,0]
v_pk_fma_f16 v14, v57, v76, v14 op_sel:[1,0,0]
v_pk_fma_f16 v11, v59, v75, v11 op_sel:[1,0,0]
v_pk_fma_f16 v12, v59, v76, v12 op_sel:[1,0,0]
v_pk_fma_f16 v9, v61, v75, v9 op_sel:[1,0,0]
v_pk_fma_f16 v10, v61, v76, v10 op_sel:[1,0,0]
v_pk_fma_f16 v7, v63, v75, v7 op_sel:[1,0,0]
v_pk_fma_f16 v8, v63, v76, v8 op_sel:[1,0,0]
v_pk_fma_f16 v5, v65, v75, v5 op_sel:[1,0,0]
v_pk_fma_f16 v6, v65, v76, v6 op_sel:[1,0,0]
v_pk_fma_f16 v3, v67, v75, v3 op_sel:[1,0,0]
v_pk_fma_f16 v4, v67, v76, v4 op_sel:[1,0,0]
v_pk_fma_f16 v1, v69, v75, v1 op_sel:[1,0,0]
v_pk_fma_f16 v2, v69, v76, v2 op_sel:[1,0,0]
v_pk_fma_f16 v39, v52, v77, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v52, v78, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v54, v77, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v54, v78, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v56, v77, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v56, v78, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v58, v77, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v58, v78, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v40, v60, v77, v40 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v60, v78, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v62, v77, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v62, v78, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v64, v77, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v64, v78, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v66, v77, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v66, v78, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v68, v77, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v68, v78, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v70, v77, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v70, v78, v19 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v24, v52, v79, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v52, v80, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v54, v79, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v54, v80, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v56, v79, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v56, v80, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v58, v79, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v58, v80, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v60, v79, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v60, v80, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v62, v79, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v62, v80, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v64, v79, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v64, v80, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v66, v79, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v66, v80, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v68, v79, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v68, v80, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v70, v79, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v70, v80, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v39, v52, v81, v39 op_sel:[1,0,0]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v24, v52, v85, v24 op_sel:[1,0,0]
v_pk_fma_f16 v37, v52, v82, v37 op_sel:[1,0,0]
v_pk_fma_f16 v22, v52, v86, v22 op_sel:[1,0,0]
v_pk_fma_f16 v38, v54, v81, v38 op_sel:[1,0,0]
v_pk_fma_f16 v17, v54, v85, v17 op_sel:[1,0,0]
v_pk_fma_f16 v35, v54, v82, v35 op_sel:[1,0,0]
v_pk_fma_f16 v18, v54, v86, v18 op_sel:[1,0,0]
v_pk_fma_f16 v36, v56, v81, v36 op_sel:[1,0,0]
v_pk_fma_f16 v15, v56, v85, v15 op_sel:[1,0,0]
v_pk_fma_f16 v33, v56, v82, v33 op_sel:[1,0,0]
v_pk_fma_f16 v16, v56, v86, v16 op_sel:[1,0,0]
v_pk_fma_f16 v34, v58, v81, v34 op_sel:[1,0,0]
v_pk_fma_f16 v13, v58, v85, v13 op_sel:[1,0,0]
v_pk_fma_f16 v29, v58, v82, v29 op_sel:[1,0,0]
v_pk_fma_f16 v14, v58, v86, v14 op_sel:[1,0,0]
v_pk_fma_f16 v40, v60, v81, v40 op_sel:[1,0,0]
v_pk_fma_f16 v11, v60, v85, v11 op_sel:[1,0,0]
v_pk_fma_f16 v30, v60, v82, v30 op_sel:[1,0,0]
v_pk_fma_f16 v12, v60, v86, v12 op_sel:[1,0,0]
v_pk_fma_f16 v32, v62, v81, v32 op_sel:[1,0,0]
v_pk_fma_f16 v9, v62, v85, v9 op_sel:[1,0,0]
v_pk_fma_f16 v27, v62, v82, v27 op_sel:[1,0,0]
v_pk_fma_f16 v10, v62, v86, v10 op_sel:[1,0,0]
v_pk_fma_f16 v31, v64, v81, v31 op_sel:[1,0,0]
v_pk_fma_f16 v7, v64, v85, v7 op_sel:[1,0,0]
v_pk_fma_f16 v26, v64, v82, v26 op_sel:[1,0,0]
v_pk_fma_f16 v8, v64, v86, v8 op_sel:[1,0,0]
v_pk_fma_f16 v28, v66, v81, v28 op_sel:[1,0,0]
v_pk_fma_f16 v5, v66, v85, v5 op_sel:[1,0,0]
v_pk_fma_f16 v23, v66, v82, v23 op_sel:[1,0,0]
v_pk_fma_f16 v6, v66, v86, v6 op_sel:[1,0,0]
v_pk_fma_f16 v25, v68, v81, v25 op_sel:[1,0,0]
v_pk_fma_f16 v3, v68, v85, v3 op_sel:[1,0,0]
v_pk_fma_f16 v20, v68, v82, v20 op_sel:[1,0,0]
v_pk_fma_f16 v4, v68, v86, v4 op_sel:[1,0,0]
v_pk_fma_f16 v21, v70, v81, v21 op_sel:[1,0,0]
v_pk_fma_f16 v1, v70, v85, v1 op_sel:[1,0,0]
v_pk_fma_f16 v19, v70, v82, v19 op_sel:[1,0,0]
v_pk_fma_f16 v2, v70, v86, v2 op_sel:[1,0,0]
s_cbranch_scc1 BB60_2
s_add_i32 s9, s9, 1
s_cmp_eq_u32 s9, 32
s_cbranch_scc0 BB60_1
v_mul_u32_u24_e32 v41, 0x500, v41
s_mulk_i32 s5, 0x1400
s_mul_i32 s4, s4, 0xc800
v_lshlrev_b32_e32 v0, 1, v42
v_add3_u32 v41, s5, s4, v41
s_clause 0x2
global_load_dword v89, v0, s[0:1]
global_load_ushort v90, v0, s[0:1] offset:260
global_load_ushort v91, v0, s[0:1] offset:262
v_or_b32_e32 v41, v41, v42
v_add_nc_u32_e32 v43, 0x400, v41
v_ashrrev_i32_e32 v42, 31, v41
v_add_nc_u32_e32 v45, 0x402, v41
v_add_nc_u32_e32 v49, 0x6400, v41
v_add_nc_u32_e32 v51, 0x6402, v41
v_ashrrev_i32_e32 v44, 31, v43
v_lshlrev_b64 v[85:86], 1, v[41:42]
v_ashrrev_i32_e32 v46, 31, v45
v_ashrrev_i32_e32 v50, 31, v49
v_add_nc_u32_e32 v47, 0x480, v41
v_lshlrev_b64 v[42:43], 1, v[43:44]
v_add_nc_u32_e32 v55, 0x6500, v41
v_add_co_u32 v85, vcc_lo, s2, v85
v_lshlrev_b64 v[44:45], 1, v[45:46]
v_ashrrev_i32_e32 v52, 31, v51
v_add_co_ci_u32_e32 v86, vcc_lo, s3, v86, vcc_lo
v_add_nc_u32_e32 v57, 0x6502, v41
v_add_co_u32 v42, vcc_lo, s2, v42
v_lshlrev_b64 v[49:50], 1, v[49:50]
v_ashrrev_i32_e32 v56, 31, v55
v_ashrrev_i32_e32 v48, 31, v47
v_add_co_ci_u32_e32 v43, vcc_lo, s3, v43, vcc_lo
v_add_nc_u32_e32 v59, 0x6600, v41
v_add_co_u32 v44, vcc_lo, s2, v44
v_lshlrev_b64 v[51:52], 1, v[51:52]
v_ashrrev_i32_e32 v58, 31, v57
v_add_nc_u32_e32 v61, 0x6602, v41
v_add_co_ci_u32_e32 v45, vcc_lo, s3, v45, vcc_lo
v_lshlrev_b64 v[46:47], 1, v[47:48]
v_add_co_u32 v48, vcc_lo, s2, v49
v_lshlrev_b64 v[55:56], 1, v[55:56]
v_ashrrev_i32_e32 v60, 31, v59
v_add_co_ci_u32_e32 v49, vcc_lo, s3, v50, vcc_lo
v_add_co_u32 v50, vcc_lo, s2, v51
v_lshlrev_b64 v[57:58], 1, v[57:58]
v_ashrrev_i32_e32 v62, 31, v61
v_add_co_ci_u32_e32 v51, vcc_lo, s3, v52, vcc_lo
v_add_nc_u32_e32 v53, 0x482, v41
v_add_co_u32 v55, vcc_lo, s2, v55
v_lshlrev_b64 v[59:60], 1, v[59:60]
v_add_co_ci_u32_e32 v56, vcc_lo, s3, v56, vcc_lo
v_add_co_u32 v57, vcc_lo, s2, v57
v_lshlrev_b64 v[61:62], 1, v[61:62]
v_ashrrev_i32_e32 v54, 31, v53
v_add_co_ci_u32_e32 v58, vcc_lo, s3, v58, vcc_lo
v_add_co_u32 v59, vcc_lo, s2, v59
v_add_nc_u32_e32 v63, 0x6480, v41
v_add_co_ci_u32_e32 v60, vcc_lo, s3, v60, vcc_lo
v_add_co_u32 v61, vcc_lo, s2, v61
v_lshlrev_b64 v[53:54], 1, v[53:54]
v_add_co_ci_u32_e32 v62, vcc_lo, s3, v62, vcc_lo
v_add_co_u32 v46, vcc_lo, s2, v46
v_add_nc_u32_e32 v65, 0x6482, v41
v_add_co_ci_u32_e32 v47, vcc_lo, s3, v47, vcc_lo
v_ashrrev_i32_e32 v64, 31, v63
v_add_co_u32 v52, vcc_lo, s2, v53
v_add_nc_u32_e32 v67, 0x6580, v41
v_add_co_ci_u32_e32 v53, vcc_lo, s3, v54, vcc_lo
s_clause 0x2
global_load_dword v54, v0, s[0:1] offset:4
global_load_ushort v92, v0, s[0:1] offset:256
global_load_ushort v0, v0, s[0:1] offset:258
v_ashrrev_i32_e32 v66, 31, v65
v_add_nc_u32_e32 v69, 0x6582, v41
v_lshlrev_b64 v[63:64], 1, v[63:64]
v_ashrrev_i32_e32 v68, 31, v67
v_add_nc_u32_e32 v71, 0x6680, v41
v_lshlrev_b64 v[65:66], 1, v[65:66]
v_ashrrev_i32_e32 v70, 31, v69
v_add_nc_u32_e32 v73, 0x6682, v41
v_add_co_u32 v63, vcc_lo, s2, v63
v_lshlrev_b64 v[67:68], 1, v[67:68]
v_ashrrev_i32_e32 v72, 31, v71
v_add_co_ci_u32_e32 v64, vcc_lo, s3, v64, vcc_lo
v_add_nc_u32_e32 v75, 0x6700, v41
v_add_co_u32 v65, vcc_lo, s2, v65
v_lshlrev_b64 v[69:70], 1, v[69:70]
v_ashrrev_i32_e32 v74, 31, v73
v_add_co_ci_u32_e32 v66, vcc_lo, s3, v66, vcc_lo
v_add_nc_u32_e32 v77, 0x6780, v41
v_add_co_u32 v67, vcc_lo, s2, v67
v_lshlrev_b64 v[71:72], 1, v[71:72]
v_ashrrev_i32_e32 v76, 31, v75
v_add_co_ci_u32_e32 v68, vcc_lo, s3, v68, vcc_lo
v_add_nc_u32_e32 v79, 0x6702, v41
v_add_co_u32 v69, vcc_lo, s2, v69
v_lshlrev_b64 v[73:74], 1, v[73:74]
v_ashrrev_i32_e32 v78, 31, v77
v_add_co_ci_u32_e32 v70, vcc_lo, s3, v70, vcc_lo
v_add_nc_u32_e32 v81, 0x6782, v41
v_add_co_u32 v71, vcc_lo, s2, v71
v_lshlrev_b64 v[75:76], 1, v[75:76]
v_ashrrev_i32_e32 v80, 31, v79
v_add_co_ci_u32_e32 v72, vcc_lo, s3, v72, vcc_lo
v_add_nc_u32_e32 v83, 0x6800, v41
v_add_co_u32 v73, vcc_lo, s2, v73
v_lshlrev_b64 v[77:78], 1, v[77:78]
v_ashrrev_i32_e32 v82, 31, v81
v_add_co_ci_u32_e32 v74, vcc_lo, s3, v74, vcc_lo
v_add_co_u32 v75, vcc_lo, s2, v75
v_lshlrev_b64 v[79:80], 1, v[79:80]
v_ashrrev_i32_e32 v84, 31, v83
v_add_co_ci_u32_e32 v76, vcc_lo, s3, v76, vcc_lo
v_add_nc_u32_e32 v87, 0x6802, v41
v_add_co_u32 v77, vcc_lo, s2, v77
v_lshlrev_b64 v[81:82], 1, v[81:82]
v_add_co_ci_u32_e32 v78, vcc_lo, s3, v78, vcc_lo
v_add_co_u32 v79, vcc_lo, s2, v79
v_lshlrev_b64 v[83:84], 1, v[83:84]
v_ashrrev_i32_e32 v88, 31, v87
v_add_co_ci_u32_e32 v80, vcc_lo, s3, v80, vcc_lo
v_add_co_u32 v81, vcc_lo, s2, v81
v_add_co_ci_u32_e32 v82, vcc_lo, s3, v82, vcc_lo
v_add_co_u32 v83, vcc_lo, s2, v83
v_lshlrev_b64 v[87:88], 1, v[87:88]
v_add_co_ci_u32_e32 v84, vcc_lo, s3, v84, vcc_lo
s_waitcnt vmcnt(5)
v_pk_add_f16 v40, v89, v40
v_pk_add_f16 v32, v89, v32
v_pk_add_f16 v31, v89, v31
v_pk_add_f16 v28, v89, v28
v_pk_add_f16 v39, v89, v39
v_pk_max_f16 v40, v40, 0
v_pk_add_f16 v38, v89, v38
v_pk_add_f16 v36, v89, v36
v_pk_add_f16 v34, v89, v34
v_pk_add_f16 v25, v89, v25
global_store_dword v[42:43], v40, off
v_add_nc_u32_e32 v42, 0x6880, v41
v_pk_add_f16 v21, v89, v21
v_add_nc_u32_e32 v40, 0x6882, v41
v_pk_max_f16 v34, v34, 0
v_pk_max_f16 v25, v25, 0
v_ashrrev_i32_e32 v43, 31, v42
v_pk_max_f16 v21, v21, 0
v_ashrrev_i32_e32 v41, 31, v40
v_pk_max_f16 v32, v32, 0
v_pk_max_f16 v31, v31, 0
v_lshlrev_b64 v[42:43], 1, v[42:43]
v_pk_max_f16 v28, v28, 0
v_lshlrev_b64 v[40:41], 1, v[40:41]
v_pk_max_f16 v39, v39, 0
v_pk_max_f16 v38, v38, 0
v_pk_max_f16 v36, v36, 0
v_add_co_u32 v42, vcc_lo, s2, v42
v_add_co_ci_u32_e32 v43, vcc_lo, s3, v43, vcc_lo
v_add_co_u32 v87, vcc_lo, s2, v87
v_add_co_ci_u32_e32 v88, vcc_lo, s3, v88, vcc_lo
v_add_co_u32 v40, vcc_lo, s2, v40
v_add_co_ci_u32_e32 v41, vcc_lo, s3, v41, vcc_lo
s_waitcnt vmcnt(2)
v_pk_add_f16 v30, v54, v30
v_pk_add_f16 v27, v54, v27
v_pk_add_f16 v26, v54, v26
v_pk_add_f16 v23, v54, v23
v_pk_add_f16 v37, v54, v37
v_pk_add_f16 v35, v54, v35
v_pk_add_f16 v33, v54, v33
v_pk_add_f16 v29, v54, v29
v_pk_add_f16 v20, v54, v20
v_pk_add_f16 v19, v54, v19
v_mov_b32_e32 v54, 0xffff
v_pk_max_f16 v30, v30, 0
v_pk_max_f16 v29, v29, 0
v_pk_max_f16 v20, v20, 0
v_pk_max_f16 v19, v19, 0
s_waitcnt vmcnt(1)
v_and_b32_e32 v89, v54, v92
v_and_b32_e32 v54, v54, v90
v_add_f16_e32 v92, v92, v24
s_waitcnt vmcnt(0)
v_add_f16_sdwa v24, v0, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_max_f16 v27, v27, 0
v_lshl_or_b32 v0, v0, 16, v89
v_lshl_or_b32 v54, v91, 16, v54
v_add_f16_e32 v89, v90, v22
v_add_f16_sdwa v22, v91, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_max_f16 v26, v26, 0
v_pk_add_f16 v17, v0, v17
v_pk_add_f16 v18, v54, v18
v_pk_add_f16 v15, v0, v15
v_pk_add_f16 v16, v54, v16
v_pk_add_f16 v13, v0, v13
v_pk_add_f16 v14, v54, v14
v_pk_add_f16 v11, v0, v11
v_pk_add_f16 v12, v54, v12
v_pk_add_f16 v9, v0, v9
v_pk_add_f16 v10, v54, v10
v_pk_add_f16 v7, v0, v7
v_pk_add_f16 v8, v54, v8
v_pk_add_f16 v5, v0, v5
v_pk_add_f16 v3, v0, v3
v_pk_add_f16 v0, v0, v1
v_pk_add_f16 v1, v54, v2
v_pk_add_f16 v6, v54, v6
v_pk_add_f16 v4, v54, v4
v_pk_max_f16 v2, v17, 0
v_pk_max_f16 v17, v18, 0
v_pk_max_f16 v15, v15, 0
v_pk_max_f16 v16, v16, 0
v_pk_max_f16 v13, v13, 0
v_pk_max_f16 v23, v23, 0
v_max_f16_e32 v90, 0, v92
v_max_f16_e32 v24, 0, v24
v_max_f16_e32 v89, 0, v89
v_pk_max_f16 v37, v37, 0
v_max_f16_e32 v22, 0, v22
v_pk_max_f16 v35, v35, 0
v_pk_max_f16 v33, v33, 0
global_store_dword v[44:45], v30, off
global_store_dword v[48:49], v32, off
global_store_dword v[50:51], v27, off
global_store_dword v[55:56], v31, off
global_store_dword v[57:58], v26, off
global_store_dword v[59:60], v28, off
global_store_dword v[61:62], v23, off
global_store_short v[85:86], v90, off offset:256
global_store_dword v[85:86], v39, off
global_store_short v[85:86], v24, off offset:258
global_store_short v[85:86], v89, off offset:260
global_store_dword v[85:86], v37, off offset:4
global_store_short v[85:86], v22, off offset:262
global_store_dword v[85:86], v38, off offset:512
global_store_dword v[85:86], v35, off offset:516
global_store_dword v[85:86], v36, off offset:1024
global_store_dword v[85:86], v33, off offset:1028
global_store_dword v[85:86], v34, off offset:1536
global_store_dword v[85:86], v29, off offset:1540
global_store_dword v[75:76], v25, off
global_store_dword v[79:80], v20, off
global_store_dword v[83:84], v21, off
global_store_dword v[87:88], v19, off
v_pk_max_f16 v14, v14, 0
v_pk_max_f16 v11, v11, 0
v_pk_max_f16 v12, v12, 0
v_pk_max_f16 v9, v9, 0
v_pk_max_f16 v10, v10, 0
v_pk_max_f16 v7, v7, 0
v_pk_max_f16 v8, v8, 0
v_pk_max_f16 v5, v5, 0
v_pk_max_f16 v6, v6, 0
v_pk_max_f16 v3, v3, 0
v_pk_max_f16 v4, v4, 0
v_pk_max_f16 v0, v0, 0
v_pk_max_f16 v1, v1, 0
global_store_dword v[85:86], v2, off offset:768
global_store_dword v[85:86], v17, off offset:772
global_store_dword v[85:86], v15, off offset:1280
global_store_dword v[85:86], v16, off offset:1284
global_store_dword v[85:86], v13, off offset:1792
global_store_dword v[85:86], v14, off offset:1796
global_store_dword v[46:47], v11, off
global_store_dword v[52:53], v12, off
global_store_dword v[63:64], v9, off
global_store_dword v[65:66], v10, off
global_store_dword v[67:68], v7, off
global_store_dword v[69:70], v8, off
global_store_dword v[71:72], v5, off
global_store_dword v[73:74], v6, off
global_store_dword v[77:78], v3, off
global_store_dword v[81:82], v4, off
global_store_dword v[42:43], v0, off
global_store_dword v[40:41], v1, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_nn_relu_6_kernel0
.amdhsa_group_segment_fixed_size 9472
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 93
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end60:
.size tvmgen_default_fused_nn_conv2d_add_nn_relu_6_kernel0, .Lfunc_end60-tvmgen_default_fused_nn_conv2d_add_nn_relu_6_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_nn_relu_7_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_nn_relu_7_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_nn_relu_7_kernel0:
v_lshrrev_b32_e32 v5, 2, v0
s_mov_b32 s0, 0x30c30c31
v_add_nc_u32_e32 v9, 0x80, v0
v_mul_hi_i32 v7, v0, s0
v_lshrrev_b32_e32 v1, 6, v0
v_add_nc_u32_e32 v6, 11, v5
v_lshlrev_b32_e32 v12, 2, v0
v_lshrrev_b32_e32 v9, 2, v9
s_mul_hi_i32 s3, s6, 0x66666667
v_mul_u32_u24_e32 v13, 40, v1
v_mul_hi_u32 v3, 0x86186187, v6
v_lshrrev_b32_e32 v11, 31, v7
v_ashrrev_i32_e32 v7, 4, v7
v_mul_hi_u32 v9, v9, s0
s_lshr_b32 s14, s3, 31
s_ashr_i32 s3, s3, 1
s_movk_i32 s1, 0x4800
v_add_nc_u32_e32 v7, v7, v11
v_sub_nc_u32_e32 v10, v6, v3
s_add_i32 s3, s3, s14
s_clause 0x3
s_load_dwordx2 s[10:11], s[4:5], 0x0
s_load_dwordx2 s[12:13], s[4:5], 0x8
s_load_dwordx2 s[8:9], s[4:5], 0x10
s_load_dwordx2 s[4:5], s[4:5], 0x18
v_and_or_b32 v8, v0, 3, 0xffff9b00
v_lshrrev_b32_e32 v9, 2, v9
v_lshrrev_b32_e32 v10, 1, v10
v_lshl_or_b32 v2, v0, 1, s1
v_cmp_gt_i32_e32 vcc_lo, 0x7c, v0
v_lshlrev_b32_e32 v4, 4, v0
s_movk_i32 s2, 0x6400
v_add_nc_u32_e32 v3, v10, v3
v_mul_lo_u32 v10, 0x54, v7
v_lshlrev_b32_e32 v5, 8, v5
v_mad_i32_i24 v9, v9, s2, v8
s_mul_i32 s7, s6, 0x1400
v_lshrrev_b32_e32 v11, 4, v3
v_and_b32_e32 v3, 0xfc, v12
s_mul_i32 s15, s3, s2
s_mul_i32 s14, s3, 5
v_sub_nc_u32_e32 v10, v0, v10
v_mul_lo_u32 v12, v11, 21
v_lshl_or_b32 v0, v13, 1, s1
v_add_nc_u32_e32 v13, s3, v7
s_add_i32 s0, s7, s15
v_ashrrev_i32_e32 v10, 2, v10
s_sub_i32 s14, s6, s14
v_add3_u32 v9, s0, v9, v5
v_mul_u32_u24_e32 v11, 0x1500, v11
v_sub_nc_u32_e32 v6, v6, v12
v_mul_lo_u32 v12, v13, s2
s_mul_i32 s14, s14, 20
v_lshl_add_u32 v7, s3, 1, v7
v_add_nc_u32_e32 v13, s14, v10
v_add_nc_u32_e32 v6, s14, v6
v_sub_nc_u32_e32 v9, v9, v11
v_lshlrev_b32_e32 v10, 8, v10
v_cmp_lt_i32_e64 s1, 0, v7
v_add_nc_u32_e32 v11, v8, v12
v_cmp_lt_i32_e64 s2, 0, v13
v_cmp_lt_i32_e64 s0, 0, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, s3, s12, v4
v_lshlrev_b32_e32 v5, 1, v3
v_add_co_ci_u32_e64 v7, s3, s13, 0, s3
v_add_nc_u32_e32 v8, 0xb00, v9
v_add3_u32 v10, v11, s7, v10
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v21, 0
s_and_b32 s2, s1, s2
s_mov_b64 s[12:13], 0
s_mov_b32 s3, 0x20000
s_branch BB61_3
BB61_1:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
ds_write_b16 v2, v9 offset:256
BB61_2:
s_or_b32 exec_lo, exec_lo, s7
v_add_co_u32 v38, s1, v6, s12
v_add_nc_u32_e32 v8, 4, v8
v_add_co_ci_u32_e64 v39, s1, s13, v7, s1
v_add_nc_u32_e32 v10, 4, v10
s_add_u32 s12, s12, 0x800
v_add_co_u32 v26, s1, s3, v38
s_addc_u32 s13, s13, 0
v_add_co_ci_u32_e64 v27, s1, 0, v39, s1
v_add_co_u32 v30, s1, 0x40000, v38
s_cmp_eq_u32 s12, s3
v_add_co_ci_u32_e64 v31, s1, 0, v39, s1
v_add_co_u32 v34, s1, 0x60000, v38
v_add_co_ci_u32_e64 v35, s1, 0, v39, s1
v_add_co_u32 v40, s1, 0x80000, v38
s_clause 0x3
global_load_dwordx4 v[22:25], v[38:39], off
global_load_dwordx4 v[26:29], v[26:27], off
global_load_dwordx4 v[30:33], v[30:31], off
global_load_dwordx4 v[34:37], v[34:35], off
v_add_co_ci_u32_e64 v41, s1, 0, v39, s1
v_add_co_u32 v42, s1, 0xa0000, v38
v_add_co_ci_u32_e64 v43, s1, 0, v39, s1
v_add_co_u32 v46, s1, 0xc0000, v38
v_add_co_ci_u32_e64 v47, s1, 0, v39, s1
v_add_co_u32 v50, s1, 0xe0000, v38
v_add_co_ci_u32_e64 v51, s1, 0, v39, s1
v_add_co_u32 v54, s1, 0x100000, v38
v_add_co_ci_u32_e64 v55, s1, 0, v39, s1
s_clause 0x4
global_load_dwordx4 v[38:41], v[40:41], off
global_load_dwordx4 v[42:45], v[42:43], off
global_load_dwordx4 v[46:49], v[46:47], off
global_load_dwordx4 v[50:53], v[50:51], off
global_load_dwordx4 v[54:57], v[54:55], off
s_waitcnt vmcnt(8)
ds_write_b128 v4, v[22:25]
s_waitcnt vmcnt(7)
ds_write_b128 v4, v[26:29] offset:2048
s_waitcnt vmcnt(6)
ds_write_b128 v4, v[30:33] offset:4096
s_waitcnt vmcnt(5)
ds_write_b128 v4, v[34:37] offset:6144
s_waitcnt vmcnt(4)
ds_write_b128 v4, v[38:41] offset:8192
s_waitcnt vmcnt(3)
ds_write_b128 v4, v[42:45] offset:10240
s_waitcnt vmcnt(2)
ds_write_b128 v4, v[46:49] offset:12288
s_waitcnt vmcnt(1)
ds_write_b128 v4, v[50:53] offset:14336
s_waitcnt vmcnt(0)
ds_write_b128 v4, v[54:57] offset:16384
s_waitcnt lgkmcnt(0)
s_barrier
ds_read2_b32 v[58:59], v5 offset1:1
ds_read_b128 v[22:25], v0
ds_read_b128 v[26:29], v0 offset:16
ds_read_b128 v[30:33], v0 offset:32
ds_read_b128 v[34:37], v0 offset:48
ds_read_b128 v[38:41], v0 offset:64
ds_read2st64_b64 v[42:45], v5 offset0:1 offset1:2
ds_read2st64_b64 v[46:49], v5 offset0:3 offset1:4
ds_read2st64_b64 v[50:53], v5 offset0:5 offset1:6
ds_read2_b64 v[54:57], v0 offset0:22 offset1:23
s_waitcnt lgkmcnt(8)
v_pk_fma_f16 v9, v22, v58, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v22, v59, v20 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(7)
v_pk_fma_f16 v19, v26, v58, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v26, v59, v18 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(6)
v_pk_fma_f16 v17, v30, v58, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v30, v59, v16 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v15, v34, v58, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v34, v59, v14 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v13, v38, v58, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v38, v59, v12 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v9, v22, v42, v9 op_sel:[1,0,0]
v_pk_fma_f16 v19, v26, v42, v19 op_sel:[1,0,0]
v_pk_fma_f16 v11, v22, v43, v11 op_sel:[1,0,0]
v_pk_fma_f16 v18, v26, v43, v18 op_sel:[1,0,0]
v_pk_fma_f16 v17, v30, v42, v17 op_sel:[1,0,0]
v_pk_fma_f16 v14, v34, v43, v14 op_sel:[1,0,0]
v_pk_fma_f16 v16, v30, v43, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v34, v42, v15 op_sel:[1,0,0]
v_pk_fma_f16 v13, v38, v42, v13 op_sel:[1,0,0]
v_pk_fma_f16 v12, v38, v43, v12 op_sel:[1,0,0]
v_pk_fma_f16 v9, v23, v44, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v23, v45, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v27, v44, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v27, v45, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v31, v44, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v43, v35, v44, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v44, v39, v44, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v42, v31, v45, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v58, v35, v45, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v45, v39, v45, v12 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v9, v23, v46, v9 op_sel:[1,0,0]
v_pk_fma_f16 v44, v39, v46, v44 op_sel:[1,0,0]
v_pk_fma_f16 v20, v23, v47, v20 op_sel:[1,0,0]
v_pk_fma_f16 v23, v31, v47, v42 op_sel:[1,0,0]
v_pk_fma_f16 v42, v35, v46, v43 op_sel:[1,0,0]
v_pk_fma_f16 v43, v35, v47, v58 op_sel:[1,0,0]
v_pk_fma_f16 v45, v39, v47, v45 op_sel:[1,0,0]
v_pk_fma_f16 v21, v27, v47, v21 op_sel:[1,0,0]
v_pk_fma_f16 v19, v27, v46, v19 op_sel:[1,0,0]
v_pk_fma_f16 v22, v31, v46, v22 op_sel:[1,0,0]
ds_read2st64_b64 v[11:14], v5 offset0:7 offset1:8
ds_read2st64_b64 v[15:18], v5 offset0:9 offset1:10
v_pk_fma_f16 v9, v24, v48, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v32, v49, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v46, v24, v49, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v47, v28, v48, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v58, v28, v49, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v59, v32, v48, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v42, v36, v48, v42 op_sel_hi:[0,1,1]
v_pk_fma_f16 v43, v36, v49, v43 op_sel_hi:[0,1,1]
v_pk_fma_f16 v44, v40, v48, v44 op_sel_hi:[0,1,1]
v_pk_fma_f16 v45, v40, v49, v45 op_sel_hi:[0,1,1]
ds_read2_b64 v[19:22], v0 offset0:10 offset1:21
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v9, v24, v50, v9 op_sel:[1,0,0]
v_pk_fma_f16 v24, v24, v51, v46 op_sel:[1,0,0]
v_pk_fma_f16 v46, v28, v50, v47 op_sel:[1,0,0]
v_pk_fma_f16 v28, v28, v51, v58 op_sel:[1,0,0]
v_pk_fma_f16 v23, v32, v51, v23 op_sel:[1,0,0]
v_pk_fma_f16 v47, v32, v50, v59 op_sel:[1,0,0]
v_pk_fma_f16 v32, v36, v50, v42 op_sel:[1,0,0]
v_pk_fma_f16 v36, v36, v51, v43 op_sel:[1,0,0]
v_pk_fma_f16 v42, v40, v50, v44 op_sel:[1,0,0]
v_pk_fma_f16 v40, v40, v51, v45 op_sel:[1,0,0]
v_pk_fma_f16 v9, v25, v52, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v25, v53, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v29, v53, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v33, v53, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v37, v52, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v29, v52, v46 op_sel_hi:[0,1,1]
v_pk_fma_f16 v51, v33, v52, v47 op_sel_hi:[0,1,1]
v_pk_fma_f16 v52, v41, v52, v42 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v37, v53, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v40, v41, v53, v40 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v9, v25, v11, v9 op_sel:[1,0,0]
v_pk_fma_f16 v24, v25, v12, v24 op_sel:[1,0,0]
v_pk_fma_f16 v25, v29, v11, v50 op_sel:[1,0,0]
v_pk_fma_f16 v28, v29, v12, v28 op_sel:[1,0,0]
v_pk_fma_f16 v29, v33, v11, v51 op_sel:[1,0,0]
v_pk_fma_f16 v23, v33, v12, v23 op_sel:[1,0,0]
v_pk_fma_f16 v32, v37, v11, v32 op_sel:[1,0,0]
v_pk_fma_f16 v33, v37, v12, v36 op_sel:[1,0,0]
v_pk_fma_f16 v11, v41, v11, v52 op_sel:[1,0,0]
v_pk_fma_f16 v12, v41, v12, v40 op_sel:[1,0,0]
v_pk_fma_f16 v9, v26, v13, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v34, v14, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v26, v14, v24 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v11, v19, v13, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v19, v14, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v30, v13, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v30, v14, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v38, v14, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v34, v13, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v38, v13, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v26, v15, v9 op_sel:[1,0,0]
v_pk_fma_f16 v13, v26, v16, v24 op_sel:[1,0,0]
v_pk_fma_f16 v14, v30, v15, v25 op_sel:[1,0,0]
v_pk_fma_f16 v24, v30, v16, v28 op_sel:[1,0,0]
v_pk_fma_f16 v25, v34, v15, v29 op_sel:[1,0,0]
v_pk_fma_f16 v26, v38, v15, v32 op_sel:[1,0,0]
v_pk_fma_f16 v23, v34, v16, v23 op_sel:[1,0,0]
v_pk_fma_f16 v28, v38, v16, v33 op_sel:[1,0,0]
v_pk_fma_f16 v11, v19, v15, v11 op_sel:[1,0,0]
v_pk_fma_f16 v12, v19, v16, v12 op_sel:[1,0,0]
ds_read2st64_b64 v[42:45], v5 offset0:11 offset1:12
ds_read2st64_b64 v[46:49], v5 offset0:13 offset1:14
v_pk_fma_f16 v9, v27, v17, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v27, v18, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v40, v20, v17, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v31, v17, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v31, v18, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v35, v17, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v35, v18, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v39, v17, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v39, v18, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v41, v20, v18, v12 op_sel_hi:[0,1,1]
ds_read2_b64 v[11:14], v0 offset0:24 offset1:25
ds_read2_b64 v[15:18], v0 offset0:26 offset1:27
ds_read2_b64 v[23:26], v0 offset0:28 offset1:29
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v40, v20, v42, v40 op_sel:[1,0,0]
v_pk_fma_f16 v9, v27, v42, v9 op_sel:[1,0,0]
v_pk_fma_f16 v19, v27, v43, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v20, v43, v41 op_sel:[1,0,0]
v_pk_fma_f16 v50, v31, v42, v29 op_sel:[1,0,0]
v_pk_fma_f16 v51, v31, v43, v30 op_sel:[1,0,0]
v_pk_fma_f16 v58, v39, v42, v34 op_sel:[1,0,0]
v_pk_fma_f16 v39, v39, v43, v36 op_sel:[1,0,0]
v_pk_fma_f16 v52, v35, v42, v32 op_sel:[1,0,0]
v_pk_fma_f16 v53, v35, v43, v33 op_sel:[1,0,0]
ds_read_b128 v[27:30], v0 offset:240
ds_read2st64_b64 v[31:34], v5 offset0:15 offset1:16
ds_read2st64_b64 v[35:38], v5 offset0:17 offset1:18
v_pk_fma_f16 v9, v21, v44, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v21, v45, v19 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v39, v17, v45, v39 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v40, v25, v44, v40 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v25, v45, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v41, v56, v44, v50 op_sel_hi:[0,1,1]
v_pk_fma_f16 v42, v56, v45, v51 op_sel_hi:[0,1,1]
v_pk_fma_f16 v43, v13, v44, v52 op_sel_hi:[0,1,1]
v_pk_fma_f16 v51, v17, v44, v58 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v13, v45, v53 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v21, v46, v9 op_sel:[1,0,0]
v_pk_fma_f16 v19, v21, v47, v19 op_sel:[1,0,0]
v_pk_fma_f16 v21, v56, v46, v41 op_sel:[1,0,0]
v_pk_fma_f16 v20, v25, v47, v20 op_sel:[1,0,0]
v_pk_fma_f16 v41, v56, v47, v42 op_sel:[1,0,0]
v_pk_fma_f16 v42, v13, v46, v43 op_sel:[1,0,0]
v_pk_fma_f16 v43, v13, v47, v50 op_sel:[1,0,0]
v_pk_fma_f16 v44, v17, v46, v51 op_sel:[1,0,0]
v_pk_fma_f16 v39, v17, v47, v39 op_sel:[1,0,0]
v_pk_fma_f16 v40, v25, v46, v40 op_sel:[1,0,0]
v_pk_fma_f16 v9, v22, v48, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v22, v49, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v57, v48, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v26, v49, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v47, v57, v49, v41 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v14, v48, v42 op_sel_hi:[0,1,1]
v_pk_fma_f16 v52, v18, v48, v44 op_sel_hi:[0,1,1]
v_pk_fma_f16 v51, v14, v49, v43 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v18, v49, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v48, v26, v48, v40 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v9, v22, v31, v9 op_sel:[1,0,0]
v_pk_fma_f16 v19, v22, v32, v19 op_sel:[1,0,0]
v_pk_fma_f16 v49, v14, v32, v51 op_sel:[1,0,0]
v_pk_fma_f16 v51, v18, v32, v53 op_sel:[1,0,0]
v_pk_fma_f16 v22, v57, v32, v47 op_sel:[1,0,0]
v_pk_fma_f16 v47, v14, v31, v50 op_sel:[1,0,0]
v_pk_fma_f16 v50, v18, v31, v52 op_sel:[1,0,0]
v_pk_fma_f16 v21, v57, v31, v21 op_sel:[1,0,0]
v_pk_fma_f16 v31, v26, v31, v48 op_sel:[1,0,0]
v_pk_fma_f16 v20, v26, v32, v20 op_sel:[1,0,0]
ds_read2st64_b64 v[39:42], v5 offset0:19 offset1:20
ds_read2st64_b64 v[43:46], v5 offset0:21 offset1:22
v_pk_fma_f16 v9, v54, v33, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v48, v54, v34, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v52, v11, v33, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v47, v15, v33, v47 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v11, v34, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v49, v15, v34, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v23, v33, v50 op_sel_hi:[0,1,1]
v_pk_fma_f16 v51, v23, v34, v51 op_sel_hi:[0,1,1]
v_pk_fma_f16 v58, v27, v33, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v59, v27, v34, v20 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v47, v15, v35, v47 op_sel:[1,0,0]
v_pk_fma_f16 v15, v15, v36, v49 op_sel:[1,0,0]
v_pk_fma_f16 v49, v23, v35, v50 op_sel:[1,0,0]
v_pk_fma_f16 v9, v54, v35, v9 op_sel:[1,0,0]
v_pk_fma_f16 v52, v11, v35, v52 op_sel:[1,0,0]
v_pk_fma_f16 v35, v27, v35, v58 op_sel:[1,0,0]
v_pk_fma_f16 v11, v11, v36, v53 op_sel:[1,0,0]
v_pk_fma_f16 v23, v23, v36, v51 op_sel:[1,0,0]
v_pk_fma_f16 v27, v27, v36, v59 op_sel:[1,0,0]
v_pk_fma_f16 v48, v54, v36, v48 op_sel:[1,0,0]
v_pk_fma_f16 v9, v55, v37, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v12, v38, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v16, v38, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v24, v38, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v55, v38, v48 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v28, v38, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v48, v12, v37, v52 op_sel_hi:[0,1,1]
v_pk_fma_f16 v47, v16, v37, v47 op_sel_hi:[0,1,1]
v_pk_fma_f16 v49, v24, v37, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v28, v37, v35 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v9, v55, v39, v9 op_sel:[1,0,0]
v_pk_fma_f16 v11, v12, v40, v11 op_sel:[1,0,0]
v_pk_fma_f16 v15, v16, v40, v15 op_sel:[1,0,0]
v_pk_fma_f16 v23, v24, v40, v23 op_sel:[1,0,0]
v_pk_fma_f16 v27, v28, v40, v27 op_sel:[1,0,0]
v_pk_fma_f16 v37, v12, v39, v48 op_sel:[1,0,0]
v_pk_fma_f16 v12, v16, v39, v47 op_sel:[1,0,0]
v_pk_fma_f16 v16, v24, v39, v49 op_sel:[1,0,0]
v_pk_fma_f16 v24, v28, v39, v35 op_sel:[1,0,0]
v_pk_fma_f16 v36, v55, v40, v36 op_sel:[1,0,0]
v_pk_fma_f16 v9, v56, v41, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v47, v13, v41, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v13, v42, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v17, v41, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v56, v42, v36 op_sel_hi:[0,1,1]
ds_read_b128 v[19:22], v0 offset:336
ds_read_b128 v[31:34], v0 offset:352
v_pk_fma_f16 v15, v17, v42, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v25, v41, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v25, v42, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v29, v41, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v29, v42, v27 op_sel_hi:[0,1,1]
ds_read2st64_b64 v[35:38], v5 offset0:23 offset1:24
ds_read2st64_b64 v[39:42], v5 offset0:25 offset1:26
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v11, v13, v44, v11 op_sel:[1,0,0]
v_pk_fma_f16 v47, v13, v43, v47 op_sel:[1,0,0]
v_pk_fma_f16 v9, v56, v43, v9 op_sel:[1,0,0]
v_pk_fma_f16 v13, v17, v44, v15 op_sel:[1,0,0]
v_pk_fma_f16 v15, v25, v43, v16 op_sel:[1,0,0]
v_pk_fma_f16 v16, v25, v44, v23 op_sel:[1,0,0]
v_pk_fma_f16 v12, v17, v43, v12 op_sel:[1,0,0]
v_pk_fma_f16 v23, v29, v44, v27 op_sel:[1,0,0]
v_pk_fma_f16 v17, v29, v43, v24 op_sel:[1,0,0]
v_pk_fma_f16 v28, v56, v44, v28 op_sel:[1,0,0]
v_pk_fma_f16 v25, v14, v45, v47 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v14, v46, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v57, v45, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v18, v45, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v57, v46, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v18, v46, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v30, v45, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v26, v45, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v26, v46, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v51, v30, v46, v23 op_sel_hi:[0,1,1]
ds_read_b128 v[43:46], v0 offset:368
ds_read_b128 v[47:50], v0 offset:384
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v54, v14, v35, v25 op_sel:[1,0,0]
v_pk_fma_f16 v55, v14, v36, v11 op_sel:[1,0,0]
ds_read_b128 v[11:14], v0 offset:400
v_pk_fma_f16 v29, v30, v35, v29 op_sel:[1,0,0]
v_pk_fma_f16 v9, v57, v35, v9 op_sel:[1,0,0]
v_pk_fma_f16 v27, v18, v35, v27 op_sel:[1,0,0]
v_pk_fma_f16 v28, v18, v36, v28 op_sel:[1,0,0]
v_pk_fma_f16 v30, v30, v36, v51 op_sel:[1,0,0]
v_pk_fma_f16 v53, v57, v36, v24 op_sel:[1,0,0]
v_pk_fma_f16 v56, v26, v35, v15 op_sel:[1,0,0]
v_pk_fma_f16 v57, v26, v36, v16 op_sel:[1,0,0]
ds_read2st64_b64 v[15:18], v5 offset0:27 offset1:28
ds_read2st64_b64 v[23:26], v5 offset0:29 offset1:30
v_pk_fma_f16 v9, v19, v37, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v19, v38, v53 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v31, v37, v54 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v31, v38, v55 op_sel_hi:[0,1,1]
ds_read_b64 v[51:52], v0 offset:416
s_waitcnt lgkmcnt(6)
v_pk_fma_f16 v9, v19, v39, v9 op_sel:[1,0,0]
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v27, v43, v37, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v43, v38, v28 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v54, v47, v37, v56 op_sel_hi:[0,1,1]
v_pk_fma_f16 v55, v47, v38, v57 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v29, v11, v37, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v11, v38, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v19, v40, v35 op_sel:[1,0,0]
v_pk_fma_f16 v35, v31, v39, v36 op_sel:[1,0,0]
v_pk_fma_f16 v36, v31, v40, v53 op_sel:[1,0,0]
v_pk_fma_f16 v37, v47, v39, v54 op_sel:[1,0,0]
v_pk_fma_f16 v28, v43, v40, v28 op_sel:[1,0,0]
v_pk_fma_f16 v38, v47, v40, v55 op_sel:[1,0,0]
v_pk_fma_f16 v27, v43, v39, v27 op_sel:[1,0,0]
v_pk_fma_f16 v29, v11, v39, v29 op_sel:[1,0,0]
v_pk_fma_f16 v30, v11, v40, v30 op_sel:[1,0,0]
v_pk_fma_f16 v9, v20, v41, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v20, v42, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v32, v41, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v54, v32, v42, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v55, v44, v41, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v57, v48, v41, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v56, v44, v42, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v58, v48, v42, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v41, v12, v41, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v42, v12, v42, v30 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v9, v20, v15, v9 op_sel:[1,0,0]
v_pk_fma_f16 v19, v20, v16, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v32, v15, v53 op_sel:[1,0,0]
v_pk_fma_f16 v53, v32, v16, v54 op_sel:[1,0,0]
v_pk_fma_f16 v54, v44, v15, v55 op_sel:[1,0,0]
v_pk_fma_f16 v55, v44, v16, v56 op_sel:[1,0,0]
v_pk_fma_f16 v56, v48, v15, v57 op_sel:[1,0,0]
v_pk_fma_f16 v15, v12, v15, v41 op_sel:[1,0,0]
v_pk_fma_f16 v57, v48, v16, v58 op_sel:[1,0,0]
v_pk_fma_f16 v16, v12, v16, v42 op_sel:[1,0,0]
ds_read2st64_b64 v[27:30], v5 offset0:31 offset1:32
ds_read2st64_b64 v[35:38], v5 offset0:33 offset1:34
ds_read_b64 v[39:40], v5 offset:17920
v_pk_fma_f16 v9, v21, v17, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v13, v17, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v41, v33, v18, v53 op_sel_hi:[0,1,1]
v_pk_fma_f16 v42, v45, v17, v54 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v45, v18, v55 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v21, v18, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v33, v17, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v54, v49, v17, v56 op_sel_hi:[0,1,1]
v_pk_fma_f16 v55, v49, v18, v57 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v13, v18, v16 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v15, v13, v23, v15 op_sel:[1,0,0]
v_pk_fma_f16 v9, v21, v23, v9 op_sel:[1,0,0]
v_pk_fma_f16 v17, v21, v24, v19 op_sel:[1,0,0]
v_pk_fma_f16 v18, v33, v23, v20 op_sel:[1,0,0]
v_pk_fma_f16 v13, v13, v24, v16 op_sel:[1,0,0]
v_pk_fma_f16 v19, v33, v24, v41 op_sel:[1,0,0]
v_pk_fma_f16 v20, v45, v23, v42 op_sel:[1,0,0]
v_pk_fma_f16 v21, v45, v24, v53 op_sel:[1,0,0]
v_pk_fma_f16 v33, v49, v23, v54 op_sel:[1,0,0]
v_pk_fma_f16 v41, v49, v24, v55 op_sel:[1,0,0]
v_pk_fma_f16 v16, v22, v26, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v34, v25, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v34, v26, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v46, v25, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v46, v26, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v22, v25, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v50, v25, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v14, v25, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v14, v26, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v50, v26, v41 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v9, v22, v27, v9 op_sel:[1,0,0]
v_pk_fma_f16 v16, v22, v28, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v14, v27, v15 op_sel:[1,0,0]
v_pk_fma_f16 v13, v14, v28, v13 op_sel:[1,0,0]
v_pk_fma_f16 v17, v34, v27, v17 op_sel:[1,0,0]
v_pk_fma_f16 v18, v34, v28, v18 op_sel:[1,0,0]
v_pk_fma_f16 v19, v46, v27, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v46, v28, v20 op_sel:[1,0,0]
v_pk_fma_f16 v21, v50, v27, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v50, v28, v23 op_sel:[1,0,0]
v_pk_fma_f16 v14, v31, v30, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v43, v29, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v43, v30, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v47, v29, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v47, v30, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v11, v29, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v31, v29, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v51, v29, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v51, v30, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v11, v30, v22 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v14, v31, v36, v14 op_sel:[1,0,0]
v_pk_fma_f16 v9, v31, v35, v9 op_sel:[1,0,0]
v_pk_fma_f16 v16, v43, v35, v16 op_sel:[1,0,0]
v_pk_fma_f16 v17, v43, v36, v17 op_sel:[1,0,0]
v_pk_fma_f16 v20, v11, v35, v20 op_sel:[1,0,0]
v_pk_fma_f16 v11, v11, v36, v21 op_sel:[1,0,0]
v_pk_fma_f16 v18, v47, v35, v18 op_sel:[1,0,0]
v_pk_fma_f16 v19, v47, v36, v19 op_sel:[1,0,0]
v_pk_fma_f16 v15, v51, v35, v15 op_sel:[1,0,0]
v_pk_fma_f16 v13, v51, v36, v13 op_sel:[1,0,0]
v_pk_fma_f16 v9, v32, v37, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v32, v38, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v12, v37, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v52, v37, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v52, v38, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v44, v37, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v48, v38, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v44, v38, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v48, v37, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v12, v38, v11 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v20, v32, v40, v14 op_sel:[1,0,0]
v_pk_fma_f16 v19, v44, v39, v16 op_sel:[1,0,0]
v_pk_fma_f16 v18, v44, v40, v17 op_sel:[1,0,0]
v_pk_fma_f16 v21, v32, v39, v9 op_sel:[1,0,0]
v_pk_fma_f16 v17, v48, v39, v22 op_sel:[1,0,0]
v_pk_fma_f16 v16, v48, v40, v23 op_sel:[1,0,0]
v_pk_fma_f16 v15, v12, v39, v24 op_sel:[1,0,0]
v_pk_fma_f16 v14, v12, v40, v11 op_sel:[1,0,0]
v_pk_fma_f16 v13, v52, v39, v25 op_sel:[1,0,0]
v_pk_fma_f16 v12, v52, v40, v26 op_sel:[1,0,0]
s_cbranch_scc1 BB61_8
BB61_3:
v_mov_b32_e32 v9, 0
s_barrier
s_and_saveexec_b32 s7, s2
s_cbranch_execz BB61_5
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[22:23], 1, v[10:11]
v_add_co_u32 v22, s1, s10, v22
v_add_co_ci_u32_e64 v23, s1, s11, v23, s1
global_load_ushort v9, v[22:23], off
BB61_5:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt vmcnt(0)
ds_write_b16 v2, v9
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz BB61_2
v_mov_b32_e32 v9, 0
s_and_saveexec_b32 s14, s0
s_cbranch_execz BB61_1
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[22:23], 1, v[8:9]
v_add_co_u32 v22, s1, s10, v22
v_add_co_ci_u32_e64 v23, s1, s11, v23, s1
global_load_ushort v9, v[22:23], off
s_branch BB61_1
BB61_8:
v_lshlrev_b32_e32 v0, 1, v3
s_mulk_i32 s6, 0xa00
s_clause 0x1
global_load_dword v6, v0, s[4:5]
global_load_dword v7, v0, s[4:5] offset:4
v_mad_u32_u24 v0, 0x500, v1, s6
v_or_b32_e32 v0, v0, v3
v_add_nc_u32_e32 v2, 0x400, v0
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v4, 0x402, v0
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 1, v[2:3]
v_add_co_u32 v0, vcc_lo, s8, v0
v_lshlrev_b64 v[4:5], 1, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
s_waitcnt vmcnt(1)
v_pk_add_f16 v8, v6, v21
s_waitcnt vmcnt(0)
v_pk_add_f16 v9, v7, v20
v_pk_add_f16 v10, v6, v19
v_pk_add_f16 v11, v7, v18
v_pk_add_f16 v17, v6, v17
v_pk_add_f16 v15, v6, v15
v_pk_add_f16 v14, v7, v14
v_pk_add_f16 v6, v6, v13
v_pk_add_f16 v16, v7, v16
v_pk_add_f16 v7, v7, v12
v_pk_max_f16 v8, v8, 0
v_pk_max_f16 v9, v9, 0
v_pk_max_f16 v10, v10, 0
v_pk_max_f16 v11, v11, 0
v_pk_max_f16 v12, v17, 0
v_pk_max_f16 v13, v16, 0
v_pk_max_f16 v15, v15, 0
v_pk_max_f16 v14, v14, 0
v_pk_max_f16 v6, v6, 0
v_pk_max_f16 v7, v7, 0
global_store_dword v[0:1], v8, off
global_store_dword v[0:1], v9, off offset:4
global_store_dword v[0:1], v10, off offset:512
global_store_dword v[0:1], v11, off offset:516
global_store_dword v[0:1], v12, off offset:1024
global_store_dword v[0:1], v13, off offset:1028
global_store_dword v[0:1], v15, off offset:1536
global_store_dword v[0:1], v14, off offset:1540
global_store_dword v[2:3], v6, off
global_store_dword v[4:5], v7, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_nn_relu_7_kernel0
.amdhsa_group_segment_fixed_size 18936
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 60
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end61:
.size tvmgen_default_fused_nn_conv2d_add_nn_relu_7_kernel0, .Lfunc_end61-tvmgen_default_fused_nn_conv2d_add_nn_relu_7_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_nn_relu_8_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_nn_relu_8_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_nn_relu_8_kernel0:
s_clause 0x3
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[4:5], s[4:5], 0x18
v_lshlrev_b32_e32 v22, 1, v0
v_lshrrev_b32_e32 v20, 5, v0
s_mul_i32 s1, s6, 0xc800
v_lshlrev_b32_e32 v23, 2, v0
s_mov_b32 s0, 0x8000
v_and_b32_e32 v21, 62, v22
v_lshl_add_u32 v1, v20, 10, s1
v_mul_u32_u24_e32 v2, 0x140, v20
v_cmp_gt_i32_e32 vcc_lo, 0xc0, v0
v_or_b32_e32 v25, s0, v23
v_mov_b32_e32 v0, 0
v_or_b32_e32 v24, v1, v21
v_lshl_or_b32 v26, v2, 1, s0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v19, 0
s_mov_b32 s1, 0
s_movk_i32 s7, 0x5000
s_movk_i32 s12, 0x4000
s_movk_i32 s13, 0x7800
BB62_1:
v_lshl_add_u32 v27, s1, 6, v24
v_lshl_or_b32 v29, s1, 14, v22
v_ashrrev_i32_e32 v28, 31, v27
v_ashrrev_i32_e32 v30, 31, v29
v_lshlrev_b64 v[27:28], 1, v[27:28]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v31, s0, s8, v27
v_add_co_ci_u32_e64 v32, s0, s9, v28, s0
v_lshlrev_b64 v[27:28], 1, v[29:30]
v_add_co_u32 v29, s0, s7, v31
v_add_co_ci_u32_e64 v30, s0, 0, v32, s0
v_add_co_u32 v33, s0, 0xa000, v31
v_add_co_ci_u32_e64 v34, s0, 0, v32, s0
v_add_co_u32 v35, s0, 0xf000, v31
v_add_co_ci_u32_e64 v36, s0, 0, v32, s0
v_add_co_u32 v37, s0, 0x14000, v31
v_add_co_ci_u32_e64 v38, s0, 0, v32, s0
v_add_co_u32 v27, s0, s10, v27
v_add_co_ci_u32_e64 v28, s0, s11, v28, s0
s_clause 0x4
global_load_dword v39, v[31:32], off
global_load_dword v40, v[29:30], off
global_load_dword v41, v[33:34], off
global_load_dword v42, v[35:36], off
global_load_dword v43, v[37:38], off
s_clause 0x1
global_load_dword v44, v[27:28], off
global_load_dword v45, v[27:28], off offset:1280
v_add_co_u32 v29, s0, 0x800, v27
v_add_co_ci_u32_e64 v30, s0, 0, v28, s0
v_add_co_u32 v31, s0, 0x1000, v27
v_add_co_ci_u32_e64 v32, s0, 0, v28, s0
v_add_co_u32 v33, s0, 0x1800, v27
v_add_co_ci_u32_e64 v34, s0, 0, v28, s0
v_add_co_u32 v35, s0, 0x2000, v27
v_add_co_ci_u32_e64 v36, s0, 0, v28, s0
v_add_co_u32 v37, s0, 0x2800, v27
v_add_co_ci_u32_e64 v38, s0, 0, v28, s0
s_clause 0x7
global_load_dword v46, v[29:30], off offset:512
global_load_dword v47, v[29:30], off offset:1792
global_load_dword v48, v[31:32], off offset:1024
global_load_dword v49, v[33:34], off offset:256
global_load_dword v50, v[33:34], off offset:1536
global_load_dword v51, v[35:36], off offset:768
global_load_dword v52, v[37:38], off
global_load_dword v53, v[37:38], off offset:1280
v_add_co_u32 v29, s0, 0x3000, v27
v_add_co_ci_u32_e64 v30, s0, 0, v28, s0
v_add_co_u32 v31, s0, 0x3800, v27
v_add_co_ci_u32_e64 v32, s0, 0, v28, s0
v_add_co_u32 v33, s0, s12, v27
v_add_co_ci_u32_e64 v34, s0, 0, v28, s0
v_add_co_u32 v35, s0, 0x4800, v27
v_add_co_ci_u32_e64 v36, s0, 0, v28, s0
v_add_co_u32 v37, s0, s7, v27
v_add_co_ci_u32_e64 v38, s0, 0, v28, s0
s_clause 0x7
global_load_dword v54, v[29:30], off offset:512
global_load_dword v55, v[29:30], off offset:1792
global_load_dword v56, v[31:32], off offset:1024
global_load_dword v57, v[33:34], off offset:256
global_load_dword v58, v[33:34], off offset:1536
global_load_dword v59, v[35:36], off offset:768
global_load_dword v60, v[37:38], off
global_load_dword v61, v[37:38], off offset:1280
v_add_co_u32 v29, s0, 0x5800, v27
v_add_co_ci_u32_e64 v30, s0, 0, v28, s0
v_add_co_u32 v31, s0, 0x6000, v27
v_add_co_ci_u32_e64 v32, s0, 0, v28, s0
v_add_co_u32 v33, s0, 0x6800, v27
v_add_co_ci_u32_e64 v34, s0, 0, v28, s0
v_add_co_u32 v35, s0, 0x7000, v27
v_add_co_ci_u32_e64 v36, s0, 0, v28, s0
v_add_co_u32 v37, s0, s13, v27
v_add_co_ci_u32_e64 v38, s0, 0, v28, s0
s_clause 0x6
global_load_dword v62, v[29:30], off offset:512
global_load_dword v29, v[29:30], off offset:1792
global_load_dword v30, v[31:32], off offset:1024
global_load_dword v31, v[33:34], off offset:256
global_load_dword v32, v[33:34], off offset:1536
global_load_dword v33, v[35:36], off offset:768
global_load_dword v34, v[37:38], off
s_waitcnt vmcnt(0)
s_barrier
ds_write2st64_b32 v23, v44, v45 offset1:5
ds_write2st64_b32 v25, v39, v40 offset1:5
ds_write2st64_b32 v25, v41, v42 offset0:10 offset1:15
ds_write_b32 v25, v43 offset:5120
ds_write2st64_b32 v23, v46, v47 offset0:10 offset1:15
ds_write2st64_b32 v23, v48, v49 offset0:20 offset1:25
ds_write2st64_b32 v23, v50, v51 offset0:30 offset1:35
ds_write2st64_b32 v23, v52, v53 offset0:40 offset1:45
ds_write2st64_b32 v23, v54, v55 offset0:50 offset1:55
ds_write2st64_b32 v23, v56, v57 offset0:60 offset1:65
ds_write2st64_b32 v23, v58, v59 offset0:70 offset1:75
ds_write2st64_b32 v23, v60, v61 offset0:80 offset1:85
ds_write2st64_b32 v23, v62, v29 offset0:90 offset1:95
ds_write2st64_b32 v23, v30, v31 offset0:100 offset1:105
ds_write2st64_b32 v23, v32, v33 offset0:110 offset1:115
ds_write_b32 v23, v34 offset:30720
s_and_saveexec_b32 s14, vcc_lo
s_cbranch_execz BB62_3
v_add_co_u32 v27, s0, s13, v27
v_add_co_ci_u32_e64 v28, s0, 0, v28, s0
global_load_ushort v29, v[27:28], off offset:1280
s_waitcnt vmcnt(0)
global_load_short_d16_hi v29, v[27:28], off offset:1282
s_waitcnt vmcnt(0)
ds_write_b32 v23, v29 offset:32000
BB62_3:
s_or_b32 exec_lo, exec_lo, s14
v_mov_b32_e32 v27, v26
s_mov_b32 s0, 0
s_waitcnt lgkmcnt(0)
s_barrier
BB62_4:
v_or_b32_e32 v38, s0, v21
ds_read2_b64 v[28:31], v27 offset1:16
ds_read2_b64 v[32:35], v27 offset0:32 offset1:48
ds_read_b64 v[36:37], v27 offset:512
v_add_nc_u32_e32 v27, 8, v27
s_addk_i32 s0, 0x400
v_lshlrev_b32_e32 v44, 1, v38
s_cmp_lg_u32 s0, s12
ds_read2_b32 v[38:39], v44 offset1:32
ds_read2_b32 v[40:41], v44 offset0:64 offset1:96
v_add_nc_u32_e32 v52, 0x400, v44
ds_read2_b32 v[42:43], v44 offset0:128 offset1:160
ds_read2_b32 v[44:45], v44 offset0:192 offset1:224
ds_read2_b32 v[46:47], v52 offset1:32
ds_read2_b32 v[48:49], v52 offset0:64 offset1:96
ds_read2_b32 v[50:51], v52 offset0:128 offset1:160
ds_read2_b32 v[52:53], v52 offset0:192 offset1:224
s_waitcnt lgkmcnt(7)
v_pk_fma_f16 v17, v28, v38, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v28, v39, v19 op_sel:[0,1,0] op_sel_hi:[0,0,1]
s_waitcnt lgkmcnt(6)
v_pk_fma_f16 v18, v28, v40, v18 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v16, v28, v41, v16 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v15, v30, v38, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v30, v39, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v30, v40, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v30, v41, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v32, v38, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v32, v39, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v32, v40, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v32, v41, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v34, v38, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v34, v39, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v34, v40, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v34, v41, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v36, v38, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v36, v39, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v36, v40, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v36, v41, v0 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v17, v28, v42, v17 op_sel:[1,0,0]
v_pk_fma_f16 v19, v28, v43, v19 op_sel:[1,1,0] op_sel_hi:[1,0,1]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v18, v28, v44, v18 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v16, v28, v45, v16 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v15, v30, v42, v15 op_sel:[1,0,0]
v_pk_fma_f16 v11, v30, v43, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v30, v44, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v30, v45, v9 op_sel:[1,0,0]
v_pk_fma_f16 v14, v32, v42, v14 op_sel:[1,0,0]
v_pk_fma_f16 v8, v32, v43, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v32, v44, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v32, v45, v6 op_sel:[1,0,0]
v_pk_fma_f16 v13, v34, v42, v13 op_sel:[1,0,0]
v_pk_fma_f16 v5, v34, v43, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v34, v44, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v34, v45, v3 op_sel:[1,0,0]
v_pk_fma_f16 v12, v36, v42, v12 op_sel:[1,0,0]
v_pk_fma_f16 v2, v36, v43, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v36, v44, v1 op_sel:[1,0,0]
v_pk_fma_f16 v0, v36, v45, v0 op_sel:[1,0,0]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v17, v29, v46, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v29, v47, v19 op_sel:[0,1,0] op_sel_hi:[0,0,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v18, v29, v48, v18 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v16, v29, v49, v16 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v15, v31, v46, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v31, v47, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v31, v48, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v31, v49, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v33, v46, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v33, v47, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v33, v48, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v33, v49, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v35, v46, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v35, v47, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v35, v48, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v35, v49, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v37, v46, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v37, v47, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v37, v48, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v37, v49, v0 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v17, v29, v50, v17 op_sel:[1,0,0]
v_pk_fma_f16 v19, v29, v51, v19 op_sel:[1,1,0] op_sel_hi:[1,0,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v18, v29, v52, v18 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v16, v29, v53, v16 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v15, v31, v50, v15 op_sel:[1,0,0]
v_pk_fma_f16 v11, v31, v51, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v31, v52, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v31, v53, v9 op_sel:[1,0,0]
v_pk_fma_f16 v14, v33, v50, v14 op_sel:[1,0,0]
v_pk_fma_f16 v8, v33, v51, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v33, v52, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v33, v53, v6 op_sel:[1,0,0]
v_pk_fma_f16 v13, v35, v50, v13 op_sel:[1,0,0]
v_pk_fma_f16 v5, v35, v51, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v35, v52, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v35, v53, v3 op_sel:[1,0,0]
v_pk_fma_f16 v12, v37, v50, v12 op_sel:[1,0,0]
v_pk_fma_f16 v2, v37, v51, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v37, v52, v1 op_sel:[1,0,0]
v_pk_fma_f16 v0, v37, v53, v0 op_sel:[1,0,0]
s_cbranch_scc1 BB62_4
s_add_i32 s1, s1, 1
s_cmp_eq_u32 s1, 16
s_cbranch_scc0 BB62_1
v_lshlrev_b32_e32 v22, 1, v21
s_mulk_i32 s6, 0x3200
v_mov_b32_e32 v37, 0xffff
v_mad_u32_u24 v20, 0x500, v20, s6
s_clause 0x6
global_load_dword v30, v22, s[4:5]
global_load_ushort v31, v22, s[4:5] offset:128
global_load_ushort v32, v22, s[4:5] offset:256
global_load_ushort v33, v22, s[4:5] offset:386
global_load_ushort v34, v22, s[4:5] offset:384
global_load_ushort v35, v22, s[4:5] offset:258
global_load_ushort v36, v22, s[4:5] offset:130
v_or_b32_e32 v20, v20, v21
v_add_nc_u32_e32 v22, 0x400, v20
v_ashrrev_i32_e32 v21, 31, v20
v_add_nc_u32_e32 v24, 0x440, v20
v_add_nc_u32_e32 v26, 0x480, v20
v_add_nc_u32_e32 v28, 0x4c0, v20
v_ashrrev_i32_e32 v23, 31, v22
v_lshlrev_b64 v[20:21], 1, v[20:21]
v_ashrrev_i32_e32 v25, 31, v24
v_ashrrev_i32_e32 v27, 31, v26
v_ashrrev_i32_e32 v29, 31, v28
v_lshlrev_b64 v[22:23], 1, v[22:23]
v_add_co_u32 v20, vcc_lo, s2, v20
v_lshlrev_b64 v[24:25], 1, v[24:25]
v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo
v_lshlrev_b64 v[26:27], 1, v[26:27]
v_add_co_u32 v22, vcc_lo, s2, v22
v_lshlrev_b64 v[28:29], 1, v[28:29]
v_add_co_ci_u32_e32 v23, vcc_lo, s3, v23, vcc_lo
v_add_co_u32 v24, vcc_lo, s2, v24
v_add_co_ci_u32_e32 v25, vcc_lo, s3, v25, vcc_lo
v_add_co_u32 v26, vcc_lo, s2, v26
v_add_co_ci_u32_e32 v27, vcc_lo, s3, v27, vcc_lo
v_add_co_u32 v28, vcc_lo, s2, v28
v_add_co_ci_u32_e32 v29, vcc_lo, s3, v29, vcc_lo
s_waitcnt vmcnt(6)
v_pk_add_f16 v14, v30, v14
s_waitcnt vmcnt(5)
v_add_f16_sdwa v38, v31, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v31, v37, v31
s_waitcnt vmcnt(4)
v_add_f16_sdwa v39, v32, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v32, v37, v32
s_waitcnt vmcnt(2)
v_add_f16_sdwa v40, v34, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v34, v37, v34
s_waitcnt vmcnt(0)
v_lshl_or_b32 v31, v36, 16, v31
v_add_f16_e32 v16, v33, v16
v_lshl_or_b32 v32, v35, 16, v32
v_pk_add_f16 v13, v30, v13
v_lshl_or_b32 v33, v33, 16, v34
v_pk_add_f16 v12, v30, v12
v_pk_add_f16 v11, v31, v11
v_pk_add_f16 v10, v32, v10
v_pk_add_f16 v17, v30, v17
v_pk_add_f16 v9, v33, v9
v_pk_add_f16 v8, v31, v8
v_add_f16_e32 v19, v36, v19
v_pk_add_f16 v7, v32, v7
v_pk_add_f16 v15, v30, v15
v_add_f16_e32 v18, v35, v18
v_pk_add_f16 v6, v33, v6
v_pk_add_f16 v5, v31, v5
v_pk_add_f16 v4, v32, v4
v_pk_add_f16 v3, v33, v3
v_pk_add_f16 v2, v31, v2
v_pk_add_f16 v1, v32, v1
v_pk_add_f16 v0, v33, v0
v_max_f16_e32 v30, 0, v38
v_pk_max_f16 v14, v14, 0
v_pk_max_f16 v13, v13, 0
v_pk_max_f16 v12, v12, 0
v_pk_max_f16 v11, v11, 0
v_max_f16_e32 v37, 0, v39
v_pk_max_f16 v10, v10, 0
v_max_f16_e32 v38, 0, v40
v_pk_max_f16 v9, v9, 0
v_pk_max_f16 v17, v17, 0
v_pk_max_f16 v8, v8, 0
v_max_f16_e32 v19, 0, v19
v_pk_max_f16 v7, v7, 0
v_max_f16_e32 v18, 0, v18
v_max_f16_e32 v16, 0, v16
v_pk_max_f16 v15, v15, 0
global_store_short v[20:21], v30, off offset:128
global_store_short v[20:21], v37, off offset:256
global_store_short v[20:21], v38, off offset:384
global_store_dword v[20:21], v17, off
global_store_short v[20:21], v19, off offset:130
global_store_short v[20:21], v18, off offset:258
global_store_short v[20:21], v16, off offset:386
global_store_dword v[20:21], v15, off offset:512
global_store_dword v[20:21], v14, off offset:1024
global_store_dword v[20:21], v13, off offset:1536
global_store_dword v[22:23], v12, off
v_pk_max_f16 v6, v6, 0
v_pk_max_f16 v5, v5, 0
v_pk_max_f16 v4, v4, 0
v_pk_max_f16 v3, v3, 0
v_pk_max_f16 v2, v2, 0
v_pk_max_f16 v1, v1, 0
v_pk_max_f16 v0, v0, 0
global_store_dword v[20:21], v11, off offset:640
global_store_dword v[20:21], v10, off offset:768
global_store_dword v[20:21], v9, off offset:896
global_store_dword v[20:21], v8, off offset:1152
global_store_dword v[20:21], v7, off offset:1280
global_store_dword v[20:21], v6, off offset:1408
global_store_dword v[20:21], v5, off offset:1664
global_store_dword v[20:21], v4, off offset:1792
global_store_dword v[20:21], v3, off offset:1920
global_store_dword v[24:25], v2, off
global_store_dword v[26:27], v1, off
global_store_dword v[28:29], v0, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_nn_relu_8_kernel0
.amdhsa_group_segment_fixed_size 39168
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 63
.amdhsa_next_free_sgpr 15
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end62:
.size tvmgen_default_fused_nn_conv2d_add_nn_relu_8_kernel0, .Lfunc_end62-tvmgen_default_fused_nn_conv2d_add_nn_relu_8_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_nn_relu_9_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_nn_relu_9_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_nn_relu_9_kernel0:
s_clause 0x3
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[4:5], s[4:5], 0x18
v_lshlrev_b32_e32 v1, 1, v0
v_lshrrev_b32_e32 v20, 5, v0
s_ashr_i32 s1, s6, 1
s_mov_b32 s7, 0xc800
v_lshlrev_b32_e32 v2, 2, v0
s_mul_i32 s0, s1, s7
v_and_b32_e32 v21, 62, v1
v_lshl_add_u32 v1, v20, 10, s0
v_lshlrev_b32_e32 v25, 3, v0
v_or_b32_e32 v3, 2, v2
v_mul_u32_u24_e32 v4, 0x140, v20
s_mov_b32 s0, 0x8000
v_or_b32_e32 v22, v1, v21
v_or_b32_e32 v1, 1, v2
s_movk_i32 s12, 0x100
v_and_b32_e32 v28, 0xfe, v3
v_cmp_gt_i32_e32 vcc_lo, s12, v0
v_lshl_or_b32 v30, v4, 1, s0
v_and_b32_e32 v27, 0xfd, v1
v_or_b32_e32 v23, s0, v2
v_and_b32_e32 v24, 0xfc, v2
v_or_b32_e32 v29, 3, v2
v_and_b32_e32 v26, 0x1e00, v25
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v19, 0
s_lshl_b32 s6, s6, 8
s_movk_i32 s13, 0x5000
s_and_b32 s6, s6, s12
s_mov_b32 s12, 0
s_mov_b32 s14, 0xa000
s_mov_b32 s15, 0xf000
s_movk_i32 s16, 0x1000
s_movk_i32 s17, 0x2800
s_movk_i32 s18, 0x3800
s_movk_i32 s19, 0x6000
s_movk_i32 s20, 0x7800
s_mov_b32 s21, 0x8800
s_mov_b32 s22, 0xb000
s_mov_b32 s23, 0xd800
BB63_1:
s_lshl_b32 s0, s12, 15
v_or3_b32 v67, s0, v26, s6
v_or_b32_e32 v31, v67, v24
v_or_b32_e32 v33, v67, v28
v_ashrrev_i32_e32 v32, 31, v31
v_ashrrev_i32_e32 v34, 31, v33
v_lshlrev_b64 v[31:32], 1, v[31:32]
v_lshlrev_b64 v[35:36], 1, v[33:34]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v33, s0, s10, v31
v_add_co_ci_u32_e64 v34, s0, s11, v32, s0
v_add_co_u32 v31, s0, s10, v35
v_add_co_ci_u32_e64 v32, s0, s11, v36, s0
v_add_co_u32 v35, s0, s16, v33
v_add_co_ci_u32_e64 v36, s0, 0, v34, s0
v_add_co_u32 v37, s0, s16, v31
s_clause 0x1
global_load_ushort v43, v[33:34], off
global_load_ushort v44, v[31:32], off
v_add_co_ci_u32_e64 v38, s0, 0, v32, s0
v_add_co_u32 v39, s0, s17, v33
v_add_co_ci_u32_e64 v40, s0, 0, v34, s0
v_add_co_u32 v41, s0, s17, v31
v_add_co_ci_u32_e64 v42, s0, 0, v32, s0
v_add_co_u32 v45, s0, s18, v33
v_add_co_ci_u32_e64 v46, s0, 0, v34, s0
v_add_co_u32 v47, s0, s18, v31
v_add_co_ci_u32_e64 v48, s0, 0, v32, s0
v_add_co_u32 v49, s0, s13, v33
v_add_co_ci_u32_e64 v50, s0, 0, v34, s0
v_add_co_u32 v51, s0, s13, v31
v_add_co_ci_u32_e64 v52, s0, 0, v32, s0
v_add_co_u32 v53, s0, s19, v33
s_clause 0x7
global_load_ushort v57, v[35:36], off offset:1024
global_load_ushort v58, v[37:38], off offset:1024
global_load_ushort v39, v[39:40], off
global_load_ushort v40, v[41:42], off
global_load_ushort v41, v[45:46], off offset:1024
global_load_ushort v42, v[47:48], off offset:1024
global_load_ushort v45, v[49:50], off
global_load_ushort v46, v[51:52], off
v_add_co_ci_u32_e64 v54, s0, 0, v34, s0
v_add_co_u32 v55, s0, s19, v31
v_add_co_ci_u32_e64 v56, s0, 0, v32, s0
v_add_co_u32 v35, s0, s20, v33
v_add_co_ci_u32_e64 v36, s0, 0, v34, s0
v_add_co_u32 v37, s0, s20, v31
v_add_co_ci_u32_e64 v38, s0, 0, v32, s0
v_add_co_u32 v47, s0, s21, v33
v_add_co_ci_u32_e64 v48, s0, 0, v34, s0
v_add_co_u32 v49, s0, s21, v31
v_add_co_ci_u32_e64 v50, s0, 0, v32, s0
v_add_co_u32 v51, s0, s14, v33
v_add_co_ci_u32_e64 v52, s0, 0, v34, s0
v_add_co_u32 v59, s0, s14, v31
v_add_co_ci_u32_e64 v60, s0, 0, v32, s0
s_clause 0x7
global_load_ushort v53, v[53:54], off offset:1024
global_load_ushort v54, v[55:56], off offset:1024
global_load_ushort v55, v[35:36], off
global_load_ushort v56, v[37:38], off
global_load_ushort v47, v[47:48], off offset:1024
global_load_ushort v48, v[49:50], off offset:1024
global_load_ushort v49, v[51:52], off
global_load_ushort v50, v[59:60], off
v_add_co_u32 v35, s0, s22, v33
v_add_co_ci_u32_e64 v36, s0, 0, v34, s0
v_add_co_u32 v37, s0, s22, v31
v_add_co_ci_u32_e64 v38, s0, 0, v32, s0
v_add_co_u32 v51, s0, s7, v33
v_add_co_ci_u32_e64 v52, s0, 0, v34, s0
v_add_co_u32 v59, s0, s7, v31
v_add_co_ci_u32_e64 v60, s0, 0, v32, s0
v_add_co_u32 v61, s0, s23, v33
v_add_co_ci_u32_e64 v62, s0, 0, v34, s0
v_add_co_u32 v63, s0, s23, v31
v_add_co_ci_u32_e64 v64, s0, 0, v32, s0
s_clause 0x5
global_load_ushort v65, v[35:36], off offset:1024
global_load_ushort v66, v[37:38], off offset:1024
global_load_ushort v51, v[51:52], off
global_load_ushort v52, v[59:60], off
global_load_ushort v59, v[61:62], off offset:1024
global_load_ushort v60, v[63:64], off offset:1024
v_lshl_add_u32 v35, s12, 6, v22
v_or_b32_e32 v37, v67, v27
v_or_b32_sdwa v61, v67, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
v_ashrrev_i32_e32 v36, 31, v35
v_ashrrev_i32_e32 v38, 31, v37
v_ashrrev_i32_e32 v62, 31, v61
v_lshlrev_b64 v[35:36], 1, v[35:36]
v_add_co_u32 v63, s0, s8, v35
v_add_co_ci_u32_e64 v64, s0, s9, v36, s0
v_lshlrev_b64 v[35:36], 1, v[37:38]
v_lshlrev_b64 v[37:38], 1, v[61:62]
v_add_co_u32 v61, s0, s13, v63
v_add_co_ci_u32_e64 v62, s0, 0, v64, s0
v_add_co_u32 v67, s0, s14, v63
v_add_co_ci_u32_e64 v68, s0, 0, v64, s0
v_add_co_u32 v69, s0, s15, v63
v_add_co_ci_u32_e64 v70, s0, 0, v64, s0
v_add_co_u32 v71, s0, 0x14000, v63
v_add_co_ci_u32_e64 v72, s0, 0, v64, s0
v_add_co_u32 v35, s0, s10, v35
s_clause 0x4
global_load_dword v107, v[63:64], off
global_load_dword v108, v[61:62], off
global_load_dword v109, v[67:68], off
global_load_dword v110, v[69:70], off
global_load_dword v111, v[71:72], off
v_add_co_ci_u32_e64 v36, s0, s11, v36, s0
v_add_co_u32 v37, s0, s10, v37
v_add_co_ci_u32_e64 v38, s0, s11, v38, s0
v_add_co_u32 v61, s0, s16, v35
v_add_co_ci_u32_e64 v62, s0, 0, v36, s0
v_add_co_u32 v63, s0, s16, v37
v_add_co_ci_u32_e64 v64, s0, 0, v38, s0
v_add_co_u32 v67, s0, s17, v35
v_add_co_ci_u32_e64 v68, s0, 0, v36, s0
v_add_co_u32 v69, s0, s17, v37
v_add_co_ci_u32_e64 v70, s0, 0, v38, s0
v_add_co_u32 v71, s0, s18, v35
v_add_co_ci_u32_e64 v72, s0, 0, v36, s0
v_add_co_u32 v73, s0, s18, v37
v_add_co_ci_u32_e64 v74, s0, 0, v38, s0
v_add_co_u32 v75, s0, s13, v35
v_add_co_ci_u32_e64 v76, s0, 0, v36, s0
v_add_co_u32 v77, s0, s13, v37
v_add_co_ci_u32_e64 v78, s0, 0, v38, s0
v_add_co_u32 v79, s0, s19, v35
v_add_co_ci_u32_e64 v80, s0, 0, v36, s0
v_add_co_u32 v81, s0, s19, v37
v_add_co_ci_u32_e64 v82, s0, 0, v38, s0
v_add_co_u32 v83, s0, s20, v35
v_add_co_ci_u32_e64 v84, s0, 0, v36, s0
v_add_co_u32 v85, s0, s20, v37
v_add_co_ci_u32_e64 v86, s0, 0, v38, s0
v_add_co_u32 v87, s0, s21, v35
v_add_co_ci_u32_e64 v88, s0, 0, v36, s0
v_add_co_u32 v89, s0, s21, v37
v_add_co_ci_u32_e64 v90, s0, 0, v38, s0
v_add_co_u32 v91, s0, s14, v35
v_add_co_ci_u32_e64 v92, s0, 0, v36, s0
v_add_co_u32 v93, s0, s14, v37
v_add_co_ci_u32_e64 v94, s0, 0, v38, s0
v_add_co_u32 v95, s0, s22, v35
v_add_co_ci_u32_e64 v96, s0, 0, v36, s0
v_add_co_u32 v97, s0, s22, v37
v_add_co_ci_u32_e64 v98, s0, 0, v38, s0
v_add_co_u32 v99, s0, s7, v35
v_add_co_ci_u32_e64 v100, s0, 0, v36, s0
v_add_co_u32 v101, s0, s7, v37
v_add_co_ci_u32_e64 v102, s0, 0, v38, s0
v_add_co_u32 v103, s0, s23, v35
v_add_co_ci_u32_e64 v104, s0, 0, v36, s0
v_add_co_u32 v105, s0, s23, v37
v_add_co_ci_u32_e64 v106, s0, 0, v38, s0
s_waitcnt vmcnt(28)
global_load_short_d16_hi v43, v[35:36], off
s_waitcnt vmcnt(28)
global_load_short_d16_hi v44, v[37:38], off
s_waitcnt vmcnt(28)
global_load_short_d16_hi v57, v[61:62], off offset:1024
s_waitcnt vmcnt(28)
global_load_short_d16_hi v58, v[63:64], off offset:1024
s_waitcnt vmcnt(28)
global_load_short_d16_hi v39, v[67:68], off
s_waitcnt vmcnt(28)
global_load_short_d16_hi v40, v[69:70], off
s_waitcnt vmcnt(28)
global_load_short_d16_hi v41, v[71:72], off offset:1024
s_waitcnt vmcnt(28)
global_load_short_d16_hi v42, v[73:74], off offset:1024
s_waitcnt vmcnt(28)
global_load_short_d16_hi v45, v[75:76], off
s_waitcnt vmcnt(28)
global_load_short_d16_hi v46, v[77:78], off
s_waitcnt vmcnt(28)
global_load_short_d16_hi v53, v[79:80], off offset:1024
s_waitcnt vmcnt(28)
global_load_short_d16_hi v54, v[81:82], off offset:1024
s_waitcnt vmcnt(28)
global_load_short_d16_hi v55, v[83:84], off
s_waitcnt vmcnt(28)
global_load_short_d16_hi v56, v[85:86], off
s_waitcnt vmcnt(28)
global_load_short_d16_hi v47, v[87:88], off offset:1024
s_waitcnt vmcnt(28)
global_load_short_d16_hi v48, v[89:90], off offset:1024
s_waitcnt vmcnt(28)
global_load_short_d16_hi v49, v[91:92], off
s_waitcnt vmcnt(28)
global_load_short_d16_hi v50, v[93:94], off
s_waitcnt vmcnt(28)
global_load_short_d16_hi v65, v[95:96], off offset:1024
s_waitcnt vmcnt(28)
global_load_short_d16_hi v66, v[97:98], off offset:1024
s_waitcnt vmcnt(28)
global_load_short_d16_hi v51, v[99:100], off
s_waitcnt vmcnt(28)
global_load_short_d16_hi v52, v[101:102], off
s_waitcnt vmcnt(28)
global_load_short_d16_hi v59, v[103:104], off offset:1024
s_waitcnt vmcnt(28)
global_load_short_d16_hi v60, v[105:106], off offset:1024
s_waitcnt vmcnt(0)
s_barrier
ds_write2st64_b32 v23, v107, v108 offset1:5
ds_write2st64_b32 v23, v109, v110 offset0:10 offset1:15
ds_write_b32 v23, v111 offset:5120
ds_write2st64_b64 v25, v[43:44], v[57:58] offset1:5
ds_write2st64_b64 v25, v[39:40], v[41:42] offset0:10 offset1:15
ds_write2st64_b64 v25, v[45:46], v[53:54] offset0:20 offset1:25
ds_write2st64_b64 v25, v[55:56], v[47:48] offset0:30 offset1:35
ds_write2st64_b64 v25, v[49:50], v[65:66] offset0:40 offset1:45
ds_write2st64_b64 v25, v[51:52], v[59:60] offset0:50 offset1:55
s_and_saveexec_b32 s24, vcc_lo
s_cbranch_execz BB63_3
v_add_co_u32 v33, s0, s15, v33
v_add_co_ci_u32_e64 v34, s0, 0, v34, s0
v_add_co_u32 v31, s0, s15, v31
v_add_co_ci_u32_e64 v32, s0, 0, v32, s0
s_clause 0x1
global_load_ushort v33, v[33:34], off
global_load_ushort v34, v[31:32], off
v_add_co_u32 v31, s0, s15, v35
v_add_co_ci_u32_e64 v32, s0, 0, v36, s0
v_add_co_u32 v35, s0, s15, v37
v_add_co_ci_u32_e64 v36, s0, 0, v38, s0
s_waitcnt vmcnt(1)
global_load_short_d16_hi v33, v[31:32], off
s_waitcnt vmcnt(1)
global_load_short_d16_hi v34, v[35:36], off
s_waitcnt vmcnt(0)
ds_write_b64 v25, v[33:34] offset:30720
BB63_3:
s_or_b32 exec_lo, exec_lo, s24
v_mov_b32_e32 v31, v30
s_mov_b32 s0, 0
s_waitcnt lgkmcnt(0)
s_barrier
BB63_4:
v_or_b32_e32 v42, s0, v21
ds_read2_b64 v[32:35], v31 offset1:16
ds_read2_b64 v[36:39], v31 offset0:32 offset1:48
ds_read_b64 v[40:41], v31 offset:512
v_add_nc_u32_e32 v31, 8, v31
s_addk_i32 s0, 0x400
v_lshlrev_b32_e32 v48, 1, v42
s_cmpk_lg_i32 s0, 0x4000
ds_read2_b32 v[42:43], v48 offset1:32
ds_read2_b32 v[44:45], v48 offset0:64 offset1:96
v_add_nc_u32_e32 v56, 0x400, v48
ds_read2_b32 v[46:47], v48 offset0:128 offset1:160
ds_read2_b32 v[48:49], v48 offset0:192 offset1:224
ds_read2_b32 v[50:51], v56 offset1:32
ds_read2_b32 v[52:53], v56 offset0:64 offset1:96
ds_read2_b32 v[54:55], v56 offset0:128 offset1:160
ds_read2_b32 v[56:57], v56 offset0:192 offset1:224
s_waitcnt lgkmcnt(7)
v_pk_fma_f16 v17, v32, v42, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v32, v43, v19 op_sel:[0,1,0] op_sel_hi:[0,0,1]
s_waitcnt lgkmcnt(6)
v_pk_fma_f16 v18, v32, v44, v18 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v16, v32, v45, v16 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v15, v34, v42, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v34, v43, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v34, v44, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v34, v45, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v36, v42, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v36, v43, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v36, v44, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v36, v45, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v38, v42, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v38, v43, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v38, v44, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v38, v45, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v40, v42, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v40, v43, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v40, v44, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v40, v45, v0 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v17, v32, v46, v17 op_sel:[1,0,0]
v_pk_fma_f16 v19, v32, v47, v19 op_sel:[1,1,0] op_sel_hi:[1,0,1]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v18, v32, v48, v18 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v16, v32, v49, v16 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v15, v34, v46, v15 op_sel:[1,0,0]
v_pk_fma_f16 v11, v34, v47, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v34, v48, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v34, v49, v9 op_sel:[1,0,0]
v_pk_fma_f16 v14, v36, v46, v14 op_sel:[1,0,0]
v_pk_fma_f16 v8, v36, v47, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v36, v48, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v36, v49, v6 op_sel:[1,0,0]
v_pk_fma_f16 v13, v38, v46, v13 op_sel:[1,0,0]
v_pk_fma_f16 v5, v38, v47, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v38, v48, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v38, v49, v3 op_sel:[1,0,0]
v_pk_fma_f16 v12, v40, v46, v12 op_sel:[1,0,0]
v_pk_fma_f16 v2, v40, v47, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v40, v48, v1 op_sel:[1,0,0]
v_pk_fma_f16 v0, v40, v49, v0 op_sel:[1,0,0]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v17, v33, v50, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v33, v51, v19 op_sel:[0,1,0] op_sel_hi:[0,0,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v18, v33, v52, v18 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v16, v33, v53, v16 op_sel:[0,1,0] op_sel_hi:[0,0,1]
v_pk_fma_f16 v15, v35, v50, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v35, v51, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v35, v52, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v35, v53, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v37, v50, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v37, v51, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v37, v52, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v37, v53, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v39, v50, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v39, v51, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v39, v52, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v39, v53, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v41, v50, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v41, v51, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v41, v52, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v41, v53, v0 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v17, v33, v54, v17 op_sel:[1,0,0]
v_pk_fma_f16 v19, v33, v55, v19 op_sel:[1,1,0] op_sel_hi:[1,0,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v18, v33, v56, v18 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v16, v33, v57, v16 op_sel:[1,1,0] op_sel_hi:[1,0,1]
v_pk_fma_f16 v15, v35, v54, v15 op_sel:[1,0,0]
v_pk_fma_f16 v11, v35, v55, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v35, v56, v10 op_sel:[1,0,0]
v_pk_fma_f16 v9, v35, v57, v9 op_sel:[1,0,0]
v_pk_fma_f16 v14, v37, v54, v14 op_sel:[1,0,0]
v_pk_fma_f16 v8, v37, v55, v8 op_sel:[1,0,0]
v_pk_fma_f16 v7, v37, v56, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v37, v57, v6 op_sel:[1,0,0]
v_pk_fma_f16 v13, v39, v54, v13 op_sel:[1,0,0]
v_pk_fma_f16 v5, v39, v55, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v39, v56, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v39, v57, v3 op_sel:[1,0,0]
v_pk_fma_f16 v12, v41, v54, v12 op_sel:[1,0,0]
v_pk_fma_f16 v2, v41, v55, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v41, v56, v1 op_sel:[1,0,0]
v_pk_fma_f16 v0, v41, v57, v0 op_sel:[1,0,0]
s_cbranch_scc1 BB63_4
s_add_i32 s12, s12, 1
s_cmp_eq_u32 s12, 16
s_cbranch_scc0 BB63_1
v_or_b32_e32 v22, s6, v21
s_mulk_i32 s1, 0x6400
v_mov_b32_e32 v53, 0xffff
v_mad_u32_u24 v20, 0xa00, v20, s1
v_lshlrev_b32_e32 v22, 1, v22
v_or3_b32 v20, v20, s6, v21
s_clause 0x6
global_load_dword v46, v22, s[4:5]
global_load_ushort v47, v22, s[4:5] offset:128
global_load_ushort v48, v22, s[4:5] offset:256
global_load_ushort v49, v22, s[4:5] offset:384
global_load_ushort v50, v22, s[4:5] offset:258
global_load_ushort v51, v22, s[4:5] offset:130
global_load_ushort v52, v22, s[4:5] offset:386
v_add_nc_u32_e32 v22, 0x400, v20
v_ashrrev_i32_e32 v21, 31, v20
v_add_nc_u32_e32 v24, 0x440, v20
v_add_nc_u32_e32 v26, 0x480, v20
v_add_nc_u32_e32 v28, 0x4c0, v20
v_ashrrev_i32_e32 v23, 31, v22
v_add_nc_u32_e32 v30, 0x600, v20
v_add_nc_u32_e32 v32, 0x640, v20
v_add_nc_u32_e32 v34, 0x680, v20
v_add_nc_u32_e32 v36, 0x6c0, v20
v_add_nc_u32_e32 v38, 0x800, v20
v_add_nc_u32_e32 v40, 0x840, v20
v_add_nc_u32_e32 v42, 0x880, v20
v_add_nc_u32_e32 v44, 0x8c0, v20
v_lshlrev_b64 v[20:21], 1, v[20:21]
v_ashrrev_i32_e32 v25, 31, v24
v_lshlrev_b64 v[22:23], 1, v[22:23]
v_ashrrev_i32_e32 v27, 31, v26
v_ashrrev_i32_e32 v29, 31, v28
v_ashrrev_i32_e32 v31, 31, v30
v_add_co_u32 v20, vcc_lo, s2, v20
v_lshlrev_b64 v[24:25], 1, v[24:25]
v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo
v_add_co_u32 v22, vcc_lo, s2, v22
v_lshlrev_b64 v[26:27], 1, v[26:27]
v_add_co_ci_u32_e32 v23, vcc_lo, s3, v23, vcc_lo
v_lshlrev_b64 v[28:29], 1, v[28:29]
v_add_co_u32 v24, vcc_lo, s2, v24
v_ashrrev_i32_e32 v33, 31, v32
v_add_co_ci_u32_e32 v25, vcc_lo, s3, v25, vcc_lo
v_add_co_u32 v26, vcc_lo, s2, v26
v_lshlrev_b64 v[30:31], 1, v[30:31]
v_ashrrev_i32_e32 v35, 31, v34
v_add_co_ci_u32_e32 v27, vcc_lo, s3, v27, vcc_lo
v_add_co_u32 v28, vcc_lo, s2, v28
v_lshlrev_b64 v[32:33], 1, v[32:33]
v_ashrrev_i32_e32 v37, 31, v36
v_add_co_ci_u32_e32 v29, vcc_lo, s3, v29, vcc_lo
v_add_co_u32 v30, vcc_lo, s2, v30
v_lshlrev_b64 v[34:35], 1, v[34:35]
v_ashrrev_i32_e32 v39, 31, v38
v_add_co_ci_u32_e32 v31, vcc_lo, s3, v31, vcc_lo
v_add_co_u32 v32, vcc_lo, s2, v32
v_lshlrev_b64 v[36:37], 1, v[36:37]
v_ashrrev_i32_e32 v41, 31, v40
v_add_co_ci_u32_e32 v33, vcc_lo, s3, v33, vcc_lo
v_add_co_u32 v34, vcc_lo, s2, v34
v_lshlrev_b64 v[38:39], 1, v[38:39]
v_ashrrev_i32_e32 v43, 31, v42
v_add_co_ci_u32_e32 v35, vcc_lo, s3, v35, vcc_lo
v_add_co_u32 v36, vcc_lo, s2, v36
v_lshlrev_b64 v[40:41], 1, v[40:41]
v_ashrrev_i32_e32 v45, 31, v44
v_add_co_ci_u32_e32 v37, vcc_lo, s3, v37, vcc_lo
v_add_co_u32 v38, vcc_lo, s2, v38
v_lshlrev_b64 v[42:43], 1, v[42:43]
v_add_co_ci_u32_e32 v39, vcc_lo, s3, v39, vcc_lo
v_add_co_u32 v40, vcc_lo, s2, v40
v_lshlrev_b64 v[44:45], 1, v[44:45]
v_add_co_ci_u32_e32 v41, vcc_lo, s3, v41, vcc_lo
v_add_co_u32 v42, vcc_lo, s2, v42
v_add_co_ci_u32_e32 v43, vcc_lo, s3, v43, vcc_lo
v_add_co_u32 v44, vcc_lo, s2, v44
v_add_co_ci_u32_e32 v45, vcc_lo, s3, v45, vcc_lo
s_waitcnt vmcnt(6)
v_pk_add_f16 v14, v46, v14
s_waitcnt vmcnt(5)
v_add_f16_sdwa v54, v47, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v47, v53, v47
s_waitcnt vmcnt(4)
v_add_f16_sdwa v55, v48, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v48, v53, v48
s_waitcnt vmcnt(3)
v_add_f16_sdwa v56, v49, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v49, v53, v49
s_waitcnt vmcnt(1)
v_lshl_or_b32 v47, v51, 16, v47
v_pk_add_f16 v13, v46, v13
v_lshl_or_b32 v48, v50, 16, v48
v_pk_add_f16 v12, v46, v12
s_waitcnt vmcnt(0)
v_lshl_or_b32 v49, v52, 16, v49
v_pk_add_f16 v11, v47, v11
v_pk_add_f16 v17, v46, v17
v_pk_add_f16 v10, v48, v10
v_pk_add_f16 v8, v47, v8
v_pk_add_f16 v9, v49, v9
v_add_f16_e32 v19, v51, v19
v_pk_add_f16 v7, v48, v7
v_pk_add_f16 v15, v46, v15
v_add_f16_e32 v18, v50, v18
v_add_f16_e32 v16, v52, v16
v_pk_add_f16 v6, v49, v6
v_pk_add_f16 v5, v47, v5
v_pk_add_f16 v4, v48, v4
v_pk_add_f16 v3, v49, v3
v_pk_add_f16 v2, v47, v2
v_pk_add_f16 v1, v48, v1
v_pk_add_f16 v0, v49, v0
v_max_f16_e32 v46, 0, v54
v_pk_max_f16 v14, v14, 0
v_pk_max_f16 v13, v13, 0
v_pk_max_f16 v12, v12, 0
v_pk_max_f16 v11, v11, 0
v_max_f16_e32 v53, 0, v55
v_pk_max_f16 v10, v10, 0
v_max_f16_e32 v54, 0, v56
v_pk_max_f16 v9, v9, 0
v_pk_max_f16 v17, v17, 0
v_pk_max_f16 v8, v8, 0
v_max_f16_e32 v19, 0, v19
v_pk_max_f16 v7, v7, 0
v_max_f16_e32 v18, 0, v18
v_max_f16_e32 v16, 0, v16
v_pk_max_f16 v15, v15, 0
global_store_short v[20:21], v46, off offset:128
global_store_short v[20:21], v53, off offset:256
global_store_short v[20:21], v54, off offset:384
global_store_dword v[20:21], v17, off
global_store_short v[20:21], v19, off offset:130
global_store_short v[20:21], v18, off offset:258
global_store_short v[20:21], v16, off offset:386
global_store_dword v[20:21], v15, off offset:1024
global_store_dword v[22:23], v14, off
global_store_dword v[30:31], v13, off
global_store_dword v[38:39], v12, off
v_pk_max_f16 v6, v6, 0
v_pk_max_f16 v5, v5, 0
v_pk_max_f16 v4, v4, 0
v_pk_max_f16 v3, v3, 0
v_pk_max_f16 v2, v2, 0
v_pk_max_f16 v1, v1, 0
v_pk_max_f16 v0, v0, 0
global_store_dword v[20:21], v11, off offset:1152
global_store_dword v[20:21], v10, off offset:1280
global_store_dword v[20:21], v9, off offset:1408
global_store_dword v[24:25], v8, off
global_store_dword v[26:27], v7, off
global_store_dword v[28:29], v6, off
global_store_dword v[32:33], v5, off
global_store_dword v[34:35], v4, off
global_store_dword v[36:37], v3, off
global_store_dword v[40:41], v2, off
global_store_dword v[42:43], v1, off
global_store_dword v[44:45], v0, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_nn_relu_9_kernel0
.amdhsa_group_segment_fixed_size 39168
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 112
.amdhsa_next_free_sgpr 25
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end63:
.size tvmgen_default_fused_nn_conv2d_add_nn_relu_9_kernel0, .Lfunc_end63-tvmgen_default_fused_nn_conv2d_add_nn_relu_9_kernel0
.globl tvmgen_default_fused_nn_conv2d_add_nn_relu_kernel0
.p2align 8
.type tvmgen_default_fused_nn_conv2d_add_nn_relu_kernel0,@function
tvmgen_default_fused_nn_conv2d_add_nn_relu_kernel0:
v_mul_hi_i32 v1, 0x60606061, v0
s_mul_hi_i32 s0, s6, 0x66666667
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_lshr_b32 s1, s0, 31
s_ashr_i32 s0, s0, 2
v_mov_b32_e32 v5, 0
s_add_i32 s1, s0, s1
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v1, 5, v1
s_mul_i32 s0, s1, 10
s_mul_i32 s11, s1, 30
s_sub_i32 s2, s6, s0
s_mul_i32 s10, s1, 0x11940
v_add_nc_u32_e32 v3, v1, v2
s_mul_i32 s12, s2, 0x50
s_mul_i32 s3, s2, 0xf0
s_add_i32 s12, s12, -3
v_mul_lo_u32 v1, 0x55, v3
v_sub_nc_u32_e32 v4, v0, v1
v_add_nc_u32_e32 v1, s11, v3
v_add_nc_u32_e32 v2, s12, v4
v_cmp_lt_i32_e32 vcc_lo, 2, v1
v_cmp_gt_u32_e64 s0, 0x320, v2
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s6, s0
s_cbranch_execz BB64_2
v_mul_lo_u32 v1, 0x960, v3
v_mul_lo_u32 v2, v4, 3
v_add3_u32 v1, s3, s10, v1
v_add3_u32 v1, v1, v2, 0xffffe3d7
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_ushort v5, v[1:2], off
BB64_2:
s_or_b32 exec_lo, exec_lo, s6
v_mul_u32_u24_e32 v1, 3, v0
v_mov_b32_e32 v6, 0
v_lshlrev_b32_e32 v2, 1, v1
s_waitcnt vmcnt(0)
ds_write_b16 v2, v5
s_and_saveexec_b32 s6, s0
s_cbranch_execz BB64_4
v_mul_lo_u32 v5, 0x960, v3
v_mul_lo_u32 v6, v4, 3
v_add3_u32 v5, s3, s10, v5
v_add3_u32 v5, v5, v6, 0xffffe3d8
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 1, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
global_load_ushort v6, v[5:6], off
BB64_4:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v5, 0
s_waitcnt vmcnt(0)
ds_write_b16 v2, v6 offset:2
s_and_saveexec_b32 s6, s0
s_cbranch_execz BB64_6
v_mul_lo_u32 v3, 0x960, v3
v_mul_lo_u32 v4, v4, 3
v_add3_u32 v3, s3, s10, v3
v_add3_u32 v3, v3, v4, 0xffffe3d9
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 1, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
global_load_ushort v5, v[3:4], off
BB64_6:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v3, 55, v0
s_mov_b32 s0, 0xc0c0c0c1
s_waitcnt vmcnt(0)
ds_write_b16 v2, v5 offset:4
v_mul_hi_u32 v4, v3, s0
v_lshrrev_b32_e32 v4, 6, v4
v_mul_u32_u24_e32 v4, 0x55, v4
v_sub_nc_u32_e32 v3, v3, v4
v_add_nc_u32_e32 v4, s12, v3
v_cmp_gt_u32_e32 vcc_lo, 0x320, v4
v_mov_b32_e32 v4, 0
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz BB64_8
v_add_nc_u32_e32 v4, 0x1e0, v0
v_mul_u32_u24_e32 v5, 3, v3
v_mul_hi_u32 v4, v4, s0
v_lshrrev_b32_e32 v4, 6, v4
v_mul_i32_i24_e32 v4, 0x960, v4
v_add3_u32 v4, s10, s3, v4
v_add3_u32 v4, v4, v5, 0xffffe3d7
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 1, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, s0, s8, v4
v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
global_load_ushort v4, v[4:5], off
BB64_8:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v5, 0
s_waitcnt vmcnt(0)
ds_write_b16 v2, v4 offset:2880
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz BB64_10
v_add_nc_u32_e32 v4, 0x1e0, v0
v_mul_u32_u24_e32 v5, 3, v3
v_mul_hi_u32 v4, 0xc0c0c0c1, v4
v_lshrrev_b32_e32 v4, 6, v4
v_mul_i32_i24_e32 v4, 0x960, v4
v_add3_u32 v4, s10, s3, v4
v_add3_u32 v4, v4, v5, 0xffffe3d8
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 1, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, s0, s8, v4
v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
global_load_ushort v5, v[4:5], off
BB64_10:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v4, 0
s_waitcnt vmcnt(0)
ds_write_b16 v2, v5 offset:2882
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB64_12
v_add_nc_u32_e32 v4, 0x1e0, v0
v_mul_u32_u24_e32 v3, 3, v3
v_mul_hi_u32 v4, 0xc0c0c0c1, v4
v_lshrrev_b32_e32 v4, 6, v4
v_mul_i32_i24_e32 v4, 0x960, v4
v_add3_u32 v4, s10, s3, v4
v_add3_u32 v3, v4, v3, 0xffffe3d9
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 1, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
global_load_ushort v4, v[3:4], off
BB64_12:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v3, 25, v0
s_mov_b32 s0, 0xc0c0c0c1
s_waitcnt vmcnt(0)
ds_write_b16 v2, v4 offset:2884
v_mul_hi_u32 v5, v3, s0
v_lshrrev_b32_e32 v5, 6, v5
v_mul_u32_u24_e32 v5, 0x55, v5
v_sub_nc_u32_e32 v3, v3, v5
v_add_nc_u32_e32 v5, s12, v3
v_cmp_gt_u32_e32 vcc_lo, 0x320, v5
v_mov_b32_e32 v5, 0
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz BB64_14
v_add_nc_u32_e32 v4, 0x3c0, v0
v_mul_u32_u24_e32 v5, 3, v3
v_mul_hi_u32 v4, v4, s0
v_lshrrev_b32_e32 v4, 6, v4
v_mul_i32_i24_e32 v4, 0x960, v4
v_add3_u32 v4, s10, s3, v4
v_add3_u32 v4, v4, v5, 0xffffe3d7
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 1, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, s0, s8, v4
v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
global_load_ushort v5, v[4:5], off
BB64_14:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v6, 0
s_waitcnt vmcnt(0)
ds_write_b16 v2, v5 offset:5760
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz BB64_16
v_add_nc_u32_e32 v4, 0x3c0, v0
v_mul_u32_u24_e32 v5, 3, v3
v_mul_hi_u32 v4, 0xc0c0c0c1, v4
v_lshrrev_b32_e32 v4, 6, v4
v_mul_i32_i24_e32 v4, 0x960, v4
v_add3_u32 v4, s10, s3, v4
v_add3_u32 v4, v4, v5, 0xffffe3d8
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 1, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, s0, s8, v4
v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
global_load_ushort v6, v[4:5], off
BB64_16:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v4, 0
s_waitcnt vmcnt(0)
ds_write_b16 v2, v6 offset:5762
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB64_18
v_add_nc_u32_e32 v4, 0x3c0, v0
v_mul_u32_u24_e32 v3, 3, v3
v_mul_hi_u32 v4, 0xc0c0c0c1, v4
v_lshrrev_b32_e32 v4, 6, v4
v_mul_i32_i24_e32 v4, 0x960, v4
v_add3_u32 v4, s10, s3, v4
v_add3_u32 v3, v4, v3, 0xffffe3d9
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 1, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
global_load_ushort v4, v[3:4], off
BB64_18:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v3, 0x50, v0
s_mov_b32 s0, 0xc0c0c0c1
s_waitcnt vmcnt(0)
ds_write_b16 v2, v4 offset:5764
v_mul_hi_u32 v5, v3, s0
v_lshrrev_b32_e32 v5, 6, v5
v_mul_u32_u24_e32 v5, 0x55, v5
v_sub_nc_u32_e32 v3, v3, v5
v_add_nc_u32_e32 v5, s12, v3
v_cmp_gt_u32_e32 vcc_lo, 0x320, v5
v_mov_b32_e32 v5, 0
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz BB64_20
v_add_nc_u32_e32 v4, 0x5a0, v0
v_mul_u32_u24_e32 v5, 3, v3
v_mul_hi_u32 v4, v4, s0
v_lshrrev_b32_e32 v4, 6, v4
v_mul_i32_i24_e32 v4, 0x960, v4
v_add3_u32 v4, s10, s3, v4
v_add3_u32 v4, v4, v5, 0xffffe3d7
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 1, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, s0, s8, v4
v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
global_load_ushort v5, v[4:5], off
BB64_20:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v6, 0
s_waitcnt vmcnt(0)
ds_write_b16 v2, v5 offset:8640
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz BB64_22
v_add_nc_u32_e32 v4, 0x5a0, v0
v_mul_u32_u24_e32 v5, 3, v3
v_mul_hi_u32 v4, 0xc0c0c0c1, v4
v_lshrrev_b32_e32 v4, 6, v4
v_mul_i32_i24_e32 v4, 0x960, v4
v_add3_u32 v4, s10, s3, v4
v_add3_u32 v4, v4, v5, 0xffffe3d8
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 1, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, s0, s8, v4
v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
global_load_ushort v6, v[4:5], off
BB64_22:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v4, 0
s_waitcnt vmcnt(0)
ds_write_b16 v2, v6 offset:8642
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB64_24
v_add_nc_u32_e32 v4, 0x5a0, v0
v_mul_u32_u24_e32 v3, 3, v3
v_mul_hi_u32 v4, 0xc0c0c0c1, v4
v_lshrrev_b32_e32 v4, 6, v4
v_mul_i32_i24_e32 v4, 0x960, v4
v_add3_u32 v4, s10, s3, v4
v_add3_u32 v3, v4, v3, 0xffffe3d9
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 1, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
global_load_ushort v4, v[3:4], off
BB64_24:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v3, 50, v0
s_mov_b32 s0, 0xc0c0c0c1
s_waitcnt vmcnt(0)
ds_write_b16 v2, v4 offset:8644
v_mul_hi_u32 v5, v3, s0
v_lshrrev_b32_e32 v5, 6, v5
v_mul_u32_u24_e32 v5, 0x55, v5
v_sub_nc_u32_e32 v3, v3, v5
v_add_nc_u32_e32 v5, s12, v3
v_cmp_gt_u32_e32 vcc_lo, 0x320, v5
v_mov_b32_e32 v5, 0
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz BB64_26
v_add_nc_u32_e32 v4, 0x780, v0
v_mul_u32_u24_e32 v5, 3, v3
v_mul_hi_u32 v4, v4, s0
v_lshrrev_b32_e32 v4, 6, v4
v_mul_i32_i24_e32 v4, 0x960, v4
v_add3_u32 v4, s10, s3, v4
v_add3_u32 v4, v4, v5, 0xffffe3d7
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 1, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, s0, s8, v4
v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
global_load_ushort v5, v[4:5], off
BB64_26:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v4, 0
s_waitcnt vmcnt(0)
ds_write_b16 v2, v5 offset:11520
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz BB64_28
v_add_nc_u32_e32 v4, 0x780, v0
v_mul_u32_u24_e32 v5, 3, v3
v_mul_hi_u32 v4, 0xc0c0c0c1, v4
v_lshrrev_b32_e32 v4, 6, v4
v_mul_i32_i24_e32 v4, 0x960, v4
v_add3_u32 v4, s10, s3, v4
v_add3_u32 v4, v4, v5, 0xffffe3d8
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 1, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, s0, s8, v4
v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
global_load_ushort v4, v[4:5], off
BB64_28:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v5, 0
s_waitcnt vmcnt(0)
ds_write_b16 v2, v4 offset:11522
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB64_30
v_add_nc_u32_e32 v4, 0x780, v0
v_mul_u32_u24_e32 v3, 3, v3
v_mul_hi_u32 v4, 0xc0c0c0c1, v4
v_lshrrev_b32_e32 v4, 6, v4
v_mul_i32_i24_e32 v4, 0x960, v4
v_add3_u32 v4, s10, s3, v4
v_add3_u32 v3, v4, v3, 0xffffe3d9
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 1, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
global_load_ushort v5, v[3:4], off
BB64_30:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v3, 20, v0
s_mov_b32 s0, 0xc0c0c0c1
s_movk_i32 s7, 0x960
s_waitcnt vmcnt(0)
ds_write_b16 v2, v5 offset:11524
v_add_nc_u32_e32 v6, s7, v0
v_mul_hi_u32 v4, v3, s0
v_mul_hi_u32 v6, v6, s0
v_lshrrev_b32_e32 v4, 6, v4
v_mul_u32_u24_e32 v7, 0x55, v4
v_lshrrev_b32_e32 v4, 6, v6
v_sub_nc_u32_e32 v3, v3, v7
v_add_nc_u32_e32 v6, s11, v4
v_add_nc_u32_e32 v7, s12, v3
v_cmp_gt_i32_e32 vcc_lo, 0x2f1, v6
v_mov_b32_e32 v6, 0
v_cmp_gt_u32_e64 s0, 0x320, v7
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s6, s0
s_cbranch_execz BB64_32
v_mul_i32_i24_e32 v5, s7, v4
v_mul_u32_u24_e32 v6, 3, v3
v_add3_u32 v5, s10, s3, v5
v_add3_u32 v5, v5, v6, 0xffffe3d7
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 1, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
global_load_ushort v6, v[5:6], off
BB64_32:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v7, 0
s_waitcnt vmcnt(0)
ds_write_b16 v2, v6 offset:14400
s_and_saveexec_b32 s6, s0
s_cbranch_execz BB64_34
v_mul_i32_i24_e32 v5, 0x960, v4
v_mul_u32_u24_e32 v6, 3, v3
v_add3_u32 v5, s10, s3, v5
v_add3_u32 v5, v5, v6, 0xffffe3d8
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 1, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
global_load_ushort v7, v[5:6], off
BB64_34:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v5, 0
s_waitcnt vmcnt(0)
ds_write_b16 v2, v7 offset:14402
s_and_saveexec_b32 s6, s0
s_cbranch_execz BB64_36
v_mul_i32_i24_e32 v4, 0x960, v4
v_mul_u32_u24_e32 v3, 3, v3
v_add3_u32 v4, s10, s3, v4
v_add3_u32 v3, v4, v3, 0xffffe3d9
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 1, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
global_load_ushort v5, v[3:4], off
BB64_36:
s_or_b32 exec_lo, exec_lo, s6
s_clause 0x1
s_load_dwordx2 s[14:15], s[4:5], 0x8
s_load_dwordx2 s[6:7], s[4:5], 0x10
v_cmp_gt_i32_e32 vcc_lo, 0x5f, v0
s_waitcnt vmcnt(0)
ds_write_b16 v2, v5 offset:14404
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz BB64_44
v_add_nc_u32_e32 v3, 0x4b, v0
s_mov_b32 s0, 0xc0c0c0c1
v_add_nc_u32_e32 v5, 0xb40, v0
v_mul_hi_u32 v4, v3, s0
v_mul_hi_u32 v5, v5, s0
v_lshrrev_b32_e32 v4, 6, v4
v_mul_u32_u24_e32 v6, 0x55, v4
v_lshrrev_b32_e32 v4, 6, v5
v_sub_nc_u32_e32 v3, v3, v6
v_add_nc_u32_e32 v5, s11, v4
v_add_nc_u32_e32 v6, s12, v3
v_cmp_gt_i32_e32 vcc_lo, 0x2f1, v5
v_mov_b32_e32 v5, 0
v_cmp_gt_u32_e64 s0, 0x320, v6
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s11, s0
s_cbranch_execz BB64_39
v_mul_i32_i24_e32 v5, 0x960, v4
v_mul_u32_u24_e32 v6, 3, v3
v_add3_u32 v5, s10, s3, v5
v_add3_u32 v5, v5, v6, 0xffffe3d7
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 1, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
global_load_ushort v5, v[5:6], off
BB64_39:
s_or_b32 exec_lo, exec_lo, s11
v_mov_b32_e32 v6, 0
s_waitcnt vmcnt(0)
ds_write_b16 v2, v5 offset:17280
s_and_saveexec_b32 s11, s0
s_cbranch_execz BB64_41
v_mul_i32_i24_e32 v5, 0x960, v4
v_mul_u32_u24_e32 v6, 3, v3
v_add3_u32 v5, s10, s3, v5
v_add3_u32 v5, v5, v6, 0xffffe3d8
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 1, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
global_load_ushort v6, v[5:6], off
BB64_41:
s_or_b32 exec_lo, exec_lo, s11
v_mov_b32_e32 v5, 0
s_waitcnt vmcnt(0)
ds_write_b16 v2, v6 offset:17282
s_and_saveexec_b32 s11, s0
s_cbranch_execz BB64_43
v_mul_i32_i24_e32 v4, 0x960, v4
v_mul_u32_u24_e32 v3, 3, v3
v_add3_u32 v4, s10, s3, v4
v_add3_u32 v3, v4, v3, 0xffffe3d9
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 1, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
global_load_ushort v5, v[3:4], off
BB64_43:
s_or_b32 exec_lo, exec_lo, s11
s_waitcnt vmcnt(0)
ds_write_b16 v2, v5 offset:17284
BB64_44:
s_or_b32 exec_lo, exec_lo, s13
v_lshlrev_b32_e32 v11, 1, v1
s_load_dwordx2 s[4:5], s[4:5], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, s0, s14, v11
v_add_co_ci_u32_e64 v2, s0, s15, 0, s0
v_add_co_u32 v3, vcc_lo, 0x800, v1
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, 0x1000, v1
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v2, vcc_lo
s_clause 0x7
global_load_ushort v12, v11, s[14:15]
global_load_ushort v13, v11, s[14:15] offset:2
global_load_ushort v14, v11, s[14:15] offset:4
global_load_ushort v15, v[3:4], off offset:832
global_load_ushort v16, v[3:4], off offset:834
global_load_ushort v17, v[3:4], off offset:836
global_load_ushort v18, v[5:6], off offset:1664
global_load_ushort v19, v[5:6], off offset:1666
v_add_co_u32 v3, vcc_lo, 0x2000, v1
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v7, vcc_lo, 0x2800, v1
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v9, vcc_lo, 0x3800, v1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v2, vcc_lo
s_clause 0x9
global_load_ushort v5, v[5:6], off offset:1668
global_load_ushort v6, v[3:4], off offset:448
global_load_ushort v20, v[3:4], off offset:450
global_load_ushort v4, v[3:4], off offset:452
global_load_ushort v21, v[7:8], off offset:1280
global_load_ushort v22, v[7:8], off offset:1282
global_load_ushort v7, v[7:8], off offset:1284
global_load_ushort v8, v[9:10], off offset:64
global_load_ushort v23, v[9:10], off offset:66
global_load_ushort v9, v[9:10], off offset:68
v_cmp_gt_i32_e32 vcc_lo, 0x100, v0
v_add_nc_u32_e32 v3, 0x45c0, v11
s_waitcnt vmcnt(17)
ds_write_b16 v11, v12 offset:17856
s_waitcnt vmcnt(16)
ds_write_b16 v11, v13 offset:17858
s_waitcnt vmcnt(15)
ds_write_b16 v11, v14 offset:17860
s_waitcnt vmcnt(14)
ds_write_b16 v11, v15 offset:20736
s_waitcnt vmcnt(13)
ds_write_b16 v11, v16 offset:20738
s_waitcnt vmcnt(12)
ds_write_b16 v11, v17 offset:20740
s_waitcnt vmcnt(11)
ds_write_b16 v11, v18 offset:23616
s_waitcnt vmcnt(10)
ds_write_b16 v11, v19 offset:23618
s_waitcnt vmcnt(9)
ds_write_b16 v11, v5 offset:23620
s_waitcnt vmcnt(8)
ds_write_b16 v11, v6 offset:26496
s_waitcnt vmcnt(7)
ds_write_b16 v11, v20 offset:26498
s_waitcnt vmcnt(6)
ds_write_b16 v11, v4 offset:26500
s_waitcnt vmcnt(5)
ds_write_b16 v11, v21 offset:29376
s_waitcnt vmcnt(4)
ds_write_b16 v11, v22 offset:29378
s_waitcnt vmcnt(3)
ds_write_b16 v11, v7 offset:29380
s_waitcnt vmcnt(2)
ds_write_b16 v11, v8 offset:32256
s_waitcnt vmcnt(1)
ds_write_b16 v11, v23 offset:32258
s_waitcnt vmcnt(0)
ds_write_b16 v11, v9 offset:32260
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB64_46
v_add_co_u32 v1, vcc_lo, 0x4000, v1
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_clause 0x2
global_load_ushort v4, v[1:2], off offset:896
global_load_ushort v5, v[1:2], off offset:898
global_load_ushort v1, v[1:2], off offset:900
s_waitcnt vmcnt(2)
ds_write_b16 v3, v4 offset:17280
s_waitcnt vmcnt(1)
ds_write_b16 v3, v5 offset:17282
s_waitcnt vmcnt(0)
ds_write_b16 v3, v1 offset:17284
BB64_46:
s_or_b32 exec_lo, exec_lo, s0
v_mul_hi_i32 v1, 0x66666667, v0
v_lshlrev_b32_e32 v2, 1, v0
v_mov_b32_e32 v31, 0
v_mov_b32_e32 v34, 0
v_mov_b32_e32 v33, 0
v_mov_b32_e32 v35, 0
v_and_b32_e32 v42, 14, v2
v_mov_b32_e32 v36, 0
v_lshrrev_b32_e32 v3, 31, v1
v_ashrrev_i32_e32 v1, 6, v1
v_mov_b32_e32 v37, 0
v_mov_b32_e32 v38, 0
v_mov_b32_e32 v39, 0
v_mov_b32_e32 v32, 0
v_add_nc_u32_e32 v40, v1, v3
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v28, 0
v_mul_lo_u32 v1, 0xa0, v40
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
v_sub_nc_u32_e32 v41, v0, v1
v_mul_lo_u32 v1, 0x9f6, v40
v_mov_b32_e32 v30, 0
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v15, 0
v_ashrrev_i32_e32 v0, 3, v41
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v29, 0
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v13, 0
v_mul_lo_u32 v0, v0, 12
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v24, 0
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v23, 0
v_add_lshl_u32 v43, v1, v0, 1
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v0, 0
s_mov_b32 s0, 0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
BB64_47:
s_mov_b32 s8, s0
s_mov_b32 s9, 0
BB64_48:
v_or_b32_e32 v44, s8, v42
v_add_nc_u32_e32 v45, s9, v43
s_add_i32 s9, s9, 2
s_add_i32 s8, s8, 64
s_cmp_lg_u32 s9, 6
v_lshlrev_b32_e32 v46, 1, v44
ds_read_u16 v47, v45
ds_read_u16 v48, v45 offset:12
ds_read_u16 v49, v45 offset:510
ds_read_u16 v50, v45 offset:2040
ds_read_u16 v51, v45 offset:2052
ds_read_u16 v52, v45 offset:1542
ds_read_u16 v53, v45 offset:1530
ds_read_u16 v54, v45 offset:1032
ds_read_u16 v55, v45 offset:1020
ds_read_u16 v56, v45 offset:522
ds_read_u16 v57, v45 offset:4080
ds_read_u16 v58, v45 offset:4092
ds_read_u16 v59, v45 offset:3582
ds_read_u16 v60, v45 offset:3570
ds_read_u16 v61, v45 offset:3072
ds_read_u16 v62, v45 offset:3060
ds_read_u16 v63, v45 offset:2562
ds_read_u16 v64, v45 offset:2550
ds_read_u16 v65, v45 offset:5622
ds_read_u16 v66, v45 offset:5610
ds_read_u16 v67, v45 offset:5112
ds_read_u16 v68, v45 offset:5100
ds_read_u16 v69, v45 offset:4602
ds_read_u16 v70, v45 offset:4590
ds_read_u16 v71, v45 offset:6120
ds_read_u16 v72, v45 offset:6132
ds_read_u16 v73, v45 offset:7152
ds_read_u16 v74, v45 offset:7140
ds_read_u16 v75, v45 offset:6642
ds_read_u16 v76, v45 offset:6630
v_add_nc_u32_e32 v77, 0x4400, v46
v_add_nc_u32_e32 v78, 0x5000, v46
ds_read2_b32 v[44:45], v77 offset0:112 offset1:120
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v39, v47, v44, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v47, v45, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v55, v44, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v55, v45, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v50, v44, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v50, v45, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v62, v44, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v62, v45, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v57, v44, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v57, v45, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v48, v44, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v48, v45, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v54, v44, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v54, v45, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v51, v44, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v61, v44, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v51, v45, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v61, v45, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v44, v58, v44, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v45, v58, v45, v2 op_sel_hi:[0,1,1]
ds_read2_b32 v[2:3], v77 offset0:128 offset1:136
v_add_nc_u32_e32 v77, 0x6c00, v46
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v35, v47, v2, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v47, v3, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v48, v2, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v48, v3, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v55, v2, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v55, v3, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v50, v2, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v50, v3, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v62, v2, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v62, v3, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v57, v2, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v57, v3, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v54, v2, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v54, v3, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v51, v2, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v61, v2, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v51, v3, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v61, v3, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v58, v2, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v58, v3, v0 op_sel_hi:[0,1,1]
ds_read2_b32 v[0:1], v78 offset0:16 offset1:24
v_add_nc_u32_e32 v47, 0x5800, v46
v_add_nc_u32_e32 v48, 0x6400, v46
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v39, v49, v0, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v49, v1, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v53, v0, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v53, v1, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v64, v0, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v64, v1, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v60, v0, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v60, v1, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v70, v0, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v70, v1, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v56, v0, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v56, v1, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v52, v0, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v52, v1, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v63, v0, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v63, v1, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v59, v0, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v59, v1, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v44, v69, v0, v44 op_sel_hi:[0,1,1]
v_pk_fma_f16 v45, v69, v1, v45 op_sel_hi:[0,1,1]
ds_read2_b32 v[0:1], v78 offset0:32 offset1:40
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v35, v49, v0, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v49, v1, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v56, v0, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v56, v1, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v53, v0, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v53, v1, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v64, v0, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v64, v1, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v60, v0, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v60, v1, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v78, v70, v0, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v79, v70, v1, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v52, v0, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v52, v1, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v63, v0, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v63, v1, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v59, v0, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v59, v1, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v80, v69, v0, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v81, v69, v1, v3 op_sel_hi:[0,1,1]
ds_read2_b32 v[0:1], v47 offset0:176 offset1:184
ds_read2_b32 v[2:3], v48 offset0:80 offset1:88
ds_read2_b32 v[4:5], v48 offset0:96 offset1:104
v_add_nc_u32_e32 v49, 0x7000, v46
v_add_nc_u32_e32 v56, 0x7800, v46
v_add_nc_u32_e32 v46, 0x8400, v46
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v39, v55, v0, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v55, v1, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v50, v0, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v50, v1, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v62, v0, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v62, v1, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v57, v0, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v57, v1, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v68, v0, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v68, v1, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v54, v0, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v54, v1, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v51, v0, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v51, v1, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v61, v0, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v61, v1, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v58, v0, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v58, v1, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v44, v67, v0, v44 op_sel_hi:[0,1,1]
v_pk_fma_f16 v45, v67, v1, v45 op_sel_hi:[0,1,1]
ds_read2_b32 v[0:1], v47 offset0:192 offset1:200
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v39, v53, v2, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v53, v3, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v64, v2, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v64, v3, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v60, v2, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v60, v3, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v70, v2, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v70, v3, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v66, v2, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v66, v3, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v52, v2, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v52, v3, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v63, v2, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v63, v3, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v59, v2, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v59, v3, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v69, v2, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v69, v3, v24 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v35, v55, v0, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v55, v1, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v54, v0, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v54, v1, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v48, v50, v1, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v57, v0, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v57, v1, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v51, v0, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v51, v1, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v61, v0, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v61, v1, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v58, v0, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v58, v1, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v47, v50, v0, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v54, v62, v0, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v55, v62, v1, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v78, v68, v0, v78 op_sel_hi:[0,1,1]
v_pk_fma_f16 v79, v68, v1, v79 op_sel_hi:[0,1,1]
v_pk_fma_f16 v80, v67, v0, v80 op_sel_hi:[0,1,1]
v_pk_fma_f16 v81, v67, v1, v81 op_sel_hi:[0,1,1]
ds_read2_b32 v[0:1], v77 offset0:240 offset1:248
ds_read2_b32 v[6:7], v49 offset1:8
v_pk_fma_f16 v49, v65, v2, v44 op_sel_hi:[0,1,1]
v_pk_fma_f16 v77, v65, v3, v45 op_sel_hi:[0,1,1]
ds_read2_b32 v[2:3], v56 offset0:144 offset1:152
ds_read2_b32 v[8:9], v56 offset0:160 offset1:168
v_pk_fma_f16 v33, v52, v4, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v52, v5, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v52, v64, v4, v47 op_sel_hi:[0,1,1]
ds_read2_b32 v[44:45], v46 offset0:48 offset1:56
ds_read2_b32 v[46:47], v46 offset0:64 offset1:72
v_pk_fma_f16 v35, v53, v4, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v53, v5, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v48, v64, v5, v48 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v70, v4, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v70, v5, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v63, v4, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v63, v5, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v59, v4, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v59, v5, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v69, v4, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v69, v5, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v60, v4, v54 op_sel_hi:[0,1,1]
v_pk_fma_f16 v54, v60, v5, v55 op_sel_hi:[0,1,1]
v_pk_fma_f16 v55, v66, v4, v78 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v65, v4, v80 op_sel_hi:[0,1,1]
v_pk_fma_f16 v56, v66, v5, v79 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v65, v5, v81 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(5)
v_pk_fma_f16 v32, v62, v0, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v62, v1, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v57, v0, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v57, v1, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v68, v0, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v68, v1, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v71, v0, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v71, v1, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v51, v0, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v51, v1, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v61, v0, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v61, v1, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v58, v0, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v58, v1, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v67, v0, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v67, v1, v24 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(4)
v_pk_fma_f16 v35, v50, v6, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v50, v7, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v51, v6, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v51, v7, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v48, v62, v7, v48 op_sel_hi:[0,1,1]
v_pk_fma_f16 v51, v57, v7, v54 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v68, v6, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v68, v7, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v61, v6, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v61, v7, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v67, v6, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v67, v7, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v39, v50, v0, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v72, v0, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v49, v62, v6, v52 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v50, v1, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v57, v6, v53 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v72, v1, v77 op_sel_hi:[0,1,1]
v_pk_fma_f16 v52, v71, v6, v55 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v71, v7, v56 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v72, v6, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v58, v6, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v72, v7, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v58, v7, v16 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(3)
v_pk_fma_f16 v6, v64, v2, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v64, v3, v37 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v35, v64, v8, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v64, v9, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v60, v2, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v60, v3, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v70, v2, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v70, v3, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v66, v2, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v66, v3, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v66, v8, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v66, v9, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v76, v2, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v76, v3, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v63, v2, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v63, v3, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v63, v8, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v63, v9, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v59, v2, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v59, v3, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v59, v8, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v59, v9, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v69, v2, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v69, v3, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v65, v2, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v65, v3, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v65, v8, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v65, v9, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v75, v2, v0 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v69, v8, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v75, v3, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v69, v9, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v49, v60, v8, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v48, v60, v9, v48 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v70, v8, v50 op_sel_hi:[0,1,1]
v_pk_fma_f16 v51, v70, v9, v51 op_sel_hi:[0,1,1]
v_pk_fma_f16 v52, v76, v8, v52 op_sel_hi:[0,1,1]
v_pk_fma_f16 v54, v75, v8, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v76, v9, v53 op_sel_hi:[0,1,1]
v_pk_fma_f16 v55, v75, v9, v5 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v39, v62, v44, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v62, v45, v7 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v15, v67, v46, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v67, v47, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v73, v44, v0 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v73, v45, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v62, v46, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v62, v47, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v57, v44, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v57, v45, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v57, v46, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v57, v47, v48 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v68, v44, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v68, v45, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v68, v46, v50 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v68, v47, v51 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v71, v44, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v71, v45, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v71, v46, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v71, v47, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v74, v44, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v74, v45, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v74, v46, v52 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v74, v47, v53 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v61, v44, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v61, v45, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v61, v46, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v61, v47, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v58, v44, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v58, v45, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v58, v46, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v58, v47, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v67, v44, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v67, v45, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v72, v44, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v72, v45, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v72, v46, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v72, v47, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v73, v46, v54 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v73, v47, v55 op_sel_hi:[0,1,1]
s_cbranch_scc1 BB64_48
v_add_nc_u32_e32 v43, 6, v43
s_add_i32 s3, s3, 1
s_addk_i32 s0, 0xc0
s_cmp_eq_u32 s3, 7
s_cbranch_scc0 BB64_47
v_lshlrev_b32_e32 v43, 1, v42
v_mul_lo_u32 v40, 0x1f400, v40
s_mulk_i32 s2, 0xa00
s_mul_i32 s1, s1, 0x5dc00
v_lshlrev_b32_e32 v41, 4, v41
s_clause 0x6
global_load_ushort v73, v43, s[4:5] offset:32
global_load_ushort v74, v43, s[4:5] offset:64
global_load_ushort v75, v43, s[4:5] offset:96
global_load_ushort v76, v43, s[4:5] offset:66
global_load_ushort v77, v43, s[4:5] offset:34
global_load_dword v78, v43, s[4:5]
global_load_ushort v79, v43, s[4:5] offset:98
v_mov_b32_e32 v45, 0
v_add3_u32 v40, s2, s1, v40
v_and_b32_e32 v41, 0xffffff80, v41
v_or_b32_e32 v40, v40, v42
v_add_nc_u32_e32 v40, v40, v41
v_add_nc_u32_e32 v42, 0x6400, v40
v_ashrrev_i32_e32 v41, 31, v40
v_add_nc_u32_e32 v49, 0x6440, v40
v_add_nc_u32_e32 v54, 0xc840, v40
v_add_nc_u32_e32 v44, 0x6410, v40
v_ashrrev_i32_e32 v43, 31, v42
v_lshlrev_b64 v[52:53], 1, v[40:41]
v_add_nc_u32_e32 v41, 0xc800, v40
v_add_nc_u32_e32 v46, 0x6420, v40
v_add_nc_u32_e32 v48, 0x6430, v40
v_lshlrev_b64 v[42:43], 1, v[42:43]
v_add_nc_u32_e32 v51, 0x6450, v40
v_add_co_u32 v52, vcc_lo, s6, v52
v_add_nc_u32_e32 v56, 0x6460, v40
v_add_co_ci_u32_e32 v53, vcc_lo, s7, v53, vcc_lo
v_add_nc_u32_e32 v59, 0x6470, v40
v_add_co_u32 v57, vcc_lo, s6, v42
v_add_nc_u32_e32 v61, 0xc810, v40
v_add_co_ci_u32_e32 v58, vcc_lo, s7, v43, vcc_lo
v_add_nc_u32_e32 v63, 0xc820, v40
v_ashrrev_i32_e32 v60, 31, v59
v_add_nc_u32_e32 v67, 0x12c60, v40
v_ashrrev_i32_e32 v62, 31, v61
v_add_nc_u32_e32 v65, 0x12c50, v40
v_ashrrev_i32_e32 v64, 31, v63
v_add_nc_u32_e32 v69, 0x12c70, v40
v_ashrrev_i32_e32 v68, 31, v67
v_add_nc_u32_e32 v71, 0x19030, v40
v_ashrrev_i32_e32 v66, 31, v65
v_ashrrev_i32_e32 v70, 31, v69
v_ashrrev_i32_e32 v72, 31, v71
v_lshlrev_b64 v[71:72], 1, v[71:72]
s_waitcnt vmcnt(6)
v_add_f16_e32 v47, v73, v37
s_waitcnt vmcnt(5)
v_add_f16_e32 v50, v74, v35
s_waitcnt vmcnt(4)
v_add_f16_e32 v55, v75, v34
s_waitcnt vmcnt(3)
v_add_f16_sdwa v35, v76, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
s_waitcnt vmcnt(2)
v_add_f16_sdwa v37, v77, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
s_waitcnt vmcnt(1)
v_pk_add_f16 v39, v78, v39
v_max_f16_e32 v42, 0, v47
s_waitcnt vmcnt(0)
v_add_f16_sdwa v34, v79, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_max_f16_e32 v43, 0, v50
v_pk_add_f16 v38, v78, v38
v_pk_max_f16 v39, v39, 0
v_max_f16_e32 v47, 0, v55
v_max_f16_e32 v37, 0, v37
v_max_f16_e32 v35, 0, v35
global_store_short v[52:53], v42, off offset:32
global_store_short v[52:53], v43, off offset:64
global_store_short v[52:53], v47, off offset:96
v_max_f16_sdwa v42, v38, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
global_store_dword v[52:53], v39, off
v_add_f16_e32 v39, v73, v36
v_max_f16_e32 v34, 0, v34
v_max_f16_e32 v38, 0, v38
global_store_short v[52:53], v37, off offset:34
v_add_f16_e32 v37, v74, v33
global_store_short v[52:53], v35, off offset:66
global_store_short v[52:53], v34, off offset:98
v_add_f16_e32 v35, v75, v31
global_store_short v[52:53], v38, off offset:128
v_max_f16_e32 v38, 0, v39
v_max_f16_e32 v37, 0, v37
v_add_f16_sdwa v36, v77, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_max_f16_e32 v35, 0, v35
v_ashrrev_i32_e32 v50, 31, v49
global_store_short v[52:53], v38, off offset:160
global_store_short v[52:53], v37, off offset:192
v_add_f16_sdwa v37, v79, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_add_f16_sdwa v39, v76, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
global_store_short v[52:53], v35, off offset:224
global_store_short v[52:53], v42, off offset:130
v_ashrrev_i32_e32 v42, 31, v41
v_add_nc_u32_e32 v34, 0x12c00, v40
v_max_f16_e32 v35, 0, v37
v_max_f16_e32 v36, 0, v36
v_lshlrev_b64 v[49:50], 1, v[49:50]
v_max_f16_e32 v38, 0, v39
v_ashrrev_i32_e32 v55, 31, v54
v_lshlrev_b64 v[41:42], 1, v[41:42]
v_pk_add_f16 v28, v78, v28
global_store_short v[52:53], v36, off offset:162
global_store_short v[52:53], v38, off offset:194
global_store_short v[52:53], v35, off offset:226
v_ashrrev_i32_e32 v35, 31, v34
v_add_co_u32 v49, vcc_lo, s6, v49
v_lshlrev_b64 v[54:55], 1, v[54:55]
v_add_co_ci_u32_e32 v50, vcc_lo, s7, v50, vcc_lo
v_add_co_u32 v41, vcc_lo, s6, v41
v_lshlrev_b64 v[34:35], 1, v[34:35]
v_add_co_ci_u32_e32 v42, vcc_lo, s7, v42, vcc_lo
v_pk_max_f16 v28, v28, 0
v_add_co_u32 v54, vcc_lo, s6, v54
v_pk_add_f16 v37, v78, v29
v_pk_add_f16 v30, v78, v30
v_ashrrev_i32_e32 v45, 31, v44
v_add_co_ci_u32_e32 v55, vcc_lo, s7, v55, vcc_lo
v_add_co_u32 v34, vcc_lo, s6, v34
v_ashrrev_i32_e32 v47, 31, v46
global_store_dword v[49:50], v28, off
v_pk_max_f16 v28, v30, 0
v_add_nc_u32_e32 v33, 0x12c40, v40
v_add_co_ci_u32_e32 v35, vcc_lo, s7, v35, vcc_lo
v_pk_max_f16 v30, v37, 0
v_lshlrev_b64 v[43:44], 1, v[44:45]
v_pk_add_f16 v32, v78, v32
v_ashrrev_i32_e32 v49, 31, v48
v_lshlrev_b64 v[45:46], 1, v[46:47]
global_store_dword v[34:35], v30, off
v_ashrrev_i32_e32 v34, 31, v33
v_pk_max_f16 v32, v32, 0
v_add_co_u32 v43, vcc_lo, s6, v43
v_lshlrev_b64 v[47:48], 1, v[48:49]
v_ashrrev_i32_e32 v52, 31, v51
v_add_co_ci_u32_e32 v44, vcc_lo, s7, v44, vcc_lo
v_add_co_u32 v45, vcc_lo, s6, v45
v_lshlrev_b64 v[33:34], 1, v[33:34]
global_store_dword v[57:58], v32, off
v_ashrrev_i32_e32 v57, 31, v56
v_add_co_ci_u32_e32 v46, vcc_lo, s7, v46, vcc_lo
v_pk_add_f16 v32, v78, v27
v_add_co_u32 v47, vcc_lo, s6, v47
v_lshlrev_b64 v[49:50], 1, v[51:52]
v_add_co_ci_u32_e32 v48, vcc_lo, s7, v48, vcc_lo
v_add_co_u32 v33, vcc_lo, s6, v33
v_lshlrev_b64 v[51:52], 1, v[56:57]
v_add_co_ci_u32_e32 v34, vcc_lo, s7, v34, vcc_lo
v_pk_max_f16 v32, v32, 0
v_add_nc_u32_e32 v31, 0xc830, v40
v_add_co_u32 v49, vcc_lo, s6, v49
global_store_dword v[54:55], v28, off
v_lshlrev_b64 v[55:56], 1, v[59:60]
v_add_co_ci_u32_e32 v50, vcc_lo, s7, v50, vcc_lo
v_add_nc_u32_e32 v36, 0xc850, v40
v_add_co_u32 v51, vcc_lo, s6, v51
v_lshlrev_b64 v[57:58], 1, v[61:62]
global_store_dword v[41:42], v32, off
v_ashrrev_i32_e32 v32, 31, v31
v_add_co_ci_u32_e32 v52, vcc_lo, s7, v52, vcc_lo
v_add_nc_u32_e32 v38, 0xc860, v40
v_add_co_u32 v55, vcc_lo, s6, v55
v_lshlrev_b64 v[59:60], 1, v[63:64]
v_ashrrev_i32_e32 v37, 31, v36
v_add_co_ci_u32_e32 v56, vcc_lo, s7, v56, vcc_lo
v_add_nc_u32_e32 v53, 0xc870, v40
v_add_co_u32 v57, vcc_lo, s6, v57
v_lshlrev_b64 v[31:32], 1, v[31:32]
v_ashrrev_i32_e32 v39, 31, v38
v_add_co_ci_u32_e32 v58, vcc_lo, s7, v58, vcc_lo
v_add_nc_u32_e32 v27, 0x12c10, v40
v_add_co_u32 v59, vcc_lo, s6, v59
v_pk_add_f16 v26, v78, v26
v_lshlrev_b64 v[35:36], 1, v[36:37]
v_ashrrev_i32_e32 v54, 31, v53
v_add_co_ci_u32_e32 v60, vcc_lo, s7, v60, vcc_lo
v_add_nc_u32_e32 v29, 0x12c20, v40
v_add_co_u32 v31, vcc_lo, s6, v31
v_lshlrev_b64 v[37:38], 1, v[38:39]
v_ashrrev_i32_e32 v28, 31, v27
v_add_co_ci_u32_e32 v32, vcc_lo, s7, v32, vcc_lo
v_add_nc_u32_e32 v41, 0x12c30, v40
v_pk_max_f16 v26, v26, 0
v_add_co_u32 v35, vcc_lo, s6, v35
v_lshlrev_b64 v[53:54], 1, v[53:54]
v_ashrrev_i32_e32 v30, 31, v29
v_add_co_ci_u32_e32 v36, vcc_lo, s7, v36, vcc_lo
v_add_co_u32 v37, vcc_lo, s6, v37
v_lshlrev_b64 v[27:28], 1, v[27:28]
v_ashrrev_i32_e32 v42, 31, v41
global_store_dword v[33:34], v26, off
v_mov_b32_e32 v26, 0xffff
v_add_co_ci_u32_e32 v38, vcc_lo, s7, v38, vcc_lo
v_add_co_u32 v53, vcc_lo, s6, v53
v_lshlrev_b64 v[29:30], 1, v[29:30]
v_add_co_ci_u32_e32 v54, vcc_lo, s7, v54, vcc_lo
v_and_b32_e32 v39, v26, v73
v_add_co_u32 v27, vcc_lo, s6, v27
v_lshlrev_b64 v[41:42], 1, v[41:42]
v_and_b32_e32 v73, v26, v74
v_add_co_ci_u32_e32 v28, vcc_lo, s7, v28, vcc_lo
v_and_b32_e32 v26, v26, v75
v_lshlrev_b64 v[63:64], 1, v[67:68]
v_add_nc_u32_e32 v67, 0x19000, v40
v_add_co_u32 v29, vcc_lo, s6, v29
v_lshlrev_b64 v[61:62], 1, v[65:66]
v_lshl_or_b32 v39, v77, 16, v39
v_add_co_ci_u32_e32 v30, vcc_lo, s7, v30, vcc_lo
v_add_nc_u32_e32 v33, 0x19010, v40
v_lshl_or_b32 v73, v76, 16, v73
v_add_co_u32 v41, vcc_lo, s6, v41
v_lshl_or_b32 v26, v79, 16, v26
v_ashrrev_i32_e32 v68, 31, v67
v_add_co_ci_u32_e32 v42, vcc_lo, s7, v42, vcc_lo
v_lshlrev_b64 v[65:66], 1, v[69:70]
v_add_nc_u32_e32 v69, 0x19020, v40
v_add_co_u32 v61, vcc_lo, s6, v61
v_ashrrev_i32_e32 v34, 31, v33
v_pk_add_f16 v12, v39, v12
v_add_co_ci_u32_e32 v62, vcc_lo, s7, v62, vcc_lo
v_pk_add_f16 v6, v73, v6
v_add_co_u32 v63, vcc_lo, s6, v63
v_pk_add_f16 v7, v26, v7
v_lshlrev_b64 v[67:68], 1, v[67:68]
v_ashrrev_i32_e32 v70, 31, v69
v_pk_add_f16 v18, v39, v18
v_add_co_ci_u32_e32 v64, vcc_lo, s7, v64, vcc_lo
v_pk_add_f16 v10, v73, v10
v_add_co_u32 v65, vcc_lo, s6, v65
v_pk_add_f16 v11, v26, v11
v_pk_add_f16 v17, v39, v17
v_pk_add_f16 v8, v73, v8
v_pk_add_f16 v9, v26, v9
v_pk_add_f16 v22, v39, v22
v_pk_add_f16 v15, v73, v15
v_pk_add_f16 v16, v26, v16
v_pk_add_f16 v21, v39, v21
v_pk_add_f16 v13, v73, v13
v_pk_add_f16 v14, v26, v14
v_pk_add_f16 v24, v39, v24
v_pk_add_f16 v19, v73, v19
v_pk_add_f16 v20, v26, v20
v_lshlrev_b64 v[33:34], 1, v[33:34]
v_pk_max_f16 v12, v12, 0
v_pk_max_f16 v6, v6, 0
v_add_co_ci_u32_e32 v66, vcc_lo, s7, v66, vcc_lo
v_pk_max_f16 v7, v7, 0
v_add_co_u32 v67, vcc_lo, s6, v67
v_lshlrev_b64 v[69:70], 1, v[69:70]
v_pk_max_f16 v18, v18, 0
v_pk_max_f16 v10, v10, 0
v_add_co_ci_u32_e32 v68, vcc_lo, s7, v68, vcc_lo
v_pk_max_f16 v11, v11, 0
v_pk_max_f16 v17, v17, 0
v_pk_max_f16 v8, v8, 0
v_pk_max_f16 v9, v9, 0
v_pk_max_f16 v22, v22, 0
v_pk_max_f16 v15, v15, 0
v_pk_max_f16 v16, v16, 0
v_pk_max_f16 v21, v21, 0
v_pk_max_f16 v13, v13, 0
v_pk_max_f16 v14, v14, 0
v_pk_max_f16 v24, v24, 0
v_pk_max_f16 v19, v19, 0
v_pk_max_f16 v20, v20, 0
global_store_dword v[43:44], v12, off
global_store_dword v[45:46], v6, off
global_store_dword v[47:48], v7, off
global_store_dword v[49:50], v18, off
global_store_dword v[51:52], v10, off
global_store_dword v[55:56], v11, off
global_store_dword v[57:58], v17, off
global_store_dword v[59:60], v8, off
global_store_dword v[31:32], v9, off
global_store_dword v[35:36], v22, off
global_store_dword v[37:38], v15, off
global_store_dword v[53:54], v16, off
global_store_dword v[27:28], v21, off
global_store_dword v[29:30], v13, off
global_store_dword v[41:42], v14, off
global_store_dword v[61:62], v24, off
global_store_dword v[63:64], v19, off
global_store_dword v[65:66], v20, off
v_add_nc_u32_e32 v6, 0x19040, v40
v_add_co_u32 v33, vcc_lo, s6, v33
v_pk_add_f16 v5, v73, v5
v_add_co_ci_u32_e32 v34, vcc_lo, s7, v34, vcc_lo
v_add_nc_u32_e32 v8, 0x19050, v40
v_add_co_u32 v69, vcc_lo, s6, v69
v_pk_add_f16 v10, v26, v4
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_ci_u32_e32 v70, vcc_lo, s7, v70, vcc_lo
v_pk_max_f16 v5, v5, 0
v_add_nc_u32_e32 v4, 0x19060, v40
v_ashrrev_i32_e32 v9, 31, v8
v_pk_max_f16 v12, v10, 0
v_add_nc_u32_e32 v10, 0x19070, v40
v_lshlrev_b64 v[6:7], 1, v[6:7]
global_store_dword v[69:70], v5, off
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v71, vcc_lo, s6, v71
v_lshlrev_b64 v[8:9], 1, v[8:9]
v_ashrrev_i32_e32 v11, 31, v10
v_add_co_ci_u32_e32 v72, vcc_lo, s7, v72, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v6
v_lshlrev_b64 v[4:5], 1, v[4:5]
v_pk_add_f16 v25, v78, v25
v_pk_add_f16 v23, v39, v23
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v8
v_pk_add_f16 v3, v78, v3
v_lshlrev_b64 v[10:11], 1, v[10:11]
v_pk_add_f16 v2, v39, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
v_pk_add_f16 v13, v73, v1
v_add_co_u32 v4, vcc_lo, s6, v4
v_pk_add_f16 v14, v26, v0
v_pk_max_f16 v25, v25, 0
v_pk_max_f16 v23, v23, 0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_pk_max_f16 v3, v3, 0
v_add_co_u32 v0, vcc_lo, s6, v10
v_pk_max_f16 v2, v2, 0
v_pk_max_f16 v10, v13, 0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v11, vcc_lo
v_pk_max_f16 v11, v14, 0
global_store_dword v[67:68], v25, off
global_store_dword v[33:34], v23, off
global_store_dword v[71:72], v12, off
global_store_dword v[6:7], v3, off
global_store_dword v[8:9], v2, off
global_store_dword v[4:5], v10, off
global_store_dword v[0:1], v11, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_conv2d_add_nn_relu_kernel0
.amdhsa_group_segment_fixed_size 36672
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 82
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end64:
.size tvmgen_default_fused_nn_conv2d_add_nn_relu_kernel0, .Lfunc_end64-tvmgen_default_fused_nn_conv2d_add_nn_relu_kernel0
.globl tvmgen_default_fused_nn_dense_1_kernel0
.p2align 8
.type tvmgen_default_fused_nn_dense_1_kernel0,@function
tvmgen_default_fused_nn_dense_1_kernel0:
s_clause 0x2
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
v_lshlrev_b32_e32 v3, 6, v0
v_and_b32_e32 v1, 31, v0
v_lshlrev_b32_e32 v2, 3, v0
s_ashr_i32 s1, s6, 2
s_mov_b32 s7, 0x8000
v_lshl_or_b32 v3, s6, 17, v3
s_mul_i32 s0, s1, 0x1e00
v_and_or_b32 v1, 0x1f00, v2, v1
v_and_b32_e32 v2, 24, v2
v_lshl_or_b32 v59, v0, 1, s7
v_cmp_gt_i32_e32 vcc_lo, 64, v0
v_lshlrev_b32_e32 v61, 4, v0
v_add_nc_u32_e32 v58, s0, v1
v_and_or_b32 v60, 0x6ff00, v3, v2
v_lshlrev_b32_e32 v62, 7, v0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v24, 0
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v28, 0
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v29, 0
v_mov_b32_e32 v30, 0
v_mov_b32_e32 v31, 0
v_mov_b32_e32 v32, 0
v_mov_b32_e32 v33, 0
v_mov_b32_e32 v34, 0
v_mov_b32_e32 v36, 0
v_mov_b32_e32 v35, 0
v_mov_b32_e32 v38, 0
v_mov_b32_e32 v37, 0
v_mov_b32_e32 v39, 0
v_mov_b32_e32 v40, 0
v_mov_b32_e32 v41, 0
v_mov_b32_e32 v42, 0
v_mov_b32_e32 v43, 0
v_mov_b32_e32 v44, 0
v_mov_b32_e32 v46, 0
v_mov_b32_e32 v45, 0
v_mov_b32_e32 v48, 0
v_mov_b32_e32 v47, 0
v_mov_b32_e32 v49, 0
v_mov_b32_e32 v50, 0
v_mov_b32_e32 v51, 0
v_mov_b32_e32 v52, 0
v_mov_b32_e32 v53, 0
v_mov_b32_e32 v54, 0
v_mov_b32_e32 v56, 0
v_mov_b32_e32 v55, 0
v_mov_b32_e32 v63, 0
v_mov_b32_e32 v57, 0
v_mov_b32_e32 v64, 0
v_mov_b32_e32 v65, 0
s_mov_b32 s4, 0
BB65_1:
s_lshl_b32 s5, s4, 5
v_add_nc_u32_e32 v66, s5, v58
v_ashrrev_i32_e32 v67, 31, v66
v_lshlrev_b64 v[66:67], 1, v[66:67]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v66, s0, s8, v66
v_add_co_ci_u32_e64 v67, s0, s9, v67, s0
v_add_co_u32 v68, s0, v66, 0x1000
v_add_co_ci_u32_e64 v69, s0, 0, v67, s0
v_add_co_u32 v70, s0, v66, 0x2000
v_add_co_ci_u32_e64 v71, s0, 0, v67, s0
v_add_co_u32 v72, s0, v66, 0x3000
v_add_co_ci_u32_e64 v73, s0, 0, v67, s0
s_clause 0x6
global_load_ushort v74, v[66:67], off
global_load_ushort v75, v[68:69], off offset:-2048
global_load_ushort v68, v[68:69], off
global_load_ushort v69, v[70:71], off offset:-2048
global_load_ushort v70, v[70:71], off
global_load_ushort v71, v[72:73], off offset:-2048
global_load_ushort v72, v[72:73], off
s_waitcnt vmcnt(0)
s_barrier
ds_write_b16 v59, v74
ds_write_b16 v59, v75 offset:256
ds_write_b16 v59, v68 offset:512
ds_write_b16 v59, v69 offset:768
ds_write_b16 v59, v70 offset:1024
ds_write_b16 v59, v71 offset:1280
ds_write_b16 v59, v72 offset:1536
s_and_saveexec_b32 s12, vcc_lo
s_cbranch_execz BB65_3
v_add_co_u32 v66, s0, 0x3800, v66
v_add_co_ci_u32_e64 v67, s0, 0, v67, s0
global_load_ushort v66, v[66:67], off
s_waitcnt vmcnt(0)
ds_write_b16 v59, v66 offset:1792
BB65_3:
s_or_b32 exec_lo, exec_lo, s12
v_add_nc_u32_e32 v66, s5, v60
v_ashrrev_i32_e32 v67, 31, v66
v_lshlrev_b64 v[66:67], 1, v[66:67]
v_add_co_u32 v74, s0, s10, v66
v_add_co_ci_u32_e64 v75, s0, s11, v67, s0
v_add_co_u32 v70, s0, 0x4000, v74
v_add_co_ci_u32_e64 v71, s0, 0, v75, s0
v_add_co_u32 v76, s0, s7, v74
v_add_co_ci_u32_e64 v77, s0, 0, v75, s0
s_clause 0x1
global_load_dwordx4 v[66:69], v[74:75], off
global_load_dwordx4 v[70:73], v[70:71], off
v_add_co_u32 v78, s0, 0xc000, v74
v_add_co_ci_u32_e64 v79, s0, 0, v75, s0
v_add_co_u32 v82, s0, 0x10000, v74
v_add_co_ci_u32_e64 v83, s0, 0, v75, s0
v_add_co_u32 v86, s0, 0x14000, v74
v_add_co_ci_u32_e64 v87, s0, 0, v75, s0
v_add_co_u32 v90, s0, 0x18000, v74
v_add_co_ci_u32_e64 v91, s0, 0, v75, s0
v_add_co_u32 v94, s0, 0x1c000, v74
v_add_co_ci_u32_e64 v95, s0, 0, v75, s0
v_add_co_u32 v98, s0, 0x20000, v74
v_add_co_ci_u32_e64 v99, s0, 0, v75, s0
v_add_co_u32 v102, s0, 0x24000, v74
v_add_co_ci_u32_e64 v103, s0, 0, v75, s0
v_add_co_u32 v106, s0, 0x28000, v74
v_add_co_ci_u32_e64 v107, s0, 0, v75, s0
v_add_co_u32 v110, s0, 0x2c000, v74
v_add_co_ci_u32_e64 v111, s0, 0, v75, s0
v_add_co_u32 v114, s0, 0x30000, v74
v_add_co_ci_u32_e64 v115, s0, 0, v75, s0
v_add_co_u32 v116, s0, 0x34000, v74
v_add_co_ci_u32_e64 v117, s0, 0, v75, s0
v_add_co_u32 v118, s0, 0x38000, v74
v_add_co_ci_u32_e64 v119, s0, 0, v75, s0
v_add_co_u32 v120, s0, 0x3c000, v74
v_add_co_ci_u32_e64 v121, s0, 0, v75, s0
s_clause 0x9
global_load_dwordx4 v[74:77], v[76:77], off
global_load_dwordx4 v[78:81], v[78:79], off
global_load_dwordx4 v[82:85], v[82:83], off
global_load_dwordx4 v[86:89], v[86:87], off
global_load_dwordx4 v[90:93], v[90:91], off
global_load_dwordx4 v[94:97], v[94:95], off
global_load_dwordx4 v[98:101], v[98:99], off
global_load_dwordx4 v[102:105], v[102:103], off
global_load_dwordx4 v[106:109], v[106:107], off
global_load_dwordx4 v[110:113], v[110:111], off
s_mov_b32 s0, 0
s_waitcnt vmcnt(11)
ds_write_b128 v61, v[66:69]
s_clause 0x1
global_load_dwordx4 v[66:69], v[114:115], off
global_load_dwordx4 v[114:117], v[116:117], off
s_waitcnt vmcnt(12)
ds_write_b128 v61, v[70:73] offset:2048
s_clause 0x1
global_load_dwordx4 v[70:73], v[118:119], off
global_load_dwordx4 v[118:121], v[120:121], off
s_waitcnt vmcnt(13)
ds_write_b128 v61, v[74:77] offset:4096
s_waitcnt vmcnt(12)
ds_write_b128 v61, v[78:81] offset:6144
s_waitcnt vmcnt(11)
ds_write_b128 v61, v[82:85] offset:8192
s_waitcnt vmcnt(10)
ds_write_b128 v61, v[86:89] offset:10240
s_waitcnt vmcnt(9)
ds_write_b128 v61, v[90:93] offset:12288
s_waitcnt vmcnt(8)
ds_write_b128 v61, v[94:97] offset:14336
s_waitcnt vmcnt(7)
ds_write_b128 v61, v[98:101] offset:16384
s_waitcnt vmcnt(6)
ds_write_b128 v61, v[102:105] offset:18432
s_waitcnt vmcnt(5)
ds_write_b128 v61, v[106:109] offset:20480
s_waitcnt vmcnt(4)
ds_write_b128 v61, v[110:113] offset:22528
s_waitcnt vmcnt(3)
ds_write_b128 v61, v[66:69] offset:24576
s_waitcnt vmcnt(2)
ds_write_b128 v61, v[114:117] offset:26624
s_waitcnt vmcnt(1)
ds_write_b128 v61, v[70:73] offset:28672
s_waitcnt vmcnt(0)
ds_write_b128 v61, v[118:121] offset:30720
s_waitcnt lgkmcnt(0)
s_barrier
BB65_4:
s_lshl_b32 s5, s0, 3
v_mov_b32_e32 v70, 0xffff
v_add_lshl_u32 v71, s5, v62, 1
s_lshl_b32 s5, s0, 4
s_add_i32 s0, s0, 1
s_cmp_lg_u32 s0, 4
ds_read_b128 v[66:69], v71
ds_read_b128 v[82:85], v71 offset:64
s_waitcnt lgkmcnt(1)
v_and_b32_e32 v72, v70, v66
v_and_b32_e32 v73, v70, v67
v_and_b32_sdwa v74, v70, v66 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v75, v70, v67 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v76, v70, v68
v_and_b32_sdwa v78, v70, v68 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v79, v70, v69
v_and_b32_sdwa v90, v70, v69 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
ds_read_b128 v[66:69], v71 offset:128
ds_read_b128 v[86:89], v71 offset:192
s_waitcnt lgkmcnt(2)
v_lshl_or_b32 v81, v82, 16, v72
v_lshl_or_b32 v77, v83, 16, v73
v_lshl_or_b32 v73, v84, 16, v76
s_waitcnt lgkmcnt(1)
v_and_b32_e32 v71, v70, v66
v_and_b32_sdwa v91, v70, v66 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v92, v70, v67
v_and_b32_sdwa v93, v70, v67 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v67, v70, v68
v_and_b32_sdwa v94, v70, v68 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v68, v70, v69
v_and_b32_sdwa v69, v70, v69 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v70, 16, v82
v_lshrrev_b32_e32 v82, 16, v83
v_lshl_or_b32 v66, v85, 16, v79
v_lshrrev_b32_e32 v83, 16, v84
v_lshrrev_b32_e32 v84, 16, v85
s_waitcnt lgkmcnt(0)
v_lshl_or_b32 v80, v86, 16, v71
v_lshl_or_b32 v72, v88, 16, v67
v_lshrrev_b32_e32 v85, 16, v86
v_lshl_or_b32 v75, v82, 16, v75
v_lshl_or_b32 v76, v87, 16, v92
v_lshrrev_b32_e32 v86, 16, v87
v_lshrrev_b32_e32 v87, 16, v88
v_lshrrev_b32_e32 v88, 16, v89
v_mov_b32_e32 v82, s5
v_lshl_or_b32 v79, v70, 16, v74
v_lshl_or_b32 v67, v89, 16, v68
v_lshl_or_b32 v71, v83, 16, v78
v_lshl_or_b32 v68, v84, 16, v90
v_lshl_or_b32 v78, v85, 16, v91
v_lshl_or_b32 v74, v86, 16, v93
v_lshl_or_b32 v70, v87, 16, v94
v_lshl_or_b32 v69, v88, 16, v69
ds_read_b128 v[83:86], v82 offset:32768
ds_read_b128 v[87:90], v82 offset:32832
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v64, v83, v81, v64 op_sel_hi:[0,1,1]
v_pk_fma_f16 v65, v83, v80, v65 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v63, v87, v81, v63 op_sel_hi:[0,1,1]
v_pk_fma_f16 v57, v87, v80, v57 op_sel_hi:[0,1,1]
v_pk_fma_f16 v64, v83, v79, v64 op_sel:[1,0,0]
v_pk_fma_f16 v65, v83, v78, v65 op_sel:[1,0,0]
v_pk_fma_f16 v63, v87, v79, v63 op_sel:[1,0,0]
v_pk_fma_f16 v57, v87, v78, v57 op_sel:[1,0,0]
v_pk_fma_f16 v64, v84, v77, v64 op_sel_hi:[0,1,1]
v_pk_fma_f16 v65, v84, v76, v65 op_sel_hi:[0,1,1]
v_pk_fma_f16 v63, v88, v77, v63 op_sel_hi:[0,1,1]
v_pk_fma_f16 v57, v88, v76, v57 op_sel_hi:[0,1,1]
v_pk_fma_f16 v64, v84, v75, v64 op_sel:[1,0,0]
v_pk_fma_f16 v65, v84, v74, v65 op_sel:[1,0,0]
v_pk_fma_f16 v63, v88, v75, v63 op_sel:[1,0,0]
v_pk_fma_f16 v57, v88, v74, v57 op_sel:[1,0,0]
v_pk_fma_f16 v64, v85, v73, v64 op_sel_hi:[0,1,1]
v_pk_fma_f16 v65, v85, v72, v65 op_sel_hi:[0,1,1]
v_pk_fma_f16 v63, v89, v73, v63 op_sel_hi:[0,1,1]
v_pk_fma_f16 v57, v89, v72, v57 op_sel_hi:[0,1,1]
v_pk_fma_f16 v64, v85, v71, v64 op_sel:[1,0,0]
v_pk_fma_f16 v65, v85, v70, v65 op_sel:[1,0,0]
v_pk_fma_f16 v63, v89, v71, v63 op_sel:[1,0,0]
v_pk_fma_f16 v57, v89, v70, v57 op_sel:[1,0,0]
v_pk_fma_f16 v64, v86, v66, v64 op_sel_hi:[0,1,1]
v_pk_fma_f16 v65, v86, v67, v65 op_sel_hi:[0,1,1]
v_pk_fma_f16 v63, v90, v66, v63 op_sel_hi:[0,1,1]
v_pk_fma_f16 v57, v90, v67, v57 op_sel_hi:[0,1,1]
v_pk_fma_f16 v64, v86, v68, v64 op_sel:[1,0,0]
v_pk_fma_f16 v65, v86, v69, v65 op_sel:[1,0,0]
v_pk_fma_f16 v63, v90, v68, v63 op_sel:[1,0,0]
v_pk_fma_f16 v57, v90, v69, v57 op_sel:[1,0,0]
ds_read_b128 v[83:86], v82 offset:32896
ds_read_b128 v[87:90], v82 offset:32960
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v56, v83, v81, v56 op_sel_hi:[0,1,1]
v_pk_fma_f16 v55, v83, v80, v55 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v53, v87, v81, v53 op_sel_hi:[0,1,1]
v_pk_fma_f16 v54, v87, v80, v54 op_sel_hi:[0,1,1]
v_pk_fma_f16 v56, v83, v79, v56 op_sel:[1,0,0]
v_pk_fma_f16 v55, v83, v78, v55 op_sel:[1,0,0]
v_pk_fma_f16 v53, v87, v79, v53 op_sel:[1,0,0]
v_pk_fma_f16 v54, v87, v78, v54 op_sel:[1,0,0]
v_pk_fma_f16 v56, v84, v77, v56 op_sel_hi:[0,1,1]
v_pk_fma_f16 v55, v84, v76, v55 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v88, v77, v53 op_sel_hi:[0,1,1]
v_pk_fma_f16 v54, v88, v76, v54 op_sel_hi:[0,1,1]
v_pk_fma_f16 v56, v84, v75, v56 op_sel:[1,0,0]
v_pk_fma_f16 v55, v84, v74, v55 op_sel:[1,0,0]
v_pk_fma_f16 v53, v88, v75, v53 op_sel:[1,0,0]
v_pk_fma_f16 v54, v88, v74, v54 op_sel:[1,0,0]
v_pk_fma_f16 v56, v85, v73, v56 op_sel_hi:[0,1,1]
v_pk_fma_f16 v55, v85, v72, v55 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v89, v73, v53 op_sel_hi:[0,1,1]
v_pk_fma_f16 v54, v89, v72, v54 op_sel_hi:[0,1,1]
v_pk_fma_f16 v56, v85, v71, v56 op_sel:[1,0,0]
v_pk_fma_f16 v55, v85, v70, v55 op_sel:[1,0,0]
v_pk_fma_f16 v53, v89, v71, v53 op_sel:[1,0,0]
v_pk_fma_f16 v54, v89, v70, v54 op_sel:[1,0,0]
v_pk_fma_f16 v56, v86, v66, v56 op_sel_hi:[0,1,1]
v_pk_fma_f16 v55, v86, v67, v55 op_sel_hi:[0,1,1]
v_pk_fma_f16 v53, v90, v66, v53 op_sel_hi:[0,1,1]
v_pk_fma_f16 v54, v90, v67, v54 op_sel_hi:[0,1,1]
v_pk_fma_f16 v56, v86, v68, v56 op_sel:[1,0,0]
v_pk_fma_f16 v55, v86, v69, v55 op_sel:[1,0,0]
v_pk_fma_f16 v53, v90, v68, v53 op_sel:[1,0,0]
v_pk_fma_f16 v54, v90, v69, v54 op_sel:[1,0,0]
ds_read_b128 v[83:86], v82 offset:33024
ds_read_b128 v[87:90], v82 offset:33088
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v51, v83, v81, v51 op_sel_hi:[0,1,1]
v_pk_fma_f16 v52, v83, v80, v52 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v49, v87, v81, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v87, v80, v50 op_sel_hi:[0,1,1]
v_pk_fma_f16 v51, v83, v79, v51 op_sel:[1,0,0]
v_pk_fma_f16 v52, v83, v78, v52 op_sel:[1,0,0]
v_pk_fma_f16 v49, v87, v79, v49 op_sel:[1,0,0]
v_pk_fma_f16 v50, v87, v78, v50 op_sel:[1,0,0]
v_pk_fma_f16 v51, v84, v77, v51 op_sel_hi:[0,1,1]
v_pk_fma_f16 v52, v84, v76, v52 op_sel_hi:[0,1,1]
v_pk_fma_f16 v49, v88, v77, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v88, v76, v50 op_sel_hi:[0,1,1]
v_pk_fma_f16 v51, v84, v75, v51 op_sel:[1,0,0]
v_pk_fma_f16 v52, v84, v74, v52 op_sel:[1,0,0]
v_pk_fma_f16 v49, v88, v75, v49 op_sel:[1,0,0]
v_pk_fma_f16 v50, v88, v74, v50 op_sel:[1,0,0]
v_pk_fma_f16 v51, v85, v73, v51 op_sel_hi:[0,1,1]
v_pk_fma_f16 v52, v85, v72, v52 op_sel_hi:[0,1,1]
v_pk_fma_f16 v49, v89, v73, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v89, v72, v50 op_sel_hi:[0,1,1]
v_pk_fma_f16 v51, v85, v71, v51 op_sel:[1,0,0]
v_pk_fma_f16 v52, v85, v70, v52 op_sel:[1,0,0]
v_pk_fma_f16 v49, v89, v71, v49 op_sel:[1,0,0]
v_pk_fma_f16 v50, v89, v70, v50 op_sel:[1,0,0]
v_pk_fma_f16 v51, v86, v66, v51 op_sel_hi:[0,1,1]
v_pk_fma_f16 v52, v86, v67, v52 op_sel_hi:[0,1,1]
v_pk_fma_f16 v49, v90, v66, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v50, v90, v67, v50 op_sel_hi:[0,1,1]
v_pk_fma_f16 v51, v86, v68, v51 op_sel:[1,0,0]
v_pk_fma_f16 v52, v86, v69, v52 op_sel:[1,0,0]
v_pk_fma_f16 v49, v90, v68, v49 op_sel:[1,0,0]
v_pk_fma_f16 v50, v90, v69, v50 op_sel:[1,0,0]
ds_read_b128 v[83:86], v82 offset:33152
ds_read_b128 v[87:90], v82 offset:33216
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v48, v83, v81, v48 op_sel_hi:[0,1,1]
v_pk_fma_f16 v47, v83, v80, v47 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v46, v87, v81, v46 op_sel_hi:[0,1,1]
v_pk_fma_f16 v45, v87, v80, v45 op_sel_hi:[0,1,1]
v_pk_fma_f16 v48, v83, v79, v48 op_sel:[1,0,0]
v_pk_fma_f16 v47, v83, v78, v47 op_sel:[1,0,0]
v_pk_fma_f16 v46, v87, v79, v46 op_sel:[1,0,0]
v_pk_fma_f16 v45, v87, v78, v45 op_sel:[1,0,0]
v_pk_fma_f16 v48, v84, v77, v48 op_sel_hi:[0,1,1]
v_pk_fma_f16 v47, v84, v76, v47 op_sel_hi:[0,1,1]
v_pk_fma_f16 v46, v88, v77, v46 op_sel_hi:[0,1,1]
v_pk_fma_f16 v45, v88, v76, v45 op_sel_hi:[0,1,1]
v_pk_fma_f16 v48, v84, v75, v48 op_sel:[1,0,0]
v_pk_fma_f16 v47, v84, v74, v47 op_sel:[1,0,0]
v_pk_fma_f16 v46, v88, v75, v46 op_sel:[1,0,0]
v_pk_fma_f16 v45, v88, v74, v45 op_sel:[1,0,0]
v_pk_fma_f16 v48, v85, v73, v48 op_sel_hi:[0,1,1]
v_pk_fma_f16 v47, v85, v72, v47 op_sel_hi:[0,1,1]
v_pk_fma_f16 v46, v89, v73, v46 op_sel_hi:[0,1,1]
v_pk_fma_f16 v45, v89, v72, v45 op_sel_hi:[0,1,1]
v_pk_fma_f16 v48, v85, v71, v48 op_sel:[1,0,0]
v_pk_fma_f16 v47, v85, v70, v47 op_sel:[1,0,0]
v_pk_fma_f16 v46, v89, v71, v46 op_sel:[1,0,0]
v_pk_fma_f16 v45, v89, v70, v45 op_sel:[1,0,0]
v_pk_fma_f16 v48, v86, v66, v48 op_sel_hi:[0,1,1]
v_pk_fma_f16 v47, v86, v67, v47 op_sel_hi:[0,1,1]
v_pk_fma_f16 v46, v90, v66, v46 op_sel_hi:[0,1,1]
v_pk_fma_f16 v45, v90, v67, v45 op_sel_hi:[0,1,1]
v_pk_fma_f16 v48, v86, v68, v48 op_sel:[1,0,0]
v_pk_fma_f16 v47, v86, v69, v47 op_sel:[1,0,0]
v_pk_fma_f16 v46, v90, v68, v46 op_sel:[1,0,0]
v_pk_fma_f16 v45, v90, v69, v45 op_sel:[1,0,0]
ds_read_b128 v[83:86], v82 offset:33280
ds_read_b128 v[87:90], v82 offset:33344
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v43, v83, v81, v43 op_sel_hi:[0,1,1]
v_pk_fma_f16 v44, v83, v80, v44 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v41, v87, v81, v41 op_sel_hi:[0,1,1]
v_pk_fma_f16 v42, v87, v80, v42 op_sel_hi:[0,1,1]
v_pk_fma_f16 v43, v83, v79, v43 op_sel:[1,0,0]
v_pk_fma_f16 v44, v83, v78, v44 op_sel:[1,0,0]
v_pk_fma_f16 v41, v87, v79, v41 op_sel:[1,0,0]
v_pk_fma_f16 v42, v87, v78, v42 op_sel:[1,0,0]
v_pk_fma_f16 v43, v84, v77, v43 op_sel_hi:[0,1,1]
v_pk_fma_f16 v44, v84, v76, v44 op_sel_hi:[0,1,1]
v_pk_fma_f16 v41, v88, v77, v41 op_sel_hi:[0,1,1]
v_pk_fma_f16 v42, v88, v76, v42 op_sel_hi:[0,1,1]
v_pk_fma_f16 v43, v84, v75, v43 op_sel:[1,0,0]
v_pk_fma_f16 v44, v84, v74, v44 op_sel:[1,0,0]
v_pk_fma_f16 v41, v88, v75, v41 op_sel:[1,0,0]
v_pk_fma_f16 v42, v88, v74, v42 op_sel:[1,0,0]
v_pk_fma_f16 v43, v85, v73, v43 op_sel_hi:[0,1,1]
v_pk_fma_f16 v44, v85, v72, v44 op_sel_hi:[0,1,1]
v_pk_fma_f16 v41, v89, v73, v41 op_sel_hi:[0,1,1]
v_pk_fma_f16 v42, v89, v72, v42 op_sel_hi:[0,1,1]
v_pk_fma_f16 v43, v85, v71, v43 op_sel:[1,0,0]
v_pk_fma_f16 v44, v85, v70, v44 op_sel:[1,0,0]
v_pk_fma_f16 v41, v89, v71, v41 op_sel:[1,0,0]
v_pk_fma_f16 v42, v89, v70, v42 op_sel:[1,0,0]
v_pk_fma_f16 v43, v86, v66, v43 op_sel_hi:[0,1,1]
v_pk_fma_f16 v44, v86, v67, v44 op_sel_hi:[0,1,1]
v_pk_fma_f16 v41, v90, v66, v41 op_sel_hi:[0,1,1]
v_pk_fma_f16 v42, v90, v67, v42 op_sel_hi:[0,1,1]
v_pk_fma_f16 v43, v86, v68, v43 op_sel:[1,0,0]
v_pk_fma_f16 v44, v86, v69, v44 op_sel:[1,0,0]
v_pk_fma_f16 v41, v90, v68, v41 op_sel:[1,0,0]
v_pk_fma_f16 v42, v90, v69, v42 op_sel:[1,0,0]
ds_read_b128 v[83:86], v82 offset:33408
ds_read_b128 v[87:90], v82 offset:33472
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v39, v83, v81, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v40, v83, v80, v40 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v38, v87, v81, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v87, v80, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v39, v83, v79, v39 op_sel:[1,0,0]
v_pk_fma_f16 v40, v83, v78, v40 op_sel:[1,0,0]
v_pk_fma_f16 v38, v87, v79, v38 op_sel:[1,0,0]
v_pk_fma_f16 v37, v87, v78, v37 op_sel:[1,0,0]
v_pk_fma_f16 v39, v84, v77, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v40, v84, v76, v40 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v88, v77, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v88, v76, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v39, v84, v75, v39 op_sel:[1,0,0]
v_pk_fma_f16 v40, v84, v74, v40 op_sel:[1,0,0]
v_pk_fma_f16 v38, v88, v75, v38 op_sel:[1,0,0]
v_pk_fma_f16 v37, v88, v74, v37 op_sel:[1,0,0]
v_pk_fma_f16 v39, v85, v73, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v40, v85, v72, v40 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v89, v73, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v89, v72, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v39, v85, v71, v39 op_sel:[1,0,0]
v_pk_fma_f16 v40, v85, v70, v40 op_sel:[1,0,0]
v_pk_fma_f16 v38, v89, v71, v38 op_sel:[1,0,0]
v_pk_fma_f16 v37, v89, v70, v37 op_sel:[1,0,0]
v_pk_fma_f16 v39, v86, v66, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v40, v86, v67, v40 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v90, v66, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v90, v67, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v39, v86, v68, v39 op_sel:[1,0,0]
v_pk_fma_f16 v40, v86, v69, v40 op_sel:[1,0,0]
v_pk_fma_f16 v38, v90, v68, v38 op_sel:[1,0,0]
v_pk_fma_f16 v37, v90, v69, v37 op_sel:[1,0,0]
ds_read_b128 v[83:86], v82 offset:33536
ds_read_b128 v[87:90], v82 offset:33600
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v36, v83, v81, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v83, v80, v35 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v33, v87, v81, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v87, v80, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v83, v79, v36 op_sel:[1,0,0]
v_pk_fma_f16 v35, v83, v78, v35 op_sel:[1,0,0]
v_pk_fma_f16 v33, v87, v79, v33 op_sel:[1,0,0]
v_pk_fma_f16 v34, v87, v78, v34 op_sel:[1,0,0]
v_pk_fma_f16 v36, v84, v77, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v84, v76, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v88, v77, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v88, v76, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v84, v75, v36 op_sel:[1,0,0]
v_pk_fma_f16 v35, v84, v74, v35 op_sel:[1,0,0]
v_pk_fma_f16 v33, v88, v75, v33 op_sel:[1,0,0]
v_pk_fma_f16 v34, v88, v74, v34 op_sel:[1,0,0]
v_pk_fma_f16 v36, v85, v73, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v85, v72, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v89, v73, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v89, v72, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v85, v71, v36 op_sel:[1,0,0]
v_pk_fma_f16 v35, v85, v70, v35 op_sel:[1,0,0]
v_pk_fma_f16 v33, v89, v71, v33 op_sel:[1,0,0]
v_pk_fma_f16 v34, v89, v70, v34 op_sel:[1,0,0]
v_pk_fma_f16 v36, v86, v66, v36 op_sel_hi:[0,1,1]
v_pk_fma_f16 v35, v86, v67, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v90, v66, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v90, v67, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v36, v86, v68, v36 op_sel:[1,0,0]
v_pk_fma_f16 v35, v86, v69, v35 op_sel:[1,0,0]
v_pk_fma_f16 v33, v90, v68, v33 op_sel:[1,0,0]
v_pk_fma_f16 v34, v90, v69, v34 op_sel:[1,0,0]
ds_read_b128 v[83:86], v82 offset:33664
ds_read_b128 v[87:90], v82 offset:33728
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v31, v83, v81, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v83, v80, v32 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v29, v87, v81, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v87, v80, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v83, v79, v31 op_sel:[1,0,0]
v_pk_fma_f16 v32, v83, v78, v32 op_sel:[1,0,0]
v_pk_fma_f16 v29, v87, v79, v29 op_sel:[1,0,0]
v_pk_fma_f16 v30, v87, v78, v30 op_sel:[1,0,0]
v_pk_fma_f16 v31, v84, v77, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v84, v76, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v88, v77, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v88, v76, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v84, v75, v31 op_sel:[1,0,0]
v_pk_fma_f16 v32, v84, v74, v32 op_sel:[1,0,0]
v_pk_fma_f16 v29, v88, v75, v29 op_sel:[1,0,0]
v_pk_fma_f16 v30, v88, v74, v30 op_sel:[1,0,0]
v_pk_fma_f16 v31, v85, v73, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v85, v72, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v89, v73, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v89, v72, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v85, v71, v31 op_sel:[1,0,0]
v_pk_fma_f16 v32, v85, v70, v32 op_sel:[1,0,0]
v_pk_fma_f16 v29, v89, v71, v29 op_sel:[1,0,0]
v_pk_fma_f16 v30, v89, v70, v30 op_sel:[1,0,0]
v_pk_fma_f16 v31, v86, v66, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v86, v67, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v90, v66, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v90, v67, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v86, v68, v31 op_sel:[1,0,0]
v_pk_fma_f16 v32, v86, v69, v32 op_sel:[1,0,0]
v_pk_fma_f16 v29, v90, v68, v29 op_sel:[1,0,0]
v_pk_fma_f16 v30, v90, v69, v30 op_sel:[1,0,0]
ds_read_b128 v[83:86], v82 offset:33792
ds_read_b128 v[87:90], v82 offset:33856
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v28, v83, v81, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v83, v80, v27 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v26, v87, v81, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v87, v80, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v83, v79, v28 op_sel:[1,0,0]
v_pk_fma_f16 v27, v83, v78, v27 op_sel:[1,0,0]
v_pk_fma_f16 v26, v87, v79, v26 op_sel:[1,0,0]
v_pk_fma_f16 v25, v87, v78, v25 op_sel:[1,0,0]
v_pk_fma_f16 v28, v84, v77, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v84, v76, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v88, v77, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v88, v76, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v84, v75, v28 op_sel:[1,0,0]
v_pk_fma_f16 v27, v84, v74, v27 op_sel:[1,0,0]
v_pk_fma_f16 v26, v88, v75, v26 op_sel:[1,0,0]
v_pk_fma_f16 v25, v88, v74, v25 op_sel:[1,0,0]
v_pk_fma_f16 v28, v85, v73, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v85, v72, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v89, v73, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v89, v72, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v85, v71, v28 op_sel:[1,0,0]
v_pk_fma_f16 v27, v85, v70, v27 op_sel:[1,0,0]
v_pk_fma_f16 v26, v89, v71, v26 op_sel:[1,0,0]
v_pk_fma_f16 v25, v89, v70, v25 op_sel:[1,0,0]
v_pk_fma_f16 v28, v86, v66, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v86, v67, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v90, v66, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v90, v67, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v86, v68, v28 op_sel:[1,0,0]
v_pk_fma_f16 v27, v86, v69, v27 op_sel:[1,0,0]
v_pk_fma_f16 v26, v90, v68, v26 op_sel:[1,0,0]
v_pk_fma_f16 v25, v90, v69, v25 op_sel:[1,0,0]
ds_read_b128 v[83:86], v82 offset:33920
ds_read_b128 v[87:90], v82 offset:33984
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v23, v83, v81, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v83, v80, v24 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v21, v87, v81, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v87, v80, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v83, v79, v23 op_sel:[1,0,0]
v_pk_fma_f16 v24, v83, v78, v24 op_sel:[1,0,0]
v_pk_fma_f16 v21, v87, v79, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v87, v78, v22 op_sel:[1,0,0]
v_pk_fma_f16 v23, v84, v77, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v84, v76, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v88, v77, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v88, v76, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v84, v75, v23 op_sel:[1,0,0]
v_pk_fma_f16 v24, v84, v74, v24 op_sel:[1,0,0]
v_pk_fma_f16 v21, v88, v75, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v88, v74, v22 op_sel:[1,0,0]
v_pk_fma_f16 v23, v85, v73, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v85, v72, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v89, v73, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v89, v72, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v85, v71, v23 op_sel:[1,0,0]
v_pk_fma_f16 v24, v85, v70, v24 op_sel:[1,0,0]
v_pk_fma_f16 v21, v89, v71, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v89, v70, v22 op_sel:[1,0,0]
v_pk_fma_f16 v23, v86, v66, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v86, v67, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v90, v66, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v90, v67, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v86, v68, v23 op_sel:[1,0,0]
v_pk_fma_f16 v24, v86, v69, v24 op_sel:[1,0,0]
v_pk_fma_f16 v21, v90, v68, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v90, v69, v22 op_sel:[1,0,0]
ds_read_b128 v[83:86], v82 offset:34048
ds_read_b128 v[87:90], v82 offset:34112
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v19, v83, v81, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v83, v80, v20 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v18, v87, v81, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v87, v80, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v83, v79, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v83, v78, v20 op_sel:[1,0,0]
v_pk_fma_f16 v18, v87, v79, v18 op_sel:[1,0,0]
v_pk_fma_f16 v17, v87, v78, v17 op_sel:[1,0,0]
v_pk_fma_f16 v19, v84, v77, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v84, v76, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v88, v77, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v88, v76, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v84, v75, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v84, v74, v20 op_sel:[1,0,0]
v_pk_fma_f16 v18, v88, v75, v18 op_sel:[1,0,0]
v_pk_fma_f16 v17, v88, v74, v17 op_sel:[1,0,0]
v_pk_fma_f16 v19, v85, v73, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v85, v72, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v89, v73, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v89, v72, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v85, v71, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v85, v70, v20 op_sel:[1,0,0]
v_pk_fma_f16 v18, v89, v71, v18 op_sel:[1,0,0]
v_pk_fma_f16 v17, v89, v70, v17 op_sel:[1,0,0]
v_pk_fma_f16 v19, v86, v66, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v20, v86, v67, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v90, v66, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v90, v67, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v86, v68, v19 op_sel:[1,0,0]
v_pk_fma_f16 v20, v86, v69, v20 op_sel:[1,0,0]
v_pk_fma_f16 v18, v90, v68, v18 op_sel:[1,0,0]
v_pk_fma_f16 v17, v90, v69, v17 op_sel:[1,0,0]
ds_read_b128 v[83:86], v82 offset:34176
ds_read_b128 v[87:90], v82 offset:34240
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v16, v83, v81, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v83, v80, v15 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v13, v87, v81, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v87, v80, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v83, v79, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v83, v78, v15 op_sel:[1,0,0]
v_pk_fma_f16 v13, v87, v79, v13 op_sel:[1,0,0]
v_pk_fma_f16 v14, v87, v78, v14 op_sel:[1,0,0]
v_pk_fma_f16 v16, v84, v77, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v84, v76, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v88, v77, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v88, v76, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v84, v75, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v84, v74, v15 op_sel:[1,0,0]
v_pk_fma_f16 v13, v88, v75, v13 op_sel:[1,0,0]
v_pk_fma_f16 v14, v88, v74, v14 op_sel:[1,0,0]
v_pk_fma_f16 v16, v85, v73, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v85, v72, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v89, v73, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v89, v72, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v85, v71, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v85, v70, v15 op_sel:[1,0,0]
v_pk_fma_f16 v13, v89, v71, v13 op_sel:[1,0,0]
v_pk_fma_f16 v14, v89, v70, v14 op_sel:[1,0,0]
v_pk_fma_f16 v16, v86, v66, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v86, v67, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v90, v66, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v90, v67, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v86, v68, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v86, v69, v15 op_sel:[1,0,0]
v_pk_fma_f16 v13, v90, v68, v13 op_sel:[1,0,0]
v_pk_fma_f16 v14, v90, v69, v14 op_sel:[1,0,0]
ds_read_b128 v[83:86], v82 offset:34304
ds_read_b128 v[87:90], v82 offset:34368
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v10, v83, v81, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v83, v80, v12 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v7, v87, v81, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v87, v80, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v83, v79, v10 op_sel:[1,0,0]
v_pk_fma_f16 v12, v83, v78, v12 op_sel:[1,0,0]
v_pk_fma_f16 v7, v87, v79, v7 op_sel:[1,0,0]
v_pk_fma_f16 v8, v87, v78, v8 op_sel:[1,0,0]
v_pk_fma_f16 v10, v84, v77, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v84, v76, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v88, v77, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v88, v76, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v84, v75, v10 op_sel:[1,0,0]
v_pk_fma_f16 v12, v84, v74, v12 op_sel:[1,0,0]
v_pk_fma_f16 v7, v88, v75, v7 op_sel:[1,0,0]
v_pk_fma_f16 v8, v88, v74, v8 op_sel:[1,0,0]
v_pk_fma_f16 v10, v85, v73, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v85, v72, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v89, v73, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v89, v72, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v85, v71, v10 op_sel:[1,0,0]
v_pk_fma_f16 v12, v85, v70, v12 op_sel:[1,0,0]
v_pk_fma_f16 v7, v89, v71, v7 op_sel:[1,0,0]
v_pk_fma_f16 v8, v89, v70, v8 op_sel:[1,0,0]
v_pk_fma_f16 v10, v86, v66, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v86, v67, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v90, v66, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v90, v67, v8 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v86, v68, v10 op_sel:[1,0,0]
v_pk_fma_f16 v12, v86, v69, v12 op_sel:[1,0,0]
v_pk_fma_f16 v7, v90, v68, v7 op_sel:[1,0,0]
v_pk_fma_f16 v8, v90, v69, v8 op_sel:[1,0,0]
ds_read_b128 v[83:86], v82 offset:34432
ds_read_b128 v[87:90], v82 offset:34496
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v6, v83, v81, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v83, v80, v5 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v4, v87, v81, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v87, v80, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v83, v79, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v83, v78, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v87, v79, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v87, v78, v3 op_sel:[1,0,0]
v_pk_fma_f16 v6, v84, v77, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v84, v76, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v88, v77, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v88, v76, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v84, v75, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v84, v74, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v88, v75, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v88, v74, v3 op_sel:[1,0,0]
v_pk_fma_f16 v6, v85, v73, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v85, v72, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v89, v73, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v89, v72, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v85, v71, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v85, v70, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v89, v71, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v89, v70, v3 op_sel:[1,0,0]
v_pk_fma_f16 v6, v86, v66, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v86, v67, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v90, v66, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v3, v90, v67, v3 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v86, v68, v6 op_sel:[1,0,0]
v_pk_fma_f16 v5, v86, v69, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v90, v68, v4 op_sel:[1,0,0]
v_pk_fma_f16 v3, v90, v69, v3 op_sel:[1,0,0]
ds_read_b128 v[83:86], v82 offset:34560
ds_read_b128 v[87:90], v82 offset:34624
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v1, v83, v81, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v83, v80, v2 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v11, v87, v81, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v87, v80, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v83, v79, v1 op_sel:[1,0,0]
v_pk_fma_f16 v2, v83, v78, v2 op_sel:[1,0,0]
v_pk_fma_f16 v11, v87, v79, v11 op_sel:[1,0,0]
v_pk_fma_f16 v9, v87, v78, v9 op_sel:[1,0,0]
v_pk_fma_f16 v1, v84, v77, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v84, v76, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v88, v77, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v88, v76, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v84, v75, v1 op_sel:[1,0,0]
v_pk_fma_f16 v2, v84, v74, v2 op_sel:[1,0,0]
v_pk_fma_f16 v11, v88, v75, v11 op_sel:[1,0,0]
v_pk_fma_f16 v9, v88, v74, v9 op_sel:[1,0,0]
v_pk_fma_f16 v1, v85, v73, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v85, v72, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v89, v73, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v89, v72, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v85, v71, v1 op_sel:[1,0,0]
v_pk_fma_f16 v2, v85, v70, v2 op_sel:[1,0,0]
v_pk_fma_f16 v11, v89, v71, v11 op_sel:[1,0,0]
v_pk_fma_f16 v9, v89, v70, v9 op_sel:[1,0,0]
v_pk_fma_f16 v1, v86, v66, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v86, v67, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v90, v66, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v9, v90, v67, v9 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v86, v68, v1 op_sel:[1,0,0]
v_pk_fma_f16 v2, v86, v69, v2 op_sel:[1,0,0]
v_pk_fma_f16 v11, v90, v68, v11 op_sel:[1,0,0]
v_pk_fma_f16 v9, v90, v69, v9 op_sel:[1,0,0]
s_cbranch_scc1 BB65_4
s_add_i32 s4, s4, 1
s_cmp_eq_u32 s4, 8
s_cbranch_scc0 BB65_1
s_lshl_b32 s0, s6, 9
s_mul_i32 s1, s1, 0xf000
s_and_b32 s0, s0, 0x600
s_or_b32 s0, s0, s1
v_lshl_add_u32 v58, v0, 2, s0
v_add_nc_u32_e32 v60, 0x800, v58
v_ashrrev_i32_e32 v59, 31, v58
v_add_nc_u32_e32 v66, 0x802, v58
v_add_nc_u32_e32 v68, 0x1000, v58
v_add_nc_u32_e32 v72, 0x1002, v58
v_ashrrev_i32_e32 v61, 31, v60
v_lshlrev_b64 v[70:71], 1, v[58:59]
v_ashrrev_i32_e32 v67, 31, v66
v_ashrrev_i32_e32 v69, 31, v68
v_ashrrev_i32_e32 v73, 31, v72
v_lshlrev_b64 v[59:60], 1, v[60:61]
v_add_co_u32 v70, vcc_lo, s2, v70
v_lshlrev_b64 v[61:62], 1, v[66:67]
v_add_co_ci_u32_e32 v71, vcc_lo, s3, v71, vcc_lo
v_lshlrev_b64 v[66:67], 1, v[68:69]
v_add_co_u32 v59, vcc_lo, s2, v59
v_add_co_ci_u32_e32 v60, vcc_lo, s3, v60, vcc_lo
global_store_dword v[70:71], v64, off
global_store_dword v[70:71], v65, off offset:4
v_add_co_u32 v61, vcc_lo, s2, v61
v_add_nc_u32_e32 v65, 0x1802, v58
v_add_co_ci_u32_e32 v62, vcc_lo, s3, v62, vcc_lo
global_store_dword v[59:60], v63, off
v_add_nc_u32_e32 v59, 0x1800, v58
v_add_co_u32 v63, vcc_lo, s2, v66
v_ashrrev_i32_e32 v66, 31, v65
v_add_co_ci_u32_e32 v64, vcc_lo, s3, v67, vcc_lo
v_lshlrev_b64 v[67:68], 1, v[72:73]
v_ashrrev_i32_e32 v60, 31, v59
global_store_dword v[61:62], v57, off
global_store_dword v[63:64], v56, off
v_lshlrev_b64 v[61:62], 1, v[65:66]
v_add_nc_u32_e32 v63, 0x2000, v58
v_lshlrev_b64 v[56:57], 1, v[59:60]
v_add_co_u32 v59, vcc_lo, s2, v67
v_add_nc_u32_e32 v65, 0x2002, v58
v_add_co_ci_u32_e32 v60, vcc_lo, s3, v68, vcc_lo
v_ashrrev_i32_e32 v64, 31, v63
v_add_co_u32 v56, vcc_lo, s2, v56
v_ashrrev_i32_e32 v66, 31, v65
v_add_co_ci_u32_e32 v57, vcc_lo, s3, v57, vcc_lo
v_add_co_u32 v61, vcc_lo, s2, v61
global_store_dword v[59:60], v55, off
v_add_co_ci_u32_e32 v62, vcc_lo, s3, v62, vcc_lo
v_lshlrev_b64 v[59:60], 1, v[63:64]
v_add_nc_u32_e32 v63, 0x3000, v58
global_store_dword v[56:57], v53, off
global_store_dword v[61:62], v54, off
v_add_nc_u32_e32 v53, 0x2800, v58
v_lshlrev_b64 v[55:56], 1, v[65:66]
v_add_nc_u32_e32 v61, 0x2802, v58
v_add_co_u32 v59, vcc_lo, s2, v59
v_ashrrev_i32_e32 v64, 31, v63
v_ashrrev_i32_e32 v54, 31, v53
v_add_co_ci_u32_e32 v60, vcc_lo, s3, v60, vcc_lo
v_add_co_u32 v55, vcc_lo, s2, v55
v_ashrrev_i32_e32 v62, 31, v61
v_add_co_ci_u32_e32 v56, vcc_lo, s3, v56, vcc_lo
v_lshlrev_b64 v[53:54], 1, v[53:54]
global_store_dword v[59:60], v51, off
global_store_dword v[55:56], v52, off
v_lshlrev_b64 v[51:52], 1, v[61:62]
v_add_nc_u32_e32 v59, 0x3002, v58
v_add_co_u32 v53, vcc_lo, s2, v53
v_lshlrev_b64 v[55:56], 1, v[63:64]
v_add_co_ci_u32_e32 v54, vcc_lo, s3, v54, vcc_lo
v_add_nc_u32_e32 v61, 0x3800, v58
v_add_co_u32 v51, vcc_lo, s2, v51
v_ashrrev_i32_e32 v60, 31, v59
v_add_co_ci_u32_e32 v52, vcc_lo, s3, v52, vcc_lo
v_add_co_u32 v55, vcc_lo, s2, v55
global_store_dword v[53:54], v49, off
v_add_co_ci_u32_e32 v56, vcc_lo, s3, v56, vcc_lo
v_ashrrev_i32_e32 v62, 31, v61
v_lshlrev_b64 v[53:54], 1, v[59:60]
global_store_dword v[51:52], v50, off
global_store_dword v[55:56], v48, off
v_add_nc_u32_e32 v50, 0x3802, v58
v_lshlrev_b64 v[48:49], 1, v[61:62]
v_add_nc_u32_e32 v56, 0x4002, v58
v_add_co_u32 v52, vcc_lo, s2, v53
v_add_co_ci_u32_e32 v53, vcc_lo, s3, v54, vcc_lo
v_ashrrev_i32_e32 v51, 31, v50
v_add_nc_u32_e32 v54, 0x4000, v58
v_add_co_u32 v48, vcc_lo, s2, v48
v_ashrrev_i32_e32 v57, 31, v56
v_add_co_ci_u32_e32 v49, vcc_lo, s3, v49, vcc_lo
v_lshlrev_b64 v[50:51], 1, v[50:51]
v_ashrrev_i32_e32 v55, 31, v54
global_store_dword v[52:53], v47, off
global_store_dword v[48:49], v46, off
v_add_nc_u32_e32 v52, 0x4800, v58
v_lshlrev_b64 v[46:47], 1, v[54:55]
v_add_co_u32 v48, vcc_lo, s2, v50
v_add_nc_u32_e32 v54, 0x4802, v58
v_add_co_ci_u32_e32 v49, vcc_lo, s3, v51, vcc_lo
v_lshlrev_b64 v[50:51], 1, v[56:57]
v_ashrrev_i32_e32 v53, 31, v52
v_add_co_u32 v46, vcc_lo, s2, v46
v_ashrrev_i32_e32 v55, 31, v54
v_add_co_ci_u32_e32 v47, vcc_lo, s3, v47, vcc_lo
global_store_dword v[48:49], v45, off
v_add_co_u32 v50, vcc_lo, s2, v50
v_lshlrev_b64 v[48:49], 1, v[52:53]
v_add_co_ci_u32_e32 v51, vcc_lo, s3, v51, vcc_lo
v_add_nc_u32_e32 v45, 0x5000, v58
global_store_dword v[46:47], v43, off
global_store_dword v[50:51], v44, off
v_add_co_u32 v47, vcc_lo, s2, v48
v_lshlrev_b64 v[43:44], 1, v[54:55]
v_add_co_ci_u32_e32 v48, vcc_lo, s3, v49, vcc_lo
v_ashrrev_i32_e32 v46, 31, v45
v_add_nc_u32_e32 v49, 0x5002, v58
v_add_nc_u32_e32 v51, 0x5800, v58
v_add_co_u32 v43, vcc_lo, s2, v43
v_lshlrev_b64 v[45:46], 1, v[45:46]
v_ashrrev_i32_e32 v50, 31, v49
v_add_co_ci_u32_e32 v44, vcc_lo, s3, v44, vcc_lo
v_ashrrev_i32_e32 v52, 31, v51
global_store_dword v[47:48], v41, off
global_store_dword v[43:44], v42, off
v_lshlrev_b64 v[41:42], 1, v[49:50]
v_add_co_u32 v43, vcc_lo, s2, v45
v_add_nc_u32_e32 v47, 0x5802, v58
v_add_co_ci_u32_e32 v44, vcc_lo, s3, v46, vcc_lo
v_lshlrev_b64 v[45:46], 1, v[51:52]
v_add_nc_u32_e32 v49, 0x6000, v58
v_add_co_u32 v41, vcc_lo, s2, v41
v_ashrrev_i32_e32 v48, 31, v47
v_add_co_ci_u32_e32 v42, vcc_lo, s3, v42, vcc_lo
global_store_dword v[43:44], v39, off
v_add_co_u32 v45, vcc_lo, s2, v45
v_ashrrev_i32_e32 v50, 31, v49
v_add_co_ci_u32_e32 v46, vcc_lo, s3, v46, vcc_lo
v_lshlrev_b64 v[43:44], 1, v[47:48]
global_store_dword v[41:42], v40, off
global_store_dword v[45:46], v38, off
v_add_nc_u32_e32 v40, 0x6002, v58
v_lshlrev_b64 v[38:39], 1, v[49:50]
v_add_co_u32 v42, vcc_lo, s2, v43
v_add_nc_u32_e32 v46, 0x6802, v58
v_add_co_ci_u32_e32 v43, vcc_lo, s3, v44, vcc_lo
v_ashrrev_i32_e32 v41, 31, v40
v_add_nc_u32_e32 v44, 0x6800, v58
v_add_co_u32 v38, vcc_lo, s2, v38
v_ashrrev_i32_e32 v47, 31, v46
v_add_co_ci_u32_e32 v39, vcc_lo, s3, v39, vcc_lo
v_lshlrev_b64 v[40:41], 1, v[40:41]
v_ashrrev_i32_e32 v45, 31, v44
global_store_dword v[42:43], v37, off
global_store_dword v[38:39], v36, off
v_add_nc_u32_e32 v42, 0x7000, v58
v_lshlrev_b64 v[36:37], 1, v[44:45]
v_add_co_u32 v38, vcc_lo, s2, v40
v_add_nc_u32_e32 v44, 0x7002, v58
v_add_co_ci_u32_e32 v39, vcc_lo, s3, v41, vcc_lo
v_lshlrev_b64 v[40:41], 1, v[46:47]
v_ashrrev_i32_e32 v43, 31, v42
v_add_co_u32 v36, vcc_lo, s2, v36
v_ashrrev_i32_e32 v45, 31, v44
v_add_co_ci_u32_e32 v37, vcc_lo, s3, v37, vcc_lo
global_store_dword v[38:39], v35, off
v_add_co_u32 v40, vcc_lo, s2, v40
v_lshlrev_b64 v[38:39], 1, v[42:43]
v_add_co_ci_u32_e32 v41, vcc_lo, s3, v41, vcc_lo
v_add_nc_u32_e32 v35, 0x7800, v58
global_store_dword v[36:37], v33, off
global_store_dword v[40:41], v34, off
v_add_co_u32 v37, vcc_lo, s2, v38
v_lshlrev_b64 v[33:34], 1, v[44:45]
v_add_co_ci_u32_e32 v38, vcc_lo, s3, v39, vcc_lo
v_ashrrev_i32_e32 v36, 31, v35
v_add_nc_u32_e32 v39, 0x7802, v58
v_add_nc_u32_e32 v41, 0x8000, v58
v_add_co_u32 v33, vcc_lo, s2, v33
v_lshlrev_b64 v[35:36], 1, v[35:36]
v_ashrrev_i32_e32 v40, 31, v39
v_add_co_ci_u32_e32 v34, vcc_lo, s3, v34, vcc_lo
v_ashrrev_i32_e32 v42, 31, v41
global_store_dword v[37:38], v31, off
global_store_dword v[33:34], v32, off
v_lshlrev_b64 v[31:32], 1, v[39:40]
v_add_co_u32 v33, vcc_lo, s2, v35
v_add_nc_u32_e32 v37, 0x8002, v58
v_add_co_ci_u32_e32 v34, vcc_lo, s3, v36, vcc_lo
v_lshlrev_b64 v[35:36], 1, v[41:42]
v_add_nc_u32_e32 v39, 0x8800, v58
v_add_co_u32 v31, vcc_lo, s2, v31
v_ashrrev_i32_e32 v38, 31, v37
v_add_co_ci_u32_e32 v32, vcc_lo, s3, v32, vcc_lo
global_store_dword v[33:34], v29, off
v_add_co_u32 v35, vcc_lo, s2, v35
v_ashrrev_i32_e32 v40, 31, v39
v_add_co_ci_u32_e32 v36, vcc_lo, s3, v36, vcc_lo
v_lshlrev_b64 v[33:34], 1, v[37:38]
global_store_dword v[31:32], v30, off
global_store_dword v[35:36], v28, off
v_add_nc_u32_e32 v30, 0x8802, v58
v_lshlrev_b64 v[28:29], 1, v[39:40]
v_add_co_u32 v32, vcc_lo, s2, v33
v_add_nc_u32_e32 v36, 0x9002, v58
v_add_co_ci_u32_e32 v33, vcc_lo, s3, v34, vcc_lo
v_ashrrev_i32_e32 v31, 31, v30
v_add_nc_u32_e32 v34, 0x9000, v58
v_add_co_u32 v28, vcc_lo, s2, v28
v_ashrrev_i32_e32 v37, 31, v36
v_add_co_ci_u32_e32 v29, vcc_lo, s3, v29, vcc_lo
v_lshlrev_b64 v[30:31], 1, v[30:31]
v_ashrrev_i32_e32 v35, 31, v34
global_store_dword v[32:33], v27, off
global_store_dword v[28:29], v26, off
v_add_nc_u32_e32 v32, 0x9800, v58
v_lshlrev_b64 v[26:27], 1, v[34:35]
v_add_co_u32 v28, vcc_lo, s2, v30
v_add_nc_u32_e32 v34, 0x9802, v58
v_add_co_ci_u32_e32 v29, vcc_lo, s3, v31, vcc_lo
v_lshlrev_b64 v[30:31], 1, v[36:37]
v_ashrrev_i32_e32 v33, 31, v32
v_add_co_u32 v26, vcc_lo, s2, v26
v_ashrrev_i32_e32 v35, 31, v34
v_add_co_ci_u32_e32 v27, vcc_lo, s3, v27, vcc_lo
global_store_dword v[28:29], v25, off
v_add_co_u32 v30, vcc_lo, s2, v30
v_lshlrev_b64 v[28:29], 1, v[32:33]
v_add_co_ci_u32_e32 v31, vcc_lo, s3, v31, vcc_lo
v_add_nc_u32_e32 v25, 0xa000, v58
global_store_dword v[26:27], v23, off
global_store_dword v[30:31], v24, off
v_add_co_u32 v27, vcc_lo, s2, v28
v_lshlrev_b64 v[23:24], 1, v[34:35]
v_add_co_ci_u32_e32 v28, vcc_lo, s3, v29, vcc_lo
v_ashrrev_i32_e32 v26, 31, v25
v_add_nc_u32_e32 v29, 0xa002, v58
v_add_nc_u32_e32 v31, 0xa800, v58
v_add_co_u32 v23, vcc_lo, s2, v23
v_lshlrev_b64 v[25:26], 1, v[25:26]
v_ashrrev_i32_e32 v30, 31, v29
v_add_co_ci_u32_e32 v24, vcc_lo, s3, v24, vcc_lo
v_ashrrev_i32_e32 v32, 31, v31
global_store_dword v[27:28], v21, off
global_store_dword v[23:24], v22, off
v_lshlrev_b64 v[21:22], 1, v[29:30]
v_add_co_u32 v23, vcc_lo, s2, v25
v_add_nc_u32_e32 v27, 0xa802, v58
v_add_co_ci_u32_e32 v24, vcc_lo, s3, v26, vcc_lo
v_lshlrev_b64 v[25:26], 1, v[31:32]
v_add_nc_u32_e32 v29, 0xb000, v58
v_add_co_u32 v21, vcc_lo, s2, v21
v_ashrrev_i32_e32 v28, 31, v27
v_add_co_ci_u32_e32 v22, vcc_lo, s3, v22, vcc_lo
global_store_dword v[23:24], v19, off
v_add_co_u32 v25, vcc_lo, s2, v25
v_ashrrev_i32_e32 v30, 31, v29
v_add_co_ci_u32_e32 v26, vcc_lo, s3, v26, vcc_lo
v_lshlrev_b64 v[23:24], 1, v[27:28]
global_store_dword v[21:22], v20, off
global_store_dword v[25:26], v18, off
v_add_nc_u32_e32 v20, 0xb002, v58
v_lshlrev_b64 v[18:19], 1, v[29:30]
v_add_co_u32 v22, vcc_lo, s2, v23
v_add_nc_u32_e32 v26, 0xb802, v58
v_add_co_ci_u32_e32 v23, vcc_lo, s3, v24, vcc_lo
v_ashrrev_i32_e32 v21, 31, v20
v_add_nc_u32_e32 v24, 0xb800, v58
v_add_co_u32 v18, vcc_lo, s2, v18
v_ashrrev_i32_e32 v27, 31, v26
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
v_lshlrev_b64 v[20:21], 1, v[20:21]
v_ashrrev_i32_e32 v25, 31, v24
global_store_dword v[22:23], v17, off
global_store_dword v[18:19], v16, off
v_add_nc_u32_e32 v22, 0xc000, v58
v_lshlrev_b64 v[16:17], 1, v[24:25]
v_add_co_u32 v18, vcc_lo, s2, v20
v_add_nc_u32_e32 v24, 0xc002, v58
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v21, vcc_lo
v_lshlrev_b64 v[20:21], 1, v[26:27]
v_ashrrev_i32_e32 v23, 31, v22
v_add_co_u32 v16, vcc_lo, s2, v16
v_ashrrev_i32_e32 v25, 31, v24
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
global_store_dword v[18:19], v15, off
v_add_co_u32 v20, vcc_lo, s2, v20
v_lshlrev_b64 v[18:19], 1, v[22:23]
v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo
v_add_nc_u32_e32 v15, 0xc800, v58
global_store_dword v[16:17], v13, off
global_store_dword v[20:21], v14, off
v_add_co_u32 v17, vcc_lo, s2, v18
v_lshlrev_b64 v[13:14], 1, v[24:25]
v_add_co_ci_u32_e32 v18, vcc_lo, s3, v19, vcc_lo
v_ashrrev_i32_e32 v16, 31, v15
v_add_nc_u32_e32 v19, 0xc802, v58
v_add_nc_u32_e32 v21, 0xd000, v58
v_add_co_u32 v13, vcc_lo, s2, v13
v_lshlrev_b64 v[15:16], 1, v[15:16]
v_ashrrev_i32_e32 v20, 31, v19
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
v_ashrrev_i32_e32 v22, 31, v21
global_store_dword v[17:18], v10, off
global_store_dword v[13:14], v12, off
v_lshlrev_b64 v[12:13], 1, v[19:20]
v_add_co_u32 v14, vcc_lo, s2, v15
v_add_nc_u32_e32 v18, 0xd002, v58
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v16, vcc_lo
v_lshlrev_b64 v[16:17], 1, v[21:22]
v_add_nc_u32_e32 v20, 0xd800, v58
v_add_co_u32 v12, vcc_lo, s2, v12
v_ashrrev_i32_e32 v19, 31, v18
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
global_store_dword v[14:15], v7, off
v_add_co_u32 v16, vcc_lo, s2, v16
v_ashrrev_i32_e32 v21, 31, v20
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
v_lshlrev_b64 v[14:15], 1, v[18:19]
v_add_nc_u32_e32 v18, 0xe002, v58
global_store_dword v[12:13], v8, off
global_store_dword v[16:17], v6, off
v_lshlrev_b64 v[6:7], 1, v[20:21]
v_add_nc_u32_e32 v12, 0xd802, v58
v_add_co_u32 v14, vcc_lo, s2, v14
v_add_nc_u32_e32 v16, 0xe000, v58
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
v_ashrrev_i32_e32 v19, 31, v18
v_add_co_u32 v6, vcc_lo, s2, v6
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_ashrrev_i32_e32 v17, 31, v16
global_store_dword v[14:15], v5, off
v_lshlrev_b64 v[14:15], 1, v[18:19]
v_lshlrev_b64 v[12:13], 1, v[12:13]
global_store_dword v[6:7], v4, off
v_add_nc_u32_e32 v6, 0xe800, v58
v_lshlrev_b64 v[4:5], 1, v[16:17]
v_add_nc_u32_e32 v16, 0xe802, v58
v_add_co_u32 v12, vcc_lo, s2, v12
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
v_ashrrev_i32_e32 v17, 31, v16
v_add_co_u32 v4, vcc_lo, s2, v4
v_lshlrev_b64 v[6:7], 1, v[6:7]
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v14, vcc_lo, s2, v14
v_lshlrev_b64 v[16:17], 1, v[16:17]
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v16, vcc_lo, s2, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
global_store_dword v[12:13], v3, off
global_store_dword v[4:5], v1, off
global_store_dword v[14:15], v2, off
global_store_dword v[6:7], v11, off
global_store_dword v[16:17], v9, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_dense_1_kernel0
.amdhsa_group_segment_fixed_size 34688
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 122
.amdhsa_next_free_sgpr 13
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end65:
.size tvmgen_default_fused_nn_dense_1_kernel0, .Lfunc_end65-tvmgen_default_fused_nn_dense_1_kernel0
.globl tvmgen_default_fused_nn_dense_2_kernel0
.p2align 8
.type tvmgen_default_fused_nn_dense_2_kernel0,@function
tvmgen_default_fused_nn_dense_2_kernel0:
s_load_dwordx2 s[8:9], s[4:5], 0x8
v_lshrrev_b32_e32 v3, 3, v0
s_mov_b32 s7, 0x14000
s_ashr_i32 s1, s6, 3
v_lshlrev_b32_e32 v5, 12, v0
s_mul_i32 s2, s1, s7
s_lshl_b32 s10, s6, 16
v_lshl_add_u32 v2, v3, 11, s2
s_clause 0x1
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[4:5], s[4:5], 0x0
s_and_b32 s10, s10, 0x70000
v_and_b32_e32 v1, 7, v0
v_add_lshl_u32 v8, s10, v5, 1
s_movk_i32 s0, 0x400
v_cmp_gt_i32_e32 vcc_lo, 16, v0
v_lshl_add_u32 v4, v0, 2, s0
v_lshl_add_u32 v6, v3, 8, s0
v_lshl_or_b32 v2, v1, 1, v2
v_lshlrev_b32_e32 v5, 6, v0
v_lshlrev_b32_e32 v7, 5, v1
v_mov_b32_e32 v10, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, s0, s8, v8
v_mov_b32_e32 v12, 0
v_add_co_ci_u32_e64 v9, s0, s9, 0, s0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v24, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v19, 0
s_mov_b64 s[8:9], 0
s_movk_i32 s10, 0x1000
s_branch BB66_2
BB66_1:
s_or_b32 exec_lo, exec_lo, s11
s_waitcnt lgkmcnt(0)
s_barrier
ds_read_b128 v[26:29], v7 offset:256
ds_read_b128 v[30:33], v7
ds_read_b128 v[34:37], v7 offset:512
ds_read_b128 v[38:41], v7 offset:16
ds_read_b128 v[42:45], v7 offset:768
v_mov_b32_e32 v3, 0xffff
ds_read_b128 v[46:49], v7 offset:272
ds_read_b128 v[50:53], v7 offset:528
ds_read_b128 v[54:57], v6 offset:224
ds_read_b128 v[70:73], v6 offset:96
v_add_nc_u32_e32 v2, 16, v2
s_add_u32 s8, s8, 32
s_addc_u32 s9, s9, 0
s_cmp_eq_u32 s8, s10
s_waitcnt lgkmcnt(8)
v_lshrrev_b32_e32 v58, 16, v26
s_waitcnt lgkmcnt(7)
v_and_b32_e32 v59, v3, v30
s_waitcnt lgkmcnt(6)
v_and_b32_e32 v60, v3, v34
v_and_b32_e32 v65, v3, v35
v_and_b32_sdwa v30, v3, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v61, v3, v31
v_and_b32_e32 v68, v3, v36
s_waitcnt lgkmcnt(4)
v_lshl_or_b32 v82, v42, 16, v60
v_lshl_or_b32 v83, v43, 16, v65
v_lshl_or_b32 v87, v58, 16, v30
v_and_b32_sdwa v30, v3, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v65, 16, v43
v_lshrrev_b32_e32 v62, 16, v27
v_and_b32_sdwa v31, v3, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v42, 16, v42
v_and_b32_sdwa v34, v3, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v66, v3, v32
v_and_b32_e32 v67, v3, v33
v_lshl_or_b32 v84, v44, 16, v68
v_and_b32_sdwa v68, v3, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v86, v42, 16, v34
v_and_b32_sdwa v34, v3, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v88, v65, 16, v30
v_lshl_or_b32 v89, v62, 16, v31
ds_read_b128 v[30:33], v6 offset:160
v_lshl_or_b32 v78, v26, 16, v59
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v19, v54, v82, v19 op_sel_hi:[0,1,1]
v_lshl_or_b32 v79, v27, 16, v61
ds_read_b128 v[58:61], v6 offset:192
v_lshrrev_b32_e32 v64, 16, v29
v_pk_fma_f16 v18, v54, v78, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v54, v86, v19 op_sel:[1,0,0]
v_and_b32_e32 v69, v3, v37
v_lshl_or_b32 v80, v28, 16, v66
v_lshl_or_b32 v81, v29, 16, v67
v_pk_fma_f16 v18, v54, v87, v18 op_sel:[1,0,0]
v_pk_fma_f16 v19, v55, v83, v19 op_sel_hi:[0,1,1]
v_lshrrev_b32_e32 v66, 16, v44
v_and_b32_sdwa v35, v3, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v67, 16, v45
v_and_b32_sdwa v54, v3, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_fma_f16 v18, v55, v79, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v55, v88, v19 op_sel:[1,0,0]
v_lshl_or_b32 v85, v45, 16, v69
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v22, v30, v82, v22 op_sel_hi:[0,1,1]
v_lshl_or_b32 v91, v66, 16, v35
v_lshl_or_b32 v92, v64, 16, v68
v_lshl_or_b32 v93, v67, 16, v54
ds_read_b128 v[66:69], v6 offset:128
v_lshrrev_b32_e32 v63, 16, v28
v_pk_fma_f16 v18, v55, v89, v18 op_sel:[1,0,0]
v_pk_fma_f16 v19, v56, v84, v19 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v14, v58, v82, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v58, v78, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v30, v78, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v30, v86, v22 op_sel:[1,0,0]
v_lshl_or_b32 v90, v63, 16, v34
v_pk_fma_f16 v18, v56, v80, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v56, v91, v19 op_sel:[1,0,0]
v_pk_fma_f16 v14, v58, v86, v14 op_sel:[1,0,0]
v_pk_fma_f16 v17, v58, v87, v17 op_sel:[1,0,0]
v_pk_fma_f16 v25, v30, v87, v25 op_sel:[1,0,0]
v_pk_fma_f16 v22, v31, v83, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v56, v90, v18 op_sel:[1,0,0]
v_pk_fma_f16 v14, v59, v83, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v59, v79, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v31, v79, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v57, v85, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v31, v88, v22 op_sel:[1,0,0]
v_pk_fma_f16 v14, v59, v88, v14 op_sel:[1,0,0]
v_pk_fma_f16 v17, v59, v89, v17 op_sel:[1,0,0]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v21, v66, v82, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v70, v82, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v70, v78, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v31, v89, v25 op_sel:[1,0,0]
v_pk_fma_f16 v31, v66, v78, v20 op_sel_hi:[0,1,1]
v_pk_fma_f16 v94, v57, v93, v19 op_sel:[1,0,0]
v_pk_fma_f16 v19, v32, v84, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v57, v81, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v32, v80, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v60, v84, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v60, v80, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v66, v86, v21 op_sel:[1,0,0]
v_pk_fma_f16 v25, v57, v92, v18 op_sel:[1,0,0]
v_pk_fma_f16 v31, v66, v87, v31 op_sel:[1,0,0]
v_pk_fma_f16 v24, v70, v86, v24 op_sel:[1,0,0]
v_pk_fma_f16 v23, v70, v87, v23 op_sel:[1,0,0]
v_pk_fma_f16 v18, v32, v91, v19 op_sel:[1,0,0]
v_pk_fma_f16 v14, v60, v91, v14 op_sel:[1,0,0]
v_pk_fma_f16 v17, v60, v90, v17 op_sel:[1,0,0]
v_pk_fma_f16 v21, v67, v83, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v71, v79, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v33, v85, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v67, v79, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v71, v83, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v61, v85, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v59, v71, v89, v23 op_sel:[1,0,0]
v_pk_fma_f16 v17, v61, v81, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v96, v33, v93, v30 op_sel:[1,0,0]
v_pk_fma_f16 v30, v67, v89, v31 op_sel:[1,0,0]
v_pk_fma_f16 v21, v67, v88, v21 op_sel:[1,0,0]
v_pk_fma_f16 v31, v71, v88, v24 op_sel:[1,0,0]
v_pk_fma_f16 v59, v72, v80, v59 op_sel_hi:[0,1,1]
v_pk_fma_f16 v95, v61, v92, v17 op_sel:[1,0,0]
v_pk_fma_f16 v60, v68, v80, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v58, v68, v84, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v61, v93, v14 op_sel:[1,0,0]
v_pk_fma_f16 v61, v72, v84, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v32, v90, v22 op_sel:[1,0,0]
v_pk_fma_f16 v60, v68, v90, v60 op_sel:[1,0,0]
v_pk_fma_f16 v58, v68, v91, v58 op_sel:[1,0,0]
v_pk_fma_f16 v59, v72, v90, v59 op_sel:[1,0,0]
v_pk_fma_f16 v61, v72, v91, v61 op_sel:[1,0,0]
v_pk_fma_f16 v22, v33, v81, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v60, v69, v81, v60 op_sel_hi:[0,1,1]
v_pk_fma_f16 v58, v69, v85, v58 op_sel_hi:[0,1,1]
v_pk_fma_f16 v59, v73, v81, v59 op_sel_hi:[0,1,1]
v_pk_fma_f16 v61, v73, v85, v61 op_sel_hi:[0,1,1]
v_pk_fma_f16 v97, v33, v92, v22 op_sel:[1,0,0]
ds_read_b128 v[21:24], v6 offset:64
ds_read_b128 v[30:33], v6 offset:32
ds_read_b128 v[26:29], v7 offset:784
ds_read_b128 v[42:45], v6 offset:240
ds_read_b128 v[34:37], v6 offset:208
ds_read_b128 v[62:65], v6 offset:176
ds_read_b128 v[54:57], v6 offset:144
ds_read_b128 v[17:20], v6 offset:112
v_pk_fma_f16 v98, v69, v93, v58 op_sel:[1,0,0]
v_pk_fma_f16 v99, v69, v92, v60 op_sel:[1,0,0]
v_pk_fma_f16 v100, v73, v93, v61 op_sel:[1,0,0]
v_pk_fma_f16 v101, v73, v92, v59 op_sel:[1,0,0]
ds_read_b128 v[58:61], v6 offset:80
ds_read_b128 v[66:69], v6 offset:48
ds_read_b128 v[70:73], v6
ds_read_b128 v[74:77], v6 offset:16
s_waitcnt lgkmcnt(11)
v_pk_fma_f16 v16, v21, v82, v16 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(10)
v_pk_fma_f16 v15, v30, v82, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v21, v78, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v30, v78, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v21, v86, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v30, v86, v15 op_sel:[1,0,0]
v_pk_fma_f16 v13, v21, v87, v13 op_sel:[1,0,0]
v_pk_fma_f16 v11, v30, v87, v11 op_sel:[1,0,0]
v_and_b32_e32 v21, v3, v38
v_pk_fma_f16 v16, v22, v83, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v31, v83, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v22, v79, v13 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v12, v70, v82, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v70, v78, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v31, v79, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v22, v88, v16 op_sel:[1,0,0]
v_pk_fma_f16 v13, v22, v89, v13 op_sel:[1,0,0]
v_pk_fma_f16 v12, v70, v86, v12 op_sel:[1,0,0]
v_pk_fma_f16 v10, v70, v87, v10 op_sel:[1,0,0]
v_pk_fma_f16 v15, v31, v88, v15 op_sel:[1,0,0]
v_pk_fma_f16 v11, v31, v89, v11 op_sel:[1,0,0]
v_pk_fma_f16 v16, v23, v84, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v71, v83, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v23, v80, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v71, v79, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v32, v84, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v32, v80, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v71, v88, v12 op_sel:[1,0,0]
v_pk_fma_f16 v16, v23, v91, v16 op_sel:[1,0,0]
v_pk_fma_f16 v13, v23, v90, v13 op_sel:[1,0,0]
v_pk_fma_f16 v10, v71, v89, v10 op_sel:[1,0,0]
v_pk_fma_f16 v15, v32, v91, v15 op_sel:[1,0,0]
v_pk_fma_f16 v12, v72, v84, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v32, v90, v11 op_sel:[1,0,0]
v_pk_fma_f16 v16, v24, v85, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v72, v80, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v24, v81, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v72, v91, v12 op_sel:[1,0,0]
v_pk_fma_f16 v15, v33, v85, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v33, v81, v11 op_sel_hi:[0,1,1]
v_and_b32_e32 v23, v3, v39
v_and_b32_e32 v30, v3, v40
v_pk_fma_f16 v12, v73, v85, v12 op_sel_hi:[0,1,1]
v_and_b32_sdwa v22, v3, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v38, v3, v50
v_and_b32_sdwa v31, v3, v40 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v40, v3, v51
v_pk_fma_f16 v10, v72, v90, v10 op_sel:[1,0,0]
v_and_b32_e32 v32, v3, v41
v_lshl_or_b32 v21, v46, 16, v21
v_pk_fma_f16 v13, v24, v92, v13 op_sel:[1,0,0]
v_pk_fma_f16 v11, v33, v92, v11 op_sel:[1,0,0]
v_lshl_or_b32 v38, v26, 16, v38
v_pk_fma_f16 v16, v24, v93, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v33, v93, v15 op_sel:[1,0,0]
v_pk_fma_f16 v12, v73, v93, v12 op_sel:[1,0,0]
v_and_b32_sdwa v24, v3, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v33, v3, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v39, v3, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v26, 16, v26
v_and_b32_sdwa v41, v3, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v23, v47, 16, v23
v_lshrrev_b32_e32 v46, 16, v46
v_lshrrev_b32_e32 v47, 16, v47
v_lshl_or_b32 v40, v27, 16, v40
v_lshrrev_b32_e32 v27, 16, v27
v_pk_fma_f16 v10, v73, v81, v10 op_sel_hi:[0,1,1]
v_lshl_or_b32 v22, v46, 16, v22
v_lshl_or_b32 v26, v26, 16, v39
v_pk_fma_f16 v14, v34, v38, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v58, v38, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v66, v38, v15 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v12, v74, v38, v12 op_sel_hi:[0,1,1]
v_lshl_or_b32 v24, v47, 16, v24
v_lshl_or_b32 v27, v27, 16, v41
v_pk_fma_f16 v39, v42, v38, v94 op_sel_hi:[0,1,1]
v_pk_fma_f16 v41, v62, v38, v96 op_sel_hi:[0,1,1]
v_pk_fma_f16 v46, v54, v38, v98 op_sel_hi:[0,1,1]
v_pk_fma_f16 v47, v17, v38, v100 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v73, v92, v10 op_sel:[1,0,0]
v_pk_fma_f16 v14, v34, v26, v14 op_sel:[1,0,0]
v_pk_fma_f16 v16, v58, v26, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v66, v26, v15 op_sel:[1,0,0]
v_pk_fma_f16 v12, v74, v26, v12 op_sel:[1,0,0]
v_pk_fma_f16 v38, v42, v26, v39 op_sel:[1,0,0]
v_pk_fma_f16 v39, v62, v26, v41 op_sel:[1,0,0]
v_pk_fma_f16 v41, v54, v26, v46 op_sel:[1,0,0]
v_pk_fma_f16 v46, v17, v26, v47 op_sel:[1,0,0]
v_and_b32_e32 v50, v3, v52
v_pk_fma_f16 v14, v35, v40, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v59, v40, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v67, v40, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v75, v40, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v58, v21, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v66, v21, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v74, v21, v10 op_sel_hi:[0,1,1]
v_and_b32_sdwa v51, v3, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v52, v3, v53
v_and_b32_sdwa v3, v3, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_fma_f16 v53, v17, v21, v101 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v43, v40, v38 op_sel_hi:[0,1,1]
v_pk_fma_f16 v38, v63, v40, v39 op_sel_hi:[0,1,1]
v_pk_fma_f16 v39, v55, v40, v41 op_sel_hi:[0,1,1]
v_pk_fma_f16 v41, v18, v40, v46 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v42, v21, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v40, v34, v21, v95 op_sel_hi:[0,1,1]
v_pk_fma_f16 v46, v62, v21, v97 op_sel_hi:[0,1,1]
v_pk_fma_f16 v47, v54, v21, v99 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v17, v22, v53 op_sel:[1,0,0]
v_pk_fma_f16 v21, v42, v22, v25 op_sel:[1,0,0]
v_pk_fma_f16 v25, v34, v22, v40 op_sel:[1,0,0]
v_pk_fma_f16 v13, v58, v22, v13 op_sel:[1,0,0]
v_pk_fma_f16 v11, v66, v22, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v74, v22, v10 op_sel:[1,0,0]
v_pk_fma_f16 v34, v62, v22, v46 op_sel:[1,0,0]
v_pk_fma_f16 v40, v54, v22, v47 op_sel:[1,0,0]
v_pk_fma_f16 v22, v35, v23, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v43, v23, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v18, v23, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v59, v23, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v67, v23, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v75, v23, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v63, v23, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v55, v23, v40 op_sel_hi:[0,1,1]
v_lshl_or_b32 v30, v48, 16, v30
v_pk_fma_f16 v17, v18, v24, v17 op_sel:[1,0,0]
v_pk_fma_f16 v21, v43, v24, v21 op_sel:[1,0,0]
v_pk_fma_f16 v23, v63, v24, v25 op_sel:[1,0,0]
v_pk_fma_f16 v25, v55, v24, v34 op_sel:[1,0,0]
v_pk_fma_f16 v22, v35, v24, v22 op_sel:[1,0,0]
v_pk_fma_f16 v13, v59, v24, v13 op_sel:[1,0,0]
v_pk_fma_f16 v11, v67, v24, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v75, v24, v10 op_sel:[1,0,0]
v_lshl_or_b32 v50, v28, 16, v50
v_pk_fma_f16 v24, v43, v27, v26 op_sel:[1,0,0]
v_lshrrev_b32_e32 v28, 16, v28
v_pk_fma_f16 v14, v35, v27, v14 op_sel:[1,0,0]
v_pk_fma_f16 v26, v63, v27, v38 op_sel:[1,0,0]
v_pk_fma_f16 v18, v18, v27, v41 op_sel:[1,0,0]
v_pk_fma_f16 v16, v59, v27, v16 op_sel:[1,0,0]
v_pk_fma_f16 v15, v67, v27, v15 op_sel:[1,0,0]
v_pk_fma_f16 v12, v75, v27, v12 op_sel:[1,0,0]
v_lshrrev_b32_e32 v48, 16, v48
v_pk_fma_f16 v34, v55, v27, v39 op_sel:[1,0,0]
v_pk_fma_f16 v10, v76, v30, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v68, v30, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v60, v30, v13 op_sel_hi:[0,1,1]
v_lshl_or_b32 v27, v48, 16, v31
v_pk_fma_f16 v17, v19, v30, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v64, v30, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v36, v30, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v44, v30, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v56, v30, v25 op_sel_hi:[0,1,1]
v_lshl_or_b32 v28, v28, 16, v51
v_pk_fma_f16 v12, v76, v50, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v68, v50, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v60, v50, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v19, v50, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v64, v50, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v36, v50, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v44, v50, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v56, v50, v34 op_sel_hi:[0,1,1]
v_lshl_or_b32 v32, v49, 16, v32
v_pk_fma_f16 v10, v76, v27, v10 op_sel:[1,0,0]
v_pk_fma_f16 v11, v68, v27, v11 op_sel:[1,0,0]
v_pk_fma_f16 v13, v60, v27, v13 op_sel:[1,0,0]
v_pk_fma_f16 v17, v19, v27, v17 op_sel:[1,0,0]
v_lshl_or_b32 v52, v29, 16, v52
v_pk_fma_f16 v18, v19, v28, v18 op_sel:[1,0,0]
v_pk_fma_f16 v19, v56, v27, v25 op_sel:[1,0,0]
v_pk_fma_f16 v12, v76, v28, v12 op_sel:[1,0,0]
v_pk_fma_f16 v15, v68, v28, v15 op_sel:[1,0,0]
v_pk_fma_f16 v16, v60, v28, v16 op_sel:[1,0,0]
v_pk_fma_f16 v25, v56, v28, v30 op_sel:[1,0,0]
v_pk_fma_f16 v26, v64, v28, v26 op_sel:[1,0,0]
v_pk_fma_f16 v14, v36, v28, v14 op_sel:[1,0,0]
v_lshrrev_b32_e32 v49, 16, v49
v_lshrrev_b32_e32 v29, 16, v29
v_pk_fma_f16 v24, v44, v28, v24 op_sel:[1,0,0]
v_pk_fma_f16 v22, v36, v27, v22 op_sel:[1,0,0]
v_pk_fma_f16 v23, v64, v27, v23 op_sel:[1,0,0]
v_pk_fma_f16 v21, v44, v27, v21 op_sel:[1,0,0]
v_lshl_or_b32 v3, v29, 16, v3
v_pk_fma_f16 v12, v77, v52, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v69, v52, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v61, v52, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v37, v52, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v77, v32, v10 op_sel_hi:[0,1,1]
v_lshl_or_b32 v30, v49, 16, v33
v_pk_fma_f16 v11, v69, v32, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v61, v32, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v17, v20, v32, v17 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v65, v32, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v18, v20, v52, v18 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v45, v52, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v19, v57, v32, v19 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v57, v52, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v45, v32, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v65, v52, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v37, v32, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v20, v30, v17 op_sel:[1,0,0]
v_pk_fma_f16 v24, v20, v3, v18 op_sel:[1,0,0]
v_pk_fma_f16 v20, v57, v30, v19 op_sel:[1,0,0]
v_pk_fma_f16 v21, v57, v3, v25 op_sel:[1,0,0]
v_pk_fma_f16 v10, v77, v30, v10 op_sel:[1,0,0]
v_pk_fma_f16 v12, v77, v3, v12 op_sel:[1,0,0]
v_pk_fma_f16 v11, v69, v30, v11 op_sel:[1,0,0]
v_pk_fma_f16 v15, v69, v3, v15 op_sel:[1,0,0]
v_pk_fma_f16 v13, v61, v30, v13 op_sel:[1,0,0]
v_pk_fma_f16 v16, v61, v3, v16 op_sel:[1,0,0]
v_pk_fma_f16 v25, v65, v30, v27 op_sel:[1,0,0]
v_pk_fma_f16 v22, v65, v3, v26 op_sel:[1,0,0]
v_pk_fma_f16 v17, v37, v30, v28 op_sel:[1,0,0]
v_pk_fma_f16 v14, v37, v3, v14 op_sel:[1,0,0]
v_pk_fma_f16 v18, v45, v30, v29 op_sel:[1,0,0]
v_pk_fma_f16 v19, v45, v3, v31 op_sel:[1,0,0]
s_cbranch_scc1 BB66_4
BB66_2:
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[26:27], 1, v[2:3]
v_add_co_u32 v26, s0, s4, v26
v_add_co_ci_u32_e64 v27, s0, s5, v27, s0
v_add_co_u32 v28, s0, 0x5000, v26
v_add_co_ci_u32_e64 v29, s0, 0, v27, s0
v_add_co_u32 v30, s0, 0xa000, v26
v_add_co_ci_u32_e64 v31, s0, 0, v27, s0
v_add_co_u32 v32, s0, 0xf000, v26
v_add_co_ci_u32_e64 v33, s0, 0, v27, s0
v_add_co_u32 v34, s0, s7, v26
v_add_co_ci_u32_e64 v35, s0, 0, v27, s0
v_add_co_u32 v36, s0, 0x19000, v26
v_add_co_ci_u32_e64 v37, s0, 0, v27, s0
v_add_co_u32 v38, s0, 0x1e000, v26
v_add_co_ci_u32_e64 v39, s0, 0, v27, s0
v_add_co_u32 v40, s0, 0x23000, v26
v_add_co_ci_u32_e64 v41, s0, 0, v27, s0
s_clause 0x7
global_load_dword v3, v[26:27], off
global_load_dword v26, v[28:29], off
global_load_dword v27, v[30:31], off
global_load_dword v28, v[32:33], off
global_load_dword v29, v[34:35], off
global_load_dword v30, v[36:37], off
global_load_dword v31, v[38:39], off
global_load_dword v32, v[40:41], off
v_add_nc_u32_e32 v33, 0x200, v4
s_waitcnt vmcnt(0)
s_barrier
ds_write2_b32 v4, v3, v26 offset1:40
ds_write2_b32 v4, v27, v28 offset0:80 offset1:120
ds_write2_b32 v4, v29, v30 offset0:160 offset1:200
ds_write2_b32 v33, v31, v32 offset0:112 offset1:152
s_and_saveexec_b32 s11, vcc_lo
s_cbranch_execz BB66_1
v_add_co_u32 v33, s0, v8, s8
v_add_co_ci_u32_e64 v34, s0, s9, v9, s0
v_add_co_u32 v41, s0, s10, v33
v_add_co_ci_u32_e64 v42, s0, 0, v34, s0
s_clause 0xf
global_load_dword v26, v[33:34], off
global_load_dword v27, v[33:34], off offset:4
global_load_dword v28, v[33:34], off offset:8
global_load_dword v29, v[33:34], off offset:12
global_load_dword v30, v[33:34], off offset:16
global_load_dword v31, v[33:34], off offset:20
global_load_dword v32, v[33:34], off offset:24
global_load_dword v33, v[33:34], off offset:28
global_load_dword v34, v[41:42], off
global_load_dword v35, v[41:42], off offset:4
global_load_dword v36, v[41:42], off offset:8
global_load_dword v37, v[41:42], off offset:12
global_load_dword v38, v[41:42], off offset:16
global_load_dword v39, v[41:42], off offset:20
global_load_dword v40, v[41:42], off offset:24
global_load_dword v41, v[41:42], off offset:28
s_waitcnt vmcnt(12)
ds_write_b128 v5, v[26:29]
s_waitcnt vmcnt(8)
ds_write_b128 v5, v[30:33] offset:16
s_waitcnt vmcnt(4)
ds_write_b128 v5, v[34:37] offset:32
s_waitcnt vmcnt(0)
ds_write_b128 v5, v[38:41] offset:48
s_branch BB66_1
BB66_4:
v_lshlrev_b32_e32 v0, 8, v0
s_mulk_i32 s1, 0x2800
s_lshl_b32 s0, s6, 5
v_and_or_b32 v0, 0x3f800, v0, v1
v_add_nc_u32_e32 v0, s1, v0
v_and_or_b32 v0, 0xe0, s0, v0
v_or_b32_e32 v2, 0x400, v0
v_ashrrev_i32_e32 v1, 31, v0
v_or_b32_e32 v4, 0x408, v0
v_or_b32_e32 v8, 0x410, v0
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[6:7], 1, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
v_or_b32_e32 v1, 0x418, v0
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[2:3], 1, v[2:3]
v_add_co_u32 v6, vcc_lo, s2, v6
v_lshlrev_b64 v[4:5], 1, v[4:5]
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_short v[6:7], v10, off
global_store_short_d16_hi v[6:7], v10, off offset:16
global_store_short v[6:7], v12, off offset:32
global_store_short_d16_hi v[6:7], v12, off offset:48
global_store_short v[6:7], v11, off offset:512
global_store_short_d16_hi v[6:7], v11, off offset:528
global_store_short v[6:7], v15, off offset:544
global_store_short_d16_hi v[6:7], v15, off offset:560
global_store_short v[6:7], v13, off offset:1024
global_store_short_d16_hi v[6:7], v13, off offset:1040
global_store_short v[6:7], v16, off offset:1056
global_store_short_d16_hi v[6:7], v16, off offset:1072
global_store_short v[6:7], v23, off offset:1536
global_store_short_d16_hi v[6:7], v23, off offset:1552
global_store_short v[6:7], v24, off offset:1568
global_store_short_d16_hi v[6:7], v24, off offset:1584
global_store_short v[2:3], v20, off
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v3, vcc_lo, s2, v4
v_lshlrev_b64 v[6:7], 1, v[8:9]
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v5, vcc_lo
v_or_b32_e32 v5, 0x500, v0
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_or_b32_e32 v10, 0x508, v0
v_add_co_u32 v8, vcc_lo, s2, v6
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v1, vcc_lo, s2, v1
v_ashrrev_i32_e32 v11, 31, v10
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_short_d16_hi v[3:4], v20, off
v_lshlrev_b64 v[3:4], 1, v[5:6]
v_or_b32_e32 v5, 0x510, v0
global_store_short v[8:9], v21, off
global_store_short_d16_hi v[1:2], v21, off
v_lshlrev_b64 v[1:2], 1, v[10:11]
v_or_b32_e32 v7, 0x518, v0
v_or_b32_e32 v9, 0x600, v0
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s2, v1
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[5:6], 1, v[5:6]
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
v_ashrrev_i32_e32 v10, 31, v9
global_store_short v[3:4], v25, off
global_store_short_d16_hi v[1:2], v25, off
v_lshlrev_b64 v[1:2], 1, v[7:8]
v_add_co_u32 v3, vcc_lo, s2, v5
v_or_b32_e32 v7, 0x608, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v6, vcc_lo
v_lshlrev_b64 v[5:6], 1, v[9:10]
v_or_b32_e32 v9, 0x610, v0
v_add_co_u32 v1, vcc_lo, s2, v1
v_ashrrev_i32_e32 v8, 31, v7
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_short v[3:4], v22, off
v_add_co_u32 v5, vcc_lo, s2, v5
v_ashrrev_i32_e32 v10, 31, v9
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_lshlrev_b64 v[3:4], 1, v[7:8]
v_or_b32_e32 v7, 0x700, v0
global_store_short_d16_hi v[1:2], v22, off
global_store_short v[5:6], v17, off
v_lshlrev_b64 v[1:2], 1, v[9:10]
v_or_b32_e32 v5, 0x618, v0
v_add_co_u32 v3, vcc_lo, s2, v3
v_or_b32_e32 v9, 0x708, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v1, vcc_lo, s2, v1
v_ashrrev_i32_e32 v10, 31, v9
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_short_d16_hi v[3:4], v17, off
v_lshlrev_b64 v[3:4], 1, v[5:6]
v_or_b32_e32 v5, 0x710, v0
v_or_b32_e32 v0, 0x718, v0
global_store_short v[1:2], v14, off
v_lshlrev_b64 v[1:2], 1, v[7:8]
v_lshlrev_b64 v[7:8], 1, v[9:10]
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v9, vcc_lo, s2, v1
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[5:6], 1, v[5:6]
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v7
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_short_d16_hi v[3:4], v14, off
global_store_short v[9:10], v18, off
global_store_short_d16_hi v[7:8], v18, off
global_store_short v[5:6], v19, off
global_store_short_d16_hi v[0:1], v19, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_dense_2_kernel0
.amdhsa_group_segment_fixed_size 2304
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 102
.amdhsa_next_free_sgpr 12
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end66:
.size tvmgen_default_fused_nn_dense_2_kernel0, .Lfunc_end66-tvmgen_default_fused_nn_dense_2_kernel0
.globl tvmgen_default_fused_nn_dense_3_kernel0
.p2align 8
.type tvmgen_default_fused_nn_dense_3_kernel0,@function
tvmgen_default_fused_nn_dense_3_kernel0:
v_lshlrev_b32_e32 v1, 7, v0
s_clause 0x2
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_lshl_b32 s4, s6, 12
v_lshlrev_b32_e32 v3, 2, v0
s_and_b32 s4, s4, 0xf000
v_and_b32_e32 v1, 0x1ff00, v1
v_and_b32_e32 v7, 0x3f0, v0
v_and_b32_e32 v5, 7, v0
v_lshlrev_b32_e32 v6, 1, v0
v_lshlrev_b32_e32 v8, 4, v0
v_add_nc_u32_e32 v4, s4, v1
v_lshlrev_b32_e32 v1, 5, v0
s_movk_i32 s0, 0x100
s_lshl_b32 s1, s6, 6
v_mov_b32_e32 v11, 0
v_and_or_b32 v4, v3, 4, v4
v_and_or_b32 v9, 0x7f00, v1, v5
v_add_nc_u32_e32 v3, s0, v6
v_or_b32_e32 v6, 30, v6
v_and_b32_e32 v5, 0xf0, v8
v_lshlrev_b32_e32 v10, 1, v4
v_lshl_add_u32 v4, v7, 1, s0
s_and_b32 s1, s1, 0xfffffc00
v_lshlrev_b32_e32 v2, 3, v0
v_add_nc_u32_e32 v6, s0, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, s4, v10, s10
v_add_nc_u32_e32 v9, s1, v9
v_add_co_ci_u32_e64 v8, s4, 0, s11, s4
v_mov_b32_e32 v10, 0xffff
s_mov_b32 s4, 0
v_add_co_u32 v7, vcc_lo, v7, 16
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
BB67_1:
v_add_nc_u32_e32 v12, s4, v9
s_barrier
global_load_dwordx2 v[14:15], v[7:8], off offset:-16
s_add_i32 s4, s4, 16
v_ashrrev_i32_e32 v13, 31, v12
s_cmp_eq_u32 s4, s0
v_lshlrev_b64 v[16:17], 1, v[12:13]
v_add_nc_u32_e32 v12, 8, v12
v_add_co_u32 v16, vcc_lo, s8, v16
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_ci_u32_e32 v17, vcc_lo, s9, v17, vcc_lo
v_lshlrev_b64 v[12:13], 1, v[12:13]
global_load_ushort v16, v[16:17], off
v_add_co_u32 v12, vcc_lo, s8, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
global_load_ushort v26, v[12:13], off
s_waitcnt vmcnt(2)
ds_write_b64 v2, v[14:15]
s_waitcnt vmcnt(1)
ds_write_b16 v3, v16
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
ds_read_b128 v[12:15], v4
ds_read2_b64 v[16:19], v4 offset0:2 offset1:3
ds_read_b128 v[20:23], v5
s_waitcnt lgkmcnt(2)
v_lshrrev_b32_e32 v28, 16, v15
v_and_b32_e32 v31, v10, v12
s_waitcnt lgkmcnt(1)
v_lshrrev_b32_e32 v27, 16, v16
v_and_b32_sdwa v12, v10, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_e32 v33, v10, v14
ds_read_u16_d16_hi v28, v6
s_waitcnt lgkmcnt(0)
s_barrier
global_load_dwordx2 v[24:25], v[7:8], off
v_and_b32_sdwa v34, v10, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v14, v16, 16, v31
v_and_b32_e32 v32, v10, v13
v_lshl_or_b32 v12, v27, 16, v12
v_and_b32_e32 v35, v10, v15
v_lshrrev_b32_e32 v29, 16, v17
v_pk_fma_f16 v11, v14, v20, v11 op_sel_hi:[1,0,1]
v_and_b32_sdwa v13, v10, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v15, v17, 16, v32
ds_write_b16 v3, v26
v_lshrrev_b32_e32 v30, 16, v18
v_pk_fma_f16 v11, v12, v20, v11 op_sel:[0,1,0]
v_lshl_or_b32 v16, v29, 16, v13
v_lshl_or_b32 v20, v18, 16, v33
v_lshl_or_b32 v19, v19, 16, v35
v_lshl_or_b32 v29, v30, 16, v34
v_pk_fma_f16 v15, v15, v21, v11 op_sel_hi:[1,0,1]
v_add_co_u32 v7, vcc_lo, v7, 32
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
v_pk_fma_f16 v21, v16, v21, v15 op_sel:[0,1,0]
v_pk_fma_f16 v20, v20, v22, v21 op_sel_hi:[1,0,1]
v_pk_fma_f16 v20, v29, v22, v20 op_sel:[0,1,0]
v_pk_fma_f16 v19, v19, v23, v20 op_sel_hi:[1,0,1]
v_pk_fma_f16 v19, v28, v23, v19 op_sel:[0,1,0]
s_waitcnt vmcnt(0)
ds_write_b64 v2, v[24:25]
s_waitcnt lgkmcnt(0)
s_barrier
ds_read_b128 v[11:14], v4
ds_read2_b64 v[15:18], v4 offset0:2 offset1:3
ds_read_b128 v[24:27], v5
s_waitcnt lgkmcnt(2)
v_and_b32_e32 v20, v10, v11
s_waitcnt lgkmcnt(1)
v_lshrrev_b32_e32 v21, 16, v15
v_and_b32_sdwa v11, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v15, v15, 16, v20
v_and_b32_e32 v20, v10, v12
v_lshl_or_b32 v11, v21, 16, v11
v_and_b32_sdwa v12, v10, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v15, v15, v24, v19 op_sel_hi:[1,0,1]
v_lshrrev_b32_e32 v19, 16, v16
v_lshl_or_b32 v16, v16, 16, v20
v_and_b32_e32 v20, v10, v13
v_and_b32_sdwa v13, v10, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_fma_f16 v11, v11, v24, v15 op_sel:[0,1,0]
v_lshrrev_b32_e32 v15, 16, v14
v_lshl_or_b32 v12, v19, 16, v12
v_pk_fma_f16 v11, v16, v25, v11 op_sel_hi:[1,0,1]
v_lshrrev_b32_e32 v16, 16, v17
v_lshl_or_b32 v17, v17, 16, v20
ds_read_u16_d16_hi v15, v6
v_pk_fma_f16 v11, v12, v25, v11 op_sel:[0,1,0]
v_and_b32_e32 v12, v10, v14
v_lshl_or_b32 v13, v16, 16, v13
v_pk_fma_f16 v11, v17, v26, v11 op_sel_hi:[1,0,1]
v_lshl_or_b32 v12, v18, 16, v12
v_pk_fma_f16 v11, v13, v26, v11 op_sel:[0,1,0]
v_pk_fma_f16 v11, v12, v27, v11 op_sel_hi:[1,0,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v11, v15, v27, v11 op_sel:[0,1,0]
s_cbranch_scc0 BB67_1
v_and_b32_e32 v0, 15, v0
s_lshl_b32 s0, s6, 4
v_and_or_b32 v0, 0x7e00, v1, v0
v_add_nc_u32_e32 v0, s1, v0
v_and_or_b32 v0, 0xf0, s0, v0
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_short v[0:1], v11, off
global_store_short_d16_hi v[0:1], v11, off offset:512
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_dense_3_kernel0
.amdhsa_group_segment_fixed_size 320
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 36
.amdhsa_next_free_sgpr 12
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end67:
.size tvmgen_default_fused_nn_dense_3_kernel0, .Lfunc_end67-tvmgen_default_fused_nn_dense_3_kernel0
.globl tvmgen_default_fused_nn_dense_4_kernel0
.p2align 8
.type tvmgen_default_fused_nn_dense_4_kernel0,@function
tvmgen_default_fused_nn_dense_4_kernel0:
v_lshlrev_b32_e32 v3, 8, v0
s_clause 0x2
s_load_dwordx2 s[0:1], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[4:5], s[4:5], 0x0
v_lshlrev_b32_e32 v5, 5, v0
v_and_b32_e32 v4, 7, v0
v_lshl_add_u32 v1, s6, 14, v3
v_and_b32_e32 v6, 0x3f0, v0
v_lshlrev_b32_e32 v9, 1, v0
v_and_b32_e32 v7, 0x1e0, v5
v_and_or_b32 v4, 0x7f00, v5, v4
v_ashrrev_i32_e32 v2, 31, v1
s_movk_i32 s7, 0x640
v_lshlrev_b32_e32 v12, 1, v6
v_add_nc_u32_e32 v15, s7, v7
v_lshlrev_b32_e32 v4, 1, v4
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_cmp_gt_i32_e32 vcc_lo, 64, v0
v_lshl_add_u32 v8, v0, 4, s7
v_or_b32_e32 v14, 30, v9
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v24, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v17, s0, s0, v1
v_mov_b32_e32 v1, 0
v_add_co_ci_u32_e64 v18, s0, s1, v2, s0
v_add_co_u32 v19, s0, s4, v4
v_mov_b32_e32 v2, 0
v_add_co_ci_u32_e64 v20, s0, s5, 0, s0
v_mov_b32_e32 v25, 0
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
v_mov_b32_e32 v28, 0
v_mov_b32_e32 v29, 0
v_mov_b32_e32 v30, 0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v22, 0
s_mov_b64 s[4:5], 0
s_branch BB68_2
BB68_1:
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_barrier
ds_read_b128 v[31:34], v15 offset:16
ds_read_b128 v[35:38], v15
ds_read_b128 v[39:42], v15 offset:528
ds_read_b128 v[43:46], v15 offset:512
ds_read2_b64 v[47:50], v12 offset0:2 offset1:42
ds_read2_b64 v[51:54], v12 offset0:82 offset1:122
ds_read_b128 v[55:58], v12 offset:320
v_mov_b32_e32 v59, 0xffff
s_add_u32 s4, s4, 16
s_addc_u32 s5, s5, 0
s_cmpk_eq_i32 s4, 0x200
s_waitcnt lgkmcnt(6)
v_lshrrev_b32_e32 v60, 16, v31
s_waitcnt lgkmcnt(5)
v_and_b32_e32 v62, v59, v35
v_and_b32_sdwa v35, v59, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
s_waitcnt lgkmcnt(3)
v_and_b32_e32 v65, v59, v43
v_lshrrev_b32_e32 v63, 16, v39
v_and_b32_sdwa v43, v59, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v62, v31, 16, v62
v_and_b32_e32 v66, v59, v36
v_lshl_or_b32 v65, v39, 16, v65
v_and_b32_e32 v67, v59, v44
v_lshl_or_b32 v60, v60, 16, v35
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v26, v51, v62, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v53, v62, v24 op_sel_hi:[0,1,1]
v_lshl_or_b32 v43, v63, 16, v43
v_pk_fma_f16 v25, v51, v65, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v53, v65, v23 op_sel_hi:[0,1,1]
v_lshrrev_b32_e32 v64, 16, v40
v_and_b32_sdwa v44, v59, v44 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v61, 16, v32
v_and_b32_sdwa v36, v59, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v63, v32, 16, v66
v_pk_fma_f16 v26, v51, v60, v26 op_sel:[1,0,0]
v_pk_fma_f16 v24, v53, v60, v24 op_sel:[1,0,0]
v_lshl_or_b32 v44, v64, 16, v44
v_lshl_or_b32 v64, v40, 16, v67
v_pk_fma_f16 v25, v51, v43, v25 op_sel:[1,0,0]
v_pk_fma_f16 v23, v53, v43, v23 op_sel:[1,0,0]
v_lshl_or_b32 v61, v61, 16, v36
v_pk_fma_f16 v26, v52, v63, v26 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v54, v63, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v52, v64, v25 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v54, v64, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v49, v62, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v49, v65, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v51, v52, v61, v26 op_sel:[1,0,0]
v_pk_fma_f16 v53, v54, v61, v24 op_sel:[1,0,0]
v_pk_fma_f16 v52, v52, v44, v25 op_sel:[1,0,0]
v_pk_fma_f16 v54, v54, v44, v23 op_sel:[1,0,0]
ds_read_b128 v[23:26], v12
v_pk_fma_f16 v30, v47, v62, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v47, v65, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v28, v49, v60, v28 op_sel:[1,0,0]
v_pk_fma_f16 v27, v49, v43, v27 op_sel:[1,0,0]
v_lshrrev_b32_e32 v31, 16, v33
v_pk_fma_f16 v30, v47, v60, v30 op_sel:[1,0,0]
v_pk_fma_f16 v29, v47, v43, v29 op_sel:[1,0,0]
v_pk_fma_f16 v28, v50, v63, v28 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v50, v64, v27 op_sel_hi:[0,1,1]
v_and_b32_sdwa v35, v59, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_fma_f16 v30, v48, v63, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v48, v64, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v49, v50, v61, v28 op_sel:[1,0,0]
v_pk_fma_f16 v50, v50, v44, v27 op_sel:[1,0,0]
v_and_b32_e32 v27, v59, v37
v_and_b32_e32 v28, v59, v38
v_pk_fma_f16 v47, v48, v61, v30 op_sel:[1,0,0]
v_pk_fma_f16 v48, v48, v44, v29 op_sel:[1,0,0]
v_and_b32_e32 v29, v59, v46
v_lshl_or_b32 v66, v33, 16, v27
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v21, v23, v62, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v23, v65, v22 op_sel_hi:[0,1,1]
v_and_b32_e32 v27, v59, v45
v_and_b32_sdwa v36, v59, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v32, 16, v34
v_lshl_or_b32 v67, v34, 16, v28
v_lshrrev_b32_e32 v33, 16, v41
v_lshrrev_b32_e32 v34, 16, v42
v_and_b32_sdwa v38, v59, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v37, v59, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_fma_f16 v21, v23, v60, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v23, v43, v22 op_sel:[1,0,0]
v_lshl_or_b32 v68, v41, 16, v27
v_lshl_or_b32 v69, v42, 16, v29
ds_read_b128 v[27:30], v12 offset:640
ds_read_u16 v45, v12 offset:24
ds_read_u16 v46, v12 offset:26
ds_read_u16 v59, v12 offset:28
ds_read_u16 v71, v12 offset:344
ds_read_u16 v72, v12 offset:346
ds_read_u16 v73, v12 offset:348
ds_read_u16 v76, v12 offset:664
ds_read_u16 v77, v12 offset:666
ds_read_u16 v78, v12 offset:350
v_lshl_or_b32 v70, v31, 16, v35
v_lshl_or_b32 v23, v33, 16, v37
v_lshl_or_b32 v74, v32, 16, v36
v_lshl_or_b32 v75, v34, 16, v38
ds_read_b128 v[31:34], v12 offset:960
ds_read_b128 v[35:38], v12 offset:1280
ds_read2_b64 v[39:42], v12 offset0:162 offset1:163
v_pk_fma_f16 v21, v24, v63, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v24, v64, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v55, v62, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v55, v65, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v24, v61, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v24, v44, v22 op_sel:[1,0,0]
v_pk_fma_f16 v11, v55, v60, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v55, v43, v10 op_sel:[1,0,0]
s_waitcnt lgkmcnt(12)
v_pk_fma_f16 v13, v27, v62, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v27, v65, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v21, v25, v66, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v25, v68, v22 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v56, v63, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v27, v60, v13 op_sel:[1,0,0]
v_pk_fma_f16 v16, v27, v43, v16 op_sel:[1,0,0]
v_pk_fma_f16 v21, v25, v70, v21 op_sel:[1,0,0]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v7, v31, v62, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v31, v65, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v28, v63, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v28, v64, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v25, v23, v22 op_sel:[1,0,0]
v_pk_fma_f16 v7, v31, v60, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v31, v43, v6 op_sel:[1,0,0]
v_pk_fma_f16 v13, v28, v61, v13 op_sel:[1,0,0]
v_pk_fma_f16 v16, v28, v44, v16 op_sel:[1,0,0]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v5, v35, v62, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v32, v63, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v32, v64, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v35, v65, v4 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v2, v39, v62, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v39, v65, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v32, v61, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v32, v44, v6 op_sel:[1,0,0]
v_pk_fma_f16 v21, v26, v67, v21 op_sel_hi:[0,1,1]
v_pk_fma_f16 v22, v26, v69, v22 op_sel_hi:[0,1,1]
ds_read_u16 v24, v12 offset:984
ds_read_u16 v25, v12 offset:670
v_pk_fma_f16 v13, v29, v66, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v29, v68, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v35, v60, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v35, v43, v4 op_sel:[1,0,0]
v_pk_fma_f16 v7, v33, v66, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v33, v68, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v39, v60, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v39, v43, v1 op_sel:[1,0,0]
v_pk_fma_f16 v21, v26, v74, v21 op_sel:[1,0,0]
v_pk_fma_f16 v22, v26, v75, v22 op_sel:[1,0,0]
ds_read_u16 v55, v12 offset:990
ds_read_u16 v26, v12 offset:668
ds_read_u16 v27, v12 offset:986
ds_read_u16 v28, v12 offset:988
v_pk_fma_f16 v10, v56, v64, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v29, v70, v13 op_sel:[1,0,0]
v_pk_fma_f16 v16, v29, v23, v16 op_sel:[1,0,0]
v_pk_fma_f16 v5, v36, v63, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v36, v64, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v33, v70, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v33, v23, v6 op_sel:[1,0,0]
v_pk_fma_f16 v2, v40, v63, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v40, v64, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v56, v61, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v56, v44, v10 op_sel:[1,0,0]
v_pk_fma_f16 v13, v30, v67, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v16, v30, v69, v16 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v36, v61, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v36, v44, v4 op_sel:[1,0,0]
v_pk_fma_f16 v7, v34, v67, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v34, v69, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v40, v61, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v40, v44, v1 op_sel:[1,0,0]
ds_read_u16 v36, v14
s_waitcnt lgkmcnt(6)
v_pk_fma_f16 v35, v24, v66, v53 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v57, v66, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v57, v68, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v37, v66, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v37, v68, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v45, v66, v47 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v71, v66, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v71, v68, v50 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v76, v66, v51 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v24, v68, v54 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v41, v66, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v41, v68, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v30, v74, v13 op_sel:[1,0,0]
v_pk_fma_f16 v16, v30, v75, v16 op_sel:[1,0,0]
v_pk_fma_f16 v30, v45, v68, v48 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v34, v74, v7 op_sel:[1,0,0]
v_pk_fma_f16 v6, v34, v75, v6 op_sel:[1,0,0]
v_pk_fma_f16 v34, v76, v68, v52 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v57, v70, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v57, v23, v10 op_sel:[1,0,0]
v_pk_fma_f16 v5, v37, v70, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v37, v23, v4 op_sel:[1,0,0]
v_pk_fma_f16 v31, v72, v70, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v72, v23, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v77, v70, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v77, v23, v34 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(2)
v_pk_fma_f16 v35, v27, v70, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v41, v70, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v41, v23, v1 op_sel:[1,0,0]
v_pk_fma_f16 v24, v27, v23, v24 op_sel_hi:[0,1,1]
v_pk_fma_f16 v30, v46, v23, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v46, v70, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v58, v67, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v58, v69, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v38, v67, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v4, v38, v69, v4 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v42, v67, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v42, v69, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v59, v67, v29 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v59, v69, v30 op_sel_hi:[0,1,1]
v_pk_fma_f16 v31, v73, v67, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v32, v73, v69, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v33, v26, v67, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v34, v26, v69, v34 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v35, v28, v67, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v37, v28, v69, v24 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v30, v36, v74, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v29, v36, v75, v27 op_sel_hi:[0,1,1]
v_pk_fma_f16 v26, v25, v74, v33 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v58, v74, v11 op_sel:[1,0,0]
v_pk_fma_f16 v10, v58, v75, v10 op_sel:[1,0,0]
v_pk_fma_f16 v5, v38, v74, v5 op_sel:[1,0,0]
v_pk_fma_f16 v4, v38, v75, v4 op_sel:[1,0,0]
v_pk_fma_f16 v28, v78, v74, v31 op_sel_hi:[0,1,1]
v_pk_fma_f16 v27, v78, v75, v32 op_sel_hi:[0,1,1]
v_pk_fma_f16 v25, v25, v75, v34 op_sel_hi:[0,1,1]
v_pk_fma_f16 v24, v55, v74, v35 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v55, v75, v37 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v42, v74, v2 op_sel:[1,0,0]
v_pk_fma_f16 v1, v42, v75, v1 op_sel:[1,0,0]
s_cbranch_scc1 BB68_4
BB68_2:
v_add_co_u32 v31, s0, v19, s4
v_add_co_ci_u32_e64 v32, s0, s5, v20, s0
v_add_co_u32 v33, s0, 0x2800, v31
v_add_co_ci_u32_e64 v34, s0, 0, v32, s0
v_add_co_u32 v35, s0, 0x5000, v31
v_add_co_ci_u32_e64 v36, s0, 0, v32, s0
v_add_co_u32 v37, s0, 0x7800, v31
v_add_co_ci_u32_e64 v38, s0, 0, v32, s0
v_add_co_u32 v39, s0, 0xa000, v31
v_add_co_ci_u32_e64 v40, s0, 0, v32, s0
s_clause 0x4
global_load_ushort v31, v[31:32], off
global_load_ushort v32, v[33:34], off
global_load_ushort v33, v[35:36], off
global_load_ushort v34, v[37:38], off
global_load_ushort v35, v[39:40], off
s_waitcnt vmcnt(0)
s_barrier
ds_write_b16 v9, v31
ds_write_b16 v9, v32 offset:320
ds_write_b16 v9, v33 offset:640
ds_write_b16 v9, v34 offset:960
ds_write_b16 v9, v35 offset:1280
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz BB68_1
v_add_co_u32 v31, s0, v17, s4
v_add_co_ci_u32_e64 v32, s0, s5, v18, s0
global_load_dwordx4 v[31:34], v[31:32], off
s_waitcnt vmcnt(0)
ds_write_b128 v8, v[31:34]
s_branch BB68_1
BB68_4:
v_and_b32_e32 v3, 0x3f000, v3
v_lshlrev_b32_e32 v0, 1, v0
v_lshl_add_u32 v3, s6, 6, v3
v_and_or_b32 v8, v0, 30, v3
v_ashrrev_i32_e32 v9, 31, v8
v_add_nc_u32_e32 v17, 0x800, v8
v_add_nc_u32_e32 v3, 0x820, v8
v_lshlrev_b64 v[14:15], 1, v[8:9]
v_ashrrev_i32_e32 v18, 31, v17
v_add_co_u32 v14, vcc_lo, s2, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
v_add_co_u32 v19, vcc_lo, 0x50000, v14
v_add_co_ci_u32_e32 v20, vcc_lo, 0, v15, vcc_lo
global_store_short v[14:15], v22, off offset:64
global_store_dword v[14:15], v21, off
global_store_short_d16_hi v[14:15], v22, off offset:66
v_add_co_u32 v21, vcc_lo, 0x3c000, v14
v_add_co_ci_u32_e32 v22, vcc_lo, 0, v15, vcc_lo
v_add_co_u32 v31, vcc_lo, 0x28000, v14
v_add_co_ci_u32_e32 v32, vcc_lo, 0, v15, vcc_lo
v_add_co_u32 v14, vcc_lo, 0x14000, v14
global_store_dword v[19:20], v4, off offset:64
global_store_dword v[19:20], v5, off
global_store_dword v[21:22], v6, off offset:64
global_store_dword v[21:22], v7, off
global_store_dword v[31:32], v16, off offset:64
global_store_dword v[31:32], v13, off
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo
v_add_nc_u32_e32 v5, 0xa800, v8
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v13, 0x14800, v8
v_add_nc_u32_e32 v19, 0x1e820, v8
global_store_dword v[14:15], v11, off
v_add_nc_u32_e32 v11, 0xa820, v8
global_store_dword v[14:15], v10, off offset:64
v_lshlrev_b64 v[9:10], 1, v[17:18]
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_ashrrev_i32_e32 v12, 31, v11
v_add_nc_u32_e32 v15, 0x14820, v8
v_ashrrev_i32_e32 v14, 31, v13
v_add_co_u32 v9, vcc_lo, s2, v9
v_lshlrev_b64 v[5:6], 1, v[5:6]
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
v_add_nc_u32_e32 v17, 0x1e800, v8
v_add_co_u32 v3, vcc_lo, s2, v3
v_lshlrev_b64 v[11:12], 1, v[11:12]
v_ashrrev_i32_e32 v16, 31, v15
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
v_lshlrev_b64 v[13:14], 1, v[13:14]
v_ashrrev_i32_e32 v18, 31, v17
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_nc_u32_e32 v21, 0x28800, v8
v_add_co_u32 v11, vcc_lo, s2, v11
v_lshlrev_b64 v[15:16], 1, v[15:16]
v_ashrrev_i32_e32 v20, 31, v19
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
v_add_nc_u32_e32 v7, 0x28820, v8
v_add_co_u32 v13, vcc_lo, s2, v13
v_lshlrev_b64 v[17:18], 1, v[17:18]
v_ashrrev_i32_e32 v22, 31, v21
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
v_add_co_u32 v15, vcc_lo, s2, v15
v_lshlrev_b64 v[19:20], 1, v[19:20]
v_ashrrev_i32_e32 v8, 31, v7
v_add_co_ci_u32_e32 v16, vcc_lo, s3, v16, vcc_lo
v_add_co_u32 v17, vcc_lo, s2, v17
v_lshlrev_b64 v[21:22], 1, v[21:22]
v_add_co_ci_u32_e32 v18, vcc_lo, s3, v18, vcc_lo
v_add_co_u32 v19, vcc_lo, s2, v19
v_lshlrev_b64 v[7:8], 1, v[7:8]
v_add_co_ci_u32_e32 v20, vcc_lo, s3, v20, vcc_lo
v_add_co_u32 v21, vcc_lo, s2, v21
v_add_co_ci_u32_e32 v22, vcc_lo, s3, v22, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_store_dword v[9:10], v30, off
global_store_dword v[3:4], v29, off
global_store_dword v[5:6], v28, off
global_store_dword v[11:12], v27, off
global_store_dword v[13:14], v26, off
global_store_dword v[15:16], v25, off
global_store_dword v[17:18], v24, off
global_store_dword v[19:20], v23, off
global_store_dword v[21:22], v2, off
global_store_dword v[7:8], v1, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_dense_4_kernel0
.amdhsa_group_segment_fixed_size 2624
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 79
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end68:
.size tvmgen_default_fused_nn_dense_4_kernel0, .Lfunc_end68-tvmgen_default_fused_nn_dense_4_kernel0
.globl tvmgen_default_fused_nn_dense_5_kernel0
.p2align 8
.type tvmgen_default_fused_nn_dense_5_kernel0,@function
tvmgen_default_fused_nn_dense_5_kernel0:
s_clause 0x2
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
v_lshrrev_b32_e32 v7, 3, v0
s_ashr_i32 s1, s6, 4
s_mov_b32 s4, 0xa000
v_lshlrev_b32_e32 v6, 7, v0
s_mul_i32 s0, s1, s4
v_and_b32_e32 v1, 7, v0
v_lshl_add_u32 v3, v7, 11, s0
s_lshl_b32 s0, s6, 15
s_movk_i32 s7, 0x200
s_and_b32 s5, s0, 0x78000
v_lshlrev_b32_e32 v2, 1, v0
v_or_b32_e32 v8, s5, v0
v_lshl_or_b32 v3, v1, 1, v3
v_lshl_add_u32 v4, v0, 2, s7
v_lshl_add_u32 v7, v7, 5, s7
v_and_b32_e32 v5, 15, v0
v_lshl_or_b32 v9, v8, 1, 0xf000
v_and_b32_e32 v6, 0x1f800, v6
v_cmp_gt_i32_e32 vcc_lo, 16, v0
v_lshlrev_b32_e32 v8, 5, v1
v_mov_b32_e32 v11, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, s0, s10, v9
v_mov_b32_e32 v12, 0
v_add_co_ci_u32_e64 v10, s0, s11, 0, s0
s_mov_b32 s7, 0
s_branch BB69_2
BB69_1:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_barrier
ds_read_b128 v[13:16], v7
ds_read_b128 v[17:20], v8
ds_read_b128 v[21:24], v8 offset:256
ds_read_b128 v[25:28], v7 offset:320
ds_read_b128 v[29:32], v7 offset:16
ds_read_b128 v[33:36], v8 offset:16
v_lshrrev_b32_e32 v45, 16, v11
v_lshrrev_b32_e32 v46, 16, v12
v_mov_b32_e32 v47, 0xffff
ds_read_b128 v[37:40], v8 offset:272
ds_read_b128 v[41:44], v7 offset:336
v_add_co_u32 v9, s0, v9, 32
s_add_i32 s7, s7, 16
v_add_co_ci_u32_e64 v10, s0, 0, v10, s0
s_cmpk_eq_i32 s7, 0x800
s_waitcnt lgkmcnt(7)
v_lshrrev_b32_e32 v48, 16, v13
s_waitcnt lgkmcnt(6)
v_lshrrev_b32_e32 v50, 16, v17
v_fmac_f16_e32 v11, v13, v17
s_waitcnt lgkmcnt(5)
v_fmac_f16_e32 v45, v13, v21
v_lshrrev_b32_e32 v52, 16, v21
s_waitcnt lgkmcnt(4)
v_fmac_f16_e32 v12, v25, v17
v_lshrrev_b32_e32 v13, 16, v25
v_fmac_f16_e32 v46, v25, v21
v_fmac_f16_e32 v11, v48, v50
v_fmac_f16_e32 v45, v48, v52
v_lshrrev_b32_e32 v49, 16, v14
v_fmac_f16_e32 v12, v13, v50
v_fmac_f16_e32 v46, v13, v52
v_lshrrev_b32_e32 v51, 16, v18
v_fmac_f16_e32 v11, v14, v18
v_fmac_f16_e32 v45, v14, v22
v_lshrrev_b32_e32 v17, 16, v22
v_fmac_f16_e32 v12, v26, v18
v_lshrrev_b32_e32 v13, 16, v26
v_fmac_f16_e32 v46, v26, v22
v_fmac_f16_e32 v11, v49, v51
v_fmac_f16_e32 v45, v49, v17
v_lshrrev_b32_e32 v14, 16, v23
v_fmac_f16_e32 v12, v13, v51
v_fmac_f16_e32 v46, v13, v17
v_and_b32_sdwa v13, v47, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_fmac_f16_e32 v11, v15, v19
v_fmac_f16_e32 v45, v15, v23
v_fmac_f16_e32 v12, v27, v19
v_fmac_f16_e32 v46, v27, v23
v_and_b32_e32 v17, v47, v20
v_lshl_or_b32 v13, v14, 16, v13
v_pack_b32_f16 v11, v11, v45
v_lshrrev_b32_e32 v14, 16, v24
v_pack_b32_f16 v12, v12, v46
v_and_b32_sdwa v18, v47, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v17, v24, 16, v17
v_pk_fma_f16 v11, v15, v13, v11 op_sel:[1,0,0]
s_waitcnt lgkmcnt(1)
v_lshrrev_b32_e32 v15, 16, v37
v_pk_fma_f16 v12, v27, v13, v12 op_sel:[1,0,0]
v_and_b32_e32 v13, v47, v33
v_lshl_or_b32 v14, v14, 16, v18
v_pk_fma_f16 v11, v16, v17, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v28, v17, v12 op_sel_hi:[0,1,1]
v_and_b32_sdwa v17, v47, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v13, v37, 16, v13
v_pk_fma_f16 v11, v16, v14, v11 op_sel:[1,0,0]
v_and_b32_sdwa v16, v47, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_fma_f16 v12, v28, v14, v12 op_sel:[1,0,0]
v_and_b32_e32 v14, v47, v34
v_lshl_or_b32 v15, v15, 16, v17
v_pk_fma_f16 v11, v29, v13, v11 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v12, v41, v13, v12 op_sel_hi:[0,1,1]
v_lshrrev_b32_e32 v13, 16, v38
v_lshl_or_b32 v14, v38, 16, v14
v_pk_fma_f16 v11, v29, v15, v11 op_sel:[1,0,0]
v_pk_fma_f16 v12, v41, v15, v12 op_sel:[1,0,0]
v_and_b32_e32 v15, v47, v35
v_lshl_or_b32 v13, v13, 16, v16
v_pk_fma_f16 v11, v30, v14, v11 op_sel_hi:[0,1,1]
v_and_b32_sdwa v16, v47, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_fma_f16 v12, v42, v14, v12 op_sel_hi:[0,1,1]
v_lshrrev_b32_e32 v14, 16, v39
v_lshl_or_b32 v15, v39, 16, v15
v_pk_fma_f16 v11, v30, v13, v11 op_sel:[1,0,0]
v_pk_fma_f16 v12, v42, v13, v12 op_sel:[1,0,0]
v_and_b32_e32 v13, v47, v36
v_lshl_or_b32 v14, v14, 16, v16
v_pk_fma_f16 v11, v31, v15, v11 op_sel_hi:[0,1,1]
v_and_b32_sdwa v16, v47, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_pk_fma_f16 v12, v43, v15, v12 op_sel_hi:[0,1,1]
v_lshrrev_b32_e32 v15, 16, v40
v_lshl_or_b32 v13, v40, 16, v13
v_pk_fma_f16 v11, v31, v14, v11 op_sel:[1,0,0]
v_pk_fma_f16 v12, v43, v14, v12 op_sel:[1,0,0]
v_lshl_or_b32 v14, v15, 16, v16
v_pk_fma_f16 v11, v32, v13, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v44, v13, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v32, v14, v11 op_sel:[1,0,0]
v_pk_fma_f16 v12, v44, v14, v12 op_sel:[1,0,0]
s_cbranch_scc1 BB69_4
BB69_2:
s_add_i32 s0, s5, s7
v_add_nc_u32_e32 v13, s7, v3
v_or_b32_e32 v14, s0, v5
v_add_nc_u32_e32 v15, v14, v6
v_ashrrev_i32_e32 v14, 31, v13
v_ashrrev_i32_e32 v16, 31, v15
v_lshlrev_b64 v[13:14], 1, v[13:14]
v_lshlrev_b64 v[15:16], 1, v[15:16]
v_add_co_u32 v13, s0, s8, v13
v_add_co_ci_u32_e64 v14, s0, s9, v14, s0
v_add_co_u32 v15, s0, s10, v15
v_add_co_ci_u32_e64 v16, s0, s11, v16, s0
v_add_co_u32 v17, s0, s4, v13
v_add_co_ci_u32_e64 v18, s0, 0, v14, s0
v_add_co_u32 v19, s0, 0x5000, v15
v_add_co_ci_u32_e64 v20, s0, 0, v16, s0
v_add_co_u32 v21, s0, s4, v15
v_add_co_ci_u32_e64 v22, s0, 0, v16, s0
s_clause 0x1
global_load_dword v13, v[13:14], off
global_load_dword v14, v[17:18], off
s_clause 0x2
global_load_ushort v15, v[15:16], off
global_load_ushort v16, v[19:20], off
global_load_ushort v17, v[21:22], off
s_waitcnt vmcnt(0)
s_barrier
ds_write2_b32 v4, v13, v14 offset1:80
ds_write_b16 v2, v15
ds_write_b16 v2, v16 offset:160
ds_write_b16 v2, v17 offset:320
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB69_1
global_load_ushort v13, v[9:10], off
s_waitcnt vmcnt(0)
ds_write_b16 v2, v13 offset:480
s_branch BB69_1
BB69_4:
v_lshlrev_b32_e32 v0, 5, v0
s_mulk_i32 s1, 0x1400
s_lshl_b32 s0, s6, 4
s_and_b32 s0, s0, 0xf0
v_and_b32_e32 v0, 0x7f00, v0
v_add_nc_u32_e32 v0, s1, v0
v_or3_b32 v0, v0, s0, v1
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, 0x1000, v0
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
global_store_short v[0:1], v11, off
global_store_short_d16_hi v[0:1], v11, off offset:16
global_store_short v[2:3], v12, off offset:1024
global_store_short_d16_hi v[2:3], v12, off offset:1040
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_dense_5_kernel0
.amdhsa_group_segment_fixed_size 1152
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 53
.amdhsa_next_free_sgpr 12
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end69:
.size tvmgen_default_fused_nn_dense_5_kernel0, .Lfunc_end69-tvmgen_default_fused_nn_dense_5_kernel0
.globl tvmgen_default_fused_nn_dense_6_kernel0
.p2align 8
.type tvmgen_default_fused_nn_dense_6_kernel0,@function
tvmgen_default_fused_nn_dense_6_kernel0:
v_lshlrev_b32_e32 v1, 1, v0
s_mov_b64 s[18:19], s[2:3]
v_add_nc_u32_e32 v5, 50, v0
s_mov_b64 s[16:17], s[0:1]
s_movk_i32 s0, 0xf00
v_add_nc_u32_e32 v4, 0x2b2, v1
v_add_nc_u32_e32 v6, 0x564, v1
s_add_u32 s16, s16, s7
s_movk_i32 s7, 0x7f
v_add_nc_u32_e32 v3, 0x59, v0
v_and_b32_e32 v38, s0, v4
v_add_nc_u32_e32 v4, 0x816, v1
v_and_b32_e32 v127, s7, v5
v_mov_b32_e32 v2, 0x7f
v_add_nc_u32_e32 v5, 0x64, v0
v_and_b32_e32 v34, s0, v6
s_movk_i32 s0, 0x1f00
v_and_b32_e32 v15, s7, v3
v_and_b32_e32 v21, s0, v4
v_add_nc_u32_e32 v4, 0xac8, v1
v_add_nc_u32_e32 v3, 11, v0
v_and_b32_e32 v22, v2, v5
v_add_nc_u32_e32 v5, 61, v0
v_add_nc_u32_e32 v7, 22, v0
v_add_nc_u32_e32 v6, 0xd7a, v1
v_and_b32_e32 v23, s0, v4
v_add_nc_u32_e32 v4, 0x6f, v0
v_and_b32_e32 v88, v2, v3
v_and_b32_e32 v24, v2, v5
v_and_b32_e32 v26, v2, v7
v_mov_b32_e32 v3, 0x1f00
v_add_nc_u32_e32 v5, 0x12de, v1
v_add_nc_u32_e32 v7, 0x1590, v1
v_add_nc_u32_e32 v8, 0x102c, v1
v_and_b32_e32 v25, s0, v6
v_add_nc_u32_e32 v6, 0x48, v0
v_and_b32_e32 v28, v2, v4
v_add_nc_u32_e32 v4, 0x7a, v0
v_and_b32_e32 v29, v3, v5
v_and_b32_e32 v30, v3, v7
v_add_nc_u32_e32 v3, 0x1842, v1
v_and_b32_e32 v27, s0, v8
v_and_b32_e32 v31, v2, v6
s_movk_i32 s0, 0x3f00
v_add_nc_u32_e32 v6, 0x1af4, v1
v_and_b32_e32 v73, v2, v4
v_add_nc_u32_e32 v4, 0x1da6, v1
v_and_b32_e32 v33, s0, v3
v_add_nc_u32_e32 v3, 0x53, v0
v_add_nc_u32_e32 v7, 0x2058, v1
v_and_b32_e32 v110, s0, v6
v_and_b32_e32 v16, s0, v4
s_movk_i32 s0, 0x2f00
v_add_nc_u32_e32 v8, 33, v0
v_and_b32_e32 v17, v2, v3
v_and_b32_e32 v18, s0, v7
v_add_nc_u32_e32 v3, 5, v0
v_add_nc_u32_e32 v7, 0x25bc, v1
v_and_b32_e32 v32, v2, v8
v_add_nc_u32_e32 v8, 55, v0
v_mov_b32_e32 v5, 0x3f00
v_and_b32_e32 v44, v2, v3
v_and_b32_e32 v49, s0, v7
v_add_nc_u32_e32 v3, 0x286e, v1
v_add_nc_u32_e32 v7, 0x2dd2, v1
v_and_b32_e32 v50, v2, v8
v_add_nc_u32_e32 v8, 0x42, v0
s_addc_u32 s17, s17, 0
v_and_b32_e32 v51, v5, v3
v_and_b32_e32 v3, v5, v7
s_clause 0x2
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
v_add_nc_u32_e32 v6, 44, v0
v_add_nc_u32_e32 v4, 0x230a, v1
v_add_nc_u32_e32 v7, 0x74, v0
buffer_store_dword v3, off, s[16:19], 0 offset:4
v_and_b32_e32 v3, v2, v8
v_and_b32_e32 v19, v2, v6
v_and_b32_e32 v47, s0, v4
v_add_nc_u32_e32 v6, 0x5e, v0
v_add_nc_u32_e32 v4, 16, v0
buffer_store_dword v3, off, s[16:19], 0 offset:8
v_add_nc_u32_e32 v3, 0x3084, v1
v_add_nc_u32_e32 v8, 0x35e8, v1
v_and_b32_e32 v48, v2, v6
v_add_nc_u32_e32 v6, 0x2b20, v1
v_and_b32_e32 v54, v2, v4
v_and_b32_e32 v3, v5, v3
v_add_nc_u32_e32 v4, 27, v0
v_add_nc_u32_e32 v10, 0x58f2, v1
v_and_b32_e32 v53, v5, v6
v_add_nc_u32_e32 v6, 0x3336, v1
buffer_store_dword v3, off, s[16:19], 0 offset:12
v_and_b32_e32 v3, v2, v4
v_mov_b32_e32 v4, 0x7f00
v_add_nc_u32_e32 v12, 0x6bd0, v1
v_add_nc_u32_e32 v9, 38, v0
v_add_nc_u32_e32 v11, -1, v0
buffer_store_dword v3, off, s[16:19], 0 offset:16
v_and_b32_e32 v3, v5, v6
v_mul_hi_i32 v6, 0xb21642c9, v0
v_and_b32_e32 v52, s7, v0
v_cmp_gt_i32_e64 s0, 0xb4, v0
v_cmp_gt_i32_e64 s1, 23, v0
buffer_store_dword v3, off, s[16:19], 0 offset:20
v_and_b32_e32 v3, v2, v7
v_add_nc_u32_e32 v7, 0x538e, v1
s_movk_i32 s7, 0x7f00
s_movk_i32 s12, 0x4f00
s_movk_i32 s13, 0x2e00
buffer_store_dword v3, off, s[16:19], 0 offset:24
v_and_b32_e32 v3, v5, v8
v_mov_b32_e32 v5, 0x5f00
v_add_nc_u32_e32 v8, 0x5640, v1
v_and_b32_e32 v55, 0x700, v1
v_add_nc_u32_e32 v111, s13, v1
buffer_store_dword v3, off, s[16:19], 0 offset:28
v_and_b32_e32 v7, v5, v7
v_and_b32_e32 v5, v5, v8
v_add_nc_u32_e32 v8, 0x691e, v1
v_add_nc_u32_e32 v3, 0x4d, v0
v_mov_b32_e32 v89, 0
buffer_store_dword v7, off, s[16:19], 0 offset:32
buffer_store_dword v5, off, s[16:19], 0 offset:36
v_add_nc_u32_e32 v5, v6, v0
v_and_b32_e32 v6, v4, v10
v_add_nc_u32_e32 v7, 0x5e56, v1
v_and_b32_e32 v3, v2, v3
v_mov_b32_e32 v90, 0
v_lshrrev_b32_e32 v10, 31, v5
buffer_store_dword v6, off, s[16:19], 0 offset:40
v_add_nc_u32_e32 v6, 0x5ba4, v1
v_ashrrev_i32_e32 v5, 4, v5
buffer_store_dword v3, off, s[16:19], 0 offset:72
v_and_b32_e32 v3, v2, v9
v_mov_b32_e32 v91, 0
v_and_b32_e32 v6, v4, v6
v_add_nc_u32_e32 v13, v5, v10
v_and_b32_e32 v5, v4, v12
v_add_nc_u32_e32 v10, 0x7698, v1
buffer_store_dword v3, off, s[16:19], 0 offset:76
buffer_store_dword v6, off, s[16:19], 0 offset:44
v_and_b32_e32 v6, v4, v7
buffer_store_dword v5, off, s[16:19], 0 offset:56
v_add_nc_u32_e32 v5, 0x6e82, v1
v_add_nc_u32_e32 v7, 0x73e6, v1
v_and_b32_e32 v3, v2, v11
buffer_store_dword v6, off, s[16:19], 0 offset:48
v_and_b32_e32 v6, v4, v8
v_and_b32_e32 v5, v4, v5
v_mul_lo_u32 v8, 0xb80, v13
buffer_store_dword v3, off, s[16:19], 0 offset:80
v_mul_lo_u32 v9, v13, 23
buffer_store_dword v6, off, s[16:19], 0 offset:52
v_add_nc_u32_e32 v6, 0x7134, v1
buffer_store_dword v5, off, s[16:19], 0 offset:60
v_lshlrev_b32_e32 v5, 7, v0
v_lshl_add_u32 v112, v13, 11, s13
v_mov_b32_e32 v92, 0
v_and_b32_e32 v6, v4, v6
v_mov_b32_e32 v93, 0
v_sub_nc_u32_e32 v5, v5, v8
v_add_nc_u32_e32 v8, 21, v0
v_mov_b32_e32 v94, 0
buffer_store_dword v6, off, s[16:19], 0 offset:64
v_and_b32_e32 v6, v4, v7
v_and_b32_e32 v4, v4, v10
v_add_nc_u32_e32 v7, 60, v0
v_lshlrev_b32_e32 v109, 1, v5
v_mov_b32_e32 v95, 0
buffer_store_dword v6, off, s[16:19], 0 offset:68
buffer_store_dword v4, off, s[16:19], 0 offset:276
v_add_nc_u32_e32 v4, 0x58, v0
v_add_nc_u32_e32 v6, 49, v0
v_mov_b32_e32 v96, 0
v_mov_b32_e32 v97, 0
v_mov_b32_e32 v98, 0
v_and_b32_e32 v3, v2, v4
v_add_nc_u32_e32 v4, 0x63, v0
v_and_b32_e32 v6, v2, v6
v_mov_b32_e32 v99, 0
v_mov_b32_e32 v100, 0
buffer_store_dword v3, off, s[16:19], 0 offset:84
v_add_nc_u32_e32 v3, 10, v0
buffer_store_dword v6, off, s[16:19], 0 offset:88
v_add_nc_u32_e32 v6, 32, v0
v_mov_b32_e32 v101, 0
v_mov_b32_e32 v102, 0
v_and_b32_e32 v3, v2, v3
v_mov_b32_e32 v103, 0
v_mov_b32_e32 v104, 0
s_ashr_i32 s4, s6, 1
s_and_b32 s6, s6, 1
buffer_store_dword v3, off, s[16:19], 0 offset:92
v_and_b32_e32 v3, v2, v4
v_add_nc_u32_e32 v4, 0x47, v0
s_mul_i32 s5, s4, 0x7800
buffer_store_dword v3, off, s[16:19], 0 offset:96
v_and_b32_e32 v3, v2, v7
v_add_nc_u32_e32 v7, 0x79, v0
buffer_store_dword v3, off, s[16:19], 0 offset:100
v_and_b32_e32 v3, v2, v8
v_add_nc_u32_e32 v8, 0x52, v0
buffer_store_dword v3, off, s[16:19], 0 offset:104
v_add_nc_u32_e32 v3, 0x6e, v0
v_and_b32_e32 v3, v2, v3
buffer_store_dword v3, off, s[16:19], 0 offset:108
v_and_b32_e32 v3, v2, v4
v_add_nc_u32_e32 v4, 4, v0
buffer_store_dword v3, off, s[16:19], 0 offset:112
v_and_b32_e32 v3, v2, v6
v_add_nc_u32_e32 v6, 0x5d, v0
buffer_store_dword v3, off, s[16:19], 0 offset:116
v_and_b32_e32 v3, v2, v7
v_add_nc_u32_e32 v7, 54, v0
buffer_store_dword v3, off, s[16:19], 0 offset:120
v_and_b32_e32 v3, v2, v8
v_add_nc_u32_e32 v8, 15, v0
buffer_store_dword v3, off, s[16:19], 0 offset:124
v_add_nc_u32_e32 v3, 43, v0
v_and_b32_e32 v3, v2, v3
buffer_store_dword v3, off, s[16:19], 0 offset:128
v_and_b32_e32 v3, v2, v4
v_add_nc_u32_e32 v4, 0x41, v0
buffer_store_dword v3, off, s[16:19], 0 offset:132
v_and_b32_e32 v3, v2, v6
v_add_nc_u32_e32 v6, 26, v0
buffer_store_dword v3, off, s[16:19], 0 offset:136
v_and_b32_e32 v3, v2, v7
v_add_nc_u32_e32 v7, 0x73, v0
buffer_store_dword v3, off, s[16:19], 0 offset:140
v_and_b32_e32 v3, v2, v8
v_add_nc_u32_e32 v8, 0x69, v0
buffer_store_dword v3, off, s[16:19], 0 offset:144
v_sub_nc_u32_e32 v3, v0, v9
buffer_store_dword v3, off, s[16:19], 0 offset:292
v_add_nc_u32_e32 v3, 0x68, v0
v_add_nc_u32_e32 v0, 0x4c, v0
v_and_b32_e32 v3, v2, v3
v_and_b32_e32 v0, v2, v0
buffer_store_dword v3, off, s[16:19], 0 offset:148
v_and_b32_e32 v3, v2, v4
v_add_nc_u32_e32 v4, 0x4362, v1
buffer_store_dword v3, off, s[16:19], 0 offset:152
v_and_b32_e32 v3, v2, v6
buffer_store_dword v3, off, s[16:19], 0 offset:156
v_and_b32_e32 v3, v2, v7
buffer_store_dword v3, off, s[16:19], 0 offset:160
buffer_store_dword v0, off, s[16:19], 0 offset:284
buffer_store_dword v8, off, s[16:19], 0 offset:280
v_and_b32_e32 v0, v2, v8
v_add_nc_u32_e32 v3, 0x389a, v1
buffer_store_dword v13, off, s[16:19], 0 offset:288
buffer_store_dword v0, off, s[16:19], 0 offset:164
v_add_nc_u32_e32 v0, 0x3b4c, v1
v_and_b32_e32 v2, s7, v3
v_add_nc_u32_e32 v3, 0x40b0, v1
v_and_b32_e32 v0, s7, v0
buffer_store_dword v2, off, s[16:19], 0 offset:168
v_add_nc_u32_e32 v2, 0x3dfe, v1
buffer_store_dword v0, off, s[16:19], 0 offset:172
v_and_b32_e32 v0, s7, v2
v_add_nc_u32_e32 v2, 0x48c6, v1
s_movk_i32 s7, 0x5f00
buffer_store_dword v0, off, s[16:19], 0 offset:176
v_and_b32_e32 v0, s12, v3
v_add_nc_u32_e32 v3, 0x4b78, v1
buffer_store_dword v0, off, s[16:19], 0 offset:180
v_and_b32_e32 v0, s12, v4
v_add_nc_u32_e32 v4, 0x4e2a, v1
buffer_store_dword v0, off, s[16:19], 0 offset:184
v_add_nc_u32_e32 v0, 0x4614, v1
v_and_b32_e32 v0, s12, v0
s_movk_i32 s12, 0x6f00
buffer_store_dword v0, off, s[16:19], 0 offset:188
v_and_b32_e32 v0, s7, v2
v_add_nc_u32_e32 v2, 0x6108, v1
buffer_store_dword v0, off, s[16:19], 0 offset:192
v_and_b32_e32 v0, s7, v3
v_add_nc_u32_e32 v3, 0x63ba, v1
buffer_store_dword v0, off, s[16:19], 0 offset:196
v_and_b32_e32 v0, s7, v4
v_add_nc_u32_e32 v4, 0x666c, v1
buffer_store_dword v0, off, s[16:19], 0 offset:200
v_add_nc_u32_e32 v0, 0x50dc, v1
v_and_b32_e32 v0, s7, v0
s_mul_i32 s7, s6, s13
s_mov_b32 s13, 0
buffer_store_dword v0, off, s[16:19], 0 offset:204
v_and_b32_e32 v0, s12, v2
buffer_store_dword v0, off, s[16:19], 0 offset:208
v_and_b32_e32 v0, s12, v3
buffer_store_dword v0, off, s[16:19], 0 offset:212
v_and_b32_e32 v0, s12, v4
s_mov_b32 s12, -1
buffer_store_dword v0, off, s[16:19], 0 offset:216
buffer_store_dword v44, off, s[16:19], 0 offset:220
buffer_store_dword v15, off, s[16:19], 0 offset:224
buffer_store_dword v16, off, s[16:19], 0 offset:228
buffer_store_dword v17, off, s[16:19], 0 offset:232
buffer_store_dword v18, off, s[16:19], 0 offset:236
buffer_store_dword v19, off, s[16:19], 0 offset:240
buffer_store_dword v47, off, s[16:19], 0 offset:244
buffer_store_dword v48, off, s[16:19], 0 offset:248
buffer_store_dword v49, off, s[16:19], 0 offset:252
buffer_store_dword v50, off, s[16:19], 0 offset:256
buffer_store_dword v34, off, s[16:19], 0 offset:260
buffer_store_dword v54, off, s[16:19], 0 offset:264
buffer_store_dword v51, off, s[16:19], 0 offset:268
buffer_store_dword v38, off, s[16:19], 0 offset:272
BB70_1:
s_or_b32 s14, s13, s5
v_mov_b32_e32 v0, v53
v_or_b32_e32 v2, s14, v52
v_or_b32_e32 v3, s14, v15
v_or_b32_e32 v4, s14, v88
v_or_b32_e32 v5, s14, v24
buffer_load_dword v6, off, s[16:19], 0 offset:136
v_add_nc_u32_e32 v113, v2, v55
v_or_b32_e32 v2, s14, v127
v_add_nc_u32_e32 v115, v3, v38
v_or_b32_e32 v3, s14, v22
v_add_nc_u32_e32 v119, v4, v21
buffer_load_dword v4, off, s[16:19], 0 offset:132
v_add_nc_u32_e32 v117, v2, v34
v_or_b32_e32 v2, s14, v26
v_add_nc_u32_e32 v121, v3, v23
v_or_b32_e32 v3, s14, v19
v_mov_b32_e32 v34, v55
v_add_nc_u32_e32 v123, v5, v25
v_add_nc_u32_e32 v125, v2, v27
v_or_b32_e32 v2, s14, v28
v_add_nc_u32_e32 v45, v3, v18
s_clause 0x2
buffer_load_dword v3, off, s[16:19], 0 offset:4
buffer_load_dword v5, off, s[16:19], 0 offset:208
buffer_load_dword v8, off, s[16:19], 0 offset:140
v_add_nc_u32_e32 v35, v2, v29
v_or_b32_e32 v2, s14, v31
s_clause 0x3
buffer_load_dword v7, off, s[16:19], 0 offset:212
buffer_load_dword v10, off, s[16:19], 0 offset:144
buffer_load_dword v9, off, s[16:19], 0 offset:216
buffer_load_dword v12, off, s[16:19], 0 offset:148
v_add_nc_u32_e32 v37, v2, v30
v_or_b32_e32 v2, s14, v32
s_clause 0x3
buffer_load_dword v11, off, s[16:19], 0 offset:52
buffer_load_dword v14, off, s[16:19], 0 offset:152
buffer_load_dword v13, off, s[16:19], 0 offset:56
buffer_load_dword v15, off, s[16:19], 0 offset:60
v_add_nc_u32_e32 v39, v2, v33
v_or_b32_e32 v2, s14, v73
s_clause 0x1
buffer_load_dword v18, off, s[16:19], 0 offset:160
buffer_load_dword v19, off, s[16:19], 0 offset:68
v_ashrrev_i32_e32 v114, 31, v113
v_ashrrev_i32_e32 v116, 31, v115
v_add_nc_u32_e32 v41, v2, v110
v_or_b32_e32 v2, s14, v17
buffer_load_dword v17, off, s[16:19], 0 offset:64
v_lshlrev_b64 v[113:114], 1, v[113:114]
v_ashrrev_i32_e32 v118, 31, v117
v_lshlrev_b64 v[115:116], 1, v[115:116]
v_add_nc_u32_e32 v43, v2, v16
v_or_b32_e32 v2, s14, v44
buffer_load_dword v16, off, s[16:19], 0 offset:156
v_ashrrev_i32_e32 v120, 31, v119
s_waitcnt lgkmcnt(0)
v_add_co_u32 v113, vcc_lo, s8, v113
v_lshlrev_b64 v[117:118], 1, v[117:118]
v_add_nc_u32_e32 v47, v2, v47
v_or_b32_e32 v2, s14, v48
v_ashrrev_i32_e32 v122, 31, v121
v_add_co_ci_u32_e32 v114, vcc_lo, s9, v114, vcc_lo
v_add_co_u32 v115, vcc_lo, s8, v115
v_lshlrev_b64 v[119:120], 1, v[119:120]
v_add_nc_u32_e32 v49, v2, v49
v_or_b32_e32 v2, s14, v50
v_ashrrev_i32_e32 v124, 31, v123
v_add_co_ci_u32_e32 v116, vcc_lo, s9, v116, vcc_lo
v_add_co_u32 v117, vcc_lo, s8, v117
v_lshlrev_b64 v[121:122], 1, v[121:122]
v_add_nc_u32_e32 v51, v2, v51
v_or_b32_e32 v2, s14, v54
v_ashrrev_i32_e32 v126, 31, v125
v_add_co_ci_u32_e32 v118, vcc_lo, s9, v118, vcc_lo
v_add_co_u32 v119, vcc_lo, s8, v119
v_lshlrev_b64 v[123:124], 1, v[123:124]
v_add_nc_u32_e32 v53, v2, v0
buffer_load_dword v2, off, s[16:19], 0 offset:164
v_ashrrev_i32_e32 v36, 31, v35
v_add_co_ci_u32_e32 v120, vcc_lo, s9, v120, vcc_lo
v_add_co_u32 v121, vcc_lo, s8, v121
v_lshlrev_b64 v[125:126], 1, v[125:126]
v_ashrrev_i32_e32 v38, 31, v37
v_add_co_ci_u32_e32 v122, vcc_lo, s9, v122, vcc_lo
v_add_co_u32 v123, vcc_lo, s8, v123
v_lshlrev_b64 v[35:36], 1, v[35:36]
v_ashrrev_i32_e32 v40, 31, v39
v_add_co_ci_u32_e32 v124, vcc_lo, s9, v124, vcc_lo
v_add_co_u32 v125, vcc_lo, s8, v125
v_lshlrev_b64 v[37:38], 1, v[37:38]
v_ashrrev_i32_e32 v42, 31, v41
v_add_co_ci_u32_e32 v126, vcc_lo, s9, v126, vcc_lo
v_add_co_u32 v35, vcc_lo, s8, v35
v_lshlrev_b64 v[39:40], 1, v[39:40]
v_ashrrev_i32_e32 v44, 31, v43
v_add_co_ci_u32_e32 v36, vcc_lo, s9, v36, vcc_lo
v_add_co_u32 v37, vcc_lo, s8, v37
v_lshlrev_b64 v[41:42], 1, v[41:42]
v_ashrrev_i32_e32 v46, 31, v45
v_add_co_ci_u32_e32 v38, vcc_lo, s9, v38, vcc_lo
v_add_co_u32 v39, vcc_lo, s8, v39
v_lshlrev_b64 v[43:44], 1, v[43:44]
v_ashrrev_i32_e32 v48, 31, v47
v_add_co_ci_u32_e32 v40, vcc_lo, s9, v40, vcc_lo
v_add_co_u32 v41, vcc_lo, s8, v41
v_lshlrev_b64 v[45:46], 1, v[45:46]
v_ashrrev_i32_e32 v50, 31, v49
v_add_co_ci_u32_e32 v42, vcc_lo, s9, v42, vcc_lo
v_add_co_u32 v43, vcc_lo, s8, v43
v_lshlrev_b64 v[47:48], 1, v[47:48]
v_mov_b32_e32 v20, v52
v_ashrrev_i32_e32 v52, 31, v51
v_add_co_ci_u32_e32 v44, vcc_lo, s9, v44, vcc_lo
v_add_co_u32 v45, vcc_lo, s8, v45
v_lshlrev_b64 v[49:50], 1, v[49:50]
v_ashrrev_i32_e32 v54, 31, v53
v_add_co_ci_u32_e32 v46, vcc_lo, s9, v46, vcc_lo
v_add_co_u32 v47, vcc_lo, s8, v47
v_lshlrev_b64 v[51:52], 1, v[51:52]
v_add_co_ci_u32_e32 v48, vcc_lo, s9, v48, vcc_lo
v_add_co_u32 v49, vcc_lo, s8, v49
v_lshlrev_b64 v[53:54], 1, v[53:54]
v_add_co_ci_u32_e32 v50, vcc_lo, s9, v50, vcc_lo
v_add_co_u32 v51, vcc_lo, s8, v51
v_add_co_ci_u32_e32 v52, vcc_lo, s9, v52, vcc_lo
v_add_co_u32 v53, vcc_lo, s8, v53
v_add_co_ci_u32_e32 v54, vcc_lo, s9, v54, vcc_lo
s_waitcnt vmcnt(17)
v_or_b32_e32 v6, s14, v6
s_waitcnt vmcnt(16)
v_or_b32_e32 v4, s14, v4
s_waitcnt vmcnt(14)
v_add_nc_u32_e32 v4, v4, v5
s_waitcnt vmcnt(13)
v_or_b32_e32 v8, s14, v8
s_waitcnt vmcnt(12)
v_add_nc_u32_e32 v6, v6, v7
s_waitcnt vmcnt(11)
v_or_b32_e32 v10, s14, v10
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt vmcnt(10)
v_add_nc_u32_e32 v8, v8, v9
s_waitcnt vmcnt(9)
v_or_b32_e32 v12, s14, v12
v_ashrrev_i32_e32 v7, 31, v6
s_waitcnt vmcnt(8)
v_add_nc_u32_e32 v10, v10, v11
s_waitcnt vmcnt(7)
v_or_b32_e32 v14, s14, v14
v_lshlrev_b64 v[4:5], 1, v[4:5]
v_ashrrev_i32_e32 v9, 31, v8
s_waitcnt vmcnt(6)
v_add_nc_u32_e32 v12, v12, v13
v_lshlrev_b64 v[6:7], 1, v[6:7]
v_ashrrev_i32_e32 v11, 31, v10
s_waitcnt vmcnt(5)
v_add_nc_u32_e32 v14, v14, v15
s_waitcnt vmcnt(4)
v_or_b32_e32 v18, s14, v18
v_lshlrev_b64 v[8:9], 1, v[8:9]
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[10:11], 1, v[10:11]
v_ashrrev_i32_e32 v15, 31, v14
s_waitcnt vmcnt(3)
v_add_nc_u32_e32 v18, v18, v19
v_lshlrev_b64 v[12:13], 1, v[12:13]
v_lshlrev_b64 v[14:15], 1, v[14:15]
s_waitcnt vmcnt(1)
v_or_b32_e32 v16, s14, v16
v_ashrrev_i32_e32 v19, 31, v18
v_add_nc_u32_e32 v16, v16, v17
v_lshlrev_b64 v[18:19], 1, v[18:19]
v_ashrrev_i32_e32 v17, 31, v16
v_lshlrev_b64 v[16:17], 1, v[16:17]
s_waitcnt vmcnt(0)
v_or_b32_e32 v2, s14, v2
v_add_nc_u32_e32 v55, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:8
buffer_load_dword v3, off, s[16:19], 0 offset:12
v_ashrrev_i32_e32 v56, 31, v55
v_lshlrev_b64 v[55:56], 1, v[55:56]
v_add_co_u32 v55, vcc_lo, s8, v55
v_add_co_ci_u32_e32 v56, vcc_lo, s9, v56, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v57, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:16
buffer_load_dword v3, off, s[16:19], 0 offset:20
v_ashrrev_i32_e32 v58, 31, v57
v_lshlrev_b64 v[57:58], 1, v[57:58]
v_add_co_u32 v57, vcc_lo, s8, v57
v_add_co_ci_u32_e32 v58, vcc_lo, s9, v58, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v59, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:24
buffer_load_dword v3, off, s[16:19], 0 offset:28
v_ashrrev_i32_e32 v60, 31, v59
v_lshlrev_b64 v[59:60], 1, v[59:60]
v_add_co_u32 v59, vcc_lo, s8, v59
v_add_co_ci_u32_e32 v60, vcc_lo, s9, v60, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v61, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:72
buffer_load_dword v3, off, s[16:19], 0 offset:168
v_ashrrev_i32_e32 v62, 31, v61
v_lshlrev_b64 v[61:62], 1, v[61:62]
v_add_co_u32 v61, vcc_lo, s8, v61
v_add_co_ci_u32_e32 v62, vcc_lo, s9, v62, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v63, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:76
buffer_load_dword v3, off, s[16:19], 0 offset:172
v_ashrrev_i32_e32 v64, 31, v63
v_lshlrev_b64 v[63:64], 1, v[63:64]
v_add_co_u32 v63, vcc_lo, s8, v63
v_add_co_ci_u32_e32 v64, vcc_lo, s9, v64, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v65, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:80
buffer_load_dword v3, off, s[16:19], 0 offset:176
v_ashrrev_i32_e32 v66, 31, v65
v_lshlrev_b64 v[65:66], 1, v[65:66]
v_add_co_u32 v65, vcc_lo, s8, v65
v_add_co_ci_u32_e32 v66, vcc_lo, s9, v66, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v67, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:84
buffer_load_dword v3, off, s[16:19], 0 offset:180
v_ashrrev_i32_e32 v68, 31, v67
v_lshlrev_b64 v[67:68], 1, v[67:68]
v_add_co_u32 v67, vcc_lo, s8, v67
v_add_co_ci_u32_e32 v68, vcc_lo, s9, v68, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v69, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:88
buffer_load_dword v3, off, s[16:19], 0 offset:184
v_ashrrev_i32_e32 v70, 31, v69
v_lshlrev_b64 v[69:70], 1, v[69:70]
v_add_co_u32 v69, vcc_lo, s8, v69
v_add_co_ci_u32_e32 v70, vcc_lo, s9, v70, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v71, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:92
buffer_load_dword v3, off, s[16:19], 0 offset:188
v_ashrrev_i32_e32 v72, 31, v71
v_lshlrev_b64 v[71:72], 1, v[71:72]
v_add_co_u32 v71, vcc_lo, s8, v71
v_add_co_ci_u32_e32 v72, vcc_lo, s9, v72, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v74, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:96
buffer_load_dword v3, off, s[16:19], 0 offset:192
v_ashrrev_i32_e32 v75, 31, v74
v_lshlrev_b64 v[74:75], 1, v[74:75]
v_add_co_u32 v74, vcc_lo, s8, v74
v_add_co_ci_u32_e32 v75, vcc_lo, s9, v75, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v76, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:100
buffer_load_dword v3, off, s[16:19], 0 offset:196
v_ashrrev_i32_e32 v77, 31, v76
v_lshlrev_b64 v[76:77], 1, v[76:77]
v_add_co_u32 v76, vcc_lo, s8, v76
v_add_co_ci_u32_e32 v77, vcc_lo, s9, v77, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v78, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:104
buffer_load_dword v3, off, s[16:19], 0 offset:200
v_ashrrev_i32_e32 v79, 31, v78
v_lshlrev_b64 v[78:79], 1, v[78:79]
v_add_co_u32 v78, vcc_lo, s8, v78
v_add_co_ci_u32_e32 v79, vcc_lo, s9, v79, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v80, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:108
buffer_load_dword v3, off, s[16:19], 0 offset:204
v_ashrrev_i32_e32 v81, 31, v80
v_lshlrev_b64 v[80:81], 1, v[80:81]
v_add_co_u32 v80, vcc_lo, s8, v80
v_add_co_ci_u32_e32 v81, vcc_lo, s9, v81, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v82, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:112
buffer_load_dword v3, off, s[16:19], 0 offset:32
v_ashrrev_i32_e32 v83, 31, v82
v_lshlrev_b64 v[82:83], 1, v[82:83]
v_add_co_u32 v82, vcc_lo, s8, v82
v_add_co_ci_u32_e32 v83, vcc_lo, s9, v83, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v84, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:116
buffer_load_dword v3, off, s[16:19], 0 offset:36
v_ashrrev_i32_e32 v85, 31, v84
v_lshlrev_b64 v[84:85], 1, v[84:85]
v_add_co_u32 v84, vcc_lo, s8, v84
v_add_co_ci_u32_e32 v85, vcc_lo, s9, v85, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v86, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:120
buffer_load_dword v3, off, s[16:19], 0 offset:40
v_ashrrev_i32_e32 v87, 31, v86
v_lshlrev_b64 v[86:87], 1, v[86:87]
v_add_co_u32 v86, vcc_lo, s8, v86
v_add_co_ci_u32_e32 v87, vcc_lo, s9, v87, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v105, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:124
buffer_load_dword v3, off, s[16:19], 0 offset:44
v_ashrrev_i32_e32 v106, 31, v105
v_lshlrev_b64 v[105:106], 1, v[105:106]
v_add_co_u32 v105, vcc_lo, s8, v105
v_add_co_ci_u32_e32 v106, vcc_lo, s9, v106, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v107, v2, v3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:128
buffer_load_dword v3, off, s[16:19], 0 offset:48
v_ashrrev_i32_e32 v108, 31, v107
v_lshlrev_b64 v[107:108], 1, v[107:108]
v_add_co_u32 v107, vcc_lo, s8, v107
v_add_co_ci_u32_e32 v108, vcc_lo, s9, v108, vcc_lo
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 1, v[2:3]
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
v_add_co_u32 v12, vcc_lo, s8, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
v_add_co_u32 v14, vcc_lo, s8, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s9, v15, vcc_lo
v_add_co_u32 v16, vcc_lo, s8, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s9, v17, vcc_lo
v_add_co_u32 v18, vcc_lo, s8, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s9, v19, vcc_lo
s_clause 0x2b
global_load_ushort v113, v[113:114], off
global_load_ushort v114, v[115:116], off
global_load_ushort v115, v[117:118], off
global_load_ushort v116, v[119:120], off
global_load_ushort v117, v[121:122], off
global_load_ushort v118, v[123:124], off
global_load_ushort v119, v[125:126], off
global_load_ushort v35, v[35:36], off
global_load_ushort v36, v[37:38], off
global_load_ushort v37, v[39:40], off
global_load_ushort v38, v[41:42], off
global_load_ushort v39, v[43:44], off
global_load_ushort v40, v[45:46], off
global_load_ushort v41, v[47:48], off
global_load_ushort v42, v[49:50], off
global_load_ushort v43, v[51:52], off
global_load_ushort v44, v[53:54], off
global_load_ushort v45, v[55:56], off
global_load_ushort v46, v[57:58], off
global_load_ushort v47, v[59:60], off
global_load_ushort v48, v[61:62], off
global_load_ushort v49, v[63:64], off
global_load_ushort v50, v[65:66], off
global_load_ushort v51, v[67:68], off
global_load_ushort v52, v[69:70], off
global_load_ushort v53, v[71:72], off
global_load_ushort v54, v[74:75], off
global_load_ushort v55, v[76:77], off
global_load_ushort v56, v[78:79], off
global_load_ushort v57, v[80:81], off
global_load_ushort v58, v[82:83], off
global_load_ushort v59, v[84:85], off
global_load_ushort v60, v[86:87], off
global_load_ushort v61, v[105:106], off
global_load_ushort v62, v[107:108], off
global_load_ushort v2, v[2:3], off
global_load_ushort v3, v[4:5], off
global_load_ushort v4, v[6:7], off
global_load_ushort v5, v[8:9], off
global_load_ushort v6, v[10:11], off
global_load_ushort v7, v[12:13], off
global_load_ushort v8, v[14:15], off
global_load_ushort v9, v[16:17], off
global_load_ushort v10, v[18:19], off
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
ds_write_b16 v111, v113
ds_write_b16 v111, v114 offset:690
ds_write_b16 v111, v115 offset:1380
ds_write_b16 v111, v116 offset:2070
ds_write_b16 v111, v117 offset:2760
ds_write_b16 v111, v118 offset:3450
ds_write_b16 v111, v119 offset:4140
ds_write_b16 v111, v35 offset:4830
ds_write_b16 v111, v36 offset:5520
ds_write_b16 v111, v37 offset:6210
ds_write_b16 v111, v38 offset:6900
ds_write_b16 v111, v39 offset:7590
ds_write_b16 v111, v40 offset:8280
ds_write_b16 v111, v41 offset:8970
ds_write_b16 v111, v42 offset:9660
ds_write_b16 v111, v43 offset:10350
ds_write_b16 v111, v44 offset:11040
ds_write_b16 v111, v45 offset:11730
ds_write_b16 v111, v46 offset:12420
ds_write_b16 v111, v47 offset:13110
ds_write_b16 v111, v48 offset:13800
ds_write_b16 v111, v49 offset:14490
ds_write_b16 v111, v50 offset:15180
ds_write_b16 v111, v51 offset:15870
ds_write_b16 v111, v52 offset:16560
ds_write_b16 v111, v53 offset:17250
ds_write_b16 v111, v54 offset:17940
ds_write_b16 v111, v55 offset:18630
ds_write_b16 v111, v56 offset:19320
ds_write_b16 v111, v57 offset:20010
ds_write_b16 v111, v58 offset:20700
ds_write_b16 v111, v59 offset:21390
ds_write_b16 v111, v60 offset:22080
ds_write_b16 v111, v61 offset:22770
ds_write_b16 v111, v62 offset:23460
ds_write_b16 v111, v2 offset:24150
ds_write_b16 v111, v3 offset:24840
ds_write_b16 v111, v4 offset:25530
ds_write_b16 v111, v5 offset:26220
ds_write_b16 v111, v6 offset:26910
ds_write_b16 v111, v7 offset:27600
ds_write_b16 v111, v8 offset:28290
ds_write_b16 v111, v9 offset:28980
ds_write_b16 v111, v10 offset:29670
s_and_saveexec_b32 s15, s0
s_cbranch_execz BB70_3
s_clause 0x1
buffer_load_dword v2, off, s[16:19], 0 offset:284
buffer_load_dword v3, off, s[16:19], 0 offset:276
s_waitcnt vmcnt(1)
v_or_b32_e32 v2, s14, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 1, v[2:3]
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_ushort v2, v[2:3], off
s_waitcnt vmcnt(0)
ds_write_b16 v111, v2 offset:30360
BB70_3:
s_or_b32 exec_lo, exec_lo, s15
s_clause 0x1
buffer_load_dword v46, off, s[16:19], 0 offset:224
buffer_load_dword v57, off, s[16:19], 0 offset:272
v_mov_b32_e32 v56, v34
buffer_load_dword v34, off, s[16:19], 0 offset:260
v_mov_b32_e32 v55, v20
s_or_b32 s13, s13, s7
v_or_b32_e32 v5, s13, v127
v_or_b32_e32 v7, s13, v88
v_or_b32_e32 v2, s13, v55
v_or_b32_e32 v9, s13, v22
v_or_b32_e32 v12, s13, v24
v_or_b32_e32 v14, s13, v26
v_add_nc_u32_e32 v8, v7, v21
v_add_nc_u32_e32 v2, v2, v56
v_add_nc_u32_e32 v10, v9, v23
v_add_nc_u32_e32 v12, v12, v25
v_or_b32_e32 v16, s13, v28
v_ashrrev_i32_e32 v9, 31, v8
v_add_nc_u32_e32 v14, v14, v27
v_ashrrev_i32_e32 v11, 31, v10
v_ashrrev_i32_e32 v13, 31, v12
v_add_nc_u32_e32 v16, v16, v29
v_lshlrev_b64 v[8:9], 1, v[8:9]
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[10:11], 1, v[10:11]
v_lshlrev_b64 v[12:13], 1, v[12:13]
v_ashrrev_i32_e32 v17, 31, v16
v_or_b32_e32 v35, s13, v32
v_lshlrev_b64 v[14:15], 1, v[14:15]
v_or_b32_e32 v37, s13, v73
v_or_b32_e32 v18, s13, v31
v_lshlrev_b64 v[16:17], 1, v[16:17]
v_add_nc_u32_e32 v35, v35, v33
v_add_nc_u32_e32 v18, v18, v30
v_ashrrev_i32_e32 v36, 31, v35
v_ashrrev_i32_e32 v19, 31, v18
v_lshlrev_b64 v[18:19], 1, v[18:19]
s_waitcnt vmcnt(2)
v_or_b32_e32 v3, s13, v46
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v6, v5, v34
v_add_nc_u32_e32 v4, v3, v57
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 1, v[2:3]
v_lshlrev_b64 v[6:7], 1, v[6:7]
v_lshlrev_b64 v[4:5], 1, v[4:5]
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s10, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
v_add_co_u32 v12, vcc_lo, s10, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
v_add_co_u32 v14, vcc_lo, s10, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
v_add_co_u32 v16, vcc_lo, s10, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s11, v17, vcc_lo
s_clause 0x7
global_load_ushort v38, v[2:3], off
global_load_ushort v39, v[4:5], off
global_load_ushort v40, v[6:7], off
global_load_ushort v41, v[8:9], off
global_load_ushort v42, v[10:11], off
global_load_ushort v43, v[12:13], off
global_load_ushort v44, v[14:15], off
global_load_ushort v45, v[16:17], off
v_add_nc_u32_e32 v2, v37, v110
s_clause 0x1
buffer_load_dword v37, off, s[16:19], 0 offset:232
buffer_load_dword v48, off, s[16:19], 0 offset:240
v_lshlrev_b64 v[6:7], 1, v[35:36]
s_clause 0x8
buffer_load_dword v36, off, s[16:19], 0 offset:228
buffer_load_dword v35, off, s[16:19], 0 offset:220
buffer_load_dword v47, off, s[16:19], 0 offset:236
buffer_load_dword v50, off, s[16:19], 0 offset:248
buffer_load_dword v49, off, s[16:19], 0 offset:244
buffer_load_dword v52, off, s[16:19], 0 offset:256
buffer_load_dword v51, off, s[16:19], 0 offset:252
buffer_load_dword v54, off, s[16:19], 0 offset:264
buffer_load_dword v53, off, s[16:19], 0 offset:268
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v4, vcc_lo, s10, v18
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v19, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v6
v_lshlrev_b64 v[2:3], 1, v[2:3]
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_waitcnt vmcnt(10)
v_or_b32_e32 v8, s13, v37
s_waitcnt vmcnt(9)
v_or_b32_e32 v10, s13, v48
s_waitcnt vmcnt(7)
v_or_b32_e32 v11, s13, v35
v_add_nc_u32_e32 v8, v8, v36
s_waitcnt vmcnt(6)
v_add_nc_u32_e32 v10, v10, v47
s_waitcnt vmcnt(5)
v_or_b32_e32 v14, s13, v50
s_waitcnt vmcnt(3)
v_or_b32_e32 v16, s13, v52
v_add_nc_u32_e32 v12, v11, v49
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v11, 31, v10
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v14, v14, v51
s_waitcnt vmcnt(1)
v_or_b32_e32 v18, s13, v54
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[8:9], 1, v[8:9]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v16, v16, v53
v_lshlrev_b64 v[10:11], 1, v[10:11]
v_ashrrev_i32_e32 v15, 31, v14
v_add_nc_u32_e32 v18, v18, v0
v_lshlrev_b64 v[12:13], 1, v[12:13]
v_add_co_u32 v8, vcc_lo, s10, v8
v_ashrrev_i32_e32 v17, 31, v16
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s10, v10
v_lshlrev_b64 v[14:15], 1, v[14:15]
v_ashrrev_i32_e32 v19, 31, v18
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
v_add_co_u32 v12, vcc_lo, s10, v12
v_lshlrev_b64 v[16:17], 1, v[16:17]
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
v_add_co_u32 v14, vcc_lo, s10, v14
v_lshlrev_b64 v[18:19], 1, v[18:19]
v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
v_add_co_u32 v16, vcc_lo, s10, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s11, v17, vcc_lo
v_add_co_u32 v18, vcc_lo, s10, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s11, v19, vcc_lo
s_clause 0x8
global_load_ushort v4, v[4:5], off
global_load_ushort v5, v[6:7], off
global_load_ushort v2, v[2:3], off
global_load_ushort v3, v[8:9], off
global_load_ushort v6, v[10:11], off
global_load_ushort v7, v[12:13], off
global_load_ushort v8, v[14:15], off
global_load_ushort v9, v[16:17], off
global_load_ushort v10, v[18:19], off
ds_write_b16 v1, v38
ds_write_b16 v1, v39 offset:690
ds_write_b16 v1, v40 offset:1380
ds_write_b16 v1, v41 offset:2070
ds_write_b16 v1, v42 offset:2760
ds_write_b16 v1, v43 offset:3450
ds_write_b16 v1, v44 offset:4140
ds_write_b16 v1, v45 offset:4830
s_waitcnt vmcnt(8)
ds_write_b16 v1, v4 offset:5520
s_waitcnt vmcnt(7)
ds_write_b16 v1, v5 offset:6210
s_waitcnt vmcnt(6)
ds_write_b16 v1, v2 offset:6900
s_waitcnt vmcnt(5)
ds_write_b16 v1, v3 offset:7590
s_waitcnt vmcnt(4)
ds_write_b16 v1, v6 offset:8280
s_waitcnt vmcnt(3)
ds_write_b16 v1, v7 offset:8970
s_waitcnt vmcnt(2)
ds_write_b16 v1, v8 offset:9660
s_waitcnt vmcnt(1)
ds_write_b16 v1, v9 offset:10350
s_waitcnt vmcnt(0)
ds_write_b16 v1, v10 offset:11040
s_mov_b32 s14, exec_lo
v_mov_b32_e32 v18, v47
v_mov_b32_e32 v19, v48
v_mov_b32_e32 v47, v49
v_mov_b32_e32 v49, v51
v_mov_b32_e32 v48, v50
v_mov_b32_e32 v50, v52
v_mov_b32_e32 v51, v53
v_mov_b32_e32 v15, v46
v_mov_b32_e32 v38, v57
v_mov_b32_e32 v16, v36
v_mov_b32_e32 v17, v37
v_mov_b32_e32 v44, v35
v_mov_b32_e32 v53, v0
v_mov_b32_e32 v52, v20
v_mov_b32_e32 v55, v56
s_and_b32 s15, s14, s1
s_mov_b32 exec_lo, s15
s_cbranch_execz BB70_5
s_clause 0x1
buffer_load_dword v0, off, s[16:19], 0 offset:4
buffer_load_dword v2, off, s[16:19], 0 offset:280
s_waitcnt vmcnt(0)
v_add3_u32 v2, s13, v2, v0
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 1, v[2:3]
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
global_load_ushort v2, v[2:3], off
s_waitcnt vmcnt(0)
ds_write_b16 v1, v2 offset:11730
BB70_5:
s_or_b32 exec_lo, exec_lo, s14
s_xor_b32 s12, s12, -1
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
s_barrier
BB70_6:
v_add_nc_u32_e32 v2, s13, v109
v_add_nc_u32_e32 v10, s13, v112
s_add_i32 s13, s13, 4
s_cmpk_lg_i32 s13, 0x100
ds_read2st64_b32 v[2:3], v2 offset1:23
ds_read2st64_b32 v[4:5], v10 offset1:1
ds_read2st64_b32 v[6:7], v10 offset0:2 offset1:3
ds_read2st64_b32 v[8:9], v10 offset0:4 offset1:5
ds_read2st64_b32 v[10:11], v10 offset0:6 offset1:7
s_waitcnt lgkmcnt(4)
v_lshrrev_b32_e32 v12, 16, v2
v_lshrrev_b32_e32 v13, 16, v3
s_waitcnt lgkmcnt(3)
v_lshrrev_b32_e32 v14, 16, v4
v_fmac_f16_e32 v89, v4, v2
v_fmac_f16_e32 v90, v4, v3
v_lshrrev_b32_e32 v4, 16, v5
v_fmac_f16_e32 v91, v5, v2
v_fmac_f16_e32 v92, v5, v3
s_waitcnt lgkmcnt(2)
v_lshrrev_b32_e32 v5, 16, v6
v_fmac_f16_e32 v93, v6, v2
v_fmac_f16_e32 v94, v6, v3
v_lshrrev_b32_e32 v6, 16, v7
v_fmac_f16_e32 v95, v7, v2
v_fmac_f16_e32 v96, v7, v3
s_waitcnt lgkmcnt(1)
v_lshrrev_b32_e32 v7, 16, v8
v_fmac_f16_e32 v97, v8, v2
v_fmac_f16_e32 v98, v8, v3
v_lshrrev_b32_e32 v8, 16, v9
v_fmac_f16_e32 v99, v9, v2
v_fmac_f16_e32 v100, v9, v3
s_waitcnt lgkmcnt(0)
v_lshrrev_b32_e32 v9, 16, v10
v_fmac_f16_e32 v101, v10, v2
v_fmac_f16_e32 v102, v10, v3
v_lshrrev_b32_e32 v10, 16, v11
v_fmac_f16_e32 v103, v11, v2
v_fmac_f16_e32 v104, v11, v3
v_fmac_f16_e32 v89, v14, v12
v_fmac_f16_e32 v90, v14, v13
v_fmac_f16_e32 v91, v4, v12
v_fmac_f16_e32 v92, v4, v13
v_fmac_f16_e32 v93, v5, v12
v_fmac_f16_e32 v94, v5, v13
v_fmac_f16_e32 v95, v6, v12
v_fmac_f16_e32 v96, v6, v13
v_fmac_f16_e32 v97, v7, v12
v_fmac_f16_e32 v98, v7, v13
v_fmac_f16_e32 v99, v8, v12
v_fmac_f16_e32 v100, v8, v13
v_fmac_f16_e32 v101, v9, v12
v_fmac_f16_e32 v102, v9, v13
v_fmac_f16_e32 v103, v10, v12
v_fmac_f16_e32 v104, v10, v13
s_cbranch_scc1 BB70_6
s_and_b32 vcc_lo, exec_lo, s12
s_movk_i32 s13, 0x80
s_mov_b32 s12, 0
s_cbranch_vccz BB70_1
s_clause 0x1
buffer_load_dword v0, off, s[16:19], 0 offset:288
buffer_load_dword v1, off, s[16:19], 0 offset:292
s_mul_i32 s6, s6, 46
s_mulk_i32 s4, 0x2b20
s_waitcnt vmcnt(1)
v_mul_lo_u32 v0, 0x2e0, v0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v1
v_add3_u32 v0, s6, s4, v0
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_short v[0:1], v89, off
global_store_short v[0:1], v90, off offset:46
global_store_short v[0:1], v91, off offset:184
global_store_short v[0:1], v92, off offset:230
global_store_short v[0:1], v93, off offset:368
global_store_short v[0:1], v94, off offset:414
global_store_short v[0:1], v95, off offset:552
global_store_short v[0:1], v96, off offset:598
global_store_short v[0:1], v97, off offset:736
global_store_short v[0:1], v98, off offset:782
global_store_short v[0:1], v99, off offset:920
global_store_short v[0:1], v100, off offset:966
global_store_short v[0:1], v101, off offset:1104
global_store_short v[0:1], v102, off offset:1150
global_store_short v[0:1], v103, off offset:1288
global_store_short v[0:1], v104, off offset:1334
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_dense_6_kernel0
.amdhsa_group_segment_fixed_size 42496
.amdhsa_private_segment_fixed_size 296
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 128
.amdhsa_next_free_sgpr 20
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end70:
.size tvmgen_default_fused_nn_dense_6_kernel0, .Lfunc_end70-tvmgen_default_fused_nn_dense_6_kernel0
.globl tvmgen_default_fused_nn_dense_7_kernel0
.p2align 8
.type tvmgen_default_fused_nn_dense_7_kernel0,@function
tvmgen_default_fused_nn_dense_7_kernel0:
v_lshlrev_b32_e32 v2, 4, v0
s_clause 0x2
s_load_dwordx2 s[2:3], s[4:5], 0x0
s_load_dwordx2 s[8:9], s[4:5], 0x8
s_load_dwordx2 s[0:1], s[4:5], 0x10
s_mul_i32 s4, s6, 0xc00
s_movk_i32 s10, 0x7f00
v_or_b32_e32 v18, s4, v0
v_add_nc_u32_e32 v3, 0x180, v2
v_add_nc_u32_e32 v5, 0x280, v2
v_add_nc_u32_e32 v6, 0x380, v2
s_ashr_i32 s4, s4, 31
v_add_nc_u32_e32 v7, 0x780, v2
v_and_b32_e32 v8, s10, v3
v_add_nc_u32_e32 v3, 0x480, v2
v_mov_b32_e32 v19, s4
v_and_b32_e32 v9, s10, v5
v_and_b32_e32 v10, s10, v6
v_add_nc_u32_e32 v5, 0x580, v2
v_and_b32_e32 v11, s10, v3
v_add_nc_u32_e32 v6, 0x680, v2
v_mov_b32_e32 v4, 0x7f00
v_add_nc_u32_e32 v3, 0x880, v2
v_lshlrev_b64 v[19:20], 1, v[18:19]
v_and_b32_e32 v12, s10, v5
v_and_b32_e32 v13, s10, v6
v_and_b32_e32 v14, s10, v7
v_and_b32_e32 v15, v4, v3
v_add_nc_u32_e32 v5, 0x980, v2
v_add_nc_u32_e32 v6, 0xa80, v2
v_add_nc_u32_e32 v7, 0xb80, v2
v_lshrrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v19, vcc_lo, v19, s2
v_and_b32_e32 v16, v4, v5
v_and_b32_e32 v17, v4, v6
v_add_co_ci_u32_e32 v20, vcc_lo, s3, v20, vcc_lo
v_and_b32_e32 v2, 3, v0
v_and_b32_e32 v21, v4, v7
v_mul_u32_u24_e32 v7, 48, v3
s_movk_i32 s7, 0x80
v_add_co_u32 v19, vcc_lo, 0x1600, v19
v_lshl_add_u32 v1, v0, 1, s7
v_lshlrev_b32_e32 v4, 2, v2
v_lshlrev_b32_e32 v5, 8, v3
v_lshlrev_b32_e32 v0, 3, v0
v_lshlrev_b32_e32 v6, 5, v2
v_lshl_add_u32 v7, v7, 1, s7
v_add3_u32 v8, v18, v8, 8
v_add3_u32 v9, v18, v9, 8
v_add3_u32 v10, v18, v10, 8
v_add3_u32 v11, v18, v11, 8
v_add3_u32 v12, v18, v12, 8
v_add3_u32 v13, v18, v13, 8
v_add3_u32 v14, v18, v14, 8
v_add3_u32 v15, v18, v15, 8
v_add3_u32 v16, v18, v16, 8
v_add3_u32 v17, v18, v17, 8
v_add3_u32 v18, v18, v21, 8
v_add_co_ci_u32_e32 v20, vcc_lo, 0, v20, vcc_lo
v_mov_b32_e32 v22, 0
v_mov_b32_e32 v21, 0xffff
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v24, 0
s_mov_b32 s4, 0
BB71_1:
v_add_nc_u32_e32 v27, s4, v8
v_add_nc_u32_e32 v29, s4, v9
v_add_nc_u32_e32 v31, s4, v10
v_add_co_u32 v25, vcc_lo, 0xfffff000, v19
v_add_nc_u32_e32 v35, s4, v11
v_ashrrev_i32_e32 v28, 31, v27
v_ashrrev_i32_e32 v30, 31, v29
v_ashrrev_i32_e32 v32, 31, v31
v_add_co_ci_u32_e32 v26, vcc_lo, -1, v20, vcc_lo
v_add_co_u32 v33, vcc_lo, 0xfffff800, v19
v_lshlrev_b64 v[27:28], 1, v[27:28]
v_add_nc_u32_e32 v37, s4, v12
v_lshlrev_b64 v[29:30], 1, v[29:30]
v_add_co_ci_u32_e32 v34, vcc_lo, -1, v20, vcc_lo
v_ashrrev_i32_e32 v36, 31, v35
v_add_nc_u32_e32 v39, s4, v13
v_add_co_u32 v27, vcc_lo, s2, v27
v_lshlrev_b64 v[31:32], 1, v[31:32]
v_ashrrev_i32_e32 v38, 31, v37
v_add_co_ci_u32_e32 v28, vcc_lo, s3, v28, vcc_lo
v_add_nc_u32_e32 v41, s4, v14
v_add_co_u32 v29, vcc_lo, s2, v29
s_barrier
s_clause 0xc
global_load_ushort v51, v[19:20], off offset:-2048
global_load_ushort v52, v[19:20], off offset:-1536
global_load_ushort v53, v[19:20], off offset:-1024
global_load_ushort v54, v[19:20], off offset:-512
global_load_ushort v55, v[19:20], off
global_load_ushort v57, v[25:26], off offset:-1536
global_load_ushort v58, v[25:26], off offset:-1520
global_load_ushort v59, v[25:26], off offset:-1024
global_load_ushort v60, v[25:26], off offset:-512
global_load_ushort v61, v[25:26], off
global_load_ushort v62, v[33:34], off offset:-1536
global_load_ushort v63, v[33:34], off offset:-1024
global_load_ushort v64, v[33:34], off offset:-512
v_lshlrev_b64 v[33:34], 1, v[35:36]
v_ashrrev_i32_e32 v40, 31, v39
v_add_co_ci_u32_e32 v30, vcc_lo, s3, v30, vcc_lo
v_add_nc_u32_e32 v43, s4, v15
v_add_co_u32 v31, vcc_lo, s2, v31
v_lshlrev_b64 v[35:36], 1, v[37:38]
v_ashrrev_i32_e32 v42, 31, v41
v_add_co_ci_u32_e32 v32, vcc_lo, s3, v32, vcc_lo
v_add_nc_u32_e32 v45, s4, v16
v_add_co_u32 v33, vcc_lo, s2, v33
v_lshlrev_b64 v[37:38], 1, v[39:40]
v_ashrrev_i32_e32 v44, 31, v43
v_add_co_ci_u32_e32 v34, vcc_lo, s3, v34, vcc_lo
v_add_nc_u32_e32 v47, s4, v17
v_add_co_u32 v35, vcc_lo, s2, v35
v_add_nc_u32_e32 v56, s4, v5
v_lshlrev_b64 v[39:40], 1, v[41:42]
v_ashrrev_i32_e32 v46, 31, v45
v_add_nc_u32_e32 v49, s4, v18
v_add_co_ci_u32_e32 v36, vcc_lo, s3, v36, vcc_lo
v_add_co_u32 v37, vcc_lo, s2, v37
v_lshlrev_b64 v[41:42], 1, v[43:44]
v_ashrrev_i32_e32 v48, 31, v47
v_add_co_ci_u32_e32 v38, vcc_lo, s3, v38, vcc_lo
v_or_b32_e32 v25, v56, v4
v_add_co_u32 v39, vcc_lo, s2, v39
v_lshlrev_b64 v[43:44], 1, v[45:46]
v_ashrrev_i32_e32 v50, 31, v49
v_add_co_ci_u32_e32 v40, vcc_lo, s3, v40, vcc_lo
v_add_co_u32 v41, vcc_lo, s2, v41
v_lshlrev_b64 v[45:46], 1, v[47:48]
v_ashrrev_i32_e32 v26, 31, v25
v_add_co_ci_u32_e32 v42, vcc_lo, s3, v42, vcc_lo
v_lshlrev_b64 v[47:48], 1, v[49:50]
v_add_co_u32 v43, vcc_lo, s2, v43
s_clause 0x2
global_load_ushort v49, v[27:28], off
global_load_ushort v29, v[29:30], off
global_load_ushort v30, v[31:32], off
v_add_co_ci_u32_e32 v44, vcc_lo, s3, v44, vcc_lo
v_add_co_u32 v45, vcc_lo, s2, v45
v_lshlrev_b64 v[25:26], 1, v[25:26]
v_add_co_ci_u32_e32 v46, vcc_lo, s3, v46, vcc_lo
v_add_co_u32 v47, vcc_lo, s2, v47
s_add_i32 s4, s4, 16
v_add_co_ci_u32_e32 v48, vcc_lo, s3, v48, vcc_lo
s_cmpk_eq_i32 s4, 0x100
v_add_co_u32 v25, vcc_lo, s8, v25
v_add_co_ci_u32_e32 v26, vcc_lo, s9, v26, vcc_lo
s_clause 0x7
global_load_ushort v31, v[33:34], off
global_load_ushort v32, v[35:36], off
global_load_ushort v33, v[37:38], off
global_load_ushort v34, v[39:40], off
global_load_ushort v35, v[41:42], off
global_load_ushort v36, v[43:44], off
global_load_ushort v37, v[45:46], off
global_load_ushort v38, v[47:48], off
s_clause 0x1
global_load_dwordx2 v[27:28], v[25:26], off
global_load_dwordx2 v[25:26], v[25:26], off offset:1024
v_add_co_u32 v19, vcc_lo, v19, 32
v_add_co_ci_u32_e32 v20, vcc_lo, 0, v20, vcc_lo
s_waitcnt vmcnt(25)
ds_write_b16 v1, v51 offset:224
s_waitcnt vmcnt(24)
ds_write_b16 v1, v52 offset:256
s_waitcnt vmcnt(23)
ds_write_b16 v1, v53 offset:288
s_waitcnt vmcnt(22)
ds_write_b16 v1, v54 offset:320
s_waitcnt vmcnt(21)
ds_write_b16 v1, v55 offset:352
s_waitcnt vmcnt(20)
ds_write_b16 v1, v57
s_waitcnt vmcnt(19)
ds_write_b16 v1, v58 offset:16
s_waitcnt vmcnt(18)
ds_write_b16 v1, v59 offset:32
s_waitcnt vmcnt(17)
ds_write_b16 v1, v60 offset:64
s_waitcnt vmcnt(16)
ds_write_b16 v1, v61 offset:96
s_waitcnt vmcnt(15)
ds_write_b16 v1, v62 offset:128
s_waitcnt vmcnt(14)
ds_write_b16 v1, v63 offset:160
s_waitcnt vmcnt(13)
ds_write_b16 v1, v64 offset:192
s_waitcnt vmcnt(12)
ds_write_b16 v1, v49 offset:48
s_waitcnt vmcnt(11)
ds_write_b16 v1, v29 offset:80
s_waitcnt vmcnt(10)
ds_write_b16 v1, v30 offset:112
s_waitcnt vmcnt(9)
ds_write_b16 v1, v31 offset:144
s_waitcnt vmcnt(8)
ds_write_b16 v1, v32 offset:176
s_waitcnt vmcnt(7)
ds_write_b16 v1, v33 offset:208
s_waitcnt vmcnt(6)
ds_write_b16 v1, v34 offset:240
s_waitcnt vmcnt(5)
ds_write_b16 v1, v35 offset:272
s_waitcnt vmcnt(4)
ds_write_b16 v1, v36 offset:304
s_waitcnt vmcnt(3)
ds_write_b16 v1, v37 offset:336
s_waitcnt vmcnt(2)
ds_write_b16 v1, v38 offset:368
s_waitcnt vmcnt(0)
ds_write2_b64 v0, v[27:28], v[25:26] offset1:8
s_waitcnt lgkmcnt(0)
s_barrier
ds_read_b128 v[25:28], v7
ds_read_b128 v[29:32], v7 offset:32
ds_read_b128 v[33:36], v7 offset:256
ds_read_b128 v[37:40], v7 offset:16
ds_read_b128 v[41:44], v7 offset:224
ds_read_b128 v[45:48], v7 offset:48
ds_read_b128 v[49:52], v7 offset:240
ds_read_b128 v[53:56], v7 offset:272
ds_read_b128 v[57:60], v7 offset:192
ds_read_b128 v[61:64], v7 offset:208
ds_read_b128 v[65:68], v7 offset:64
ds_read_b128 v[69:72], v7 offset:80
s_waitcnt lgkmcnt(11)
v_lshrrev_b32_e32 v73, 16, v25
s_waitcnt lgkmcnt(10)
v_and_b32_e32 v76, v21, v29
v_and_b32_e32 v77, v21, v30
v_and_b32_e32 v78, v21, v31
v_and_b32_e32 v79, v21, v32
v_lshrrev_b32_e32 v74, 16, v26
v_lshl_or_b32 v76, v25, 16, v76
v_lshl_or_b32 v77, v26, 16, v77
v_lshrrev_b32_e32 v75, 16, v27
v_lshl_or_b32 v78, v27, 16, v78
v_lshrrev_b32_e32 v80, 16, v28
v_lshl_or_b32 v79, v28, 16, v79
s_waitcnt lgkmcnt(7)
v_lshrrev_b32_e32 v85, 16, v41
v_and_b32_sdwa v28, v21, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
s_waitcnt lgkmcnt(1)
v_lshrrev_b32_e32 v93, 16, v65
v_and_b32_sdwa v26, v21, v57 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v25, 16, v66
v_and_b32_sdwa v27, v21, v58 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v85, v85, 16, v28
v_and_b32_e32 v81, v21, v33
v_lshl_or_b32 v93, v93, 16, v26
v_and_b32_e32 v89, v21, v57
v_lshl_or_b32 v97, v25, 16, v27
ds_read_b128 v[25:28], v6
v_lshl_or_b32 v41, v41, 16, v81
v_and_b32_sdwa v29, v21, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v65, v65, 16, v89
v_and_b32_e32 v90, v21, v58
v_and_b32_e32 v82, v21, v34
v_lshrrev_b32_e32 v86, 16, v42
v_lshl_or_b32 v73, v73, 16, v29
v_and_b32_sdwa v33, v21, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v30, v21, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshl_or_b32 v42, v42, 16, v82
v_lshl_or_b32 v66, v66, 16, v90
v_and_b32_e32 v83, v21, v35
v_and_b32_e32 v91, v21, v59
v_lshl_or_b32 v74, v74, 16, v30
v_lshl_or_b32 v33, v86, 16, v33
v_lshrrev_b32_e32 v87, 16, v43
v_and_b32_sdwa v34, v21, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v31, v21, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v32, v21, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v24, v76, v25, v24 op_sel_hi:[1,0,1]
v_pk_fma_f16 v23, v65, v25, v23 op_sel_hi:[1,0,1]
v_pk_fma_f16 v22, v41, v25, v22 op_sel_hi:[1,0,1]
v_and_b32_sdwa v57, v21, v59 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v82, 16, v67
v_pk_fma_f16 v24, v73, v25, v24 op_sel:[0,1,0]
v_pk_fma_f16 v23, v93, v25, v23 op_sel:[0,1,0]
v_pk_fma_f16 v22, v85, v25, v22 op_sel:[0,1,0]
v_lshl_or_b32 v43, v43, 16, v83
v_lshl_or_b32 v67, v67, 16, v91
v_pk_fma_f16 v24, v77, v26, v24 op_sel_hi:[1,0,1]
v_pk_fma_f16 v23, v66, v26, v23 op_sel_hi:[1,0,1]
v_pk_fma_f16 v22, v42, v26, v22 op_sel_hi:[1,0,1]
v_lshl_or_b32 v57, v82, 16, v57
v_and_b32_e32 v84, v21, v36
v_pk_fma_f16 v24, v74, v26, v24 op_sel:[0,1,0]
v_pk_fma_f16 v23, v97, v26, v23 op_sel:[0,1,0]
v_pk_fma_f16 v22, v33, v26, v22 op_sel:[0,1,0]
v_and_b32_e32 v92, v21, v60
v_lshl_or_b32 v75, v75, 16, v31
v_pk_fma_f16 v24, v78, v27, v24 op_sel_hi:[1,0,1]
v_pk_fma_f16 v23, v67, v27, v23 op_sel_hi:[1,0,1]
v_lshl_or_b32 v80, v80, 16, v32
v_lshl_or_b32 v34, v87, 16, v34
v_pk_fma_f16 v22, v43, v27, v22 op_sel_hi:[1,0,1]
ds_read_b128 v[29:32], v6 offset:16
v_pk_fma_f16 v24, v75, v27, v24 op_sel:[0,1,0]
v_lshrrev_b32_e32 v88, 16, v44
v_and_b32_sdwa v35, v21, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v58, v21, v60 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v83, 16, v68
v_lshl_or_b32 v44, v44, 16, v84
v_pk_fma_f16 v22, v34, v27, v22 op_sel:[0,1,0]
v_lshl_or_b32 v68, v68, 16, v92
v_pk_fma_f16 v23, v57, v27, v23 op_sel:[0,1,0]
v_and_b32_e32 v36, v21, v45
v_and_b32_e32 v81, v21, v48
v_pk_fma_f16 v24, v79, v28, v24 op_sel_hi:[1,0,1]
v_and_b32_e32 v84, v21, v61
v_and_b32_e32 v92, v21, v53
v_lshl_or_b32 v58, v83, 16, v58
v_pk_fma_f16 v23, v68, v28, v23 op_sel_hi:[1,0,1]
v_and_b32_sdwa v48, v21, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v41, 16, v40
v_lshl_or_b32 v35, v88, 16, v35
v_pk_fma_f16 v22, v44, v28, v22 op_sel_hi:[1,0,1]
v_and_b32_e32 v59, v21, v46
v_lshl_or_b32 v33, v40, 16, v81
v_lshl_or_b32 v34, v41, 16, v48
v_and_b32_sdwa v45, v21, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v61, v21, v61 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v53, v21, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v82, 16, v37
v_lshl_or_b32 v36, v37, 16, v36
v_pk_fma_f16 v24, v80, v28, v24 op_sel:[0,1,0]
v_lshrrev_b32_e32 v73, 16, v69
v_lshrrev_b32_e32 v83, 16, v49
v_pk_fma_f16 v22, v35, v28, v22 op_sel:[0,1,0]
v_lshl_or_b32 v41, v49, 16, v92
v_pk_fma_f16 v23, v58, v28, v23 op_sel:[0,1,0]
v_lshl_or_b32 v40, v69, 16, v84
v_and_b32_e32 v89, v21, v62
v_and_b32_e32 v94, v21, v54
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v24, v36, v29, v24 op_sel_hi:[1,0,1]
v_lshrrev_b32_e32 v76, 16, v38
v_lshl_or_b32 v37, v38, 16, v59
v_lshl_or_b32 v38, v82, 16, v45
v_pk_fma_f16 v23, v40, v29, v23 op_sel_hi:[1,0,1]
v_lshl_or_b32 v28, v73, 16, v61
v_lshl_or_b32 v35, v83, 16, v53
v_pk_fma_f16 v22, v41, v29, v22 op_sel_hi:[1,0,1]
v_and_b32_e32 v60, v21, v47
v_pk_fma_f16 v24, v38, v29, v24 op_sel:[0,1,0]
v_and_b32_sdwa v46, v21, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v62, v21, v62 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v54, v21, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v25, 16, v50
v_lshrrev_b32_e32 v42, 16, v70
v_pk_fma_f16 v23, v28, v29, v23 op_sel:[0,1,0]
v_lshl_or_b32 v36, v70, 16, v89
v_lshl_or_b32 v40, v50, 16, v94
v_pk_fma_f16 v22, v35, v29, v22 op_sel:[0,1,0]
v_and_b32_e32 v90, v21, v63
v_and_b32_e32 v95, v21, v55
v_lshrrev_b32_e32 v65, 16, v39
v_lshl_or_b32 v26, v39, 16, v60
v_lshl_or_b32 v39, v76, 16, v46
v_pk_fma_f16 v24, v37, v30, v24 op_sel_hi:[1,0,1]
v_lshl_or_b32 v28, v42, 16, v62
v_pk_fma_f16 v23, v36, v30, v23 op_sel_hi:[1,0,1]
v_lshl_or_b32 v25, v25, 16, v54
v_pk_fma_f16 v22, v40, v30, v22 op_sel_hi:[1,0,1]
v_pk_fma_f16 v24, v39, v30, v24 op_sel:[0,1,0]
v_and_b32_sdwa v47, v21, v47 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v63, v21, v63 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v55, v21, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v77, 16, v51
v_pk_fma_f16 v23, v28, v30, v23 op_sel:[0,1,0]
v_lshl_or_b32 v29, v71, 16, v90
v_lshrrev_b32_e32 v74, 16, v71
v_pk_fma_f16 v22, v25, v30, v22 op_sel:[0,1,0]
v_lshl_or_b32 v35, v51, 16, v95
v_and_b32_e32 v91, v21, v64
v_and_b32_e32 v96, v21, v56
v_pk_fma_f16 v24, v26, v31, v24 op_sel_hi:[1,0,1]
v_lshl_or_b32 v27, v65, 16, v47
v_pk_fma_f16 v23, v29, v31, v23 op_sel_hi:[1,0,1]
v_lshl_or_b32 v25, v74, 16, v63
v_lshl_or_b32 v28, v77, 16, v55
v_pk_fma_f16 v22, v35, v31, v22 op_sel_hi:[1,0,1]
v_pk_fma_f16 v24, v27, v31, v24 op_sel:[0,1,0]
v_and_b32_sdwa v64, v21, v64 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v56, v21, v56 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v66, 16, v52
v_lshrrev_b32_e32 v85, 16, v72
v_pk_fma_f16 v23, v25, v31, v23 op_sel:[0,1,0]
v_lshl_or_b32 v26, v72, 16, v91
v_lshl_or_b32 v29, v52, 16, v96
v_pk_fma_f16 v22, v28, v31, v22 op_sel:[0,1,0]
v_pk_fma_f16 v24, v33, v32, v24 op_sel_hi:[1,0,1]
v_lshl_or_b32 v25, v85, 16, v64
v_pk_fma_f16 v23, v26, v32, v23 op_sel_hi:[1,0,1]
v_lshl_or_b32 v27, v66, 16, v56
v_pk_fma_f16 v22, v29, v32, v22 op_sel_hi:[1,0,1]
v_pk_fma_f16 v24, v34, v32, v24 op_sel:[0,1,0]
v_pk_fma_f16 v23, v25, v32, v23 op_sel:[0,1,0]
v_pk_fma_f16 v22, v27, v32, v22 op_sel:[0,1,0]
s_cbranch_scc0 BB71_1
s_mul_i32 s6, s6, 48
v_or_b32_e32 v0, s6, v2
v_mad_u32_u24 v0, v3, 12, v0
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_short_d16_hi v[0:1], v24, off
global_store_short v[0:1], v23, off offset:48
global_store_short v[0:1], v24, off offset:8
global_store_short_d16_hi v[0:1], v22, off offset:56
global_store_short_d16_hi v[0:1], v23, off offset:16
global_store_short v[0:1], v22, off offset:64
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_dense_7_kernel0
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 98
.amdhsa_next_free_sgpr 11
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end71:
.size tvmgen_default_fused_nn_dense_7_kernel0, .Lfunc_end71-tvmgen_default_fused_nn_dense_7_kernel0
.globl tvmgen_default_fused_nn_dense_kernel0
.p2align 8
.type tvmgen_default_fused_nn_dense_kernel0,@function
tvmgen_default_fused_nn_dense_kernel0:
v_lshlrev_b32_e32 v4, 4, v0
v_lshlrev_b32_e32 v1, 5, v0
s_mov_b64 s[22:23], s[2:3]
s_mov_b64 s[20:21], s[0:1]
s_clause 0x2
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_add_u32 s20, s20, s7
s_addc_u32 s21, s21, 0
v_and_b32_e32 v5, 0x70, v4
v_and_b32_e32 v3, 0x7f00, v1
s_ashr_i32 s0, s6, 2
s_movk_i32 s7, 0x4000
s_mul_i32 s4, s0, 0x3200
buffer_store_dword v5, off, s[20:23], 0 offset:4
v_or_b32_e32 v5, 1, v4
v_add_nc_u32_e32 v3, s4, v3
v_or_b32_e32 v6, 2, v4
v_or_b32_e32 v7, 3, v4
v_lshlrev_b32_e32 v18, 1, v0
v_and_b32_e32 v5, 0x71, v5
buffer_store_dword v3, off, s[20:23], 0 offset:8
v_add_nc_u32_e32 v3, s7, v1
v_or_b32_e32 v1, 4, v4
s_movk_i32 s12, 0x7f
buffer_store_dword v5, off, s[20:23], 0 offset:12
v_and_b32_e32 v5, 0x72, v6
v_or_b32_e32 v6, 7, v4
v_and_b32_e32 v1, 0x74, v1
s_lshl_b32 s1, s6, 14
v_add_nc_u32_e32 v8, 0x60, v0
buffer_store_dword v5, off, s[20:23], 0 offset:16
v_and_b32_e32 v5, 0x73, v7
buffer_store_dword v1, off, s[20:23], 0 offset:24
v_or_b32_e32 v1, 6, v4
v_or_b32_e32 v7, 8, v4
s_and_b32 s5, s1, 0xc000
buffer_store_dword v5, off, s[20:23], 0 offset:20
v_or_b32_e32 v5, 5, v4
v_and_b32_e32 v1, 0x76, v1
s_movk_i32 s1, 0xf00
buffer_store_dword v8, off, s[20:23], 0 offset:48
v_add_nc_u32_e32 v9, 0x2bc0, v18
v_and_b32_e32 v5, 0x75, v5
buffer_store_dword v1, off, s[20:23], 0 offset:32
v_and_b32_e32 v1, 0x77, v6
v_or_b32_e32 v6, 12, v4
v_add_nc_u32_e32 v10, 0x2e40, v18
buffer_store_dword v5, off, s[20:23], 0 offset:28
v_or_b32_e32 v5, 9, v4
buffer_store_dword v1, off, s[20:23], 0 offset:36
v_and_b32_e32 v1, 0x78, v7
v_or_b32_e32 v7, 13, v4
v_and_b32_e32 v65, 0x7c, v6
v_and_b32_e32 v5, 0x79, v5
v_add_nc_u32_e32 v6, 64, v0
buffer_store_dword v1, off, s[20:23], 0 offset:40
v_or_b32_e32 v1, 10, v4
v_and_b32_e32 v16, 0x7d, v7
buffer_store_dword v5, off, s[20:23], 0 offset:44
v_or_b32_e32 v5, 11, v4
v_add_nc_u32_e32 v7, 0x780, v18
v_and_b32_e32 v59, 0x7a, v1
v_or_b32_e32 v1, 14, v4
v_or_b32_e32 v4, 15, v4
v_and_b32_e32 v127, 0x7b, v5
v_add_nc_u32_e32 v5, 0x140, v18
v_and_b32_e32 v28, s1, v7
v_and_b32_e32 v17, 0x7e, v1
v_and_b32_e32 v19, s12, v4
v_add_nc_u32_e32 v4, 32, v0
v_mov_b32_e32 v1, 0x7f
v_and_b32_e32 v21, s1, v5
v_add_nc_u32_e32 v5, 0x3c0, v18
v_add_nc_u32_e32 v7, 0xdc0, v18
v_and_b32_e32 v20, s12, v4
v_add_nc_u32_e32 v4, 0x280, v18
v_and_b32_e32 v22, v1, v6
v_add_nc_u32_e32 v6, 0x640, v18
v_and_b32_e32 v26, s1, v5
v_and_b32_e32 v25, v1, v8
v_and_b32_e32 v24, s1, v4
v_add_nc_u32_e32 v4, 0xb40, v18
v_and_b32_e32 v27, s1, v6
s_movk_i32 s1, 0x1f00
v_add_nc_u32_e32 v1, 0x8c0, v18
v_and_b32_e32 v32, s1, v7
v_and_b32_e32 v30, s1, v4
v_add_nc_u32_e32 v4, 0x1180, v18
v_mov_b32_e32 v5, 0x1f00
v_add_nc_u32_e32 v7, 0x1680, v18
v_and_b32_e32 v29, s1, v1
v_add_nc_u32_e32 v1, 0x1040, v18
v_and_b32_e32 v34, s1, v4
v_add_nc_u32_e32 v4, 0x17c0, v18
v_and_b32_e32 v37, v5, v7
v_add_nc_u32_e32 v7, 0x2940, v18
v_add_nc_u32_e32 v8, 0x2a80, v18
v_add_nc_u32_e32 v6, 0xc80, v18
v_and_b32_e32 v38, v5, v4
v_mov_b32_e32 v4, 0x3f00
v_and_b32_e32 v33, s1, v1
v_add_nc_u32_e32 v1, 0x1540, v18
v_add_nc_u32_e32 v11, 0x2f80, v18
v_and_b32_e32 v31, s1, v6
v_and_b32_e32 v41, v4, v7
v_and_b32_e32 v42, v4, v8
v_and_b32_e32 v43, v4, v9
v_and_b32_e32 v44, v4, v10
v_add_nc_u32_e32 v7, 0x30c0, v18
v_add_nc_u32_e32 v8, 0x3340, v18
v_add_nc_u32_e32 v9, 0x3480, v18
v_add_nc_u32_e32 v10, 0x35c0, v18
v_add_nc_u32_e32 v6, 0x12c0, v18
v_and_b32_e32 v36, v5, v1
v_and_b32_e32 v45, v4, v11
v_and_b32_e32 v50, v4, v7
v_and_b32_e32 v51, v4, v8
v_and_b32_e32 v52, v4, v9
v_and_b32_e32 v53, v4, v10
v_mov_b32_e32 v2, 0x7f00
v_add_nc_u32_e32 v11, 0x3840, v18
v_add_nc_u32_e32 v4, 0x3980, v18
v_add_nc_u32_e32 v7, 0x3ac0, v18
v_add_nc_u32_e32 v8, 0x3d40, v18
v_add_nc_u32_e32 v9, 0x3e80, v18
v_add_nc_u32_e32 v1, 0x1a40, v18
v_add_nc_u32_e32 v10, 0x3fc0, v18
v_and_b32_e32 v35, s1, v6
s_movk_i32 s1, 0x3f00
v_add_nc_u32_e32 v5, 0x1f40, v18
v_and_b32_e32 v39, s1, v1
v_add_nc_u32_e32 v1, 0x1cc0, v18
v_and_b32_e32 v55, v2, v4
v_and_b32_e32 v54, v2, v11
v_and_b32_e32 v56, v2, v7
v_and_b32_e32 v57, v2, v8
v_and_b32_e32 v58, v2, v9
v_and_b32_e32 v2, v2, v10
v_add_nc_u32_e32 v6, 0x1b80, v18
v_and_b32_e32 v60, s1, v1
v_and_b32_e32 v61, s1, v5
v_lshrrev_b32_e32 v5, 5, v0
buffer_store_dword v2, off, s[20:23], 0 offset:52
v_add_nc_u32_e32 v2, 0x21c0, v18
v_add_nc_u32_e32 v1, 0x2440, v18
v_add_nc_u32_e32 v4, 0x2580, v18
s_movk_i32 s13, 0x2f00
v_and_b32_e32 v40, s1, v6
v_add_nc_u32_e32 v6, 0x2080, v18
v_and_b32_e32 v67, s13, v2
v_and_b32_e32 v69, s13, v1
v_and_b32_e32 v71, s13, v4
v_add_nc_u32_e32 v1, 0x26c0, v18
v_lshlrev_b32_e32 v2, 9, v0
v_mul_u32_u24_e32 v4, 0x500, v5
v_and_b32_e32 v72, s12, v0
v_cmp_gt_i32_e64 s0, 0x50, v0
v_cmp_gt_i32_e64 s1, 32, v0
v_and_b32_e32 v64, s13, v6
v_and_b32_e32 v73, s13, v1
v_and_b32_e32 v74, 0x3e00, v2
v_lshl_add_u32 v75, v4, 1, s7
v_and_b32_e32 v76, 0x700, v18
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v46, 0
v_mov_b32_e32 v47, 0
v_mov_b32_e32 v48, 0
v_mov_b32_e32 v49, 0
v_mov_b32_e32 v62, 0
v_mov_b32_e32 v63, 0
v_mov_b32_e32 v66, 0
v_mov_b32_e32 v70, 0
v_mov_b32_e32 v68, 0
s_mov_b32 s15, 0
s_mov_b32 s14, -1
s_movk_i32 s12, 0x2800
s_movk_i32 s13, 0x5000
buffer_store_dword v5, off, s[20:23], 0 offset:56
BB72_1:
s_clause 0x1
buffer_load_dword v1, off, s[20:23], 0 offset:8
buffer_load_dword v2, off, s[20:23], 0 offset:4
s_waitcnt vmcnt(1)
v_or_b32_e32 v1, s15, v1
s_waitcnt vmcnt(0)
v_or_b32_e32 v77, v1, v2
buffer_load_dword v2, off, s[20:23], 0 offset:16
v_or_b32_e32 v93, v1, v65
v_or_b32_e32 v95, v1, v17
v_ashrrev_i32_e32 v78, 31, v77
v_ashrrev_i32_e32 v94, 31, v93
v_ashrrev_i32_e32 v96, 31, v95
v_lshlrev_b64 v[77:78], 1, v[77:78]
v_lshlrev_b64 v[93:94], 1, v[93:94]
v_lshlrev_b64 v[95:96], 1, v[95:96]
s_waitcnt vmcnt(0)
v_or_b32_e32 v79, v1, v2
buffer_load_dword v2, off, s[20:23], 0 offset:24
v_ashrrev_i32_e32 v80, 31, v79
v_lshlrev_b64 v[86:87], 1, v[79:80]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v79, vcc_lo, s8, v77
v_add_co_ci_u32_e32 v80, vcc_lo, s9, v78, vcc_lo
v_add_co_u32 v77, vcc_lo, s8, v86
v_add_co_ci_u32_e32 v78, vcc_lo, s9, v87, vcc_lo
v_or_b32_e32 v87, v1, v59
v_ashrrev_i32_e32 v88, 31, v87
s_waitcnt vmcnt(0)
v_or_b32_e32 v81, v1, v2
buffer_load_dword v2, off, s[20:23], 0 offset:32
v_ashrrev_i32_e32 v82, 31, v81
v_lshlrev_b64 v[81:82], 1, v[81:82]
v_add_co_u32 v91, vcc_lo, s8, v81
v_add_co_ci_u32_e32 v92, vcc_lo, s9, v82, vcc_lo
s_waitcnt vmcnt(0)
v_or_b32_e32 v83, v1, v2
buffer_load_dword v2, off, s[20:23], 0 offset:40
v_ashrrev_i32_e32 v84, 31, v83
v_lshlrev_b64 v[83:84], 1, v[83:84]
v_add_co_u32 v89, vcc_lo, s8, v83
v_add_co_ci_u32_e32 v90, vcc_lo, s9, v84, vcc_lo
v_lshlrev_b64 v[83:84], 1, v[87:88]
s_waitcnt vmcnt(0)
v_or_b32_e32 v85, v1, v2
v_ashrrev_i32_e32 v86, 31, v85
v_lshlrev_b64 v[81:82], 1, v[85:86]
v_add_co_u32 v87, vcc_lo, s8, v81
v_add_co_ci_u32_e32 v88, vcc_lo, s9, v82, vcc_lo
v_add_co_u32 v85, vcc_lo, s8, v83
v_add_co_ci_u32_e32 v86, vcc_lo, s9, v84, vcc_lo
v_add_co_u32 v83, vcc_lo, s8, v93
v_add_co_ci_u32_e32 v84, vcc_lo, s9, v94, vcc_lo
v_add_co_u32 v81, vcc_lo, s8, v95
v_add_co_ci_u32_e32 v82, vcc_lo, s9, v96, vcc_lo
v_add_co_u32 v93, vcc_lo, s12, v79
s_clause 0x7
global_load_ushort v109, v[79:80], off
global_load_ushort v110, v[77:78], off
global_load_ushort v111, v[91:92], off
global_load_ushort v112, v[89:90], off
global_load_ushort v113, v[87:88], off
global_load_ushort v114, v[85:86], off
global_load_ushort v115, v[83:84], off
global_load_ushort v116, v[81:82], off
v_add_co_ci_u32_e32 v94, vcc_lo, 0, v80, vcc_lo
v_add_co_u32 v95, vcc_lo, s12, v77
v_add_co_ci_u32_e32 v96, vcc_lo, 0, v78, vcc_lo
v_add_co_u32 v97, vcc_lo, s12, v91
v_add_co_ci_u32_e32 v98, vcc_lo, 0, v92, vcc_lo
v_add_co_u32 v99, vcc_lo, s12, v89
v_add_co_ci_u32_e32 v100, vcc_lo, 0, v90, vcc_lo
v_add_co_u32 v101, vcc_lo, s12, v87
v_add_co_ci_u32_e32 v102, vcc_lo, 0, v88, vcc_lo
v_add_co_u32 v103, vcc_lo, s12, v85
v_add_co_ci_u32_e32 v104, vcc_lo, 0, v86, vcc_lo
v_add_co_u32 v105, vcc_lo, s12, v83
v_add_co_ci_u32_e32 v106, vcc_lo, 0, v84, vcc_lo
v_add_co_u32 v107, vcc_lo, s12, v81
v_add_co_ci_u32_e32 v108, vcc_lo, 0, v82, vcc_lo
s_clause 0x7
global_load_ushort v117, v[93:94], off
global_load_ushort v118, v[95:96], off
global_load_ushort v119, v[97:98], off
global_load_ushort v120, v[99:100], off
global_load_ushort v121, v[101:102], off
global_load_ushort v122, v[103:104], off
global_load_ushort v123, v[105:106], off
global_load_ushort v124, v[107:108], off
buffer_load_dword v2, off, s[20:23], 0 offset:12
v_or_b32_e32 v103, v1, v127
v_or_b32_e32 v105, v1, v16
v_or_b32_e32 v107, v1, v19
v_ashrrev_i32_e32 v104, 31, v103
v_ashrrev_i32_e32 v106, 31, v105
v_ashrrev_i32_e32 v108, 31, v107
v_lshlrev_b64 v[103:104], 1, v[103:104]
v_lshlrev_b64 v[105:106], 1, v[105:106]
v_lshlrev_b64 v[107:108], 1, v[107:108]
s_waitcnt vmcnt(0)
v_or_b32_e32 v93, v1, v2
buffer_load_dword v2, off, s[20:23], 0 offset:20
v_ashrrev_i32_e32 v94, 31, v93
v_lshlrev_b64 v[93:94], 1, v[93:94]
v_add_co_u32 v93, vcc_lo, s8, v93
v_add_co_ci_u32_e32 v94, vcc_lo, s9, v94, vcc_lo
s_waitcnt vmcnt(0)
v_or_b32_e32 v95, v1, v2
buffer_load_dword v2, off, s[20:23], 0 offset:28
v_ashrrev_i32_e32 v96, 31, v95
v_lshlrev_b64 v[95:96], 1, v[95:96]
v_add_co_u32 v95, vcc_lo, s8, v95
v_add_co_ci_u32_e32 v96, vcc_lo, s9, v96, vcc_lo
s_waitcnt vmcnt(0)
v_or_b32_e32 v97, v1, v2
buffer_load_dword v2, off, s[20:23], 0 offset:36
v_ashrrev_i32_e32 v98, 31, v97
v_lshlrev_b64 v[97:98], 1, v[97:98]
v_add_co_u32 v97, vcc_lo, s8, v97
v_add_co_ci_u32_e32 v98, vcc_lo, s9, v98, vcc_lo
s_waitcnt vmcnt(0)
v_or_b32_e32 v99, v1, v2
buffer_load_dword v2, off, s[20:23], 0 offset:44
v_ashrrev_i32_e32 v100, 31, v99
v_lshlrev_b64 v[99:100], 1, v[99:100]
v_add_co_u32 v99, vcc_lo, s8, v99
v_add_co_ci_u32_e32 v100, vcc_lo, s9, v100, vcc_lo
s_waitcnt vmcnt(0)
v_or_b32_e32 v101, v1, v2
v_ashrrev_i32_e32 v102, 31, v101
v_lshlrev_b64 v[101:102], 1, v[101:102]
v_add_co_u32 v101, vcc_lo, s8, v101
v_add_co_ci_u32_e32 v102, vcc_lo, s9, v102, vcc_lo
v_add_co_u32 v103, vcc_lo, s8, v103
v_add_co_ci_u32_e32 v104, vcc_lo, s9, v104, vcc_lo
v_add_co_u32 v105, vcc_lo, s8, v105
v_add_co_ci_u32_e32 v106, vcc_lo, s9, v106, vcc_lo
v_add_co_u32 v107, vcc_lo, s8, v107
v_add_co_ci_u32_e32 v108, vcc_lo, s9, v108, vcc_lo
v_add_co_u32 v125, vcc_lo, s12, v93
v_add_co_ci_u32_e32 v126, vcc_lo, 0, v94, vcc_lo
v_add_co_u32 v1, vcc_lo, s12, v95
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v96, vcc_lo
v_add_co_u32 v4, vcc_lo, s12, v97
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v98, vcc_lo
v_add_co_u32 v6, vcc_lo, s12, v99
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v100, vcc_lo
v_add_co_u32 v8, vcc_lo, s12, v101
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v102, vcc_lo
v_add_co_u32 v10, vcc_lo, s12, v103
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v104, vcc_lo
v_add_co_u32 v12, vcc_lo, s12, v105
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v106, vcc_lo
v_add_co_u32 v14, vcc_lo, s12, v107
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v108, vcc_lo
s_clause 0xf
global_load_short_d16_hi v109, v[93:94], off
global_load_short_d16_hi v110, v[95:96], off
global_load_short_d16_hi v111, v[97:98], off
global_load_short_d16_hi v112, v[99:100], off
global_load_short_d16_hi v113, v[101:102], off
global_load_short_d16_hi v114, v[103:104], off
global_load_short_d16_hi v115, v[105:106], off
global_load_short_d16_hi v116, v[107:108], off
global_load_short_d16_hi v117, v[125:126], off
global_load_short_d16_hi v118, v[1:2], off
global_load_short_d16_hi v119, v[4:5], off
global_load_short_d16_hi v120, v[6:7], off
global_load_short_d16_hi v121, v[8:9], off
global_load_short_d16_hi v122, v[10:11], off
global_load_short_d16_hi v123, v[12:13], off
global_load_short_d16_hi v124, v[14:15], off
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
ds_write_b128 v3, v[109:112]
ds_write_b128 v3, v[113:116] offset:16
ds_write_b128 v3, v[117:120] offset:5120
ds_write_b128 v3, v[121:124] offset:5136
s_and_saveexec_b32 s16, s0
s_cbranch_execz BB72_3
v_add_co_u32 v1, vcc_lo, s13, v79
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v80, vcc_lo
v_add_co_u32 v4, vcc_lo, s13, v77
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v78, vcc_lo
v_add_co_u32 v6, vcc_lo, s13, v91
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v92, vcc_lo
v_add_co_u32 v8, vcc_lo, s13, v89
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v90, vcc_lo
v_add_co_u32 v10, vcc_lo, s13, v87
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v88, vcc_lo
v_add_co_u32 v12, vcc_lo, s13, v85
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v86, vcc_lo
v_add_co_u32 v14, vcc_lo, s13, v83
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v84, vcc_lo
v_add_co_u32 v84, vcc_lo, s13, v81
v_add_co_ci_u32_e32 v85, vcc_lo, 0, v82, vcc_lo
s_clause 0x7
global_load_ushort v77, v[1:2], off
global_load_ushort v78, v[4:5], off
global_load_ushort v79, v[6:7], off
global_load_ushort v80, v[8:9], off
global_load_ushort v81, v[10:11], off
global_load_ushort v82, v[12:13], off
global_load_ushort v83, v[14:15], off
global_load_ushort v84, v[84:85], off
v_add_co_u32 v1, vcc_lo, s13, v93
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v94, vcc_lo
v_add_co_u32 v4, vcc_lo, s13, v95
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v96, vcc_lo
v_add_co_u32 v6, vcc_lo, s13, v97
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v98, vcc_lo
v_add_co_u32 v8, vcc_lo, s13, v99
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v100, vcc_lo
v_add_co_u32 v10, vcc_lo, s13, v101
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v102, vcc_lo
v_add_co_u32 v12, vcc_lo, s13, v103
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v104, vcc_lo
v_add_co_u32 v14, vcc_lo, s13, v105
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v106, vcc_lo
v_add_co_u32 v85, vcc_lo, s13, v107
v_add_co_ci_u32_e32 v86, vcc_lo, 0, v108, vcc_lo
s_waitcnt vmcnt(7)
global_load_short_d16_hi v77, v[1:2], off
s_waitcnt vmcnt(7)
global_load_short_d16_hi v78, v[4:5], off
s_waitcnt vmcnt(7)
global_load_short_d16_hi v79, v[6:7], off
s_waitcnt vmcnt(7)
global_load_short_d16_hi v80, v[8:9], off
s_waitcnt vmcnt(7)
global_load_short_d16_hi v81, v[10:11], off
s_waitcnt vmcnt(7)
global_load_short_d16_hi v82, v[12:13], off
s_waitcnt vmcnt(7)
global_load_short_d16_hi v83, v[14:15], off
s_waitcnt vmcnt(7)
global_load_short_d16_hi v84, v[85:86], off
s_waitcnt vmcnt(4)
ds_write_b128 v3, v[77:80] offset:10240
s_waitcnt vmcnt(0)
ds_write_b128 v3, v[81:84] offset:10256
BB72_3:
s_or_b32 exec_lo, exec_lo, s16
s_or_b32 s15, s15, s5
v_or_b32_e32 v1, s15, v72
v_or_b32_e32 v85, s15, v20
v_or_b32_e32 v86, s15, v22
v_or_b32_e32 v87, s15, v25
v_add_nc_u32_e32 v1, v1, v76
v_add_nc_u32_e32 v4, v85, v21
v_add_nc_u32_e32 v6, v86, v24
v_add_nc_u32_e32 v8, v87, v26
v_add_nc_u32_e32 v10, v85, v27
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v9, 31, v8
v_add_nc_u32_e32 v12, v86, v28
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_lshlrev_b64 v[4:5], 1, v[4:5]
v_lshlrev_b64 v[6:7], 1, v[6:7]
v_lshlrev_b64 v[8:9], 1, v[8:9]
v_ashrrev_i32_e32 v11, 31, v10
v_add_nc_u32_e32 v14, v87, v29
v_add_co_u32 v1, vcc_lo, s10, v1
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v4
v_lshlrev_b64 v[10:11], 1, v[10:11]
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v6
v_ashrrev_i32_e32 v15, 31, v14
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s10, v8
v_lshlrev_b64 v[12:13], 1, v[12:13]
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
v_add_co_u32 v77, vcc_lo, 0x800, v1
v_lshlrev_b64 v[14:15], 1, v[14:15]
v_add_co_ci_u32_e32 v78, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v10, vcc_lo, s10, v10
v_add_nc_u32_e32 v79, v85, v30
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
v_add_co_u32 v12, vcc_lo, s10, v12
v_add_nc_u32_e32 v81, v86, v31
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
v_add_co_u32 v14, vcc_lo, s10, v14
v_ashrrev_i32_e32 v80, 31, v79
v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
s_clause 0x7
global_load_ushort v88, v[1:2], off
global_load_ushort v89, v[4:5], off
global_load_ushort v90, v[6:7], off
global_load_ushort v91, v[8:9], off
global_load_ushort v92, v[77:78], off offset:512
global_load_ushort v93, v[10:11], off
global_load_ushort v94, v[12:13], off
global_load_ushort v95, v[14:15], off
v_add_nc_u32_e32 v6, v87, v32
v_ashrrev_i32_e32 v82, 31, v81
v_lshlrev_b64 v[4:5], 1, v[79:80]
v_add_nc_u32_e32 v12, v85, v33
v_add_co_u32 v8, vcc_lo, 0x1000, v1
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[10:11], 1, v[81:82]
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v2, vcc_lo
v_add_nc_u32_e32 v14, v86, v34
v_add_co_u32 v4, vcc_lo, s10, v4
v_lshlrev_b64 v[6:7], 1, v[6:7]
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
v_add_nc_u32_e32 v77, v87, v35
v_add_co_u32 v10, vcc_lo, s10, v10
v_ashrrev_i32_e32 v15, 31, v14
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v6
v_lshlrev_b64 v[12:13], 1, v[12:13]
v_ashrrev_i32_e32 v78, 31, v77
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
v_add_co_u32 v79, vcc_lo, 0x1800, v1
v_lshlrev_b64 v[14:15], 1, v[14:15]
v_add_co_ci_u32_e32 v80, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v12, vcc_lo, s10, v12
v_lshlrev_b64 v[77:78], 1, v[77:78]
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
v_add_nc_u32_e32 v81, v85, v36
v_add_co_u32 v14, vcc_lo, s10, v14
v_add_nc_u32_e32 v83, v86, v37
v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
v_add_co_u32 v77, vcc_lo, s10, v77
v_ashrrev_i32_e32 v82, 31, v81
v_add_co_ci_u32_e32 v78, vcc_lo, s11, v78, vcc_lo
s_clause 0x7
global_load_ushort v96, v[8:9], off offset:1024
global_load_ushort v97, v[4:5], off
global_load_ushort v98, v[10:11], off
global_load_ushort v99, v[6:7], off
global_load_ushort v100, v[79:80], off offset:1536
global_load_ushort v101, v[12:13], off
global_load_ushort v102, v[14:15], off
global_load_ushort v103, v[77:78], off
v_add_nc_u32_e32 v6, v87, v38
v_ashrrev_i32_e32 v84, 31, v83
v_lshlrev_b64 v[4:5], 1, v[81:82]
v_add_nc_u32_e32 v12, v85, v39
v_add_co_u32 v8, vcc_lo, s12, v1
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[10:11], 1, v[83:84]
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v2, vcc_lo
v_add_nc_u32_e32 v14, v86, v40
v_add_co_u32 v4, vcc_lo, s10, v4
v_lshlrev_b64 v[6:7], 1, v[6:7]
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
v_add_nc_u32_e32 v77, v87, v60
v_add_co_u32 v10, vcc_lo, s10, v10
v_ashrrev_i32_e32 v15, 31, v14
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v6
v_lshlrev_b64 v[12:13], 1, v[12:13]
v_ashrrev_i32_e32 v78, 31, v77
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
v_add_co_u32 v79, vcc_lo, 0x3000, v1
v_lshlrev_b64 v[14:15], 1, v[14:15]
v_add_co_ci_u32_e32 v80, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v12, vcc_lo, s10, v12
v_lshlrev_b64 v[77:78], 1, v[77:78]
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
v_add_nc_u32_e32 v81, v85, v61
v_add_co_u32 v14, vcc_lo, s10, v14
v_add_nc_u32_e32 v83, v86, v64
v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
v_add_co_u32 v77, vcc_lo, s10, v77
v_ashrrev_i32_e32 v82, 31, v81
v_add_co_ci_u32_e32 v78, vcc_lo, s11, v78, vcc_lo
s_clause 0x7
global_load_ushort v104, v[8:9], off
global_load_ushort v105, v[4:5], off
global_load_ushort v106, v[10:11], off
global_load_ushort v107, v[6:7], off
global_load_ushort v108, v[79:80], off offset:512
global_load_ushort v109, v[12:13], off
global_load_ushort v110, v[14:15], off
global_load_ushort v111, v[77:78], off
v_add_nc_u32_e32 v6, v87, v67
v_ashrrev_i32_e32 v84, 31, v83
v_lshlrev_b64 v[4:5], 1, v[81:82]
v_add_nc_u32_e32 v12, v85, v69
v_add_co_u32 v8, vcc_lo, 0x3800, v1
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[10:11], 1, v[83:84]
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v2, vcc_lo
v_add_nc_u32_e32 v14, v86, v71
v_add_co_u32 v4, vcc_lo, s10, v4
v_lshlrev_b64 v[6:7], 1, v[6:7]
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
v_add_nc_u32_e32 v77, v87, v73
v_add_co_u32 v10, vcc_lo, s10, v10
v_ashrrev_i32_e32 v15, 31, v14
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v6
v_lshlrev_b64 v[12:13], 1, v[12:13]
v_ashrrev_i32_e32 v78, 31, v77
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
v_add_co_u32 v79, vcc_lo, s7, v1
v_lshlrev_b64 v[14:15], 1, v[14:15]
v_add_co_ci_u32_e32 v80, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v12, vcc_lo, s10, v12
v_lshlrev_b64 v[77:78], 1, v[77:78]
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
v_add_nc_u32_e32 v81, v85, v41
v_add_co_u32 v14, vcc_lo, s10, v14
v_add_nc_u32_e32 v83, v86, v42
v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
v_add_co_u32 v77, vcc_lo, s10, v77
v_ashrrev_i32_e32 v82, 31, v81
v_add_co_ci_u32_e32 v78, vcc_lo, s11, v78, vcc_lo
s_clause 0x7
global_load_ushort v112, v[8:9], off offset:1024
global_load_ushort v113, v[4:5], off
global_load_ushort v114, v[10:11], off
global_load_ushort v115, v[6:7], off
global_load_ushort v116, v[79:80], off offset:1536
global_load_ushort v117, v[12:13], off
global_load_ushort v118, v[14:15], off
global_load_ushort v119, v[77:78], off
v_add_nc_u32_e32 v6, v87, v43
v_ashrrev_i32_e32 v84, 31, v83
v_lshlrev_b64 v[4:5], 1, v[81:82]
v_add_nc_u32_e32 v12, v85, v44
v_add_co_u32 v8, vcc_lo, s13, v1
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[10:11], 1, v[83:84]
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v2, vcc_lo
v_add_nc_u32_e32 v14, v86, v45
v_add_co_u32 v4, vcc_lo, s10, v4
v_lshlrev_b64 v[6:7], 1, v[6:7]
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
v_add_nc_u32_e32 v77, v87, v50
v_add_co_u32 v10, vcc_lo, s10, v10
v_ashrrev_i32_e32 v15, 31, v14
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v6
v_lshlrev_b64 v[12:13], 1, v[12:13]
v_ashrrev_i32_e32 v78, 31, v77
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
v_add_co_u32 v79, vcc_lo, 0x5800, v1
v_lshlrev_b64 v[14:15], 1, v[14:15]
v_add_co_ci_u32_e32 v80, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v12, vcc_lo, s10, v12
v_lshlrev_b64 v[77:78], 1, v[77:78]
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
v_add_nc_u32_e32 v81, v85, v51
v_add_co_u32 v14, vcc_lo, s10, v14
v_add_nc_u32_e32 v83, v86, v52
v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
v_add_co_u32 v77, vcc_lo, s10, v77
v_ashrrev_i32_e32 v82, 31, v81
v_add_co_ci_u32_e32 v78, vcc_lo, s11, v78, vcc_lo
s_clause 0x7
global_load_ushort v120, v[8:9], off
global_load_ushort v121, v[4:5], off
global_load_ushort v122, v[10:11], off
global_load_ushort v123, v[6:7], off
global_load_ushort v124, v[79:80], off offset:512
global_load_ushort v125, v[12:13], off
global_load_ushort v126, v[14:15], off
global_load_ushort v23, v[77:78], off
v_add_nc_u32_e32 v6, v87, v53
v_ashrrev_i32_e32 v84, 31, v83
v_lshlrev_b64 v[4:5], 1, v[81:82]
v_add_nc_u32_e32 v12, v85, v54
v_add_co_u32 v8, vcc_lo, 0x6000, v1
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[10:11], 1, v[83:84]
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v2, vcc_lo
v_add_nc_u32_e32 v14, v86, v55
v_add_co_u32 v4, vcc_lo, s10, v4
v_lshlrev_b64 v[6:7], 1, v[6:7]
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
v_add_nc_u32_e32 v77, v87, v56
v_add_co_u32 v10, vcc_lo, s10, v10
v_ashrrev_i32_e32 v15, 31, v14
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v6
v_lshlrev_b64 v[12:13], 1, v[12:13]
v_ashrrev_i32_e32 v78, 31, v77
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
v_add_nc_u32_e32 v81, v85, v57
v_add_co_u32 v79, vcc_lo, 0x6800, v1
v_lshlrev_b64 v[14:15], 1, v[14:15]
v_add_co_ci_u32_e32 v80, vcc_lo, 0, v2, vcc_lo
v_add_nc_u32_e32 v83, v86, v58
v_add_co_u32 v12, vcc_lo, s10, v12
v_lshlrev_b64 v[77:78], 1, v[77:78]
v_ashrrev_i32_e32 v82, 31, v81
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
v_add_co_u32 v14, vcc_lo, s10, v14
v_ashrrev_i32_e32 v84, 31, v83
v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
v_add_co_u32 v77, vcc_lo, s10, v77
v_lshlrev_b64 v[81:82], 1, v[81:82]
v_add_co_ci_u32_e32 v78, vcc_lo, s11, v78, vcc_lo
v_add_co_u32 v1, vcc_lo, 0x7800, v1
v_lshlrev_b64 v[83:84], 1, v[83:84]
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v81, vcc_lo, s10, v81
v_add_co_ci_u32_e32 v82, vcc_lo, s11, v82, vcc_lo
v_add_co_u32 v83, vcc_lo, s10, v83
v_add_co_ci_u32_e32 v84, vcc_lo, s11, v84, vcc_lo
s_clause 0xa
global_load_ushort v8, v[8:9], off offset:1024
global_load_ushort v4, v[4:5], off
global_load_ushort v5, v[10:11], off
global_load_ushort v6, v[6:7], off
global_load_ushort v7, v[79:80], off offset:1536
global_load_ushort v9, v[12:13], off
global_load_ushort v10, v[14:15], off
global_load_ushort v11, v[77:78], off
global_load_ushort v1, v[1:2], off
global_load_ushort v2, v[81:82], off
global_load_ushort v12, v[83:84], off
s_waitcnt vmcnt(50)
ds_write_b16 v18, v88
s_waitcnt vmcnt(49)
ds_write_b16 v18, v89 offset:320
s_waitcnt vmcnt(48)
ds_write_b16 v18, v90 offset:640
s_waitcnt vmcnt(47)
ds_write_b16 v18, v91 offset:960
s_waitcnt vmcnt(46)
ds_write_b16 v18, v92 offset:1280
s_waitcnt vmcnt(45)
ds_write_b16 v18, v93 offset:1600
s_waitcnt vmcnt(44)
ds_write_b16 v18, v94 offset:1920
s_waitcnt vmcnt(43)
ds_write_b16 v18, v95 offset:2240
s_waitcnt vmcnt(42)
ds_write_b16 v18, v96 offset:2560
s_waitcnt vmcnt(41)
ds_write_b16 v18, v97 offset:2880
s_waitcnt vmcnt(40)
ds_write_b16 v18, v98 offset:3200
s_waitcnt vmcnt(39)
ds_write_b16 v18, v99 offset:3520
s_waitcnt vmcnt(38)
ds_write_b16 v18, v100 offset:3840
s_waitcnt vmcnt(37)
ds_write_b16 v18, v101 offset:4160
s_waitcnt vmcnt(36)
ds_write_b16 v18, v102 offset:4480
s_waitcnt vmcnt(35)
ds_write_b16 v18, v103 offset:4800
s_waitcnt vmcnt(34)
ds_write_b16 v18, v104 offset:5120
s_waitcnt vmcnt(33)
ds_write_b16 v18, v105 offset:5440
s_waitcnt vmcnt(32)
ds_write_b16 v18, v106 offset:5760
s_waitcnt vmcnt(31)
ds_write_b16 v18, v107 offset:6080
s_waitcnt vmcnt(30)
ds_write_b16 v18, v108 offset:6400
s_waitcnt vmcnt(29)
ds_write_b16 v18, v109 offset:6720
s_waitcnt vmcnt(28)
ds_write_b16 v18, v110 offset:7040
s_waitcnt vmcnt(27)
ds_write_b16 v18, v111 offset:7360
s_waitcnt vmcnt(26)
ds_write_b16 v18, v112 offset:7680
s_waitcnt vmcnt(25)
ds_write_b16 v18, v113 offset:8000
s_waitcnt vmcnt(24)
ds_write_b16 v18, v114 offset:8320
s_waitcnt vmcnt(23)
ds_write_b16 v18, v115 offset:8640
s_waitcnt vmcnt(22)
ds_write_b16 v18, v116 offset:8960
s_waitcnt vmcnt(21)
ds_write_b16 v18, v117 offset:9280
s_waitcnt vmcnt(20)
ds_write_b16 v18, v118 offset:9600
s_waitcnt vmcnt(19)
ds_write_b16 v18, v119 offset:9920
s_waitcnt vmcnt(18)
ds_write_b16 v18, v120 offset:10240
s_waitcnt vmcnt(17)
ds_write_b16 v18, v121 offset:10560
s_waitcnt vmcnt(16)
ds_write_b16 v18, v122 offset:10880
s_waitcnt vmcnt(15)
ds_write_b16 v18, v123 offset:11200
s_waitcnt vmcnt(14)
ds_write_b16 v18, v124 offset:11520
s_waitcnt vmcnt(13)
ds_write_b16 v18, v125 offset:11840
s_waitcnt vmcnt(12)
ds_write_b16 v18, v126 offset:12160
s_waitcnt vmcnt(11)
ds_write_b16 v18, v23 offset:12480
s_waitcnt vmcnt(10)
ds_write_b16 v18, v8 offset:12800
s_waitcnt vmcnt(9)
ds_write_b16 v18, v4 offset:13120
s_waitcnt vmcnt(8)
ds_write_b16 v18, v5 offset:13440
s_waitcnt vmcnt(7)
ds_write_b16 v18, v6 offset:13760
s_waitcnt vmcnt(6)
ds_write_b16 v18, v7 offset:14080
s_waitcnt vmcnt(5)
ds_write_b16 v18, v9 offset:14400
s_waitcnt vmcnt(4)
ds_write_b16 v18, v10 offset:14720
s_waitcnt vmcnt(3)
ds_write_b16 v18, v11 offset:15040
s_waitcnt vmcnt(2)
ds_write_b16 v18, v1 offset:15360
s_waitcnt vmcnt(1)
ds_write_b16 v18, v2 offset:15680
s_waitcnt vmcnt(0)
ds_write_b16 v18, v12 offset:16000
s_and_saveexec_b32 s16, s1
s_cbranch_execz BB72_5
s_clause 0x1
buffer_load_dword v1, off, s[20:23], 0 offset:48
buffer_load_dword v2, off, s[20:23], 0 offset:52
s_waitcnt vmcnt(0)
v_add3_u32 v1, s15, v1, v2
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_add_co_u32 v1, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
global_load_ushort v1, v[1:2], off
s_waitcnt vmcnt(0)
ds_write_b16 v18, v1 offset:16320
BB72_5:
s_or_b32 exec_lo, exec_lo, s16
s_xor_b32 s14, s14, -1
s_mov_b32 s15, 0
s_waitcnt lgkmcnt(0)
s_barrier
BB72_6:
v_add_nc_u32_e32 v1, s15, v74
v_add_nc_u32_e32 v2, s15, v75
v_mov_b32_e32 v4, 0xffff
s_add_i32 s15, s15, 16
ds_read_b128 v[77:80], v1
ds_read_b128 v[81:84], v1 offset:256
ds_read_b128 v[85:88], v2
ds_read_b128 v[89:92], v2 offset:256
ds_read_b128 v[93:96], v2 offset:512
ds_read_b128 v[97:100], v2 offset:768
ds_read_b128 v[101:104], v2 offset:1024
ds_read_b128 v[105:108], v2 offset:1280
ds_read_b128 v[109:112], v2 offset:1536
ds_read_b128 v[113:116], v2 offset:1792
ds_read_b128 v[117:120], v2 offset:2048
ds_read_b128 v[121:124], v2 offset:2304
s_cmpk_lg_i32 s15, 0x100
s_waitcnt lgkmcnt(11)
v_and_b32_e32 v1, v4, v77
v_and_b32_e32 v5, v4, v78
v_and_b32_e32 v7, v4, v79
v_and_b32_e32 v9, v4, v80
v_and_b32_sdwa v2, v4, v77 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
s_waitcnt lgkmcnt(10)
v_lshl_or_b32 v1, v81, 16, v1
v_lshrrev_b32_e32 v10, 16, v81
v_and_b32_sdwa v6, v4, v78 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_and_b32_sdwa v8, v4, v79 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v11, 16, v82
v_lshrrev_b32_e32 v12, 16, v83
v_and_b32_sdwa v4, v4, v80 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
v_lshrrev_b32_e32 v13, 16, v84
v_lshl_or_b32 v2, v10, 16, v2
s_waitcnt lgkmcnt(1)
v_pk_fma_f16 v46, v117, v1, v46 op_sel_hi:[0,1,1]
s_waitcnt lgkmcnt(0)
v_pk_fma_f16 v0, v121, v1, v0 op_sel_hi:[0,1,1]
v_lshl_or_b32 v6, v11, 16, v6
v_lshl_or_b32 v8, v12, 16, v8
v_lshl_or_b32 v4, v13, 16, v4
v_pk_fma_f16 v10, v85, v1, v70 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v89, v1, v68 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v93, v1, v66 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v97, v1, v63 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v101, v1, v62 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v105, v1, v49 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v109, v1, v48 op_sel_hi:[0,1,1]
v_pk_fma_f16 v47, v113, v1, v47 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v85, v2, v10 op_sel:[1,0,0]
v_lshl_or_b32 v5, v82, 16, v5
v_pk_fma_f16 v0, v121, v2, v0 op_sel:[1,0,0]
v_pk_fma_f16 v10, v89, v2, v11 op_sel:[1,0,0]
v_pk_fma_f16 v11, v93, v2, v12 op_sel:[1,0,0]
v_pk_fma_f16 v12, v97, v2, v13 op_sel:[1,0,0]
v_pk_fma_f16 v13, v101, v2, v14 op_sel:[1,0,0]
v_pk_fma_f16 v14, v105, v2, v15 op_sel:[1,0,0]
v_pk_fma_f16 v15, v109, v2, v23 op_sel:[1,0,0]
v_pk_fma_f16 v23, v113, v2, v47 op_sel:[1,0,0]
v_pk_fma_f16 v46, v117, v2, v46 op_sel:[1,0,0]
v_pk_fma_f16 v2, v90, v5, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v86, v5, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v122, v5, v0 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v94, v5, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v98, v5, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v102, v5, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v106, v5, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v110, v5, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v15, v114, v5, v23 op_sel_hi:[0,1,1]
v_pk_fma_f16 v23, v118, v5, v46 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v94, v6, v10 op_sel:[1,0,0]
v_lshl_or_b32 v7, v83, 16, v7
v_pk_fma_f16 v1, v86, v6, v1 op_sel:[1,0,0]
v_pk_fma_f16 v2, v90, v6, v2 op_sel:[1,0,0]
v_pk_fma_f16 v0, v122, v6, v0 op_sel:[1,0,0]
v_pk_fma_f16 v10, v98, v6, v11 op_sel:[1,0,0]
v_pk_fma_f16 v11, v102, v6, v12 op_sel:[1,0,0]
v_pk_fma_f16 v12, v106, v6, v13 op_sel:[1,0,0]
v_pk_fma_f16 v13, v110, v6, v14 op_sel:[1,0,0]
v_pk_fma_f16 v14, v114, v6, v15 op_sel:[1,0,0]
v_pk_fma_f16 v15, v118, v6, v23 op_sel:[1,0,0]
v_pk_fma_f16 v6, v99, v7, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v87, v7, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v91, v7, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v95, v7, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v0, v123, v7, v0 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v103, v7, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v107, v7, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v111, v7, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v13, v115, v7, v14 op_sel_hi:[0,1,1]
v_pk_fma_f16 v14, v119, v7, v15 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v103, v8, v10 op_sel:[1,0,0]
v_lshl_or_b32 v9, v84, 16, v9
v_pk_fma_f16 v1, v87, v8, v1 op_sel:[1,0,0]
v_pk_fma_f16 v2, v91, v8, v2 op_sel:[1,0,0]
v_pk_fma_f16 v5, v95, v8, v5 op_sel:[1,0,0]
v_pk_fma_f16 v6, v99, v8, v6 op_sel:[1,0,0]
v_pk_fma_f16 v0, v123, v8, v0 op_sel:[1,0,0]
v_pk_fma_f16 v10, v107, v8, v11 op_sel:[1,0,0]
v_pk_fma_f16 v11, v111, v8, v12 op_sel:[1,0,0]
v_pk_fma_f16 v12, v115, v8, v13 op_sel:[1,0,0]
v_pk_fma_f16 v13, v119, v8, v14 op_sel:[1,0,0]
v_pk_fma_f16 v0, v124, v9, v0 op_sel_hi:[0,1,1]
v_pk_fma_f16 v8, v108, v9, v10 op_sel_hi:[0,1,1]
v_pk_fma_f16 v10, v112, v9, v11 op_sel_hi:[0,1,1]
v_pk_fma_f16 v11, v116, v9, v12 op_sel_hi:[0,1,1]
v_pk_fma_f16 v1, v88, v9, v1 op_sel_hi:[0,1,1]
v_pk_fma_f16 v2, v92, v9, v2 op_sel_hi:[0,1,1]
v_pk_fma_f16 v5, v96, v9, v5 op_sel_hi:[0,1,1]
v_pk_fma_f16 v6, v100, v9, v6 op_sel_hi:[0,1,1]
v_pk_fma_f16 v7, v104, v9, v7 op_sel_hi:[0,1,1]
v_pk_fma_f16 v12, v120, v9, v13 op_sel_hi:[0,1,1]
v_pk_fma_f16 v70, v88, v4, v1 op_sel:[1,0,0]
v_pk_fma_f16 v68, v92, v4, v2 op_sel:[1,0,0]
v_pk_fma_f16 v66, v96, v4, v5 op_sel:[1,0,0]
v_pk_fma_f16 v63, v100, v4, v6 op_sel:[1,0,0]
v_pk_fma_f16 v62, v104, v4, v7 op_sel:[1,0,0]
v_pk_fma_f16 v49, v108, v4, v8 op_sel:[1,0,0]
v_pk_fma_f16 v48, v112, v4, v10 op_sel:[1,0,0]
v_pk_fma_f16 v47, v116, v4, v11 op_sel:[1,0,0]
v_pk_fma_f16 v46, v120, v4, v12 op_sel:[1,0,0]
v_pk_fma_f16 v0, v124, v4, v0 op_sel:[1,0,0]
s_cbranch_scc1 BB72_6
s_and_b32 vcc_lo, exec_lo, s14
s_movk_i32 s15, 0x80
s_mov_b32 s14, 0
s_cbranch_vccz BB72_1
buffer_load_dword v2, off, s[20:23], 0 offset:56
v_and_b32_e32 v1, 62, v18
s_lshl_b32 s0, s6, 6
s_and_b32 s0, s0, 0xc0
s_waitcnt vmcnt(0)
v_mad_u32_u24 v2, 0xa00, v2, s4
v_or3_b32 v1, v2, s0, v1
v_add_nc_u32_e32 v3, 0x400, v1
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v5, 0x500, v1
v_add_nc_u32_e32 v7, 0x600, v1
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[9:10], 1, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
v_add_nc_u32_e32 v2, 0x700, v1
v_lshlrev_b64 v[11:12], 1, v[3:4]
v_add_co_u32 v9, vcc_lo, s2, v9
v_lshlrev_b64 v[4:5], 1, v[5:6]
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
v_lshlrev_b64 v[6:7], 1, v[7:8]
v_add_co_u32 v11, vcc_lo, s2, v11
v_add_nc_u32_e32 v8, 0x800, v1
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
global_store_dword v[9:10], v70, off
global_store_short v[9:10], v68, off offset:512
global_store_short_d16_hi v[9:10], v68, off offset:514
global_store_dword v[9:10], v66, off offset:1024
global_store_dword v[9:10], v63, off offset:1536
global_store_dword v[11:12], v62, off
v_add_nc_u32_e32 v10, 0x900, v1
v_ashrrev_i32_e32 v9, 31, v8
v_add_co_u32 v4, vcc_lo, s2, v4
v_lshlrev_b64 v[2:3], 1, v[2:3]
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_ashrrev_i32_e32 v11, 31, v10
v_add_co_u32 v6, vcc_lo, s2, v6
v_lshlrev_b64 v[8:9], 1, v[8:9]
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v1, vcc_lo, s2, v2
v_lshlrev_b64 v[10:11], 1, v[10:11]
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s2, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
global_store_dword v[4:5], v49, off
global_store_dword v[6:7], v48, off
global_store_dword v[1:2], v47, off
global_store_dword v[8:9], v46, off
global_store_dword v[10:11], v0, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_dense_kernel0
.amdhsa_group_segment_fixed_size 29184
.amdhsa_private_segment_fixed_size 60
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 128
.amdhsa_next_free_sgpr 24
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end72:
.size tvmgen_default_fused_nn_dense_kernel0, .Lfunc_end72-tvmgen_default_fused_nn_dense_kernel0
.globl tvmgen_default_fused_nn_max_pool2d_kernel0
.p2align 8
.type tvmgen_default_fused_nn_max_pool2d_kernel0,@function
tvmgen_default_fused_nn_max_pool2d_kernel0:
v_lshl_add_u32 v0, s6, 5, v0
s_load_dwordx2 s[6:7], s[4:5], 0x8
v_mul_hi_i32 v1, 0x51eb851f, v0
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v1, 12, v1
v_add_nc_u32_e32 v1, v1, v2
v_mul_i32_i24_e32 v2, 0x3200, v1
v_lshlrev_b32_e32 v6, 1, v1
v_sub_nc_u32_e32 v4, v0, v2
v_mul_i32_i24_e32 v2, 0xc800, v1
v_add_nc_u32_e32 v1, -1, v6
v_ashrrev_i32_e32 v5, 6, v4
v_and_or_b32 v2, v0, 63, v2
v_cmp_gt_u32_e64 s2, 0x177, v1
v_cmp_lt_i32_e64 s1, 63, v4
v_mov_b32_e32 v1, 0xfbff
v_lshlrev_b32_e32 v3, 7, v5
s_and_b32 s3, s2, s1
v_add3_u32 v2, v2, v3, 0xffff9bc0
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[7:8], 1, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_and_saveexec_b32 s0, s3
s_cbranch_execz BB73_2
global_load_ushort v1, v[7:8], off
BB73_2:
s_or_b32 exec_lo, exec_lo, s0
v_lshl_or_b32 v3, v5, 1, 1
v_cmp_lt_i32_e64 s0, 0, v3
v_mov_b32_e32 v3, 0xfbff
s_and_b32 s8, s2, s0
s_and_saveexec_b32 s3, s8
s_cbranch_execz BB73_4
global_load_ushort v3, v[7:8], off offset:128
BB73_4:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_lt_i32_e32 vcc_lo, -1, v4
v_mov_b32_e32 v4, 0xfbff
s_and_b32 s3, s2, vcc_lo
s_and_saveexec_b32 s2, s3
s_cbranch_execz BB73_6
global_load_ushort v4, v[7:8], off offset:256
BB73_6:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_u32_e64 s2, 0x177, v6
v_mov_b32_e32 v5, 0xfbff
s_and_b32 s3, s2, s1
s_and_saveexec_b32 s8, s3
s_cbranch_execz BB73_8
v_add_nc_u32_e32 v7, 0x6400, v2
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 1, v[7:8]
v_add_co_u32 v7, s3, s6, v7
v_add_co_ci_u32_e64 v8, s3, s7, v8, s3
global_load_ushort v5, v[7:8], off
BB73_8:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v7, 0xfbff
s_and_b32 s3, s2, s0
s_and_saveexec_b32 s8, s3
s_cbranch_execz BB73_10
v_add_nc_u32_e32 v7, 0x6440, v2
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 1, v[7:8]
v_add_co_u32 v7, s3, s6, v7
v_add_co_ci_u32_e64 v8, s3, s7, v8, s3
global_load_ushort v7, v[7:8], off
BB73_10:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v8, 0xfbff
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz BB73_12
v_add_nc_u32_e32 v8, 0x6480, v2
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 1, v[8:9]
v_add_co_u32 v8, s2, s6, v8
v_add_co_ci_u32_e64 v9, s2, s7, v9, s2
global_load_ushort v8, v[8:9], off
BB73_12:
s_or_b32 exec_lo, exec_lo, s3
v_or_b32_e32 v6, 1, v6
v_cmp_gt_u32_e64 s2, 0x177, v6
v_mov_b32_e32 v6, 0xfbff
s_and_b32 s1, s2, s1
s_and_saveexec_b32 s3, s1
s_cbranch_execz BB73_14
v_add_nc_u32_e32 v9, 0xc800, v2
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 1, v[9:10]
v_add_co_u32 v9, s1, s6, v9
v_add_co_ci_u32_e64 v10, s1, s7, v10, s1
global_load_ushort v6, v[9:10], off
BB73_14:
s_or_b32 exec_lo, exec_lo, s3
s_load_dwordx2 s[4:5], s[4:5], 0x0
v_mov_b32_e32 v9, 0xfbff
s_and_b32 s0, s2, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB73_16
v_add_nc_u32_e32 v9, 0xc840, v2
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 1, v[9:10]
v_add_co_u32 v9, s0, s6, v9
v_add_co_ci_u32_e64 v10, s0, s7, v10, s0
global_load_ushort v9, v[9:10], off
BB73_16:
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v10, 0xfbff
s_and_b32 s1, s2, vcc_lo
s_and_saveexec_b32 s0, s1
s_cbranch_execz BB73_18
v_add_nc_u32_e32 v10, 0xc880, v2
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 1, v[10:11]
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
global_load_ushort v10, v[10:11], off
BB73_18:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s0, 0xfbff
s_waitcnt vmcnt(0)
v_cmp_ngt_f16_e32 vcc_lo, s0, v1
v_cndmask_b32_e32 v1, s0, v1, vcc_lo
v_cmp_gt_f16_e32 vcc_lo, v1, v3
v_cndmask_b32_e32 v1, v3, v1, vcc_lo
v_cmp_gt_f16_e32 vcc_lo, v1, v4
v_cndmask_b32_e32 v1, v4, v1, vcc_lo
v_cmp_gt_f16_e32 vcc_lo, v1, v5
v_cndmask_b32_e32 v1, v5, v1, vcc_lo
v_cmp_gt_f16_e32 vcc_lo, v1, v7
v_cndmask_b32_e32 v1, v7, v1, vcc_lo
v_cmp_gt_f16_e32 vcc_lo, v1, v8
v_cndmask_b32_e32 v2, v8, v1, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
v_cmp_gt_f16_e32 vcc_lo, v2, v6
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_cndmask_b32_e32 v2, v6, v2, vcc_lo
v_cmp_gt_f16_e32 vcc_lo, v2, v9
v_cndmask_b32_e32 v2, v9, v2, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_cmp_gt_f16_e32 vcc_lo, v2, v10
v_cndmask_b32_e32 v2, v10, v2, vcc_lo
global_store_short v[0:1], v2, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_max_pool2d_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 9
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end73:
.size tvmgen_default_fused_nn_max_pool2d_kernel0, .Lfunc_end73-tvmgen_default_fused_nn_max_pool2d_kernel0
.globl tvmgen_default_fused_nn_softmax_cast_1_kernel0
.p2align 8
.type tvmgen_default_fused_nn_softmax_cast_1_kernel0,@function
tvmgen_default_fused_nn_softmax_cast_1_kernel0:
s_movk_i32 s1, 0x258
s_load_dwordx2 s[2:3], s[4:5], 0x0
s_mul_i32 s6, s6, s1
s_mov_b32 s0, 0xff7fffff
v_add_nc_u32_e32 v1, s6, v0
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v5, 0x200, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_clause 0x7
global_load_dword v14, v[3:4], off
global_load_dword v13, v[3:4], off offset:256
global_load_dword v12, v[3:4], off offset:512
global_load_dword v11, v[3:4], off offset:768
global_load_dword v10, v[3:4], off offset:1024
global_load_dword v9, v[3:4], off offset:1280
global_load_dword v8, v[3:4], off offset:1536
global_load_dword v7, v[3:4], off offset:1792
v_add_co_u32 v3, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v6, vcc_lo
global_load_dword v5, v[3:4], off
s_waitcnt vmcnt(8)
v_cmp_ngt_f32_e32 vcc_lo, s0, v14
v_cndmask_b32_e32 v3, s0, v14, vcc_lo
v_cmp_gt_i32_e64 s0, 24, v0
s_waitcnt vmcnt(7)
v_cmp_gt_f32_e32 vcc_lo, v3, v13
v_cndmask_b32_e32 v3, v13, v3, vcc_lo
s_waitcnt vmcnt(6)
v_cmp_gt_f32_e32 vcc_lo, v3, v12
v_cndmask_b32_e32 v3, v12, v3, vcc_lo
s_waitcnt vmcnt(5)
v_cmp_gt_f32_e32 vcc_lo, v3, v11
v_cndmask_b32_e32 v3, v11, v3, vcc_lo
s_waitcnt vmcnt(4)
v_cmp_gt_f32_e32 vcc_lo, v3, v10
v_cndmask_b32_e32 v3, v10, v3, vcc_lo
s_waitcnt vmcnt(3)
v_cmp_gt_f32_e32 vcc_lo, v3, v9
v_cndmask_b32_e32 v4, v9, v3, vcc_lo
v_add_nc_u32_e32 v3, 0x240, v1
s_waitcnt vmcnt(2)
v_cmp_gt_f32_e32 vcc_lo, v4, v8
v_cndmask_b32_e32 v6, v8, v4, vcc_lo
v_ashrrev_i32_e32 v4, 31, v3
s_waitcnt vmcnt(1)
v_cmp_gt_f32_e32 vcc_lo, v6, v7
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_cndmask_b32_e32 v6, v7, v6, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v5
v_cndmask_b32_e32 v6, v5, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_and_saveexec_b32 s2, s0
s_cbranch_execz BB74_2
global_load_dword v15, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v15
v_cndmask_b32_e32 v6, v15, v6, vcc_lo
BB74_2:
s_or_b32 exec_lo, exec_lo, s2
v_mbcnt_lo_u32_b32 v15, -1, 0
v_mbcnt_hi_u32_b32 v20, -1, v15
v_lshlrev_b32_e32 v19, 2, v20
v_cmp_lt_u32_e32 vcc_lo, 31, v20
v_or_b32_e32 v15, 0x80, v19
v_add_nc_u32_e32 v16, 64, v19
v_add_nc_u32_e32 v22, 8, v19
v_cndmask_b32_e32 v15, v15, v19, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 47, v20
ds_bpermute_b32 v17, v15, v6
v_cndmask_b32_e32 v16, v16, v19, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v17
v_cndmask_b32_e32 v6, v17, v6, vcc_lo
v_add_nc_u32_e32 v17, 32, v19
v_cmp_lt_u32_e32 vcc_lo, 55, v20
ds_bpermute_b32 v18, v16, v6
v_cndmask_b32_e32 v17, v17, v19, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v18
v_cndmask_b32_e32 v6, v18, v6, vcc_lo
v_add_nc_u32_e32 v18, 16, v19
v_cmp_lt_u32_e32 vcc_lo, 59, v20
ds_bpermute_b32 v21, v17, v6
v_cndmask_b32_e32 v18, v18, v19, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v21
v_cndmask_b32_e32 v6, v21, v6, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 61, v20
ds_bpermute_b32 v21, v18, v6
v_cndmask_b32_e32 v19, v22, v19, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v21
v_cndmask_b32_e32 v6, v21, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 63, v20
ds_bpermute_b32 v21, v19, v6
v_add_co_ci_u32_e32 v20, vcc_lo, 0, v20, vcc_lo
v_lshlrev_b32_e32 v20, 2, v20
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v21
v_cndmask_b32_e32 v6, v21, v6, vcc_lo
v_mov_b32_e32 v21, 0
ds_bpermute_b32 v22, v20, v6
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v22
v_cndmask_b32_e32 v6, v22, v6, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s1, v0
ds_bpermute_b32 v6, v21, v6
s_waitcnt lgkmcnt(0)
ds_write_b32 v21, v6
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execnz BB74_24
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s10, 0x218, v0
s_and_saveexec_b32 s2, s10
s_cbranch_execnz BB74_25
BB74_4:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s9, 0x1d8, v0
s_and_saveexec_b32 s2, s9
s_cbranch_execnz BB74_26
BB74_5:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s8, 0x198, v0
s_and_saveexec_b32 s2, s8
s_cbranch_execnz BB74_27
BB74_6:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s7, 0x158, v0
s_and_saveexec_b32 s2, s7
s_cbranch_execnz BB74_28
BB74_7:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s6, 0x118, v0
s_and_saveexec_b32 s2, s6
s_cbranch_execnz BB74_29
BB74_8:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s3, 0xd8, v0
s_and_saveexec_b32 s2, s3
s_cbranch_execnz BB74_30
BB74_9:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s2, 0x98, v0
s_and_saveexec_b32 s11, s2
s_cbranch_execnz BB74_31
BB74_10:
s_or_b32 exec_lo, exec_lo, s11
v_cmp_gt_i32_e64 s1, 0x58, v0
s_and_saveexec_b32 s12, s1
s_cbranch_execnz BB74_32
BB74_11:
s_or_b32 exec_lo, exec_lo, s12
s_load_dwordx2 s[12:13], s[4:5], 0x8
s_and_saveexec_b32 s5, s0
s_cbranch_execz BB74_13
BB74_12:
global_load_dword v0, v[3:4], off
s_mov_b32 s4, 0x39a3b295
s_mov_b32 s11, 0x3fb8a000
s_waitcnt vmcnt(0)
v_sub_f32_e32 v0, v0, v6
v_and_b32_e32 v22, 0xfffff000, v0
v_sub_f32_e32 v23, v0, v22
v_mul_f32_e32 v25, s11, v22
v_mul_f32_e32 v24, s4, v23
v_fmac_f32_e32 v24, s11, v23
v_rndne_f32_e32 v23, v25
v_fmac_f32_e32 v24, s4, v22
v_fma_f32 v22, v22, s11, -v23
v_cvt_i32_f32_e32 v23, v23
v_cmp_ngt_f32_e64 s4, 0xc2ce8ed0, v0
v_add_f32_e32 v22, v22, v24
v_exp_f32_e32 v22, v22
v_ldexp_f32 v22, v22, v23
v_cndmask_b32_e64 v22, 0, v22, s4
v_cmp_nlt_f32_e64 s4, 0x42b17218, v0
v_cndmask_b32_e64 v0, 0x7f800000, v22, s4
v_add_f32_e32 v21, v21, v0
BB74_13:
s_or_b32 exec_lo, exec_lo, s5
ds_bpermute_b32 v0, v15, v21
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v21, v0
ds_bpermute_b32 v15, v16, v0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v15
ds_bpermute_b32 v15, v17, v0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v15
ds_bpermute_b32 v15, v18, v0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v15
ds_bpermute_b32 v15, v19, v0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v15
ds_bpermute_b32 v15, v20, v0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v15
v_mov_b32_e32 v15, 0
ds_bpermute_b32 v0, v15, v0
s_waitcnt lgkmcnt(0)
ds_write_b32 v15, v0 offset:4
s_and_saveexec_b32 s4, vcc_lo
s_xor_b32 s4, exec_lo, s4
s_cbranch_execnz BB74_33
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s10
s_cbranch_execnz BB74_34
BB74_15:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s9
s_cbranch_execnz BB74_35
BB74_16:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s8
s_cbranch_execnz BB74_36
BB74_17:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s7
s_cbranch_execnz BB74_37
BB74_18:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s6
s_cbranch_execnz BB74_38
BB74_19:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s3
s_cbranch_execnz BB74_39
BB74_20:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s3, s2
s_cbranch_execnz BB74_40
BB74_21:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s2, s1
s_cbranch_execnz BB74_41
BB74_22:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s1, s0
s_cbranch_execnz BB74_42
BB74_23:
s_endpgm
BB74_24:
v_sub_f32_e32 v21, v14, v6
s_mov_b32 s1, 0x39a3b295
s_mov_b32 s3, 0x3fb8a000
v_and_b32_e32 v22, 0xfffff000, v21
v_sub_f32_e32 v23, v21, v22
v_mul_f32_e32 v25, s3, v22
v_mul_f32_e32 v24, s1, v23
v_fmac_f32_e32 v24, s3, v23
v_rndne_f32_e32 v23, v25
v_fmac_f32_e32 v24, s1, v22
v_fma_f32 v22, v22, s3, -v23
v_cvt_i32_f32_e32 v23, v23
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v21
v_add_f32_e32 v22, v22, v24
v_exp_f32_e32 v22, v22
v_ldexp_f32 v22, v22, v23
v_add_f32_e32 v22, 0, v22
v_cndmask_b32_e64 v22, 0, v22, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v21
v_cndmask_b32_e64 v21, 0x7f800000, v22, s1
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s10, 0x218, v0
s_and_saveexec_b32 s2, s10
s_cbranch_execz BB74_4
BB74_25:
v_sub_f32_e32 v22, v13, v6
s_mov_b32 s1, 0x39a3b295
s_mov_b32 s3, 0x3fb8a000
v_and_b32_e32 v23, 0xfffff000, v22
v_sub_f32_e32 v24, v22, v23
v_mul_f32_e32 v26, s3, v23
v_mul_f32_e32 v25, s1, v24
v_fmac_f32_e32 v25, s3, v24
v_rndne_f32_e32 v24, v26
v_fmac_f32_e32 v25, s1, v23
v_fma_f32 v23, v23, s3, -v24
v_cvt_i32_f32_e32 v24, v24
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v22
v_add_f32_e32 v23, v23, v25
v_exp_f32_e32 v23, v23
v_ldexp_f32 v23, v23, v24
v_cndmask_b32_e64 v23, 0, v23, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v22
v_cndmask_b32_e64 v22, 0x7f800000, v23, s1
v_add_f32_e32 v21, v21, v22
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s9, 0x1d8, v0
s_and_saveexec_b32 s2, s9
s_cbranch_execz BB74_5
BB74_26:
v_sub_f32_e32 v22, v12, v6
s_mov_b32 s1, 0x39a3b295
s_mov_b32 s3, 0x3fb8a000
v_and_b32_e32 v23, 0xfffff000, v22
v_sub_f32_e32 v24, v22, v23
v_mul_f32_e32 v26, s3, v23
v_mul_f32_e32 v25, s1, v24
v_fmac_f32_e32 v25, s3, v24
v_rndne_f32_e32 v24, v26
v_fmac_f32_e32 v25, s1, v23
v_fma_f32 v23, v23, s3, -v24
v_cvt_i32_f32_e32 v24, v24
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v22
v_add_f32_e32 v23, v23, v25
v_exp_f32_e32 v23, v23
v_ldexp_f32 v23, v23, v24
v_cndmask_b32_e64 v23, 0, v23, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v22
v_cndmask_b32_e64 v22, 0x7f800000, v23, s1
v_add_f32_e32 v21, v21, v22
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s8, 0x198, v0
s_and_saveexec_b32 s2, s8
s_cbranch_execz BB74_6
BB74_27:
v_sub_f32_e32 v22, v11, v6
s_mov_b32 s1, 0x39a3b295
s_mov_b32 s3, 0x3fb8a000
v_and_b32_e32 v23, 0xfffff000, v22
v_sub_f32_e32 v24, v22, v23
v_mul_f32_e32 v26, s3, v23
v_mul_f32_e32 v25, s1, v24
v_fmac_f32_e32 v25, s3, v24
v_rndne_f32_e32 v24, v26
v_fmac_f32_e32 v25, s1, v23
v_fma_f32 v23, v23, s3, -v24
v_cvt_i32_f32_e32 v24, v24
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v22
v_add_f32_e32 v23, v23, v25
v_exp_f32_e32 v23, v23
v_ldexp_f32 v23, v23, v24
v_cndmask_b32_e64 v23, 0, v23, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v22
v_cndmask_b32_e64 v22, 0x7f800000, v23, s1
v_add_f32_e32 v21, v21, v22
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s7, 0x158, v0
s_and_saveexec_b32 s2, s7
s_cbranch_execz BB74_7
BB74_28:
v_sub_f32_e32 v22, v10, v6
s_mov_b32 s1, 0x39a3b295
s_mov_b32 s3, 0x3fb8a000
v_and_b32_e32 v23, 0xfffff000, v22
v_sub_f32_e32 v24, v22, v23
v_mul_f32_e32 v26, s3, v23
v_mul_f32_e32 v25, s1, v24
v_fmac_f32_e32 v25, s3, v24
v_rndne_f32_e32 v24, v26
v_fmac_f32_e32 v25, s1, v23
v_fma_f32 v23, v23, s3, -v24
v_cvt_i32_f32_e32 v24, v24
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v22
v_add_f32_e32 v23, v23, v25
v_exp_f32_e32 v23, v23
v_ldexp_f32 v23, v23, v24
v_cndmask_b32_e64 v23, 0, v23, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v22
v_cndmask_b32_e64 v22, 0x7f800000, v23, s1
v_add_f32_e32 v21, v21, v22
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s6, 0x118, v0
s_and_saveexec_b32 s2, s6
s_cbranch_execz BB74_8
BB74_29:
v_sub_f32_e32 v22, v9, v6
s_mov_b32 s1, 0x39a3b295
s_mov_b32 s3, 0x3fb8a000
v_and_b32_e32 v23, 0xfffff000, v22
v_sub_f32_e32 v24, v22, v23
v_mul_f32_e32 v26, s3, v23
v_mul_f32_e32 v25, s1, v24
v_fmac_f32_e32 v25, s3, v24
v_rndne_f32_e32 v24, v26
v_fmac_f32_e32 v25, s1, v23
v_fma_f32 v23, v23, s3, -v24
v_cvt_i32_f32_e32 v24, v24
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v22
v_add_f32_e32 v23, v23, v25
v_exp_f32_e32 v23, v23
v_ldexp_f32 v23, v23, v24
v_cndmask_b32_e64 v23, 0, v23, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v22
v_cndmask_b32_e64 v22, 0x7f800000, v23, s1
v_add_f32_e32 v21, v21, v22
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s3, 0xd8, v0
s_and_saveexec_b32 s2, s3
s_cbranch_execz BB74_9
BB74_30:
v_sub_f32_e32 v22, v8, v6
s_mov_b32 s1, 0x39a3b295
s_mov_b32 s11, 0x3fb8a000
v_and_b32_e32 v23, 0xfffff000, v22
v_sub_f32_e32 v24, v22, v23
v_mul_f32_e32 v26, s11, v23
v_mul_f32_e32 v25, s1, v24
v_fmac_f32_e32 v25, s11, v24
v_rndne_f32_e32 v24, v26
v_fmac_f32_e32 v25, s1, v23
v_fma_f32 v23, v23, s11, -v24
v_cvt_i32_f32_e32 v24, v24
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v22
v_add_f32_e32 v23, v23, v25
v_exp_f32_e32 v23, v23
v_ldexp_f32 v23, v23, v24
v_cndmask_b32_e64 v23, 0, v23, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v22
v_cndmask_b32_e64 v22, 0x7f800000, v23, s1
v_add_f32_e32 v21, v21, v22
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s2, 0x98, v0
s_and_saveexec_b32 s11, s2
s_cbranch_execz BB74_10
BB74_31:
v_sub_f32_e32 v22, v7, v6
s_mov_b32 s1, 0x39a3b295
s_mov_b32 s12, 0x3fb8a000
v_and_b32_e32 v23, 0xfffff000, v22
v_sub_f32_e32 v24, v22, v23
v_mul_f32_e32 v26, s12, v23
v_mul_f32_e32 v25, s1, v24
v_fmac_f32_e32 v25, s12, v24
v_rndne_f32_e32 v24, v26
v_fmac_f32_e32 v25, s1, v23
v_fma_f32 v23, v23, s12, -v24
v_cvt_i32_f32_e32 v24, v24
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v22
v_add_f32_e32 v23, v23, v25
v_exp_f32_e32 v23, v23
v_ldexp_f32 v23, v23, v24
v_cndmask_b32_e64 v23, 0, v23, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v22
v_cndmask_b32_e64 v22, 0x7f800000, v23, s1
v_add_f32_e32 v21, v21, v22
s_or_b32 exec_lo, exec_lo, s11
v_cmp_gt_i32_e64 s1, 0x58, v0
s_and_saveexec_b32 s12, s1
s_cbranch_execz BB74_11
BB74_32:
v_sub_f32_e32 v0, v5, v6
s_mov_b32 s11, 0x39a3b295
s_mov_b32 s13, 0x3fb8a000
v_and_b32_e32 v22, 0xfffff000, v0
v_sub_f32_e32 v23, v0, v22
v_mul_f32_e32 v25, s13, v22
v_mul_f32_e32 v24, s11, v23
v_fmac_f32_e32 v24, s13, v23
v_rndne_f32_e32 v23, v25
v_fmac_f32_e32 v24, s11, v22
v_fma_f32 v22, v22, s13, -v23
v_cvt_i32_f32_e32 v23, v23
v_cmp_ngt_f32_e64 s11, 0xc2ce8ed0, v0
v_add_f32_e32 v22, v22, v24
v_exp_f32_e32 v22, v22
v_ldexp_f32 v22, v22, v23
v_cndmask_b32_e64 v22, 0, v22, s11
v_cmp_nlt_f32_e64 s11, 0x42b17218, v0
v_cndmask_b32_e64 v0, 0x7f800000, v22, s11
v_add_f32_e32 v21, v21, v0
s_or_b32 exec_lo, exec_lo, s12
s_load_dwordx2 s[12:13], s[4:5], 0x8
s_and_saveexec_b32 s5, s0
s_cbranch_execnz BB74_12
s_branch BB74_13
BB74_33:
v_sub_f32_e32 v14, v14, v6
s_mov_b32 s5, 0x3fb8a000
s_mov_b32 s11, 0x39a3b295
v_and_b32_e32 v15, 0xfffff000, v14
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v14
v_sub_f32_e32 v16, v14, v15
v_mul_f32_e32 v17, s5, v15
v_mul_f32_e32 v18, s11, v16
v_rndne_f32_e32 v17, v17
v_fmac_f32_e32 v18, s5, v16
v_fma_f32 v16, v15, s5, -v17
v_fmac_f32_e32 v18, s11, v15
v_add_f32_e32 v15, v16, v18
v_cvt_i32_f32_e32 v16, v17
v_exp_f32_e32 v15, v15
v_ldexp_f32 v15, v15, v16
v_cndmask_b32_e32 v15, 0, v15, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v14
v_cndmask_b32_e32 v14, 0x7f800000, v15, vcc_lo
v_div_scale_f32 v15, s5, v0, v0, v14
v_div_scale_f32 v18, vcc_lo, v14, v0, v14
v_rcp_f32_e32 v16, v15
v_fma_f32 v17, -v15, v16, 1.0
v_fmac_f32_e32 v16, v17, v16
v_mul_f32_e32 v17, v18, v16
v_fma_f32 v19, v17, -v15, v18
v_fmac_f32_e32 v17, v19, v16
v_fmac_f32_e64 v18, -v15, v17
v_div_fmas_f32 v15, v18, v16, v17
v_div_fixup_f32 v16, v15, v0, v14
v_lshlrev_b64 v[14:15], 1, v[1:2]
v_cvt_f16_f32_e32 v16, v16
v_add_co_u32 v14, vcc_lo, s12, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s13, v15, vcc_lo
global_store_short v[14:15], v16, off
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s10
s_cbranch_execz BB74_15
BB74_34:
v_sub_f32_e32 v13, v13, v6
s_mov_b32 s5, 0x3fb8a000
s_mov_b32 s10, 0x39a3b295
v_and_b32_e32 v14, 0xfffff000, v13
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v13
v_sub_f32_e32 v15, v13, v14
v_mul_f32_e32 v16, s5, v14
v_mul_f32_e32 v17, s10, v15
v_rndne_f32_e32 v16, v16
v_fmac_f32_e32 v17, s5, v15
v_fma_f32 v15, v14, s5, -v16
v_fmac_f32_e32 v17, s10, v14
v_add_f32_e32 v14, v15, v17
v_cvt_i32_f32_e32 v15, v16
v_exp_f32_e32 v14, v14
v_ldexp_f32 v14, v14, v15
v_cndmask_b32_e32 v14, 0, v14, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v13
v_cndmask_b32_e32 v13, 0x7f800000, v14, vcc_lo
v_div_scale_f32 v14, s5, v0, v0, v13
v_div_scale_f32 v17, vcc_lo, v13, v0, v13
v_rcp_f32_e32 v15, v14
v_fma_f32 v16, -v14, v15, 1.0
v_fmac_f32_e32 v15, v16, v15
v_mul_f32_e32 v16, v17, v15
v_fma_f32 v18, v16, -v14, v17
v_fmac_f32_e32 v16, v18, v15
v_fmac_f32_e64 v17, -v14, v16
v_div_fmas_f32 v14, v17, v15, v16
v_div_fixup_f32 v15, v14, v0, v13
v_lshlrev_b64 v[13:14], 1, v[1:2]
v_cvt_f16_f32_e32 v15, v15
v_add_co_u32 v13, vcc_lo, s12, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s13, v14, vcc_lo
global_store_short v[13:14], v15, off offset:128
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s9
s_cbranch_execz BB74_16
BB74_35:
v_sub_f32_e32 v12, v12, v6
s_mov_b32 s5, 0x3fb8a000
s_mov_b32 s9, 0x39a3b295
v_and_b32_e32 v13, 0xfffff000, v12
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v12
v_sub_f32_e32 v14, v12, v13
v_mul_f32_e32 v15, s5, v13
v_mul_f32_e32 v16, s9, v14
v_rndne_f32_e32 v15, v15
v_fmac_f32_e32 v16, s5, v14
v_fma_f32 v14, v13, s5, -v15
v_fmac_f32_e32 v16, s9, v13
v_add_f32_e32 v13, v14, v16
v_cvt_i32_f32_e32 v14, v15
v_exp_f32_e32 v13, v13
v_ldexp_f32 v13, v13, v14
v_cndmask_b32_e32 v13, 0, v13, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v12
v_cndmask_b32_e32 v12, 0x7f800000, v13, vcc_lo
v_div_scale_f32 v13, s5, v0, v0, v12
v_div_scale_f32 v16, vcc_lo, v12, v0, v12
v_rcp_f32_e32 v14, v13
v_fma_f32 v15, -v13, v14, 1.0
v_fmac_f32_e32 v14, v15, v14
v_mul_f32_e32 v15, v16, v14
v_fma_f32 v17, v15, -v13, v16
v_fmac_f32_e32 v15, v17, v14
v_fmac_f32_e64 v16, -v13, v15
v_div_fmas_f32 v13, v16, v14, v15
v_div_fixup_f32 v14, v13, v0, v12
v_lshlrev_b64 v[12:13], 1, v[1:2]
v_cvt_f16_f32_e32 v14, v14
v_add_co_u32 v12, vcc_lo, s12, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s13, v13, vcc_lo
global_store_short v[12:13], v14, off offset:256
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s8
s_cbranch_execz BB74_17
BB74_36:
v_sub_f32_e32 v11, v11, v6
s_mov_b32 s5, 0x3fb8a000
s_mov_b32 s8, 0x39a3b295
v_and_b32_e32 v12, 0xfffff000, v11
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v11
v_sub_f32_e32 v13, v11, v12
v_mul_f32_e32 v14, s5, v12
v_mul_f32_e32 v15, s8, v13
v_rndne_f32_e32 v14, v14
v_fmac_f32_e32 v15, s5, v13
v_fma_f32 v13, v12, s5, -v14
v_fmac_f32_e32 v15, s8, v12
v_add_f32_e32 v12, v13, v15
v_cvt_i32_f32_e32 v13, v14
v_exp_f32_e32 v12, v12
v_ldexp_f32 v12, v12, v13
v_cndmask_b32_e32 v12, 0, v12, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v11
v_cndmask_b32_e32 v11, 0x7f800000, v12, vcc_lo
v_div_scale_f32 v12, s5, v0, v0, v11
v_div_scale_f32 v15, vcc_lo, v11, v0, v11
v_rcp_f32_e32 v13, v12
v_fma_f32 v14, -v12, v13, 1.0
v_fmac_f32_e32 v13, v14, v13
v_mul_f32_e32 v14, v15, v13
v_fma_f32 v16, v14, -v12, v15
v_fmac_f32_e32 v14, v16, v13
v_fmac_f32_e64 v15, -v12, v14
v_div_fmas_f32 v12, v15, v13, v14
v_div_fixup_f32 v13, v12, v0, v11
v_lshlrev_b64 v[11:12], 1, v[1:2]
v_cvt_f16_f32_e32 v13, v13
v_add_co_u32 v11, vcc_lo, s12, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
global_store_short v[11:12], v13, off offset:384
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s7
s_cbranch_execz BB74_18
BB74_37:
v_sub_f32_e32 v10, v10, v6
s_mov_b32 s5, 0x3fb8a000
s_mov_b32 s7, 0x39a3b295
v_and_b32_e32 v11, 0xfffff000, v10
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v10
v_sub_f32_e32 v12, v10, v11
v_mul_f32_e32 v13, s5, v11
v_mul_f32_e32 v14, s7, v12
v_rndne_f32_e32 v13, v13
v_fmac_f32_e32 v14, s5, v12
v_fma_f32 v12, v11, s5, -v13
v_fmac_f32_e32 v14, s7, v11
v_add_f32_e32 v11, v12, v14
v_cvt_i32_f32_e32 v12, v13
v_exp_f32_e32 v11, v11
v_ldexp_f32 v11, v11, v12
v_cndmask_b32_e32 v11, 0, v11, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v10
v_cndmask_b32_e32 v10, 0x7f800000, v11, vcc_lo
v_div_scale_f32 v11, s5, v0, v0, v10
v_div_scale_f32 v14, vcc_lo, v10, v0, v10
v_rcp_f32_e32 v12, v11
v_fma_f32 v13, -v11, v12, 1.0
v_fmac_f32_e32 v12, v13, v12
v_mul_f32_e32 v13, v14, v12
v_fma_f32 v15, v13, -v11, v14
v_fmac_f32_e32 v13, v15, v12
v_fmac_f32_e64 v14, -v11, v13
v_div_fmas_f32 v11, v14, v12, v13
v_div_fixup_f32 v12, v11, v0, v10
v_lshlrev_b64 v[10:11], 1, v[1:2]
v_cvt_f16_f32_e32 v12, v12
v_add_co_u32 v10, vcc_lo, s12, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s13, v11, vcc_lo
global_store_short v[10:11], v12, off offset:512
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s6
s_cbranch_execz BB74_19
BB74_38:
v_sub_f32_e32 v9, v9, v6
s_mov_b32 s5, 0x3fb8a000
s_mov_b32 s6, 0x39a3b295
v_and_b32_e32 v10, 0xfffff000, v9
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
v_sub_f32_e32 v11, v9, v10
v_mul_f32_e32 v12, s5, v10
v_mul_f32_e32 v13, s6, v11
v_rndne_f32_e32 v12, v12
v_fmac_f32_e32 v13, s5, v11
v_fma_f32 v11, v10, s5, -v12
v_fmac_f32_e32 v13, s6, v10
v_add_f32_e32 v10, v11, v13
v_cvt_i32_f32_e32 v11, v12
v_exp_f32_e32 v10, v10
v_ldexp_f32 v10, v10, v11
v_cndmask_b32_e32 v10, 0, v10, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v9
v_cndmask_b32_e32 v9, 0x7f800000, v10, vcc_lo
v_div_scale_f32 v10, s5, v0, v0, v9
v_div_scale_f32 v13, vcc_lo, v9, v0, v9
v_rcp_f32_e32 v11, v10
v_fma_f32 v12, -v10, v11, 1.0
v_fmac_f32_e32 v11, v12, v11
v_mul_f32_e32 v12, v13, v11
v_fma_f32 v14, v12, -v10, v13
v_fmac_f32_e32 v12, v14, v11
v_fmac_f32_e64 v13, -v10, v12
v_div_fmas_f32 v10, v13, v11, v12
v_div_fixup_f32 v11, v10, v0, v9
v_lshlrev_b64 v[9:10], 1, v[1:2]
v_cvt_f16_f32_e32 v11, v11
v_add_co_u32 v9, vcc_lo, s12, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s13, v10, vcc_lo
global_store_short v[9:10], v11, off offset:640
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s3
s_cbranch_execz BB74_20
BB74_39:
v_sub_f32_e32 v8, v8, v6
s_mov_b32 s3, 0x3fb8a000
s_mov_b32 s5, 0x39a3b295
v_and_b32_e32 v9, 0xfffff000, v8
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v8
v_sub_f32_e32 v10, v8, v9
v_mul_f32_e32 v11, s3, v9
v_mul_f32_e32 v12, s5, v10
v_rndne_f32_e32 v11, v11
v_fmac_f32_e32 v12, s3, v10
v_fma_f32 v10, v9, s3, -v11
v_fmac_f32_e32 v12, s5, v9
v_add_f32_e32 v9, v10, v12
v_cvt_i32_f32_e32 v10, v11
v_exp_f32_e32 v9, v9
v_ldexp_f32 v9, v9, v10
v_cndmask_b32_e32 v9, 0, v9, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v8
v_cndmask_b32_e32 v8, 0x7f800000, v9, vcc_lo
v_div_scale_f32 v9, s3, v0, v0, v8
v_div_scale_f32 v12, vcc_lo, v8, v0, v8
v_rcp_f32_e32 v10, v9
v_fma_f32 v11, -v9, v10, 1.0
v_fmac_f32_e32 v10, v11, v10
v_mul_f32_e32 v11, v12, v10
v_fma_f32 v13, v11, -v9, v12
v_fmac_f32_e32 v11, v13, v10
v_fmac_f32_e64 v12, -v9, v11
v_div_fmas_f32 v9, v12, v10, v11
v_div_fixup_f32 v10, v9, v0, v8
v_lshlrev_b64 v[8:9], 1, v[1:2]
v_cvt_f16_f32_e32 v10, v10
v_add_co_u32 v8, vcc_lo, s12, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s13, v9, vcc_lo
global_store_short v[8:9], v10, off offset:768
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s3, s2
s_cbranch_execz BB74_21
BB74_40:
v_sub_f32_e32 v7, v7, v6
s_mov_b32 s2, 0x3fb8a000
s_mov_b32 s4, 0x39a3b295
v_and_b32_e32 v8, 0xfffff000, v7
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v7
v_sub_f32_e32 v9, v7, v8
v_mul_f32_e32 v10, s2, v8
v_mul_f32_e32 v11, s4, v9
v_rndne_f32_e32 v10, v10
v_fmac_f32_e32 v11, s2, v9
v_fma_f32 v9, v8, s2, -v10
v_fmac_f32_e32 v11, s4, v8
v_add_f32_e32 v8, v9, v11
v_cvt_i32_f32_e32 v9, v10
v_exp_f32_e32 v8, v8
v_ldexp_f32 v8, v8, v9
v_cndmask_b32_e32 v8, 0, v8, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v7
v_cndmask_b32_e32 v7, 0x7f800000, v8, vcc_lo
v_div_scale_f32 v8, s2, v0, v0, v7
v_div_scale_f32 v11, vcc_lo, v7, v0, v7
v_rcp_f32_e32 v9, v8
v_fma_f32 v10, -v8, v9, 1.0
v_fmac_f32_e32 v9, v10, v9
v_mul_f32_e32 v10, v11, v9
v_fma_f32 v12, v10, -v8, v11
v_fmac_f32_e32 v10, v12, v9
v_fmac_f32_e64 v11, -v8, v10
v_div_fmas_f32 v8, v11, v9, v10
v_div_fixup_f32 v9, v8, v0, v7
v_lshlrev_b64 v[7:8], 1, v[1:2]
v_cvt_f16_f32_e32 v9, v9
v_add_co_u32 v7, vcc_lo, s12, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s13, v8, vcc_lo
global_store_short v[7:8], v9, off offset:896
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s2, s1
s_cbranch_execz BB74_22
BB74_41:
v_sub_f32_e32 v5, v5, v6
s_mov_b32 s1, 0x3fb8a000
s_mov_b32 s3, 0x39a3b295
v_and_b32_e32 v7, 0xfffff000, v5
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v5
v_sub_f32_e32 v8, v5, v7
v_mul_f32_e32 v9, s1, v7
v_mul_f32_e32 v10, s3, v8
v_rndne_f32_e32 v9, v9
v_fmac_f32_e32 v10, s1, v8
v_fma_f32 v8, v7, s1, -v9
v_fmac_f32_e32 v10, s3, v7
v_add_f32_e32 v7, v8, v10
v_cvt_i32_f32_e32 v8, v9
v_exp_f32_e32 v7, v7
v_ldexp_f32 v7, v7, v8
v_cndmask_b32_e32 v7, 0, v7, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v5
v_cndmask_b32_e32 v5, 0x7f800000, v7, vcc_lo
v_div_scale_f32 v7, s1, v0, v0, v5
v_div_scale_f32 v10, vcc_lo, v5, v0, v5
v_rcp_f32_e32 v8, v7
v_fma_f32 v9, -v7, v8, 1.0
v_fmac_f32_e32 v8, v9, v8
v_mul_f32_e32 v9, v10, v8
v_fma_f32 v11, v9, -v7, v10
v_fmac_f32_e32 v9, v11, v8
v_fmac_f32_e64 v10, -v7, v9
v_div_fmas_f32 v7, v10, v8, v9
v_div_fixup_f32 v5, v7, v0, v5
v_lshlrev_b64 v[7:8], 1, v[1:2]
v_cvt_f16_f32_e32 v5, v5
v_add_co_u32 v7, vcc_lo, s12, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s13, v8, vcc_lo
global_store_short v[7:8], v5, off offset:1024
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB74_23
BB74_42:
global_load_dword v3, v[3:4], off
s_mov_b32 s0, 0x3fb8a000
s_mov_b32 s1, 0x39a3b295
s_waitcnt vmcnt(0)
v_sub_f32_e32 v3, v3, v6
v_and_b32_e32 v4, 0xfffff000, v3
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
v_sub_f32_e32 v5, v3, v4
v_mul_f32_e32 v6, s0, v4
v_mul_f32_e32 v7, s1, v5
v_rndne_f32_e32 v6, v6
v_fmac_f32_e32 v7, s0, v5
v_fma_f32 v5, v4, s0, -v6
v_fmac_f32_e32 v7, s1, v4
v_add_f32_e32 v4, v5, v7
v_cvt_i32_f32_e32 v5, v6
v_exp_f32_e32 v4, v4
v_ldexp_f32 v4, v4, v5
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
v_cndmask_b32_e32 v3, 0x7f800000, v4, vcc_lo
v_div_scale_f32 v4, s0, v0, v0, v3
v_div_scale_f32 v7, vcc_lo, v3, v0, v3
v_rcp_f32_e32 v5, v4
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, v6, -v4, v7
v_fmac_f32_e32 v6, v8, v5
v_fmac_f32_e64 v7, -v4, v6
v_div_fmas_f32 v4, v7, v5, v6
v_div_fixup_f32 v3, v4, v0, v3
v_lshlrev_b64 v[0:1], 1, v[1:2]
v_cvt_f16_f32_e32 v2, v3
v_add_co_u32 v0, vcc_lo, s12, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
global_store_short v[0:1], v2, off offset:1152
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_softmax_cast_1_kernel0
.amdhsa_group_segment_fixed_size 8
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 14
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end74:
.size tvmgen_default_fused_nn_softmax_cast_1_kernel0, .Lfunc_end74-tvmgen_default_fused_nn_softmax_cast_1_kernel0
.globl tvmgen_default_fused_nn_softmax_cast_2_kernel0
.p2align 8
.type tvmgen_default_fused_nn_softmax_cast_2_kernel0,@function
tvmgen_default_fused_nn_softmax_cast_2_kernel0:
s_load_dwordx2 s[0:1], s[4:5], 0x0
s_mulk_i32 s6, 0x64
v_add_nc_u32_e32 v1, s6, v0
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s0, v3
s_mov_b32 s0, 0xff7fffff
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
s_clause 0x1
global_load_dword v4, v[5:6], off
global_load_dword v3, v[5:6], off offset:200
v_lshlrev_b32_e32 v5, 2, v0
s_waitcnt vmcnt(0)
s_barrier
v_cmp_ngt_f32_e32 vcc_lo, s0, v4
v_cndmask_b32_e32 v6, s0, v4, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, v6, v3
v_cndmask_b32_e32 v6, v3, v6, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, 18, v0
ds_write_b32 v5, v6
s_waitcnt lgkmcnt(0)
s_barrier
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz BB75_2
ds_read_b32 v6, v5
ds_read_b32 v7, v5 offset:128
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e64 s0, v6, v7
v_cndmask_b32_e64 v6, v7, v6, s0
ds_write_b32 v5, v6
BB75_2:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_i32_e64 s0, 16, v0
s_waitcnt lgkmcnt(0)
s_barrier
s_and_saveexec_b32 s2, s0
s_cbranch_execz BB75_4
ds_read_b32 v6, v5
ds_read_b32 v7, v5 offset:64
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e64 s1, v6, v7
v_cndmask_b32_e64 v6, v7, v6, s1
ds_write_b32 v5, v6
ds_read_b32 v6, v5
ds_read_b32 v7, v5 offset:32
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e64 s1, v6, v7
v_cndmask_b32_e64 v6, v7, v6, s1
ds_write_b32 v5, v6
ds_read_b32 v6, v5
ds_read_b32 v7, v5 offset:16
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e64 s1, v6, v7
v_cndmask_b32_e64 v6, v7, v6, s1
ds_write_b32 v5, v6
ds_read_b32 v6, v5
ds_read_b32 v7, v5 offset:8
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e64 s1, v6, v7
v_cndmask_b32_e64 v6, v7, v6, s1
ds_write_b32 v5, v6
ds_read_b32 v6, v5
ds_read_b32 v7, v5 offset:4
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e64 s1, v6, v7
v_cndmask_b32_e64 v6, v7, v6, s1
ds_write_b32 v5, v6
BB75_4:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
s_barrier
s_mov_b32 s1, 0x3fb8a000
s_mov_b32 s2, 0x39a3b295
ds_read_b32 v6, v5
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v7, v4, v6
v_sub_f32_e32 v8, v3, v6
ds_write_b32 v5, v6 offset:400
s_waitcnt lgkmcnt(0)
s_barrier
v_and_b32_e32 v9, 0xfffff000, v7
v_and_b32_e32 v10, 0xfffff000, v8
v_sub_f32_e32 v11, v7, v9
v_sub_f32_e32 v12, v8, v10
v_mul_f32_e32 v13, s1, v9
v_mul_f32_e32 v15, s1, v10
v_mul_f32_e32 v14, s2, v11
v_mul_f32_e32 v16, s2, v12
v_rndne_f32_e32 v13, v13
v_fmac_f32_e32 v14, s1, v11
v_fmac_f32_e32 v16, s1, v12
v_rndne_f32_e32 v11, v15
v_fma_f32 v12, v9, s1, -v13
v_fmac_f32_e32 v14, s2, v9
v_fmac_f32_e32 v16, s2, v10
v_fma_f32 v9, v10, s1, -v11
v_cvt_i32_f32_e32 v11, v11
s_load_dwordx2 s[2:3], s[4:5], 0x8
v_add_f32_e32 v10, v12, v14
v_cvt_i32_f32_e32 v12, v13
v_add_f32_e32 v9, v9, v16
s_mov_b32 s4, 0xc2ce8ed0
s_mov_b32 s5, 0x42b17218
v_exp_f32_e32 v10, v10
v_cmp_ngt_f32_e64 s1, s4, v8
v_exp_f32_e32 v9, v9
v_ldexp_f32 v10, v10, v12
v_ldexp_f32 v9, v9, v11
v_add_f32_e32 v10, 0, v10
v_cndmask_b32_e64 v9, 0, v9, s1
v_cmp_ngt_f32_e64 s1, s4, v7
s_mov_b32 s4, 0x7f800000
v_cndmask_b32_e64 v10, 0, v10, s1
v_cmp_nlt_f32_e64 s1, s5, v8
v_cndmask_b32_e64 v8, s4, v9, s1
v_cmp_nlt_f32_e64 s1, s5, v7
v_lshlrev_b32_e32 v9, 2, v0
v_cndmask_b32_e64 v7, s4, v10, s1
v_add_nc_u32_e32 v0, 0xc8, v9
v_add_f32_e32 v7, v7, v8
ds_write_b32 v9, v7 offset:200
s_waitcnt lgkmcnt(0)
s_barrier
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz BB75_6
ds_read_b32 v5, v0 offset:128
ds_read_b32 v6, v0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v5, v6
ds_write_b32 v0, v5
BB75_6:
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_barrier
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB75_8
ds_read_b32 v5, v0 offset:64
ds_read_b32 v6, v0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v5, v6
ds_write_b32 v0, v5
ds_read_b32 v5, v0 offset:32
ds_read_b32 v6, v0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v5, v6
ds_write_b32 v0, v5
ds_read_b32 v5, v0 offset:16
ds_read_b32 v6, v0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v5, v6
ds_write_b32 v0, v5
ds_read_b32 v5, v0 offset:8
ds_read_b32 v6, v0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v5, v6
ds_write_b32 v0, v5
ds_read_b32 v5, v0 offset:4
ds_read_b32 v6, v0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v5, v6
ds_write_b32 v0, v5
BB75_8:
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
s_barrier
s_mov_b32 s0, 0x3fb8a000
s_mov_b32 s1, 0x39a3b295
ds_read_b32 v6, v5 offset:200
ds_read_b32 v0, v5 offset:400
s_waitcnt lgkmcnt(1)
ds_write_b32 v5, v6 offset:404
s_waitcnt lgkmcnt(1)
v_sub_f32_e32 v4, v4, v0
v_sub_f32_e32 v0, v3, v0
v_and_b32_e32 v3, 0xfffff000, v4
v_and_b32_e32 v7, 0xfffff000, v0
v_sub_f32_e32 v8, v4, v3
v_mul_f32_e32 v10, s0, v3
v_sub_f32_e32 v9, v0, v7
v_mul_f32_e32 v12, s0, v7
v_mul_f32_e32 v11, s1, v8
v_rndne_f32_e32 v10, v10
v_mul_f32_e32 v13, s1, v9
v_fmac_f32_e32 v11, s0, v8
v_rndne_f32_e32 v8, v12
v_fmac_f32_e32 v13, s0, v9
v_fma_f32 v9, v3, s0, -v10
v_fmac_f32_e32 v11, s1, v3
v_fma_f32 v3, v7, s0, -v8
v_fmac_f32_e32 v13, s1, v7
s_mov_b32 s0, 0xc2ce8ed0
v_cvt_i32_f32_e32 v8, v8
v_add_f32_e32 v7, v9, v11
v_cvt_i32_f32_e32 v9, v10
v_add_f32_e32 v3, v3, v13
v_cmp_ngt_f32_e32 vcc_lo, s0, v4
s_mov_b32 s1, 0x42b17218
v_exp_f32_e32 v7, v7
v_exp_f32_e32 v3, v3
v_ldexp_f32 v7, v7, v9
v_ldexp_f32 v3, v3, v8
v_cndmask_b32_e32 v7, 0, v7, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, s0, v0
s_mov_b32 s0, 0x7f800000
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, s1, v4
v_cndmask_b32_e32 v4, s0, v7, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, s1, v0
v_cndmask_b32_e32 v3, s0, v3, vcc_lo
v_div_scale_f32 v0, s0, v6, v6, v4
v_div_scale_f32 v12, vcc_lo, v4, v6, v4
v_div_scale_f32 v7, s0, v6, v6, v3
v_rcp_f32_e32 v8, v0
v_rcp_f32_e32 v9, v7
v_fma_f32 v10, -v0, v8, 1.0
v_fma_f32 v11, -v7, v9, 1.0
v_fmac_f32_e32 v8, v10, v8
v_div_scale_f32 v10, s0, v3, v6, v3
v_fmac_f32_e32 v9, v11, v9
v_mul_f32_e32 v11, v12, v8
v_mul_f32_e32 v13, v10, v9
v_fma_f32 v14, v11, -v0, v12
v_fma_f32 v15, v13, -v7, v10
v_fmac_f32_e32 v11, v14, v8
v_fmac_f32_e32 v13, v15, v9
v_fmac_f32_e64 v12, -v0, v11
v_lshlrev_b64 v[0:1], 1, v[1:2]
v_fmac_f32_e64 v10, -v7, v13
v_div_fmas_f32 v7, v12, v8, v11
s_mov_b32 vcc_lo, s0
v_div_fmas_f32 v8, v10, v9, v13
v_div_fixup_f32 v2, v7, v6, v4
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_div_fixup_f32 v3, v8, v6, v3
v_cvt_f16_f32_e32 v2, v2
v_cvt_f16_f32_e32 v3, v3
global_store_short v[0:1], v2, off
global_store_short v[0:1], v3, off offset:100
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_softmax_cast_2_kernel0
.amdhsa_group_segment_fixed_size 408
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end75:
.size tvmgen_default_fused_nn_softmax_cast_2_kernel0, .Lfunc_end75-tvmgen_default_fused_nn_softmax_cast_2_kernel0
.globl tvmgen_default_fused_nn_softmax_cast_kernel0
.p2align 8
.type tvmgen_default_fused_nn_softmax_cast_kernel0,@function
tvmgen_default_fused_nn_softmax_cast_kernel0:
s_movk_i32 s1, 0x258
s_load_dwordx2 s[2:3], s[4:5], 0x0
s_mul_i32 s6, s6, s1
s_mov_b32 s0, 0xff7fffff
v_add_nc_u32_e32 v1, s6, v0
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v5, 0x200, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_clause 0x7
global_load_dword v14, v[3:4], off
global_load_dword v13, v[3:4], off offset:256
global_load_dword v12, v[3:4], off offset:512
global_load_dword v11, v[3:4], off offset:768
global_load_dword v10, v[3:4], off offset:1024
global_load_dword v9, v[3:4], off offset:1280
global_load_dword v8, v[3:4], off offset:1536
global_load_dword v7, v[3:4], off offset:1792
v_add_co_u32 v3, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v6, vcc_lo
global_load_dword v5, v[3:4], off
s_waitcnt vmcnt(8)
v_cmp_ngt_f32_e32 vcc_lo, s0, v14
v_cndmask_b32_e32 v3, s0, v14, vcc_lo
v_cmp_gt_i32_e64 s0, 24, v0
s_waitcnt vmcnt(7)
v_cmp_gt_f32_e32 vcc_lo, v3, v13
v_cndmask_b32_e32 v3, v13, v3, vcc_lo
s_waitcnt vmcnt(6)
v_cmp_gt_f32_e32 vcc_lo, v3, v12
v_cndmask_b32_e32 v3, v12, v3, vcc_lo
s_waitcnt vmcnt(5)
v_cmp_gt_f32_e32 vcc_lo, v3, v11
v_cndmask_b32_e32 v3, v11, v3, vcc_lo
s_waitcnt vmcnt(4)
v_cmp_gt_f32_e32 vcc_lo, v3, v10
v_cndmask_b32_e32 v3, v10, v3, vcc_lo
s_waitcnt vmcnt(3)
v_cmp_gt_f32_e32 vcc_lo, v3, v9
v_cndmask_b32_e32 v4, v9, v3, vcc_lo
v_add_nc_u32_e32 v3, 0x240, v1
s_waitcnt vmcnt(2)
v_cmp_gt_f32_e32 vcc_lo, v4, v8
v_cndmask_b32_e32 v6, v8, v4, vcc_lo
v_ashrrev_i32_e32 v4, 31, v3
s_waitcnt vmcnt(1)
v_cmp_gt_f32_e32 vcc_lo, v6, v7
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_cndmask_b32_e32 v6, v7, v6, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v5
v_cndmask_b32_e32 v6, v5, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_and_saveexec_b32 s2, s0
s_cbranch_execz BB76_2
global_load_dword v15, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v15
v_cndmask_b32_e32 v6, v15, v6, vcc_lo
BB76_2:
s_or_b32 exec_lo, exec_lo, s2
v_mbcnt_lo_u32_b32 v15, -1, 0
v_mbcnt_hi_u32_b32 v20, -1, v15
v_lshlrev_b32_e32 v19, 2, v20
v_cmp_lt_u32_e32 vcc_lo, 31, v20
v_or_b32_e32 v15, 0x80, v19
v_add_nc_u32_e32 v16, 64, v19
v_add_nc_u32_e32 v22, 8, v19
v_cndmask_b32_e32 v15, v15, v19, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 47, v20
ds_bpermute_b32 v17, v15, v6
v_cndmask_b32_e32 v16, v16, v19, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v17
v_cndmask_b32_e32 v6, v17, v6, vcc_lo
v_add_nc_u32_e32 v17, 32, v19
v_cmp_lt_u32_e32 vcc_lo, 55, v20
ds_bpermute_b32 v18, v16, v6
v_cndmask_b32_e32 v17, v17, v19, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v18
v_cndmask_b32_e32 v6, v18, v6, vcc_lo
v_add_nc_u32_e32 v18, 16, v19
v_cmp_lt_u32_e32 vcc_lo, 59, v20
ds_bpermute_b32 v21, v17, v6
v_cndmask_b32_e32 v18, v18, v19, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v21
v_cndmask_b32_e32 v6, v21, v6, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 61, v20
ds_bpermute_b32 v21, v18, v6
v_cndmask_b32_e32 v19, v22, v19, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v21
v_cndmask_b32_e32 v6, v21, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 63, v20
ds_bpermute_b32 v21, v19, v6
v_add_co_ci_u32_e32 v20, vcc_lo, 0, v20, vcc_lo
v_lshlrev_b32_e32 v20, 2, v20
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v21
v_cndmask_b32_e32 v6, v21, v6, vcc_lo
v_mov_b32_e32 v21, 0
ds_bpermute_b32 v22, v20, v6
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v22
v_cndmask_b32_e32 v6, v22, v6, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s1, v0
ds_bpermute_b32 v6, v21, v6
s_waitcnt lgkmcnt(0)
ds_write_b32 v21, v6
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execnz BB76_24
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s10, 0x218, v0
s_and_saveexec_b32 s2, s10
s_cbranch_execnz BB76_25
BB76_4:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s9, 0x1d8, v0
s_and_saveexec_b32 s2, s9
s_cbranch_execnz BB76_26
BB76_5:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s8, 0x198, v0
s_and_saveexec_b32 s2, s8
s_cbranch_execnz BB76_27
BB76_6:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s7, 0x158, v0
s_and_saveexec_b32 s2, s7
s_cbranch_execnz BB76_28
BB76_7:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s6, 0x118, v0
s_and_saveexec_b32 s2, s6
s_cbranch_execnz BB76_29
BB76_8:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s3, 0xd8, v0
s_and_saveexec_b32 s2, s3
s_cbranch_execnz BB76_30
BB76_9:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s2, 0x98, v0
s_and_saveexec_b32 s11, s2
s_cbranch_execnz BB76_31
BB76_10:
s_or_b32 exec_lo, exec_lo, s11
v_cmp_gt_i32_e64 s1, 0x58, v0
s_and_saveexec_b32 s12, s1
s_cbranch_execnz BB76_32
BB76_11:
s_or_b32 exec_lo, exec_lo, s12
s_load_dwordx2 s[12:13], s[4:5], 0x8
s_and_saveexec_b32 s5, s0
s_cbranch_execz BB76_13
BB76_12:
global_load_dword v0, v[3:4], off
s_mov_b32 s4, 0x39a3b295
s_mov_b32 s11, 0x3fb8a000
s_waitcnt vmcnt(0)
v_sub_f32_e32 v0, v0, v6
v_and_b32_e32 v22, 0xfffff000, v0
v_sub_f32_e32 v23, v0, v22
v_mul_f32_e32 v25, s11, v22
v_mul_f32_e32 v24, s4, v23
v_fmac_f32_e32 v24, s11, v23
v_rndne_f32_e32 v23, v25
v_fmac_f32_e32 v24, s4, v22
v_fma_f32 v22, v22, s11, -v23
v_cvt_i32_f32_e32 v23, v23
v_cmp_ngt_f32_e64 s4, 0xc2ce8ed0, v0
v_add_f32_e32 v22, v22, v24
v_exp_f32_e32 v22, v22
v_ldexp_f32 v22, v22, v23
v_cndmask_b32_e64 v22, 0, v22, s4
v_cmp_nlt_f32_e64 s4, 0x42b17218, v0
v_cndmask_b32_e64 v0, 0x7f800000, v22, s4
v_add_f32_e32 v21, v21, v0
BB76_13:
s_or_b32 exec_lo, exec_lo, s5
ds_bpermute_b32 v0, v15, v21
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v21, v0
ds_bpermute_b32 v15, v16, v0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v15
ds_bpermute_b32 v15, v17, v0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v15
ds_bpermute_b32 v15, v18, v0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v15
ds_bpermute_b32 v15, v19, v0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v15
ds_bpermute_b32 v15, v20, v0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v15
v_mov_b32_e32 v15, 0
ds_bpermute_b32 v0, v15, v0
s_waitcnt lgkmcnt(0)
ds_write_b32 v15, v0 offset:4
s_and_saveexec_b32 s4, vcc_lo
s_xor_b32 s4, exec_lo, s4
s_cbranch_execnz BB76_33
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s10
s_cbranch_execnz BB76_34
BB76_15:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s9
s_cbranch_execnz BB76_35
BB76_16:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s8
s_cbranch_execnz BB76_36
BB76_17:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s7
s_cbranch_execnz BB76_37
BB76_18:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s6
s_cbranch_execnz BB76_38
BB76_19:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s3
s_cbranch_execnz BB76_39
BB76_20:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s3, s2
s_cbranch_execnz BB76_40
BB76_21:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s2, s1
s_cbranch_execnz BB76_41
BB76_22:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s1, s0
s_cbranch_execnz BB76_42
BB76_23:
s_endpgm
BB76_24:
v_sub_f32_e32 v21, v14, v6
s_mov_b32 s1, 0x39a3b295
s_mov_b32 s3, 0x3fb8a000
v_and_b32_e32 v22, 0xfffff000, v21
v_sub_f32_e32 v23, v21, v22
v_mul_f32_e32 v25, s3, v22
v_mul_f32_e32 v24, s1, v23
v_fmac_f32_e32 v24, s3, v23
v_rndne_f32_e32 v23, v25
v_fmac_f32_e32 v24, s1, v22
v_fma_f32 v22, v22, s3, -v23
v_cvt_i32_f32_e32 v23, v23
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v21
v_add_f32_e32 v22, v22, v24
v_exp_f32_e32 v22, v22
v_ldexp_f32 v22, v22, v23
v_add_f32_e32 v22, 0, v22
v_cndmask_b32_e64 v22, 0, v22, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v21
v_cndmask_b32_e64 v21, 0x7f800000, v22, s1
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s10, 0x218, v0
s_and_saveexec_b32 s2, s10
s_cbranch_execz BB76_4
BB76_25:
v_sub_f32_e32 v22, v13, v6
s_mov_b32 s1, 0x39a3b295
s_mov_b32 s3, 0x3fb8a000
v_and_b32_e32 v23, 0xfffff000, v22
v_sub_f32_e32 v24, v22, v23
v_mul_f32_e32 v26, s3, v23
v_mul_f32_e32 v25, s1, v24
v_fmac_f32_e32 v25, s3, v24
v_rndne_f32_e32 v24, v26
v_fmac_f32_e32 v25, s1, v23
v_fma_f32 v23, v23, s3, -v24
v_cvt_i32_f32_e32 v24, v24
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v22
v_add_f32_e32 v23, v23, v25
v_exp_f32_e32 v23, v23
v_ldexp_f32 v23, v23, v24
v_cndmask_b32_e64 v23, 0, v23, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v22
v_cndmask_b32_e64 v22, 0x7f800000, v23, s1
v_add_f32_e32 v21, v21, v22
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s9, 0x1d8, v0
s_and_saveexec_b32 s2, s9
s_cbranch_execz BB76_5
BB76_26:
v_sub_f32_e32 v22, v12, v6
s_mov_b32 s1, 0x39a3b295
s_mov_b32 s3, 0x3fb8a000
v_and_b32_e32 v23, 0xfffff000, v22
v_sub_f32_e32 v24, v22, v23
v_mul_f32_e32 v26, s3, v23
v_mul_f32_e32 v25, s1, v24
v_fmac_f32_e32 v25, s3, v24
v_rndne_f32_e32 v24, v26
v_fmac_f32_e32 v25, s1, v23
v_fma_f32 v23, v23, s3, -v24
v_cvt_i32_f32_e32 v24, v24
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v22
v_add_f32_e32 v23, v23, v25
v_exp_f32_e32 v23, v23
v_ldexp_f32 v23, v23, v24
v_cndmask_b32_e64 v23, 0, v23, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v22
v_cndmask_b32_e64 v22, 0x7f800000, v23, s1
v_add_f32_e32 v21, v21, v22
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s8, 0x198, v0
s_and_saveexec_b32 s2, s8
s_cbranch_execz BB76_6
BB76_27:
v_sub_f32_e32 v22, v11, v6
s_mov_b32 s1, 0x39a3b295
s_mov_b32 s3, 0x3fb8a000
v_and_b32_e32 v23, 0xfffff000, v22
v_sub_f32_e32 v24, v22, v23
v_mul_f32_e32 v26, s3, v23
v_mul_f32_e32 v25, s1, v24
v_fmac_f32_e32 v25, s3, v24
v_rndne_f32_e32 v24, v26
v_fmac_f32_e32 v25, s1, v23
v_fma_f32 v23, v23, s3, -v24
v_cvt_i32_f32_e32 v24, v24
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v22
v_add_f32_e32 v23, v23, v25
v_exp_f32_e32 v23, v23
v_ldexp_f32 v23, v23, v24
v_cndmask_b32_e64 v23, 0, v23, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v22
v_cndmask_b32_e64 v22, 0x7f800000, v23, s1
v_add_f32_e32 v21, v21, v22
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s7, 0x158, v0
s_and_saveexec_b32 s2, s7
s_cbranch_execz BB76_7
BB76_28:
v_sub_f32_e32 v22, v10, v6
s_mov_b32 s1, 0x39a3b295
s_mov_b32 s3, 0x3fb8a000
v_and_b32_e32 v23, 0xfffff000, v22
v_sub_f32_e32 v24, v22, v23
v_mul_f32_e32 v26, s3, v23
v_mul_f32_e32 v25, s1, v24
v_fmac_f32_e32 v25, s3, v24
v_rndne_f32_e32 v24, v26
v_fmac_f32_e32 v25, s1, v23
v_fma_f32 v23, v23, s3, -v24
v_cvt_i32_f32_e32 v24, v24
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v22
v_add_f32_e32 v23, v23, v25
v_exp_f32_e32 v23, v23
v_ldexp_f32 v23, v23, v24
v_cndmask_b32_e64 v23, 0, v23, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v22
v_cndmask_b32_e64 v22, 0x7f800000, v23, s1
v_add_f32_e32 v21, v21, v22
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s6, 0x118, v0
s_and_saveexec_b32 s2, s6
s_cbranch_execz BB76_8
BB76_29:
v_sub_f32_e32 v22, v9, v6
s_mov_b32 s1, 0x39a3b295
s_mov_b32 s3, 0x3fb8a000
v_and_b32_e32 v23, 0xfffff000, v22
v_sub_f32_e32 v24, v22, v23
v_mul_f32_e32 v26, s3, v23
v_mul_f32_e32 v25, s1, v24
v_fmac_f32_e32 v25, s3, v24
v_rndne_f32_e32 v24, v26
v_fmac_f32_e32 v25, s1, v23
v_fma_f32 v23, v23, s3, -v24
v_cvt_i32_f32_e32 v24, v24
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v22
v_add_f32_e32 v23, v23, v25
v_exp_f32_e32 v23, v23
v_ldexp_f32 v23, v23, v24
v_cndmask_b32_e64 v23, 0, v23, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v22
v_cndmask_b32_e64 v22, 0x7f800000, v23, s1
v_add_f32_e32 v21, v21, v22
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s3, 0xd8, v0
s_and_saveexec_b32 s2, s3
s_cbranch_execz BB76_9
BB76_30:
v_sub_f32_e32 v22, v8, v6
s_mov_b32 s1, 0x39a3b295
s_mov_b32 s11, 0x3fb8a000
v_and_b32_e32 v23, 0xfffff000, v22
v_sub_f32_e32 v24, v22, v23
v_mul_f32_e32 v26, s11, v23
v_mul_f32_e32 v25, s1, v24
v_fmac_f32_e32 v25, s11, v24
v_rndne_f32_e32 v24, v26
v_fmac_f32_e32 v25, s1, v23
v_fma_f32 v23, v23, s11, -v24
v_cvt_i32_f32_e32 v24, v24
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v22
v_add_f32_e32 v23, v23, v25
v_exp_f32_e32 v23, v23
v_ldexp_f32 v23, v23, v24
v_cndmask_b32_e64 v23, 0, v23, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v22
v_cndmask_b32_e64 v22, 0x7f800000, v23, s1
v_add_f32_e32 v21, v21, v22
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_i32_e64 s2, 0x98, v0
s_and_saveexec_b32 s11, s2
s_cbranch_execz BB76_10
BB76_31:
v_sub_f32_e32 v22, v7, v6
s_mov_b32 s1, 0x39a3b295
s_mov_b32 s12, 0x3fb8a000
v_and_b32_e32 v23, 0xfffff000, v22
v_sub_f32_e32 v24, v22, v23
v_mul_f32_e32 v26, s12, v23
v_mul_f32_e32 v25, s1, v24
v_fmac_f32_e32 v25, s12, v24
v_rndne_f32_e32 v24, v26
v_fmac_f32_e32 v25, s1, v23
v_fma_f32 v23, v23, s12, -v24
v_cvt_i32_f32_e32 v24, v24
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v22
v_add_f32_e32 v23, v23, v25
v_exp_f32_e32 v23, v23
v_ldexp_f32 v23, v23, v24
v_cndmask_b32_e64 v23, 0, v23, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v22
v_cndmask_b32_e64 v22, 0x7f800000, v23, s1
v_add_f32_e32 v21, v21, v22
s_or_b32 exec_lo, exec_lo, s11
v_cmp_gt_i32_e64 s1, 0x58, v0
s_and_saveexec_b32 s12, s1
s_cbranch_execz BB76_11
BB76_32:
v_sub_f32_e32 v0, v5, v6
s_mov_b32 s11, 0x39a3b295
s_mov_b32 s13, 0x3fb8a000
v_and_b32_e32 v22, 0xfffff000, v0
v_sub_f32_e32 v23, v0, v22
v_mul_f32_e32 v25, s13, v22
v_mul_f32_e32 v24, s11, v23
v_fmac_f32_e32 v24, s13, v23
v_rndne_f32_e32 v23, v25
v_fmac_f32_e32 v24, s11, v22
v_fma_f32 v22, v22, s13, -v23
v_cvt_i32_f32_e32 v23, v23
v_cmp_ngt_f32_e64 s11, 0xc2ce8ed0, v0
v_add_f32_e32 v22, v22, v24
v_exp_f32_e32 v22, v22
v_ldexp_f32 v22, v22, v23
v_cndmask_b32_e64 v22, 0, v22, s11
v_cmp_nlt_f32_e64 s11, 0x42b17218, v0
v_cndmask_b32_e64 v0, 0x7f800000, v22, s11
v_add_f32_e32 v21, v21, v0
s_or_b32 exec_lo, exec_lo, s12
s_load_dwordx2 s[12:13], s[4:5], 0x8
s_and_saveexec_b32 s5, s0
s_cbranch_execnz BB76_12
s_branch BB76_13
BB76_33:
v_sub_f32_e32 v14, v14, v6
s_mov_b32 s5, 0x3fb8a000
s_mov_b32 s11, 0x39a3b295
v_and_b32_e32 v15, 0xfffff000, v14
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v14
v_sub_f32_e32 v16, v14, v15
v_mul_f32_e32 v17, s5, v15
v_mul_f32_e32 v18, s11, v16
v_rndne_f32_e32 v17, v17
v_fmac_f32_e32 v18, s5, v16
v_fma_f32 v16, v15, s5, -v17
v_fmac_f32_e32 v18, s11, v15
v_add_f32_e32 v15, v16, v18
v_cvt_i32_f32_e32 v16, v17
v_exp_f32_e32 v15, v15
v_ldexp_f32 v15, v15, v16
v_cndmask_b32_e32 v15, 0, v15, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v14
v_cndmask_b32_e32 v14, 0x7f800000, v15, vcc_lo
v_div_scale_f32 v15, s5, v0, v0, v14
v_div_scale_f32 v18, vcc_lo, v14, v0, v14
v_rcp_f32_e32 v16, v15
v_fma_f32 v17, -v15, v16, 1.0
v_fmac_f32_e32 v16, v17, v16
v_mul_f32_e32 v17, v18, v16
v_fma_f32 v19, v17, -v15, v18
v_fmac_f32_e32 v17, v19, v16
v_fmac_f32_e64 v18, -v15, v17
v_div_fmas_f32 v15, v18, v16, v17
v_div_fixup_f32 v16, v15, v0, v14
v_lshlrev_b64 v[14:15], 1, v[1:2]
v_cvt_f16_f32_e32 v16, v16
v_add_co_u32 v14, vcc_lo, s12, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s13, v15, vcc_lo
global_store_short v[14:15], v16, off
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s10
s_cbranch_execz BB76_15
BB76_34:
v_sub_f32_e32 v13, v13, v6
s_mov_b32 s5, 0x3fb8a000
s_mov_b32 s10, 0x39a3b295
v_and_b32_e32 v14, 0xfffff000, v13
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v13
v_sub_f32_e32 v15, v13, v14
v_mul_f32_e32 v16, s5, v14
v_mul_f32_e32 v17, s10, v15
v_rndne_f32_e32 v16, v16
v_fmac_f32_e32 v17, s5, v15
v_fma_f32 v15, v14, s5, -v16
v_fmac_f32_e32 v17, s10, v14
v_add_f32_e32 v14, v15, v17
v_cvt_i32_f32_e32 v15, v16
v_exp_f32_e32 v14, v14
v_ldexp_f32 v14, v14, v15
v_cndmask_b32_e32 v14, 0, v14, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v13
v_cndmask_b32_e32 v13, 0x7f800000, v14, vcc_lo
v_div_scale_f32 v14, s5, v0, v0, v13
v_div_scale_f32 v17, vcc_lo, v13, v0, v13
v_rcp_f32_e32 v15, v14
v_fma_f32 v16, -v14, v15, 1.0
v_fmac_f32_e32 v15, v16, v15
v_mul_f32_e32 v16, v17, v15
v_fma_f32 v18, v16, -v14, v17
v_fmac_f32_e32 v16, v18, v15
v_fmac_f32_e64 v17, -v14, v16
v_div_fmas_f32 v14, v17, v15, v16
v_div_fixup_f32 v15, v14, v0, v13
v_lshlrev_b64 v[13:14], 1, v[1:2]
v_cvt_f16_f32_e32 v15, v15
v_add_co_u32 v13, vcc_lo, s12, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s13, v14, vcc_lo
global_store_short v[13:14], v15, off offset:128
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s9
s_cbranch_execz BB76_16
BB76_35:
v_sub_f32_e32 v12, v12, v6
s_mov_b32 s5, 0x3fb8a000
s_mov_b32 s9, 0x39a3b295
v_and_b32_e32 v13, 0xfffff000, v12
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v12
v_sub_f32_e32 v14, v12, v13
v_mul_f32_e32 v15, s5, v13
v_mul_f32_e32 v16, s9, v14
v_rndne_f32_e32 v15, v15
v_fmac_f32_e32 v16, s5, v14
v_fma_f32 v14, v13, s5, -v15
v_fmac_f32_e32 v16, s9, v13
v_add_f32_e32 v13, v14, v16
v_cvt_i32_f32_e32 v14, v15
v_exp_f32_e32 v13, v13
v_ldexp_f32 v13, v13, v14
v_cndmask_b32_e32 v13, 0, v13, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v12
v_cndmask_b32_e32 v12, 0x7f800000, v13, vcc_lo
v_div_scale_f32 v13, s5, v0, v0, v12
v_div_scale_f32 v16, vcc_lo, v12, v0, v12
v_rcp_f32_e32 v14, v13
v_fma_f32 v15, -v13, v14, 1.0
v_fmac_f32_e32 v14, v15, v14
v_mul_f32_e32 v15, v16, v14
v_fma_f32 v17, v15, -v13, v16
v_fmac_f32_e32 v15, v17, v14
v_fmac_f32_e64 v16, -v13, v15
v_div_fmas_f32 v13, v16, v14, v15
v_div_fixup_f32 v14, v13, v0, v12
v_lshlrev_b64 v[12:13], 1, v[1:2]
v_cvt_f16_f32_e32 v14, v14
v_add_co_u32 v12, vcc_lo, s12, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s13, v13, vcc_lo
global_store_short v[12:13], v14, off offset:256
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s8
s_cbranch_execz BB76_17
BB76_36:
v_sub_f32_e32 v11, v11, v6
s_mov_b32 s5, 0x3fb8a000
s_mov_b32 s8, 0x39a3b295
v_and_b32_e32 v12, 0xfffff000, v11
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v11
v_sub_f32_e32 v13, v11, v12
v_mul_f32_e32 v14, s5, v12
v_mul_f32_e32 v15, s8, v13
v_rndne_f32_e32 v14, v14
v_fmac_f32_e32 v15, s5, v13
v_fma_f32 v13, v12, s5, -v14
v_fmac_f32_e32 v15, s8, v12
v_add_f32_e32 v12, v13, v15
v_cvt_i32_f32_e32 v13, v14
v_exp_f32_e32 v12, v12
v_ldexp_f32 v12, v12, v13
v_cndmask_b32_e32 v12, 0, v12, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v11
v_cndmask_b32_e32 v11, 0x7f800000, v12, vcc_lo
v_div_scale_f32 v12, s5, v0, v0, v11
v_div_scale_f32 v15, vcc_lo, v11, v0, v11
v_rcp_f32_e32 v13, v12
v_fma_f32 v14, -v12, v13, 1.0
v_fmac_f32_e32 v13, v14, v13
v_mul_f32_e32 v14, v15, v13
v_fma_f32 v16, v14, -v12, v15
v_fmac_f32_e32 v14, v16, v13
v_fmac_f32_e64 v15, -v12, v14
v_div_fmas_f32 v12, v15, v13, v14
v_div_fixup_f32 v13, v12, v0, v11
v_lshlrev_b64 v[11:12], 1, v[1:2]
v_cvt_f16_f32_e32 v13, v13
v_add_co_u32 v11, vcc_lo, s12, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
global_store_short v[11:12], v13, off offset:384
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s7
s_cbranch_execz BB76_18
BB76_37:
v_sub_f32_e32 v10, v10, v6
s_mov_b32 s5, 0x3fb8a000
s_mov_b32 s7, 0x39a3b295
v_and_b32_e32 v11, 0xfffff000, v10
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v10
v_sub_f32_e32 v12, v10, v11
v_mul_f32_e32 v13, s5, v11
v_mul_f32_e32 v14, s7, v12
v_rndne_f32_e32 v13, v13
v_fmac_f32_e32 v14, s5, v12
v_fma_f32 v12, v11, s5, -v13
v_fmac_f32_e32 v14, s7, v11
v_add_f32_e32 v11, v12, v14
v_cvt_i32_f32_e32 v12, v13
v_exp_f32_e32 v11, v11
v_ldexp_f32 v11, v11, v12
v_cndmask_b32_e32 v11, 0, v11, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v10
v_cndmask_b32_e32 v10, 0x7f800000, v11, vcc_lo
v_div_scale_f32 v11, s5, v0, v0, v10
v_div_scale_f32 v14, vcc_lo, v10, v0, v10
v_rcp_f32_e32 v12, v11
v_fma_f32 v13, -v11, v12, 1.0
v_fmac_f32_e32 v12, v13, v12
v_mul_f32_e32 v13, v14, v12
v_fma_f32 v15, v13, -v11, v14
v_fmac_f32_e32 v13, v15, v12
v_fmac_f32_e64 v14, -v11, v13
v_div_fmas_f32 v11, v14, v12, v13
v_div_fixup_f32 v12, v11, v0, v10
v_lshlrev_b64 v[10:11], 1, v[1:2]
v_cvt_f16_f32_e32 v12, v12
v_add_co_u32 v10, vcc_lo, s12, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s13, v11, vcc_lo
global_store_short v[10:11], v12, off offset:512
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s6
s_cbranch_execz BB76_19
BB76_38:
v_sub_f32_e32 v9, v9, v6
s_mov_b32 s5, 0x3fb8a000
s_mov_b32 s6, 0x39a3b295
v_and_b32_e32 v10, 0xfffff000, v9
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
v_sub_f32_e32 v11, v9, v10
v_mul_f32_e32 v12, s5, v10
v_mul_f32_e32 v13, s6, v11
v_rndne_f32_e32 v12, v12
v_fmac_f32_e32 v13, s5, v11
v_fma_f32 v11, v10, s5, -v12
v_fmac_f32_e32 v13, s6, v10
v_add_f32_e32 v10, v11, v13
v_cvt_i32_f32_e32 v11, v12
v_exp_f32_e32 v10, v10
v_ldexp_f32 v10, v10, v11
v_cndmask_b32_e32 v10, 0, v10, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v9
v_cndmask_b32_e32 v9, 0x7f800000, v10, vcc_lo
v_div_scale_f32 v10, s5, v0, v0, v9
v_div_scale_f32 v13, vcc_lo, v9, v0, v9
v_rcp_f32_e32 v11, v10
v_fma_f32 v12, -v10, v11, 1.0
v_fmac_f32_e32 v11, v12, v11
v_mul_f32_e32 v12, v13, v11
v_fma_f32 v14, v12, -v10, v13
v_fmac_f32_e32 v12, v14, v11
v_fmac_f32_e64 v13, -v10, v12
v_div_fmas_f32 v10, v13, v11, v12
v_div_fixup_f32 v11, v10, v0, v9
v_lshlrev_b64 v[9:10], 1, v[1:2]
v_cvt_f16_f32_e32 v11, v11
v_add_co_u32 v9, vcc_lo, s12, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s13, v10, vcc_lo
global_store_short v[9:10], v11, off offset:640
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s3
s_cbranch_execz BB76_20
BB76_39:
v_sub_f32_e32 v8, v8, v6
s_mov_b32 s3, 0x3fb8a000
s_mov_b32 s5, 0x39a3b295
v_and_b32_e32 v9, 0xfffff000, v8
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v8
v_sub_f32_e32 v10, v8, v9
v_mul_f32_e32 v11, s3, v9
v_mul_f32_e32 v12, s5, v10
v_rndne_f32_e32 v11, v11
v_fmac_f32_e32 v12, s3, v10
v_fma_f32 v10, v9, s3, -v11
v_fmac_f32_e32 v12, s5, v9
v_add_f32_e32 v9, v10, v12
v_cvt_i32_f32_e32 v10, v11
v_exp_f32_e32 v9, v9
v_ldexp_f32 v9, v9, v10
v_cndmask_b32_e32 v9, 0, v9, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v8
v_cndmask_b32_e32 v8, 0x7f800000, v9, vcc_lo
v_div_scale_f32 v9, s3, v0, v0, v8
v_div_scale_f32 v12, vcc_lo, v8, v0, v8
v_rcp_f32_e32 v10, v9
v_fma_f32 v11, -v9, v10, 1.0
v_fmac_f32_e32 v10, v11, v10
v_mul_f32_e32 v11, v12, v10
v_fma_f32 v13, v11, -v9, v12
v_fmac_f32_e32 v11, v13, v10
v_fmac_f32_e64 v12, -v9, v11
v_div_fmas_f32 v9, v12, v10, v11
v_div_fixup_f32 v10, v9, v0, v8
v_lshlrev_b64 v[8:9], 1, v[1:2]
v_cvt_f16_f32_e32 v10, v10
v_add_co_u32 v8, vcc_lo, s12, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s13, v9, vcc_lo
global_store_short v[8:9], v10, off offset:768
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s3, s2
s_cbranch_execz BB76_21
BB76_40:
v_sub_f32_e32 v7, v7, v6
s_mov_b32 s2, 0x3fb8a000
s_mov_b32 s4, 0x39a3b295
v_and_b32_e32 v8, 0xfffff000, v7
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v7
v_sub_f32_e32 v9, v7, v8
v_mul_f32_e32 v10, s2, v8
v_mul_f32_e32 v11, s4, v9
v_rndne_f32_e32 v10, v10
v_fmac_f32_e32 v11, s2, v9
v_fma_f32 v9, v8, s2, -v10
v_fmac_f32_e32 v11, s4, v8
v_add_f32_e32 v8, v9, v11
v_cvt_i32_f32_e32 v9, v10
v_exp_f32_e32 v8, v8
v_ldexp_f32 v8, v8, v9
v_cndmask_b32_e32 v8, 0, v8, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v7
v_cndmask_b32_e32 v7, 0x7f800000, v8, vcc_lo
v_div_scale_f32 v8, s2, v0, v0, v7
v_div_scale_f32 v11, vcc_lo, v7, v0, v7
v_rcp_f32_e32 v9, v8
v_fma_f32 v10, -v8, v9, 1.0
v_fmac_f32_e32 v9, v10, v9
v_mul_f32_e32 v10, v11, v9
v_fma_f32 v12, v10, -v8, v11
v_fmac_f32_e32 v10, v12, v9
v_fmac_f32_e64 v11, -v8, v10
v_div_fmas_f32 v8, v11, v9, v10
v_div_fixup_f32 v9, v8, v0, v7
v_lshlrev_b64 v[7:8], 1, v[1:2]
v_cvt_f16_f32_e32 v9, v9
v_add_co_u32 v7, vcc_lo, s12, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s13, v8, vcc_lo
global_store_short v[7:8], v9, off offset:896
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s2, s1
s_cbranch_execz BB76_22
BB76_41:
v_sub_f32_e32 v5, v5, v6
s_mov_b32 s1, 0x3fb8a000
s_mov_b32 s3, 0x39a3b295
v_and_b32_e32 v7, 0xfffff000, v5
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v5
v_sub_f32_e32 v8, v5, v7
v_mul_f32_e32 v9, s1, v7
v_mul_f32_e32 v10, s3, v8
v_rndne_f32_e32 v9, v9
v_fmac_f32_e32 v10, s1, v8
v_fma_f32 v8, v7, s1, -v9
v_fmac_f32_e32 v10, s3, v7
v_add_f32_e32 v7, v8, v10
v_cvt_i32_f32_e32 v8, v9
v_exp_f32_e32 v7, v7
v_ldexp_f32 v7, v7, v8
v_cndmask_b32_e32 v7, 0, v7, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v5
v_cndmask_b32_e32 v5, 0x7f800000, v7, vcc_lo
v_div_scale_f32 v7, s1, v0, v0, v5
v_div_scale_f32 v10, vcc_lo, v5, v0, v5
v_rcp_f32_e32 v8, v7
v_fma_f32 v9, -v7, v8, 1.0
v_fmac_f32_e32 v8, v9, v8
v_mul_f32_e32 v9, v10, v8
v_fma_f32 v11, v9, -v7, v10
v_fmac_f32_e32 v9, v11, v8
v_fmac_f32_e64 v10, -v7, v9
v_div_fmas_f32 v7, v10, v8, v9
v_div_fixup_f32 v5, v7, v0, v5
v_lshlrev_b64 v[7:8], 1, v[1:2]
v_cvt_f16_f32_e32 v5, v5
v_add_co_u32 v7, vcc_lo, s12, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s13, v8, vcc_lo
global_store_short v[7:8], v5, off offset:1024
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB76_23
BB76_42:
global_load_dword v3, v[3:4], off
s_mov_b32 s0, 0x3fb8a000
s_mov_b32 s1, 0x39a3b295
s_waitcnt vmcnt(0)
v_sub_f32_e32 v3, v3, v6
v_and_b32_e32 v4, 0xfffff000, v3
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
v_sub_f32_e32 v5, v3, v4
v_mul_f32_e32 v6, s0, v4
v_mul_f32_e32 v7, s1, v5
v_rndne_f32_e32 v6, v6
v_fmac_f32_e32 v7, s0, v5
v_fma_f32 v5, v4, s0, -v6
v_fmac_f32_e32 v7, s1, v4
v_add_f32_e32 v4, v5, v7
v_cvt_i32_f32_e32 v5, v6
v_exp_f32_e32 v4, v4
v_ldexp_f32 v4, v4, v5
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
v_cndmask_b32_e32 v3, 0x7f800000, v4, vcc_lo
v_div_scale_f32 v4, s0, v0, v0, v3
v_div_scale_f32 v7, vcc_lo, v3, v0, v3
v_rcp_f32_e32 v5, v4
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, v6, -v4, v7
v_fmac_f32_e32 v6, v8, v5
v_fmac_f32_e64 v7, -v4, v6
v_div_fmas_f32 v4, v7, v5, v6
v_div_fixup_f32 v3, v4, v0, v3
v_lshlrev_b64 v[0:1], 1, v[1:2]
v_cvt_f16_f32_e32 v2, v3
v_add_co_u32 v0, vcc_lo, s12, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
global_store_short v[0:1], v2, off offset:1152
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_nn_softmax_cast_kernel0
.amdhsa_group_segment_fixed_size 8
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 14
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end76:
.size tvmgen_default_fused_nn_softmax_cast_kernel0, .Lfunc_end76-tvmgen_default_fused_nn_softmax_cast_kernel0
.globl tvmgen_default_fused_reshape_add_add_cast_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_add_add_cast_kernel0,@function
tvmgen_default_fused_reshape_add_add_cast_kernel0:
s_clause 0x3
s_load_dwordx2 s[8:9], s[4:5], 0x18
s_load_dwordx2 s[0:1], s[4:5], 0x0
s_load_dwordx2 s[2:3], s[4:5], 0x8
s_load_dwordx2 s[4:5], s[4:5], 0x10
v_lshl_add_u32 v2, s6, 8, v0
v_lshlrev_b32_e32 v0, 1, v0
s_mov_b32 s7, 0x25800
v_cmp_gt_i32_e64 s10, 0x258, s6
v_cmp_gt_i32_e32 vcc_lo, s7, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s8, s8, v0
v_add_co_ci_u32_e64 v1, s8, s9, 0, s8
s_and_b32 s9, s10, vcc_lo
s_and_saveexec_b32 s8, s9
s_cbranch_execz BB77_2
v_ashrrev_i32_e32 v3, 31, v2
global_load_ushort v8, v[0:1], off
v_lshlrev_b64 v[4:5], 1, v[2:3]
v_add_co_u32 v6, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_ushort v6, v[6:7], off
global_load_ushort v4, v[4:5], off
s_waitcnt vmcnt(1)
v_add_f16_e32 v5, v8, v6
s_waitcnt vmcnt(0)
v_add_f16_e32 v5, v4, v5
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_cvt_f32_f16_e32 v5, v5
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_dword v[3:4], v5, off
BB77_2:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v3, 0x10000, v2
v_cmp_gt_i32_e64 s8, 0x158, s6
v_cmp_gt_i32_e32 vcc_lo, s7, v3
s_and_b32 s8, s8, vcc_lo
s_and_saveexec_b32 s7, s8
s_cbranch_execz BB77_4
v_ashrrev_i32_e32 v4, 31, v3
global_load_ushort v9, v[0:1], off
v_lshlrev_b64 v[5:6], 1, v[3:4]
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v7, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_ushort v7, v[7:8], off
global_load_ushort v5, v[5:6], off
s_waitcnt vmcnt(1)
v_add_f16_e32 v6, v9, v7
s_waitcnt vmcnt(0)
v_add_f16_e32 v5, v5, v6
v_cvt_f32_f16_e32 v5, v5
global_store_dword v[3:4], v5, off
BB77_4:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v2, 0x20000, v2
v_cmp_gt_i32_e64 s6, 0x58, s6
v_cmp_gt_i32_e32 vcc_lo, 0x25800, v2
s_and_b32 s6, s6, vcc_lo
s_and_saveexec_b32 s7, s6
s_cbranch_execz BB77_6
v_ashrrev_i32_e32 v3, 31, v2
global_load_ushort v6, v[0:1], off
v_lshlrev_b64 v[4:5], 1, v[2:3]
v_add_co_u32 v0, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_ushort v0, v[0:1], off
global_load_ushort v1, v[4:5], off
s_waitcnt vmcnt(1)
v_add_f16_e32 v0, v6, v0
s_waitcnt vmcnt(0)
v_add_f16_e32 v4, v1, v0
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_cvt_f32_f16_e32 v2, v4
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_dword v[0:1], v2, off
BB77_6:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_add_add_cast_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 11
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end77:
.size tvmgen_default_fused_reshape_add_add_cast_kernel0, .Lfunc_end77-tvmgen_default_fused_reshape_add_add_cast_kernel0
.globl tvmgen_default_fused_reshape_add_cast_add_1_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_add_cast_add_1_kernel0,@function
tvmgen_default_fused_reshape_add_cast_add_1_kernel0:
s_load_dwordx2 s[0:1], s[4:5], 0x10
v_lshl_add_u32 v1, s6, 8, v0
s_clause 0x1
s_load_dwordx2 s[2:3], s[4:5], 0x18
s_load_dwordx2 s[6:7], s[4:5], 0x8
v_lshlrev_b32_e32 v5, 1, v0
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 1, v[1:2]
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v0
s_load_dwordx2 s[0:1], s[4:5], 0x0
global_load_ushort v5, v5, s[2:3]
global_load_ushort v4, v[3:4], off
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_dword v2, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(1)
v_add_f16_e32 v3, v5, v4
v_cvt_f32_f16_e32 v3, v3
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_dword v[0:1], v2, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_add_cast_add_1_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end78:
.size tvmgen_default_fused_reshape_add_cast_add_1_kernel0, .Lfunc_end78-tvmgen_default_fused_reshape_add_cast_add_1_kernel0
.globl tvmgen_default_fused_reshape_add_cast_add_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_add_cast_add_kernel0,@function
tvmgen_default_fused_reshape_add_cast_add_kernel0:
s_clause 0x3
s_load_dwordx2 s[8:9], s[4:5], 0x18
s_load_dwordx2 s[0:1], s[4:5], 0x0
s_load_dwordx2 s[2:3], s[4:5], 0x8
s_load_dwordx2 s[4:5], s[4:5], 0x10
v_lshl_add_u32 v2, s6, 8, v0
v_lshlrev_b32_e32 v0, 1, v0
s_mov_b32 s7, 0x25800
v_cmp_gt_i32_e64 s10, 0x258, s6
v_cmp_gt_i32_e32 vcc_lo, s7, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s8, s8, v0
v_add_co_ci_u32_e64 v1, s8, s9, 0, s8
s_and_b32 s9, s10, vcc_lo
s_and_saveexec_b32 s8, s9
s_cbranch_execz BB79_2
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 1, v[2:3]
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v6
global_load_ushort v8, v[0:1], off
global_load_ushort v5, v[4:5], off
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v7, vcc_lo
global_load_dword v3, v[3:4], off
s_waitcnt vmcnt(1)
v_add_f16_e32 v4, v8, v5
v_cvt_f32_f16_e32 v4, v4
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v3, v4
v_add_co_u32 v3, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v7, vcc_lo
global_store_dword v[3:4], v5, off
BB79_2:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v3, 0x10000, v2
v_cmp_gt_i32_e64 s8, 0x158, s6
v_cmp_gt_i32_e32 vcc_lo, s7, v3
s_and_b32 s8, s8, vcc_lo
s_and_saveexec_b32 s7, s8
s_cbranch_execz BB79_4
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 1, v[3:4]
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_ushort v7, v[0:1], off
global_load_ushort v8, v[5:6], off
v_add_co_u32 v5, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_dword v5, v[5:6], off
s_waitcnt vmcnt(1)
v_add_f16_e32 v6, v7, v8
v_cvt_f32_f16_e32 v6, v6
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v5, v6
global_store_dword v[3:4], v5, off
BB79_4:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v2, 0x20000, v2
v_cmp_gt_i32_e64 s6, 0x58, s6
v_cmp_gt_i32_e32 vcc_lo, 0x25800, v2
s_and_b32 s6, s6, vcc_lo
s_and_saveexec_b32 s7, s6
s_cbranch_execz BB79_6
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 1, v[2:3]
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_ushort v6, v[0:1], off
global_load_ushort v4, v[4:5], off
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_load_dword v0, v[0:1], off
s_waitcnt vmcnt(1)
v_add_f16_e32 v1, v6, v4
v_cvt_f32_f16_e32 v1, v1
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v0, v1
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_dword v[0:1], v4, off
BB79_6:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_add_cast_add_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 11
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end79:
.size tvmgen_default_fused_reshape_add_cast_add_kernel0, .Lfunc_end79-tvmgen_default_fused_reshape_add_cast_add_kernel0
.globl tvmgen_default_fused_reshape_add_nn_relu_reshape_1_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_add_nn_relu_reshape_1_kernel0,@function
tvmgen_default_fused_reshape_add_nn_relu_reshape_1_kernel0:
s_lshl_b32 s2, s6, 9
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_lshl_add_u32 v0, v0, 1, s2
s_load_dwordx2 s[2:3], s[4:5], 0x10
v_add_nc_u32_e32 v2, 0x19000, v0
v_ashrrev_i32_e32 v1, 31, v0
v_and_b32_e32 v4, 0x7fe, v0
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_lshlrev_b32_e32 v8, 1, v4
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
global_load_dword v8, v8, s[2:3]
s_clause 0x1
global_load_dword v4, v[4:5], off
global_load_dword v5, v[6:7], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(1)
v_pk_add_f16 v4, v8, v4
s_waitcnt vmcnt(0)
v_pk_add_f16 v5, v8, v5
v_pk_max_f16 v4, v4, 0
v_pk_max_f16 v5, v5, 0
global_store_dword v[0:1], v4, off
global_store_dword v[2:3], v5, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_add_nn_relu_reshape_1_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end80:
.size tvmgen_default_fused_reshape_add_nn_relu_reshape_1_kernel0, .Lfunc_end80-tvmgen_default_fused_reshape_add_nn_relu_reshape_1_kernel0
.globl tvmgen_default_fused_reshape_add_nn_relu_reshape_2_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_add_nn_relu_reshape_2_kernel0,@function
tvmgen_default_fused_reshape_add_nn_relu_reshape_2_kernel0:
s_clause 0x2
s_load_dwordx2 s[2:3], s[4:5], 0x0
s_load_dwordx2 s[8:9], s[4:5], 0x8
s_load_dwordx2 s[4:5], s[4:5], 0x10
v_lshlrev_b32_e32 v1, 1, v0
s_lshl_b32 s7, s6, 9
v_lshl_add_u32 v3, s6, 8, v0
s_mov_b32 s10, 0x25800
s_lshl_b32 s6, s6, 1
v_add_nc_u32_e32 v4, s7, v1
v_cmp_gt_i32_e64 s0, 0x12c00, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v3
v_cmp_gt_i32_e64 s1, s10, v4
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB81_2
v_lshrrev_b32_e32 v2, 7, v0
s_mov_b32 s0, 0x51eb851f
v_mul_hi_i32 v6, v4, s0
v_add_nc_u32_e32 v2, s6, v2
v_mul_hi_i32 v5, v2, s0
v_lshrrev_b32_e32 v8, 31, v6
v_ashrrev_i32_e32 v6, 13, v6
v_add_nc_u32_e32 v6, v6, v8
v_lshrrev_b32_e32 v7, 31, v5
v_lshrrev_b32_e32 v5, 5, v5
v_mul_i32_i24_e32 v6, 0x6400, v6
v_add_nc_u32_e32 v5, v5, v7
v_and_b32_e32 v7, 0xfe, v1
v_mul_lo_u32 v5, 0x64, v5
v_or_b32_e32 v6, v6, v7
v_sub_nc_u32_e32 v2, v2, v5
v_lshl_add_u32 v5, v2, 8, v6
v_lshlrev_b32_e32 v2, 1, v7
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 1, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, s0, s8, v5
v_add_co_ci_u32_e64 v6, s0, s9, v6, s0
global_load_ushort v2, v2, s[4:5]
global_load_ushort v6, v[5:6], off
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt vmcnt(0)
v_add_f16_e32 v2, v2, v6
v_lshlrev_b64 v[5:6], 1, v[4:5]
v_max_f16_e32 v2, 0, v2
v_add_co_u32 v5, s0, s2, v5
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
global_store_short v[5:6], v2, off
BB81_2:
s_or_b32 exec_lo, exec_lo, s1
v_or_b32_e32 v2, 1, v1
s_xor_b32 s1, vcc_lo, -1
v_add_nc_u32_e32 v5, s7, v2
v_cmp_gt_i32_e64 s0, s10, v5
s_and_b32 s1, s0, s1
s_and_saveexec_b32 s0, s1
s_cbranch_execz BB81_4
v_lshrrev_b32_e32 v6, 7, v0
s_mov_b32 s1, 0x51eb851f
v_mul_hi_i32 v8, v5, s1
v_add_nc_u32_e32 v6, s6, v6
v_mul_hi_i32 v7, v6, s1
v_lshrrev_b32_e32 v10, 31, v8
v_ashrrev_i32_e32 v8, 13, v8
v_add_nc_u32_e32 v8, v8, v10
v_lshrrev_b32_e32 v9, 31, v7
v_lshrrev_b32_e32 v7, 5, v7
v_mul_i32_i24_e32 v8, 0x6400, v8
v_add_nc_u32_e32 v7, v7, v9
v_and_b32_e32 v9, 0xff, v2
v_mul_lo_u32 v7, 0x64, v7
v_or_b32_e32 v8, v8, v9
v_sub_nc_u32_e32 v6, v6, v7
v_lshl_add_u32 v6, v6, 8, v8
v_lshlrev_b32_e32 v8, 1, v9
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 1, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
global_load_ushort v8, v8, s[4:5]
global_load_ushort v7, v[6:7], off
v_ashrrev_i32_e32 v6, 31, v5
s_waitcnt vmcnt(0)
v_add_f16_e32 v8, v8, v7
v_lshlrev_b64 v[6:7], 1, v[5:6]
v_max_f16_e32 v8, 0, v8
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_store_short v[6:7], v8, off
BB81_4:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s7, 0x20000
v_add_nc_u32_e32 v6, 0x10000, v3
v_add_nc_u32_e32 v3, s7, v4
s_mov_b32 s10, 0x25800
s_addk_i32 s6, 0x200
v_cmp_gt_i32_e64 s0, 0x12c00, v6
v_cmp_gt_i32_e64 s1, s10, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v6
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB81_6
v_lshrrev_b32_e32 v4, 7, v0
s_mov_b32 s0, 0x51eb851f
v_and_b32_e32 v1, 0xfe, v1
v_mul_hi_i32 v7, v3, s0
v_add_nc_u32_e32 v4, s6, v4
v_mul_hi_i32 v6, v4, s0
v_lshrrev_b32_e32 v9, 31, v7
v_ashrrev_i32_e32 v7, 13, v7
v_add_nc_u32_e32 v7, v7, v9
v_lshrrev_b32_e32 v8, 31, v6
v_lshrrev_b32_e32 v6, 5, v6
v_mul_i32_i24_e32 v7, 0x6400, v7
v_add_nc_u32_e32 v6, v6, v8
v_or_b32_e32 v7, v7, v1
v_lshlrev_b32_e32 v1, 1, v1
v_mul_lo_u32 v6, 0x64, v6
v_sub_nc_u32_e32 v4, v4, v6
v_lshl_add_u32 v6, v4, 8, v7
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_lshlrev_b64 v[6:7], 1, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, s0, s8, v6
v_add_co_ci_u32_e64 v7, s0, s9, v7, s0
v_add_co_u32 v3, s0, s2, v3
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
global_load_ushort v1, v1, s[4:5]
global_load_ushort v6, v[6:7], off
s_waitcnt vmcnt(0)
v_add_f16_e32 v1, v1, v6
v_max_f16_e32 v1, 0, v1
global_store_short v[3:4], v1, off
BB81_6:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, s7, v5
s_xor_b32 s1, vcc_lo, -1
v_cmp_gt_i32_e64 s0, s10, v1
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB81_8
v_lshrrev_b32_e32 v0, 7, v0
s_mov_b32 s0, 0x51eb851f
v_mul_hi_i32 v4, v1, s0
v_add_nc_u32_e32 v0, s6, v0
v_mul_hi_i32 v3, v0, s0
v_lshrrev_b32_e32 v6, 31, v4
v_ashrrev_i32_e32 v4, 13, v4
v_add_nc_u32_e32 v4, v4, v6
v_lshrrev_b32_e32 v5, 31, v3
v_lshrrev_b32_e32 v3, 5, v3
v_add_nc_u32_e32 v3, v3, v5
v_and_b32_e32 v5, 0xff, v2
v_mul_i32_i24_e32 v2, 0x6400, v4
v_mul_lo_u32 v3, 0x64, v3
v_or_b32_e32 v2, v2, v5
v_sub_nc_u32_e32 v0, v0, v3
v_lshl_add_u32 v2, v0, 8, v2
v_lshlrev_b32_e32 v0, 1, v5
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_ushort v0, v0, s[4:5]
global_load_ushort v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt vmcnt(0)
v_add_f16_e32 v3, v0, v3
v_lshlrev_b64 v[0:1], 1, v[1:2]
v_max_f16_e32 v2, 0, v3
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_short v[0:1], v2, off
BB81_8:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_add_nn_relu_reshape_2_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 11
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end81:
.size tvmgen_default_fused_reshape_add_nn_relu_reshape_2_kernel0, .Lfunc_end81-tvmgen_default_fused_reshape_add_nn_relu_reshape_2_kernel0
.globl tvmgen_default_fused_reshape_add_nn_relu_reshape_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_add_nn_relu_reshape_kernel0,@function
tvmgen_default_fused_reshape_add_nn_relu_reshape_kernel0:
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_lshl_b32 s6, s6, 9
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_lshl_add_u32 v0, v0, 1, s6
v_add_nc_u32_e32 v2, 0x1e000, v0
v_and_b32_e32 v7, 0x7fe, v0
v_add_nc_u32_e32 v4, 0x3c000, v0
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v6, 0x5a000, v0
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b32_e32 v9, 1, v7
v_add_nc_u32_e32 v8, 0x78000, v0
v_lshlrev_b64 v[10:11], 1, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[1:2], 1, v[2:3]
s_waitcnt lgkmcnt(0)
global_load_dword v42, v9, s[2:3]
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[3:4], 1, v[4:5]
v_lshlrev_b64 v[5:6], 1, v[6:7]
v_add_nc_u32_e32 v7, 0x96000, v0
v_add_co_u32 v12, vcc_lo, s0, v10
v_add_nc_u32_e32 v20, 0xb4000, v0
v_add_co_ci_u32_e32 v13, vcc_lo, s1, v11, vcc_lo
v_add_co_u32 v14, vcc_lo, s0, v1
v_lshlrev_b64 v[18:19], 1, v[8:9]
v_ashrrev_i32_e32 v8, 31, v7
v_add_co_ci_u32_e32 v15, vcc_lo, s1, v2, vcc_lo
v_add_nc_u32_e32 v24, 0xd2000, v0
v_add_co_u32 v16, vcc_lo, s0, v3
v_ashrrev_i32_e32 v21, 31, v20
v_add_co_ci_u32_e32 v17, vcc_lo, s1, v4, vcc_lo
v_add_nc_u32_e32 v28, 0xf0000, v0
v_add_co_u32 v22, vcc_lo, s0, v5
v_lshlrev_b64 v[7:8], 1, v[7:8]
v_ashrrev_i32_e32 v25, 31, v24
v_add_co_ci_u32_e32 v23, vcc_lo, s1, v6, vcc_lo
v_add_nc_u32_e32 v32, 0x10e000, v0
v_add_co_u32 v26, vcc_lo, s0, v18
v_lshlrev_b64 v[20:21], 1, v[20:21]
v_ashrrev_i32_e32 v29, 31, v28
v_add_co_ci_u32_e32 v27, vcc_lo, s1, v19, vcc_lo
v_add_co_u32 v30, vcc_lo, s0, v7
v_lshlrev_b64 v[24:25], 1, v[24:25]
v_ashrrev_i32_e32 v33, 31, v32
v_add_co_ci_u32_e32 v31, vcc_lo, s1, v8, vcc_lo
v_add_co_u32 v34, vcc_lo, s0, v20
v_lshlrev_b64 v[28:29], 1, v[28:29]
v_add_co_ci_u32_e32 v35, vcc_lo, s1, v21, vcc_lo
v_add_co_u32 v36, vcc_lo, s0, v24
v_lshlrev_b64 v[32:33], 1, v[32:33]
v_add_co_ci_u32_e32 v37, vcc_lo, s1, v25, vcc_lo
v_add_co_u32 v38, vcc_lo, s0, v28
v_add_co_ci_u32_e32 v39, vcc_lo, s1, v29, vcc_lo
v_add_co_u32 v40, vcc_lo, s0, v32
v_add_co_ci_u32_e32 v41, vcc_lo, s1, v33, vcc_lo
s_clause 0x9
global_load_dword v43, v[12:13], off
global_load_dword v44, v[14:15], off
global_load_dword v45, v[16:17], off
global_load_dword v22, v[22:23], off
global_load_dword v23, v[26:27], off
global_load_dword v26, v[30:31], off
global_load_dword v27, v[34:35], off
global_load_dword v30, v[36:37], off
global_load_dword v31, v[38:39], off
global_load_dword v34, v[40:41], off
s_load_dwordx2 s[0:1], s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v11, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v11, vcc_lo, s0, v18
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v19, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v8, vcc_lo
v_add_co_u32 v13, vcc_lo, s0, v20
v_add_co_ci_u32_e32 v14, vcc_lo, s1, v21, vcc_lo
v_add_co_u32 v15, vcc_lo, s0, v24
v_add_co_ci_u32_e32 v16, vcc_lo, s1, v25, vcc_lo
v_add_co_u32 v17, vcc_lo, s0, v28
v_add_co_ci_u32_e32 v18, vcc_lo, s1, v29, vcc_lo
v_add_co_u32 v19, vcc_lo, s0, v32
v_add_co_ci_u32_e32 v20, vcc_lo, s1, v33, vcc_lo
s_waitcnt vmcnt(9)
v_pk_add_f16 v8, v42, v43
s_waitcnt vmcnt(8)
v_pk_add_f16 v21, v42, v44
s_waitcnt vmcnt(7)
v_pk_add_f16 v24, v42, v45
s_waitcnt vmcnt(6)
v_pk_add_f16 v22, v42, v22
s_waitcnt vmcnt(5)
v_pk_add_f16 v23, v42, v23
s_waitcnt vmcnt(4)
v_pk_add_f16 v25, v42, v26
s_waitcnt vmcnt(3)
v_pk_add_f16 v26, v42, v27
s_waitcnt vmcnt(2)
v_pk_add_f16 v27, v42, v30
s_waitcnt vmcnt(1)
v_pk_add_f16 v28, v42, v31
s_waitcnt vmcnt(0)
v_pk_add_f16 v29, v42, v34
v_pk_max_f16 v8, v8, 0
v_pk_max_f16 v21, v21, 0
v_pk_max_f16 v24, v24, 0
v_pk_max_f16 v22, v22, 0
v_pk_max_f16 v23, v23, 0
v_pk_max_f16 v25, v25, 0
v_pk_max_f16 v26, v26, 0
v_pk_max_f16 v27, v27, 0
v_pk_max_f16 v28, v28, 0
v_pk_max_f16 v29, v29, 0
global_store_dword v[9:10], v8, off
global_store_dword v[0:1], v21, off
global_store_dword v[2:3], v24, off
global_store_dword v[4:5], v22, off
global_store_dword v[11:12], v23, off
global_store_dword v[6:7], v25, off
global_store_dword v[13:14], v26, off
global_store_dword v[15:16], v27, off
global_store_dword v[17:18], v28, off
global_store_dword v[19:20], v29, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_add_nn_relu_reshape_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 46
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end82:
.size tvmgen_default_fused_reshape_add_nn_relu_reshape_kernel0, .Lfunc_end82-tvmgen_default_fused_reshape_add_nn_relu_reshape_kernel0
.globl tvmgen_default_fused_reshape_add_reshape_transpose_1_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_add_reshape_transpose_1_kernel0,@function
tvmgen_default_fused_reshape_add_reshape_transpose_1_kernel0:
s_clause 0x2
s_load_dwordx2 s[2:3], s[4:5], 0x0
s_load_dwordx2 s[8:9], s[4:5], 0x8
s_load_dwordx2 s[4:5], s[4:5], 0x10
s_lshl_b32 s0, s6, 9
v_lshl_add_u32 v2, s6, 8, v0
v_lshl_add_u32 v0, v0, 1, s0
s_mov_b32 s6, 0x25800
v_cmp_gt_i32_e64 s0, 0x12c00, v2
v_cmp_gt_i32_e64 s1, s6, v0
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v2
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB83_2
v_mul_hi_i32 v1, 0x1b4e81b5, v0
v_lshrrev_b32_e32 v3, 31, v1
v_ashrrev_i32_e32 v1, 6, v1
v_add_nc_u32_e32 v3, v1, v3
v_mul_i32_i24_e32 v1, 0x258, v3
v_ashrrev_i32_e32 v4, 31, v3
v_sub_nc_u32_e32 v1, v0, v1
v_lshl_add_u32 v5, v1, 8, v3
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v6, 31, v5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s0, s4, v3
v_add_co_ci_u32_e64 v4, s0, s5, v4, s0
v_lshlrev_b64 v[5:6], 1, v[5:6]
v_add_co_u32 v5, s0, s8, v5
v_add_co_ci_u32_e64 v6, s0, s9, v6, s0
global_load_ushort v7, v[3:4], off
global_load_ushort v5, v[5:6], off
v_lshlrev_b64 v[3:4], 1, v[0:1]
v_add_co_u32 v3, s0, s2, v3
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
s_waitcnt vmcnt(0)
v_add_f16_e32 v1, v7, v5
global_store_short v[3:4], v1, off
BB83_2:
s_or_b32 exec_lo, exec_lo, s1
v_or_b32_e32 v1, 1, v0
s_xor_b32 s1, vcc_lo, -1
v_cmp_gt_i32_e64 s0, s6, v1
s_and_b32 s1, s0, s1
s_and_saveexec_b32 s0, s1
s_cbranch_execz BB83_4
v_mul_hi_i32 v3, 0x1b4e81b5, v1
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 6, v3
v_add_nc_u32_e32 v3, v3, v4
v_mul_i32_i24_e32 v4, 0x258, v3
v_sub_nc_u32_e32 v1, v1, v4
v_ashrrev_i32_e32 v4, 31, v3
v_lshl_add_u32 v5, v1, 8, v3
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v6, 31, v5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_lshlrev_b64 v[5:6], 1, v[5:6]
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
global_load_ushort v7, v[3:4], off
global_load_ushort v5, v[5:6], off
v_lshlrev_b64 v[3:4], 1, v[0:1]
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_waitcnt vmcnt(0)
v_add_f16_e32 v1, v7, v5
global_store_short v[3:4], v1, off offset:2
BB83_4:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v2, 0x10000, v2
v_add_nc_u32_e32 v1, 0x20000, v0
s_mov_b32 s6, 0x25800
v_cmp_gt_i32_e64 s0, 0x12c00, v2
v_cmp_gt_i32_e64 s1, s6, v1
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v2
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB83_6
v_mul_hi_i32 v2, 0x1b4e81b5, v1
v_lshrrev_b32_e32 v3, 31, v2
v_ashrrev_i32_e32 v2, 6, v2
v_add_nc_u32_e32 v2, v2, v3
v_mul_i32_i24_e32 v3, 0x258, v2
v_sub_nc_u32_e32 v3, v1, v3
v_lshl_add_u32 v4, v3, 8, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 1, v[2:3]
v_lshlrev_b64 v[4:5], 1, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s0, s4, v2
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
v_add_co_u32 v4, s0, s8, v4
v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
global_load_ushort v3, v[2:3], off
global_load_ushort v4, v[4:5], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_add_co_u32 v1, s0, s2, v1
v_add_co_ci_u32_e64 v2, s0, s3, v2, s0
s_waitcnt vmcnt(0)
v_add_f16_e32 v3, v3, v4
global_store_short v[1:2], v3, off
BB83_6:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v0, 0x20001, v0
s_xor_b32 s1, vcc_lo, -1
v_cmp_gt_i32_e64 s0, s6, v0
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB83_8
v_mul_hi_i32 v1, 0x1b4e81b5, v0
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v1, 6, v1
v_add_nc_u32_e32 v1, v1, v2
v_mul_i32_i24_e32 v2, 0x258, v1
v_sub_nc_u32_e32 v2, v0, v2
v_lshl_add_u32 v3, v2, 8, v1
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_lshlrev_b64 v[3:4], 1, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
global_load_ushort v2, v[1:2], off
global_load_ushort v3, v[3:4], off
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f16_e32 v2, v2, v3
global_store_short v[0:1], v2, off
BB83_8:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_add_reshape_transpose_1_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 10
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end83:
.size tvmgen_default_fused_reshape_add_reshape_transpose_1_kernel0, .Lfunc_end83-tvmgen_default_fused_reshape_add_reshape_transpose_1_kernel0
.globl tvmgen_default_fused_reshape_add_reshape_transpose_2_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_add_reshape_transpose_2_kernel0,@function
tvmgen_default_fused_reshape_add_reshape_transpose_2_kernel0:
v_lshrrev_b32_e32 v1, 4, v0
s_mov_b32 s0, 0x51eb851f
v_lshlrev_b32_e32 v3, 1, v0
v_lshl_add_u32 v1, s6, 4, v1
v_lshl_add_u32 v0, s6, 9, v3
v_mul_hi_i32 v2, v1, s0
v_mul_hi_i32 v5, v0, s0
s_clause 0x1
s_load_dwordx2 s[0:1], s[4:5], 0x10
s_load_dwordx2 s[2:3], s[4:5], 0x8
v_lshrrev_b32_e32 v4, 31, v2
v_lshrrev_b32_e32 v2, 5, v2
v_add_nc_u32_e32 v2, v2, v4
v_lshrrev_b32_e32 v4, 31, v5
v_ashrrev_i32_e32 v5, 10, v5
v_mul_lo_u32 v2, 0x64, v2
v_add_lshl_u32 v4, v5, v4, 5
v_sub_nc_u32_e32 v1, v1, v2
v_and_b32_e32 v2, 30, v3
v_lshl_add_u32 v3, v1, 8, v4
v_or_b32_e32 v1, v4, v2
v_or_b32_e32 v3, v3, v2
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_lshlrev_b64 v[3:4], 1, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_dword v2, v[1:2], off
global_load_dword v3, v[3:4], off
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_pk_add_f16 v2, v2, v3
global_store_dword v[0:1], v2, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_add_reshape_transpose_2_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end84:
.size tvmgen_default_fused_reshape_add_reshape_transpose_2_kernel0, .Lfunc_end84-tvmgen_default_fused_reshape_add_reshape_transpose_2_kernel0
.globl tvmgen_default_fused_reshape_add_reshape_transpose_3_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_add_reshape_transpose_3_kernel0,@function
tvmgen_default_fused_reshape_add_reshape_transpose_3_kernel0:
v_lshlrev_b32_e32 v0, 1, v0
s_clause 0x1
s_load_dwordx2 s[0:1], s[4:5], 0x8
s_load_dwordx2 s[2:3], s[4:5], 0x10
v_lshl_add_u32 v0, s6, 9, v0
v_mul_hi_i32 v1, 0x51eb851f, v0
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v1, 5, v1
v_add_nc_u32_e32 v1, v1, v2
v_mul_lo_u32 v2, 0x64, v1
v_sub_nc_u32_e32 v2, v0, v2
v_lshl_add_u32 v2, v2, 8, v1
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v2
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_lshlrev_b64 v[1:2], 1, v[1:2]
global_load_ushort v3, v[4:5], off
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_ushort v2, v[1:2], off
s_waitcnt vmcnt(1)
global_load_short_d16_hi v3, v[4:5], off offset:512
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_pk_add_f16 v2, v2, v3 op_sel_hi:[0,1]
global_store_dword v[0:1], v2, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_add_reshape_transpose_3_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end85:
.size tvmgen_default_fused_reshape_add_reshape_transpose_3_kernel0, .Lfunc_end85-tvmgen_default_fused_reshape_add_reshape_transpose_3_kernel0
.globl tvmgen_default_fused_reshape_add_reshape_transpose_divide_1_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_add_reshape_transpose_divide_1_kernel0,@function
tvmgen_default_fused_reshape_add_reshape_transpose_divide_1_kernel0:
v_lshrrev_b32_e32 v1, 4, v0
s_mov_b32 s0, 0x51eb851f
v_lshlrev_b32_e32 v3, 1, v0
v_lshl_add_u32 v1, s6, 4, v1
v_lshl_add_u32 v0, s6, 9, v3
s_load_dwordx2 s[6:7], s[4:5], 0x18
v_mul_hi_i32 v2, v1, s0
v_mul_hi_i32 v5, v0, s0
s_clause 0x1
s_load_dwordx2 s[0:1], s[4:5], 0x10
s_load_dwordx2 s[2:3], s[4:5], 0x8
v_lshrrev_b32_e32 v4, 31, v2
v_lshrrev_b32_e32 v2, 5, v2
v_add_nc_u32_e32 v2, v2, v4
v_lshrrev_b32_e32 v4, 31, v5
v_ashrrev_i32_e32 v5, 10, v5
v_mul_lo_u32 v2, 0x64, v2
v_add_lshl_u32 v4, v5, v4, 5
v_mov_b32_e32 v5, 0
v_sub_nc_u32_e32 v1, v1, v2
v_and_b32_e32 v2, 30, v3
v_lshl_add_u32 v3, v1, 8, v4
v_or_b32_e32 v1, v4, v2
v_or_b32_e32 v3, v3, v2
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_lshlrev_b64 v[3:4], 1, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_ushort v5, v5, s[6:7]
global_load_dword v1, v[1:2], off
global_load_dword v2, v[3:4], off
s_waitcnt vmcnt(2)
v_cvt_f32_f16_e32 v3, v5
s_waitcnt vmcnt(0)
v_pk_add_f16 v2, v1, v2
v_rcp_f32_e32 v1, v3
v_lshrrev_b32_e32 v3, 16, v2
v_cvt_f32_f16_e32 v4, v2
v_cvt_f32_f16_e32 v6, v3
v_mul_f32_e32 v4, v4, v1
v_mul_f32_e32 v1, v6, v1
v_cvt_f16_f32_e32 v4, v4
v_cvt_f16_f32_e32 v6, v1
v_ashrrev_i32_e32 v1, 31, v0
v_div_fixup_f16 v2, v4, v5, v2
v_div_fixup_f16 v3, v6, v5, v3
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_pack_b32_f16 v2, v2, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_dword v[0:1], v2, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_add_reshape_transpose_divide_1_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end86:
.size tvmgen_default_fused_reshape_add_reshape_transpose_divide_1_kernel0, .Lfunc_end86-tvmgen_default_fused_reshape_add_reshape_transpose_divide_1_kernel0
.globl tvmgen_default_fused_reshape_add_reshape_transpose_divide_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_add_reshape_transpose_divide_kernel0,@function
tvmgen_default_fused_reshape_add_reshape_transpose_divide_kernel0:
s_clause 0x3
s_load_dwordx2 s[2:3], s[4:5], 0x0
s_load_dwordx2 s[8:9], s[4:5], 0x8
s_load_dwordx2 s[10:11], s[4:5], 0x10
s_load_dwordx2 s[4:5], s[4:5], 0x18
v_lshlrev_b32_e32 v1, 1, v0
s_lshl_b32 s7, s6, 9
v_lshl_add_u32 v3, s6, 8, v0
s_mov_b32 s12, 0x25800
s_lshl_b32 s6, s6, 4
v_add_nc_u32_e32 v4, s7, v1
v_cmp_gt_i32_e64 s0, 0x12c00, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v3
v_cmp_gt_i32_e64 s1, s12, v4
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB87_2
v_lshrrev_b32_e32 v2, 4, v0
s_mov_b32 s0, 0x1b4e81b5
v_mul_hi_i32 v7, v4, s0
v_add_nc_u32_e32 v2, s6, v2
v_mul_hi_i32 v5, v2, s0
v_lshrrev_b32_e32 v6, 31, v5
v_lshrrev_b32_e32 v5, 6, v5
v_add_nc_u32_e32 v5, v5, v6
v_lshrrev_b32_e32 v6, 31, v7
v_ashrrev_i32_e32 v7, 11, v7
v_mul_lo_u32 v5, 0x258, v5
v_add_lshl_u32 v6, v7, v6, 5
v_and_b32_e32 v7, 30, v1
v_sub_nc_u32_e32 v2, v2, v5
v_or_b32_e32 v5, v7, v6
v_lshl_add_u32 v2, v2, 8, v6
v_ashrrev_i32_e32 v6, 31, v5
v_or_b32_e32 v7, v2, v7
v_lshlrev_b64 v[5:6], 1, v[5:6]
v_mov_b32_e32 v2, 0
v_ashrrev_i32_e32 v8, 31, v7
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, s0, s10, v5
global_load_ushort v2, v2, s[4:5]
v_add_co_ci_u32_e64 v6, s0, s11, v6, s0
v_lshlrev_b64 v[7:8], 1, v[7:8]
v_add_co_u32 v7, s0, s8, v7
v_add_co_ci_u32_e64 v8, s0, s9, v8, s0
global_load_ushort v5, v[5:6], off
global_load_ushort v6, v[7:8], off
s_waitcnt vmcnt(2)
v_cvt_f32_f16_e32 v7, v2
v_rcp_f32_e32 v7, v7
s_waitcnt vmcnt(0)
v_add_f16_e32 v8, v5, v6
v_cvt_f32_f16_e32 v5, v8
v_mul_f32_e32 v6, v5, v7
v_ashrrev_i32_e32 v5, 31, v4
v_cvt_f16_f32_e32 v7, v6
v_lshlrev_b64 v[5:6], 1, v[4:5]
v_div_fixup_f16 v2, v7, v2, v8
v_add_co_u32 v5, s0, s2, v5
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
global_store_short v[5:6], v2, off
BB87_2:
s_or_b32 exec_lo, exec_lo, s1
v_or_b32_e32 v2, 1, v1
s_xor_b32 s1, vcc_lo, -1
v_add_nc_u32_e32 v5, s7, v2
v_cmp_gt_i32_e64 s0, s12, v5
s_and_b32 s1, s0, s1
s_and_saveexec_b32 s0, s1
s_cbranch_execz BB87_4
v_lshrrev_b32_e32 v6, 4, v0
s_mov_b32 s1, 0x1b4e81b5
v_mov_b32_e32 v10, 0
v_mul_hi_i32 v9, v5, s1
v_add_nc_u32_e32 v6, s6, v6
s_waitcnt lgkmcnt(0)
global_load_ushort v10, v10, s[4:5]
v_mul_hi_i32 v7, v6, s1
v_lshrrev_b32_e32 v8, 31, v7
v_lshrrev_b32_e32 v7, 6, v7
v_add_nc_u32_e32 v7, v7, v8
v_lshrrev_b32_e32 v8, 31, v9
v_ashrrev_i32_e32 v9, 11, v9
v_mul_lo_u32 v7, 0x258, v7
v_add_lshl_u32 v8, v9, v8, 5
v_sub_nc_u32_e32 v6, v6, v7
v_and_b32_e32 v7, 31, v2
v_lshl_add_u32 v9, v6, 8, v8
v_or_b32_e32 v6, v7, v8
v_or_b32_e32 v8, v9, v7
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[6:7], 1, v[6:7]
v_lshlrev_b64 v[8:9], 1, v[8:9]
v_add_co_u32 v6, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_load_ushort v6, v[6:7], off
global_load_ushort v7, v[8:9], off
s_waitcnt vmcnt(2)
v_cvt_f32_f16_e32 v8, v10
v_rcp_f32_e32 v8, v8
s_waitcnt vmcnt(0)
v_add_f16_e32 v9, v6, v7
v_cvt_f32_f16_e32 v6, v9
v_mul_f32_e32 v7, v6, v8
v_ashrrev_i32_e32 v6, 31, v5
v_cvt_f16_f32_e32 v8, v7
v_lshlrev_b64 v[6:7], 1, v[5:6]
v_div_fixup_f16 v8, v8, v10, v9
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_store_short v[6:7], v8, off
BB87_4:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s7, 0x20000
v_add_nc_u32_e32 v6, 0x10000, v3
v_add_nc_u32_e32 v3, s7, v4
s_mov_b32 s12, 0x25800
s_addk_i32 s6, 0x1000
v_cmp_gt_i32_e64 s0, 0x12c00, v6
v_cmp_gt_i32_e64 s1, s12, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v6
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB87_6
v_lshrrev_b32_e32 v4, 4, v0
s_mov_b32 s0, 0x1b4e81b5
v_and_b32_e32 v1, 30, v1
v_mul_hi_i32 v8, v3, s0
v_add_nc_u32_e32 v4, s6, v4
v_mul_hi_i32 v6, v4, s0
v_lshrrev_b32_e32 v7, 31, v6
v_lshrrev_b32_e32 v6, 6, v6
v_add_nc_u32_e32 v6, v6, v7
v_lshrrev_b32_e32 v7, 31, v8
v_ashrrev_i32_e32 v8, 11, v8
v_mul_lo_u32 v6, 0x258, v6
v_add_lshl_u32 v7, v8, v7, 5
v_sub_nc_u32_e32 v4, v4, v6
v_or_b32_e32 v6, v1, v7
v_lshl_add_u32 v4, v4, 8, v7
v_ashrrev_i32_e32 v7, 31, v6
v_or_b32_e32 v8, v4, v1
v_lshlrev_b64 v[6:7], 1, v[6:7]
v_mov_b32_e32 v1, 0
v_ashrrev_i32_e32 v9, 31, v8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, s0, s10, v6
global_load_ushort v1, v1, s[4:5]
v_add_co_ci_u32_e64 v7, s0, s11, v7, s0
v_lshlrev_b64 v[8:9], 1, v[8:9]
v_add_co_u32 v8, s0, s8, v8
v_add_co_ci_u32_e64 v9, s0, s9, v9, s0
global_load_ushort v4, v[6:7], off
global_load_ushort v6, v[8:9], off
s_waitcnt vmcnt(2)
v_cvt_f32_f16_e32 v7, v1
v_rcp_f32_e32 v7, v7
s_waitcnt vmcnt(0)
v_add_f16_e32 v6, v4, v6
v_cvt_f32_f16_e32 v4, v6
v_mul_f32_e32 v7, v4, v7
v_ashrrev_i32_e32 v4, 31, v3
v_cvt_f16_f32_e32 v7, v7
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_div_fixup_f16 v1, v7, v1, v6
v_add_co_u32 v3, s0, s2, v3
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
global_store_short v[3:4], v1, off
BB87_6:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, s7, v5
s_xor_b32 s1, vcc_lo, -1
v_cmp_gt_i32_e64 s0, s12, v1
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB87_8
v_lshrrev_b32_e32 v0, 4, v0
s_mov_b32 s0, 0x1b4e81b5
v_mul_hi_i32 v5, v1, s0
v_add_nc_u32_e32 v0, s6, v0
v_mul_hi_i32 v3, v0, s0
v_lshrrev_b32_e32 v4, 31, v3
v_lshrrev_b32_e32 v3, 6, v3
v_add_nc_u32_e32 v3, v3, v4
v_lshrrev_b32_e32 v4, 31, v5
v_ashrrev_i32_e32 v5, 11, v5
v_mul_lo_u32 v3, 0x258, v3
v_add_lshl_u32 v4, v5, v4, 5
v_sub_nc_u32_e32 v0, v0, v3
v_and_b32_e32 v3, 31, v2
v_lshl_add_u32 v0, v0, 8, v4
v_or_b32_e32 v2, v3, v4
v_or_b32_e32 v4, v0, v3
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v0, 0
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_waitcnt lgkmcnt(0)
global_load_ushort v6, v0, s[4:5]
v_lshlrev_b64 v[4:5], 1, v[4:5]
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
global_load_ushort v0, v[2:3], off
global_load_ushort v2, v[4:5], off
s_waitcnt vmcnt(2)
v_cvt_f32_f16_e32 v3, v6
v_rcp_f32_e32 v3, v3
s_waitcnt vmcnt(0)
v_add_f16_e32 v4, v0, v2
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_f16_e32 v0, v4
v_mul_f32_e32 v0, v0, v3
v_cvt_f16_f32_e32 v3, v0
v_lshlrev_b64 v[0:1], 1, v[1:2]
v_div_fixup_f16 v2, v3, v6, v4
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_short v[0:1], v2, off
BB87_8:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_add_reshape_transpose_divide_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 13
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end87:
.size tvmgen_default_fused_reshape_add_reshape_transpose_divide_kernel0, .Lfunc_end87-tvmgen_default_fused_reshape_add_reshape_transpose_divide_kernel0
.globl tvmgen_default_fused_reshape_add_reshape_transpose_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_add_reshape_transpose_kernel0,@function
tvmgen_default_fused_reshape_add_reshape_transpose_kernel0:
s_clause 0x2
s_load_dwordx2 s[2:3], s[4:5], 0x0
s_load_dwordx2 s[8:9], s[4:5], 0x8
s_load_dwordx2 s[4:5], s[4:5], 0x10
v_lshlrev_b32_e32 v1, 1, v0
s_lshl_b32 s7, s6, 9
v_lshl_add_u32 v3, s6, 8, v0
s_mov_b32 s10, 0x25800
s_lshl_b32 s6, s6, 4
v_add_nc_u32_e32 v4, s7, v1
v_cmp_gt_i32_e64 s0, 0x12c00, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v3
v_cmp_gt_i32_e64 s1, s10, v4
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB88_2
v_lshrrev_b32_e32 v2, 4, v0
s_mov_b32 s0, 0x1b4e81b5
v_mul_hi_i32 v7, v4, s0
v_add_nc_u32_e32 v2, s6, v2
v_mul_hi_i32 v5, v2, s0
v_lshrrev_b32_e32 v6, 31, v5
v_lshrrev_b32_e32 v5, 6, v5
v_add_nc_u32_e32 v5, v5, v6
v_lshrrev_b32_e32 v6, 31, v7
v_ashrrev_i32_e32 v7, 11, v7
v_mul_lo_u32 v5, 0x258, v5
v_add_lshl_u32 v6, v7, v6, 5
v_and_b32_e32 v7, 30, v1
v_sub_nc_u32_e32 v2, v2, v5
v_or_b32_e32 v5, v7, v6
v_lshl_add_u32 v2, v2, 8, v6
v_ashrrev_i32_e32 v6, 31, v5
v_or_b32_e32 v7, v2, v7
v_lshlrev_b64 v[5:6], 1, v[5:6]
v_ashrrev_i32_e32 v8, 31, v7
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, s0, s4, v5
v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
v_lshlrev_b64 v[7:8], 1, v[7:8]
v_add_co_u32 v7, s0, s8, v7
v_add_co_ci_u32_e64 v8, s0, s9, v8, s0
global_load_ushort v2, v[5:6], off
global_load_ushort v7, v[7:8], off
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[5:6], 1, v[4:5]
v_add_co_u32 v5, s0, s2, v5
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
s_waitcnt vmcnt(0)
v_add_f16_e32 v2, v2, v7
global_store_short v[5:6], v2, off
BB88_2:
s_or_b32 exec_lo, exec_lo, s1
v_or_b32_e32 v2, 1, v1
s_xor_b32 s1, vcc_lo, -1
v_add_nc_u32_e32 v5, s7, v2
v_cmp_gt_i32_e64 s0, s10, v5
s_and_b32 s1, s0, s1
s_and_saveexec_b32 s0, s1
s_cbranch_execz BB88_4
v_lshrrev_b32_e32 v6, 4, v0
s_mov_b32 s1, 0x1b4e81b5
v_mul_hi_i32 v9, v5, s1
v_add_nc_u32_e32 v6, s6, v6
v_mul_hi_i32 v7, v6, s1
v_lshrrev_b32_e32 v8, 31, v7
v_lshrrev_b32_e32 v7, 6, v7
v_add_nc_u32_e32 v7, v7, v8
v_lshrrev_b32_e32 v8, 31, v9
v_ashrrev_i32_e32 v9, 11, v9
v_mul_lo_u32 v7, 0x258, v7
v_add_lshl_u32 v8, v9, v8, 5
v_sub_nc_u32_e32 v6, v6, v7
v_and_b32_e32 v7, 31, v2
v_lshl_add_u32 v9, v6, 8, v8
v_or_b32_e32 v6, v7, v8
v_or_b32_e32 v8, v9, v7
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[6:7], 1, v[6:7]
v_lshlrev_b64 v[8:9], 1, v[8:9]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_load_ushort v10, v[6:7], off
global_load_ushort v8, v[8:9], off
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[6:7], 1, v[5:6]
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_waitcnt vmcnt(0)
v_add_f16_e32 v8, v10, v8
global_store_short v[6:7], v8, off
BB88_4:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s7, 0x20000
v_add_nc_u32_e32 v6, 0x10000, v3
v_add_nc_u32_e32 v3, s7, v4
s_mov_b32 s10, 0x25800
s_addk_i32 s6, 0x1000
v_cmp_gt_i32_e64 s0, 0x12c00, v6
v_cmp_gt_i32_e64 s1, s10, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v6
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB88_6
v_lshrrev_b32_e32 v4, 4, v0
s_mov_b32 s0, 0x1b4e81b5
v_and_b32_e32 v1, 30, v1
v_mul_hi_i32 v8, v3, s0
v_add_nc_u32_e32 v4, s6, v4
v_mul_hi_i32 v6, v4, s0
v_lshrrev_b32_e32 v7, 31, v6
v_lshrrev_b32_e32 v6, 6, v6
v_add_nc_u32_e32 v6, v6, v7
v_lshrrev_b32_e32 v7, 31, v8
v_ashrrev_i32_e32 v8, 11, v8
v_mul_lo_u32 v6, 0x258, v6
v_add_lshl_u32 v7, v8, v7, 5
v_sub_nc_u32_e32 v4, v4, v6
v_or_b32_e32 v6, v1, v7
v_lshl_add_u32 v4, v4, 8, v7
v_ashrrev_i32_e32 v7, 31, v6
v_or_b32_e32 v8, v4, v1
v_lshlrev_b64 v[6:7], 1, v[6:7]
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v9, 31, v8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, s0, s4, v6
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
v_lshlrev_b64 v[8:9], 1, v[8:9]
v_add_co_u32 v8, s0, s8, v8
v_add_co_ci_u32_e64 v9, s0, s9, v9, s0
v_add_co_u32 v3, s0, s2, v3
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
global_load_ushort v1, v[6:7], off
global_load_ushort v6, v[8:9], off
s_waitcnt vmcnt(0)
v_add_f16_e32 v1, v1, v6
global_store_short v[3:4], v1, off
BB88_6:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, s7, v5
s_xor_b32 s1, vcc_lo, -1
v_cmp_gt_i32_e64 s0, s10, v1
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB88_8
v_lshrrev_b32_e32 v0, 4, v0
s_mov_b32 s0, 0x1b4e81b5
v_mul_hi_i32 v5, v1, s0
v_add_nc_u32_e32 v0, s6, v0
v_mul_hi_i32 v3, v0, s0
v_lshrrev_b32_e32 v4, 31, v3
v_lshrrev_b32_e32 v3, 6, v3
v_add_nc_u32_e32 v3, v3, v4
v_lshrrev_b32_e32 v4, 31, v5
v_ashrrev_i32_e32 v5, 11, v5
v_mul_lo_u32 v3, 0x258, v3
v_add_lshl_u32 v4, v5, v4, 5
v_sub_nc_u32_e32 v0, v0, v3
v_and_b32_e32 v3, 31, v2
v_lshl_add_u32 v0, v0, 8, v4
v_or_b32_e32 v2, v3, v4
v_or_b32_e32 v4, v0, v3
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 1, v[2:3]
v_lshlrev_b64 v[4:5], 1, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
global_load_ushort v3, v[2:3], off
global_load_ushort v4, v[4:5], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 1, v[1:2]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f16_e32 v2, v3, v4
global_store_short v[0:1], v2, off
BB88_8:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_add_reshape_transpose_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 11
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end88:
.size tvmgen_default_fused_reshape_add_reshape_transpose_kernel0, .Lfunc_end88-tvmgen_default_fused_reshape_add_reshape_transpose_kernel0
.globl tvmgen_default_fused_reshape_add_sigmoid_take_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_add_sigmoid_take_kernel0,@function
tvmgen_default_fused_reshape_add_sigmoid_take_kernel0:
s_clause 0x2
s_load_dwordx2 s[2:3], s[4:5], 0x0
s_load_dwordx2 s[6:7], s[4:5], 0x8
s_load_dwordx2 s[4:5], s[4:5], 0x10
v_lshlrev_b32_e32 v1, 1, v0
v_cmp_gt_i32_e32 vcc_lo, 0xc8, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB89_2
v_and_b32_e32 v0, 2, v1
v_lshlrev_b32_e32 v2, 1, v1
v_lshlrev_b32_e32 v0, 1, v0
v_add_nc_u32_e32 v3, 0xfa0, v2
s_waitcnt lgkmcnt(0)
global_load_ushort v0, v0, s[4:5]
global_load_ushort v3, v3, s[6:7]
s_waitcnt vmcnt(0)
v_add_f16_e32 v0, v0, v3
v_sub_f16_e32 v0, 0, v0
v_cvt_f32_f16_e32 v0, v0
v_mul_f32_e32 v0, 0x3fb8aa3b, v0
v_exp_f32_e32 v0, v0
v_cvt_f16_f32_e32 v0, v0
v_add_f16_e32 v0, 1.0, v0
v_cvt_f32_f16_e32 v3, v0
v_rcp_f32_e32 v3, v3
v_cvt_f16_f32_e32 v3, v3
v_div_fixup_f16 v0, v3, v0, 1.0
global_store_short v2, v0, s[2:3]
BB89_2:
s_or_b32 exec_lo, exec_lo, s0
v_or_b32_e32 v0, 1, v1
v_cmp_gt_i32_e64 s0, 0x190, v0
s_and_b32 s0, s0, vcc_lo
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB89_4
v_and_b32_e32 v0, 3, v0
v_lshlrev_b32_e32 v1, 1, v1
v_lshlrev_b32_e32 v0, 1, v0
v_add_nc_u32_e32 v2, 0xfa2, v1
s_waitcnt lgkmcnt(0)
global_load_ushort v0, v0, s[4:5]
global_load_ushort v2, v2, s[6:7]
s_waitcnt vmcnt(0)
v_add_f16_e32 v0, v0, v2
v_sub_f16_e32 v0, 0, v0
v_cvt_f32_f16_e32 v0, v0
v_mul_f32_e32 v0, 0x3fb8aa3b, v0
v_exp_f32_e32 v0, v0
v_cvt_f16_f32_e32 v0, v0
v_add_f16_e32 v0, 1.0, v0
v_cvt_f32_f16_e32 v2, v0
v_rcp_f32_e32 v2, v2
v_cvt_f16_f32_e32 v2, v2
v_div_fixup_f16 v0, v2, v0, 1.0
global_store_short v1, v0, s[2:3] offset:2
BB89_4:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_add_sigmoid_take_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end89:
.size tvmgen_default_fused_reshape_add_sigmoid_take_kernel0, .Lfunc_end89-tvmgen_default_fused_reshape_add_sigmoid_take_kernel0
.globl tvmgen_default_fused_reshape_add_take_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_add_take_kernel0,@function
tvmgen_default_fused_reshape_add_take_kernel0:
s_clause 0x2
s_load_dwordx2 s[2:3], s[4:5], 0x0
s_load_dwordx2 s[8:9], s[4:5], 0x8
s_load_dwordx2 s[4:5], s[4:5], 0x10
v_lshlrev_b32_e32 v1, 1, v0
v_lshl_add_u32 v2, s6, 8, v0
v_lshl_add_u32 v0, s6, 9, v1
s_movk_i32 s6, 0x23f0
v_cmp_gt_i32_e64 s0, 0x11f8, v2
v_cmp_lt_i32_e32 vcc_lo, 0x11f7, v2
v_cmp_gt_i32_e64 s1, s6, v0
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB90_2
v_mul_hi_i32 v1, 0xb21642c9, v0
v_add_nc_u32_e32 v1, v1, v0
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v1, 6, v1
v_add_nc_u32_e32 v1, v1, v2
v_mul_lo_u32 v2, 0x5c, v1
v_add_nc_u32_e32 v1, 0xb3b0, v0
v_sub_nc_u32_e32 v3, v0, v2
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_lshlrev_b64 v[3:4], 1, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, s0, s8, v1
v_add_co_ci_u32_e64 v2, s0, s9, v2, s0
v_add_co_u32 v3, s0, s4, v3
v_add_co_ci_u32_e64 v4, s0, s5, v4, s0
global_load_ushort v5, v[1:2], off
global_load_ushort v3, v[3:4], off
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[1:2], 1, v[0:1]
v_add_co_u32 v1, s0, s2, v1
v_add_co_ci_u32_e64 v2, s0, s3, v2, s0
s_waitcnt vmcnt(0)
v_add_f16_e32 v3, v3, v5
global_store_short v[1:2], v3, off
BB90_2:
s_or_b32 exec_lo, exec_lo, s1
v_or_b32_e32 v1, 1, v0
s_xor_b32 s1, vcc_lo, -1
v_cmp_gt_i32_e64 s0, s6, v1
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB90_4
v_mul_hi_i32 v2, 0xb21642c9, v1
v_add_nc_u32_e32 v2, v2, v1
v_lshrrev_b32_e32 v3, 31, v2
v_ashrrev_i32_e32 v2, 6, v2
v_add_nc_u32_e32 v2, v2, v3
v_mul_lo_u32 v3, 0x5c, v2
v_add_nc_u32_e32 v2, 0xb3b1, v0
v_sub_nc_u32_e32 v4, v1, v3
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[1:2], 1, v[2:3]
v_lshlrev_b64 v[3:4], 1, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_ushort v2, v[1:2], off
global_load_ushort v3, v[3:4], off
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f16_e32 v2, v3, v2
global_store_short v[0:1], v2, off offset:2
BB90_4:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_add_take_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 10
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end90:
.size tvmgen_default_fused_reshape_add_take_kernel0, .Lfunc_end90-tvmgen_default_fused_reshape_add_take_kernel0
.globl tvmgen_default_fused_reshape_cast_1_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_cast_1_kernel0,@function
tvmgen_default_fused_reshape_cast_1_kernel0:
v_lshlrev_b32_e32 v0, 1, v0
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_lshl_add_u32 v0, s6, 9, v0
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
global_load_dwordx2 v[2:3], v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cvt_f16_f32_e32 v3, v3
v_cvt_f16_f32_e32 v2, v2
v_pack_b32_f16 v2, v2, v3
global_store_dword v[0:1], v2, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_cast_1_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end91:
.size tvmgen_default_fused_reshape_cast_1_kernel0, .Lfunc_end91-tvmgen_default_fused_reshape_cast_1_kernel0
.globl tvmgen_default_fused_reshape_cast_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_cast_kernel0,@function
tvmgen_default_fused_reshape_cast_kernel0:
s_clause 0x1
s_load_dwordx2 s[2:3], s[4:5], 0x0
s_load_dwordx2 s[4:5], s[4:5], 0x8
v_lshlrev_b32_e32 v1, 1, v0
s_lshl_b32 s7, s6, 9
v_lshl_add_u32 v3, s6, 8, v0
s_mov_b32 s8, 0x25800
s_lshl_b32 s6, s6, 1
v_add_nc_u32_e32 v4, s7, v1
v_cmp_gt_i32_e64 s0, 0x12c00, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v3
v_cmp_gt_i32_e64 s1, s8, v4
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB92_2
v_lshrrev_b32_e32 v2, 7, v0
v_add_nc_u32_e32 v2, s6, v2
v_mul_hi_i32 v5, 0x1b4e81b5, v2
v_lshrrev_b32_e32 v6, 31, v5
v_lshrrev_b32_e32 v5, 6, v5
v_add_nc_u32_e32 v5, v5, v6
v_and_b32_e32 v6, 0xfe, v1
v_mul_lo_u32 v5, 0x258, v5
v_sub_nc_u32_e32 v2, v2, v5
v_lshl_or_b32 v5, v2, 8, v6
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, s0, s4, v5
v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
global_load_dword v2, v[5:6], off
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[5:6], 1, v[4:5]
v_add_co_u32 v5, s0, s2, v5
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
s_waitcnt vmcnt(0)
v_cvt_f16_f32_e32 v2, v2
global_store_short v[5:6], v2, off
BB92_2:
s_or_b32 exec_lo, exec_lo, s1
v_or_b32_e32 v2, 1, v1
s_xor_b32 s1, vcc_lo, -1
v_add_nc_u32_e32 v5, s7, v2
v_cmp_gt_i32_e64 s0, s8, v5
s_and_b32 s1, s0, s1
s_and_saveexec_b32 s0, s1
s_cbranch_execz BB92_4
v_lshrrev_b32_e32 v6, 7, v0
v_add_nc_u32_e32 v6, s6, v6
v_mul_hi_i32 v7, 0x1b4e81b5, v6
v_lshrrev_b32_e32 v8, 31, v7
v_ashrrev_i32_e32 v7, 6, v7
v_add_nc_u32_e32 v7, v7, v8
v_mul_lo_u32 v7, 0x258, v7
v_sub_nc_u32_e32 v6, v6, v7
v_perm_b32 v6, v6, v2, 0x6050400
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_dword v8, v[6:7], off
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[6:7], 1, v[5:6]
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_waitcnt vmcnt(0)
v_cvt_f16_f32_e32 v8, v8
global_store_short v[6:7], v8, off
BB92_4:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s7, 0x20000
v_add_nc_u32_e32 v6, 0x10000, v3
v_add_nc_u32_e32 v3, s7, v4
s_mov_b32 s8, 0x25800
s_addk_i32 s6, 0x200
v_cmp_gt_i32_e64 s0, 0x12c00, v6
v_cmp_gt_i32_e64 s1, s8, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v6
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB92_6
v_lshrrev_b32_e32 v4, 7, v0
v_and_b32_e32 v1, 0xfe, v1
v_add_nc_u32_e32 v4, s6, v4
v_mul_hi_i32 v6, 0x1b4e81b5, v4
v_lshrrev_b32_e32 v7, 31, v6
v_lshrrev_b32_e32 v6, 6, v6
v_add_nc_u32_e32 v6, v6, v7
v_mul_lo_u32 v6, 0x258, v6
v_sub_nc_u32_e32 v4, v4, v6
v_lshl_or_b32 v6, v4, 8, v1
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, s0, s4, v6
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
v_add_co_u32 v3, s0, s2, v3
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
global_load_dword v1, v[6:7], off
s_waitcnt vmcnt(0)
v_cvt_f16_f32_e32 v1, v1
global_store_short v[3:4], v1, off
BB92_6:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, s7, v5
s_xor_b32 s1, vcc_lo, -1
v_cmp_gt_i32_e64 s0, s8, v1
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB92_8
v_lshrrev_b32_e32 v0, 7, v0
v_add_nc_u32_e32 v0, s6, v0
v_mul_hi_i32 v3, 0x1b4e81b5, v0
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 6, v3
v_add_nc_u32_e32 v3, v3, v4
v_mul_lo_u32 v3, 0x258, v3
v_sub_nc_u32_e32 v0, v0, v3
v_perm_b32 v2, v0, v2, 0x6050400
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_dword v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 1, v[1:2]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cvt_f16_f32_e32 v2, v3
global_store_short v[0:1], v2, off
BB92_8:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_cast_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 9
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end92:
.size tvmgen_default_fused_reshape_cast_kernel0, .Lfunc_end92-tvmgen_default_fused_reshape_cast_kernel0
.globl tvmgen_default_fused_reshape_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_kernel0,@function
tvmgen_default_fused_reshape_kernel0:
s_clause 0x1
s_load_dwordx2 s[2:3], s[4:5], 0x0
s_load_dwordx2 s[4:5], s[4:5], 0x8
v_lshlrev_b32_e32 v1, 1, v0
s_lshl_b32 s7, s6, 9
v_lshl_add_u32 v3, s6, 8, v0
s_mov_b32 s8, 0x25800
s_lshl_b32 s6, s6, 1
v_add_nc_u32_e32 v4, s7, v1
v_cmp_gt_i32_e64 s0, 0x12c00, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v3
v_cmp_gt_i32_e64 s1, s8, v4
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB93_2
v_lshrrev_b32_e32 v2, 7, v0
v_add_nc_u32_e32 v2, s6, v2
v_mul_hi_i32 v5, 0x1b4e81b5, v2
v_lshrrev_b32_e32 v6, 31, v5
v_lshrrev_b32_e32 v5, 6, v5
v_add_nc_u32_e32 v5, v5, v6
v_and_b32_e32 v6, 0xfe, v1
v_mul_lo_u32 v5, 0x258, v5
v_sub_nc_u32_e32 v2, v2, v5
v_lshl_or_b32 v5, v2, 8, v6
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 1, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, s0, s4, v5
v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
global_load_ushort v2, v[5:6], off
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[5:6], 1, v[4:5]
v_add_co_u32 v5, s0, s2, v5
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
s_waitcnt vmcnt(0)
global_store_short v[5:6], v2, off
BB93_2:
s_or_b32 exec_lo, exec_lo, s1
v_or_b32_e32 v2, 1, v1
s_xor_b32 s1, vcc_lo, -1
v_add_nc_u32_e32 v5, s7, v2
v_cmp_gt_i32_e64 s0, s8, v5
s_and_b32 s1, s0, s1
s_and_saveexec_b32 s0, s1
s_cbranch_execz BB93_4
v_lshrrev_b32_e32 v6, 7, v0
v_add_nc_u32_e32 v6, s6, v6
v_mul_hi_i32 v7, 0x1b4e81b5, v6
v_lshrrev_b32_e32 v8, 31, v7
v_ashrrev_i32_e32 v7, 6, v7
v_add_nc_u32_e32 v7, v7, v8
v_mul_lo_u32 v7, 0x258, v7
v_sub_nc_u32_e32 v6, v6, v7
v_perm_b32 v6, v6, v2, 0x6050400
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 1, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_ushort v8, v[6:7], off
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[6:7], 1, v[5:6]
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_short v[6:7], v8, off
BB93_4:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s7, 0x20000
v_add_nc_u32_e32 v6, 0x10000, v3
v_add_nc_u32_e32 v3, s7, v4
s_mov_b32 s8, 0x25800
s_addk_i32 s6, 0x200
v_cmp_gt_i32_e64 s0, 0x12c00, v6
v_cmp_gt_i32_e64 s1, s8, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v6
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB93_6
v_lshrrev_b32_e32 v4, 7, v0
v_and_b32_e32 v1, 0xfe, v1
v_add_nc_u32_e32 v4, s6, v4
v_mul_hi_i32 v6, 0x1b4e81b5, v4
v_lshrrev_b32_e32 v7, 31, v6
v_lshrrev_b32_e32 v6, 6, v6
v_add_nc_u32_e32 v6, v6, v7
v_mul_lo_u32 v6, 0x258, v6
v_sub_nc_u32_e32 v4, v4, v6
v_lshl_or_b32 v6, v4, 8, v1
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_lshlrev_b64 v[6:7], 1, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, s0, s4, v6
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
v_add_co_u32 v3, s0, s2, v3
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
global_load_ushort v1, v[6:7], off
s_waitcnt vmcnt(0)
global_store_short v[3:4], v1, off
BB93_6:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, s7, v5
s_xor_b32 s1, vcc_lo, -1
v_cmp_gt_i32_e64 s0, s8, v1
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB93_8
v_lshrrev_b32_e32 v0, 7, v0
v_add_nc_u32_e32 v0, s6, v0
v_mul_hi_i32 v3, 0x1b4e81b5, v0
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 6, v3
v_add_nc_u32_e32 v3, v3, v4
v_mul_lo_u32 v3, 0x258, v3
v_sub_nc_u32_e32 v0, v0, v3
v_perm_b32 v2, v0, v2, 0x6050400
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_ushort v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 1, v[1:2]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_short v[0:1], v3, off
BB93_8:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 9
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end93:
.size tvmgen_default_fused_reshape_kernel0, .Lfunc_end93-tvmgen_default_fused_reshape_kernel0
.globl tvmgen_default_fused_reshape_squeeze_reshape_repeat_reshape_zeros_where_kernel0
.p2align 8
.type tvmgen_default_fused_reshape_squeeze_reshape_repeat_reshape_zeros_where_kernel0,@function
tvmgen_default_fused_reshape_squeeze_reshape_repeat_reshape_zeros_where_kernel0:
v_lshl_add_u32 v0, s6, 8, v0
v_cmp_gt_i32_e32 vcc_lo, 0x12c0, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB94_2
v_mul_hi_i32 v1, 0x1b4e81b5, v0
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_lshrrev_b32_e32 v2, 31, v1
v_ashrrev_i32_e32 v1, 6, v1
v_add_nc_u32_e32 v1, v1, v2
v_mul_lo_u32 v1, 0x258, v1
v_sub_nc_u32_e32 v1, v0, v1
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
global_load_dword v2, v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt vmcnt(0)
v_cmp_lg_f32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, 0, 0xff800000, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_dword v[0:1], v2, off
BB94_2:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_reshape_squeeze_reshape_repeat_reshape_zeros_where_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end94:
.size tvmgen_default_fused_reshape_squeeze_reshape_repeat_reshape_zeros_where_kernel0, .Lfunc_end94-tvmgen_default_fused_reshape_squeeze_reshape_repeat_reshape_zeros_where_kernel0
.globl tvmgen_default_fused_strided_slice_add_divide_multiply_expand_dims_divide_strided_slice_sin_str_dbf4827b0a4481cc__kernel0
.p2align 8
.type tvmgen_default_fused_strided_slice_add_divide_multiply_expand_dims_divide_strided_slice_sin_str_dbf4827b0a4481cc__kernel0,@function
tvmgen_default_fused_strided_slice_add_divide_multiply_expand_dims_divide_strided_slice_sin_str_dbf4827b0a4481cc__kernel0:
s_clause 0x3
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[8:9], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[14:15], s[4:5], 0x18
v_and_b32_e32 v2, 0x3fe, v0
v_and_b32_e32 v1, 1, v0
v_lshl_or_b32 v4, v0, 2, 4
v_and_b32_e32 v3, 0x7e, v0
v_mov_b32_e32 v6, 0
v_lshlrev_b32_e32 v5, 2, v2
v_cmp_eq_u32_e64 s1, 1, v1
v_lshrrev_b32_e32 v8, 7, v0
v_lshlrev_b32_e32 v7, 2, v3
v_cmp_gt_i32_e64 s0, 0x80, v0
v_lshl_add_u32 v0, s6, 8, v0
s_mov_b32 s13, 0
s_mov_b32 s5, 0x51eb851f
s_mov_b32 s16, 0x358637bd
s_mov_b32 s17, 0x40c90fdb
s_brev_b32 s18, -2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v4
s_brev_b32 s19, 18
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v5
s_mov_b32 s20, 0x800000
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v7
v_or_b32_e32 v7, 24, v8
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_mov_b32 s21, 0x7fffff
s_mov_b32 s22, 0xfe5163ab
s_mov_b32 s23, 0x3c439041
s_mov_b32 s24, 0xdb629599
s_mov_b32 s25, 0xf534ddc0
s_mov_b32 s26, 0xfc2757d1
s_mov_b32 s27, 0x4e441529
s_mov_b32 s28, 0xa2f9836e
s_movk_i32 s29, 0xff88
s_movk_i32 s30, 0xffe0
s_mov_b32 s31, 0xff800000
s_movk_i32 s33, 0xf000
s_mov_b32 s34, 0x3fc90fda
s_mov_b32 s35, 0x3fc90000
s_mov_b32 s36, 0x39fda000
s_mov_b32 s37, 0x33000000
s_mov_b32 s38, 0x33a22168
s_mov_b32 s39, 0x3f22f983
s_mov_b32 s40, 0xbfc90fda
s_mov_b32 s41, 0xb3a22168
s_mov_b32 s42, 0x33a22000
s_mov_b32 s43, 0x2c340000
s_mov_b32 s44, 0xa7c234c4
s_mov_b32 s45, 0xb94c1982
s_mov_b32 s46, 0x37d75334
s_brev_b32 s47, 1
s_mov_b32 s48, 0
s_branch BB95_6
BB95_1:
s_or_b32 exec_lo, exec_lo, s2
v_mul_f32_e32 v13, v11, v11
v_and_b32_e32 v16, 1, v12
v_lshlrev_b32_e32 v12, 30, v12
v_xor_b32_e32 v9, v10, v9
v_fma_f32 v14, v13, s45, 0x3c0881c4
v_fma_f32 v15, v13, s46, 0xbab64f3b
v_cmp_eq_u32_e32 vcc_lo, 0, v16
v_and_b32_e32 v12, s47, v12
v_fmaak_f32 v14, v13, v14, 0xbe2aaa9d
v_fmaak_f32 v15, v13, v15, 0x3d2aabf7
v_mul_f32_e32 v14, v13, v14
v_fmaak_f32 v15, v13, v15, 0xbf000004
v_fmac_f32_e32 v11, v11, v14
v_fma_f32 v13, v13, v15, 1.0
v_cndmask_b32_e32 v11, v13, v11, vcc_lo
v_xor3_b32 v11, v9, v12, v11
BB95_2:
s_or_b32 exec_lo, exec_lo, s12
BB95_3:
s_or_b32 exec_lo, exec_lo, s7
v_ashrrev_i32_e32 v9, 31, v8
v_cmp_class_f32_e64 vcc_lo, v10, 0x1f8
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_cndmask_b32_e32 v10, 0x7fc00000, v11, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_store_dword v[8:9], v10, off
BB95_4:
s_or_b32 exec_lo, exec_lo, s49
BB95_5:
s_add_i32 s48, s48, 0x10000
s_addk_i32 s6, 0x100
s_cmp_eq_u32 s48, 0x30000
s_cbranch_scc1 BB95_34
BB95_6:
s_cmpk_lt_i32 s6, 0x258
s_cbranch_scc0 BB95_5
v_add_nc_u32_e32 v8, s48, v0
v_cmp_gt_i32_e32 vcc_lo, 0x25800, v8
s_and_saveexec_b32 s49, vcc_lo
s_cbranch_execz BB95_4
s_mul_hi_i32 s50, s6, s5
s_and_saveexec_b32 s2, s0
s_xor_b32 s51, exec_lo, s2
s_cbranch_execz BB95_22
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[2:3], s[6:7], 2
s_add_u32 s2, s14, s2
s_addc_u32 s3, s15, s3
s_lshr_b32 s4, s50, 31
s_ashr_i32 s7, s50, 3
s_add_i32 s4, s7, s4
s_mul_i32 s4, s4, 25
s_sub_i32 s4, s6, s4
s_add_i32 s12, s4, 0x23f
s_lshl_b64 s[52:53], s[12:13], 2
s_add_u32 s52, s14, s52
s_addc_u32 s53, s15, s53
s_clause 0x1
s_load_dword s4, s[52:53], 0x0
s_load_dword s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v9, s4, s16
v_div_scale_f32 v10, s3, v9, v9, s2
v_rcp_f32_e32 v11, v10
v_fma_f32 v12, -v10, v11, 1.0
v_fmac_f32_e32 v11, v12, v11
v_div_scale_f32 v12, vcc_lo, s2, v9, s2
v_mul_f32_e32 v13, v12, v11
v_fma_f32 v14, v13, -v10, v12
v_fmac_f32_e32 v13, v14, v11
v_fmac_f32_e64 v12, -v10, v13
v_div_fmas_f32 v10, v12, v11, v13
v_div_fixup_f32 v9, v10, v9, s2
v_mul_f32_e32 v9, s17, v9
s_and_saveexec_b32 s2, s1
s_xor_b32 s7, exec_lo, s2
s_cbranch_execz BB95_15
global_load_dword v10, v[1:2], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v11, s2, v10, v10, v9
v_div_scale_f32 v14, vcc_lo, v9, v10, v9
v_rcp_f32_e32 v12, v11
v_fma_f32 v13, -v11, v12, 1.0
v_fmac_f32_e32 v12, v13, v12
v_mul_f32_e32 v13, v14, v12
v_fma_f32 v15, v13, -v11, v14
v_fmac_f32_e32 v13, v15, v12
v_fmac_f32_e64 v14, -v11, v13
v_div_fmas_f32 v11, v14, v12, v13
v_div_fixup_f32 v9, v11, v10, v9
v_and_b32_e32 v10, s18, v9
v_cmp_nlt_f32_e64 s2, |v9|, s19
s_and_saveexec_b32 s3, s2
s_xor_b32 s12, exec_lo, s3
s_cbranch_execz BB95_12
v_and_or_b32 v9, v10, s21, s20
v_lshrrev_b32_e32 v11, 23, v10
v_mul_hi_u32 v12, v9, s22
v_mul_lo_u32 v13, v9, s23
v_mul_hi_u32 v14, v9, s23
v_mul_lo_u32 v15, v9, s24
v_mul_hi_u32 v16, v9, s24
v_mul_lo_u32 v17, v9, s25
v_mul_hi_u32 v18, v9, s25
v_mul_lo_u32 v19, v9, s26
v_mul_hi_u32 v20, v9, s27
v_add_co_u32 v12, vcc_lo, v13, v12
v_mul_lo_u32 v21, v9, s28
v_add_co_ci_u32_e32 v13, vcc_lo, v15, v14, vcc_lo
v_mul_hi_u32 v14, v9, s26
v_mul_lo_u32 v15, v9, s27
v_add_co_ci_u32_e32 v16, vcc_lo, v17, v16, vcc_lo
v_mul_hi_u32 v22, v9, s28
v_add_co_ci_u32_e32 v17, vcc_lo, v19, v18, vcc_lo
v_add_nc_u32_e32 v11, s29, v11
v_mul_lo_u32 v9, v9, s22
v_add_co_ci_u32_e32 v14, vcc_lo, v15, v14, vcc_lo
v_add_co_ci_u32_e32 v15, vcc_lo, v21, v20, vcc_lo
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v22, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 31, v11
v_cndmask_b32_e64 v19, 0, s30, vcc_lo
v_cndmask_b32_e32 v18, v18, v15, vcc_lo
v_cndmask_b32_e32 v15, v15, v14, vcc_lo
v_cndmask_b32_e32 v14, v14, v17, vcc_lo
v_cndmask_b32_e32 v17, v17, v16, vcc_lo
v_add_nc_u32_e32 v11, v19, v11
v_cndmask_b32_e32 v16, v16, v13, vcc_lo
v_cndmask_b32_e32 v13, v13, v12, vcc_lo
v_cndmask_b32_e32 v9, v12, v9, vcc_lo
v_cmp_lt_u32_e64 s2, 31, v11
v_cndmask_b32_e64 v19, 0, s30, s2
v_cndmask_b32_e64 v18, v18, v15, s2
v_cndmask_b32_e64 v15, v15, v14, s2
v_cndmask_b32_e64 v14, v14, v17, s2
v_cndmask_b32_e64 v17, v17, v16, s2
v_add_nc_u32_e32 v11, v19, v11
v_cndmask_b32_e64 v16, v16, v13, s2
v_cndmask_b32_e64 v9, v13, v9, s2
v_cmp_lt_u32_e64 s3, 31, v11
v_cndmask_b32_e64 v19, 0, s30, s3
v_cndmask_b32_e64 v18, v18, v15, s3
v_cndmask_b32_e64 v15, v15, v14, s3
v_cndmask_b32_e64 v14, v14, v17, s3
v_cndmask_b32_e64 v17, v17, v16, s3
v_add_nc_u32_e32 v11, v19, v11
v_cndmask_b32_e64 v9, v16, v9, s3
v_cmp_lt_u32_e64 s4, 31, v11
v_cndmask_b32_e64 v19, 0, s30, s4
v_cndmask_b32_e64 v12, v15, v14, s4
v_cndmask_b32_e64 v18, v18, v15, s4
v_cndmask_b32_e64 v14, v14, v17, s4
v_cndmask_b32_e64 v9, v17, v9, s4
v_add_nc_u32_e32 v11, v19, v11
v_sub_nc_u32_e32 v15, 32, v11
v_cmp_eq_u32_e32 vcc_lo, 0, v11
v_alignbit_b32 v13, v18, v12, v15
v_alignbit_b32 v19, v12, v14, v15
v_alignbit_b32 v15, v14, v9, v15
v_cndmask_b32_e32 v11, v13, v18, vcc_lo
v_cndmask_b32_e32 v12, v19, v12, vcc_lo
v_cndmask_b32_e32 v14, v15, v14, vcc_lo
v_bfe_i32 v16, v11, 29, 1
v_alignbit_b32 v13, v11, v12, 30
v_alignbit_b32 v12, v12, v14, 30
v_alignbit_b32 v9, v14, v9, 30
v_xor_b32_e32 v13, v16, v13
v_xor_b32_e32 v12, v16, v12
v_xor_b32_e32 v9, v16, v9
v_lshrrev_b32_e32 v16, 29, v11
v_ffbh_u32_e32 v15, v13
v_cmp_ne_u32_e32 vcc_lo, 0, v13
v_cndmask_b32_e32 v15, 32, v15, vcc_lo
v_sub_nc_u32_e32 v14, 31, v15
v_alignbit_b32 v13, v13, v12, v14
v_alignbit_b32 v9, v12, v9, v14
v_lshlrev_b32_e32 v12, 31, v16
v_mad_i32_i24 v16, v15, s31, 0.5
v_alignbit_b32 v14, v13, v9, 9
v_lshrrev_b32_e32 v13, 9, v13
v_ffbh_u32_e32 v17, v14
v_cmp_ne_u32_e32 vcc_lo, 0, v14
v_or3_b32 v13, v16, v12, v13
v_cndmask_b32_e32 v16, 32, v17, vcc_lo
v_and_b32_e32 v17, s33, v13
v_mul_f32_e32 v18, s34, v13
v_sub_nc_u32_e32 v19, 31, v16
v_add_nc_u32_e32 v15, v16, v15
v_fma_f32 v18, v17, s35, -v18
v_mul_f32_e32 v16, s38, v13
v_alignbit_b32 v9, v14, v9, v19
v_sub_f32_e32 v14, v13, v17
v_fmac_f32_e32 v18, s36, v17
v_mad_i32_i24 v15, v15, s31, s37
v_lshrrev_b32_e32 v9, 9, v9
v_fmac_f32_e32 v18, s35, v14
v_or3_b32 v9, v15, v12, v9
v_bfe_u32 v12, v11, 29, 1
v_fmac_f32_e32 v18, s36, v14
v_lshrrev_b32_e32 v11, 30, v11
v_fmac_f32_e32 v16, s34, v9
v_add_nc_u32_e32 v11, v12, v11
v_add_f32_e32 v9, v18, v16
v_fmac_f32_e32 v9, s34, v13
BB95_12:
s_or_saveexec_b32 s2, s12
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execz BB95_14
v_mul_f32_e32 v9, s39, v10
v_rndne_f32_e32 v11, v9
v_and_b32_e32 v9, s33, v11
v_mul_f32_e32 v12, s40, v11
v_fma_f32 v13, s40, v11, v10
v_mul_f32_e32 v16, s41, v11
v_sub_f32_e32 v14, v11, v9
v_fmac_f32_e32 v12, s35, v9
v_sub_f32_e32 v15, v10, v13
v_fmac_f32_e32 v16, s42, v9
v_fmac_f32_e32 v12, s36, v9
v_fmac_f32_e32 v15, s40, v11
v_fmac_f32_e32 v16, s43, v9
v_fmac_f32_e32 v12, s35, v14
v_fmac_f32_e32 v16, s42, v14
v_fmac_f32_e32 v12, s36, v14
v_fmac_f32_e32 v16, s43, v14
v_sub_f32_e32 v12, v15, v12
v_add_f32_e32 v12, v13, v12
v_fma_f32 v9, s41, v11, v12
v_sub_f32_e32 v12, v12, v9
v_fmac_f32_e32 v12, s41, v11
v_sub_f32_e32 v12, v12, v16
v_add_f32_e32 v9, v9, v12
v_fmac_f32_e32 v9, s44, v11
v_cvt_i32_f32_e32 v11, v11
BB95_14:
s_or_b32 exec_lo, exec_lo, s2
v_mul_f32_e32 v12, v9, v9
v_and_b32_e32 v15, 1, v11
v_lshlrev_b32_e32 v11, 30, v11
v_fma_f32 v13, v12, s45, 0x3c0881c4
v_fma_f32 v14, v12, s46, 0xbab64f3b
v_cmp_eq_u32_e32 vcc_lo, 0, v15
v_and_b32_e32 v11, s47, v11
v_fmaak_f32 v13, v12, v13, 0xbe2aaa9d
v_fmaak_f32 v14, v12, v14, 0x3d2aabf7
v_mul_f32_e32 v13, v12, v13
v_fmaak_f32 v14, v12, v14, 0xbf000004
v_fmac_f32_e32 v9, v9, v13
v_fma_f32 v12, v12, v14, 1.0
v_cndmask_b32_e64 v9, -v9, v12, vcc_lo
v_xor_b32_e32 v11, v11, v9
BB95_15:
s_or_saveexec_b32 s7, s7
s_xor_b32 exec_lo, exec_lo, s7
s_cbranch_execz BB95_21
global_load_dword v10, v[3:4], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v11, s2, v10, v10, v9
v_div_scale_f32 v14, vcc_lo, v9, v10, v9
v_rcp_f32_e32 v12, v11
v_fma_f32 v13, -v11, v12, 1.0
v_fmac_f32_e32 v12, v13, v12
v_mul_f32_e32 v13, v14, v12
v_fma_f32 v15, v13, -v11, v14
v_fmac_f32_e32 v13, v15, v12
v_fmac_f32_e64 v14, -v11, v13
v_div_fmas_f32 v11, v14, v12, v13
v_div_fixup_f32 v9, v11, v10, v9
v_and_b32_e32 v10, s18, v9
v_cmp_nlt_f32_e64 s2, |v9|, s19
s_and_saveexec_b32 s3, s2
s_xor_b32 s12, exec_lo, s3
s_cbranch_execz BB95_18
v_and_or_b32 v11, v10, s21, s20
v_lshrrev_b32_e32 v12, 23, v10
v_mul_hi_u32 v13, v11, s22
v_mul_lo_u32 v14, v11, s23
v_mul_hi_u32 v15, v11, s23
v_mul_lo_u32 v16, v11, s24
v_mul_hi_u32 v17, v11, s24
v_mul_lo_u32 v18, v11, s25
v_mul_hi_u32 v19, v11, s25
v_mul_lo_u32 v20, v11, s26
v_mul_hi_u32 v21, v11, s27
v_add_co_u32 v13, vcc_lo, v14, v13
v_mul_lo_u32 v22, v11, s28
v_add_co_ci_u32_e32 v14, vcc_lo, v16, v15, vcc_lo
v_mul_hi_u32 v15, v11, s26
v_mul_lo_u32 v16, v11, s27
v_add_co_ci_u32_e32 v17, vcc_lo, v18, v17, vcc_lo
v_mul_hi_u32 v23, v11, s28
v_add_co_ci_u32_e32 v18, vcc_lo, v20, v19, vcc_lo
v_add_nc_u32_e32 v12, s29, v12
v_mul_lo_u32 v11, v11, s22
v_add_co_ci_u32_e32 v15, vcc_lo, v16, v15, vcc_lo
v_add_co_ci_u32_e32 v16, vcc_lo, v22, v21, vcc_lo
v_add_co_ci_u32_e32 v19, vcc_lo, 0, v23, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 31, v12
v_cndmask_b32_e64 v20, 0, s30, vcc_lo
v_cndmask_b32_e32 v19, v19, v16, vcc_lo
v_cndmask_b32_e32 v16, v16, v15, vcc_lo
v_cndmask_b32_e32 v15, v15, v18, vcc_lo
v_cndmask_b32_e32 v18, v18, v17, vcc_lo
v_add_nc_u32_e32 v12, v20, v12
v_cndmask_b32_e32 v17, v17, v14, vcc_lo
v_cndmask_b32_e32 v14, v14, v13, vcc_lo
v_cndmask_b32_e32 v11, v13, v11, vcc_lo
v_cmp_lt_u32_e64 s2, 31, v12
v_cndmask_b32_e64 v20, 0, s30, s2
v_cndmask_b32_e64 v19, v19, v16, s2
v_cndmask_b32_e64 v16, v16, v15, s2
v_cndmask_b32_e64 v15, v15, v18, s2
v_cndmask_b32_e64 v18, v18, v17, s2
v_add_nc_u32_e32 v12, v20, v12
v_cndmask_b32_e64 v17, v17, v14, s2
v_cndmask_b32_e64 v11, v14, v11, s2
v_cmp_lt_u32_e64 s3, 31, v12
v_cndmask_b32_e64 v20, 0, s30, s3
v_cndmask_b32_e64 v19, v19, v16, s3
v_cndmask_b32_e64 v16, v16, v15, s3
v_cndmask_b32_e64 v15, v15, v18, s3
v_cndmask_b32_e64 v18, v18, v17, s3
v_add_nc_u32_e32 v12, v20, v12
v_cndmask_b32_e64 v11, v17, v11, s3
v_cmp_lt_u32_e64 s4, 31, v12
v_cndmask_b32_e64 v20, 0, s30, s4
v_cndmask_b32_e64 v13, v16, v15, s4
v_cndmask_b32_e64 v19, v19, v16, s4
v_cndmask_b32_e64 v15, v15, v18, s4
v_cndmask_b32_e64 v11, v18, v11, s4
v_add_nc_u32_e32 v12, v20, v12
v_sub_nc_u32_e32 v16, 32, v12
v_cmp_eq_u32_e32 vcc_lo, 0, v12
v_alignbit_b32 v14, v19, v13, v16
v_alignbit_b32 v20, v13, v15, v16
v_alignbit_b32 v16, v15, v11, v16
v_cndmask_b32_e32 v12, v14, v19, vcc_lo
v_cndmask_b32_e32 v13, v20, v13, vcc_lo
v_cndmask_b32_e32 v15, v16, v15, vcc_lo
v_bfe_i32 v17, v12, 29, 1
v_alignbit_b32 v14, v12, v13, 30
v_alignbit_b32 v13, v13, v15, 30
v_alignbit_b32 v11, v15, v11, 30
v_xor_b32_e32 v14, v17, v14
v_xor_b32_e32 v13, v17, v13
v_xor_b32_e32 v11, v17, v11
v_lshrrev_b32_e32 v17, 29, v12
v_ffbh_u32_e32 v16, v14
v_cmp_ne_u32_e32 vcc_lo, 0, v14
v_cndmask_b32_e32 v16, 32, v16, vcc_lo
v_sub_nc_u32_e32 v15, 31, v16
v_alignbit_b32 v14, v14, v13, v15
v_alignbit_b32 v11, v13, v11, v15
v_lshlrev_b32_e32 v13, 31, v17
v_mad_i32_i24 v17, v16, s31, 0.5
v_alignbit_b32 v15, v14, v11, 9
v_lshrrev_b32_e32 v14, 9, v14
v_ffbh_u32_e32 v18, v15
v_cmp_ne_u32_e32 vcc_lo, 0, v15
v_or3_b32 v14, v17, v13, v14
v_cndmask_b32_e32 v17, 32, v18, vcc_lo
v_and_b32_e32 v18, s33, v14
v_mul_f32_e32 v19, s34, v14
v_sub_nc_u32_e32 v20, 31, v17
v_add_nc_u32_e32 v16, v17, v16
v_fma_f32 v19, v18, s35, -v19
v_mul_f32_e32 v17, s38, v14
v_alignbit_b32 v11, v15, v11, v20
v_sub_f32_e32 v15, v14, v18
v_fmac_f32_e32 v19, s36, v18
v_mad_i32_i24 v16, v16, s31, s37
v_lshrrev_b32_e32 v11, 9, v11
v_fmac_f32_e32 v19, s35, v15
v_or3_b32 v11, v16, v13, v11
v_bfe_u32 v13, v12, 29, 1
v_fmac_f32_e32 v19, s36, v15
v_lshrrev_b32_e32 v12, 30, v12
v_fmac_f32_e32 v17, s34, v11
v_add_nc_u32_e32 v12, v13, v12
v_add_f32_e32 v11, v19, v17
v_fmac_f32_e32 v11, s34, v14
BB95_18:
s_or_saveexec_b32 s2, s12
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execz BB95_20
v_mul_f32_e32 v11, s39, v10
v_rndne_f32_e32 v12, v11
v_and_b32_e32 v11, s33, v12
v_mul_f32_e32 v13, s40, v12
v_fma_f32 v14, s40, v12, v10
v_mul_f32_e32 v17, s41, v12
v_sub_f32_e32 v15, v12, v11
v_fmac_f32_e32 v13, s35, v11
v_sub_f32_e32 v16, v10, v14
v_fmac_f32_e32 v17, s42, v11
v_fmac_f32_e32 v13, s36, v11
v_fmac_f32_e32 v16, s40, v12
v_fmac_f32_e32 v17, s43, v11
v_fmac_f32_e32 v13, s35, v15
v_fmac_f32_e32 v17, s42, v15
v_fmac_f32_e32 v13, s36, v15
v_fmac_f32_e32 v17, s43, v15
v_sub_f32_e32 v13, v16, v13
v_add_f32_e32 v13, v14, v13
v_fma_f32 v11, s41, v12, v13
v_sub_f32_e32 v13, v13, v11
v_fmac_f32_e32 v13, s41, v12
v_sub_f32_e32 v13, v13, v17
v_add_f32_e32 v11, v11, v13
v_fmac_f32_e32 v11, s44, v12
v_cvt_i32_f32_e32 v12, v12
BB95_20:
s_or_b32 exec_lo, exec_lo, s2
v_mul_f32_e32 v13, v11, v11
v_and_b32_e32 v16, 1, v12
v_lshlrev_b32_e32 v12, 30, v12
v_xor_b32_e32 v9, v10, v9
v_fma_f32 v14, v13, s45, 0x3c0881c4
v_fma_f32 v15, v13, s46, 0xbab64f3b
v_cmp_eq_u32_e32 vcc_lo, 0, v16
v_and_b32_e32 v12, s47, v12
v_fmaak_f32 v14, v13, v14, 0xbe2aaa9d
v_fmaak_f32 v15, v13, v15, 0x3d2aabf7
v_mul_f32_e32 v14, v13, v14
v_fmaak_f32 v15, v13, v15, 0xbf000004
v_fmac_f32_e32 v11, v11, v14
v_fma_f32 v13, v13, v15, 1.0
v_cndmask_b32_e32 v11, v13, v11, vcc_lo
v_xor3_b32 v11, v9, v12, v11
BB95_21:
s_or_b32 exec_lo, exec_lo, s7
BB95_22:
s_or_saveexec_b32 s7, s51
s_xor_b32 exec_lo, exec_lo, s7
s_cbranch_execz BB95_3
s_lshr_b32 s2, s50, 31
s_ashr_i32 s3, s50, 3
s_add_i32 s2, s3, s2
s_mul_i32 s2, s2, 25
s_sub_i32 s3, s6, s2
v_add_nc_u32_e32 v9, s3, v7
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 2
v_mul_hi_u32 v9, v9, s5
s_add_u32 s2, s10, s2
s_addc_u32 s3, s11, s3
s_load_dword s2, s[2:3], 0x60
v_lshrrev_b32_e32 v9, 3, v9
v_mul_lo_u32 v9, 0xffffffe7, v9
v_add3_u32 v9, v7, s6, v9
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s10, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
global_load_dword v9, v[9:10], off
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v10, s2, s16
s_waitcnt vmcnt(0)
v_div_scale_f32 v11, s2, v10, v10, v9
v_rcp_f32_e32 v12, v11
v_fma_f32 v13, -v11, v12, 1.0
v_fmac_f32_e32 v12, v13, v12
v_div_scale_f32 v13, vcc_lo, v9, v10, v9
v_mul_f32_e32 v14, v13, v12
v_fma_f32 v15, v14, -v11, v13
v_fmac_f32_e32 v14, v15, v12
v_fmac_f32_e64 v13, -v11, v14
v_div_fmas_f32 v11, v13, v12, v14
v_div_fixup_f32 v9, v11, v10, v9
v_mul_f32_e32 v9, s17, v9
s_and_saveexec_b32 s2, s1
s_xor_b32 s12, exec_lo, s2
s_cbranch_execz BB95_29
global_load_dword v10, v[5:6], off offset:4
s_waitcnt vmcnt(0)
v_div_scale_f32 v11, s2, v10, v10, v9
v_div_scale_f32 v14, vcc_lo, v9, v10, v9
v_rcp_f32_e32 v12, v11
v_fma_f32 v13, -v11, v12, 1.0
v_fmac_f32_e32 v12, v13, v12
v_mul_f32_e32 v13, v14, v12
v_fma_f32 v15, v13, -v11, v14
v_fmac_f32_e32 v13, v15, v12
v_fmac_f32_e64 v14, -v11, v13
v_div_fmas_f32 v11, v14, v12, v13
v_div_fixup_f32 v9, v11, v10, v9
v_and_b32_e32 v10, s18, v9
v_cmp_nlt_f32_e64 s2, |v9|, s19
s_and_saveexec_b32 s3, s2
s_xor_b32 s50, exec_lo, s3
s_cbranch_execz BB95_26
v_and_or_b32 v9, v10, s21, s20
v_lshrrev_b32_e32 v11, 23, v10
v_mul_hi_u32 v12, v9, s22
v_mul_lo_u32 v13, v9, s23
v_mul_hi_u32 v14, v9, s23
v_mul_lo_u32 v15, v9, s24
v_mul_hi_u32 v16, v9, s24
v_mul_lo_u32 v17, v9, s25
v_mul_hi_u32 v18, v9, s25
v_mul_lo_u32 v19, v9, s26
v_mul_hi_u32 v20, v9, s27
v_add_co_u32 v12, vcc_lo, v13, v12
v_mul_lo_u32 v21, v9, s28
v_add_co_ci_u32_e32 v13, vcc_lo, v15, v14, vcc_lo
v_mul_hi_u32 v14, v9, s26
v_mul_lo_u32 v15, v9, s27
v_add_co_ci_u32_e32 v16, vcc_lo, v17, v16, vcc_lo
v_mul_hi_u32 v22, v9, s28
v_add_co_ci_u32_e32 v17, vcc_lo, v19, v18, vcc_lo
v_add_nc_u32_e32 v11, s29, v11
v_mul_lo_u32 v9, v9, s22
v_add_co_ci_u32_e32 v14, vcc_lo, v15, v14, vcc_lo
v_add_co_ci_u32_e32 v15, vcc_lo, v21, v20, vcc_lo
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v22, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 31, v11
v_cndmask_b32_e64 v19, 0, s30, vcc_lo
v_cndmask_b32_e32 v18, v18, v15, vcc_lo
v_cndmask_b32_e32 v15, v15, v14, vcc_lo
v_cndmask_b32_e32 v14, v14, v17, vcc_lo
v_cndmask_b32_e32 v17, v17, v16, vcc_lo
v_add_nc_u32_e32 v11, v19, v11
v_cndmask_b32_e32 v16, v16, v13, vcc_lo
v_cndmask_b32_e32 v13, v13, v12, vcc_lo
v_cndmask_b32_e32 v9, v12, v9, vcc_lo
v_cmp_lt_u32_e64 s2, 31, v11
v_cndmask_b32_e64 v19, 0, s30, s2
v_cndmask_b32_e64 v18, v18, v15, s2
v_cndmask_b32_e64 v15, v15, v14, s2
v_cndmask_b32_e64 v14, v14, v17, s2
v_cndmask_b32_e64 v17, v17, v16, s2
v_add_nc_u32_e32 v11, v19, v11
v_cndmask_b32_e64 v16, v16, v13, s2
v_cndmask_b32_e64 v9, v13, v9, s2
v_cmp_lt_u32_e64 s3, 31, v11
v_cndmask_b32_e64 v19, 0, s30, s3
v_cndmask_b32_e64 v18, v18, v15, s3
v_cndmask_b32_e64 v15, v15, v14, s3
v_cndmask_b32_e64 v14, v14, v17, s3
v_cndmask_b32_e64 v17, v17, v16, s3
v_add_nc_u32_e32 v11, v19, v11
v_cndmask_b32_e64 v9, v16, v9, s3
v_cmp_lt_u32_e64 s4, 31, v11
v_cndmask_b32_e64 v19, 0, s30, s4
v_cndmask_b32_e64 v12, v15, v14, s4
v_cndmask_b32_e64 v18, v18, v15, s4
v_cndmask_b32_e64 v14, v14, v17, s4
v_cndmask_b32_e64 v9, v17, v9, s4
v_add_nc_u32_e32 v11, v19, v11
v_sub_nc_u32_e32 v15, 32, v11
v_cmp_eq_u32_e32 vcc_lo, 0, v11
v_alignbit_b32 v13, v18, v12, v15
v_alignbit_b32 v19, v12, v14, v15
v_alignbit_b32 v15, v14, v9, v15
v_cndmask_b32_e32 v11, v13, v18, vcc_lo
v_cndmask_b32_e32 v12, v19, v12, vcc_lo
v_cndmask_b32_e32 v14, v15, v14, vcc_lo
v_bfe_i32 v16, v11, 29, 1
v_alignbit_b32 v13, v11, v12, 30
v_alignbit_b32 v12, v12, v14, 30
v_alignbit_b32 v9, v14, v9, 30
v_xor_b32_e32 v13, v16, v13
v_xor_b32_e32 v12, v16, v12
v_xor_b32_e32 v9, v16, v9
v_lshrrev_b32_e32 v16, 29, v11
v_ffbh_u32_e32 v15, v13
v_cmp_ne_u32_e32 vcc_lo, 0, v13
v_cndmask_b32_e32 v15, 32, v15, vcc_lo
v_sub_nc_u32_e32 v14, 31, v15
v_alignbit_b32 v13, v13, v12, v14
v_alignbit_b32 v9, v12, v9, v14
v_lshlrev_b32_e32 v12, 31, v16
v_mad_i32_i24 v16, v15, s31, 0.5
v_alignbit_b32 v14, v13, v9, 9
v_lshrrev_b32_e32 v13, 9, v13
v_ffbh_u32_e32 v17, v14
v_cmp_ne_u32_e32 vcc_lo, 0, v14
v_or3_b32 v13, v16, v12, v13
v_cndmask_b32_e32 v16, 32, v17, vcc_lo
v_and_b32_e32 v17, s33, v13
v_mul_f32_e32 v18, s34, v13
v_sub_nc_u32_e32 v19, 31, v16
v_add_nc_u32_e32 v15, v16, v15
v_fma_f32 v18, v17, s35, -v18
v_mul_f32_e32 v16, s38, v13
v_alignbit_b32 v9, v14, v9, v19
v_sub_f32_e32 v14, v13, v17
v_fmac_f32_e32 v18, s36, v17
v_mad_i32_i24 v15, v15, s31, s37
v_lshrrev_b32_e32 v9, 9, v9
v_fmac_f32_e32 v18, s35, v14
v_or3_b32 v9, v15, v12, v9
v_bfe_u32 v12, v11, 29, 1
v_fmac_f32_e32 v18, s36, v14
v_lshrrev_b32_e32 v11, 30, v11
v_fmac_f32_e32 v16, s34, v9
v_add_nc_u32_e32 v11, v12, v11
v_add_f32_e32 v9, v18, v16
v_fmac_f32_e32 v9, s34, v13
BB95_26:
s_or_saveexec_b32 s2, s50
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execz BB95_28
v_mul_f32_e32 v9, s39, v10
v_rndne_f32_e32 v11, v9
v_and_b32_e32 v9, s33, v11
v_mul_f32_e32 v12, s40, v11
v_fma_f32 v13, s40, v11, v10
v_mul_f32_e32 v16, s41, v11
v_sub_f32_e32 v14, v11, v9
v_fmac_f32_e32 v12, s35, v9
v_sub_f32_e32 v15, v10, v13
v_fmac_f32_e32 v16, s42, v9
v_fmac_f32_e32 v12, s36, v9
v_fmac_f32_e32 v15, s40, v11
v_fmac_f32_e32 v16, s43, v9
v_fmac_f32_e32 v12, s35, v14
v_fmac_f32_e32 v16, s42, v14
v_fmac_f32_e32 v12, s36, v14
v_fmac_f32_e32 v16, s43, v14
v_sub_f32_e32 v12, v15, v12
v_add_f32_e32 v12, v13, v12
v_fma_f32 v9, s41, v11, v12
v_sub_f32_e32 v12, v12, v9
v_fmac_f32_e32 v12, s41, v11
v_sub_f32_e32 v12, v12, v16
v_add_f32_e32 v9, v9, v12
v_fmac_f32_e32 v9, s44, v11
v_cvt_i32_f32_e32 v11, v11
BB95_28:
s_or_b32 exec_lo, exec_lo, s2
v_mul_f32_e32 v12, v9, v9
v_and_b32_e32 v15, 1, v11
v_lshlrev_b32_e32 v11, 30, v11
v_fma_f32 v13, v12, s45, 0x3c0881c4
v_fma_f32 v14, v12, s46, 0xbab64f3b
v_cmp_eq_u32_e32 vcc_lo, 0, v15
v_and_b32_e32 v11, s47, v11
v_fmaak_f32 v13, v12, v13, 0xbe2aaa9d
v_fmaak_f32 v14, v12, v14, 0x3d2aabf7
v_mul_f32_e32 v13, v12, v13
v_fmaak_f32 v14, v12, v14, 0xbf000004
v_fmac_f32_e32 v9, v9, v13
v_fma_f32 v12, v12, v14, 1.0
v_cndmask_b32_e64 v9, -v9, v12, vcc_lo
v_xor_b32_e32 v11, v11, v9
BB95_29:
s_or_saveexec_b32 s12, s12
s_xor_b32 exec_lo, exec_lo, s12
s_cbranch_execz BB95_2
global_load_dword v10, v[5:6], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v11, s2, v10, v10, v9
v_div_scale_f32 v14, vcc_lo, v9, v10, v9
v_rcp_f32_e32 v12, v11
v_fma_f32 v13, -v11, v12, 1.0
v_fmac_f32_e32 v12, v13, v12
v_mul_f32_e32 v13, v14, v12
v_fma_f32 v15, v13, -v11, v14
v_fmac_f32_e32 v13, v15, v12
v_fmac_f32_e64 v14, -v11, v13
v_div_fmas_f32 v11, v14, v12, v13
v_div_fixup_f32 v9, v11, v10, v9
v_and_b32_e32 v10, s18, v9
v_cmp_nlt_f32_e64 s2, |v9|, s19
s_and_saveexec_b32 s3, s2
s_xor_b32 s50, exec_lo, s3
s_cbranch_execz BB95_32
v_and_or_b32 v11, v10, s21, s20
v_lshrrev_b32_e32 v12, 23, v10
v_mul_hi_u32 v13, v11, s22
v_mul_lo_u32 v14, v11, s23
v_mul_hi_u32 v15, v11, s23
v_mul_lo_u32 v16, v11, s24
v_mul_hi_u32 v17, v11, s24
v_mul_lo_u32 v18, v11, s25
v_mul_hi_u32 v19, v11, s25
v_mul_lo_u32 v20, v11, s26
v_mul_hi_u32 v21, v11, s27
v_add_co_u32 v13, vcc_lo, v14, v13
v_mul_lo_u32 v22, v11, s28
v_add_co_ci_u32_e32 v14, vcc_lo, v16, v15, vcc_lo
v_mul_hi_u32 v15, v11, s26
v_mul_lo_u32 v16, v11, s27
v_add_co_ci_u32_e32 v17, vcc_lo, v18, v17, vcc_lo
v_mul_hi_u32 v23, v11, s28
v_add_co_ci_u32_e32 v18, vcc_lo, v20, v19, vcc_lo
v_add_nc_u32_e32 v12, s29, v12
v_mul_lo_u32 v11, v11, s22
v_add_co_ci_u32_e32 v15, vcc_lo, v16, v15, vcc_lo
v_add_co_ci_u32_e32 v16, vcc_lo, v22, v21, vcc_lo
v_add_co_ci_u32_e32 v19, vcc_lo, 0, v23, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 31, v12
v_cndmask_b32_e64 v20, 0, s30, vcc_lo
v_cndmask_b32_e32 v19, v19, v16, vcc_lo
v_cndmask_b32_e32 v16, v16, v15, vcc_lo
v_cndmask_b32_e32 v15, v15, v18, vcc_lo
v_cndmask_b32_e32 v18, v18, v17, vcc_lo
v_add_nc_u32_e32 v12, v20, v12
v_cndmask_b32_e32 v17, v17, v14, vcc_lo
v_cndmask_b32_e32 v14, v14, v13, vcc_lo
v_cndmask_b32_e32 v11, v13, v11, vcc_lo
v_cmp_lt_u32_e64 s2, 31, v12
v_cndmask_b32_e64 v20, 0, s30, s2
v_cndmask_b32_e64 v19, v19, v16, s2
v_cndmask_b32_e64 v16, v16, v15, s2
v_cndmask_b32_e64 v15, v15, v18, s2
v_cndmask_b32_e64 v18, v18, v17, s2
v_add_nc_u32_e32 v12, v20, v12
v_cndmask_b32_e64 v17, v17, v14, s2
v_cndmask_b32_e64 v11, v14, v11, s2
v_cmp_lt_u32_e64 s3, 31, v12
v_cndmask_b32_e64 v20, 0, s30, s3
v_cndmask_b32_e64 v19, v19, v16, s3
v_cndmask_b32_e64 v16, v16, v15, s3
v_cndmask_b32_e64 v15, v15, v18, s3
v_cndmask_b32_e64 v18, v18, v17, s3
v_add_nc_u32_e32 v12, v20, v12
v_cndmask_b32_e64 v11, v17, v11, s3
v_cmp_lt_u32_e64 s4, 31, v12
v_cndmask_b32_e64 v20, 0, s30, s4
v_cndmask_b32_e64 v13, v16, v15, s4
v_cndmask_b32_e64 v19, v19, v16, s4
v_cndmask_b32_e64 v15, v15, v18, s4
v_cndmask_b32_e64 v11, v18, v11, s4
v_add_nc_u32_e32 v12, v20, v12
v_sub_nc_u32_e32 v16, 32, v12
v_cmp_eq_u32_e32 vcc_lo, 0, v12
v_alignbit_b32 v14, v19, v13, v16
v_alignbit_b32 v20, v13, v15, v16
v_alignbit_b32 v16, v15, v11, v16
v_cndmask_b32_e32 v12, v14, v19, vcc_lo
v_cndmask_b32_e32 v13, v20, v13, vcc_lo
v_cndmask_b32_e32 v15, v16, v15, vcc_lo
v_bfe_i32 v17, v12, 29, 1
v_alignbit_b32 v14, v12, v13, 30
v_alignbit_b32 v13, v13, v15, 30
v_alignbit_b32 v11, v15, v11, 30
v_xor_b32_e32 v14, v17, v14
v_xor_b32_e32 v13, v17, v13
v_xor_b32_e32 v11, v17, v11
v_lshrrev_b32_e32 v17, 29, v12
v_ffbh_u32_e32 v16, v14
v_cmp_ne_u32_e32 vcc_lo, 0, v14
v_cndmask_b32_e32 v16, 32, v16, vcc_lo
v_sub_nc_u32_e32 v15, 31, v16
v_alignbit_b32 v14, v14, v13, v15
v_alignbit_b32 v11, v13, v11, v15
v_lshlrev_b32_e32 v13, 31, v17
v_mad_i32_i24 v17, v16, s31, 0.5
v_alignbit_b32 v15, v14, v11, 9
v_lshrrev_b32_e32 v14, 9, v14
v_ffbh_u32_e32 v18, v15
v_cmp_ne_u32_e32 vcc_lo, 0, v15
v_or3_b32 v14, v17, v13, v14
v_cndmask_b32_e32 v17, 32, v18, vcc_lo
v_and_b32_e32 v18, s33, v14
v_mul_f32_e32 v19, s34, v14
v_sub_nc_u32_e32 v20, 31, v17
v_add_nc_u32_e32 v16, v17, v16
v_fma_f32 v19, v18, s35, -v19
v_mul_f32_e32 v17, s38, v14
v_alignbit_b32 v11, v15, v11, v20
v_sub_f32_e32 v15, v14, v18
v_fmac_f32_e32 v19, s36, v18
v_mad_i32_i24 v16, v16, s31, s37
v_lshrrev_b32_e32 v11, 9, v11
v_fmac_f32_e32 v19, s35, v15
v_or3_b32 v11, v16, v13, v11
v_bfe_u32 v13, v12, 29, 1
v_fmac_f32_e32 v19, s36, v15
v_lshrrev_b32_e32 v12, 30, v12
v_fmac_f32_e32 v17, s34, v11
v_add_nc_u32_e32 v12, v13, v12
v_add_f32_e32 v11, v19, v17
v_fmac_f32_e32 v11, s34, v14
BB95_32:
s_or_saveexec_b32 s2, s50
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execz BB95_1
v_mul_f32_e32 v11, s39, v10
v_rndne_f32_e32 v12, v11
v_and_b32_e32 v11, s33, v12
v_mul_f32_e32 v13, s40, v12
v_fma_f32 v14, s40, v12, v10
v_mul_f32_e32 v17, s41, v12
v_sub_f32_e32 v15, v12, v11
v_fmac_f32_e32 v13, s35, v11
v_sub_f32_e32 v16, v10, v14
v_fmac_f32_e32 v17, s42, v11
v_fmac_f32_e32 v13, s36, v11
v_fmac_f32_e32 v16, s40, v12
v_fmac_f32_e32 v17, s43, v11
v_fmac_f32_e32 v13, s35, v15
v_fmac_f32_e32 v17, s42, v15
v_fmac_f32_e32 v13, s36, v15
v_fmac_f32_e32 v17, s43, v15
v_sub_f32_e32 v13, v16, v13
v_add_f32_e32 v13, v14, v13
v_fma_f32 v11, s41, v12, v13
v_sub_f32_e32 v13, v13, v11
v_fmac_f32_e32 v13, s41, v12
v_sub_f32_e32 v13, v13, v17
v_add_f32_e32 v11, v11, v13
v_fmac_f32_e32 v11, s44, v12
v_cvt_i32_f32_e32 v12, v12
s_branch BB95_1
BB95_34:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_strided_slice_add_divide_multiply_expand_dims_divide_strided_slice_sin_str_dbf4827b0a4481cc__kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 24
.amdhsa_next_free_sgpr 54
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end95:
.size tvmgen_default_fused_strided_slice_add_divide_multiply_expand_dims_divide_strided_slice_sin_str_dbf4827b0a4481cc__kernel0, .Lfunc_end95-tvmgen_default_fused_strided_slice_add_divide_multiply_expand_dims_divide_strided_slice_sin_str_dbf4827b0a4481cc__kernel0
.globl tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_1_kernel0
.p2align 8
.type tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_1_kernel0,@function
tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_1_kernel0:
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_lshl_add_u32 v1, s6, 8, v0
s_clause 0x1
s_load_dwordx2 s[2:3], s[4:5], 0x10
s_load_dwordx2 s[8:9], s[4:5], 0x18
v_lshlrev_b32_e32 v0, 2, v0
s_ashr_i32 s7, s6, 31
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
s_load_dwordx2 s[0:1], s[4:5], 0x20
s_load_dwordx2 s[10:11], s[4:5], 0x28
global_load_dword v3, v[3:4], off
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_dword v4, v0, s[0:1]
global_load_dword v5, v0, s[10:11]
s_lshl_b64 s[0:1], s[6:7], 2
s_add_u32 s2, s2, s0
s_addc_u32 s3, s3, s1
s_add_u32 s0, s8, s0
s_addc_u32 s1, s9, s1
s_load_dword s0, s[0:1], 0x0
s_load_dword s1, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v0, 0x3727c5ac, s0
v_sqrt_f32_e32 v0, v0
s_waitcnt vmcnt(2)
v_subrev_f32_e32 v3, s1, v3
v_div_scale_f32 v6, s0, v0, v0, v3
v_div_scale_f32 v9, vcc_lo, v3, v0, v3
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_rcp_f32_e32 v7, v6
v_fma_f32 v8, -v6, v7, 1.0
v_fmac_f32_e32 v7, v8, v7
v_mul_f32_e32 v8, v9, v7
v_fma_f32 v10, v8, -v6, v9
v_fmac_f32_e32 v8, v10, v7
v_fmac_f32_e64 v9, -v6, v8
v_div_fmas_f32 v6, v9, v7, v8
v_div_fixup_f32 v0, v6, v0, v3
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v0, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_dword v[0:1], v5, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_1_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 12
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end96:
.size tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_1_kernel0, .Lfunc_end96-tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_1_kernel0
.globl tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_kernel0
.p2align 8
.type tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_kernel0,@function
tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_kernel0:
s_clause 0x5
s_load_dwordx2 s[12:13], s[4:5], 0x20
s_load_dwordx2 s[14:15], s[4:5], 0x28
s_load_dwordx2 s[0:1], s[4:5], 0x0
s_load_dwordx2 s[10:11], s[4:5], 0x8
s_load_dwordx2 s[8:9], s[4:5], 0x10
s_load_dwordx2 s[2:3], s[4:5], 0x18
v_lshl_add_u32 v4, s6, 8, v0
v_lshlrev_b32_e32 v0, 2, v0
s_mov_b32 s4, 0x25800
v_cmp_gt_i32_e64 s5, 0x258, s6
v_cmp_gt_i32_e32 vcc_lo, s4, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s7, s12, v0
v_add_co_ci_u32_e64 v3, s7, s13, 0, s7
v_add_co_u32 v0, s7, s14, v0
v_add_co_ci_u32_e64 v1, s7, s15, 0, s7
s_and_b32 s7, s5, vcc_lo
s_and_saveexec_b32 s5, s7
s_cbranch_execz BB97_2
v_ashrrev_i32_e32 v5, 31, v4
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[12:13], s[6:7], 2
v_lshlrev_b64 v[5:6], 2, v[4:5]
s_add_u32 s14, s8, s12
s_addc_u32 s15, s9, s13
s_add_u32 s12, s2, s12
s_addc_u32 s13, s3, s13
v_add_co_u32 v7, vcc_lo, s10, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v6, vcc_lo
global_load_dword v7, v[7:8], off
global_load_dword v8, v[2:3], off
global_load_dword v9, v[0:1], off
s_load_dword s7, s[12:13], 0x0
s_load_dword s12, s[14:15], 0x0
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v10, 0x3727c5ac, s7
v_sqrt_f32_e32 v10, v10
s_waitcnt vmcnt(2)
v_subrev_f32_e32 v7, s12, v7
v_div_scale_f32 v11, s7, v10, v10, v7
v_div_scale_f32 v14, vcc_lo, v7, v10, v7
v_rcp_f32_e32 v12, v11
v_fma_f32 v13, -v11, v12, 1.0
v_fmac_f32_e32 v12, v13, v12
v_mul_f32_e32 v13, v14, v12
v_fma_f32 v15, v13, -v11, v14
v_fmac_f32_e32 v13, v15, v12
v_fmac_f32_e64 v14, -v11, v13
v_div_fmas_f32 v11, v14, v12, v13
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_div_fixup_f32 v7, v11, v10, v7
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v9, v7, v8
global_store_dword v[5:6], v9, off
BB97_2:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v5, 0x10000, v4
v_cmp_gt_i32_e64 s5, 0x158, s6
v_cmp_gt_i32_e32 vcc_lo, s4, v5
s_and_b32 s5, s5, vcc_lo
s_and_saveexec_b32 s4, s5
s_cbranch_execz BB97_4
v_ashrrev_i32_e32 v6, 31, v5
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[12:13], s[6:7], 2
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_add_u32 s14, s8, s12
s_addc_u32 s15, s9, s13
s_add_u32 s12, s2, s12
s_addc_u32 s13, s3, s13
v_add_co_u32 v7, vcc_lo, s10, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v6, vcc_lo
global_load_dword v7, v[7:8], off
global_load_dword v8, v[2:3], off
global_load_dword v9, v[0:1], off
s_load_dword s5, s[12:13], 0x400
s_load_dword s7, s[14:15], 0x400
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v10, 0x3727c5ac, s5
v_sqrt_f32_e32 v10, v10
s_waitcnt vmcnt(2)
v_subrev_f32_e32 v7, s7, v7
v_div_scale_f32 v11, s5, v10, v10, v7
v_div_scale_f32 v14, vcc_lo, v7, v10, v7
v_rcp_f32_e32 v12, v11
v_fma_f32 v13, -v11, v12, 1.0
v_fmac_f32_e32 v12, v13, v12
v_mul_f32_e32 v13, v14, v12
v_fma_f32 v15, v13, -v11, v14
v_fmac_f32_e32 v13, v15, v12
v_fmac_f32_e64 v14, -v11, v13
v_div_fmas_f32 v11, v14, v12, v13
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_div_fixup_f32 v7, v11, v10, v7
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v9, v7, v8
global_store_dword v[5:6], v9, off
BB97_4:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v4, 0x20000, v4
v_cmp_gt_i32_e64 s4, 0x58, s6
v_cmp_gt_i32_e32 vcc_lo, 0x25800, v4
s_and_b32 s4, s4, vcc_lo
s_and_saveexec_b32 s5, s4
s_cbranch_execz BB97_6
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s4, s6, 0x200
s_ashr_i32 s5, s4, 31
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s6, s8, s4
s_addc_u32 s7, s9, s5
s_add_u32 s2, s2, s4
v_add_co_u32 v6, vcc_lo, s10, v4
s_addc_u32 s3, s3, s5
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v5, vcc_lo
global_load_dword v6, v[6:7], off
global_load_dword v2, v[2:3], off
global_load_dword v3, v[0:1], off
s_load_dword s2, s[2:3], 0x0
s_load_dword s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v0, 0x3727c5ac, s2
v_sqrt_f32_e32 v0, v0
s_waitcnt vmcnt(2)
v_subrev_f32_e32 v1, s3, v6
v_div_scale_f32 v6, s2, v0, v0, v1
v_div_scale_f32 v9, vcc_lo, v1, v0, v1
v_rcp_f32_e32 v7, v6
v_fma_f32 v8, -v6, v7, 1.0
v_fmac_f32_e32 v7, v8, v7
v_mul_f32_e32 v8, v9, v7
v_fma_f32 v10, v8, -v6, v9
v_fmac_f32_e32 v8, v10, v7
v_fmac_f32_e64 v9, -v6, v8
v_div_fmas_f32 v6, v9, v7, v8
v_div_fixup_f32 v0, v6, v0, v1
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v0, v2
v_add_co_u32 v0, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v5, vcc_lo
global_store_dword v[0:1], v3, off
BB97_6:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end97:
.size tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_kernel0, .Lfunc_end97-tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_kernel0
.globl tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_subtract_add_sqrt_divide_multiply_ad_680b67fb8a56ff9f__kernel0
.p2align 8
.type tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_subtract_add_sqrt_divide_multiply_ad_680b67fb8a56ff9f__kernel0,@function
tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_subtract_add_sqrt_divide_multiply_ad_680b67fb8a56ff9f__kernel0:
s_clause 0x14
s_load_dwordx2 s[42:43], s[4:5], 0xa0
s_load_dwordx2 s[46:47], s[4:5], 0x98
s_load_dwordx2 s[44:45], s[4:5], 0x90
s_load_dwordx2 s[36:37], s[4:5], 0x88
s_load_dwordx2 s[40:41], s[4:5], 0x80
s_load_dwordx2 s[38:39], s[4:5], 0x78
s_load_dwordx2 s[28:29], s[4:5], 0x70
s_load_dwordx2 s[34:35], s[4:5], 0x68
s_load_dwordx2 s[30:31], s[4:5], 0x60
s_load_dwordx2 s[22:23], s[4:5], 0x58
s_load_dwordx2 s[26:27], s[4:5], 0x50
s_load_dwordx2 s[24:25], s[4:5], 0x48
s_load_dwordx2 s[18:19], s[4:5], 0x40
s_load_dwordx2 s[2:3], s[4:5], 0x0
s_load_dwordx2 s[14:15], s[4:5], 0x8
s_load_dwordx2 s[16:17], s[4:5], 0x10
s_load_dwordx2 s[12:13], s[4:5], 0x18
s_load_dwordx2 s[10:11], s[4:5], 0x20
s_load_dwordx2 s[8:9], s[4:5], 0x28
s_load_dwordx2 s[20:21], s[4:5], 0x30
s_load_dwordx2 s[4:5], s[4:5], 0x38
v_lshlrev_b32_e32 v2, 1, v0
s_lshl_b32 s7, s6, 9
v_lshl_add_u32 v7, s6, 8, v0
s_lshl_b32 s6, s6, 1
v_add_nc_u32_e32 v5, s7, v2
v_cmp_gt_i32_e32 vcc_lo, 0x12c00, v7
v_cmp_lt_i32_e64 s0, 0x12bff, v7
v_cmp_gt_i32_e64 s1, 0x25800, v5
s_and_b32 s33, s1, vcc_lo
s_and_saveexec_b32 s1, s33
s_cbranch_execz BB98_22
v_add_nc_u32_e32 v1, 0xfffe0c00, v5
s_movk_i32 s48, 0x63ff
v_cmp_lt_u32_e32 vcc_lo, s48, v1
s_and_saveexec_b32 s33, vcc_lo
s_xor_b32 s33, exec_lo, s33
s_cbranch_execz BB98_19
v_add_nc_u32_e32 v1, 0xfffe7000, v5
v_cmp_lt_u32_e32 vcc_lo, s48, v1
s_and_saveexec_b32 s48, vcc_lo
s_xor_b32 s48, exec_lo, s48
s_cbranch_execz BB98_16
v_add_nc_u32_e32 v1, 0xfffed400, v5
s_movk_i32 s50, 0x63ff
v_cmp_lt_u32_e32 vcc_lo, s50, v1
s_and_saveexec_b32 s49, vcc_lo
s_xor_b32 s49, exec_lo, s49
s_cbranch_execz BB98_13
v_add_nc_u32_e32 v1, 0xffff3800, v5
v_cmp_lt_u32_e32 vcc_lo, s50, v1
s_and_saveexec_b32 s50, vcc_lo
s_xor_b32 s50, exec_lo, s50
s_cbranch_execz BB98_10
v_lshrrev_b32_e32 v1, 7, v0
v_add_nc_u32_e32 v1, s6, v1
v_mul_hi_i32 v3, 0x51eb851f, v1
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 5, v3
v_add_nc_u32_e32 v3, v3, v4
v_add_nc_u32_e32 v4, 0xffff9c00, v5
v_mul_lo_u32 v3, 0x64, v3
v_cmp_lt_u32_e32 vcc_lo, 0x63ff, v4
v_sub_nc_u32_e32 v10, v1, v3
v_ashrrev_i32_e32 v11, 31, v10
s_and_saveexec_b32 s51, vcc_lo
s_xor_b32 s51, exec_lo, s51
s_cbranch_execz BB98_7
v_and_b32_e32 v3, 0xfe, v2
v_lshl_or_b32 v8, v10, 8, v3
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_ashrrev_i32_e32 v9, 31, v8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v12, vcc_lo, s46, v10
v_add_co_ci_u32_e32 v13, vcc_lo, s47, v11, vcc_lo
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, vcc_lo, s44, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s45, v9, vcc_lo
global_load_dword v1, v[12:13], off
global_load_dword v4, v[8:9], off
v_add_co_u32 v8, vcc_lo, s42, v10
v_add_co_ci_u32_e32 v9, vcc_lo, s43, v11, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v4, v1
BB98_7:
s_or_saveexec_b32 s51, s51
s_xor_b32 exec_lo, exec_lo, s51
s_cbranch_execz BB98_9
v_and_b32_e32 v3, 0xfe, v2
v_lshl_or_b32 v8, v10, 8, v3
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_ashrrev_i32_e32 v9, 31, v8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v12, vcc_lo, s40, v10
v_add_co_ci_u32_e32 v13, vcc_lo, s41, v11, vcc_lo
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, vcc_lo, s38, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s39, v9, vcc_lo
global_load_dword v1, v[12:13], off
global_load_dword v4, v[8:9], off
v_add_co_u32 v8, vcc_lo, s36, v10
v_add_co_ci_u32_e32 v9, vcc_lo, s37, v11, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v4, v1
BB98_9:
s_or_b32 exec_lo, exec_lo, s51
BB98_10:
s_or_saveexec_b32 s50, s50
s_xor_b32 exec_lo, exec_lo, s50
s_cbranch_execz BB98_12
v_lshrrev_b32_e32 v1, 7, v0
v_add_nc_u32_e32 v1, s6, v1
v_mul_hi_i32 v3, 0x51eb851f, v1
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 5, v3
v_add_nc_u32_e32 v3, v3, v4
v_mul_lo_u32 v4, 0x64, v3
v_and_b32_e32 v3, 0xfe, v2
v_sub_nc_u32_e32 v8, v1, v4
v_lshl_or_b32 v10, v8, 8, v3
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v12, vcc_lo, s34, v8
v_add_co_ci_u32_e32 v13, vcc_lo, s35, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s30, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s31, v11, vcc_lo
v_add_co_u32 v8, vcc_lo, s28, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s29, v9, vcc_lo
global_load_dword v1, v[12:13], off
global_load_dword v4, v[10:11], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v4, v1
BB98_12:
s_or_b32 exec_lo, exec_lo, s50
BB98_13:
s_or_saveexec_b32 s49, s49
s_xor_b32 exec_lo, exec_lo, s49
s_cbranch_execz BB98_15
v_lshrrev_b32_e32 v1, 7, v0
v_add_nc_u32_e32 v1, s6, v1
v_mul_hi_i32 v3, 0x51eb851f, v1
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 5, v3
v_add_nc_u32_e32 v3, v3, v4
v_mul_lo_u32 v4, 0x64, v3
v_and_b32_e32 v3, 0xfe, v2
v_sub_nc_u32_e32 v8, v1, v4
v_lshl_or_b32 v10, v8, 8, v3
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v12, vcc_lo, s26, v8
v_add_co_ci_u32_e32 v13, vcc_lo, s27, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s24, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s25, v11, vcc_lo
v_add_co_u32 v8, vcc_lo, s22, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s23, v9, vcc_lo
global_load_dword v1, v[12:13], off
global_load_dword v4, v[10:11], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v4, v1
BB98_15:
s_or_b32 exec_lo, exec_lo, s49
BB98_16:
s_or_saveexec_b32 s48, s48
s_xor_b32 exec_lo, exec_lo, s48
s_cbranch_execz BB98_18
v_lshrrev_b32_e32 v1, 7, v0
v_add_nc_u32_e32 v1, s6, v1
v_mul_hi_i32 v3, 0x51eb851f, v1
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 5, v3
v_add_nc_u32_e32 v3, v3, v4
v_mul_lo_u32 v4, 0x64, v3
v_and_b32_e32 v3, 0xfe, v2
v_sub_nc_u32_e32 v8, v1, v4
v_lshl_or_b32 v10, v8, 8, v3
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v12, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s20, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s21, v11, vcc_lo
v_add_co_u32 v8, vcc_lo, s18, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s19, v9, vcc_lo
global_load_dword v1, v[12:13], off
global_load_dword v4, v[10:11], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v4, v1
BB98_18:
s_or_b32 exec_lo, exec_lo, s48
BB98_19:
s_or_saveexec_b32 s33, s33
s_xor_b32 exec_lo, exec_lo, s33
s_cbranch_execz BB98_21
v_lshrrev_b32_e32 v1, 7, v0
v_add_nc_u32_e32 v1, s6, v1
v_mul_hi_i32 v3, 0x51eb851f, v1
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 5, v3
v_add_nc_u32_e32 v3, v3, v4
v_mul_lo_u32 v4, 0x64, v3
v_and_b32_e32 v3, 0xfe, v2
v_sub_nc_u32_e32 v8, v1, v4
v_lshl_or_b32 v10, v8, 8, v3
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v12, vcc_lo, s16, v8
v_add_co_ci_u32_e32 v13, vcc_lo, s17, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s14, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s15, v11, vcc_lo
v_add_co_u32 v8, vcc_lo, s12, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s13, v9, vcc_lo
global_load_dword v1, v[12:13], off
global_load_dword v4, v[10:11], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v4, v1
BB98_21:
s_or_b32 exec_lo, exec_lo, s33
global_load_dword v6, v[8:9], off
v_mov_b32_e32 v4, 0
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
global_load_dword v8, v[8:9], off
global_load_dword v9, v[3:4], off
s_waitcnt vmcnt(2)
v_add_f32_e32 v3, 0x3727c5ac, v6
v_sqrt_f32_e32 v3, v3
v_div_scale_f32 v4, s33, v3, v3, v1
v_div_scale_f32 v11, vcc_lo, v1, v3, v1
v_rcp_f32_e32 v6, v4
v_fma_f32 v10, -v4, v6, 1.0
v_fmac_f32_e32 v6, v10, v6
v_mul_f32_e32 v10, v11, v6
v_fma_f32 v12, v10, -v4, v11
v_fmac_f32_e32 v10, v12, v6
v_fmac_f32_e64 v11, -v4, v10
v_div_fmas_f32 v4, v11, v6, v10
v_ashrrev_i32_e32 v6, 31, v5
v_div_fixup_f32 v1, v4, v3, v1
v_lshlrev_b64 v[3:4], 1, v[5:6]
s_waitcnt vmcnt(0)
v_fma_mixlo_f16 v1, v1, v8, v9
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_short v[3:4], v1, off
BB98_22:
s_or_b32 exec_lo, exec_lo, s1
v_or_b32_e32 v1, 1, v2
s_xor_b32 s0, s0, -1
v_add_nc_u32_e32 v3, s7, v1
v_cmp_gt_i32_e32 vcc_lo, 0x25800, v3
s_and_b32 s1, vcc_lo, s0
s_and_saveexec_b32 s0, s1
s_cbranch_execz BB98_44
v_add_nc_u32_e32 v4, 0xfffe0c00, v3
s_movk_i32 s7, 0x63ff
v_cmp_lt_u32_e32 vcc_lo, s7, v4
s_and_saveexec_b32 s1, vcc_lo
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz BB98_41
v_add_nc_u32_e32 v4, 0xfffe7000, v3
v_cmp_lt_u32_e32 vcc_lo, s7, v4
s_and_saveexec_b32 s7, vcc_lo
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz BB98_38
v_add_nc_u32_e32 v4, 0xfffed400, v3
s_movk_i32 s48, 0x63ff
v_cmp_lt_u32_e32 vcc_lo, s48, v4
s_and_saveexec_b32 s33, vcc_lo
s_xor_b32 s33, exec_lo, s33
s_cbranch_execz BB98_35
v_add_nc_u32_e32 v4, 0xffff3800, v3
v_cmp_lt_u32_e32 vcc_lo, s48, v4
s_and_saveexec_b32 s48, vcc_lo
s_xor_b32 s48, exec_lo, s48
s_cbranch_execz BB98_32
v_lshrrev_b32_e32 v4, 7, v0
v_add_nc_u32_e32 v4, s6, v4
v_mul_hi_i32 v6, 0x51eb851f, v4
v_lshrrev_b32_e32 v8, 31, v6
v_ashrrev_i32_e32 v6, 5, v6
v_add_nc_u32_e32 v6, v6, v8
v_add_nc_u32_e32 v8, 0xffff9c00, v3
v_mul_lo_u32 v6, 0x64, v6
v_cmp_lt_u32_e32 vcc_lo, 0x63ff, v8
v_sub_nc_u32_e32 v11, v4, v6
v_ashrrev_i32_e32 v12, 31, v11
s_and_saveexec_b32 s49, vcc_lo
s_xor_b32 s49, exec_lo, s49
s_cbranch_execz BB98_29
v_and_b32_e32 v8, 0xff, v1
v_lshl_or_b32 v9, v11, 8, v8
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_ashrrev_i32_e32 v10, 31, v9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, vcc_lo, s46, v11
v_add_co_ci_u32_e32 v14, vcc_lo, s47, v12, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s44, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s45, v10, vcc_lo
global_load_dword v4, v[13:14], off
global_load_dword v6, v[9:10], off
v_add_co_u32 v9, vcc_lo, s42, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s43, v12, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v6, v4
BB98_29:
s_or_saveexec_b32 s49, s49
s_xor_b32 exec_lo, exec_lo, s49
s_cbranch_execz BB98_31
v_and_b32_e32 v8, 0xff, v1
v_lshl_or_b32 v9, v11, 8, v8
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_ashrrev_i32_e32 v10, 31, v9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, vcc_lo, s40, v11
v_add_co_ci_u32_e32 v14, vcc_lo, s41, v12, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s38, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s39, v10, vcc_lo
global_load_dword v4, v[13:14], off
global_load_dword v6, v[9:10], off
v_add_co_u32 v9, vcc_lo, s36, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s37, v12, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v6, v4
BB98_31:
s_or_b32 exec_lo, exec_lo, s49
BB98_32:
s_or_saveexec_b32 s48, s48
s_xor_b32 exec_lo, exec_lo, s48
s_cbranch_execz BB98_34
v_lshrrev_b32_e32 v4, 7, v0
v_add_nc_u32_e32 v4, s6, v4
v_mul_hi_i32 v6, 0x51eb851f, v4
v_lshrrev_b32_e32 v8, 31, v6
v_ashrrev_i32_e32 v6, 5, v6
v_add_nc_u32_e32 v6, v6, v8
v_and_b32_e32 v8, 0xff, v1
v_mul_lo_u32 v6, 0x64, v6
v_sub_nc_u32_e32 v9, v4, v6
v_lshl_or_b32 v11, v9, 8, v8
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, vcc_lo, s34, v9
v_add_co_ci_u32_e32 v14, vcc_lo, s35, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s30, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s31, v12, vcc_lo
v_add_co_u32 v9, vcc_lo, s28, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s29, v10, vcc_lo
global_load_dword v4, v[13:14], off
global_load_dword v6, v[11:12], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v6, v4
BB98_34:
s_or_b32 exec_lo, exec_lo, s48
BB98_35:
s_or_saveexec_b32 s33, s33
s_xor_b32 exec_lo, exec_lo, s33
s_cbranch_execz BB98_37
v_lshrrev_b32_e32 v4, 7, v0
v_add_nc_u32_e32 v4, s6, v4
v_mul_hi_i32 v6, 0x51eb851f, v4
v_lshrrev_b32_e32 v8, 31, v6
v_ashrrev_i32_e32 v6, 5, v6
v_add_nc_u32_e32 v6, v6, v8
v_and_b32_e32 v8, 0xff, v1
v_mul_lo_u32 v6, 0x64, v6
v_sub_nc_u32_e32 v9, v4, v6
v_lshl_or_b32 v11, v9, 8, v8
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, vcc_lo, s26, v9
v_add_co_ci_u32_e32 v14, vcc_lo, s27, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s24, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s25, v12, vcc_lo
v_add_co_u32 v9, vcc_lo, s22, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s23, v10, vcc_lo
global_load_dword v4, v[13:14], off
global_load_dword v6, v[11:12], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v6, v4
BB98_37:
s_or_b32 exec_lo, exec_lo, s33
BB98_38:
s_or_saveexec_b32 s7, s7
s_xor_b32 exec_lo, exec_lo, s7
s_cbranch_execz BB98_40
v_lshrrev_b32_e32 v4, 7, v0
v_add_nc_u32_e32 v4, s6, v4
v_mul_hi_i32 v6, 0x51eb851f, v4
v_lshrrev_b32_e32 v8, 31, v6
v_ashrrev_i32_e32 v6, 5, v6
v_add_nc_u32_e32 v6, v6, v8
v_and_b32_e32 v8, 0xff, v1
v_mul_lo_u32 v6, 0x64, v6
v_sub_nc_u32_e32 v9, v4, v6
v_lshl_or_b32 v11, v9, 8, v8
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s20, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s21, v12, vcc_lo
v_add_co_u32 v9, vcc_lo, s18, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s19, v10, vcc_lo
global_load_dword v4, v[13:14], off
global_load_dword v6, v[11:12], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v6, v4
BB98_40:
s_or_b32 exec_lo, exec_lo, s7
BB98_41:
s_or_saveexec_b32 s1, s1
s_xor_b32 exec_lo, exec_lo, s1
s_cbranch_execz BB98_43
v_lshrrev_b32_e32 v4, 7, v0
v_add_nc_u32_e32 v4, s6, v4
v_mul_hi_i32 v6, 0x51eb851f, v4
v_lshrrev_b32_e32 v8, 31, v6
v_ashrrev_i32_e32 v6, 5, v6
v_add_nc_u32_e32 v6, v6, v8
v_and_b32_e32 v8, 0xff, v1
v_mul_lo_u32 v6, 0x64, v6
v_sub_nc_u32_e32 v9, v4, v6
v_lshl_or_b32 v11, v9, 8, v8
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, vcc_lo, s16, v9
v_add_co_ci_u32_e32 v14, vcc_lo, s17, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s14, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s15, v12, vcc_lo
v_add_co_u32 v9, vcc_lo, s12, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s13, v10, vcc_lo
global_load_dword v4, v[13:14], off
global_load_dword v6, v[11:12], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v6, v4
BB98_43:
s_or_b32 exec_lo, exec_lo, s1
global_load_dword v4, v[9:10], off
v_mov_b32_e32 v9, 0
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v9, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_load_dword v10, v[10:11], off
global_load_dword v11, v[8:9], off
s_waitcnt vmcnt(2)
v_add_f32_e32 v4, 0x3727c5ac, v4
v_sqrt_f32_e32 v8, v4
v_div_scale_f32 v4, s1, v8, v8, v6
v_div_scale_f32 v13, vcc_lo, v6, v8, v6
v_rcp_f32_e32 v9, v4
v_fma_f32 v12, -v4, v9, 1.0
v_fmac_f32_e32 v9, v12, v9
v_mul_f32_e32 v12, v13, v9
v_fma_f32 v14, v12, -v4, v13
v_fmac_f32_e32 v12, v14, v9
v_fmac_f32_e64 v13, -v4, v12
v_ashrrev_i32_e32 v4, 31, v3
v_div_fmas_f32 v9, v13, v9, v12
v_div_fixup_f32 v6, v9, v8, v6
v_lshlrev_b64 v[8:9], 1, v[3:4]
s_waitcnt vmcnt(0)
v_fma_mixlo_f16 v4, v6, v10, v11
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_store_short v[8:9], v4, off
BB98_44:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v6, 0x10000, v7
v_add_nc_u32_e32 v4, 0x20000, v5
s_addk_i32 s6, 0x200
v_cmp_gt_i32_e32 vcc_lo, 0x12c00, v6
v_cmp_gt_i32_e64 s1, 0x25800, v4
v_cmp_lt_i32_e64 s0, 0x12bff, v6
s_and_b32 s7, s1, vcc_lo
s_and_saveexec_b32 s1, s7
s_cbranch_execz BB98_66
v_add_nc_u32_e32 v6, 0xc00, v5
s_movk_i32 s33, 0x63ff
v_cmp_lt_u32_e32 vcc_lo, s33, v6
s_and_saveexec_b32 s7, vcc_lo
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz BB98_63
v_add_nc_u32_e32 v6, 0x7000, v5
v_cmp_lt_u32_e32 vcc_lo, s33, v6
s_and_saveexec_b32 s33, vcc_lo
s_xor_b32 s33, exec_lo, s33
s_cbranch_execz BB98_60
v_add_nc_u32_e32 v6, 0xd400, v5
s_movk_i32 s49, 0x63ff
v_cmp_lt_u32_e32 vcc_lo, s49, v6
s_and_saveexec_b32 s48, vcc_lo
s_xor_b32 s48, exec_lo, s48
s_cbranch_execz BB98_57
v_add_nc_u32_e32 v6, 0x13800, v5
v_cmp_lt_u32_e32 vcc_lo, s49, v6
s_and_saveexec_b32 s49, vcc_lo
s_xor_b32 s49, exec_lo, s49
s_cbranch_execz BB98_54
v_lshrrev_b32_e32 v6, 7, v0
v_add_nc_u32_e32 v5, 0x19c00, v5
v_add_nc_u32_e32 v6, s6, v6
v_cmp_lt_u32_e32 vcc_lo, 0x63ff, v5
v_mul_hi_i32 v7, 0x51eb851f, v6
v_lshrrev_b32_e32 v8, 31, v7
v_ashrrev_i32_e32 v7, 5, v7
v_add_nc_u32_e32 v7, v7, v8
v_mul_lo_u32 v7, 0x64, v7
v_sub_nc_u32_e32 v11, v6, v7
v_ashrrev_i32_e32 v12, 31, v11
s_and_saveexec_b32 s50, vcc_lo
s_xor_b32 s50, exec_lo, s50
s_cbranch_execz BB98_51
v_and_b32_e32 v6, 0xfe, v2
v_lshlrev_b64 v[9:10], 2, v[11:12]
v_lshl_or_b32 v7, v11, 8, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v11, vcc_lo, s46, v9
v_add_co_ci_u32_e32 v12, vcc_lo, s47, v10, vcc_lo
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s44, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s45, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s42, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s43, v10, vcc_lo
global_load_dword v2, v[11:12], off
global_load_dword v5, v[7:8], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v8, v5, v2
BB98_51:
s_or_saveexec_b32 s50, s50
s_xor_b32 exec_lo, exec_lo, s50
s_cbranch_execz BB98_53
v_and_b32_e32 v6, 0xfe, v2
v_lshlrev_b64 v[9:10], 2, v[11:12]
v_lshl_or_b32 v7, v11, 8, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v11, vcc_lo, s40, v9
v_add_co_ci_u32_e32 v12, vcc_lo, s41, v10, vcc_lo
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s38, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s39, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s36, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s37, v10, vcc_lo
global_load_dword v2, v[11:12], off
global_load_dword v5, v[7:8], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v8, v5, v2
BB98_53:
s_or_b32 exec_lo, exec_lo, s50
BB98_54:
s_or_saveexec_b32 s49, s49
s_xor_b32 exec_lo, exec_lo, s49
s_cbranch_execz BB98_56
v_lshrrev_b32_e32 v5, 7, v0
v_add_nc_u32_e32 v5, s6, v5
v_mul_hi_i32 v6, 0x51eb851f, v5
v_lshrrev_b32_e32 v7, 31, v6
v_ashrrev_i32_e32 v6, 5, v6
v_add_nc_u32_e32 v6, v6, v7
v_mul_lo_u32 v7, 0x64, v6
v_and_b32_e32 v6, 0xfe, v2
v_sub_nc_u32_e32 v7, v5, v7
v_lshl_or_b32 v9, v7, 8, v6
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[11:12], 2, v[7:8]
v_lshlrev_b64 v[7:8], 2, v[9:10]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s34, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s35, v12, vcc_lo
v_add_co_u32 v7, vcc_lo, s30, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s31, v8, vcc_lo
global_load_dword v2, v[9:10], off
global_load_dword v5, v[7:8], off
v_add_co_u32 v9, vcc_lo, s28, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s29, v12, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v8, v5, v2
BB98_56:
s_or_b32 exec_lo, exec_lo, s49
BB98_57:
s_or_saveexec_b32 s48, s48
s_xor_b32 exec_lo, exec_lo, s48
s_cbranch_execz BB98_59
v_lshrrev_b32_e32 v5, 7, v0
v_add_nc_u32_e32 v5, s6, v5
v_mul_hi_i32 v6, 0x51eb851f, v5
v_lshrrev_b32_e32 v7, 31, v6
v_ashrrev_i32_e32 v6, 5, v6
v_add_nc_u32_e32 v6, v6, v7
v_mul_lo_u32 v7, 0x64, v6
v_and_b32_e32 v6, 0xfe, v2
v_sub_nc_u32_e32 v7, v5, v7
v_lshl_or_b32 v9, v7, 8, v6
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[11:12], 2, v[7:8]
v_lshlrev_b64 v[7:8], 2, v[9:10]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s26, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s27, v12, vcc_lo
v_add_co_u32 v7, vcc_lo, s24, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s25, v8, vcc_lo
global_load_dword v2, v[9:10], off
global_load_dword v5, v[7:8], off
v_add_co_u32 v9, vcc_lo, s22, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s23, v12, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v8, v5, v2
BB98_59:
s_or_b32 exec_lo, exec_lo, s48
BB98_60:
s_or_saveexec_b32 s33, s33
s_xor_b32 exec_lo, exec_lo, s33
s_cbranch_execz BB98_62
v_lshrrev_b32_e32 v5, 7, v0
v_add_nc_u32_e32 v5, s6, v5
v_mul_hi_i32 v6, 0x51eb851f, v5
v_lshrrev_b32_e32 v7, 31, v6
v_ashrrev_i32_e32 v6, 5, v6
v_add_nc_u32_e32 v6, v6, v7
v_mul_lo_u32 v7, 0x64, v6
v_and_b32_e32 v6, 0xfe, v2
v_sub_nc_u32_e32 v7, v5, v7
v_lshl_or_b32 v9, v7, 8, v6
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[11:12], 2, v[7:8]
v_lshlrev_b64 v[7:8], 2, v[9:10]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v12, vcc_lo
v_add_co_u32 v7, vcc_lo, s20, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s21, v8, vcc_lo
global_load_dword v2, v[9:10], off
global_load_dword v5, v[7:8], off
v_add_co_u32 v9, vcc_lo, s18, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s19, v12, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v8, v5, v2
BB98_62:
s_or_b32 exec_lo, exec_lo, s33
BB98_63:
s_or_saveexec_b32 s7, s7
s_xor_b32 exec_lo, exec_lo, s7
s_cbranch_execz BB98_65
v_lshrrev_b32_e32 v5, 7, v0
v_add_nc_u32_e32 v5, s6, v5
v_mul_hi_i32 v6, 0x51eb851f, v5
v_lshrrev_b32_e32 v7, 31, v6
v_ashrrev_i32_e32 v6, 5, v6
v_add_nc_u32_e32 v6, v6, v7
v_mul_lo_u32 v7, 0x64, v6
v_and_b32_e32 v6, 0xfe, v2
v_sub_nc_u32_e32 v7, v5, v7
v_lshl_or_b32 v9, v7, 8, v6
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[11:12], 2, v[7:8]
v_lshlrev_b64 v[7:8], 2, v[9:10]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s16, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s17, v12, vcc_lo
v_add_co_u32 v7, vcc_lo, s14, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s15, v8, vcc_lo
global_load_dword v2, v[9:10], off
global_load_dword v5, v[7:8], off
v_add_co_u32 v9, vcc_lo, s12, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s13, v12, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v8, v5, v2
BB98_65:
s_or_b32 exec_lo, exec_lo, s7
global_load_dword v2, v[9:10], off
v_mov_b32_e32 v7, 0
v_lshlrev_b64 v[5:6], 2, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s10, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
global_load_dword v7, v[9:10], off
global_load_dword v6, v[5:6], off
s_waitcnt vmcnt(2)
v_add_f32_e32 v2, 0x3727c5ac, v2
v_sqrt_f32_e32 v2, v2
v_div_scale_f32 v5, s7, v2, v2, v8
v_div_scale_f32 v11, vcc_lo, v8, v2, v8
v_rcp_f32_e32 v9, v5
v_fma_f32 v10, -v5, v9, 1.0
v_fmac_f32_e32 v9, v10, v9
v_mul_f32_e32 v10, v11, v9
v_fma_f32 v12, v10, -v5, v11
v_fmac_f32_e32 v10, v12, v9
v_fmac_f32_e64 v11, -v5, v10
v_ashrrev_i32_e32 v5, 31, v4
v_div_fmas_f32 v9, v11, v9, v10
v_lshlrev_b64 v[4:5], 1, v[4:5]
v_div_fixup_f32 v2, v9, v2, v8
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_mixlo_f16 v2, v2, v7, v6
global_store_short v[4:5], v2, off
BB98_66:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v2, 0x20000, v3
s_xor_b32 s0, s0, -1
v_cmp_gt_i32_e32 vcc_lo, 0x25800, v2
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB98_88
v_add_nc_u32_e32 v4, 0xc00, v3
s_movk_i32 s1, 0x63ff
v_cmp_lt_u32_e32 vcc_lo, s1, v4
s_and_saveexec_b32 s0, vcc_lo
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz BB98_85
v_add_nc_u32_e32 v4, 0x7000, v3
v_cmp_lt_u32_e32 vcc_lo, s1, v4
s_and_saveexec_b32 s1, vcc_lo
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz BB98_82
v_add_nc_u32_e32 v4, 0xd400, v3
s_movk_i32 s33, 0x63ff
v_cmp_lt_u32_e32 vcc_lo, s33, v4
s_and_saveexec_b32 s7, vcc_lo
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz BB98_79
v_add_nc_u32_e32 v4, 0x13800, v3
v_cmp_lt_u32_e32 vcc_lo, s33, v4
s_and_saveexec_b32 s33, vcc_lo
s_xor_b32 s33, exec_lo, s33
s_cbranch_execz BB98_76
v_lshrrev_b32_e32 v0, 7, v0
v_add_nc_u32_e32 v3, 0x19c00, v3
v_add_nc_u32_e32 v0, s6, v0
v_cmp_lt_u32_e32 vcc_lo, 0x63ff, v3
v_mul_hi_i32 v4, 0x51eb851f, v0
v_lshrrev_b32_e32 v5, 31, v4
v_ashrrev_i32_e32 v4, 5, v4
v_add_nc_u32_e32 v4, v4, v5
v_mul_lo_u32 v4, 0x64, v4
v_sub_nc_u32_e32 v9, v0, v4
v_ashrrev_i32_e32 v10, 31, v9
s_and_saveexec_b32 s48, vcc_lo
s_xor_b32 s48, exec_lo, s48
s_cbranch_execz BB98_73
v_and_b32_e32 v4, 0xff, v1
v_lshlrev_b64 v[7:8], 2, v[9:10]
v_lshl_or_b32 v0, v9, 8, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s46, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s47, v8, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s44, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s45, v1, vcc_lo
v_add_co_u32 v7, vcc_lo, s42, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s43, v8, vcc_lo
global_load_dword v3, v[5:6], off
global_load_dword v0, v[0:1], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v0, v3
BB98_73:
s_waitcnt lgkmcnt(0)
s_or_saveexec_b32 s42, s48
s_xor_b32 exec_lo, exec_lo, s42
s_cbranch_execz BB98_75
v_and_b32_e32 v4, 0xff, v1
v_lshlrev_b64 v[7:8], 2, v[9:10]
v_lshl_or_b32 v0, v9, 8, v4
v_add_co_u32 v5, vcc_lo, s40, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s41, v8, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s38, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s39, v1, vcc_lo
v_add_co_u32 v7, vcc_lo, s36, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s37, v8, vcc_lo
global_load_dword v3, v[5:6], off
global_load_dword v0, v[0:1], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v0, v3
BB98_75:
s_or_b32 exec_lo, exec_lo, s42
BB98_76:
s_or_saveexec_b32 s33, s33
s_xor_b32 exec_lo, exec_lo, s33
s_cbranch_execz BB98_78
v_lshrrev_b32_e32 v0, 7, v0
v_add_nc_u32_e32 v0, s6, v0
v_mul_hi_i32 v3, 0x51eb851f, v0
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 5, v3
v_add_nc_u32_e32 v3, v3, v4
v_and_b32_e32 v4, 0xff, v1
v_mul_lo_u32 v3, 0x64, v3
v_sub_nc_u32_e32 v0, v0, v3
v_lshl_or_b32 v5, v0, 8, v4
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s34, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s35, v1, vcc_lo
v_add_co_u32 v5, vcc_lo, s30, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s31, v6, vcc_lo
global_load_dword v3, v[7:8], off
global_load_dword v5, v[5:6], off
v_add_co_u32 v7, vcc_lo, s28, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s29, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v5, v3
BB98_78:
s_or_b32 exec_lo, exec_lo, s33
BB98_79:
s_or_saveexec_b32 s7, s7
s_xor_b32 exec_lo, exec_lo, s7
s_cbranch_execz BB98_81
v_lshrrev_b32_e32 v0, 7, v0
v_add_nc_u32_e32 v0, s6, v0
v_mul_hi_i32 v3, 0x51eb851f, v0
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 5, v3
v_add_nc_u32_e32 v3, v3, v4
v_and_b32_e32 v4, 0xff, v1
v_mul_lo_u32 v3, 0x64, v3
v_sub_nc_u32_e32 v0, v0, v3
v_lshl_or_b32 v5, v0, 8, v4
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s26, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s27, v1, vcc_lo
v_add_co_u32 v5, vcc_lo, s24, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s25, v6, vcc_lo
global_load_dword v3, v[7:8], off
global_load_dword v5, v[5:6], off
v_add_co_u32 v7, vcc_lo, s22, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s23, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v5, v3
BB98_81:
s_or_b32 exec_lo, exec_lo, s7
BB98_82:
s_or_saveexec_b32 s1, s1
s_xor_b32 exec_lo, exec_lo, s1
s_cbranch_execz BB98_84
v_lshrrev_b32_e32 v0, 7, v0
v_add_nc_u32_e32 v0, s6, v0
v_mul_hi_i32 v3, 0x51eb851f, v0
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 5, v3
v_add_nc_u32_e32 v3, v3, v4
v_and_b32_e32 v4, 0xff, v1
v_mul_lo_u32 v3, 0x64, v3
v_sub_nc_u32_e32 v0, v0, v3
v_lshl_or_b32 v5, v0, 8, v4
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v5, vcc_lo, s20, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s21, v6, vcc_lo
global_load_dword v3, v[7:8], off
global_load_dword v5, v[5:6], off
v_add_co_u32 v7, vcc_lo, s18, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s19, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v5, v3
BB98_84:
s_or_b32 exec_lo, exec_lo, s1
BB98_85:
s_or_saveexec_b32 s0, s0
s_xor_b32 exec_lo, exec_lo, s0
s_cbranch_execz BB98_87
v_lshrrev_b32_e32 v0, 7, v0
v_add_nc_u32_e32 v0, s6, v0
v_mul_hi_i32 v3, 0x51eb851f, v0
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 5, v3
v_add_nc_u32_e32 v3, v3, v4
v_and_b32_e32 v4, 0xff, v1
v_mul_lo_u32 v3, 0x64, v3
v_sub_nc_u32_e32 v0, v0, v3
v_lshl_or_b32 v5, v0, 8, v4
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s16, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s17, v1, vcc_lo
v_add_co_u32 v5, vcc_lo, s14, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s15, v6, vcc_lo
global_load_dword v3, v[7:8], off
global_load_dword v5, v[5:6], off
v_add_co_u32 v7, vcc_lo, s12, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s13, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v5, v3
BB98_87:
s_or_b32 exec_lo, exec_lo, s0
global_load_dword v7, v[7:8], off
v_mov_b32_e32 v5, 0
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_load_dword v4, v[3:4], off
global_load_dword v5, v[0:1], off
s_waitcnt vmcnt(2)
v_add_f32_e32 v0, 0x3727c5ac, v7
v_sqrt_f32_e32 v0, v0
v_div_scale_f32 v1, s0, v0, v0, v6
v_div_scale_f32 v8, vcc_lo, v6, v0, v6
v_rcp_f32_e32 v3, v1
v_fma_f32 v7, -v1, v3, 1.0
v_fmac_f32_e32 v3, v7, v3
v_mul_f32_e32 v7, v8, v3
v_fma_f32 v9, v7, -v1, v8
v_fmac_f32_e32 v7, v9, v3
v_fmac_f32_e64 v8, -v1, v7
v_div_fmas_f32 v1, v8, v3, v7
v_ashrrev_i32_e32 v3, 31, v2
v_div_fixup_f32 v6, v1, v0, v6
v_lshlrev_b64 v[0:1], 1, v[2:3]
s_waitcnt vmcnt(0)
v_fma_mixlo_f16 v2, v6, v4, v5
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_short v[0:1], v2, off
BB98_88:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_subtract_add_sqrt_divide_multiply_ad_680b67fb8a56ff9f__kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 168
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 52
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end98:
.size tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_subtract_add_sqrt_divide_multiply_ad_680b67fb8a56ff9f__kernel0, .Lfunc_end98-tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_subtract_add_sqrt_divide_multiply_ad_680b67fb8a56ff9f__kernel0
.globl tvmgen_default_fused_transpose_reshape_1_kernel0
.p2align 8
.type tvmgen_default_fused_transpose_reshape_1_kernel0,@function
tvmgen_default_fused_transpose_reshape_1_kernel0:
v_lshrrev_b32_e32 v1, 2, v0
v_lshlrev_b32_e32 v2, 1, v0
v_bfe_u32 v0, v0, 4, 3
s_load_dwordx2 s[0:1], s[4:5], 0x8
v_and_b32_e32 v1, 0xe0, v1
v_lshl_add_u32 v1, s6, 6, v1
v_and_or_b32 v1, v2, 30, v1
v_mad_u32_u24 v0, 0xc80, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_load_dwordx2 s[0:1], s[4:5], 0x0
global_load_dword v3, v[0:1], off
v_lshl_add_u32 v0, s6, 9, v2
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_dword v[0:1], v3, off
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_transpose_reshape_1_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end99:
.size tvmgen_default_fused_transpose_reshape_1_kernel0, .Lfunc_end99-tvmgen_default_fused_transpose_reshape_1_kernel0
.globl tvmgen_default_fused_transpose_reshape_kernel0
.p2align 8
.type tvmgen_default_fused_transpose_reshape_kernel0,@function
tvmgen_default_fused_transpose_reshape_kernel0:
s_clause 0x1
s_load_dwordx2 s[2:3], s[4:5], 0x0
s_load_dwordx2 s[4:5], s[4:5], 0x8
v_lshlrev_b32_e32 v1, 1, v0
s_lshl_b32 s7, s6, 9
v_lshl_add_u32 v3, s6, 8, v0
s_mov_b32 s8, 0x25800
s_lshl_b32 s6, s6, 1
v_add_nc_u32_e32 v4, s7, v1
v_cmp_gt_i32_e64 s0, 0x12c00, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v3
v_cmp_gt_i32_e64 s1, s8, v4
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB100_2
v_lshrrev_b32_e32 v2, 7, v0
v_add_nc_u32_e32 v2, s6, v2
v_mul_hi_i32 v5, 0x1b4e81b5, v2
v_lshrrev_b32_e32 v6, 31, v5
v_ashrrev_i32_e32 v5, 6, v5
v_add_nc_u32_e32 v5, v5, v6
v_bfe_u32 v6, v0, 4, 3
v_mul_lo_u32 v5, 0x258, v5
v_mul_u32_u24_e32 v6, 0x4b00, v6
v_sub_nc_u32_e32 v2, v2, v5
v_lshl_add_u32 v2, v2, 5, v6
v_and_or_b32 v5, v1, 30, v2
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 1, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, s0, s4, v5
v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
global_load_ushort v2, v[5:6], off
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[5:6], 1, v[4:5]
v_add_co_u32 v5, s0, s2, v5
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
s_waitcnt vmcnt(0)
global_store_short v[5:6], v2, off
BB100_2:
s_or_b32 exec_lo, exec_lo, s1
v_or_b32_e32 v2, 1, v1
s_xor_b32 s1, vcc_lo, -1
v_add_nc_u32_e32 v5, s7, v2
v_cmp_gt_i32_e64 s0, s8, v5
s_and_b32 s1, s0, s1
s_and_saveexec_b32 s0, s1
s_cbranch_execz BB100_4
v_lshrrev_b32_e32 v6, 7, v0
v_add_nc_u32_e32 v6, s6, v6
v_mul_hi_i32 v7, 0x1b4e81b5, v6
v_lshrrev_b32_e32 v8, 31, v7
v_ashrrev_i32_e32 v7, 6, v7
v_add_nc_u32_e32 v7, v7, v8
v_bfe_u32 v8, v0, 4, 3
v_mul_lo_u32 v7, 0x258, v7
v_mul_u32_u24_e32 v8, 0x4b00, v8
v_sub_nc_u32_e32 v6, v6, v7
v_lshl_add_u32 v6, v6, 5, v8
v_and_or_b32 v6, v2, 31, v6
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 1, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_ushort v8, v[6:7], off
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[6:7], 1, v[5:6]
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_short v[6:7], v8, off
BB100_4:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s7, 0x20000
v_add_nc_u32_e32 v6, 0x10000, v3
v_add_nc_u32_e32 v3, s7, v4
s_mov_b32 s8, 0x25800
s_addk_i32 s6, 0x200
v_cmp_gt_i32_e64 s0, 0x12c00, v6
v_cmp_gt_i32_e64 s1, s8, v3
v_cmp_lt_i32_e32 vcc_lo, 0x12bff, v6
s_and_b32 s0, s1, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB100_6
v_lshrrev_b32_e32 v4, 7, v0
v_add_nc_u32_e32 v4, s6, v4
v_mul_hi_i32 v6, 0x1b4e81b5, v4
v_lshrrev_b32_e32 v7, 31, v6
v_ashrrev_i32_e32 v6, 6, v6
v_add_nc_u32_e32 v6, v6, v7
v_bfe_u32 v7, v0, 4, 3
v_mul_lo_u32 v6, 0x258, v6
v_mul_u32_u24_e32 v7, 0x4b00, v7
v_sub_nc_u32_e32 v4, v4, v6
v_lshl_add_u32 v4, v4, 5, v7
v_and_or_b32 v6, v1, 30, v4
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_lshlrev_b64 v[6:7], 1, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, s0, s4, v6
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
v_add_co_u32 v3, s0, s2, v3
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
global_load_ushort v1, v[6:7], off
s_waitcnt vmcnt(0)
global_store_short v[3:4], v1, off
BB100_6:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, s7, v5
s_xor_b32 s1, vcc_lo, -1
v_cmp_gt_i32_e64 s0, s8, v1
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz BB100_8
v_lshrrev_b32_e32 v3, 7, v0
v_bfe_u32 v0, v0, 4, 3
v_add_nc_u32_e32 v3, s6, v3
v_mul_u32_u24_e32 v0, 0x4b00, v0
v_mul_hi_i32 v4, 0x1b4e81b5, v3
v_lshrrev_b32_e32 v5, 31, v4
v_ashrrev_i32_e32 v4, 6, v4
v_add_nc_u32_e32 v4, v4, v5
v_mul_lo_u32 v4, 0x258, v4
v_sub_nc_u32_e32 v3, v3, v4
v_lshl_add_u32 v0, v3, 5, v0
v_and_or_b32 v2, v2, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_ushort v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 1, v[1:2]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_short v[0:1], v3, off
BB100_8:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_transpose_reshape_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 9
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end100:
.size tvmgen_default_fused_transpose_reshape_kernel0, .Lfunc_end100-tvmgen_default_fused_transpose_reshape_kernel0
.globl tvmgen_default_fused_variance_1_kernel0
.p2align 8
.type tvmgen_default_fused_variance_1_kernel0,@function
tvmgen_default_fused_variance_1_kernel0:
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_lshl_add_u32 v1, s6, 8, v0
s_load_dwordx2 s[2:3], s[4:5], 0x8
s_ashr_i32 s7, s6, 31
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_lshl_b64 s[0:1], s[6:7], 2
v_cmp_gt_i32_e32 vcc_lo, 16, v0
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_clause 0x7
global_load_dword v3, v[1:2], off
global_load_dword v4, v[1:2], off offset:128
global_load_dword v5, v[1:2], off offset:256
global_load_dword v6, v[1:2], off offset:384
global_load_dword v7, v[1:2], off offset:512
global_load_dword v8, v[1:2], off offset:640
global_load_dword v9, v[1:2], off offset:768
global_load_dword v1, v[1:2], off offset:896
s_load_dword s0, s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
v_subrev_f32_e32 v2, s0, v3
v_subrev_f32_e32 v3, s0, v4
v_subrev_f32_e32 v4, s0, v5
v_fma_f32 v2, v2, v2, 0
v_fmac_f32_e32 v2, v3, v3
v_subrev_f32_e32 v3, s0, v6
v_fmac_f32_e32 v2, v4, v4
v_subrev_f32_e32 v4, s0, v7
v_fmac_f32_e32 v2, v3, v3
v_subrev_f32_e32 v3, s0, v8
v_fmac_f32_e32 v2, v4, v4
v_subrev_f32_e32 v4, s0, v9
v_fmac_f32_e32 v2, v3, v3
v_subrev_f32_e32 v3, s0, v1
v_lshlrev_b32_e32 v1, 2, v0
v_fmac_f32_e32 v2, v4, v4
v_fmac_f32_e32 v2, v3, v3
ds_write_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB101_2
ds_read_b32 v2, v1 offset:64
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
ds_read_b32 v2, v1 offset:32
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
ds_read_b32 v2, v1 offset:16
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
ds_read_b32 v2, v1 offset:8
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
ds_read_b32 v2, v1 offset:4
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
BB101_2:
s_or_b32 exec_lo, exec_lo, s0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_barrier
v_cmp_gt_i32_e32 vcc_lo, 1, v0
ds_read_b32 v2, v1
s_waitcnt lgkmcnt(0)
ds_write_b32 v1, v2 offset:128
s_waitcnt lgkmcnt(0)
s_barrier
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB101_4
v_lshlrev_b32_e32 v1, 2, v0
s_load_dwordx2 s[0:1], s[4:5], 0x10
v_add_nc_u32_e32 v0, s6, v0
ds_read_b32 v2, v1 offset:128
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_mul_f32_e32 v2, 0x3b800000, v2
global_store_dword v[0:1], v2, off
BB101_4:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_variance_1_kernel0
.amdhsa_group_segment_fixed_size 132
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end101:
.size tvmgen_default_fused_variance_1_kernel0, .Lfunc_end101-tvmgen_default_fused_variance_1_kernel0
.globl tvmgen_default_fused_variance_kernel0
.p2align 8
.type tvmgen_default_fused_variance_kernel0,@function
tvmgen_default_fused_variance_kernel0:
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_lshl_add_u32 v1, s6, 8, v0
s_load_dwordx2 s[2:3], s[4:5], 0x8
s_ashr_i32 s7, s6, 31
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_lshl_b64 s[0:1], s[6:7], 2
v_cmp_gt_i32_e32 vcc_lo, 16, v0
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_clause 0x7
global_load_dword v3, v[1:2], off
global_load_dword v4, v[1:2], off offset:128
global_load_dword v5, v[1:2], off offset:256
global_load_dword v6, v[1:2], off offset:384
global_load_dword v7, v[1:2], off offset:512
global_load_dword v8, v[1:2], off offset:640
global_load_dword v9, v[1:2], off offset:768
global_load_dword v1, v[1:2], off offset:896
s_load_dword s0, s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
v_subrev_f32_e32 v2, s0, v3
v_subrev_f32_e32 v3, s0, v4
v_subrev_f32_e32 v4, s0, v5
v_fma_f32 v2, v2, v2, 0
v_fmac_f32_e32 v2, v3, v3
v_subrev_f32_e32 v3, s0, v6
v_fmac_f32_e32 v2, v4, v4
v_subrev_f32_e32 v4, s0, v7
v_fmac_f32_e32 v2, v3, v3
v_subrev_f32_e32 v3, s0, v8
v_fmac_f32_e32 v2, v4, v4
v_subrev_f32_e32 v4, s0, v9
v_fmac_f32_e32 v2, v3, v3
v_subrev_f32_e32 v3, s0, v1
v_lshlrev_b32_e32 v1, 2, v0
v_fmac_f32_e32 v2, v4, v4
v_fmac_f32_e32 v2, v3, v3
ds_write_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB102_2
ds_read_b32 v2, v1 offset:64
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
ds_read_b32 v2, v1 offset:32
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
ds_read_b32 v2, v1 offset:16
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
ds_read_b32 v2, v1 offset:8
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
ds_read_b32 v2, v1 offset:4
ds_read_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_write_b32 v1, v2
BB102_2:
s_or_b32 exec_lo, exec_lo, s0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_barrier
v_cmp_gt_i32_e32 vcc_lo, 1, v0
ds_read_b32 v2, v1
s_waitcnt lgkmcnt(0)
ds_write_b32 v1, v2 offset:128
s_waitcnt lgkmcnt(0)
s_barrier
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB102_4
v_lshlrev_b32_e32 v1, 2, v0
s_load_dwordx2 s[0:1], s[4:5], 0x10
v_add_nc_u32_e32 v0, s6, v0
ds_read_b32 v2, v1 offset:128
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_mul_f32_e32 v2, 0x3b800000, v2
global_store_dword v[0:1], v2, off
BB102_4:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_variance_kernel0
.amdhsa_group_segment_fixed_size 132
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end102:
.size tvmgen_default_fused_variance_kernel0, .Lfunc_end102-tvmgen_default_fused_variance_kernel0
.globl tvmgen_default_fused_zeros_cast_stack_expand_dims_cast_image_resize2d_take_kernel0
.p2align 8
.type tvmgen_default_fused_zeros_cast_stack_expand_dims_cast_image_resize2d_take_kernel0,@function
tvmgen_default_fused_zeros_cast_stack_expand_dims_cast_image_resize2d_take_kernel0:
v_lshl_add_u32 v0, s6, 8, v0
v_cmp_gt_i32_e32 vcc_lo, 0x258, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz BB103_2
s_load_dwordx2 s[0:1], s[4:5], 0x0
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_dword v[0:1], v2, off
BB103_2:
s_endpgm
.section .rodata,#alloc
.p2align 6
.amdhsa_kernel tvmgen_default_fused_zeros_cast_stack_expand_dims_cast_image_resize2d_take_kernel0
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_flat_scratch_init 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_system_sgpr_private_segment_wavefront_offset 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_flat_scratch 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end103:
.size tvmgen_default_fused_zeros_cast_stack_expand_dims_cast_image_resize2d_take_kernel0, .Lfunc_end103-tvmgen_default_fused_zeros_cast_stack_expand_dims_cast_image_resize2d_take_kernel0
.protected __ockl_sanitizer_report
.weak __ockl_sanitizer_report
.p2align 2
.type __ockl_sanitizer_report,@function
__ockl_sanitizer_report:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_load_dwordx2 s[6:7], s[4:5], 0x18
v_mbcnt_lo_u32_b32 v16, -1, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v19, 0
v_mbcnt_hi_u32_b32 v20, -1, v16
;;#ASMSTART
; ockl readfirstlane hoisting hack v20
;;#ASMEND
v_readfirstlane_b32 s4, v20
v_cmp_eq_u32_e64 s4, s4, v20
s_and_saveexec_b32 s5, s4
s_cbranch_execz BB104_6
v_mov_b32_e32 v23, 0
s_waitcnt lgkmcnt(0)
global_load_dwordx2 v[18:19], v23, s[6:7] offset:24 glc dlc
s_waitcnt vmcnt(0)
buffer_gl0_inv
buffer_gl1_inv
s_clause 0x1
global_load_dwordx2 v[16:17], v23, s[6:7] offset:40
global_load_dwordx2 v[21:22], v23, s[6:7]
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v24, v16, 24
v_mul_lo_u32 v16, v16, 24
v_add_nc_u32_e32 v17, v24, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v21, v16
v_add_co_ci_u32_e32 v17, vcc_lo, v22, v17, vcc_lo
global_load_dwordx2 v[16:17], v[16:17], off glc dlc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_x2 v[23:24], v23, v[16:19], s[6:7] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl0_inv
buffer_gl1_inv
v_cmp_ne_u64_e32 vcc_lo, v[23:24], v[18:19]
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz BB104_5
s_mov_b32 s9, 0
.p2align 6
BB104_3:
v_mov_b32_e32 v25, 0
s_sleep 1
s_clause 0x1
global_load_dwordx2 v[16:17], v25, s[6:7] offset:40
global_load_dwordx2 v[18:19], v25, s[6:7]
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v24
v_and_b32_e32 v16, v16, v23
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v18, v16
v_add_co_ci_u32_e32 v17, vcc_lo, v19, v17, vcc_lo
v_mov_b32_e32 v18, v23
v_mov_b32_e32 v19, v24
global_load_dwordx2 v[21:22], v[16:17], off glc dlc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_x2 v[16:17], v25, v[21:24], s[6:7] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl0_inv
buffer_gl1_inv
v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[23:24]
v_mov_b32_e32 v24, v17
v_mov_b32_e32 v23, v16
s_or_b32 s9, vcc_lo, s9
s_andn2_b32 exec_lo, exec_lo, s9
s_cbranch_execnz BB104_3
s_or_b32 exec_lo, exec_lo, s9
BB104_5:
s_or_b32 exec_lo, exec_lo, s8
BB104_6:
s_or_b32 exec_lo, exec_lo, s5
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s8, v18
v_readfirstlane_b32 s5, v19
s_mov_b64 s[10:11], exec
s_waitcnt lgkmcnt(0)
s_clause 0x2
global_load_dwordx2 v[24:25], v21, s[6:7] offset:40
global_load_dwordx2 v[16:17], v21, s[6:7]
global_load_dwordx2 v[22:23], v21, s[6:7] offset:8
s_waitcnt vmcnt(2)
v_and_b32_e32 v18, s8, v24
v_and_b32_e32 v19, s5, v25
s_and_saveexec_b32 s9, s4
s_cbranch_execz BB104_8
v_mul_lo_u32 v21, v19, 24
v_mul_hi_u32 v26, v18, 24
v_mul_lo_u32 v27, v18, 24
v_mov_b32_e32 v25, s11
v_mov_b32_e32 v24, s10
v_add_nc_u32_e32 v21, v26, v21
s_waitcnt vmcnt(1)
v_add_co_u32 v28, vcc_lo, v16, v27
v_mov_b32_e32 v26, 4
v_mov_b32_e32 v27, 1
v_add_co_ci_u32_e32 v29, vcc_lo, v17, v21, vcc_lo
global_store_dwordx2 v[28:29], v[24:25], off offset:8
global_store_dwordx2 v[28:29], v[26:27], off offset:16
BB104_8:
s_or_b32 exec_lo, exec_lo, s9
v_mov_b32_e32 v21, 0
v_lshlrev_b64 v[24:25], 12, v[18:19]
v_lshlrev_b64 v[20:21], 6, v[20:21]
s_waitcnt vmcnt(0)
v_add_co_u32 v22, vcc_lo, v22, v24
v_add_co_ci_u32_e32 v23, vcc_lo, v23, v25, vcc_lo
v_add_co_u32 v20, vcc_lo, v22, v20
v_add_co_ci_u32_e32 v21, vcc_lo, v23, v21, vcc_lo
global_store_dwordx4 v[20:21], v[0:3], off
global_store_dwordx4 v[20:21], v[4:7], off offset:16
global_store_dwordx4 v[20:21], v[8:11], off offset:32
global_store_dwordx4 v[20:21], v[12:15], off offset:48
s_and_saveexec_b32 s9, s4
s_cbranch_execz BB104_14
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v4, s8
v_mov_b32_e32 v5, s5
s_clause 0x1
global_load_dwordx2 v[6:7], v2, s[6:7] offset:32 glc dlc
global_load_dwordx2 v[0:1], v2, s[6:7] offset:40
s_waitcnt vmcnt(0)
v_and_b32_e32 v1, s5, v1
v_and_b32_e32 v0, s8, v0
v_mul_lo_u32 v1, v1, 24
v_mul_hi_u32 v3, v0, 24
v_mul_lo_u32 v0, v0, 24
v_add_nc_u32_e32 v1, v3, v1
v_add_co_u32 v0, vcc_lo, v16, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v17, v1, vcc_lo
global_store_dwordx2 v[0:1], v[6:7], off
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_x2 v[4:5], v2, v[4:7], s[6:7] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[6:7]
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz BB104_12
s_mov_b32 s11, 0
BB104_11:
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v2, s8
v_mov_b32_e32 v3, s5
s_sleep 1
global_store_dwordx2 v[0:1], v[4:5], off
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_x2 v[2:3], v6, v[2:5], s[6:7] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_mov_b32_e32 v5, v3
v_mov_b32_e32 v4, v2
s_or_b32 s11, vcc_lo, s11
s_andn2_b32 exec_lo, exec_lo, s11
s_cbranch_execnz BB104_11
BB104_12:
s_or_b32 exec_lo, exec_lo, s10
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 1
v_mov_b32_e32 v3, 0
global_load_dwordx2 v[4:5], v1, s[6:7] offset:16
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
s_clause 0x1
global_atomic_add_x2 v[4:5], v[2:3], off offset:8
global_load_dwordx2 v[2:3], v[4:5], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_and_b32 vcc_lo, exec_lo, vcc_lo
s_cbranch_vccnz BB104_14
global_load_dword v0, v[4:5], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s10, v0
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
global_store_dwordx2 v[2:3], v[0:1], off
s_and_b32 m0, s10, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
BB104_14:
s_or_b32 exec_lo, exec_lo, s9
v_mul_lo_u32 v0, v19, 24
v_mul_hi_u32 v1, v18, 24
v_mul_lo_u32 v2, v18, 24
v_add_nc_u32_e32 v0, v1, v0
v_add_co_u32 v1, vcc_lo, v16, v2
v_add_co_ci_u32_e32 v2, vcc_lo, v17, v0, vcc_lo
v_add_co_u32 v0, vcc_lo, v1, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo
s_branch BB104_16
BB104_15:
s_andn2_b32 vcc_lo, exec_lo, s9
s_cbranch_vccz BB104_20
BB104_16:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s9, s4
s_cbranch_execz BB104_18
global_load_dword v2, v[0:1], off glc dlc
s_waitcnt vmcnt(0)
buffer_gl0_inv
buffer_gl1_inv
v_and_b32_e32 v2, 1, v2
BB104_18:
s_or_b32 exec_lo, exec_lo, s9
v_readfirstlane_b32 s9, v2
s_cmp_eq_u32 s9, 0
s_mov_b32 s9, -1
s_cbranch_scc1 BB104_15
s_mov_b32 s9, 0
s_sleep 1
s_branch BB104_15
BB104_20:
s_and_saveexec_b32 s9, s4
s_cbranch_execz BB104_24
v_mov_b32_e32 v8, 0
s_clause 0x2
global_load_dwordx2 v[2:3], v8, s[6:7] offset:40
global_load_dwordx2 v[6:7], v8, s[6:7] offset:24 glc dlc
global_load_dwordx2 v[4:5], v8, s[6:7]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, v9, s8
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_cndmask_b32_e32 v1, v1, v10, vcc_lo
v_cndmask_b32_e32 v0, v0, v9, vcc_lo
v_and_b32_e32 v3, v1, v3
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v6
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v7
global_store_dwordx2 v[4:5], v[6:7], off
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_x2 v[2:3], v8, v[0:3], s[6:7] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz BB104_24
s_mov_b32 s4, 0
BB104_23:
v_mov_b32_e32 v6, 0
s_sleep 1
global_store_dwordx2 v[4:5], v[2:3], off
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_x2 v[6:7], v6, v[0:3], s[6:7] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
v_mov_b32_e32 v2, v6
v_mov_b32_e32 v3, v7
s_or_b32 s4, vcc_lo, s4
s_andn2_b32 exec_lo, exec_lo, s4
s_cbranch_execnz BB104_23
BB104_24:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_setpc_b64 s[30:31]
.Lfunc_end104:
.size __ockl_sanitizer_report, .Lfunc_end104-__ockl_sanitizer_report
.p2alignl 6, 3214868480
.fill 48, 4, 3214868480
.ident "AMD clang version 13.0.0 (https://github.com/RadeonOpenCompute/llvm-project roc-4.5.2 21432 9bbd96fd1936641cd47defd8022edafd063019d5)"
.section ".note.GNU-stack"
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_add_reshape_cast_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_add_reshape_cast_1_kernel0.kd
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_add_reshape_cast_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 13
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_add_reshape_cast_kernel0.kd
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_cast_add_reshape_cast_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 13
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_cast_add_reshape_cast_kernel0.kd
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_cast_logical_not_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_cast_logical_not_kernel0.kd
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_cast_split_squeeze_stack_layout_transform_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_cast_split_squeeze_stack_layout_transform_kernel0.kd
.vgpr_count: 57
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_cumsum_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_cumsum_1_kernel0.kd
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_cumsum_1_kernel1
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_cumsum_1_kernel1.kd
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_cumsum_1_kernel2
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_cumsum_1_kernel2.kd
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_cumsum_1_kernel3
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_cumsum_1_kernel3.kd
.vgpr_count: 1
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_cumsum_1_kernel4
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_cumsum_1_kernel4.kd
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_cumsum_1_kernel5
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_cumsum_1_kernel5.kd
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_cumsum_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_cumsum_kernel0.kd
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_cumsum_kernel1
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_cumsum_kernel1.kd
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_cumsum_kernel2
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_cumsum_kernel2.kd
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_cumsum_kernel3
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_cumsum_kernel3.kd
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_cumsum_kernel4
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_cumsum_kernel4.kd
.vgpr_count: 1
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_cumsum_kernel5
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_cumsum_kernel5.kd
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_cumsum_kernel6
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_cumsum_kernel6.kd
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_cumsum_kernel7
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_cumsum_kernel7.kd
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_layout_transform_reshape_squeeze_transpose_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 11
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_layout_transform_reshape_squeeze_transpose_kernel0.kd
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 132
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_mean_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_mean_1_kernel0.kd
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 132
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_mean_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_mean_kernel0.kd
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 9120
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_batch_matmul_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_batch_matmul_1_kernel0.kd
.vgpr_count: 92
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2240
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_batch_matmul_2_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_batch_matmul_2_kernel0.kd
.vgpr_count: 124
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 5632
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_batch_matmul_cast_add_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 17
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_batch_matmul_cast_add_1_kernel0.kd
.vgpr_count: 118
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 1920
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_batch_matmul_cast_add_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_batch_matmul_cast_add_kernel0.kd
.vgpr_count: 56
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 480
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_batch_matmul_cast_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 17
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_batch_matmul_cast_kernel0.kd
.vgpr_count: 78
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 1760
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_batch_matmul_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 15
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_batch_matmul_kernel0.kd
.vgpr_count: 75
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel0.kd
.vgpr_count: 29
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 1824
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel1
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel1.kd
.vgpr_count: 67
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel2
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel2.kd
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel3
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_1_kernel3.kd
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel0.kd
.vgpr_count: 29
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 9152
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel1
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel1.kd
.vgpr_count: 88
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel2
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel2.kd
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel3
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_2_kernel3.kd
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel0.kd
.vgpr_count: 57
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 38144
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel1
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel1.kd
.vgpr_count: 110
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel2
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel2.kd
.vgpr_count: 60
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel3
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_3_kernel3.kd
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 15
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel0.kd
.vgpr_count: 29
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 1664
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel1
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel1.kd
.vgpr_count: 82
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel2
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel2.kd
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel3
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_contrib_conv2d_winograd_without_weight_transform_add_nn_relu_kernel3.kd
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 42176
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_1_kernel0.kd
.vgpr_count: 111
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 34336
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_2_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_2_kernel0.kd
.vgpr_count: 102
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 21088
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_3_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_3_kernel0.kd
.vgpr_count: 61
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 35328
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_4_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_4_kernel0.kd
.vgpr_count: 64
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 29184
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_add_nn_relu_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 30
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_add_nn_relu_1_kernel0.kd
.vgpr_count: 112
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 8272
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_add_nn_relu_2_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_add_nn_relu_2_kernel0.kd
.vgpr_count: 86
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 4864
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_add_nn_relu_3_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_add_nn_relu_3_kernel0.kd
.vgpr_count: 114
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 9216
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_add_nn_relu_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_add_nn_relu_kernel0.kd
.vgpr_count: 49
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 22784
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_kernel0.kd
.vgpr_count: 100
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 19928
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_nn_relu_10_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_nn_relu_10_kernel0.kd
.vgpr_count: 126
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 37888
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_nn_relu_11_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_nn_relu_11_kernel0.kd
.vgpr_count: 112
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 6912
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_nn_relu_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_nn_relu_1_kernel0.kd
.vgpr_count: 64
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 28672
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_nn_relu_2_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_nn_relu_2_kernel0.kd
.vgpr_count: 118
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 26624
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_nn_relu_3_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_nn_relu_3_kernel0.kd
.vgpr_count: 64
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 7152
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_nn_relu_4_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_nn_relu_4_kernel0.kd
.vgpr_count: 113
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 3328
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_nn_relu_5_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_nn_relu_5_kernel0.kd
.vgpr_count: 76
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 9472
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_nn_relu_6_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_nn_relu_6_kernel0.kd
.vgpr_count: 93
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 18936
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_nn_relu_7_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_nn_relu_7_kernel0.kd
.vgpr_count: 60
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 39168
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_nn_relu_8_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 17
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_nn_relu_8_kernel0.kd
.vgpr_count: 63
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 39168
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_nn_relu_9_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 27
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_nn_relu_9_kernel0.kd
.vgpr_count: 112
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 36672
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_conv2d_add_nn_relu_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_conv2d_add_nn_relu_kernel0.kd
.vgpr_count: 82
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 34688
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_dense_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 15
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_dense_1_kernel0.kd
.vgpr_count: 122
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2304
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_dense_2_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_dense_2_kernel0.kd
.vgpr_count: 102
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 320
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_dense_3_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_dense_3_kernel0.kd
.vgpr_count: 36
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2624
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_dense_4_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_dense_4_kernel0.kd
.vgpr_count: 79
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 1152
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_dense_5_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_dense_5_kernel0.kd
.vgpr_count: 53
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 42496
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_dense_6_kernel0
.private_segment_fixed_size: 296
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_dense_6_kernel0.kd
.vgpr_count: 128
.vgpr_spill_count: 73
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_dense_7_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 13
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_dense_7_kernel0.kd
.vgpr_count: 98
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 29184
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_dense_kernel0
.private_segment_fixed_size: 60
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_dense_kernel0.kd
.vgpr_count: 128
.vgpr_spill_count: 14
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_max_pool2d_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 11
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_max_pool2d_kernel0.kd
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 8
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_softmax_cast_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_softmax_cast_1_kernel0.kd
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 408
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_softmax_cast_2_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_softmax_cast_2_kernel0.kd
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 8
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_nn_softmax_cast_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_nn_softmax_cast_kernel0.kd
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_add_add_cast_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 13
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_add_add_cast_kernel0.kd
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_add_cast_add_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_add_cast_add_1_kernel0.kd
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_add_cast_add_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 13
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_add_cast_add_kernel0.kd
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_add_nn_relu_reshape_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_add_nn_relu_reshape_1_kernel0.kd
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_add_nn_relu_reshape_2_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 13
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_add_nn_relu_reshape_2_kernel0.kd
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_add_nn_relu_reshape_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_add_nn_relu_reshape_kernel0.kd
.vgpr_count: 46
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_add_reshape_transpose_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_add_reshape_transpose_1_kernel0.kd
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_add_reshape_transpose_2_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_add_reshape_transpose_2_kernel0.kd
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_add_reshape_transpose_3_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_add_reshape_transpose_3_kernel0.kd
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_add_reshape_transpose_divide_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_add_reshape_transpose_divide_1_kernel0.kd
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_add_reshape_transpose_divide_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 15
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_add_reshape_transpose_divide_kernel0.kd
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_add_reshape_transpose_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 13
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_add_reshape_transpose_kernel0.kd
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_add_sigmoid_take_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_add_sigmoid_take_kernel0.kd
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_add_take_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_add_take_kernel0.kd
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_cast_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_cast_1_kernel0.kd
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_cast_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 11
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_cast_kernel0.kd
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 11
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_kernel0.kd
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_reshape_squeeze_reshape_repeat_reshape_zeros_where_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_reshape_squeeze_reshape_repeat_reshape_zeros_where_kernel0.kd
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_strided_slice_add_divide_multiply_expand_dims_divide_strided_slice_sin_str_dbf4827b0a4481cc__kernel0
.private_segment_fixed_size: 0
.sgpr_count: 56
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_strided_slice_add_divide_multiply_expand_dims_divide_strided_slice_sin_str_dbf4827b0a4481cc__kernel0.kd
.vgpr_count: 24
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_1_kernel0.kd
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_kernel0.kd
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 96
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 104
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 112
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 120
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 128
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 136
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 144
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 152
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 160
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 168
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_subtract_add_sqrt_divide_multiply_ad_680b67fb8a56ff9f__kernel0
.private_segment_fixed_size: 0
.sgpr_count: 54
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_subtract_add_sqrt_divide_multiply_add_subtract_add_sqrt_divide_multiply_ad_680b67fb8a56ff9f__kernel0.kd
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_transpose_reshape_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_transpose_reshape_1_kernel0.kd
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_transpose_reshape_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 11
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_transpose_reshape_kernel0.kd
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 132
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_variance_1_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_variance_1_kernel0.kd
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 132
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_variance_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_variance_kernel0.kd
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: tvmgen_default_fused_zeros_cast_stack_expand_dims_cast_image_resize2d_take_kernel0
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: tvmgen_default_fused_zeros_cast_stack_expand_dims_cast_image_resize2d_take_kernel0.kd
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
amdhsa.target: amdgcn-amd-amdhsa-hcc-gfx1032
amdhsa.version:
- 1
- 1
...
.end_amdgpu_metadata
|
matgla/tinycc | 18,280 | lib/atomic.S | /* ---------------------------------------------- */
/* This file implements for arm/arm64/riscv:
* __atomic_compare_exchange_1
* __atomic_compare_exchange_2
* __atomic_compare_exchange_4
* __atomic_compare_exchange_8
*/
#ifdef __leading_underscore
# define _(s) _##s
#else
# define _(s) s
#endif
#if defined __i386__
.text
.align 2
.global _(__atomic_test_and_set)
.type _(__atomic_test_and_set), %function
_(__atomic_test_and_set):
movl 4(%esp), %edx
movl $1, %eax
xchgb (%edx), %al
ret
.size _(__atomic_test_and_set), .-_(__atomic_test_and_set)
.global _(__atomic_clear)
.type _(__atomic_clear), %function
_(__atomic_clear):
movl 4(%esp), %edx
xorl %eax, %eax
xchgb (%edx), %al
ret
.size _(__atomic_clear), .-_(__atomic_clear)
#elif defined __x86_64__
.text
.align 2
.global _(__atomic_test_and_set)
.type _(__atomic_test_and_set), %function
_(__atomic_test_and_set):
movl $1, %eax
xchgb (%rdi), %al
ret
.size _(__atomic_test_and_set), .-_(__atomic_test_and_set)
.global _(__atomic_clear)
.type _(__atomic_clear), %function
_(__atomic_clear):
xorl %eax, %eax
xchgb (%rdi), %al
ret
.size _(__atomic_clear), .-_(__atomic_clear)
#elif defined __arm__
#ifndef __TINYC__
.arch armv6k
.syntax unified
#endif
.text
.align 2
.global _(fetch_and_add_arm)
.type _(fetch_and_add_arm), %function
_(fetch_and_add_arm):
mcr p15, #0, r0, c7, c10, #5
.L0:
ldrex r3, [r0]
add r3, r3, r1
strex r2, r3, [r0]
cmp r2, #0
bne .L0
mcr p15, #0, r0, c7, c10, #5
bx lr
.size _(fetch_and_add_arm), .-_(fetch_and_add_arm)
.global _(__atomic_test_and_set)
.type _(__atomic_test_and_set), %function
_(__atomic_test_and_set):
#ifdef __TINYC__
.int 0xe92d4030
.int 0xee070fba
.int 0xe5d03000
.int 0xe24dd014
.int 0xe1a05000
.int 0xe2533000
.int 0xe1a04001
.int 0x13a03001
.int 0xee070fba
.int 0xe5cd300f
.int 0xe3a03001
.int 0xe1a02003
.int 0xe28d100f
.int 0xe1a00005
.int 0xe58d4004
.int 0xe58d4000
.int 0xeb000009
.int 0xe3500000
.int 0x0afffff6
.int 0xe5dd000f
.int 0xe28dd014
.int 0xe8bd8030
#else
push {r4, r5, lr}
mcr p15, 0, r0, c7, c10, 5
ldrb r3, [r0]
sub sp, sp, #20
mov r5, r0
subs r3, r3, #0
mov r4, r1
movne r3, #1
mcr p15, 0, r0, c7, c10, 5
strb r3, [sp, #15]
.L20:
mov r3, #1
mov r2, r3
add r1, sp, #15
mov r0, r5
str r4, [sp, #4]
str r4, [sp]
bl __atomic_compare_exchange_1
cmp r0, #0
beq .L20
ldrb r0, [sp, #15]
add sp, sp, #20
pop {r4, r5, pc}
#endif
.size _(__atomic_test_and_set), .-_(__atomic_test_and_set)
.global _(__atomic_clear)
.type _(__atomic_clear), %function
_(__atomic_clear):
#ifdef __TINYC__
.int 0xe3a03000
.int 0xee070fba
.int 0xe5c03000
.int 0xee070fba
.int 0xe12fff1e
#else
mov r3, #0
mcr p15, 0, r0, c7, c10, 5
strb r3, [r0]
mcr p15, 0, r0, c7, c10, 5
bx lr
#endif
.size _(__atomic_clear), .-_(__atomic_clear)
.global _(__atomic_compare_exchange_1)
.type _(__atomic_compare_exchange_1), %function
_(__atomic_compare_exchange_1):
#ifdef __TINYC__
.int 0xe52de004
.int 0xe5d13000
.int 0xf57ff05b
.int 0xe1d0cf9f
.int 0xe15c0003
.int 0x1a000002
.int 0xe1c0ef92
.int 0xe35e0000
.int 0x1afffff9
.int 0x03a00001
.int 0x13a00000
.int 0xf57ff05b
.int 0x15c1c000
.int 0xe49df004
#else
str lr, [sp, #-4]!
ldrb r3, [r1]
mcr p15, 0, r0, c7, c10, 5
.L1:
ldrexb ip, [r0]
cmp ip, r3
bne .L2
strexb lr, r2, [r0]
cmp lr, #0
bne .L1
.L2:
mcr p15, 0, r0, c7, c10, 5
moveq r0, #1
movne r0, #0
strbne ip, [r1]
ldr pc, [sp], #4
#endif
.size _(__atomic_compare_exchange_1), .-_(__atomic_compare_exchange_1)
.global _(__atomic_compare_exchange_2)
.type _(__atomic_compare_exchange_2), %function
_(__atomic_compare_exchange_2):
#ifdef __TINYC__
.int 0xe52de004
.int 0xe1d130b0
.int 0xf57ff05b
.int 0xe1f0cf9f
.int 0xe15c0003
.int 0x1a000002
.int 0xe1e0ef92
.int 0xe35e0000
.int 0x1afffff9
.int 0x03a00001
.int 0x13a00000
.int 0xf57ff05b
.int 0x11c1c0b0
.int 0xe49df004
#else
str lr, [sp, #-4]!
ldrh r3, [r1]
mcr p15, 0, r0, c7, c10, 5
.L3:
ldrexh ip, [r0]
cmp ip, r3
bne .L4
strexh lr, r2, [r0]
cmp lr, #0
bne .L3
.L4:
mcr p15, 0, r0, c7, c10, 5
moveq r0, #1
movne r0, #0
strhne ip, [r1]
ldr pc, [sp], #4
#endif
.size _(__atomic_compare_exchange_2), .-_(__atomic_compare_exchange_2)
.global _(__atomic_compare_exchange_4)
.type _(__atomic_compare_exchange_4), %function
_(__atomic_compare_exchange_4):
#ifdef __TINYC__
.int 0xe52de004
.int 0xe5913000
.int 0xf57ff05b
.int 0xe190cf9f
.int 0xe15c0003
.int 0x1a000002
.int 0xe180ef92
.int 0xe35e0000
.int 0x1afffff9
.int 0x03a00001
.int 0x13a00000
.int 0xf57ff05b
.int 0x1581c000
.int 0xe49df004
#else
str lr, [sp, #-4]!
ldr r3, [r1]
mcr p15, 0, r0, c7, c10, 5
.L5:
ldrex ip, [r0]
cmp ip, r3
bne .L6
strex lr, r2, [r0]
cmp lr, #0
bne .L5
.L6:
mcr p15, 0, r0, c7, c10, 5
moveq r0, #1
movne r0, #0
strne ip, [r1]
ldr pc, [sp], #4
#endif
.size _(__atomic_compare_exchange_4), .-_(__atomic_compare_exchange_4)
/* ---------------------------------------------- */
#elif defined __aarch64__
.text
.align 2
.global _(fetch_and_add_arm64)
.type _(fetch_and_add_arm64), %function
_(fetch_and_add_arm64):
#ifdef __TINYC__
.int 0x885f7c02
.int 0x0b010042
.int 0x8803fc02
.int 0x35ffffa3
.int 0xd5033bbf
.int 0xd65f03c0
#else
ldxr w2, [x0]
add w2, w2, w1
stlxr w3, w2, [x0]
cbnz w3, _(fetch_and_add_arm64)
dmb ish
ret
#endif
.size _(fetch_and_add_arm64), .-_(fetch_and_add_arm64)
.global _(__atomic_test_and_set)
.type _(__atomic_test_and_set), %function
_(__atomic_test_and_set):
#ifdef __TINYC__
.int 0xa9bf7bfd
.int 0xaa0003e1
.int 0x52800020
.int 0x910003fd
.int 0x2a0003f0
.int 0x085ffc20
.int 0x0811fc30
.int 0x35ffffd1
.int 0xa8c17bfd
.int 0xd65f03c0
#else
stp x29, x30, [sp, -16]!
mov x1, x0
mov w0, 1
mov x29, sp
mov w16, w0
.L20:
ldaxrb w0, [x1]
stlxrb w17, w16, [x1]
cbnz w17, .L20
ldp x29, x30, [sp], 16
ret
#endif
.size _(__atomic_test_and_set), .-_(__atomic_test_and_set)
.global _(__atomic_clear)
.type _(__atomic_clear), %function
_(__atomic_clear):
#ifdef __TINYC__
.int 0x089ffc1f
.int 0xd65f03c0
#else
stlrb wzr, [x0]
ret
#endif
.size _(__atomic_clear), .-_(__atomic_clear)
.global _(__atomic_compare_exchange_1)
.type _(__atomic_compare_exchange_1), %function
_(__atomic_compare_exchange_1):
#ifdef __TINYC__
.int 0xa9be7bfd
.int 0x910003fd
.int 0xa90153f3
.int 0xaa0103f3
.int 0x12001c41
.int 0xaa0003e2
.int 0x39400274
.int 0x2a1403e0
.int 0x53001c10
.int 0x085ffc40
.int 0x6b10001f
.int 0x54000061
.int 0x0811fc41
.int 0x35ffff91
.int 0x6b34001f
.int 0x1a9f17e1
.int 0x54000040
.int 0x39000260
.int 0x2a0103e0
.int 0xa94153f3
.int 0xa8c27bfd
.int 0xd65f03c0
#else
stp x29, x30, [sp, -32]!
mov x29, sp
stp x19, x20, [sp, 16]
mov x19, x1
and w1, w2, 255
mov x2, x0
ldrb w20, [x19]
mov w0, w20
uxtb w16, w0
.L1:
ldaxrb w0, [x2]
cmp w0, w16
b.ne .L2
stlxrb w17, w1, [x2]
cbnz w17, .L1
.L2:
cmp w0, w20, uxtb
cset w1, eq
beq .L3
strb w0, [x19]
.L3:
mov w0, w1
ldp x19, x20, [sp, 16]
ldp x29, x30, [sp], 32
ret
#endif
.size _(__atomic_compare_exchange_1), .-_(__atomic_compare_exchange_1)
.global _(__atomic_compare_exchange_2)
.type _(__atomic_compare_exchange_2), %function
_(__atomic_compare_exchange_2):
#ifdef __TINYC__
.int 0xa9be7bfd
.int 0x910003fd
.int 0xa90153f3
.int 0xaa0103f3
.int 0x12003c41
.int 0xaa0003e2
.int 0x79400274
.int 0x2a1403e0
.int 0x53003c10
.int 0x485ffc40
.int 0x6b10001f
.int 0x54000061
.int 0x4811fc41
.int 0x35ffff91
.int 0x6b34201f
.int 0x1a9f17e1
.int 0x54000040
.int 0x79000260
.int 0x2a0103e0
.int 0xa94153f3
.int 0xa8c27bfd
.int 0xd65f03c0
#else
stp x29, x30, [sp, -32]!
mov x29, sp
stp x19, x20, [sp, 16]
mov x19, x1
and w1, w2, 65535
mov x2, x0
ldrh w20, [x19]
mov w0, w20
uxth w16, w0
.L4:
ldaxrh w0, [x2]
cmp w0, w16
b.ne .L5
stlxrh w17, w1, [x2]
cbnz w17, .L4
.L5:
cmp w0, w20, uxth
cset w1, eq
beq .L6
strh w0, [x19]
.L6:
mov w0, w1
ldp x19, x20, [sp, 16]
ldp x29, x30, [sp], 32
ret
#endif
.size _(__atomic_compare_exchange_2), .-_(__atomic_compare_exchange_2)
.global _(__atomic_compare_exchange_4)
.type _(__atomic_compare_exchange_4), %function
_(__atomic_compare_exchange_4):
#ifdef __TINYC__
.int 0xa9be7bfd
.int 0x910003fd
.int 0xa90153f3
.int 0xaa0103f3
.int 0x2a0203e1
.int 0xaa0003e2
.int 0xb9400274
.int 0x2a1403e0
.int 0x2a0003f0
.int 0x885ffc40
.int 0x6b10001f
.int 0x54000061
.int 0x8811fc41
.int 0x35ffff91
.int 0x6b14001f
.int 0x1a9f17e1
.int 0x54000040
.int 0xb9000260
.int 0x2a0103e0
.int 0xa94153f3
.int 0xa8c27bfd
.int 0xd65f03c0
#else
stp x29, x30, [sp, -32]!
mov x29, sp
stp x19, x20, [sp, 16]
mov x19, x1
mov w1, w2
mov x2, x0
ldr w20, [x19]
mov w0, w20
mov w16, w0
.L7:
ldaxr w0, [x2]
cmp w0, w16
b.ne .L8
stlxr w17, w1, [x2]
cbnz w17, .L7
.L8:
cmp w0, w20
cset w1, eq
beq .L9
str w0, [x19]
.L9:
mov w0, w1
ldp x19, x20, [sp, 16]
ldp x29, x30, [sp], 32
ret
#endif
.size _(__atomic_compare_exchange_4), .-_(__atomic_compare_exchange_4)
.global _(__atomic_compare_exchange_8)
.type _(__atomic_compare_exchange_8), %function
_(__atomic_compare_exchange_8):
#ifdef __TINYC__
.int 0xa9be7bfd
.int 0x910003fd
.int 0xa90153f3
.int 0xaa0103f3
.int 0xaa0203e1
.int 0xaa0003e2
.int 0xf9400274
.int 0xaa1403e0
.int 0xaa0003f0
.int 0xc85ffc40
.int 0xeb10001f
.int 0x54000061
.int 0xc811fc41
.int 0x35ffff91
.int 0xeb14001f
.int 0x1a9f17e1
.int 0x54000040
.int 0xf9000260
.int 0x2a0103e0
.int 0xa94153f3
.int 0xa8c27bfd
.int 0xd65f03c0
#else
stp x29, x30, [sp, -32]!
mov x29, sp
stp x19, x20, [sp, 16]
mov x19, x1
mov x1, x2
mov x2, x0
ldr x20, [x19]
mov x0, x20
mov x16, x0
.L10:
ldaxr x0, [x2]
cmp x0, x16
b.ne .L11
stlxr w17, x1, [x2]
cbnz w17, .L10
.L11:
cmp x0, x20
cset w1, eq
beq .L12
str x0, [x19]
.L12:
mov w0, w1
ldp x19, x20, [sp, 16]
ldp x29, x30, [sp], 32
ret
#endif
.size _(__atomic_compare_exchange_8), .-_(__atomic_compare_exchange_8)
/* ---------------------------------------------- */
#elif defined __riscv
.text
.align 2
.global _(fetch_and_add_riscv64)
.type _(fetch_and_add_riscv64), %function
_(fetch_and_add_riscv64):
#ifdef __TINYC__
.int 0x0f50000f
.int 0x004b5202f
.short 0x8082
#else
fence iorw,ow
amoadd.w.aq zero,a1,0(a0)
ret
#endif
.size _(fetch_and_add_riscv64), .-_(fetch_and_add_riscv64)
.global _(__atomic_test_and_set)
.type _(__atomic_test_and_set), %function
_(__atomic_test_and_set):
#ifdef __TINYC__
.int 0x00357793
.int 0x0037979b
.short 0x4685
.short 0x9971
.int 0x00f696bb
.int 0x0f50000f
.int 0x44d5272f
.int 0x00f7553b
.int 0x0ff57513
.short 0x8082
#else
andi a5,a0,3
slliw a5,a5,3
li a3,1
andi a0,a0,-4
sllw a3,a3,a5
fence iorw,ow; amoor.w.aq a4,a3,0(a0)
srlw a0,a4,a5
andi a0,a0,0xff
ret
#endif
.size _(__atomic_test_and_set), .-_(__atomic_test_and_set)
.global _(__atomic_clear)
.type _(__atomic_clear), %function
_(__atomic_clear):
#ifdef __TINYC__
.int 0x0ff0000f
.int 0x00050023
.int 0x0ff0000f
.short 0x8082
#else
fence iorw,iorw
sb zero,0(a0)
fence iorw,iorw
ret
#endif
.size _(__atomic_clear), .-_(__atomic_clear)
.global _(__atomic_compare_exchange_1)
.type _(__atomic_compare_exchange_1), %function
_(__atomic_compare_exchange_1):
#ifdef __TINYC__
.short 0x1141
.short 0x86ba
.short 0x873e
.short 0xe406
.int 0x0ff0000f
.int 0x0005c803
.int 0xff857893
.int 0x0008b783
.short 0x891d
.short 0x050e
.int 0x0ff00693
.int 0x00a696b3
.int 0x00a81833
.int 0x00a61633
.int 0xfff6c713
.short 0x8f7d
.int 0x00f6f333
.short 0x8f51
.int 0x03031263
.int 0x1008b32f
.int 0x00f31663
.int 0x18e8be2f
.int 0xfe0e1ae3
.int 0x40f30733
.short 0x879a
.short 0xff69
.int 0x0ff0000f
.short 0x4505
.short 0xa801
.int 0x00a7d7b3
.int 0x00f58023
.int 0x0ff0000f
.short 0x4501
.short 0x60a2
.short 0x0141
.short 0x8082
#else
addi sp,sp,-16
mv a3,a4
mv a4,a5
sd ra,8(sp)
fence
lbu a6,0(a1)
andi a7,a0,-8
ld a5,0(a7)
andi a0,a0,7
slli a0,a0,0x3
li a3,255
sll a3,a3,a0
sll a6,a6,a0
sll a2,a2,a0
.L1:
not a4,a3
and a4,a4,a5
and t1,a3,a5
or a4,a4,a2
bne t1,a6,.L4
.L2:
lr.d t1,(a7)
bne t1,a5,.L3
sc.d t3,a4,(a7)
bnez t3,.L2
.L3:
sub a4,t1,a5
mv a5,t1
bnez a4,.L1
fence
li a0,1
j .L5
.L4:
srl a5,a5,a0
sb a5,0(a1)
fence
li a0,0
.L5:
ld ra,8(sp)
addi sp,sp,16
jr ra
#endif
.size _(__atomic_compare_exchange_1), .-_(__atomic_compare_exchange_1)
.global _(__atomic_compare_exchange_2)
.type _(__atomic_compare_exchange_2), %function
_(__atomic_compare_exchange_2):
#ifdef __TINYC__
.short 0x1141
.short 0x86ba
.short 0x873e
.short 0xe406
.int 0x0ff0000f
.int 0x0005d803
.int 0xff857893
.short 0x67c1
.short 0x891d
.int 0x0008b703
.short 0x050e
.short 0x17fd
.int 0x00a797b3
.int 0x00a81833
.int 0x00a61633
.int 0xfff7c693
.short 0x8ef9
.int 0x00e7f333
.short 0x8ed1
.int 0x03031263
.int 0x1008b32f
.int 0x00e31663
.int 0x18d8be2f
.int 0xfe0e1ae3
.int 0x40e306b3
.short 0x871a
.short 0xfee9
.int 0x0ff0000f
.short 0x4505
.short 0xa801
.int 0x00a75733
.int 0x00e59023
.int 0x0ff0000f
.short 0x4501
.short 0x60a2
.short 0x0141
.short 0x8082
#else
addi sp,sp,-16
mv a3,a4
mv a4,a5
sd ra,8(sp)
fence
lhu a6,0(a1)
andi a7,a0,-8
lui a5,0x10
andi a0,a0,7
ld a4,0(a7)
slli a0,a0,0x3
addi a5,a5,-1
sll a5,a5,a0
sll a6,a6,a0
sll a2,a2,a0
.L6:
not a3,a5
and a3,a3,a4
and t1,a5,a4
or a3,a3,a2
bne t1,a6,.L9
.L7:
lr.d t1,(a7)
bne t1,a4,.L8
sc.d t3,a3,(a7)
bnez t3,.L7
.L8:
sub a3,t1,a4
mv a4,t1
bnez a3,.L6
fence
li a0,1
j .L10
.L9:
srl a4,a4,a0
sh a4,0(a1)
fence
li a0,0
.L10:
ld ra,8(sp)
addi sp,sp,16
jr ra
#endif
.size _(__atomic_compare_exchange_2), .-_(__atomic_compare_exchange_2)
.global _(__atomic_compare_exchange_4)
.type _(__atomic_compare_exchange_4), %function
_(__atomic_compare_exchange_4):
#ifdef __TINYC__
.short 0x419c
.int 0x0f50000f
.int 0x1405272f
.int 0x00f71663
.int 0x1cc5282f
.int 0xfe081ae3
.int 0x40f707bb
.int 0x0017b513
.short 0xc391
.short 0xc198
.short 0x8905
.short 0x8082
#else
lw a5,0(a1)
fence iorw,ow;
.L11:
lr.w.aq a4,0(a0)
bne a4,a5,.L12
sc.w.aq a6,a2,0(a0)
bnez a6,.L11
.L12:
subw a5,a4,a5
seqz a0,a5
beq a5,zero,.L13
sw a4,0(a1)
.L13:
andi a0,a0,1
ret
#endif
.size _(__atomic_compare_exchange_4), .-_(__atomic_compare_exchange_4)
.global _(__atomic_compare_exchange_8)
.type _(__atomic_compare_exchange_8), %function
_(__atomic_compare_exchange_8):
#ifdef __TINYC__
.short 0x619c
.int 0x0f50000f
.int 0x1405372f
.int 0x00f71563
.int 0x1cc536af
.short 0xfaf5
.int 0x40f707b3
.int 0x0017b513
.short 0xc391
.short 0xe198
.short 0x8905
.short 0x8082
#else
ld a5,0(a1)
fence iorw,ow;
.L14:
lr.d.aq a4,0(a0)
bne a4,a5,.L15
sc.d.aq a3,a2,0(a0)
bnez a3,.L14
.L15:
sub a5,a4,a5
seqz a0,a5
beq a5,zero,.L16
sd a4,0(a1)
.L16:
andi a0,a0,1
ret
#endif
.size _(__atomic_compare_exchange_8), .-_(__atomic_compare_exchange_8)
/* ---------------------------------------------- */
#endif
|
matgla/tinycc | 1,767 | lib/alloca-bt.S | /* ---------------------------------------------- */
/* alloca-bt.S */
#ifdef __leading_underscore
# define _(s) _##s
#else
# define _(s) s
#endif
/* ---------------------------------------------- */
#if defined __i386__
.globl _(__bound_alloca)
_(__bound_alloca):
pop %edx
pop %eax
mov %eax, %ecx
add $3+1,%eax
and $-4,%eax
jz p6
#ifdef _WIN32
p4:
cmp $4096,%eax
jbe p5
test %eax,-4096(%esp)
sub $4096,%esp
sub $4096,%eax
jmp p4
p5:
#endif
sub %eax,%esp
mov %esp,%eax
push %edx
push %eax
push %ecx
push %eax
call _(__bound_new_region)
add $8, %esp
pop %eax
pop %edx
p6:
push %edx
push %edx
ret
/* ---------------------------------------------- */
#elif defined __x86_64__
.globl _(__bound_alloca)
_(__bound_alloca):
#ifdef _WIN32
inc %rcx # add one extra to separate regions
jmp _(alloca)
.globl _(__bound_alloca_nr)
_(__bound_alloca_nr):
dec %rcx
push %rax
mov %rcx,%rdx
mov %rax,%rcx
sub $32,%rsp
call _(__bound_new_region)
add $32,%rsp
pop %rax
ret
#else
pop %rdx
mov %rdi,%rax
mov %rax,%rsi # size, a second parm to the __bound_new_region
add $15 + 1,%rax # add one extra to separate regions
and $-16,%rax
jz p3
sub %rax,%rsp
mov %rsp,%rdi # pointer, a first parm to the __bound_new_region
mov %rsp,%rax
push %rdx
push %rax
call _(__bound_new_region)
pop %rax
pop %rdx
p3:
push %rdx
ret
#endif
/* ---------------------------------------------- */
#endif
|
matgla/tinycc | 1,445 | lib/alloca.S | /* ---------------------------------------------- */
/* alloca.S */
#ifdef __leading_underscore
# define _(s) _##s
#else
# define _(s) s
#endif
/* ---------------------------------------------- */
#if defined __i386__
.globl _(alloca), _(__alloca)
_(alloca):
_(__alloca):
push %ebp
mov %esp,%ebp
mov 8(%ebp),%eax
add $3,%eax
and $-4,%eax
#ifdef _WIN32
jmp .+16 #p2
p1:
sub $4096,%esp
sub $4096,%eax
test %eax,(%esp)
p2:
cmp $4096,%eax
jae p1
#endif
sub %eax,%esp
mov 4(%ebp),%eax
mov 0(%ebp),%ebp
add $8,%esp
push %eax
lea 8(%esp),%eax
ret
/* ---------------------------------------------- */
#elif defined __x86_64__
.globl _(alloca)
_(alloca):
pop %rdx
#ifdef _WIN32
mov %rcx,%rax
#else
mov %rdi,%rax
#endif
add $15,%rax
and $-16,%rax
jz p3
#ifdef _WIN32
p1:
cmp $4096,%rax
jbe p2
test %rax,-4096(%rsp)
sub $4096,%rsp
sub $4096,%rax
jmp p1
p2:
#endif
sub %rax,%rsp
mov %rsp,%rax
p3:
push %rdx
ret
/* ---------------------------------------------- */
#elif defined __arm__
.text
.align 2
.global alloca
.type alloca, %function
alloca:
rsb sp, r0, sp
bic sp, sp, #7
mov r0, sp
mov pc, lr
.size alloca, .-alloca
/* ---------------------------------------------- */
#endif
|
matgla/tinycc | 15,864 | tests/asmtest.S | # gas comment with ``gnu'' style quotes
/* some directive tests */
.byte 0xff
.byte 1, 2, 3
.short 1, 2, 3
.word 1, 2, 3
.long 1, 2, 3
.int 1, 2, 3
.align 8
.byte 1
/* .align 16, 0x90 gas is too clever for us with 0x90 fill */
.balign 4, 0x92
.align 16, 0x91 /* 0x91 tests the non-clever behaviour */
.skip 3
.skip 15, 0x90
.string "hello\0world"
/* Macro expansion should work like with C, the #n shouldn't be parsed
as asm line comment */
#define __stringify(n) #n
#define stringify(n) __stringify(n)
.skip 8,0x90
.asciz stringify(BLA)
.skip 8,0x90
# 28 "asmtest.S" # a line directive (and a line comment)
movl %eax, %ebx # some more asm comment
/* some label tests */
L1:
movl %eax, %ebx
mov 0x10000, %eax
L2:
movl $L2 - L1, %ecx
var1:
nop ; nop ; nop ; nop
mov var1, %eax
/* instruction tests */
movl %eax, %ebx
mov 0x10000, %eax
mov 0x10000, %ax
mov 0x10000, %al
mov %al, 0x10000
mov $1, %edx
mov $1, %dx
mov $1, %cl
movb $2, 0x100(%ebx,%edx,2)
movw $2, 0x100(%ebx,%edx,2)
movl $2, 0x100(%ebx,%edx,2)
movl %eax, 0x100(%ebx,%edx,2)
movl 0x100(%ebx,%edx,2), %edx
movw %ax, 0x100(%ebx,%edx,2)
movw $0x1122,%si
movl $0x112233,%edx
movl $0x80000000, %esi
movl $-0x7fffffff, %edi
#ifdef __x86_64__
mov $0x11223344,%rbx
movq $0x11223344,%rbx
mov $0x1122334455,%rbx
movq $0x1122334455,%rbx
movl $0x11334455,(%rbx)
#endif
mov %eax, 0x12(,%edx,2)
#ifdef __i386__
mov %cr3, %edx
mov %ecx, %cr3
movl %cr3, %eax
movl %tr3, %eax
movl %db3, %ebx
movl %dr6, %eax
#else
mov %cr3, %rdx
mov %rcx, %cr3
movq %cr3, %rax
movq %db3, %rbx
movq %dr6, %rax
mov %cr8, %rsi
mov %rdi, %cr8
#endif
movl %fs, %ecx
movl %ebx, %fs
#ifdef __x86_64__
movq %r8, %r9
movq %r10, %r11
movq %r12, %r13
movq %r14, %r15
movq %rax, %r9
movq %r15, %rsi
inc %r9b
dec %r10w
not %r11d
negq %r12
decb %r13b
incw %r14w
notl %r15d
#endif
movsbl 0x1000, %eax
movsbw 0x1000, %ax
movswl 0x1000, %eax
movzbl 0x1000, %eax
movzbw 0x1000, %ax
movzwl 0x1000, %eax
movzb 0x1000, %eax
movzb 0x1000, %ax
mov $0x12345678,%eax
#ifdef __x86_64__
movzb 0x1000, %rax
movzbq 0x1000, %rbx
movsbq 0x1000, %rdx
movzwq 0x1000, %rdi
movswq 0x1000, %rdx
movslq %eax, %rcx
mov $0x12345678,%rax
mov $0x12345678,%rdx
mov $0x12345678,%r10
mov $0x123456789abcdef0,%rax
mov $0x123456789abcdef0,%rcx
mov $0x123456789abcdef0,%r11
#endif
#ifdef __i386__
pushl %eax
push %eax
push %cs
#else
pushq %rax
push %rax
#endif
pushw %ax
push %gs
push $1
push $100
push 0x42(%eax)
pop 0x43(%esi)
#ifdef __i386__
popl %eax
pop %eax
pop %ds
#else
popq %rax
pop %rax
#endif
popw %ax
pop %fs
xchg %eax, %ecx
xchg %edx, %eax
xchg %bx, 0x10000
xchg 0x10000, %ebx
xchg 0x10000, %dl
in $100, %al
in $100, %ax
in $100, %eax
in %dx, %al
in %dx, %ax
in %dx, %eax
inb %dx
inw %dx
inl %dx
out %al, $100
out %ax, $100
out %eax, $100
/* NOTE: gas is bugged here, so size must be added */
outb %al, %dx
outw %ax, %dx
outl %eax, %dx
leal 0x1000(%ebx), %ecx
lea 0x1000(%ebx), %ecx
#ifdef __i386__
les 0x2000, %eax
lds 0x2000, %ebx
lss 0x2000, %edx
#endif
lfs 0x2000, %ecx
lgs 0x2000, %edx
addl $0x123, %eax
add $0x123, %ebx
add $-16, %ecx
add $-0x123, %esi
add $1, %bx
add $1, %ebx
add $-1, %bx
add $-1, %ebx
add $127, %bx
addl $127, %ebx
addl $-128, %ebx
addl $-128, %ebx
addl $-129, %ebx
addl $128, %ebx
addl $255, %ebx
addl $256, %ebx
andb $0xf, %ah
andb $-15, %cl
xorb $127, %dh
cmpb $42, (%eax)
addl $0x123, 0x100
addl $0x123, 0x100(%ebx)
addl $0x123, 0x100(%ebx,%edx,2)
addl $0x123, 0x100(%esp)
addl $0x123, (3*8)(%esp)
addl $0x123, (%ebp)
addl $0x123, (%esp)
cmpl $0x123, (%esp)
#ifdef __x86_64__
xor %bl,%ah
xor %bl,%r8b
xor %r9b,%bl
xor %sil,%cl
add %eax,(%r8d)
add %ebx,(%r9)
add %edx,(%r10d,%r11d)
add %ecx,(%r12,%r13)
add %esi,(%r14,%r15,4)
add %edi,0x1000(%rbx,%r12,8)
add %r11,0x1000(%ebp,%r9d,8)
movb $12, %ah
movb $13, %bpl
movb $14, %dil
movb $15, %r12b
#endif
add %eax, (%ebx)
add (%ebx), %eax
or %dx, (%ebx)
or (%ebx), %si
add %cl, (%ebx)
add (%ebx), %dl
inc %edx
incl 0x10000
incb 0x10000
dec %dx
test $1, %al
test $1, %cl
testl $1, 0x1000
testb $1, 0x1000
testw $1, 0x1000
test %eax, %ebx
test %eax, 0x1000
test 0x1000, %edx
not %edx
notw 0x10000
notl 0x10000
notb 0x10000
neg %edx
negw 0x10000
negl 0x10000
negb 0x10000
imul %ecx
mul %edx
mulb %cl
imul %eax, %ecx
imul 0x1000, %cx
imul $10, %eax, %ecx
imul $10, %ax, %cx
imul $10, %eax
imul $0x1100000, %eax
imul $1, %eax
idivw 0x1000
div %ecx
div %bl
div %ecx, %eax
and $15,%bx
and $-20,%edx
shl %edx
shl $10, %edx
shl %cl, %edx
shld $1, %eax, %edx
shld %cl, %eax, %edx
shld %eax, %edx
shrd $1, %eax, %edx
shrd %cl, %eax, %edx
shrd %eax, %edx
L4:
call 0x1000
call L4
#ifdef __i386__
call *%eax
#else
call *%rax
#endif
call *0x1000
call func1
.global L5,L6
L5:
L6:
#ifdef __i386__
lcall $0x100, $0x1000
#else
lcall *0x100
lcall *(%rax)
#endif
jmp 0x1000
jmp *(%edi)
#ifdef __i386__
jmp *%eax
#else
jmp *%rax
#endif
jmp *0x1000
#ifdef __i386__
ljmp $0x100, $0x1000
#else
ljmp *0x100
ljmp *(%rdi)
ljmpl *(%esi)
ljmpw *(%esi)
#endif
ret
ret $10
#ifdef __i386__
retl
retl $10
#else
retq
retq $10
#endif
lret
lret $10
enter $1234, $10
L3:
jo 0x1000
jnp 0x1001
jne 0x1002
jg 0x1003
jo L3
jnp L3
jne L3
jg L3
loopne L3
loopnz L3
loope L3
loopz L3
loop L3
jecxz L3
seto %al
setc %al
setcb %al
setnp 0x1000
setl 0xaaaa
setg %dl
fadd
fadd %st(1), %st
fadd %st(0), %st(1)
fadd %st(3)
fmul %st(0),%st(0)
fmul %st(0),%st(1)
faddp %st(5)
faddp
faddp %st(1), %st
fadds 0x1000
fiadds 0x1002
faddl 0x1004
fiaddl 0x1006
fmul
fmul %st(1), %st
fmul %st(3)
fmulp %st(5)
fmulp
fmulp %st(1), %st
fmuls 0x1000
fimuls 0x1002
fmull 0x1004
fimull 0x1006
fsub
fsub %st(1), %st
fsub %st(3)
fsubp %st(5)
fsubp
//fsubp %st(1), %st # not accepted by new GAS anymore
fsubs 0x1000
fisubs 0x1002
fsubl 0x1004
fisubl 0x1006
fsubr
fsubr %st(1), %st
fsubr %st(3)
fsubrp %st(5)
fsubrp
//fsubrp %st(1), %st # not accepted by new GAS anymore
fsubrs 0x1000
fisubrs 0x1002
fsubrl 0x1004
fisubrl 0x1006
fdiv
fdiv %st(1), %st
fdiv %st(3)
fdivp %st(5)
fdivp
//fdivp %st(1), %st # not accepted by new GAS anymore
fdivs 0x1000
fidivs 0x1002
fdivl 0x1004
fidivl 0x1006
fcom %st(3)
fcoms 0x1000
ficoms 0x1002
fcoml 0x1004
ficoml 0x1006
fcomp %st(5)
fcomp
fcompp
fcomps 0x1000
ficomps 0x1002
fcompl 0x1004
ficompl 0x1006
fld %st(5)
fldl 0x1000
flds 0x1002
fildl 0x1004
fst %st(4)
fstp %st(6)
fstpt 0x1006
fbstp 0x1008
fxch
fxch %st(4)
fucom %st(6)
fucomp %st(3)
fucompp
finit
fninit
fldcw 0x1000
fnstcw 0x1002
fstcw 0x1002
fnstsw 0x1004
fnstsw (%eax)
fstsw 0x1004
fstsw (%eax)
fnclex
fclex
fnstenv 0x1000
fstenv 0x1000
fldenv 0x1000
fnsave 0x1002
fsave 0x1000
frstor 0x1000
ffree %st(7)
ffreep %st(6)
ftst
fxam
fld1
fldl2t
fldl2e
fldpi
fldlg2
fldln2
fldz
f2xm1
fyl2x
fptan
fpatan
fxtract
fprem1
fdecstp
fincstp
fprem
fyl2xp1
fsqrt
fsincos
frndint
fscale
fsin
fcos
fchs
fabs
fnop
fwait
bswap %edx
bswapl %ecx
xadd %ecx, %edx
xaddb %dl, 0x1000
xaddw %ax, 0x1000
xaddl %eax, 0x1000
cmpxchg %ecx, %edx
cmpxchgb %dl, 0x1000
cmpxchgw %ax, 0x1000
cmpxchgl %eax, 0x1000
invlpg 0x1000
cmpxchg8b 0x1002
#ifdef __x86_64__
cmpxchg16b (%rax)
cmpxchg16b (%r10,%r11)
#endif
fcmovb %st(5), %st
fcmove %st(5), %st
fcmovbe %st(5), %st
fcmovu %st(5), %st
fcmovnb %st(5), %st
fcmovne %st(5), %st
fcmovnbe %st(5), %st
fcmovnu %st(5), %st
fcomi %st(5), %st
fucomi %st(5), %st
fcomip %st(5), %st
fucomip %st(5), %st
cmovo 0x1000, %eax
cmovs 0x1000, %eax
cmovns %edx, %edi
cmovne %ax, %si
cmovbw %ax, %di
cmovnbel %edx, %ecx
#ifdef __x86_64__
bswapq %rsi
bswapq %r10
cmovz %rdi,%rbx
cmovpeq %rsi, %rdx
#endif
int $3
int $0x10
#ifdef __i386__
pusha
popa
#endif
clc # another comment
cld # a comment with embedded ' tick
cli
clts
cmc
lahf
sahf
#ifdef __i386__
pushfl
popfl
#else
pushfq
popfq
#endif
pushf
popf
stc
std
sti
#ifdef __i386__
aaa
aas
daa
das
aad
aam
into
#endif
cbw
cwd
cwde
cdq
cbtw
cwtd
cwtl
cltd
leave
int3
iret
iretw
iretl
#ifdef __x86_64__
iretq
#endif
rsm
hlt
wait
nop
vmcall
vmlaunch
vmresume
vmxoff
/* XXX: handle prefixes */
#if 0
aword
addr16
#endif
lock
rep
repe
repz
repne
repnz
nop
lock ;negl (%eax)
wait ;pushf
rep ;stosb
repe ;lodsb
repz ;cmpsb
repne;movsb
repnz;outsb
/* handle one-line prefix + ops */
lock negl (%eax)
wait pushf
rep stosb
repe lodsb
repz cmpsb
repne movsb
repnz outsb
invd
wbinvd
cpuid
wrmsr
rdtsc
rdmsr
rdpmc
ud2
#ifdef __x86_64__
syscall
sysret
sysretq
lfence
mfence
sfence
prefetchnta 0x18(%rdx)
prefetcht0 (%rcx)
prefetcht1 (%rsi)
prefetcht2 (%rdi)
prefetchw (%rdi)
clflush 0x1000(%rax,%rcx)
fxsaveq (%rdx)
fxsaveq (%r11)
fxrstorq (%rcx)
fxrstorq (%r10)
movnti %ebx, (%rdi)
movntil %ecx, (%rdi)
movnti %rax, (%rdi)
movntiq %r8, (%rdi)
#endif
lar %ax,%dx
lar %eax,%dx
lar %ax,%edx
lar %eax,%edx
#ifdef __x86_64__
lar %ax,%rdx
lar %eax,%rdx
#endif
emms
movd %edx, %mm3
movd 0x1000, %mm2
movd %mm4, %ecx
movd %mm5, 0x1000
movq 0x1000, %mm2
movq %mm4, 0x1000
pand 0x1000, %mm3
pand %mm4, %mm5
psllw $1, %mm6
psllw 0x1000, %mm7
psllw %mm2, %mm7
xlat
cmpsb
scmpw
insl
outsw
lodsb
slodl
movsb
movsl
smovb
scasb
sscaw
stosw
sstol
bsf 0x1000, %ebx
bsr 0x1000, %ebx
bt %edx, 0x1000
btl $2, 0x1000
btc %edx, 0x1000
btcl $2, 0x1000
btr %edx, 0x1000
btrl $2, 0x1000
bts %edx, 0x1000
btsl $2, 0x1000
popcnt %ax, %si
popcntw %ax, %si
popcnt 0x1000, %edx
popcntl 0x1000, %edx
#ifdef __x86_64__
popcnt %rbx, %rdi
popcntq %rcx, %r8
#endif
lzcnt %cx, %ax
lzcntw %cx, %ax
lzcnt %edx, %ebx
lzcntl 8(%edi), %ecx
#ifdef __x86_64__
lzcnt %rdi, %rdx
lzcntq %r12, %r15
lzcnt 0x40(%rcx), %r11
lzcntq (%r8), %rsi
#endif
tzcnt %cx, %ax
tzcntw %cx, %ax
tzcnt %edx, %ebx
tzcntl -24(%edi), %ecx
#ifdef __x86_64__
tzcnt %rbp, %rdx
tzcntq %rax, %r15
tzcnt -8(%rbp), %rcx
tzcntq (%r8), %r12
#endif
#ifdef __i386__
boundl %edx, 0x10000
boundw %bx, 0x1000
arpl %bx, 0x1000
#endif
lar 0x1000, %eax
lgdt 0x1000
lidt 0x1000
lldt 0x1000
sgdt 0x1000
sidt 0x1000
sldt 0x1000
#ifdef __x86_64__
lgdtq 0x1000
lidtq 0x1000
sgdtq 0x1000
sidtq 0x1000
swapgs
/* Newer gas assemble 'str %rdx' as 'str %edx', based on the observation
that the 16bit value of the task register is zero-extended into the
destination anyway, and hence storing into %edx is the same as storing
into %rdx. TCC doesn't do that micro-optimization, hence just store
into the 32bit reg as well. */
str %edx
str %r9d
#endif
lmsw 0x1000
lsl 0x1000, %ecx
ltr 0x1000
ltr %si
smsw 0x1000
str 0x1000
str %ecx
str %dx
verr 0x1000
verw 0x1000
#ifdef __i386__
push %ds
pushw %ds
pushl %ds
pop %ds
popw %ds
popl %ds
#endif
fxsave 1(%ebx)
fxrstor 1(%ecx)
#ifdef __i386__
pushl $1
#else
pushq $1
#endif
pushw $1
push $1
#ifdef __ASSEMBLER__ // should be defined, for S files
inc %eax
#endif
#ifndef _WIN32
ft1: ft2: ft3: ft4: ft5: ft6: ft7: ft8: ft9:
xor %eax, %eax
ret
.type ft1,STT_FUNC
.type ft2,@STT_FUNC
.type ft3,%STT_FUNC
.type ft4,"STT_FUNC"
.type ft5,function
.type ft6,@function
.type ft7,%function
.type ft8,"function"
#endif
pause
.rept 6
nop
.endr
.fill 4,1,0x90
.section .text.one,"ax"
nop
.previous
.pushsection .text.one,"ax"
nop
.pushsection .text.two,"ax"
nop
.popsection
.popsection
1: ud2
.pushsection __bug_table,"a"
.align 8
2: .long 1b - 2b
.long 0x600000 - 2b
.long 1b + 42
.long 43 + 1b
.long 2b + 144
.long 145 + 2b
.word 164, 0
.org 2b+32
#ifdef __x86_64__
.quad 1b
#else
.long 1b
#endif
.popsection
3: mov %eax,%ecx
4:
.pushsection .text.three, "ax"
nop
.skip (-((4b-3b) > 0) * 2) , 0x90
.popsection
.globl overrideme
.weak overrideme
nop
.globl notimplemented
notimplemented:
ret
.set overrideme, notimplemented
overrideme = notimplemented
overrideme:
ret
movd %esi, %mm1
movd %edi, %xmm2
movd (%ebx), %mm3
movd (%ebx), %xmm3
movd %mm1, %esi
movd %xmm2, %edi
movd %mm3, (%edx)
movd %xmm3, (%edx)
#ifdef __x86_64__
movd %rsi, %mm1
movd %rdi, %xmm2
movd (%rbx), %mm3
movd (%rbx), %xmm3
movd %mm1, %r12
movd %xmm2, %rdi
movd %mm3, (%r8)
movd %xmm3, (%r13)
#endif
movq (%ebp), %mm1
movq %mm2, (%edi)
movq (%edi), %xmm3
movq %mm4, %mm5
#ifdef __x86_64__
movq %rcx, %mm1
movq %rdx, %xmm2
movq %r13, %xmm3
/* movq mem64->xmm is encoded as f30f7e by GAS, but as
660f6e by tcc (which really is a movd and would need
a REX.W prefix to be movq). */
movq (%rsi), %xmm3
movq %mm1, %rdx
movq %xmm3, %rcx
movq %xmm4, (%rsi)
#endif
#define TEST_MMX_SSE(insn) \
insn %mm1, %mm2; \
insn %xmm2, %xmm3; \
insn (%ebx), %xmm3;
#define TEST_MMX_SSE_I8(insn) \
TEST_MMX_SSE(insn) \
insn $0x42, %mm4; \
insn $0x42, %xmm4;
TEST_MMX_SSE(packssdw)
TEST_MMX_SSE(packsswb)
TEST_MMX_SSE(packuswb)
TEST_MMX_SSE(paddb)
TEST_MMX_SSE(paddw)
TEST_MMX_SSE(paddd)
TEST_MMX_SSE(paddsb)
TEST_MMX_SSE(paddsw)
TEST_MMX_SSE(paddusb)
TEST_MMX_SSE(paddusw)
TEST_MMX_SSE(pand)
TEST_MMX_SSE(pandn)
TEST_MMX_SSE(pcmpeqb)
TEST_MMX_SSE(pcmpeqw)
TEST_MMX_SSE(pcmpeqd)
TEST_MMX_SSE(pcmpgtb)
TEST_MMX_SSE(pcmpgtw)
TEST_MMX_SSE(pcmpgtd)
TEST_MMX_SSE(pmaddwd)
TEST_MMX_SSE(pmulhw)
TEST_MMX_SSE(pmullw)
TEST_MMX_SSE(por)
TEST_MMX_SSE(psllw)
TEST_MMX_SSE_I8(psllw)
TEST_MMX_SSE(pslld)
TEST_MMX_SSE_I8(pslld)
TEST_MMX_SSE(psllq)
TEST_MMX_SSE_I8(psllq)
TEST_MMX_SSE(psraw)
TEST_MMX_SSE_I8(psraw)
TEST_MMX_SSE(psrad)
TEST_MMX_SSE_I8(psrad)
TEST_MMX_SSE(psrlw)
TEST_MMX_SSE_I8(psrlw)
TEST_MMX_SSE(psrld)
TEST_MMX_SSE_I8(psrld)
TEST_MMX_SSE(psrlq)
TEST_MMX_SSE_I8(psrlq)
TEST_MMX_SSE(psubb)
TEST_MMX_SSE(psubw)
TEST_MMX_SSE(psubd)
TEST_MMX_SSE(psubsb)
TEST_MMX_SSE(psubsw)
TEST_MMX_SSE(psubusb)
TEST_MMX_SSE(psubusw)
TEST_MMX_SSE(punpckhbw)
TEST_MMX_SSE(punpckhwd)
TEST_MMX_SSE(punpckhdq)
TEST_MMX_SSE(punpcklbw)
TEST_MMX_SSE(punpcklwd)
TEST_MMX_SSE(punpckldq)
TEST_MMX_SSE(pxor)
cvtpi2ps %mm1, %xmm2
cvtpi2ps (%ebx), %xmm2
TEST_MMX_SSE(pmaxsw)
TEST_MMX_SSE(pmaxub)
TEST_MMX_SSE(pminsw)
TEST_MMX_SSE(pminub)
|
matgla/tinycc | 1,720 | win32/lib/chkstk.S | /* ---------------------------------------------- */
/* chkstk86.s */
#ifdef __leading_underscore
# define _(s) _##s
#else
# define _(s) s
#endif
/* ---------------------------------------------- */
#ifndef __x86_64__
/* ---------------------------------------------- */
.globl _(__chkstk)
_(__chkstk):
xchg (%esp),%ebp /* store ebp, get ret.addr */
push %ebp /* push ret.addr */
lea 4(%esp),%ebp /* setup frame ptr */
push %ecx /* save ecx */
mov %ebp,%ecx
P0:
sub $4096,%ecx
test %eax,(%ecx)
sub $4096,%eax
cmp $4096,%eax
jge P0
sub %eax,%ecx
test %eax,(%ecx)
mov %esp,%eax
mov %ecx,%esp
mov (%eax),%ecx /* restore ecx */
jmp *4(%eax)
/* ---------------------------------------------- */
#else
/* ---------------------------------------------- */
.globl _(__chkstk)
_(__chkstk):
xchg (%rsp),%rbp /* store ebp, get ret.addr */
push %rbp /* push ret.addr */
lea 8(%rsp),%rbp /* setup frame ptr */
push %rcx /* save ecx */
mov %rbp,%rcx
movslq %eax,%rax
P0:
sub $4096,%rcx
test %rax,(%rcx)
sub $4096,%rax
cmp $4096,%rax
jge P0
sub %rax,%rcx
test %rax,(%rcx)
mov %rsp,%rax
mov %rcx,%rsp
mov (%rax),%rcx /* restore ecx */
jmp *8(%rax)
/* ---------------------------------------------- */
/* setjmp/longjmp support */
.globl _(tinyc_getbp)
_(tinyc_getbp):
mov %rbp,%rax
ret
/* ---------------------------------------------- */
#endif
/* ---------------------------------------------- */
|
matgla/tinycc | 1,185 | tests/thumb/armv8m/test_add_reg.S | .syntax unified
.thumb
.global _start
_start:
.global test_add_reg
test_add_reg:
// T1
adds r2, r2, r2
adds r1, r2, r3
adds r1, r4
itte eq
addeq r3, r2, r1
addeq r3, r2, r1
addne r1, r2, r3
// T2
add r8, r9
itte eq
addeq r1, r9
addeq r3, r3, r1
addne r9, r8
add r1, r2, r3, rrx
add r10, r11, r12, rrx
itte eq
addeq r10, r11, r12
addeq r10, r12
addne r11, r1
add r1, r1, r2, lsl #1
add r6, r6, r8, lsr #2
add r1, r1, r2, asr #3
add r6, r6, r8, ror #4
add r1, r4, r2, lsl #1
add r6, r4, r8, lsr #2
add r1, r8, r2, asr #3
add r6, r7, r8, ror #4
adds r1, r2, r3, rrx
adds r10, r11, r12, rrx
adds r1, r1, r2, lsl #1
adds r6, r6, r8, lsr #2
adds r1, r1, r2, asr #3
adds r6, r6, r8, ror #4
adds r1, r4, r2, lsl #1
adds r6, r4, r8, lsr #2
adds r1, r8, r2, asr #3
adds r6, r7, r8, ror #4
ittee eq
addeq r1, r1, r2, lsl #1
addeq r6, r6, r8, lsr #2
addne r1, r1, r2, asr #3
addne r6, r6, r8, ror #4
ittee eq
addseq r1, r4, r2, lsl #1
addseq r6, r4, r8, lsr #2
addsne r1, r8, r2, asr #3
addsne r6, r7, r8, ror #4 |
matgla/tinycc | 1,049 | tests/thumb/armv8m/test_str_imm.S | .syntax unified
.thumb
.global _start
_start:
.global test_str
test_str:
str r1, [r0, #16]
str r2, [r0, #15]
str r3, [r5, #10]
str r2, [r1, #12]
str r2, [r3]
ittee eq
streq r1, [r0, #110]
streq r2, [r0, #15]
strne r3, [r5, #10]
strne r2, [r1, #12]
str r1, [sp]
str r2, [sp, #4]
str r3, [sp, #4]
itte gt
strgt r1, [sp]
strgt r2, [sp, #4]
strle r3, [sp, #4]
str.w r1, [r0, #110]
str.w r2, [r0, #15]
str.w r3, [r5, #10]
str.w r2, [r1, #12]
str.w r2, [r3]
str.w r1, [sp]
str.w r2, [sp, #4]
str.w r3, [sp, #4]
str r1, [r10, #110]
str r12, [r0, #15]
str r3, [r5, #10]
str r11, [r10, #12]
str r12, [r11]
ittee eq
streq r10, [r10, #110]
streq r9, [r0, #15]
strne r11, [r5, #10]
strne r9, [r9, #12]
str r10, [sp]
str r12, [sp, #4]
str r12, [sp, #-4]
str r1, [r1, #-110]
str r12, [r0, #-15]
str r1, [r2], #10
str r1, [r2], #-15
str r1, [r3, #-110]!
str r12, [r0, #-15]!
|
matgla/tinycc | 1,124 | tests/thumb/armv8m/test_bic_reg.S | .syntax unified
.thumb
.global _start
_start:
.global test_bic_reg
test_bic_reg:
// T1
bics.n r2, r2, r5
itte eq
biceq r1, r1, r2
biceq r3, r5
bicne r5, r5, r1
bic r1, r1, r4
// T2
bic r1, r2, r3, rrx
bic r10, r11, r12, rrx
itte eq
biceq r10, r11, r12
biceq r10, r12
bicne r11, r1
bic r1, r1, r2, lsl #1
bic r6, r6, r8, lsr #2
bic r1, r1, r2, asr #3
bic r6, r6, r8, ror #4
bic r1, r4, r2, lsl #1
bic r6, r4, r8, lsr #2
bic r1, r8, r2, asr #3
bic r6, r7, r8, ror #4
bics r1, r2, r3, rrx
bics r10, r11, r12, rrx
bics r1, r1, r2, lsl #1
bics r6, r6, r8, lsr #2
bics r1, r1, r2, asr #3
bics r6, r6, r8, ror #4
bics r1, r4, r2, lsl #1
bics r6, r4, r8, lsr #2
bics r1, r8, r2, asr #3
bics r6, r7, r8, ror #4
ittee eq
biceq r1, r1, r2, lsl #1
biceq r6, r6, r8, lsr #2
bicne r1, r1, r2, asr #3
bicne r6, r6, r8, ror #4
ittee eq
bicseq r1, r4, r2, lsl #1
bicseq r6, r4, r8, lsr #2
bicsne r1, r8, r2, asr #3
bicsne r6, r7, r8, ror #4
|
matgla/tinycc | 1,201 | tests/thumb/armv8m/test_ldmdb.S | .syntax unified
.thumb
.global _start
_start:
.global test_ldmdb
test_ldmdb:
ldmdb r0!, {r1-r4, r5}
ldmdb r1!, {r2, r3}
ldmdb r3, {r1, r10}
ldmdb r9!, {r2-r3, r8}
ldmdb r9!, {r2-r3, r8, pc}
ittee eq
ldmdbeq r0!, {r1-r4, r5}
ldmdbeq r1!, {r2, r10}
ldmdbne r3, {r1, r2}
ldmdbne r9!, {r2-r3, r8}
ldmdb sp!, {r1-r4, r5}
ldmdb.w sp!, {r1-r4, r5, pc}
ldmdb sp!, {r2, r11}
ldmdb sp, {r1, r2}
ldmdb sp!, {r2-r3, r8}
ittee eq
ldmdbeq sp!, {r1-r4, r5}
ldmdbeq sp!, {r2, r12}
ldmdbne sp!, {r1, r2}
ldmdbne sp!, {r2-r3, r8}
ldmdb lr!, {r2-r3, r8}
ldmea r0!, {r1-r4, r5}
ldmea r1!, {r2, r14}
ldmea r3, {r1, r2}
ldmea r9!, {r2-r3, r8}
ldmea r9!, {r2-r3, r8, pc}
ittee eq
ldmeaeq r0!, {r1-r4, r5}
ldmeaeq r1!, {r2, r3}
ldmeane r3, {r1, r2}
ldmeane r9!, {r2-r3, r8}
ldmdb sp!, {r1-r4, r5}
ldmdb.w sp!, {r1-r4, r5, pc}
ldmdb sp!, {r2, r11}
ldmdb sp, {r1, r2}
ldmdb sp!, {r2-r3, r8}
ittee eq
ldmdbeq sp!, {r1-r4, r5}
ldmdbeq sp!, {r2, r8}
ldmdbne sp!, {r1, r2}
ldmdbne sp!, {r2-r3, r8}
ldmdb lr!, {r2-r3, r8}
|
matgla/tinycc | 1,101 | tests/thumb/armv8m/test_rsb_reg.S | .syntax unified
.thumb
.global _start
_start:
.global test_rsb_reg
test_rsb_reg:
// T1
rsbs r2, r2, r5
itte eq
rsbeq r1, r1, r2
rsbeq r3, r5
rsbne r5, r5, r1
rsb r1, r1, r4
// T2
rsb r1, r2, r3, rrx
rsb r10, r11, r12, rrx
itte eq
rsbeq r10, r11, r12
rsbeq r10, r12
rsbne r11, r1
rsb r1, r1, r2, lsl #1
rsb r6, r6, r8, lsr #2
rsb r1, r1, r2, asr #3
rsb r6, r6, r8, ror #4
rsb r1, r4, r2, lsl #1
rsb r6, r4, r8, lsr #2
rsb r1, r8, r2, asr #3
rsb r6, r7, r8, ror #4
rsbs r1, r2, r3, rrx
rsbs r10, r11, r12, rrx
rsbs r1, r1, r2, lsl #1
rsbs r6, r6, r8, lsr #2
rsbs r1, r1, r2, asr #3
rsbs r6, r6, r8, ror #4
rsbs r1, r4, r2, lsl #1
rsbs r6, r4, r8, lsr #2
rsbs r1, r8, r2, asr #3
rsbs r6, r7, r8, ror #4
ittee eq
rsbeq r1, r1, r2, lsl #1
rsbeq r6, r6, r8, lsr #2
rsbne r1, r1, r2, asr #3
rsbne r6, r6, r8, ror #4
ittee eq
rsbseq r1, r4, r2, lsl #1
rsbseq r6, r4, r8, lsr #2
rsbsne r1, r8, r2, asr #3
rsbsne r6, r7, r8, ror #4
|
matgla/tinycc | 1,157 | tests/thumb/armv8m/test_ldrsh_imm.S | .syntax unified
.thumb
.global _start
_start:
.global test_ldrsh
test_ldrsh:
ldrsh r1, [r0, #16]
ldrsh r2, [r0, #15]
ldrsh r3, [r5, #10]
ldrsh r2, [r1, #12]
ldrsh r2, [r3]
ittee eq
ldrsheq r1, [r0, #110]
ldrsheq r2, [r0, #15]
ldrshne r3, [r5, #10]
ldrshne r2, [r1, #12]
ldrsh r1, [sp]
ldrsh r2, [sp, #4]
ldrsh r3, [sp, #4]
itte gt
ldrshgt r1, [sp]
ldrshgt r2, [sp, #4]
ldrshle r3, [sp, #4]
ldrsh.w r1, [r0, #110]
ldrsh.w r2, [r0, #15]
ldrsh.w r3, [r5, #10]
ldrsh.w r2, [r1, #12]
ldrsh.w r2, [r3]
ldrsh.w r1, [sp]
ldrsh.w r2, [sp, #4]
ldrsh.w r3, [sp, #4]
ldrsh r1, [r10, #110]
ldrsh r12, [r0, #15]
ldrsh r3, [r5, #10]
ldrsh r11, [r10, #12]
ldrsh r12, [r11]
ittee eq
ldrsheq r10, [r10, #110]
ldrsheq r9, [r0, #15]
ldrshne r11, [r5, #10]
ldrshne r9, [r9, #12]
ldrsh r10, [sp]
ldrsh r12, [sp, #4]
ldrsh r12, [sp, #-4]
ldrsh r1, [r1, #-110]
ldrsh r12, [r0, #-15]
ldrsh r1, [r2], #10
ldrsh r1, [r2], #-15
ldrsh r1, [r3, #-110]!
ldrsh r12, [r0, #-15]!
|
matgla/tinycc | 1,114 | tests/thumb/armv8m/test_ldrh_imm.S | .syntax unified
.thumb
.global _start
_start:
.global test_ldrh
test_ldrh:
ldrh r1, [r0, #16]
ldrh r2, [r0, #15]
ldrh r3, [r5, #10]
ldrh r2, [r1, #12]
ldrh r2, [r3]
ittee eq
ldrheq r1, [r0, #110]
ldrheq r2, [r0, #15]
ldrhne r3, [r5, #10]
ldrhne r2, [r1, #12]
ldrh r1, [sp]
ldrh r2, [sp, #4]
ldrh r3, [sp, #4]
itte gt
ldrhgt r1, [sp]
ldrhgt r2, [sp, #4]
ldrhle r3, [sp, #4]
ldrh.w r1, [r0, #110]
ldrh.w r2, [r0, #15]
ldrh.w r3, [r5, #10]
ldrh.w r2, [r1, #12]
ldrh.w r2, [r3]
ldrh.w r1, [sp]
ldrh.w r2, [sp, #4]
ldrh.w r3, [sp, #4]
ldrh r1, [r10, #110]
ldrh r12, [r0, #15]
ldrh r3, [r5, #10]
ldrh r11, [r10, #12]
ldrh r12, [r11]
ittee eq
ldrheq r10, [r10, #110]
ldrheq r9, [r0, #15]
ldrhne r11, [r5, #10]
ldrhne r9, [r9, #12]
ldrh r10, [sp]
ldrh r12, [sp, #4]
ldrh r12, [sp, #-4]
ldrh r1, [r1, #-110]
ldrh r12, [r0, #-15]
ldrh r1, [r2], #10
ldrh r1, [r2], #-15
ldrh r1, [r3, #-110]!
ldrh r12, [r0, #-15]!
|
matgla/tinycc | 1,101 | tests/thumb/armv8m/test_orn_reg.S | .syntax unified
.thumb
.global _start
_start:
.global test_orn_reg
test_orn_reg:
// T1
orns r2, r2, r5
itte eq
orneq r1, r1, r2
orneq r3, r5
ornne r5, r5, r1
orn r1, r1, r4
// T2
orn r1, r2, r3, rrx
orn r10, r11, r12, rrx
itte eq
orneq r10, r11, r12
orneq r10, r12
ornne r11, r1
orn r1, r1, r2, lsl #1
orn r6, r6, r8, lsr #2
orn r1, r1, r2, asr #3
orn r6, r6, r8, ror #4
orn r1, r4, r2, lsl #1
orn r6, r4, r8, lsr #2
orn r1, r8, r2, asr #3
orn r6, r7, r8, ror #4
orns r1, r2, r3, rrx
orns r10, r11, r12, rrx
orns r1, r1, r2, lsl #1
orns r6, r6, r8, lsr #2
orns r1, r1, r2, asr #3
orns r6, r6, r8, ror #4
orns r1, r4, r2, lsl #1
orns r6, r4, r8, lsr #2
orns r1, r8, r2, asr #3
orns r6, r7, r8, ror #4
ittee eq
orneq r1, r1, r2, lsl #1
orneq r6, r6, r8, lsr #2
ornne r1, r1, r2, asr #3
ornne r6, r6, r8, ror #4
ittee eq
ornseq r1, r4, r2, lsl #1
ornseq r6, r4, r8, lsr #2
ornsne r1, r8, r2, asr #3
ornsne r6, r7, r8, ror #4
|
matgla/tinycc | 1,157 | tests/thumb/armv8m/test_ldrsb_imm.S | .syntax unified
.thumb
.global _start
_start:
.global test_ldrsb
test_ldrsb:
ldrsb r1, [r0, #16]
ldrsb r2, [r0, #15]
ldrsb r3, [r5, #10]
ldrsb r2, [r1, #12]
ldrsb r2, [r3]
ittee eq
ldrsbeq r1, [r0, #110]
ldrsbeq r2, [r0, #15]
ldrsbne r3, [r5, #10]
ldrsbne r2, [r1, #12]
ldrsb r1, [sp]
ldrsb r2, [sp, #4]
ldrsb r3, [sp, #4]
itte gt
ldrsbgt r1, [sp]
ldrsbgt r2, [sp, #4]
ldrsble r3, [sp, #4]
ldrsb.w r1, [r0, #110]
ldrsb.w r2, [r0, #15]
ldrsb.w r3, [r5, #10]
ldrsb.w r2, [r1, #12]
ldrsb.w r2, [r3]
ldrsb.w r1, [sp]
ldrsb.w r2, [sp, #4]
ldrsb.w r3, [sp, #4]
ldrsb r1, [r10, #110]
ldrsb r12, [r0, #15]
ldrsb r3, [r5, #10]
ldrsb r11, [r10, #12]
ldrsb r12, [r11]
ittee eq
ldrsbeq r10, [r10, #110]
ldrsbeq r9, [r0, #15]
ldrsbne r11, [r5, #10]
ldrsbne r9, [r9, #12]
ldrsb r10, [sp]
ldrsb r12, [sp, #4]
ldrsb r12, [sp, #-4]
ldrsb r1, [r1, #-110]
ldrsb r12, [r0, #-15]
ldrsb r1, [r2], #10
ldrsb r1, [r2], #-15
ldrsb r1, [r3, #-110]!
ldrsb r12, [r0, #-15]!
|
matgla/tinycc | 1,124 | tests/thumb/armv8m/test_eor_reg.S | .syntax unified
.thumb
.global _start
_start:
.global test_eor_reg
test_eor_reg:
// T1
eors.n r2, r2, r5
itte eq
eoreq r1, r1, r2
eoreq r3, r5
eorne r5, r5, r1
eor r1, r1, r4
// T2
eor r1, r2, r3, rrx
eor r10, r11, r12, rrx
itte eq
eoreq r10, r11, r12
eoreq r10, r12
eorne r11, r1
eor r1, r1, r2, lsl #1
eor r6, r6, r8, lsr #2
eor r1, r1, r2, asr #3
eor r6, r6, r8, ror #4
eor r1, r4, r2, lsl #1
eor r6, r4, r8, lsr #2
eor r1, r8, r2, asr #3
eor r6, r7, r8, ror #4
eors r1, r2, r3, rrx
eors r10, r11, r12, rrx
eors r1, r1, r2, lsl #1
eors r6, r6, r8, lsr #2
eors r1, r1, r2, asr #3
eors r6, r6, r8, ror #4
eors r1, r4, r2, lsl #1
eors r6, r4, r8, lsr #2
eors r1, r8, r2, asr #3
eors r6, r7, r8, ror #4
ittee eq
eoreq r1, r1, r2, lsl #1
eoreq r6, r6, r8, lsr #2
eorne r1, r1, r2, asr #3
eorne r6, r6, r8, ror #4
ittee eq
eorseq r1, r4, r2, lsl #1
eorseq r6, r4, r8, lsr #2
eorsne r1, r8, r2, asr #3
eorsne r6, r7, r8, ror #4
|
matgla/tinycc | 1,092 | tests/thumb/armv8m/test_strb_imm.S | .syntax unified
.thumb
.global _start
_start:
.global test_strb
test_strb:
strb r1, [r0, #16]
strb r2, [r0, #15]
strb r3, [r5, #10]
strb r2, [r1, #12]
strb r2, [r3]
ittee eq
strbeq r1, [r0, #110]
strbeq r2, [r0, #15]
strbne r3, [r5, #10]
strbne r2, [r1, #12]
strb r1, [sp]
strb r2, [sp, #4]
strb r3, [sp, #4]
itte gt
strbgt r1, [sp]
strbgt r2, [sp, #4]
strble r3, [sp, #4]
strb.w r1, [r0, #110]
strb.w r2, [r0, #15]
strb.w r3, [r5, #10]
strb.w r2, [r1, #12]
strb.w r2, [r3]
strb.w r1, [sp]
strb.w r2, [sp, #4]
strb.w r3, [sp, #4]
strb r1, [r10, #110]
strb r12, [r0, #15]
strb r3, [r5, #10]
strb r11, [r10, #12]
strb r12, [r11]
ittee eq
strbeq r10, [r10, #110]
strbeq r9, [r0, #15]
strbne r11, [r5, #10]
strbne r9, [r9, #12]
strb r10, [sp]
strb r12, [sp, #4]
strb r12, [sp, #-4]
strb r1, [r1, #-110]
strb r12, [r0, #-15]
strb r1, [r2], #10
strb r1, [r2], #-15
strb r1, [r3, #-110]!
strb r12, [r0, #-15]!
|
matgla/tinycc | 1,092 | tests/thumb/armv8m/test_strh_imm.S | .syntax unified
.thumb
.global _start
_start:
.global test_strh
test_strh:
strh r1, [r0, #16]
strh r2, [r0, #15]
strh r3, [r5, #10]
strh r2, [r1, #12]
strh r2, [r3]
ittee eq
strheq r1, [r0, #110]
strheq r2, [r0, #15]
strhne r3, [r5, #10]
strhne r2, [r1, #12]
strh r1, [sp]
strh r2, [sp, #4]
strh r3, [sp, #4]
itte gt
strhgt r1, [sp]
strhgt r2, [sp, #4]
strhle r3, [sp, #4]
strh.w r1, [r0, #110]
strh.w r2, [r0, #15]
strh.w r3, [r5, #10]
strh.w r2, [r1, #12]
strh.w r2, [r3]
strh.w r1, [sp]
strh.w r2, [sp, #4]
strh.w r3, [sp, #4]
strh r1, [r10, #110]
strh r12, [r0, #15]
strh r3, [r5, #10]
strh r11, [r10, #12]
strh r12, [r11]
ittee eq
strheq r10, [r10, #110]
strheq r9, [r0, #15]
strhne r11, [r5, #10]
strhne r9, [r9, #12]
strh r10, [sp]
strh r12, [sp, #4]
strh r12, [sp, #-4]
strh r1, [r1, #-110]
strh r12, [r0, #-15]
strh r1, [r2], #10
strh r1, [r2], #-15
strh r1, [r3, #-110]!
strh r12, [r0, #-15]!
|
matgla/tinycc | 1,101 | tests/thumb/armv8m/test_orr_reg.S | .syntax unified
.thumb
.global _start
_start:
.global test_orr_reg
test_orr_reg:
// T1
orrs r2, r2, r5
itte eq
orreq r1, r1, r2
orreq r3, r5
orrne r5, r5, r1
orr r1, r1, r4
// T2
orr r1, r2, r3, rrx
orr r10, r11, r12, rrx
itte eq
orreq r10, r11, r12
orreq r10, r12
orrne r11, r1
orr r1, r1, r2, lsl #1
orr r6, r6, r8, lsr #2
orr r1, r1, r2, asr #3
orr r6, r6, r8, ror #4
orr r1, r4, r2, lsl #1
orr r6, r4, r8, lsr #2
orr r1, r8, r2, asr #3
orr r6, r7, r8, ror #4
orrs r1, r2, r3, rrx
orrs r10, r11, r12, rrx
orrs r1, r1, r2, lsl #1
orrs r6, r6, r8, lsr #2
orrs r1, r1, r2, asr #3
orrs r6, r6, r8, ror #4
orrs r1, r4, r2, lsl #1
orrs r6, r4, r8, lsr #2
orrs r1, r8, r2, asr #3
orrs r6, r7, r8, ror #4
ittee eq
orreq r1, r1, r2, lsl #1
orreq r6, r6, r8, lsr #2
orrne r1, r1, r2, asr #3
orrne r6, r6, r8, ror #4
ittee eq
orrseq r1, r4, r2, lsl #1
orrseq r6, r4, r8, lsr #2
orrsne r1, r8, r2, asr #3
orrsne r6, r7, r8, ror #4
|
matgla/tinycc | 1,157 | tests/thumb/armv8m/test_sub_reg.S | .syntax unified
.thumb
.global _start
_start:
.global test_sub_reg
test_sub_reg:
// T1
subs r2, r2, r2
subs r1, r2, r3
subs r1, r4
itte eq
subeq r3, r2, r1
subeq r3, r2, r1
subne r1, r2, r3
// T2
sub r8, r9
itte eq
subeq r1, r9
subeq r3, r3, r1
subne r9, r8
sub r1, r2, r3, rrx
sub r10, r11, r12, rrx
itte eq
subeq r10, r11, r12
subeq r10, r12
subne r11, r1
sub r1, r1, r2, lsl #1
sub r6, r6, r8, lsr #2
sub r1, r1, r2, asr #3
sub r6, r6, r8, ror #4
sub r1, r4, r2, lsl #1
sub r6, r4, r8, lsr #2
sub r1, r8, r2, asr #3
sub r6, r7, r8, ror #4
subs r1, r2, r3, rrx
subs r10, r11, r12, rrx
subs r1, r1, r2, lsl #1
subs r6, r6, r8, lsr #2
subs r1, r1, r2, asr #3
subs r6, r6, r8, ror #4
subs r1, r4, r2, lsl #1
subs r6, r4, r8, lsr #2
subs r1, r8, r2, asr #3
subs r6, r7, r8, ror #4
ittee eq
subeq r1, r1, r2, lsl #1
subeq r6, r6, r8, lsr #2
subne r1, r1, r2, asr #3
subne r6, r6, r8, ror #4
ittee eq
subseq r1, r4, r2, lsl #1
subseq r6, r4, r8, lsr #2
subsne r1, r8, r2, asr #3
subsne r6, r7, r8, ror #4 |
matgla/tinycc | 1,124 | tests/thumb/armv8m/test_and_reg.S | .syntax unified
.thumb
.global _start
_start:
.global test_and_reg
test_and_reg:
// T1
ands.n r2, r2, r5
itte eq
andeq r1, r1, r2
andeq r3, r5
andne r5, r5, r1
and r1, r1, r4
// T2
and r1, r2, r3, rrx
and r10, r11, r12, rrx
itte eq
andeq r10, r11, r12
andeq r10, r12
andne r11, r1
and r1, r1, r2, lsl #1
and r6, r6, r8, lsr #2
and r1, r1, r2, asr #3
and r6, r6, r8, ror #4
and r1, r4, r2, lsl #1
and r6, r4, r8, lsr #2
and r1, r8, r2, asr #3
and r6, r7, r8, ror #4
ands r1, r2, r3, rrx
ands r10, r11, r12, rrx
ands r1, r1, r2, lsl #1
ands r6, r6, r8, lsr #2
ands r1, r1, r2, asr #3
ands r6, r6, r8, ror #4
ands r1, r4, r2, lsl #1
ands r6, r4, r8, lsr #2
ands r1, r8, r2, asr #3
ands r6, r7, r8, ror #4
ittee eq
andeq r1, r1, r2, lsl #1
andeq r6, r6, r8, lsr #2
andne r1, r1, r2, asr #3
andne r6, r6, r8, ror #4
ittee eq
andseq r1, r4, r2, lsl #1
andseq r6, r4, r8, lsr #2
andsne r1, r8, r2, asr #3
andsne r6, r7, r8, ror #4
|
matgla/tinycc | 2,469 | tests/thumb/armv8m/test_b.S | .syntax unified
.thumb
.global _start
_start:
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.global jump_target
jump_target:
movs r0, #0
cmp r1, #1
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
.global test_b
test_b:
b.n jump_target
b.w next_target
.asciz "Helloasfh9ueawh9fhe9wahf79wah9efh9wahe97fh9w7ehf79haf"
next_target:
movs r1, #1
b.n jump_target
it eq
beq.n test_b
it ne
bne.n next_target
it gt
bgt.n jump_target
cmp r0, #1
bgt.n test_b
cmp r0, #2
bgt.w test_b
|
matgla/tinycc | 1,114 | tests/thumb/armv8m/test_ldrb_imm.S | .syntax unified
.thumb
.global _start
_start:
.global test_ldrb
test_ldrb:
ldrb r1, [r0, #16]
ldrb r2, [r0, #15]
ldrb r3, [r5, #10]
ldrb r2, [r1, #12]
ldrb r2, [r3]
ittee eq
ldrbeq r1, [r0, #110]
ldrbeq r2, [r0, #15]
ldrbne r3, [r5, #10]
ldrbne r2, [r1, #12]
ldrb r1, [sp]
ldrb r2, [sp, #4]
ldrb r3, [sp, #4]
itte gt
ldrbgt r1, [sp]
ldrbgt r2, [sp, #4]
ldrble r3, [sp, #4]
ldrb.w r1, [r0, #110]
ldrb.w r2, [r0, #15]
ldrb.w r3, [r5, #10]
ldrb.w r2, [r1, #12]
ldrb.w r2, [r3]
ldrb.w r1, [sp]
ldrb.w r2, [sp, #4]
ldrb.w r3, [sp, #4]
ldrb r1, [r10, #110]
ldrb r12, [r0, #15]
ldrb r3, [r5, #10]
ldrb r11, [r10, #12]
ldrb r12, [r11]
ittee eq
ldrbeq r10, [r10, #110]
ldrbeq r9, [r0, #15]
ldrbne r11, [r5, #10]
ldrbne r9, [r9, #12]
ldrb r10, [sp]
ldrb r12, [sp, #4]
ldrb r12, [sp, #-4]
ldrb r1, [r1, #-110]
ldrb r12, [r0, #-15]
ldrb r1, [r2], #10
ldrb r1, [r2], #-15
ldrb r1, [r3, #-110]!
ldrb r12, [r0, #-15]!
|
matgla/tinycc | 1,124 | tests/thumb/armv8m/test_adc_reg.S | .syntax unified
.thumb
.global _start
_start:
.global test_adc_reg
test_adc_reg:
// T1
adcs.n r2, r2, r5
itte eq
adceq r1, r1, r2
adceq r3, r5
adcne r5, r5, r1
adc r1, r1, r4
// T2
adc r1, r2, r3, rrx
adc r10, r11, r12, rrx
itte eq
adceq r10, r11, r12
adceq r10, r12
adcne r11, r1
adc r1, r1, r2, lsl #1
adc r6, r6, r8, lsr #2
adc r1, r1, r2, asr #3
adc r6, r6, r8, ror #4
adc r1, r4, r2, lsl #1
adc r6, r4, r8, lsr #2
adc r1, r8, r2, asr #3
adc r6, r7, r8, ror #4
adcs r1, r2, r3, rrx
adcs r10, r11, r12, rrx
adcs r1, r1, r2, lsl #1
adcs r6, r6, r8, lsr #2
adcs r1, r1, r2, asr #3
adcs r6, r6, r8, ror #4
adcs r1, r4, r2, lsl #1
adcs r6, r4, r8, lsr #2
adcs r1, r8, r2, asr #3
adcs r6, r7, r8, ror #4
ittee eq
adceq r1, r1, r2, lsl #1
adceq r6, r6, r8, lsr #2
adcne r1, r1, r2, asr #3
adcne r6, r6, r8, ror #4
ittee eq
adcseq r1, r4, r2, lsl #1
adcseq r6, r4, r8, lsr #2
adcsne r1, r8, r2, asr #3
adcsne r6, r7, r8, ror #4
|
matgla/tinycc | 1,103 | tests/thumb/armv8m/test_sbc_reg.S | .syntax unified
.thumb
.global _start
_start:
.global test_sbc_reg
test_sbc_reg:
// T1
sbcs.n r2, r2, r5
itte eq
sbceq r1, r1, r2
sbceq r3, r5
sbcne r5, r5, r1
sbc r1, r1, r4
// T2
sbc r1, r2, r3, rrx
sbc r10, r11, r12, rrx
itte eq
sbceq r10, r11, r12
sbceq r10, r12
sbcne r11, r1
sbc r1, r1, r2, lsl #1
sbc r6, r6, r8, lsr #2
sbc r1, r1, r2, asr #3
sbc r6, r6, r8, ror #4
sbc r1, r4, r2, lsl #1
sbc r6, r4, r8, lsr #2
sbc r1, r8, r2, asr #3
sbc r6, r7, r8, ror #4
sbcs r1, r2, r3, rrx
sbcs r10, r11, r12, rrx
sbcs r1, r1, r2, lsl #1
sbcs r6, r6, r8, lsr #2
sbcs r1, r1, r2, asr #3
sbcs r6, r6, r8, ror #4
sbcs r1, r4, r2, lsl #1
sbcs r6, r4, r8, lsr #2
sbcs r1, r8, r2, asr #3
sbcs r6, r7, r8, ror #4
ittee eq
sbceq r1, r1, r2, lsl #1
sbceq r6, r6, r8, lsr #2
sbcne r1, r1, r2, asr #3
sbcne r6, r6, r8, ror #4
ittee eq
sbcseq r1, r4, r2, lsl #1
sbcseq r6, r4, r8, lsr #2
sbcsne r1, r8, r2, asr #3
sbcsne r6, r7, r8, ror #4
|
matgla/tinycc | 1,504 | tests/thumb/armv8m/test_mov_imm.S | .syntax unified
.thumb
.global _start
_start:
.global test_mov_imm
test_mov_imm:
// T1: movs Rd, #imm8 (16-bit)
// Only low registers (r0-r7)
movs r0, #1
movs r7, #255
movs.w r2, #1
movs.n r1, #2
// T3: mov Rd, #imm16 (32-bit, MOVW)
// Any register (r0-r15)
movw r8, #0x1234
mov r9, #1
mov r0, #0xfff
mov r1, #10
cmp r0, #1
ittte eq
moveq r8, #0xdead
moveq r1, #0x0d
moveq r10, #0x0f
movne r3, #0x12
ittee cs
movcs r2, #0xde
movcs r8, #0xab12
movcc r9, #0x12
movcc r10, #0xffff
iteet mi
movmi r2, #0xde
movpl r8, #0xab12
movpl r9, #0x12
movmi r10, #0xffff
it ne
movne r0, #1
ite gt
movgt r1, #2
movle r1, #4
it eq
moveq r1, #1
itt eq
moveq r2, #2
moveq r3, #3
ite eq
moveq r4, #3
movne r5, #5
ittt eq
moveq r5, #7
moveq r8, #9
moveq r9, #10
itte eq
moveq r9, #100
moveq r10, #123
movne r11, #10
itet eq
moveq r9, #100
movne r10, #123
moveq r11, #10
itee eq
moveq r9, #100
movne r10, #123
movne r11, #10
itttt eq
moveq r9, #100
moveq r10, #123
moveq r11, #10
moveq r12, #120
ittte eq
moveq r9, #100
moveq r10, #123
moveq r11, #10
movne r12, #120
ittet eq
moveq r9, #100
moveq r10, #123
movne r11, #10
moveq r12, #120
ittee eq
moveq r9, #100
moveq r10, #123
movne r11, #10
movne r12, #120
itett eq
moveq r9, #100
movne r10, #123
moveq r11, #10
moveq r12, #120
itete eq
moveq r9, #100
movne r10, #123
moveq r11, #10
movne r12, #120
iteet eq
moveq r9, #100
movne r10, #123
movne r11, #10
moveq r12, #120
iteee eq
moveq r9, #100
movne r10, #123
movne r11, #10
movne r12, #120
|
matgla/tinycc | 1,071 | tests/thumb/armv8m/test_ldr_imm.S | .syntax unified
.thumb
.global _start
_start:
.global test_ldr
test_ldr:
ldr r1, [r0, #16]
ldr r2, [r0, #15]
ldr r3, [r5, #10]
ldr r2, [r1, #12]
ldr r2, [r3]
ittee eq
ldreq r1, [r0, #110]
ldreq r2, [r0, #15]
ldrne r3, [r5, #10]
ldrne r2, [r1, #12]
ldr r1, [sp]
ldr r2, [sp, #4]
ldr r3, [sp, #4]
itte gt
ldrgt r1, [sp]
ldrgt r2, [sp, #4]
ldrle r3, [sp, #4]
ldr.w r1, [r0, #110]
ldr.w r2, [r0, #15]
ldr.w r3, [r5, #10]
ldr.w r2, [r1, #12]
ldr.w r2, [r3]
ldr.w r1, [sp]
ldr.w r2, [sp, #4]
ldr.w r3, [sp, #4]
ldr r1, [r10, #110]
ldr r12, [r0, #15]
ldr r3, [r5, #10]
ldr r11, [r10, #12]
ldr r12, [r11]
ittee eq
ldreq r10, [r10, #110]
ldreq r9, [r0, #15]
ldrne r11, [r5, #10]
ldrne r9, [r9, #12]
ldr r10, [sp]
ldr r12, [sp, #4]
ldr r12, [sp, #-4]
ldr r1, [r1, #-110]
ldr r12, [r0, #-15]
ldr r1, [r2], #10
ldr r1, [r2], #-15
ldr r1, [r3, #-110]!
ldr r12, [r0, #-15]!
|
MaxLastBreath/TOTK-DFPS | 2,446 | source/lib/init/crt0.s | .section ".text.crt0","ax"
.macro FROM_MOD0 register_num, offset
ldr w\register_num, [x24, #\offset]
sxtw x\register_num, w\register_num
add x\register_num, x\register_num, x24
.endm
.macro FUNC_RELATIVE_ASLR name, register_num, symbol
.word \symbol - .
\name:
ldr w\register_num, [x30]
sxtw x\register_num, w\register_num
add x\register_num, x\register_num, x30
.endm
.global __module_start
__module_start:
b entrypoint
.word __nx_mod0 - __module_start
.align 4
.ascii "~~exlaunch uwu~~"
entrypoint:
// Arguments on NSO entry:
// x0=zero | x1=main thread handle
// Arguments on NRO entry (homebrew ABI):
// x0=ptr to env context | x1=UINT64_MAX (-1 aka 0xFFFFFFFFFFFFFFFF)
// Arguments on user-mode exception entry:
// x0=excpt type (non-zero) | x1=ptr to excpt context
// Detect and handle user-mode exceptions first:
// if (x0 != 0 && x1 != UINT64_MAX) exl_exception_entry(<inargs>);
cmp x0, #0
ccmn x1, #1, #4, ne // 4 = Z
beq get_module_info
b exl_exception_entry
get_module_info:
// Get start of our module
bl __get_module_start_shim
FUNC_RELATIVE_ASLR __get_module_start_shim, 23, __module_start
// Get location of MOD0
mov x24, xzr
ldr w24, [x23, #4]
add x24, x24, x23
// Get BSS regions from MOD0
FROM_MOD0 8, 0x8
FROM_MOD0 9, 0xC
bssclr_start:
// Calculate BSS address/size
sub x9, x9, x8 // calculate BSS size
add x9, x9, #7 // round up to 8
bic x9, x9, #7 // ^
// Clear the BSS in 8-byte units
bss_loop:
subs w9, w9, #8
str xzr, [x8], #8
bne bss_loop
// Preserve registers across function calls
mov x25, x0 // entrypoint argument 0
mov x26, x1 // entrypoint argument 1
// Parse ELF .dynamic section (which applies relocations to our module)
mov x0, x23
FROM_MOD0 1, 0x4
bl exl_dynamic
mov x0, x25
mov x1, x26
b exl_entrypoint_init
// failsafe
.word 0xdeadbeef
.section ".rodata.mod0","a"
.hidden exl_nx_module_runtime
.align 2
__nx_mod0:
.ascii "MOD0"
.word __dynamic_start__ - __nx_mod0
.word __bss_start__ - __nx_mod0
.word __bss_end__ - __nx_mod0
.word __eh_frame_hdr_start__ - __nx_mod0
.word __eh_frame_hdr_end__ - __nx_mod0
.word exl_nx_module_runtime - __nx_mod0 |
MaxLastBreath/TOTK-DFPS | 1,303 | source/lib/nx/arm/cache.s | .macro CODE_BEGIN name
.section .text.\name, "ax", %progbits
.global \name
.hidden \name
.type \name, %function
.align 2
.cfi_startproc
\name:
.endm
.macro CODE_END
.cfi_endproc
.endm
CODE_BEGIN armDCacheFlush
add x1, x1, x0
mrs x8, CTR_EL0
lsr x8, x8, #16
and x8, x8, #0xf
mov x9, #4
lsl x9, x9, x8
sub x10, x9, #1
bic x8, x0, x10
mov x10, x1
armDCacheFlush_L0:
dc civac, x8
add x8, x8, x9
cmp x8, x10
bcc armDCacheFlush_L0
dsb sy
ret
CODE_END
CODE_BEGIN armDCacheClean
add x1, x1, x0
mrs x8, CTR_EL0
lsr x8, x8, #16
and x8, x8, #0xf
mov x9, #4
lsl x9, x9, x8
sub x10, x9, #1
bic x8, x0, x10
mov x10, x1
armDCacheClean_L0:
dc cvac, x8
add x8, x8, x9
cmp x8, x10
bcc armDCacheClean_L0
dsb sy
ret
CODE_END
CODE_BEGIN armICacheInvalidate
add x1, x1, x0
mrs x8, CTR_EL0
and x8, x8, #0xf
mov x9, #4
lsl x9, x9, x8
sub x10, x9, #1
bic x8, x0, x10
mov x10, x1
armICacheInvalidate_L0:
ic ivau, x8
add x8, x8, x9
cmp x8, x10
bcc armICacheInvalidate_L0
dsb sy
ret
CODE_END
CODE_BEGIN armDCacheZero
add x1, x1, x0
mrs x8, CTR_EL0
lsr x8, x8, #16
and x8, x8, #0xf
mov x9, #4
lsl x9, x9, x8
sub x10, x9, #1
bic x8, x0, x10
mov x10, x1
armDCacheZero_L0:
dc zva, x8
add x8, x8, x9
cmp x8, x10
bcc armDCacheZero_L0
dsb sy
ret
CODE_END
|
MaxLastBreath/TOTK-DFPS | 8,193 | source/lib/nx/kernel/svc.s | .macro SVC_BEGIN name
.section .text.\name, "ax", %progbits
.global \name
.type \name, %function
.hidden \name
.align 2
.cfi_startproc
\name:
.endm
.macro SVC_END
.cfi_endproc
.endm
SVC_BEGIN svcSetHeapSize
str x0, [sp, #-16]!
svc 0x1
ldr x2, [sp], #16
str x1, [x2]
ret
SVC_END
SVC_BEGIN svcSetMemoryPermission
svc 0x2
ret
SVC_END
SVC_BEGIN svcSetMemoryAttribute
svc 0x3
ret
SVC_END
SVC_BEGIN svcMapMemory
svc 0x4
ret
SVC_END
SVC_BEGIN svcUnmapMemory
svc 0x5
ret
SVC_END
SVC_BEGIN svcQueryMemory
str x1, [sp, #-16]!
svc 0x6
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcExitProcess
svc 0x7
ret
SVC_END
SVC_BEGIN svcCreateThread
str x0, [sp, #-16]!
svc 0x8
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcStartThread
svc 0x9
ret
SVC_END
SVC_BEGIN svcExitThread
svc 0xA
ret
SVC_END
SVC_BEGIN svcSleepThread
svc 0xB
ret
SVC_END
SVC_BEGIN svcGetThreadPriority
str x0, [sp, #-16]!
svc 0xC
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcSetThreadPriority
svc 0xD
ret
SVC_END
SVC_BEGIN svcGetThreadCoreMask
stp x0, x1, [sp, #-16]!
svc 0xE
ldp x3, x4, [sp], #16
str w1, [x3]
str w2, [x4]
ret
SVC_END
SVC_BEGIN svcSetThreadCoreMask
svc 0xF
ret
SVC_END
SVC_BEGIN svcGetCurrentProcessorNumber
svc 0x10
ret
SVC_END
SVC_BEGIN svcSignalEvent
svc 0x11
ret
SVC_END
SVC_BEGIN svcClearEvent
svc 0x12
ret
SVC_END
SVC_BEGIN svcMapSharedMemory
svc 0x13
ret
SVC_END
SVC_BEGIN svcUnmapSharedMemory
svc 0x14
ret
SVC_END
SVC_BEGIN svcCreateTransferMemory
str x0, [sp, #-16]!
svc 0x15
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcCloseHandle
svc 0x16
ret
SVC_END
SVC_BEGIN svcResetSignal
svc 0x17
ret
SVC_END
SVC_BEGIN svcWaitSynchronization
str x0, [sp, #-16]!
svc 0x18
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcCancelSynchronization
svc 0x19
ret
SVC_END
SVC_BEGIN svcArbitrateLock
svc 0x1A
ret
SVC_END
SVC_BEGIN svcArbitrateUnlock
svc 0x1B
ret
SVC_END
SVC_BEGIN svcWaitProcessWideKeyAtomic
svc 0x1C
ret
SVC_END
SVC_BEGIN svcSignalProcessWideKey
svc 0x1D
ret
SVC_END
SVC_BEGIN svcGetSystemTick
svc 0x1E
ret
SVC_END
SVC_BEGIN svcConnectToNamedPort
str x0, [sp, #-16]!
svc 0x1F
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcSendSyncRequest
svc 0x21
ret
SVC_END
SVC_BEGIN svcSendSyncRequestWithUserBuffer
svc 0x22
ret
SVC_END
SVC_BEGIN svcSendAsyncRequestWithUserBuffer
str x0, [sp, #-16]!
svc 0x23
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcGetProcessId
str x0, [sp, #-16]!
svc 0x24
ldr x2, [sp], #16
str x1, [x2]
ret
SVC_END
SVC_BEGIN svcGetThreadId
str x0, [sp, #-16]!
svc 0x25
ldr x2, [sp], #16
str x1, [x2]
ret
SVC_END
SVC_BEGIN svcBreak
svc 0x26
ret
SVC_END
SVC_BEGIN svcOutputDebugString
svc 0x27
ret
SVC_END
SVC_BEGIN svcReturnFromException
svc 0x28
ret
SVC_END
SVC_BEGIN svcGetInfo
str x0, [sp, #-16]!
svc 0x29
ldr x2, [sp], #16
str x1, [x2]
ret
SVC_END
SVC_BEGIN svcMapPhysicalMemory
svc 0x2C
ret
SVC_END
SVC_BEGIN svcUnmapPhysicalMemory
svc 0x2D
ret
SVC_END
SVC_BEGIN svcGetResourceLimitLimitValue
str x0, [sp, #-16]!
svc 0x30
ldr x2, [sp], #16
str x1, [x2]
ret
SVC_END
SVC_BEGIN svcGetResourceLimitCurrentValue
str x0, [sp, #-16]!
svc 0x31
ldr x2, [sp], #16
str x1, [x2]
ret
SVC_END
SVC_BEGIN svcSetThreadActivity
svc 0x32
ret
SVC_END
SVC_BEGIN svcGetThreadContext3
svc 0x33
ret
SVC_END
SVC_BEGIN svcCreateSession
stp x0, x1, [sp, #-16]!
svc 0x40
ldp x3, x4, [sp], #16
str w1, [x3]
str w2, [x4]
ret
SVC_END
SVC_BEGIN svcAcceptSession
str x0, [sp, #-16]!
svc 0x41
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcReplyAndReceive
str x0, [sp, #-16]!
svc 0x43
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcReplyAndReceiveWithUserBuffer
str x0, [sp, #-16]!
svc 0x44
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcCreateEvent
stp x0, x1, [sp, #-16]!
svc 0x45
ldp x3, x4, [sp], #16
str w1, [x3]
str w2, [x4]
ret
SVC_END
SVC_BEGIN svcMapPhysicalMemoryUnsafe
svc 0x48
ret
SVC_END
SVC_BEGIN svcUnmapPhysicalMemoryUnsafe
svc 0x49
ret
SVC_END
SVC_BEGIN svcSetUnsafeLimit
svc 0x4A
ret
SVC_END
SVC_BEGIN svcCreateCodeMemory
str x0, [sp, #-16]!
svc 0x4B
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcControlCodeMemory
svc 0x4C
ret
SVC_END
SVC_BEGIN svcReadWriteRegister
str x0, [sp, #-16]!
svc 0x4E
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcCreateSharedMemory
str x0, [sp, #-16]!
svc 0x50
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcMapTransferMemory
svc 0x51
ret
SVC_END
SVC_BEGIN svcUnmapTransferMemory
svc 0x52
ret
SVC_END
SVC_BEGIN svcCreateInterruptEvent
str x0, [sp, #-16]!
svc 0x53
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcQueryPhysicalAddress
str x0, [sp, #-16]!
svc 0x54
ldr x4, [sp], #16
stp x1, x2, [x4]
str x3, [x4, #16]
ret
SVC_END
SVC_BEGIN svcQueryIoMapping
str x0, [sp, #-16]!
svc 0x55
ldr x2, [sp], #16
str x1, [x2]
ret
SVC_END
SVC_BEGIN svcCreateDeviceAddressSpace
str x0, [sp, #-16]!
svc 0x56
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcAttachDeviceAddressSpace
svc 0x57
ret
SVC_END
SVC_BEGIN svcDetachDeviceAddressSpace
svc 0x58
ret
SVC_END
SVC_BEGIN svcMapDeviceAddressSpaceByForce
svc 0x59
ret
SVC_END
SVC_BEGIN svcMapDeviceAddressSpaceAligned
svc 0x5A
ret
SVC_END
SVC_BEGIN svcUnmapDeviceAddressSpace
svc 0x5C
ret
SVC_END
SVC_BEGIN svcDebugActiveProcess
str x0, [sp, #-16]!
svc 0x60
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcBreakDebugProcess
svc 0x61
ret
SVC_END
SVC_BEGIN svcTerminateDebugProcess
svc 0x62
ret
SVC_END
SVC_BEGIN svcGetDebugEvent
svc 0x63
ret
SVC_END
SVC_BEGIN svcLegacyContinueDebugEvent
svc 0x64
ret
SVC_END
SVC_BEGIN svcContinueDebugEvent
svc 0x64
ret
SVC_END
SVC_BEGIN svcGetProcessList
str x0, [sp, #-16]!
svc 0x65
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcGetThreadList
str x0, [sp, #-16]!
svc 0x66
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcGetDebugThreadContext
svc 0x67
ret
SVC_END
SVC_BEGIN svcSetDebugThreadContext
svc 0x68
ret
SVC_END
SVC_BEGIN svcQueryDebugProcessMemory
str x1, [sp, #-16]!
svc 0x69
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcReadDebugProcessMemory
svc 0x6A
ret
SVC_END
SVC_BEGIN svcWriteDebugProcessMemory
svc 0x6B
ret
SVC_END
SVC_BEGIN svcGetDebugThreadParam
stp x0, x1, [sp, #-16]!
svc 0x6D
ldp x3, x4, [sp], #16
str x1, [x3]
str w2, [x4]
ret
SVC_END
SVC_BEGIN svcGetSystemInfo
str x0, [sp, #-16]!
svc 0x6F
ldr x2, [sp], #16
str x1, [x2]
ret
SVC_END
SVC_BEGIN svcCreatePort
stp x0, x1, [sp, #-16]!
svc 0x70
ldp x3, x4, [sp], #16
str w1, [x3]
str w2, [x4]
ret
SVC_END
SVC_BEGIN svcManageNamedPort
str x0, [sp, #-16]!
svc 0x71
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcConnectToPort
str x0, [sp, #-16]!
svc 0x72
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcSetProcessMemoryPermission
svc 0x73
ret
SVC_END
SVC_BEGIN svcMapProcessMemory
svc 0x74
ret
SVC_END
SVC_BEGIN svcUnmapProcessMemory
svc 0x75
ret
SVC_END
SVC_BEGIN svcQueryProcessMemory
str x1, [sp, #-16]!
svc 0x76
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcMapProcessCodeMemory
svc 0x77
ret
SVC_END
SVC_BEGIN svcUnmapProcessCodeMemory
svc 0x78
ret
SVC_END
SVC_BEGIN svcCreateProcess
str x0, [sp, #-16]!
svc 0x79
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcStartProcess
svc 0x7A
ret
SVC_END
SVC_BEGIN svcTerminateProcess
svc 0x7B
ret
SVC_END
SVC_BEGIN svcGetProcessInfo
str x0, [sp, #-16]!
svc 0x7C
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcCreateResourceLimit
str x0, [sp, #-16]!
svc 0x7D
ldr x2, [sp], #16
str w1, [x2]
ret
SVC_END
SVC_BEGIN svcSetResourceLimitLimitValue
svc 0x7E
ret
SVC_END
SVC_BEGIN svcCallSecureMonitor
str x0, [sp, #-16]!
mov x8, x0
ldp x0, x1, [x8]
ldp x2, x3, [x8, #0x10]
ldp x4, x5, [x8, #0x20]
ldp x6, x7, [x8, #0x30]
svc 0x7F
ldr x8, [sp], #16
stp x0, x1, [x8]
stp x2, x3, [x8, #0x10]
stp x4, x5, [x8, #0x20]
stp x6, x7, [x8, #0x30]
ret
SVC_END
|
MaxLastBreath/TOTK-DFPS | 1,192 | source/lib/reloc/rtld/dl_trampoline.s | .section ".text", "ax"
#define ip0 x16
#define ip1 x17
.global __rtld_runtime_resolve
.type __rtld_runtime_resolve, @function
__rtld_runtime_resolve:
/* AArch64 we get called with:
ip0 (x16) &PLTGOT[2]
ip1 (x17) temp(dl resolver entry point)
[sp, #0] &PLTGOT[n]
What we need:
x0 = calling module (ip0[-1])
x1 = .rel.plt index ((ip1 - ip0 - 8) / 8)
*/
ldr x17, [sp]
str x29, [sp]
stp x8, x19, [sp, #-0x10]!
stp x6, x7, [sp, #-0x10]!
stp x4, x5, [sp, #-0x10]!
stp x2, x3, [sp, #-0x10]!
stp x0, x1, [sp, #-0x10]!
stp q6, q7, [sp, #-0x20]!
stp q4, q5, [sp, #-0x20]!
stp q2, q3, [sp, #-0x20]!
stp q0, q1, [sp, #-0x20]!
mov x29, sp
mov x19, x17
sub x1, x17, x16
sub x1, x1, #8
lsr x1, x1, #3
ldur x0, [x16, #-8]
bl __rtld_lazy_bind_symbol
str x0, [x19]
mov x16, x0
ldp q0, q1, [sp], #0x20
ldp q2, q3, [sp], #0x20
ldp q4, q5, [sp], #0x20
ldp q6, q7, [sp], #0x20
ldp x0, x1, [sp], #0x10
ldp x2, x3, [sp], #0x10
ldp x4, x5, [sp], #0x10
ldp x6, x7, [sp], #0x10
ldp x8, x19, [sp], #0x10
ldp x29, x30, [sp], #0x10
br x16 |
MaxLastBreath/TOTK-DFPS | 1,869 | source/lib/hook/nx64/inline_asm.s | .macro CODE_BEGIN name
.section .text.\name, "ax", %progbits
.global \name
.type \name, %function
.align 2
.cfi_startproc
\name:
.endm
.macro CODE_END
.cfi_endproc
.endm
/* Size of stack to reserve for the context. Adjust this along with CtxStackSize in inline_impl.cpp */
.set CTX_STACK_SIZE, 0x100
/* For these macros, LR is deliberately not backed up as that's handled by the entry's entrypoint. */
.macro armBackupRegisters
sub sp, sp, CTX_STACK_SIZE
stp x0, x1, [sp, #0x00]
stp x2, x3, [sp, #0x10]
stp x4, x5, [sp, #0x20]
stp x6, x7, [sp, #0x30]
stp x8, x9, [sp, #0x40]
stp x10, x11, [sp, #0x50]
stp x12, x13, [sp, #0x60]
stp x14, x15, [sp, #0x70]
stp x16, x17, [sp, #0x80]
stp x18, x19, [sp, #0x90]
stp x20, x21, [sp, #0xA0]
stp x22, x23, [sp, #0xB0]
stp x24, x25, [sp, #0xC0]
stp x26, x27, [sp, #0xD0]
stp x28, x29, [sp, #0xE0]
.endm
.macro armRecoverRegisters
ldp x0, x1, [sp, #0x00]
ldp x2, x3, [sp, #0x10]
ldp x4, x5, [sp, #0x20]
ldp x6, x7, [sp, #0x30]
ldp x8, x9, [sp, #0x40]
ldp x10, x11, [sp, #0x50]
ldp x12, x13, [sp, #0x60]
ldp x14, x15, [sp, #0x70]
ldp x16, x17, [sp, #0x80]
ldp x18, x19, [sp, #0x90]
ldp x20, x21, [sp, #0xA0]
ldp x22, x23, [sp, #0xB0]
ldp x24, x25, [sp, #0xC0]
ldp x26, x27, [sp, #0xD0]
ldp x28, x29, [sp, #0xE0]
add sp, sp, CTX_STACK_SIZE
.endm
CODE_BEGIN exl_inline_hook_impl
armBackupRegisters
/* LR contains a pointer to the called entry here. */
mov x19, lr
/* Load inline context for the first argument of the callback. */
mov x0, sp
/* Load then call callback. */
ldr x20, [x19, #0x8]
blr x20
/* Keep a hold of entry pointer before restoring all the registers. */
mov lr, x19
armRecoverRegisters
/* Return to entry. */
ret
CODE_END |
Mbwide/MQTT_ONENET_ESP8266_STM32_FREERTOS | 15,145 | CORE/startup_stm32f10x_hd.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
Mbwide/MQTT_ONENET_ESP8266_STM32_FREERTOS | 5,593 | FreeRTOS/portable/RVDS/ARM7_LPC21xx/portASM.s | ;/*
; FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
; All rights reserved
;
;
; ***************************************************************************
; * *
; * FreeRTOS tutorial books are available in pdf and paperback. *
; * Complete, revised, and edited pdf reference manuals are also *
; * available. *
; * *
; * Purchasing FreeRTOS documentation will not only help you, by *
; * ensuring you get running as quickly as possible and with an *
; * in-depth knowledge of how to use FreeRTOS, it will also help *
; * the FreeRTOS project to continue with its mission of providing *
; * professional grade, cross platform, de facto standard solutions *
; * for microcontrollers - completely free of charge! *
; * *
; * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
; * *
; * Thank you for using FreeRTOS, and thank you for your support! *
; * *
; ***************************************************************************
;
;
; This file is part of the FreeRTOS distribution.
;
; FreeRTOS is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License (version 2) as published by the
; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
; >>>NOTE<<< The modification to the GPL is included to allow you to
; distribute a combined work that includes FreeRTOS without being obliged to
; provide the source code for proprietary components outside of the FreeRTOS
; kernel. FreeRTOS is distributed in the hope that it will be useful, but
; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
; more details. You should have received a copy of the GNU General Public
; License and the FreeRTOS license exception along with FreeRTOS; if not it
; can be viewed here: http://www.freertos.org/a00114.html and also obtained
; by writing to Richard Barry, contact details for whom are available on the
; FreeRTOS WEB site.
;
; 1 tab == 4 spaces!
;
; http://www.FreeRTOS.org - Documentation, latest information, license and
; contact details.
;
; http://www.SafeRTOS.com - A version that is certified for use in safety
; critical systems.
;
; http://www.OpenRTOS.com - Commercial support, development, porting,
; licensing and training services.
;*/
INCLUDE portmacro.inc
IMPORT vTaskSwitchContext
IMPORT xTaskIncrementTick
EXPORT vPortYieldProcessor
EXPORT vPortStartFirstTask
EXPORT vPreemptiveTick
EXPORT vPortYield
VICVECTADDR EQU 0xFFFFF030
T0IR EQU 0xE0004000
T0MATCHBIT EQU 0x00000001
ARM
AREA PORT_ASM, CODE, READONLY
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Starting the first task is done by just restoring the context
; setup by pxPortInitialiseStack
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
vPortStartFirstTask
PRESERVE8
portRESTORE_CONTEXT
vPortYield
PRESERVE8
SVC 0
bx lr
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Interrupt service routine for the SWI interrupt. The vector table is
; configured in the startup.s file.
;
; vPortYieldProcessor() is used to manually force a context switch. The
; SWI interrupt is generated by a call to taskYIELD() or portYIELD().
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
vPortYieldProcessor
PRESERVE8
; Within an IRQ ISR the link register has an offset from the true return
; address, but an SWI ISR does not. Add the offset manually so the same
; ISR return code can be used in both cases.
ADD LR, LR, #4
; Perform the context switch.
portSAVE_CONTEXT ; Save current task context
LDR R0, =vTaskSwitchContext ; Get the address of the context switch function
MOV LR, PC ; Store the return address
BX R0 ; Call the contedxt switch function
portRESTORE_CONTEXT ; restore the context of the selected task
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Interrupt service routine for preemptive scheduler tick timer
; Only used if portUSE_PREEMPTION is set to 1 in portmacro.h
;
; Uses timer 0 of LPC21XX Family
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
vPreemptiveTick
PRESERVE8
portSAVE_CONTEXT ; Save the context of the current task.
LDR R0, =xTaskIncrementTick ; Increment the tick count.
MOV LR, PC ; This may make a delayed task ready
BX R0 ; to run.
CMP R0, #0
BEQ SkipContextSwitch
LDR R0, =vTaskSwitchContext ; Find the highest priority task that
MOV LR, PC ; is ready to run.
BX R0
SkipContextSwitch
MOV R0, #T0MATCHBIT ; Clear the timer event
LDR R1, =T0IR
STR R0, [R1]
LDR R0, =VICVECTADDR ; Acknowledge the interrupt
STR R0,[R0]
portRESTORE_CONTEXT ; Restore the context of the highest
; priority task that is ready to run.
END
|
Mbwide/MQTT_ONENET_ESP8266_STM32_FREERTOS | 6,530 | FreeRTOS/portable/RVDS/ARM_CA9/portASM.s | ;/*
; FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
; All rights reserved
;
;
; ***************************************************************************
; * *
; * FreeRTOS tutorial books are available in pdf and paperback. *
; * Complete, revised, and edited pdf reference manuals are also *
; * available. *
; * *
; * Purchasing FreeRTOS documentation will not only help you, by *
; * ensuring you get running as quickly as possible and with an *
; * in-depth knowledge of how to use FreeRTOS, it will also help *
; * the FreeRTOS project to continue with its mission of providing *
; * professional grade, cross platform, de facto standard solutions *
; * for microcontrollers - completely free of charge! *
; * *
; * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
; * *
; * Thank you for using FreeRTOS, and thank you for your support! *
; * *
; ***************************************************************************
;
;
; This file is part of the FreeRTOS distribution.
;
; FreeRTOS is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License (version 2) as published by the
; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
; >>>NOTE<<< The modification to the GPL is included to allow you to
; distribute a combined work that includes FreeRTOS without being obliged to
; provide the source code for proprietary components outside of the FreeRTOS
; kernel. FreeRTOS is distributed in the hope that it will be useful, but
; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
; more details. You should have received a copy of the GNU General Public
; License and the FreeRTOS license exception along with FreeRTOS; if not it
; can be viewed here: http://www.freertos.org/a00114.html and also obtained
; by writing to Richard Barry, contact details for whom are available on the
; FreeRTOS WEB site.
;
; 1 tab == 4 spaces!
;
; http://www.FreeRTOS.org - Documentation, latest information, license and
; contact details.
;
; http://www.SafeRTOS.com - A version that is certified for use in safety
; critical systems.
;
; http://www.OpenRTOS.com - Commercial support, development, porting,
; licensing and training services.
;*/
INCLUDE portmacro.inc
IMPORT vApplicationIRQHandler
IMPORT vTaskSwitchContext
IMPORT ulPortYieldRequired
IMPORT ulPortInterruptNesting
IMPORT vTaskSwitchContext
IMPORT ulICCIAR
IMPORT ulICCEOIR
EXPORT FreeRTOS_SWI_Handler
EXPORT FreeRTOS_IRQ_Handler
EXPORT vPortRestoreTaskContext
ARM
AREA PORT_ASM, CODE, READONLY
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; SVC handler is used to yield a task.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
FreeRTOS_SWI_Handler
PRESERVE8
; Save the context of the current task and select a new task to run.
portSAVE_CONTEXT
LDR R0, =vTaskSwitchContext
BLX R0
portRESTORE_CONTEXT
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; vPortRestoreTaskContext is used to start the scheduler.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
vPortRestoreTaskContext
; Switch to system mode
CPS #SYS_MODE
portRESTORE_CONTEXT
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; PL390 GIC interrupt handler
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
FreeRTOS_IRQ_Handler
; Return to the interrupted instruction.
SUB lr, lr, #4
; Push the return address and SPSR
PUSH {lr}
MRS lr, SPSR
PUSH {lr}
; Change to supervisor mode to allow reentry.
CPS #SVC_MODE
; Push used registers.
PUSH {r0-r4, r12}
; Increment nesting count. r3 holds the address of ulPortInterruptNesting
; for future use. r1 holds the original ulPortInterruptNesting value for
; future use.
LDR r3, =ulPortInterruptNesting
LDR r1, [r3]
ADD r4, r1, #1
STR r4, [r3]
; Read value from the interrupt acknowledge register, which is stored in r0
; for future parameter and interrupt clearing use.
LDR r2, =ulICCIAR
LDR r0, [r2]
; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
; future use.
MOV r2, sp
AND r2, r2, #4
SUB sp, sp, r2
; Call the interrupt handler
PUSH {r0-r3, lr}
LDR r1, =vApplicationIRQHandler
BLX r1
POP {r0-r3, lr}
ADD sp, sp, r2
CPSID i
; Write the value read from ICCIAR to ICCEOIR
LDR r4, =ulICCEOIR
STR r0, [r4]
; Restore the old nesting count
STR r1, [r3]
; A context switch is never performed if the nesting count is not 0
CMP r1, #0
BNE exit_without_switch
; Did the interrupt request a context switch? r1 holds the address of
; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
; use.
LDR r1, =ulPortYieldRequired
LDR r0, [r1]
CMP r0, #0
BNE switch_before_exit
exit_without_switch
; No context switch. Restore used registers, LR_irq and SPSR before
; returning.
POP {r0-r4, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
MOVS PC, LR
switch_before_exit
; A context swtich is to be performed. Clear the context switch pending
; flag.
MOV r0, #0
STR r0, [r1]
; Restore used registers, LR-irq and SPSR before saving the context
; to the task stack.
POP {r0-r4, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
portSAVE_CONTEXT
; Call the function that selects the new task to execute.
; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
; instructions, or 8 byte aligned stack allocated data. LR does not need
; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
LDR r0, =vTaskSwitchContext
BLX r0
; Restore the context of, and branch to, the task selected to execute next.
portRESTORE_CONTEXT
END
|
mck1117/wideband | 11,157 | firmware/boards/f1_rev3/openblt/startup_stm32f103xb.s | /**
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
* @file startup_stm32f103xb.s
* @author MCD Application Team
* @version V4.2.0
* @date 31-March-2017
* @brief STM32F103xB Devices vector table for Atollic toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
*
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x108. This is for boot in RAM mode for
STM32F10x Medium Density devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
mck1117/wideband | 11,157 | firmware/boards/f1_common/openblt/startup_stm32f103xb.s | /**
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
* @file startup_stm32f103xb.s
* @author MCD Application Team
* @version V4.2.0
* @date 31-March-2017
* @brief STM32F103xB Devices vector table for Atollic toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
*
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x108. This is for boot in RAM mode for
STM32F10x Medium Density devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
mck1117/wideband | 11,157 | firmware/boards/f1_dual_rev1/openblt/startup_stm32f103xb.s | /**
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
* @file startup_stm32f103xb.s
* @author MCD Application Team
* @version V4.2.0
* @date 31-March-2017
* @brief STM32F103xB Devices vector table for Atollic toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
*
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x108. This is for boot in RAM mode for
STM32F10x Medium Density devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
Mdashdotdashn/LittleGPTracker | 1,883 | sources/Adapters/DINGOO/System/gpmemset.s | /* Copyright (C) 1998 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Philip Blundell <philb@gnu.org>
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
/*#include <sys/syscall.h>*/
.text
.global gpmemset;
.type gpmemset,%function
.align 4; \
gpmemset:
mov a4, a1
cmp a3, $8 @ at least 8 bytes to do?
blt 2f
orr a2, a2, a2, lsl $8
orr a2, a2, a2, lsl $16
1:
tst a4, $3 @ aligned yet?
strneb a2, [a4], $1
subne a3, a3, $1
bne 1b
mov ip, a2
1:
cmp a3, $8 @ 8 bytes still to do?
blt 2f
stmia a4!, {a2, ip}
sub a3, a3, $8
cmp a3, $8 @ 8 bytes still to do?
blt 2f
stmia a4!, {a2, ip}
sub a3, a3, $8
cmp a3, $8 @ 8 bytes still to do?
blt 2f
stmia a4!, {a2, ip}
sub a3, a3, $8
cmp a3, $8 @ 8 bytes still to do?
stmgeia a4!, {a2, ip}
subge a3, a3, $8
bge 1b
2:
movs a3, a3 @ anything left?
moveq pc, lr @ nope
rsb a3, a3, $7
add pc, pc, a3, lsl $2
mov r0, r0
strb a2, [a4], $1
strb a2, [a4], $1
strb a2, [a4], $1
strb a2, [a4], $1
strb a2, [a4], $1
strb a2, [a4], $1
strb a2, [a4], $1
mov pc, lr
.size gpmemset,.-gpmemset;
|
Mdashdotdashn/LittleGPTracker | 12,207 | sources/Adapters/DINGOO/System/gpmemcpy.s | /* $NetBSD: gpmemcpy.S,v 1.3 1997/11/22 03:27:12 mark Exp $ */
/*-
* Copyright (c) 1997 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Neil A. Carson and Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS\'\' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* This was modified by Jay Monkman <jmonkman@smoothsmoothie.com> to
* save and restore r12. This is necessary for RTEMS.
*/
/* #include <machine/asm.h>*/
#define ENTRY(_LABEL) \\
.global _LABEL; _LABEL:
.globl gpmemcpy
gpmemcpy:
stmfd sp!, {r0, r12, lr}
bl _gpmemcpy
ldmfd sp!, {r0, r12, pc}
.globl gpmemmove
gpmemmove:
stmfd sp!, {r0, r12, lr}
bl _gpmemcpy
ldmfd sp!, {r0, r12, pc}
/*
* This is one fun bit of code ...
* Some easy listening music is suggested while trying to understand this
* code e.g. Iron Maiden
*
* For anyone attempting to understand it :
*
* The core code is implemented here with simple stubs for gpmemcpy()
* gpmemmove() and bcopy().
*
* All local labels are prefixed with Lgpmemcpy_
* Following the prefix a label starting f is used in the forward copy code
* while a label using b is used in the backwards copy code
* The source and destination addresses determine whether a forward or
* backward copy is performed.
* Separate bits of code are used to deal with the following situations
* for both the forward and backwards copy.
* unaligned source address
* unaligned destination address
* Separate copy routines are used to produce an optimised result for each
* of these cases.
* The copy code will use LDM/STM instructions to copy up to 32 bytes at
* a time where possible.
*
* Note: r12 (aka ip) can be trashed during the function along with
* r0-r3 although r0-r2 have defined uses i.e. src, dest, len through out.
* Additional registers are preserved prior to use i.e. r4, r5 & lr
*
* Apologies for the state of the comments;-)
*/
/*
_gpmemcpy:
*/
.globl _gpmemcpy
_gpmemcpy:
/* Determine copy direction */
cmp r1, r0
bcc Lgpmemcpy_backwards
moveq r0, #0 /* Quick abort for len=0 */
moveq pc, lr
stmdb sp!, {r0, lr} /* gpmemcpy() returns dest addr */
subs r2, r2, #4
blt Lgpmemcpy_fl4 /* less than 4 bytes */
ands r12, r0, #3
bne Lgpmemcpy_fdestul /* oh unaligned destination addr */
ands r12, r1, #3
bne Lgpmemcpy_fsrcul /* oh unaligned source addr */
Lgpmemcpy_ft8:
/* We have aligned source and destination */
subs r2, r2, #8
blt Lgpmemcpy_fl12 /* less than 12 bytes (4 from above) */
subs r2, r2, #0x14
blt Lgpmemcpy_fl32 /* less than 32 bytes (12 from above) */
stmdb sp!, {r4} /* borrow r4 */
/* blat 32 bytes at a time */
/* XXX for really big copies perhaps we should use more registers */
Lgpmemcpy_floop32:
ldmia r1!, {r3, r4, r12, lr}
stmia r0!, {r3, r4, r12, lr}
ldmia r1!, {r3, r4, r12, lr}
stmia r0!, {r3, r4, r12, lr}
subs r2, r2, #0x20
bge Lgpmemcpy_floop32
cmn r2, #0x10
ldmgeia r1!, {r3, r4, r12, lr} /* blat a remaining 16 bytes */
stmgeia r0!, {r3, r4, r12, lr}
subge r2, r2, #0x10
ldmia sp!, {r4} /* return r4 */
Lgpmemcpy_fl32:
adds r2, r2, #0x14
/* blat 12 bytes at a time */
Lgpmemcpy_floop12:
ldmgeia r1!, {r3, r12, lr}
stmgeia r0!, {r3, r12, lr}
subges r2, r2, #0x0c
bge Lgpmemcpy_floop12
Lgpmemcpy_fl12:
adds r2, r2, #8
blt Lgpmemcpy_fl4
subs r2, r2, #4
ldrlt r3, [r1], #4
strlt r3, [r0], #4
ldmgeia r1!, {r3, r12}
stmgeia r0!, {r3, r12}
subge r2, r2, #4
Lgpmemcpy_fl4:
/* less than 4 bytes to go */
adds r2, r2, #4
ldmeqia sp!, {r0, pc} /* done */
/* copy the crud byte at a time */
cmp r2, #2
ldrb r3, [r1], #1
strb r3, [r0], #1
ldrgeb r3, [r1], #1
strgeb r3, [r0], #1
ldrgtb r3, [r1], #1
strgtb r3, [r0], #1
ldmia sp!, {r0, pc}
/* erg - unaligned destination */
Lgpmemcpy_fdestul:
rsb r12, r12, #4
cmp r12, #2
/* align destination with byte copies */
ldrb r3, [r1], #1
strb r3, [r0], #1
ldrgeb r3, [r1], #1
strgeb r3, [r0], #1
ldrgtb r3, [r1], #1
strgtb r3, [r0], #1
subs r2, r2, r12
blt Lgpmemcpy_fl4 /* less the 4 bytes */
ands r12, r1, #3
beq Lgpmemcpy_ft8 /* we have an aligned source */
/* erg - unaligned source */
/* This is where it gets nasty ... */
Lgpmemcpy_fsrcul:
bic r1, r1, #3
ldr lr, [r1], #4
cmp r12, #2
bgt Lgpmemcpy_fsrcul3
beq Lgpmemcpy_fsrcul2
cmp r2, #0x0c
blt Lgpmemcpy_fsrcul1loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5}
Lgpmemcpy_fsrcul1loop16:
mov r3, lr, lsr #8
ldmia r1!, {r4, r5, r12, lr}
orr r3, r3, r4, lsl #24
mov r4, r4, lsr #8
orr r4, r4, r5, lsl #24
mov r5, r5, lsr #8
orr r5, r5, r12, lsl #24
mov r12, r12, lsr #8
orr r12, r12, lr, lsl #24
stmia r0!, {r3-r5, r12}
subs r2, r2, #0x10
bge Lgpmemcpy_fsrcul1loop16
ldmia sp!, {r4, r5}
adds r2, r2, #0x0c
blt Lgpmemcpy_fsrcul1l4
Lgpmemcpy_fsrcul1loop4:
mov r12, lr, lsr #8
ldr lr, [r1], #4
orr r12, r12, lr, lsl #24
str r12, [r0], #4
subs r2, r2, #4
bge Lgpmemcpy_fsrcul1loop4
Lgpmemcpy_fsrcul1l4:
sub r1, r1, #3
b Lgpmemcpy_fl4
Lgpmemcpy_fsrcul2:
cmp r2, #0x0c
blt Lgpmemcpy_fsrcul2loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5}
Lgpmemcpy_fsrcul2loop16:
mov r3, lr, lsr #16
ldmia r1!, {r4, r5, r12, lr}
orr r3, r3, r4, lsl #16
mov r4, r4, lsr #16
orr r4, r4, r5, lsl #16
mov r5, r5, lsr #16
orr r5, r5, r12, lsl #16
mov r12, r12, lsr #16
orr r12, r12, lr, lsl #16
stmia r0!, {r3-r5, r12}
subs r2, r2, #0x10
bge Lgpmemcpy_fsrcul2loop16
ldmia sp!, {r4, r5}
adds r2, r2, #0x0c
blt Lgpmemcpy_fsrcul2l4
Lgpmemcpy_fsrcul2loop4:
mov r12, lr, lsr #16
ldr lr, [r1], #4
orr r12, r12, lr, lsl #16
str r12, [r0], #4
subs r2, r2, #4
bge Lgpmemcpy_fsrcul2loop4
Lgpmemcpy_fsrcul2l4:
sub r1, r1, #2
b Lgpmemcpy_fl4
Lgpmemcpy_fsrcul3:
cmp r2, #0x0c
blt Lgpmemcpy_fsrcul3loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5}
Lgpmemcpy_fsrcul3loop16:
mov r3, lr, lsr #24
ldmia r1!, {r4, r5, r12, lr}
orr r3, r3, r4, lsl #8
mov r4, r4, lsr #24
orr r4, r4, r5, lsl #8
mov r5, r5, lsr #24
orr r5, r5, r12, lsl #8
mov r12, r12, lsr #24
orr r12, r12, lr, lsl #8
stmia r0!, {r3-r5, r12}
subs r2, r2, #0x10
bge Lgpmemcpy_fsrcul3loop16
ldmia sp!, {r4, r5}
adds r2, r2, #0x0c
blt Lgpmemcpy_fsrcul3l4
Lgpmemcpy_fsrcul3loop4:
mov r12, lr, lsr #24
ldr lr, [r1], #4
orr r12, r12, lr, lsl #8
str r12, [r0], #4
subs r2, r2, #4
bge Lgpmemcpy_fsrcul3loop4
Lgpmemcpy_fsrcul3l4:
sub r1, r1, #1
b Lgpmemcpy_fl4
Lgpmemcpy_backwards:
add r1, r1, r2
add r0, r0, r2
subs r2, r2, #4
blt Lgpmemcpy_bl4 /* less than 4 bytes */
ands r12, r0, #3
bne Lgpmemcpy_bdestul /* oh unaligned destination addr */
ands r12, r1, #3
bne Lgpmemcpy_bsrcul /* oh unaligned source addr */
Lgpmemcpy_bt8:
/* We have aligned source and destination */
subs r2, r2, #8
blt Lgpmemcpy_bl12 /* less than 12 bytes (4 from above) */
stmdb sp!, {r4, lr}
subs r2, r2, #0x14 /* less than 32 bytes (12 from above) */
blt Lgpmemcpy_bl32
/* blat 32 bytes at a time */
/* XXX for really big copies perhaps we should use more registers */
Lgpmemcpy_bloop32:
ldmdb r1!, {r3, r4, r12, lr}
stmdb r0!, {r3, r4, r12, lr}
ldmdb r1!, {r3, r4, r12, lr}
stmdb r0!, {r3, r4, r12, lr}
subs r2, r2, #0x20
bge Lgpmemcpy_bloop32
Lgpmemcpy_bl32:
cmn r2, #0x10
ldmgedb r1!, {r3, r4, r12, lr} /* blat a remaining 16 bytes */
stmgedb r0!, {r3, r4, r12, lr}
subge r2, r2, #0x10
adds r2, r2, #0x14
ldmgedb r1!, {r3, r12, lr} /* blat a remaining 12 bytes */
stmgedb r0!, {r3, r12, lr}
subge r2, r2, #0x0c
ldmia sp!, {r4, lr}
Lgpmemcpy_bl12:
adds r2, r2, #8
blt Lgpmemcpy_bl4
subs r2, r2, #4
ldrlt r3, [r1, #-4]!
strlt r3, [r0, #-4]!
ldmgedb r1!, {r3, r12}
stmgedb r0!, {r3, r12}
subge r2, r2, #4
Lgpmemcpy_bl4:
/* less than 4 bytes to go */
adds r2, r2, #4
moveq pc, lr /* done */
/* copy the crud byte at a time */
cmp r2, #2
ldrb r3, [r1, #-1]!
strb r3, [r0, #-1]!
ldrgeb r3, [r1, #-1]!
strgeb r3, [r0, #-1]!
ldrgtb r3, [r1, #-1]!
strgtb r3, [r0, #-1]!
mov pc, lr
/* erg - unaligned destination */
Lgpmemcpy_bdestul:
cmp r12, #2
/* align destination with byte copies */
ldrb r3, [r1, #-1]!
strb r3, [r0, #-1]!
ldrgeb r3, [r1, #-1]!
strgeb r3, [r0, #-1]!
ldrgtb r3, [r1, #-1]!
strgtb r3, [r0, #-1]!
subs r2, r2, r12
blt Lgpmemcpy_bl4 /* less than 4 bytes to go */
ands r12, r1, #3
beq Lgpmemcpy_bt8 /* we have an aligned source */
/* erg - unaligned source */
/* This is where it gets nasty ... */
Lgpmemcpy_bsrcul:
bic r1, r1, #3
ldr r3, [r1, #0]
cmp r12, #2
blt Lgpmemcpy_bsrcul1
beq Lgpmemcpy_bsrcul2
cmp r2, #0x0c
blt Lgpmemcpy_bsrcul3loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5, lr}
Lgpmemcpy_bsrcul3loop16:
mov lr, r3, lsl #8
ldmdb r1!, {r3-r5, r12}
orr lr, lr, r12, lsr #24
mov r12, r12, lsl #8
orr r12, r12, r5, lsr #24
mov r5, r5, lsl #8
orr r5, r5, r4, lsr #24
mov r4, r4, lsl #8
orr r4, r4, r3, lsr #24
stmdb r0!, {r4, r5, r12, lr}
subs r2, r2, #0x10
bge Lgpmemcpy_bsrcul3loop16
ldmia sp!, {r4, r5, lr}
adds r2, r2, #0x0c
blt Lgpmemcpy_bsrcul3l4
Lgpmemcpy_bsrcul3loop4:
mov r12, r3, lsl #8
ldr r3, [r1, #-4]!
orr r12, r12, r3, lsr #24
str r12, [r0, #-4]!
subs r2, r2, #4
bge Lgpmemcpy_bsrcul3loop4
Lgpmemcpy_bsrcul3l4:
add r1, r1, #3
b Lgpmemcpy_bl4
Lgpmemcpy_bsrcul2:
cmp r2, #0x0c
blt Lgpmemcpy_bsrcul2loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5, lr}
Lgpmemcpy_bsrcul2loop16:
mov lr, r3, lsl #16
ldmdb r1!, {r3-r5, r12}
orr lr, lr, r12, lsr #16
mov r12, r12, lsl #16
orr r12, r12, r5, lsr #16
mov r5, r5, lsl #16
orr r5, r5, r4, lsr #16
mov r4, r4, lsl #16
orr r4, r4, r3, lsr #16
stmdb r0!, {r4, r5, r12, lr}
subs r2, r2, #0x10
bge Lgpmemcpy_bsrcul2loop16
ldmia sp!, {r4, r5, lr}
adds r2, r2, #0x0c
blt Lgpmemcpy_bsrcul2l4
Lgpmemcpy_bsrcul2loop4:
mov r12, r3, lsl #16
ldr r3, [r1, #-4]!
orr r12, r12, r3, lsr #16
str r12, [r0, #-4]!
subs r2, r2, #4
bge Lgpmemcpy_bsrcul2loop4
Lgpmemcpy_bsrcul2l4:
add r1, r1, #2
b Lgpmemcpy_bl4
Lgpmemcpy_bsrcul1:
cmp r2, #0x0c
blt Lgpmemcpy_bsrcul1loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5, lr}
Lgpmemcpy_bsrcul1loop32:
mov lr, r3, lsl #24
ldmdb r1!, {r3-r5, r12}
orr lr, lr, r12, lsr #8
mov r12, r12, lsl #24
orr r12, r12, r5, lsr #8
mov r5, r5, lsl #24
orr r5, r5, r4, lsr #8
mov r4, r4, lsl #24
orr r4, r4, r3, lsr #8
stmdb r0!, {r4, r5, r12, lr}
subs r2, r2, #0x10
bge Lgpmemcpy_bsrcul1loop32
ldmia sp!, {r4, r5, lr}
adds r2, r2, #0x0c
blt Lgpmemcpy_bsrcul1l4
Lgpmemcpy_bsrcul1loop4:
mov r12, r3, lsl #24
ldr r3, [r1, #-4]!
orr r12, r12, r3, lsr #8
str r12, [r0, #-4]!
subs r2, r2, #4
bge Lgpmemcpy_bsrcul1loop4
Lgpmemcpy_bsrcul1l4:
add r1, r1, #1
b Lgpmemcpy_bl4
|
Mdashdotdashn/LittleGPTracker | 1,883 | sources/Adapters/CAANOO/System/gpmemset.s | /* Copyright (C) 1998 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Philip Blundell <philb@gnu.org>
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
/*#include <sys/syscall.h>*/
.text
.global gpmemset;
.type gpmemset,%function
.align 4; \
gpmemset:
mov a4, a1
cmp a3, $8 @ at least 8 bytes to do?
blt 2f
orr a2, a2, a2, lsl $8
orr a2, a2, a2, lsl $16
1:
tst a4, $3 @ aligned yet?
strneb a2, [a4], $1
subne a3, a3, $1
bne 1b
mov ip, a2
1:
cmp a3, $8 @ 8 bytes still to do?
blt 2f
stmia a4!, {a2, ip}
sub a3, a3, $8
cmp a3, $8 @ 8 bytes still to do?
blt 2f
stmia a4!, {a2, ip}
sub a3, a3, $8
cmp a3, $8 @ 8 bytes still to do?
blt 2f
stmia a4!, {a2, ip}
sub a3, a3, $8
cmp a3, $8 @ 8 bytes still to do?
stmgeia a4!, {a2, ip}
subge a3, a3, $8
bge 1b
2:
movs a3, a3 @ anything left?
moveq pc, lr @ nope
rsb a3, a3, $7
add pc, pc, a3, lsl $2
mov r0, r0
strb a2, [a4], $1
strb a2, [a4], $1
strb a2, [a4], $1
strb a2, [a4], $1
strb a2, [a4], $1
strb a2, [a4], $1
strb a2, [a4], $1
mov pc, lr
.size gpmemset,.-gpmemset;
|
Mdashdotdashn/LittleGPTracker | 12,207 | sources/Adapters/CAANOO/System/gpmemcpy.s | /* $NetBSD: gpmemcpy.S,v 1.3 1997/11/22 03:27:12 mark Exp $ */
/*-
* Copyright (c) 1997 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Neil A. Carson and Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS\'\' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* This was modified by Jay Monkman <jmonkman@smoothsmoothie.com> to
* save and restore r12. This is necessary for RTEMS.
*/
/* #include <machine/asm.h>*/
#define ENTRY(_LABEL) \\
.global _LABEL; _LABEL:
.globl gpmemcpy
gpmemcpy:
stmfd sp!, {r0, r12, lr}
bl _gpmemcpy
ldmfd sp!, {r0, r12, pc}
.globl gpmemmove
gpmemmove:
stmfd sp!, {r0, r12, lr}
bl _gpmemcpy
ldmfd sp!, {r0, r12, pc}
/*
* This is one fun bit of code ...
* Some easy listening music is suggested while trying to understand this
* code e.g. Iron Maiden
*
* For anyone attempting to understand it :
*
* The core code is implemented here with simple stubs for gpmemcpy()
* gpmemmove() and bcopy().
*
* All local labels are prefixed with Lgpmemcpy_
* Following the prefix a label starting f is used in the forward copy code
* while a label using b is used in the backwards copy code
* The source and destination addresses determine whether a forward or
* backward copy is performed.
* Separate bits of code are used to deal with the following situations
* for both the forward and backwards copy.
* unaligned source address
* unaligned destination address
* Separate copy routines are used to produce an optimised result for each
* of these cases.
* The copy code will use LDM/STM instructions to copy up to 32 bytes at
* a time where possible.
*
* Note: r12 (aka ip) can be trashed during the function along with
* r0-r3 although r0-r2 have defined uses i.e. src, dest, len through out.
* Additional registers are preserved prior to use i.e. r4, r5 & lr
*
* Apologies for the state of the comments;-)
*/
/*
_gpmemcpy:
*/
.globl _gpmemcpy
_gpmemcpy:
/* Determine copy direction */
cmp r1, r0
bcc Lgpmemcpy_backwards
moveq r0, #0 /* Quick abort for len=0 */
moveq pc, lr
stmdb sp!, {r0, lr} /* gpmemcpy() returns dest addr */
subs r2, r2, #4
blt Lgpmemcpy_fl4 /* less than 4 bytes */
ands r12, r0, #3
bne Lgpmemcpy_fdestul /* oh unaligned destination addr */
ands r12, r1, #3
bne Lgpmemcpy_fsrcul /* oh unaligned source addr */
Lgpmemcpy_ft8:
/* We have aligned source and destination */
subs r2, r2, #8
blt Lgpmemcpy_fl12 /* less than 12 bytes (4 from above) */
subs r2, r2, #0x14
blt Lgpmemcpy_fl32 /* less than 32 bytes (12 from above) */
stmdb sp!, {r4} /* borrow r4 */
/* blat 32 bytes at a time */
/* XXX for really big copies perhaps we should use more registers */
Lgpmemcpy_floop32:
ldmia r1!, {r3, r4, r12, lr}
stmia r0!, {r3, r4, r12, lr}
ldmia r1!, {r3, r4, r12, lr}
stmia r0!, {r3, r4, r12, lr}
subs r2, r2, #0x20
bge Lgpmemcpy_floop32
cmn r2, #0x10
ldmgeia r1!, {r3, r4, r12, lr} /* blat a remaining 16 bytes */
stmgeia r0!, {r3, r4, r12, lr}
subge r2, r2, #0x10
ldmia sp!, {r4} /* return r4 */
Lgpmemcpy_fl32:
adds r2, r2, #0x14
/* blat 12 bytes at a time */
Lgpmemcpy_floop12:
ldmgeia r1!, {r3, r12, lr}
stmgeia r0!, {r3, r12, lr}
subges r2, r2, #0x0c
bge Lgpmemcpy_floop12
Lgpmemcpy_fl12:
adds r2, r2, #8
blt Lgpmemcpy_fl4
subs r2, r2, #4
ldrlt r3, [r1], #4
strlt r3, [r0], #4
ldmgeia r1!, {r3, r12}
stmgeia r0!, {r3, r12}
subge r2, r2, #4
Lgpmemcpy_fl4:
/* less than 4 bytes to go */
adds r2, r2, #4
ldmeqia sp!, {r0, pc} /* done */
/* copy the crud byte at a time */
cmp r2, #2
ldrb r3, [r1], #1
strb r3, [r0], #1
ldrgeb r3, [r1], #1
strgeb r3, [r0], #1
ldrgtb r3, [r1], #1
strgtb r3, [r0], #1
ldmia sp!, {r0, pc}
/* erg - unaligned destination */
Lgpmemcpy_fdestul:
rsb r12, r12, #4
cmp r12, #2
/* align destination with byte copies */
ldrb r3, [r1], #1
strb r3, [r0], #1
ldrgeb r3, [r1], #1
strgeb r3, [r0], #1
ldrgtb r3, [r1], #1
strgtb r3, [r0], #1
subs r2, r2, r12
blt Lgpmemcpy_fl4 /* less the 4 bytes */
ands r12, r1, #3
beq Lgpmemcpy_ft8 /* we have an aligned source */
/* erg - unaligned source */
/* This is where it gets nasty ... */
Lgpmemcpy_fsrcul:
bic r1, r1, #3
ldr lr, [r1], #4
cmp r12, #2
bgt Lgpmemcpy_fsrcul3
beq Lgpmemcpy_fsrcul2
cmp r2, #0x0c
blt Lgpmemcpy_fsrcul1loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5}
Lgpmemcpy_fsrcul1loop16:
mov r3, lr, lsr #8
ldmia r1!, {r4, r5, r12, lr}
orr r3, r3, r4, lsl #24
mov r4, r4, lsr #8
orr r4, r4, r5, lsl #24
mov r5, r5, lsr #8
orr r5, r5, r12, lsl #24
mov r12, r12, lsr #8
orr r12, r12, lr, lsl #24
stmia r0!, {r3-r5, r12}
subs r2, r2, #0x10
bge Lgpmemcpy_fsrcul1loop16
ldmia sp!, {r4, r5}
adds r2, r2, #0x0c
blt Lgpmemcpy_fsrcul1l4
Lgpmemcpy_fsrcul1loop4:
mov r12, lr, lsr #8
ldr lr, [r1], #4
orr r12, r12, lr, lsl #24
str r12, [r0], #4
subs r2, r2, #4
bge Lgpmemcpy_fsrcul1loop4
Lgpmemcpy_fsrcul1l4:
sub r1, r1, #3
b Lgpmemcpy_fl4
Lgpmemcpy_fsrcul2:
cmp r2, #0x0c
blt Lgpmemcpy_fsrcul2loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5}
Lgpmemcpy_fsrcul2loop16:
mov r3, lr, lsr #16
ldmia r1!, {r4, r5, r12, lr}
orr r3, r3, r4, lsl #16
mov r4, r4, lsr #16
orr r4, r4, r5, lsl #16
mov r5, r5, lsr #16
orr r5, r5, r12, lsl #16
mov r12, r12, lsr #16
orr r12, r12, lr, lsl #16
stmia r0!, {r3-r5, r12}
subs r2, r2, #0x10
bge Lgpmemcpy_fsrcul2loop16
ldmia sp!, {r4, r5}
adds r2, r2, #0x0c
blt Lgpmemcpy_fsrcul2l4
Lgpmemcpy_fsrcul2loop4:
mov r12, lr, lsr #16
ldr lr, [r1], #4
orr r12, r12, lr, lsl #16
str r12, [r0], #4
subs r2, r2, #4
bge Lgpmemcpy_fsrcul2loop4
Lgpmemcpy_fsrcul2l4:
sub r1, r1, #2
b Lgpmemcpy_fl4
Lgpmemcpy_fsrcul3:
cmp r2, #0x0c
blt Lgpmemcpy_fsrcul3loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5}
Lgpmemcpy_fsrcul3loop16:
mov r3, lr, lsr #24
ldmia r1!, {r4, r5, r12, lr}
orr r3, r3, r4, lsl #8
mov r4, r4, lsr #24
orr r4, r4, r5, lsl #8
mov r5, r5, lsr #24
orr r5, r5, r12, lsl #8
mov r12, r12, lsr #24
orr r12, r12, lr, lsl #8
stmia r0!, {r3-r5, r12}
subs r2, r2, #0x10
bge Lgpmemcpy_fsrcul3loop16
ldmia sp!, {r4, r5}
adds r2, r2, #0x0c
blt Lgpmemcpy_fsrcul3l4
Lgpmemcpy_fsrcul3loop4:
mov r12, lr, lsr #24
ldr lr, [r1], #4
orr r12, r12, lr, lsl #8
str r12, [r0], #4
subs r2, r2, #4
bge Lgpmemcpy_fsrcul3loop4
Lgpmemcpy_fsrcul3l4:
sub r1, r1, #1
b Lgpmemcpy_fl4
Lgpmemcpy_backwards:
add r1, r1, r2
add r0, r0, r2
subs r2, r2, #4
blt Lgpmemcpy_bl4 /* less than 4 bytes */
ands r12, r0, #3
bne Lgpmemcpy_bdestul /* oh unaligned destination addr */
ands r12, r1, #3
bne Lgpmemcpy_bsrcul /* oh unaligned source addr */
Lgpmemcpy_bt8:
/* We have aligned source and destination */
subs r2, r2, #8
blt Lgpmemcpy_bl12 /* less than 12 bytes (4 from above) */
stmdb sp!, {r4, lr}
subs r2, r2, #0x14 /* less than 32 bytes (12 from above) */
blt Lgpmemcpy_bl32
/* blat 32 bytes at a time */
/* XXX for really big copies perhaps we should use more registers */
Lgpmemcpy_bloop32:
ldmdb r1!, {r3, r4, r12, lr}
stmdb r0!, {r3, r4, r12, lr}
ldmdb r1!, {r3, r4, r12, lr}
stmdb r0!, {r3, r4, r12, lr}
subs r2, r2, #0x20
bge Lgpmemcpy_bloop32
Lgpmemcpy_bl32:
cmn r2, #0x10
ldmgedb r1!, {r3, r4, r12, lr} /* blat a remaining 16 bytes */
stmgedb r0!, {r3, r4, r12, lr}
subge r2, r2, #0x10
adds r2, r2, #0x14
ldmgedb r1!, {r3, r12, lr} /* blat a remaining 12 bytes */
stmgedb r0!, {r3, r12, lr}
subge r2, r2, #0x0c
ldmia sp!, {r4, lr}
Lgpmemcpy_bl12:
adds r2, r2, #8
blt Lgpmemcpy_bl4
subs r2, r2, #4
ldrlt r3, [r1, #-4]!
strlt r3, [r0, #-4]!
ldmgedb r1!, {r3, r12}
stmgedb r0!, {r3, r12}
subge r2, r2, #4
Lgpmemcpy_bl4:
/* less than 4 bytes to go */
adds r2, r2, #4
moveq pc, lr /* done */
/* copy the crud byte at a time */
cmp r2, #2
ldrb r3, [r1, #-1]!
strb r3, [r0, #-1]!
ldrgeb r3, [r1, #-1]!
strgeb r3, [r0, #-1]!
ldrgtb r3, [r1, #-1]!
strgtb r3, [r0, #-1]!
mov pc, lr
/* erg - unaligned destination */
Lgpmemcpy_bdestul:
cmp r12, #2
/* align destination with byte copies */
ldrb r3, [r1, #-1]!
strb r3, [r0, #-1]!
ldrgeb r3, [r1, #-1]!
strgeb r3, [r0, #-1]!
ldrgtb r3, [r1, #-1]!
strgtb r3, [r0, #-1]!
subs r2, r2, r12
blt Lgpmemcpy_bl4 /* less than 4 bytes to go */
ands r12, r1, #3
beq Lgpmemcpy_bt8 /* we have an aligned source */
/* erg - unaligned source */
/* This is where it gets nasty ... */
Lgpmemcpy_bsrcul:
bic r1, r1, #3
ldr r3, [r1, #0]
cmp r12, #2
blt Lgpmemcpy_bsrcul1
beq Lgpmemcpy_bsrcul2
cmp r2, #0x0c
blt Lgpmemcpy_bsrcul3loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5, lr}
Lgpmemcpy_bsrcul3loop16:
mov lr, r3, lsl #8
ldmdb r1!, {r3-r5, r12}
orr lr, lr, r12, lsr #24
mov r12, r12, lsl #8
orr r12, r12, r5, lsr #24
mov r5, r5, lsl #8
orr r5, r5, r4, lsr #24
mov r4, r4, lsl #8
orr r4, r4, r3, lsr #24
stmdb r0!, {r4, r5, r12, lr}
subs r2, r2, #0x10
bge Lgpmemcpy_bsrcul3loop16
ldmia sp!, {r4, r5, lr}
adds r2, r2, #0x0c
blt Lgpmemcpy_bsrcul3l4
Lgpmemcpy_bsrcul3loop4:
mov r12, r3, lsl #8
ldr r3, [r1, #-4]!
orr r12, r12, r3, lsr #24
str r12, [r0, #-4]!
subs r2, r2, #4
bge Lgpmemcpy_bsrcul3loop4
Lgpmemcpy_bsrcul3l4:
add r1, r1, #3
b Lgpmemcpy_bl4
Lgpmemcpy_bsrcul2:
cmp r2, #0x0c
blt Lgpmemcpy_bsrcul2loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5, lr}
Lgpmemcpy_bsrcul2loop16:
mov lr, r3, lsl #16
ldmdb r1!, {r3-r5, r12}
orr lr, lr, r12, lsr #16
mov r12, r12, lsl #16
orr r12, r12, r5, lsr #16
mov r5, r5, lsl #16
orr r5, r5, r4, lsr #16
mov r4, r4, lsl #16
orr r4, r4, r3, lsr #16
stmdb r0!, {r4, r5, r12, lr}
subs r2, r2, #0x10
bge Lgpmemcpy_bsrcul2loop16
ldmia sp!, {r4, r5, lr}
adds r2, r2, #0x0c
blt Lgpmemcpy_bsrcul2l4
Lgpmemcpy_bsrcul2loop4:
mov r12, r3, lsl #16
ldr r3, [r1, #-4]!
orr r12, r12, r3, lsr #16
str r12, [r0, #-4]!
subs r2, r2, #4
bge Lgpmemcpy_bsrcul2loop4
Lgpmemcpy_bsrcul2l4:
add r1, r1, #2
b Lgpmemcpy_bl4
Lgpmemcpy_bsrcul1:
cmp r2, #0x0c
blt Lgpmemcpy_bsrcul1loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5, lr}
Lgpmemcpy_bsrcul1loop32:
mov lr, r3, lsl #24
ldmdb r1!, {r3-r5, r12}
orr lr, lr, r12, lsr #8
mov r12, r12, lsl #24
orr r12, r12, r5, lsr #8
mov r5, r5, lsl #24
orr r5, r5, r4, lsr #8
mov r4, r4, lsl #24
orr r4, r4, r3, lsr #8
stmdb r0!, {r4, r5, r12, lr}
subs r2, r2, #0x10
bge Lgpmemcpy_bsrcul1loop32
ldmia sp!, {r4, r5, lr}
adds r2, r2, #0x0c
blt Lgpmemcpy_bsrcul1l4
Lgpmemcpy_bsrcul1loop4:
mov r12, r3, lsl #24
ldr r3, [r1, #-4]!
orr r12, r12, r3, lsr #8
str r12, [r0, #-4]!
subs r2, r2, #4
bge Lgpmemcpy_bsrcul1loop4
Lgpmemcpy_bsrcul1l4:
add r1, r1, #1
b Lgpmemcpy_bl4
|
Mdashdotdashn/LittleGPTracker | 1,883 | sources/Adapters/GP2X/System/gpmemset.s | /* Copyright (C) 1998 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Philip Blundell <philb@gnu.org>
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
/*#include <sys/syscall.h>*/
.text
.global gpmemset;
.type gpmemset,%function
.align 4; \
gpmemset:
mov a4, a1
cmp a3, $8 @ at least 8 bytes to do?
blt 2f
orr a2, a2, a2, lsl $8
orr a2, a2, a2, lsl $16
1:
tst a4, $3 @ aligned yet?
strneb a2, [a4], $1
subne a3, a3, $1
bne 1b
mov ip, a2
1:
cmp a3, $8 @ 8 bytes still to do?
blt 2f
stmia a4!, {a2, ip}
sub a3, a3, $8
cmp a3, $8 @ 8 bytes still to do?
blt 2f
stmia a4!, {a2, ip}
sub a3, a3, $8
cmp a3, $8 @ 8 bytes still to do?
blt 2f
stmia a4!, {a2, ip}
sub a3, a3, $8
cmp a3, $8 @ 8 bytes still to do?
stmgeia a4!, {a2, ip}
subge a3, a3, $8
bge 1b
2:
movs a3, a3 @ anything left?
moveq pc, lr @ nope
rsb a3, a3, $7
add pc, pc, a3, lsl $2
mov r0, r0
strb a2, [a4], $1
strb a2, [a4], $1
strb a2, [a4], $1
strb a2, [a4], $1
strb a2, [a4], $1
strb a2, [a4], $1
strb a2, [a4], $1
mov pc, lr
.size gpmemset,.-gpmemset;
|
Mdashdotdashn/LittleGPTracker | 12,207 | sources/Adapters/GP2X/System/gpmemcpy.s | /* $NetBSD: gpmemcpy.S,v 1.3 1997/11/22 03:27:12 mark Exp $ */
/*-
* Copyright (c) 1997 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Neil A. Carson and Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS\'\' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* This was modified by Jay Monkman <jmonkman@smoothsmoothie.com> to
* save and restore r12. This is necessary for RTEMS.
*/
/* #include <machine/asm.h>*/
#define ENTRY(_LABEL) \\
.global _LABEL; _LABEL:
.globl gpmemcpy
gpmemcpy:
stmfd sp!, {r0, r12, lr}
bl _gpmemcpy
ldmfd sp!, {r0, r12, pc}
.globl gpmemmove
gpmemmove:
stmfd sp!, {r0, r12, lr}
bl _gpmemcpy
ldmfd sp!, {r0, r12, pc}
/*
* This is one fun bit of code ...
* Some easy listening music is suggested while trying to understand this
* code e.g. Iron Maiden
*
* For anyone attempting to understand it :
*
* The core code is implemented here with simple stubs for gpmemcpy()
* gpmemmove() and bcopy().
*
* All local labels are prefixed with Lgpmemcpy_
* Following the prefix a label starting f is used in the forward copy code
* while a label using b is used in the backwards copy code
* The source and destination addresses determine whether a forward or
* backward copy is performed.
* Separate bits of code are used to deal with the following situations
* for both the forward and backwards copy.
* unaligned source address
* unaligned destination address
* Separate copy routines are used to produce an optimised result for each
* of these cases.
* The copy code will use LDM/STM instructions to copy up to 32 bytes at
* a time where possible.
*
* Note: r12 (aka ip) can be trashed during the function along with
* r0-r3 although r0-r2 have defined uses i.e. src, dest, len through out.
* Additional registers are preserved prior to use i.e. r4, r5 & lr
*
* Apologies for the state of the comments;-)
*/
/*
_gpmemcpy:
*/
.globl _gpmemcpy
_gpmemcpy:
/* Determine copy direction */
cmp r1, r0
bcc Lgpmemcpy_backwards
moveq r0, #0 /* Quick abort for len=0 */
moveq pc, lr
stmdb sp!, {r0, lr} /* gpmemcpy() returns dest addr */
subs r2, r2, #4
blt Lgpmemcpy_fl4 /* less than 4 bytes */
ands r12, r0, #3
bne Lgpmemcpy_fdestul /* oh unaligned destination addr */
ands r12, r1, #3
bne Lgpmemcpy_fsrcul /* oh unaligned source addr */
Lgpmemcpy_ft8:
/* We have aligned source and destination */
subs r2, r2, #8
blt Lgpmemcpy_fl12 /* less than 12 bytes (4 from above) */
subs r2, r2, #0x14
blt Lgpmemcpy_fl32 /* less than 32 bytes (12 from above) */
stmdb sp!, {r4} /* borrow r4 */
/* blat 32 bytes at a time */
/* XXX for really big copies perhaps we should use more registers */
Lgpmemcpy_floop32:
ldmia r1!, {r3, r4, r12, lr}
stmia r0!, {r3, r4, r12, lr}
ldmia r1!, {r3, r4, r12, lr}
stmia r0!, {r3, r4, r12, lr}
subs r2, r2, #0x20
bge Lgpmemcpy_floop32
cmn r2, #0x10
ldmgeia r1!, {r3, r4, r12, lr} /* blat a remaining 16 bytes */
stmgeia r0!, {r3, r4, r12, lr}
subge r2, r2, #0x10
ldmia sp!, {r4} /* return r4 */
Lgpmemcpy_fl32:
adds r2, r2, #0x14
/* blat 12 bytes at a time */
Lgpmemcpy_floop12:
ldmgeia r1!, {r3, r12, lr}
stmgeia r0!, {r3, r12, lr}
subges r2, r2, #0x0c
bge Lgpmemcpy_floop12
Lgpmemcpy_fl12:
adds r2, r2, #8
blt Lgpmemcpy_fl4
subs r2, r2, #4
ldrlt r3, [r1], #4
strlt r3, [r0], #4
ldmgeia r1!, {r3, r12}
stmgeia r0!, {r3, r12}
subge r2, r2, #4
Lgpmemcpy_fl4:
/* less than 4 bytes to go */
adds r2, r2, #4
ldmeqia sp!, {r0, pc} /* done */
/* copy the crud byte at a time */
cmp r2, #2
ldrb r3, [r1], #1
strb r3, [r0], #1
ldrgeb r3, [r1], #1
strgeb r3, [r0], #1
ldrgtb r3, [r1], #1
strgtb r3, [r0], #1
ldmia sp!, {r0, pc}
/* erg - unaligned destination */
Lgpmemcpy_fdestul:
rsb r12, r12, #4
cmp r12, #2
/* align destination with byte copies */
ldrb r3, [r1], #1
strb r3, [r0], #1
ldrgeb r3, [r1], #1
strgeb r3, [r0], #1
ldrgtb r3, [r1], #1
strgtb r3, [r0], #1
subs r2, r2, r12
blt Lgpmemcpy_fl4 /* less the 4 bytes */
ands r12, r1, #3
beq Lgpmemcpy_ft8 /* we have an aligned source */
/* erg - unaligned source */
/* This is where it gets nasty ... */
Lgpmemcpy_fsrcul:
bic r1, r1, #3
ldr lr, [r1], #4
cmp r12, #2
bgt Lgpmemcpy_fsrcul3
beq Lgpmemcpy_fsrcul2
cmp r2, #0x0c
blt Lgpmemcpy_fsrcul1loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5}
Lgpmemcpy_fsrcul1loop16:
mov r3, lr, lsr #8
ldmia r1!, {r4, r5, r12, lr}
orr r3, r3, r4, lsl #24
mov r4, r4, lsr #8
orr r4, r4, r5, lsl #24
mov r5, r5, lsr #8
orr r5, r5, r12, lsl #24
mov r12, r12, lsr #8
orr r12, r12, lr, lsl #24
stmia r0!, {r3-r5, r12}
subs r2, r2, #0x10
bge Lgpmemcpy_fsrcul1loop16
ldmia sp!, {r4, r5}
adds r2, r2, #0x0c
blt Lgpmemcpy_fsrcul1l4
Lgpmemcpy_fsrcul1loop4:
mov r12, lr, lsr #8
ldr lr, [r1], #4
orr r12, r12, lr, lsl #24
str r12, [r0], #4
subs r2, r2, #4
bge Lgpmemcpy_fsrcul1loop4
Lgpmemcpy_fsrcul1l4:
sub r1, r1, #3
b Lgpmemcpy_fl4
Lgpmemcpy_fsrcul2:
cmp r2, #0x0c
blt Lgpmemcpy_fsrcul2loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5}
Lgpmemcpy_fsrcul2loop16:
mov r3, lr, lsr #16
ldmia r1!, {r4, r5, r12, lr}
orr r3, r3, r4, lsl #16
mov r4, r4, lsr #16
orr r4, r4, r5, lsl #16
mov r5, r5, lsr #16
orr r5, r5, r12, lsl #16
mov r12, r12, lsr #16
orr r12, r12, lr, lsl #16
stmia r0!, {r3-r5, r12}
subs r2, r2, #0x10
bge Lgpmemcpy_fsrcul2loop16
ldmia sp!, {r4, r5}
adds r2, r2, #0x0c
blt Lgpmemcpy_fsrcul2l4
Lgpmemcpy_fsrcul2loop4:
mov r12, lr, lsr #16
ldr lr, [r1], #4
orr r12, r12, lr, lsl #16
str r12, [r0], #4
subs r2, r2, #4
bge Lgpmemcpy_fsrcul2loop4
Lgpmemcpy_fsrcul2l4:
sub r1, r1, #2
b Lgpmemcpy_fl4
Lgpmemcpy_fsrcul3:
cmp r2, #0x0c
blt Lgpmemcpy_fsrcul3loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5}
Lgpmemcpy_fsrcul3loop16:
mov r3, lr, lsr #24
ldmia r1!, {r4, r5, r12, lr}
orr r3, r3, r4, lsl #8
mov r4, r4, lsr #24
orr r4, r4, r5, lsl #8
mov r5, r5, lsr #24
orr r5, r5, r12, lsl #8
mov r12, r12, lsr #24
orr r12, r12, lr, lsl #8
stmia r0!, {r3-r5, r12}
subs r2, r2, #0x10
bge Lgpmemcpy_fsrcul3loop16
ldmia sp!, {r4, r5}
adds r2, r2, #0x0c
blt Lgpmemcpy_fsrcul3l4
Lgpmemcpy_fsrcul3loop4:
mov r12, lr, lsr #24
ldr lr, [r1], #4
orr r12, r12, lr, lsl #8
str r12, [r0], #4
subs r2, r2, #4
bge Lgpmemcpy_fsrcul3loop4
Lgpmemcpy_fsrcul3l4:
sub r1, r1, #1
b Lgpmemcpy_fl4
Lgpmemcpy_backwards:
add r1, r1, r2
add r0, r0, r2
subs r2, r2, #4
blt Lgpmemcpy_bl4 /* less than 4 bytes */
ands r12, r0, #3
bne Lgpmemcpy_bdestul /* oh unaligned destination addr */
ands r12, r1, #3
bne Lgpmemcpy_bsrcul /* oh unaligned source addr */
Lgpmemcpy_bt8:
/* We have aligned source and destination */
subs r2, r2, #8
blt Lgpmemcpy_bl12 /* less than 12 bytes (4 from above) */
stmdb sp!, {r4, lr}
subs r2, r2, #0x14 /* less than 32 bytes (12 from above) */
blt Lgpmemcpy_bl32
/* blat 32 bytes at a time */
/* XXX for really big copies perhaps we should use more registers */
Lgpmemcpy_bloop32:
ldmdb r1!, {r3, r4, r12, lr}
stmdb r0!, {r3, r4, r12, lr}
ldmdb r1!, {r3, r4, r12, lr}
stmdb r0!, {r3, r4, r12, lr}
subs r2, r2, #0x20
bge Lgpmemcpy_bloop32
Lgpmemcpy_bl32:
cmn r2, #0x10
ldmgedb r1!, {r3, r4, r12, lr} /* blat a remaining 16 bytes */
stmgedb r0!, {r3, r4, r12, lr}
subge r2, r2, #0x10
adds r2, r2, #0x14
ldmgedb r1!, {r3, r12, lr} /* blat a remaining 12 bytes */
stmgedb r0!, {r3, r12, lr}
subge r2, r2, #0x0c
ldmia sp!, {r4, lr}
Lgpmemcpy_bl12:
adds r2, r2, #8
blt Lgpmemcpy_bl4
subs r2, r2, #4
ldrlt r3, [r1, #-4]!
strlt r3, [r0, #-4]!
ldmgedb r1!, {r3, r12}
stmgedb r0!, {r3, r12}
subge r2, r2, #4
Lgpmemcpy_bl4:
/* less than 4 bytes to go */
adds r2, r2, #4
moveq pc, lr /* done */
/* copy the crud byte at a time */
cmp r2, #2
ldrb r3, [r1, #-1]!
strb r3, [r0, #-1]!
ldrgeb r3, [r1, #-1]!
strgeb r3, [r0, #-1]!
ldrgtb r3, [r1, #-1]!
strgtb r3, [r0, #-1]!
mov pc, lr
/* erg - unaligned destination */
Lgpmemcpy_bdestul:
cmp r12, #2
/* align destination with byte copies */
ldrb r3, [r1, #-1]!
strb r3, [r0, #-1]!
ldrgeb r3, [r1, #-1]!
strgeb r3, [r0, #-1]!
ldrgtb r3, [r1, #-1]!
strgtb r3, [r0, #-1]!
subs r2, r2, r12
blt Lgpmemcpy_bl4 /* less than 4 bytes to go */
ands r12, r1, #3
beq Lgpmemcpy_bt8 /* we have an aligned source */
/* erg - unaligned source */
/* This is where it gets nasty ... */
Lgpmemcpy_bsrcul:
bic r1, r1, #3
ldr r3, [r1, #0]
cmp r12, #2
blt Lgpmemcpy_bsrcul1
beq Lgpmemcpy_bsrcul2
cmp r2, #0x0c
blt Lgpmemcpy_bsrcul3loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5, lr}
Lgpmemcpy_bsrcul3loop16:
mov lr, r3, lsl #8
ldmdb r1!, {r3-r5, r12}
orr lr, lr, r12, lsr #24
mov r12, r12, lsl #8
orr r12, r12, r5, lsr #24
mov r5, r5, lsl #8
orr r5, r5, r4, lsr #24
mov r4, r4, lsl #8
orr r4, r4, r3, lsr #24
stmdb r0!, {r4, r5, r12, lr}
subs r2, r2, #0x10
bge Lgpmemcpy_bsrcul3loop16
ldmia sp!, {r4, r5, lr}
adds r2, r2, #0x0c
blt Lgpmemcpy_bsrcul3l4
Lgpmemcpy_bsrcul3loop4:
mov r12, r3, lsl #8
ldr r3, [r1, #-4]!
orr r12, r12, r3, lsr #24
str r12, [r0, #-4]!
subs r2, r2, #4
bge Lgpmemcpy_bsrcul3loop4
Lgpmemcpy_bsrcul3l4:
add r1, r1, #3
b Lgpmemcpy_bl4
Lgpmemcpy_bsrcul2:
cmp r2, #0x0c
blt Lgpmemcpy_bsrcul2loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5, lr}
Lgpmemcpy_bsrcul2loop16:
mov lr, r3, lsl #16
ldmdb r1!, {r3-r5, r12}
orr lr, lr, r12, lsr #16
mov r12, r12, lsl #16
orr r12, r12, r5, lsr #16
mov r5, r5, lsl #16
orr r5, r5, r4, lsr #16
mov r4, r4, lsl #16
orr r4, r4, r3, lsr #16
stmdb r0!, {r4, r5, r12, lr}
subs r2, r2, #0x10
bge Lgpmemcpy_bsrcul2loop16
ldmia sp!, {r4, r5, lr}
adds r2, r2, #0x0c
blt Lgpmemcpy_bsrcul2l4
Lgpmemcpy_bsrcul2loop4:
mov r12, r3, lsl #16
ldr r3, [r1, #-4]!
orr r12, r12, r3, lsr #16
str r12, [r0, #-4]!
subs r2, r2, #4
bge Lgpmemcpy_bsrcul2loop4
Lgpmemcpy_bsrcul2l4:
add r1, r1, #2
b Lgpmemcpy_bl4
Lgpmemcpy_bsrcul1:
cmp r2, #0x0c
blt Lgpmemcpy_bsrcul1loop4
sub r2, r2, #0x0c
stmdb sp!, {r4, r5, lr}
Lgpmemcpy_bsrcul1loop32:
mov lr, r3, lsl #24
ldmdb r1!, {r3-r5, r12}
orr lr, lr, r12, lsr #8
mov r12, r12, lsl #24
orr r12, r12, r5, lsr #8
mov r5, r5, lsl #24
orr r5, r5, r4, lsr #8
mov r4, r4, lsl #24
orr r4, r4, r3, lsr #8
stmdb r0!, {r4, r5, r12, lr}
subs r2, r2, #0x10
bge Lgpmemcpy_bsrcul1loop32
ldmia sp!, {r4, r5, lr}
adds r2, r2, #0x0c
blt Lgpmemcpy_bsrcul1l4
Lgpmemcpy_bsrcul1loop4:
mov r12, r3, lsl #24
ldr r3, [r1, #-4]!
orr r12, r12, r3, lsr #8
str r12, [r0, #-4]!
subs r2, r2, #4
bge Lgpmemcpy_bsrcul1loop4
Lgpmemcpy_bsrcul1l4:
add r1, r1, #1
b Lgpmemcpy_bl4
|
MediaTek-Labs/linkit-smart-7688-uboot | 19,812 | stage1/start.S | /*
* Startup Code for MIPS32 CPU-core
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <rt_mmap.h>
#define RT2880_LED_1 0x2
#define RT2880_LED_2 0x4
#define RT2880_LED_3 0x8
#define RT2880_LED_4 0x10
#define RT2880_LED_5 0x20
#define RT2880_LED_6 0x40
#define RT2880_LED_7 0x80
#define SDRAM_CFG0_REG RALINK_SYSCTL_BASE + 0x0300
#define SDRAM_CFG1_REG RALINK_SYSCTL_BASE + 0x0304
#define SDRAM_CFG0_ALWAYS_ONE ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_START ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_DONE ( 1 << 30)
#define RVECENT(f,n) \
b f; nop
#define XVECENT(f,bev) \
b f ; \
li k0,bev
#if 0 //DISCARD exception_vect
.section except_vect
except_vector:
RVECENT(reset,0) /* U-boot entry point */
RVECENT(reset,1) /* software reboot */
#if defined(CONFIG_INCA_IP)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word 0x00000000 /* phase of the flash */
#elif defined(CONFIG_PURPLE)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
#else
RVECENT(romReserved,2)
#endif
RVECENT(romReserved,3)
RVECENT(romReserved,4)
RVECENT(romReserved,5)
RVECENT(romReserved,6)
RVECENT(romReserved,7)
RVECENT(romReserved,8)
RVECENT(romReserved,9)
RVECENT(romReserved,10)
RVECENT(romReserved,11)
RVECENT(romReserved,12)
RVECENT(romReserved,13)
RVECENT(romReserved,14)
RVECENT(romReserved,15)
RVECENT(romReserved,16)
RVECENT(romReserved,17)
RVECENT(romReserved,18)
RVECENT(romReserved,19)
RVECENT(romReserved,20)
RVECENT(romReserved,21)
RVECENT(romReserved,22)
RVECENT(romReserved,23)
RVECENT(romReserved,24)
RVECENT(romReserved,25)
RVECENT(romReserved,26)
RVECENT(romReserved,27)
RVECENT(romReserved,28)
RVECENT(romReserved,29)
RVECENT(romReserved,30)
RVECENT(romReserved,31)
RVECENT(romReserved,32)
RVECENT(romReserved,33)
RVECENT(romReserved,34)
RVECENT(romReserved,35)
RVECENT(romReserved,36)
RVECENT(romReserved,37)
RVECENT(romReserved,38)
RVECENT(romReserved,39)
RVECENT(romReserved,40)
RVECENT(romReserved,41)
RVECENT(romReserved,42)
RVECENT(romReserved,43)
RVECENT(romReserved,44)
RVECENT(romReserved,45)
RVECENT(romReserved,46)
RVECENT(romReserved,47)
RVECENT(romReserved,48)
RVECENT(romReserved,49)
RVECENT(romReserved,50)
RVECENT(romReserved,51)
RVECENT(romReserved,52)
RVECENT(romReserved,53)
RVECENT(romReserved,54)
RVECENT(romReserved,55)
RVECENT(romReserved,56)
RVECENT(romReserved,57)
RVECENT(romReserved,58)
RVECENT(romReserved,59)
RVECENT(romReserved,60)
RVECENT(romReserved,61)
RVECENT(romReserved,62)
RVECENT(romReserved,63)
XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
RVECENT(romReserved,65)
RVECENT(romReserved,66)
RVECENT(romReserved,67)
RVECENT(romReserved,68)
RVECENT(romReserved,69)
RVECENT(romReserved,70)
RVECENT(romReserved,71)
RVECENT(romReserved,72)
RVECENT(romReserved,73)
RVECENT(romReserved,74)
RVECENT(romReserved,75)
RVECENT(romReserved,76)
RVECENT(romReserved,77)
RVECENT(romReserved,78)
RVECENT(romReserved,79)
XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
RVECENT(romReserved,81)
RVECENT(romReserved,82)
RVECENT(romReserved,83)
RVECENT(romReserved,84)
RVECENT(romReserved,85)
RVECENT(romReserved,86)
RVECENT(romReserved,87)
RVECENT(romReserved,88)
RVECENT(romReserved,89)
RVECENT(romReserved,90)
RVECENT(romReserved,91)
RVECENT(romReserved,92)
RVECENT(romReserved,93)
RVECENT(romReserved,94)
RVECENT(romReserved,95)
XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
RVECENT(romReserved,97)
RVECENT(romReserved,98)
RVECENT(romReserved,99)
RVECENT(romReserved,100)
RVECENT(romReserved,101)
RVECENT(romReserved,102)
RVECENT(romReserved,103)
RVECENT(romReserved,104)
RVECENT(romReserved,105)
RVECENT(romReserved,106)
RVECENT(romReserved,107)
RVECENT(romReserved,108)
RVECENT(romReserved,109)
RVECENT(romReserved,110)
RVECENT(romReserved,111)
XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
RVECENT(romReserved,113)
RVECENT(romReserved,114)
RVECENT(romReserved,115)
RVECENT(romReserved,116)
RVECENT(romReserved,116)
RVECENT(romReserved,118)
RVECENT(romReserved,119)
RVECENT(romReserved,120)
RVECENT(romReserved,121)
RVECENT(romReserved,122)
RVECENT(romReserved,123)
RVECENT(romReserved,124)
RVECENT(romReserved,125)
RVECENT(romReserved,126)
RVECENT(romReserved,127)
/* We hope there are no more reserved vectors!
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
#ifdef CONFIG_PURPLE
/* 0xbfc00400 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
/* 0xbfc00428 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
#endif /* CONFIG_PURPLE */
.align 4
#endif //DISCARD exception sector
.set noreorder
.globl _start
.section .text
_start:
reset:
#if defined (RT2883_FPGA_BOARD) || defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || defined (RT2883_ASIC_BOARD)
# Initialize the register file
# should not be required with good software practices
or $1,$0, $0
or $2,$0, $0
or $3,$0, $0
or $4,$0, $0
or $5,$0, $0
or $6,$0, $0
or $7,$0, $0
or $8,$0, $0
or $9,$0, $0
or $10,$0, $0
or $11,$0, $0
or $12,$0, $0
or $13,$0, $0
or $14,$0, $0
or $15,$0, $0
or $16,$0, $0
or $17,$0, $0
or $18,$0, $0
or $19,$0, $0
or $20,$0, $0
or $21,$0, $0
or $22,$0, $0
or $23,$0, $0
or $24,$0, $0
or $25,$0, $0
or $26,$0, $0
or $27,$0, $0
or $28,$0, $0
or $29,$0, $0
or $30,$0, $0
or $31,$0, $0
# Initialize Misc. Cop0 state
# Read status register
mfc0 $10, $12
# Set up Status register:
# Disable Coprocessor Usable bits
# Turn off Reduce Power bit
# Turn off reverse endian
# Turn off BEV (use normal exception vectors)
# Clear TS, SR, NMI bits
# Clear Interrupt masks
# Clear User Mode
# Clear ERL
# Set EXL
# Clear Interrupt Enable
# modify by Bruce
#li $11, 0x0000ff02
li $11, 0x00000004
mtc0 $11, $12
# Disable watch exceptions
mtc0 $0, $18
# Clear Watch Status bits
li $11, 0x3
mtc0 $11, $19
# Clear WP bit to avoid watch exception upon user code entry
# Clear IV bit - Interrupts go to general exception vector
# Clear software interrupts
mtc0 $0, $13
#if 0 // YT
# Set KSeg0 to cacheable
# Config.K0
mfc0 $10, $16
li $11, 0x7
not $11
and $10, $11
or $10, 0x3
mtc0 $10, $16
#endif //
# Clear Count register
mtc0 $0, $9
# Set compare to -1 to delay 1st count=compare
# Also, clears timer interrupt
li $10, -1
mtc0 $10, $11
#if 0 //disable cache
# Cache initialization routine
# Long and needed on HW
# Can be skipped if using magic simulation cache flush
# Determine how big the I$ is
/*
************************************************************************
* C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| MMU Size | IS | IL | IA | DS | DL | DA |Rsvd |W|C|E|F| Config1
* | | | | | | | | | |R|A|P|P|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
mfc0 $10, $16, 1 # .word 0x400a8001
# Isolate I$ Line Size
sll $11, $10, 10
srl $11, 29
# Skip ahead if No I$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true I$ line size in bytes
sll $12, $10, 7
srl $12, 29
li $14, 64
sllv $12, $14, $12 # I$ Sets per way
sll $13, $10, 13
srl $13, 29 # I$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28
mtc0 $0, $29
move $15, $12
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x8, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
# Now go through and invalidate the D$
# Now that the I$ has been flushed, the rest of the code can be
# moved to kseg0 and run from the cache to go faster
10:
# Isolate D$ Line Size
sll $11, $10, 19
srl $11, 29
# Skip ahead if No D$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true D$ line size in bytes
sll $12, $10, 16
srl $12, 29
li $14, 64
sllv $12, $14, $12 # D$ Sets per way
sll $13, $10, 22
srl $13, 29 # D$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28
mtc0 $0, $29
mtc0 $0, $28, 2
mtc0 $0, $29, 2
move $15, $12
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x9, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
#
# Now go through and initialize the L2$
10:
# Check L2 cache size
/*
************************************************************************
* C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| TU | TS | TL | TA | SU | SS | SL | SA | Config2
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
mfc0 $10, $16, 2
# Isolate L2$ Line Size
sll $11, $10, 24
srl $11, 28
# Skip ahead if No L2$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true L2$ line size in bytes
# Isolate L2$ Sets per Way
sll $12, $10, 20
srl $12, 28
li $14, 64
sllv $12, $14, $12 # D$ Sets per way
# Isolate L2$ Associativity
sll $13, $10, 28
srl $13, 28 # D$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear L23TagLo/L23TagHi registers
mtc0 $0, $28, 4
mtc0 $0, $29, 4
move $15, $12
# L2$ Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0xB, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
10:
# Determine if we have a TLB
mfc0 $11, $16
sll $11, 22
srl $11, 29
li $15, 0x1 # MT = 1 => TLB
bne $11, $15, 15f
nop
mfc0 $10, $16, 1 # .word 0x400a8001
sll $11, $10, 1
srl $11, 26 # Number of TLB entries (-1)
mtc0 $0, $2 # EntryLo0
mtc0 $0, $3 # EntryLo1
mtc0 $0, $5 # PageMask
mtc0 $0, $6 # Wired
li $12, 0x80000000
1:
mtc0 $11, $0 # Index register
mtc0 $12, $10 # EntryHi
ssnop #.word 0x00000040
ssnop #.word 0x00000040
TLBWI
add $12, (2<<13) # Add 8K to the address to avoid TLB conflict with previous entry
bne $11, $0, 1b
add $11, -1
#endif //disable cache
15:
#endif
/* delay cycle */
li t0,0xFFFF
li t1,0x1
1:
sub t0, t0, t1
bnez t0, 1b
/* end of delay cycle */
li t5,SDRAM_CFG0_REG
lw t6,0(t5)
nop
and t6,0xF0000000
#if defined (RT2880_FPGA_BOARD) || defined (RT2883_FPGA_BOARD) || defined (RT3052_FPGA_BOARD)
#ifdef RT2880_FPGA_BOARD
#ifdef RT2880_MP
nop
or t6,0x01825282
//or t6,0x01815282
nop
#else /* RT2880_SHUTTLE */
or t6,0x91825282
//or t6,0x91815282
#endif
#else //2883, 3052 fpga
nop
or t6,0xD1825282
//or t6,0x01815282
nop
#endif
#else //RT2880_ASIC_BOARD, RT2883_ASIC_BOARD, RT3052_ASIC_BOARD
or t6,0xD1825272
#endif
nop
sw t6,0(t5)
nop
// justic whether SDRAM active
li t5,SDRAM_CFG1_REG
lw t6,0(t5)
nop
and t6, t6, SDRAM_CFG1_SDRAM_INIT_DONE
bnez t6, SDRAM_INIT_DONE
nop
nop
#if defined (RT2880_ASIC_BOARD) || defined (RT2883_ASIC_BOARD) || defined (RT3052_ASIC_BOARD)
#ifdef ON_BOARD_64M_DRAM_COMPONENT
//64Mbits sdram component
li t6,0xa1010600
#elif ON_BOARD_128M_DRAM_COMPONENT
//128Mbits sdram component
li t6,0xa1110600
#elif ON_BOARD_256M_DRAM_COMPONENT
//256Mbits sdram component
li t6,0xa1120600
#else
DRAM Component not defined
#endif
#ifdef ON_BOARD_32BIT_DRAM_BUS
and t6,0xFEFFFFFF
or t6,(1<<24)
#elif ON_BOARD_16BIT_DRAM_BUS
and t6,0xFEFFFFFF
#else
DRAM bus not defined
#endif
#else
#ifdef ON_BOARD_64M_DRAM_COMPONENT
//64Mbits sdram component
li t6,0x81010096
#elif ON_BOARD_128M_DRAM_COMPONENT
//128Mbits sdram component
li t6,0x81110096
#elif ON_BOARD_256M_DRAM_COMPONENT
//256Mbits sdram component
li t6,0x81120096
#else
DRAM Component not defined
#endif
#ifdef ON_BOARD_32BIT_DRAM_BUS
and t6,0xFEFFFFFF
or t6,(1<<24)
#elif ON_BOARD_16BIT_DRAM_BUS
and t6,0xFEFFFFFF
#else
DRAM bus not defined
#endif
#endif
nop
sw t6,0(t5)
nop
WAIT_SDRAM_INIT_DOWN:
lw t6,0(t5)
nop
and t6, t6, SDRAM_CFG1_SDRAM_INIT_DONE
beqz t6, WAIT_SDRAM_INIT_DOWN
nop
SDRAM_INIT_DONE:
li t5,RALINK_SYSCTL_BASE + 0x0060
li t6,0x3
#if defined(RT3052_ASIC_BOARD)
#if defined(P5_MAC_TO_PHY_MODE)
//set mdio pin to normal mode
and t6,~0x80
#else
//set mdio pin to gpio mode
or t6,0x80
#endif
//configure UARTF pin to gpio mode (GPIO7~GPIO14)
#if defined(UARTF_AT_GPIO_FUNC)
or t6,0x1c
#endif
#endif
#ifdef MAC_TO_VITESSE_MODE
and t6,~(1<<2)
#endif
#ifdef PCI_AT_GPIO_FUNC
or t6,1<<7
#endif
nop
sw t6,0(t5)
nop
#ifdef PCI_AT_GPIO_FUNC
li t5, 0xa0300674
li t6, 0xffffffff
nop
sw t6,0(t5)
nop
li t5, 0xa0300670
li t6, 0xffffffff
nop
sw t6,0(t5)
nop
#endif
//set all GPIO to output high
li t5, RALINK_PIO_BASE + 0x24
li t6, 0xffffbfff
nop
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x2C
li t6, 0xffffffff
nop
sw t6, 0(t5)
nop
#if defined(RT2880_ASIC_BOARD)
//turn on power LED (GPIO 12)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<12
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<12
nop
sw t6, 0(t5)
nop
#elif defined(RT3052_ASIC_BOARD)
//turn on power LED (GPIO 9)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<9
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<9
nop
sw t6, 0(t5)
nop
#endif
#if defined(RT2880_ASIC_BOARD) || defined(RT2880_FPGA_BOARD)
// Need to remap the vector memory to 0x0 if no memory there
li t0, RALINK_SYSCTL_BASE + 0x0010
li t1, 0x00C10084 //prefetch off
sw t1, 0(t0)
#endif
#if defined(RT3052_ASIC_BOARD) || defined(RT3052_FPGA_BOARD)|| defined(RT3050_FPGA_BOARD)|| defined(RT3050_ASIC_BOARD)
li t0,RALINK_SYSCTL_BASE + 0x10
lw t1,0(t0)
nop
and t1,t1,(1 << 18)
bne t1,zero,SYTEM_CLOCK_SET_384MHZ
nop
// Initialize Icache size to 16K
mfc0 t0, CP0_CONFIG
or t0,(1<<19)
mtc0 t0, CP0_CONFIG
nop
mfc0 t0, CP0_CONFIG,1
move t1 ,t0
and t0,~(0x7 << 22)
or t0,(1 <<22)
mtc0 t0, CP0_CONFIG,1
nop
mfc0 t0, CP0_CONFIG
and t0,~(1<<19)
mtc0 t0, CP0_CONFIG
nop
nop
SYTEM_CLOCK_SET_384MHZ:
#endif
#if defined(RT2880_FPGA_BOARD) || defined(RT2880_ASIC_BOARD)
/* CONFIG0 register */
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
#if 1
/* Initialize caches...
*/
bal mips_cache_reset
nop
/* ... and enable them.
#define CONF_CM_CACHABLE_NO_WA 0
#define CONF_CM_CACHABLE_WA 1
#define CONF_CM_UNCACHED 2
#define CONF_CM_CACHABLE_NONCOHERENT 3
#define CONF_CM_CACHABLE_CE 4
*/
li t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG
#endif
#endif
/* Set up temporary stack.
*/
li a0, CFG_INIT_SP_OFFSET
//bal mips_cache_lock
nop
// li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
// la sp, 0(t0)
/* Initialize GOT pointer.
*/
#if 0
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_ - 1f + 4
1:
move gp, ra
lw t1, 0(ra)
add gp, t1
#else
/* winfred: a easier way to get gp value so that mipsel-linux-as can
* assemble correctly without -mips_allow_branch_to_undefined flag
*/
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_
1:
lw gp, 0(ra)
#endif
// relocate got entries
move t4, gp // <---- t4: current GP
la t3, _GLOBAL_OFFSET_TABLE_ // <---- t3: original GP
subu t1, t4, t3 // <---- t1: offset to relocate
beqz t1, toload_stage2 // <---- (t1 == 0) ?(no_relocate): (do_relocate)
nop
bal num_got
nop
.word num_got_entries
num_got:
lw t0, 0(ra) //number_got_entries
addi t4, 8 //skip first 2 enties
addiu t0, -2
blez t0, toload_stage2
nop
2: lw t2, 0(t4)
beqz t2, 3f
add t2, t1
sw t2, 0(t4)
3: addiu t0, -1
bgtz t0, 2b
addi t4, 4
toload_stage2:
.extern _fstack //this reference to stag2's stack.
la sp, TEXT_BASE - 8
.extern load_stage2
la t9, load_stage2
jal t9
nop
#if 0
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* a0 = addr_sp
* a1 = gd
* a2 = destination address
*/
.globl relocate_code
.ent relocate_code
relocate_code:
move sp, a0 /* Set new stack pointer */
li t0, CFG_MONITOR_BASE
la t3, in_ram
lw t2, -12(t3) /* t2 <-- uboot_end_data */
move t1, a2
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
*/
move t6, gp
sub gp, CFG_MONITOR_BASE
add gp, a2 /* gp now adjusted */
sub t6, gp, t6 /* t6 <-- relocation offset */
/*
* t0 = source address
* t1 = target address
* t2 = source end address
*/
/* On the purple board we copy the code earlier in a special way
* in order to solve flash problems
*/
#ifndef CONFIG_PURPLE
1:
lw t3, 0(t0)
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
addu t1, 4 /* delay slot */
#endif
/* If caches were enabled, we would have to flush them here.
*/
/* Jump to where we've relocated ourselves.
*/
addi t0, a2, in_ram - _start
j t0
nop
.word uboot_end_data
.word uboot_end
.word num_got_entries
in_ram:
/* Now we want to update GOT.
*/
lw t3, -4(t0) /* t3 <-- num_got_entries */
addi t4, gp, 8 /* Skipping first two entries. */
li t2, 2
1:
lw t1, 0(t4)
beqz t1, 2f
add t1, t6
sw t1, 0(t4)
2:
addi t2, 1
blt t2, t3, 1b
addi t4, 4 /* delay slot */
/* Clear BSS.
*/
lw t1, -12(t0) /* t1 <-- uboot_end_data */
lw t2, -8(t0) /* t2 <-- uboot_end */
add t1, t6 /* adjust pointers */
add t2, t6
sub t1, 4
1: addi t1, 4
bltl t1, t2, 1b
sw zero, 0(t1) /* delay slot */
move a0, a1
la t9, board_init_r
j t9
move a1, a2 /* delay slot */
.end relocate_code
/* Exception handlers.
*/
#endif //COFNIG_STAGE1
romReserved:
b romReserved
romExcHandle:
b romExcHandle
|
MediaTek-Labs/linkit-smart-7688-uboot | 71,829 | cpu/ralink_soc/start.S | /*
* Startup Code for MIPS32 CPU-core
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include "../../autoconf.h"
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <rt_mmap.h>
#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD)
#define SDRAM_CFG0_REG RALINK_MEMCTRL_BASE+ 0x0
#define SDRAM_CFG1_REG RALINK_MEMCTRL_BASE+ 0x4
#else
#define SDRAM_CFG0_REG RALINK_SYSCTL_BASE + 0x0300
#define SDRAM_CFG1_REG RALINK_SYSCTL_BASE + 0x0304
#define RALINK_DDR_CFG0 (RALINK_MEMCTRL_BASE+0x40)
#define RALINK_DDR_CFG1 (RALINK_MEMCTRL_BASE+0x44)
#define RALINK_DDR_CFG2 (RALINK_MEMCTRL_BASE+0x48)
#define RALINK_DDR_CFG3 (RALINK_MEMCTRL_BASE+0x4c)
#define RALINK_DDR_CFG4 (RALINK_MEMCTRL_BASE+0x50)
#define RALINK_DDR_CFG8 (RALINK_MEMCTRL_BASE+0x60)
#define RALINK_DDR_CFG9 (RALINK_MEMCTRL_BASE+0x64)
#define RALINK_DDR_CFG10 (RALINK_MEMCTRL_BASE+0x68)
#endif
#define SDRAM_CFG0_ALWAYS_ONE ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_START ( 1 << 31)
#define SDRAM_CFG1_SDRAM_INIT_DONE ( 1 << 30)
#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD) || defined(MT7620_FPGA_BOARD) || defined(MT7620_ASIC_BOARD) || \
defined(MT7628_FPGA_BOARD) || defined(MT7628_ASIC_BOARD)
#define SDRAM_CFG0_MIPSREG s7
#define SDRAM_CFG1_MIPSREG s8
#define DDR_CFG0_MIPSREG s7
#define DDR_CFG1_MIPSREG s8
#endif
#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD)
#define DELAY_USEC(us) ((700*(us))/3)
#elif defined(MT7620_FPGA_BOARD) || defined(MT7620_ASIC_BOARD)
#define DELAY_USEC(us) ((60*(us))/4)
#elif defined(MT7628_FPGA_BOARD) || defined(MT7628_ASIC_BOARD)
#define DELAY_USEC(us) ((58*(us))/3)
#else
#define DELAY_USEC(us) ((500*(us))/3)
#endif
#if defined(MT7628_ASIC_BOARD)
#if defined(ON_BOARD_DDR2)
#define MT7628_LDO_1P8V 1
#elif defined(ON_BOARD_DDR1) && defined(ON_BOARD_64M_DRAM_COMPONENT)
#define MT7628_LDO_1P8V 1
#else
#define MT7628_LDO_2P5V 1
#endif
#endif
#define CPLL_DEFAULT_CFG 0x507
#define RVECENT(f,n) \
b f; nop
#define XVECENT(f,bev) \
b f ; \
li k0,bev
.set noreorder
.globl _start
.text
_start:
RVECENT(reset,0) /* U-boot entry point */
RVECENT(reset,1) /* software reboot */
#if defined(CONFIG_INCA_IP)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word 0x00000000 /* phase of the flash */
#elif defined(CONFIG_PURPLE)
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
#else
RVECENT(romReserved,2)
#endif
RVECENT(romReserved,3)
RVECENT(romReserved,4)
RVECENT(romReserved,5)
RVECENT(romReserved,6)
RVECENT(romReserved,7)
RVECENT(romReserved,8)
RVECENT(romReserved,9)
RVECENT(romReserved,10)
RVECENT(romReserved,11)
RVECENT(romReserved,12)
RVECENT(romReserved,13)
RVECENT(romReserved,14)
RVECENT(romReserved,15)
RVECENT(romReserved,16)
RVECENT(romReserved,17)
RVECENT(romReserved,18)
RVECENT(romReserved,19)
RVECENT(romReserved,20)
RVECENT(romReserved,21)
RVECENT(romReserved,22)
RVECENT(romReserved,23)
RVECENT(romReserved,24)
RVECENT(romReserved,25)
RVECENT(romReserved,26)
RVECENT(romReserved,27)
RVECENT(romReserved,28)
RVECENT(romReserved,29)
RVECENT(romReserved,30)
RVECENT(romReserved,31)
RVECENT(romReserved,32)
RVECENT(romReserved,33)
RVECENT(romReserved,34)
RVECENT(romReserved,35)
RVECENT(romReserved,36)
RVECENT(romReserved,37)
RVECENT(romReserved,38)
RVECENT(romReserved,39)
RVECENT(romReserved,40)
RVECENT(romReserved,41)
RVECENT(romReserved,42)
RVECENT(romReserved,43)
RVECENT(romReserved,44)
RVECENT(romReserved,45)
RVECENT(romReserved,46)
RVECENT(romReserved,47)
RVECENT(romReserved,48)
RVECENT(romReserved,49)
RVECENT(romReserved,50)
RVECENT(romReserved,51)
RVECENT(romReserved,52)
RVECENT(romReserved,53)
RVECENT(romReserved,54)
RVECENT(romReserved,55)
RVECENT(romReserved,56)
RVECENT(romReserved,57)
RVECENT(romReserved,58)
RVECENT(romReserved,59)
RVECENT(romReserved,60)
RVECENT(romReserved,61)
RVECENT(romReserved,62)
RVECENT(romReserved,63)
XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
RVECENT(romReserved,65)
RVECENT(romReserved,66)
RVECENT(romReserved,67)
RVECENT(romReserved,68)
RVECENT(romReserved,69)
RVECENT(romReserved,70)
RVECENT(romReserved,71)
RVECENT(romReserved,72)
RVECENT(romReserved,73)
RVECENT(romReserved,74)
RVECENT(romReserved,75)
RVECENT(romReserved,76)
RVECENT(romReserved,77)
RVECENT(romReserved,78)
RVECENT(romReserved,79)
XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
RVECENT(romReserved,81)
RVECENT(romReserved,82)
RVECENT(romReserved,83)
RVECENT(romReserved,84)
RVECENT(romReserved,85)
RVECENT(romReserved,86)
RVECENT(romReserved,87)
RVECENT(romReserved,88)
RVECENT(romReserved,89)
RVECENT(romReserved,90)
RVECENT(romReserved,91)
RVECENT(romReserved,92)
RVECENT(romReserved,93)
RVECENT(romReserved,94)
RVECENT(romReserved,95)
XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
RVECENT(romReserved,97)
RVECENT(romReserved,98)
RVECENT(romReserved,99)
RVECENT(romReserved,100)
RVECENT(romReserved,101)
RVECENT(romReserved,102)
RVECENT(romReserved,103)
RVECENT(romReserved,104)
RVECENT(romReserved,105)
RVECENT(romReserved,106)
RVECENT(romReserved,107)
RVECENT(romReserved,108)
RVECENT(romReserved,109)
RVECENT(romReserved,110)
RVECENT(romReserved,111)
XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
RVECENT(romReserved,113)
RVECENT(romReserved,114)
RVECENT(romReserved,115)
RVECENT(romReserved,116)
RVECENT(romReserved,116)
RVECENT(romReserved,118)
RVECENT(romReserved,119)
RVECENT(romReserved,120)
RVECENT(romReserved,121)
RVECENT(romReserved,122)
RVECENT(romReserved,123)
RVECENT(romReserved,124)
RVECENT(romReserved,125)
RVECENT(romReserved,126)
RVECENT(romReserved,127)
/* We hope there are no more reserved vectors!
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
#ifdef CONFIG_PURPLE
/* 0xbfc00400 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
/* 0xbfc00428 */
.word 0xdc870000
.word 0xfca70000
.word 0x20840008
.word 0x20a50008
.word 0x20c6ffff
.word 0x14c0fffa
.word 0x00000000
.word 0x03e00008
.word 0x00000000
.word 0x00000000
#endif /* CONFIG_PURPLE */
.align 4
reset:
#if defined (RT2883_FPGA_BOARD) || defined (RT2883_ASIC_BOARD) || \
defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD) || \
defined (RT3883_FPGA_BOARD) || defined (RT3883_ASIC_BOARD) || \
defined (RT6855_FPGA_BOARD) || defined (RT6855_ASIC_BOARD) || \
defined (RT6855A_FPGA_BOARD) || defined (RT6855A_ASIC_BOARD) || \
defined (MT7620_FPGA_BOARD) || defined (MT7620_ASIC_BOARD) || \
defined (MT7628_FPGA_BOARD) || defined (MT7628_ASIC_BOARD)
# Initialize the register file
# should not be required with good software practices
or $1,$0, $0
or $2,$0, $0
or $3,$0, $0
or $4,$0, $0
or $5,$0, $0
or $6,$0, $0
or $7,$0, $0
or $8,$0, $0
or $9,$0, $0
or $10,$0, $0
or $11,$0, $0
or $12,$0, $0
or $13,$0, $0
or $14,$0, $0
or $15,$0, $0
or $16,$0, $0
or $17,$0, $0
or $18,$0, $0
or $19,$0, $0
or $20,$0, $0
or $21,$0, $0
or $22,$0, $0
or $23,$0, $0
or $24,$0, $0
or $25,$0, $0
or $26,$0, $0
or $27,$0, $0
or $28,$0, $0
or $29,$0, $0
or $30,$0, $0
or $31,$0, $0
#if defined (MT7628_ASIC_BOARD)
#if (TEXT_BASE == 0xBFC00000) || (TEXT_BASE == 0xBF000000) || (TEXT_BASE == 0xBC000000)
li t0, RALINK_SYSCTL_BASE + 0x34
lw t1, 0(t0)
ori t1, t1, 1<<10
// t1, 0x04000400
sw t1, 0(t0)
#endif
#endif
# Initialize Misc. Cop0 state
# Read status register
mfc0 $10, $12
# Set up Status register:
# Disable Coprocessor Usable bits
# Turn off Reduce Power bit
# Turn off reverse endian
# Turn off BEV (use normal exception vectors)
# Clear TS, SR, NMI bits
# Clear Interrupt masks
# Clear User Mode
# Clear ERL
# Set EXL
# Clear Interrupt Enable
# modify by Bruce
#li $11, 0x0000ff02
li $11, 0x00000004
mtc0 $11, $12
# Disable watch exceptions
mtc0 $0, $18
# Clear Watch Status bits
li $11, 0x3
mtc0 $11, $19
# Clear WP bit to avoid watch exception upon user code entry
# Clear IV bit - Interrupts go to general exception vector
# Clear software interrupts
mtc0 $0, $13
# Set KSeg0 to cacheable
# Config.K0
mfc0 $10, $16
li $11, 0x7
not $11
and $10, $11
or $10, 0x3
mtc0 $10, $16
# Clear Count register
mtc0 $0, $9
# Set compare to -1 to delay 1st count=compare
# Also, clears timer interrupt
li $10, -1
mtc0 $10, $11
# Cache initialization routine
# Long and needed on HW
# Can be skipped if using magic simulation cache flush
# Determine how big the I$ is
/*
************************************************************************
* C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| MMU Size | IS | IL | IA | DS | DL | DA |Rsvd |W|C|E|F| Config1
* | | | | | | | | | |R|A|P|P|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
mfc0 $10, $16, 1 # .word 0x400a8001
# Isolate I$ Line Size
sll $11, $10, 10
srl $11, 29
# Skip ahead if No I$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true I$ line size in bytes
sll $12, $10, 7
srl $12, 29
li $14, 64
sllv $12, $14, $12 # I$ Sets per way
sll $13, $10, 13
srl $13, 29 # I$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28
mtc0 $0, $29
move $15, $12
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x8, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
# Now go through and invalidate the D$
# Now that the I$ has been flushed, the rest of the code can be
# moved to kseg0 and run from the cache to go faster
10:
# Isolate D$ Line Size
sll $11, $10, 19
srl $11, 29
# Skip ahead if No D$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true D$ line size in bytes
sll $12, $10, 16
srl $12, 29
li $14, 64
sllv $12, $14, $12 # D$ Sets per way
sll $13, $10, 22
srl $13, 29 # D$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28
mtc0 $0, $29
mtc0 $0, $28, 2
mtc0 $0, $29, 2
move $15, $12
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x9, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
#if 0 //MTK: 64K I$->32K I$
mfc0 t0, CP0_CONFIG
or t0,(1<<19)
mtc0 t0, CP0_CONFIG
nop
mfc0 t0, CP0_CONFIG,1
move t1 ,t0
and t0,~(0x7 << 22)
or t0,(2 <<22)
mtc0 t0, CP0_CONFIG,1
nop
mfc0 t0, CP0_CONFIG
and t0,~(1<<19)
mtc0 t0, CP0_CONFIG
nop
nop
#endif
#
# Now go through and initialize the L2$
10:
# Check L2 cache size
/*
************************************************************************
* C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| TU | TS | TL | TA | SU | SS | SL | SA | Config2
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
mfc0 $10, $16, 2
# Isolate L2$ Line Size
sll $11, $10, 24
srl $11, 28
# Skip ahead if No L2$
beq $11, $0, 10f
nop
li $14, 2
sllv $11, $14, $11 # Now have true L2$ line size in bytes
# Isolate L2$ Sets per Way
sll $12, $10, 20
srl $12, 28
li $14, 64
sllv $12, $14, $12 # D$ Sets per way
# Isolate L2$ Associativity
sll $13, $10, 28
srl $13, 28 # D$ Assoc (-1)
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear L23TagLo/L23TagHi registers
mtc0 $0, $28, 4
mtc0 $0, $29, 4
move $15, $12
# L2$ Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0xB, 0($14)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
10:
# Determine if we have a TLB
mfc0 $11, $16
sll $11, 22
srl $11, 29
li $15, 0x1 # MT = 1 => TLB
bne $11, $15, 15f
nop
mfc0 $10, $16, 1 # .word 0x400a8001
sll $11, $10, 1
srl $11, 26 # Number of TLB entries (-1)
mtc0 $0, $2 # EntryLo0
mtc0 $0, $3 # EntryLo1
mtc0 $0, $5 # PageMask
mtc0 $0, $6 # Wired
li $12, 0x80000000
1:
mtc0 $11, $0 # Index register
mtc0 $12, $10 # EntryHi
ssnop #.word 0x00000040
ssnop #.word 0x00000040
TLBWI
add $12, (2<<13) # Add 8K to the address to avoid TLB conflict with previous entry
bne $11, $0, 1b
add $11, -1
15:
#endif
#if defined(RT3350_ASIC_BOARD)
// force SDRAM_MD_DRV and SDRAM_MA_DRV from 8mA --> 4mA
li t0, RALINK_SYSCTL_BASE + 0x10
lw t1, 0(t0)
nop
or t1, t1, (3 << 4)
sw t1, 0(t0)
nop
#endif
#if defined(RT6855A_ASIC_BOARD) || defined(RT6855A_FPGA_BOARD)
la t0, RALINK_SYSCTL_BASE + 0x8C
lw t1, 0(t0)
nop
srl t2, t1, 24+1
andi t2, t2, 0x1
bnez t2, 1f
nop
bal rt6855A_cpu_pll
nop
1:
la t0, RALINK_SYSCTL_BASE+0x834
lw t1, 0(t0)
ori t1, t1, 1<<8
sw t1, 0(t0)
nop
la t0, RALINK_SYSCTL_BASE+0x834
lw t1, 0(t0)
li t2, ~(1<<8)
and t1, t1, t2
sw t1, 0(t0)
nop
#endif
#if (TEXT_BASE == 0xBFC00000) || (TEXT_BASE == 0xBF000000) || (TEXT_BASE == 0xBC000000)
#if defined(MT7620_ASIC_BOARD) || defined(MT7620_FPGA_BOARD)
/* warm reset will skip CPU PLL CONFIG */
la t0, RALINK_SYSCTL_BASE+0x38
lw t1, 0(t0)
srl t1, t1, 1
andi t1, t1, 0x3
bnez t1, CPLL_DONE
nop
#if defined(CPLL_FROM_480MHZ)
li a0, 1<<11
#elif defined(CPLL_FROM_XTAL)
li a0, 1<<12
#elif defined(CPLL_FROM_CONF)
li a0, CPLL_MULTI_RATIO_CFG
sll a0, a0, 2
ori a0, a0, CPLL_DIV_RATIO_CFG
sll a0, a0, 6
ori a0, a0, CPLL_SSC_CFG
#endif
#if (defined(CPLL_FROM_480MHZ)||defined(CPLL_FROM_XTAL)||defined(CPLL_FROM_CONF))
bal init_cpu_pll
nop
#else
la t0, RALINK_SYSCTL_BASE+0x10
lw t1, 0(t0)
srl t1, t1, 4
andi t1, t1, 0x3
beqz t1, CPLL_DONE
addiu t2, zero, 3
beq t1, t2, CPLL_DONE
li a0, CPLL_DEFAULT_CFG
bal init_cpu_pll
nop
#endif
CPLL_DONE:
#endif
#if defined(MT7628_ASIC_BOARD) || defined(MT7628_FPGA_BOARD)
/* polling CPLL is ready */
li t1, DELAY_USEC(1000000)
la t5, RALINK_SYSCTL_BASE+0x28
1:
lw t2, 0(t5)
andi t2, t2, 0x1
bnez t2, CPLL_READY
subu t1, t1, 1
bgtz t1, 1b
nop
la t0, RALINK_SYSCTL_BASE+0x2c
lw t3, 0(t0)
ori t3, t3, 0x1
sw t3, 0(t0)
j CPLL_DONE
nop
CPLL_READY:
la t0, RALINK_SYSCTL_BASE+0x2c
lw t1, 0(t0)
li t2, ~0x0C
and t1, t1, t2
ori t1, t1, 0xC
sw t1, 0(t0)
#if defined(CPUCLK_FROM_BPLL)
la t0, RALINK_DYN_CFG0_REG
lw t3, 0(t0)
li t5, ~((0x0F<<8)|(0x0F<<0))
and t3, t3, t5
li t5, (10<<8)|(1<<0)
or t3, t3, t5
sw t3, 0(t0)
la t0, RALINK_SYSCTL_BASE+0x2c
lw t3, 0(t0)
li t4, ~0x0F
and t3, t3, t4
ori t3, t3, 0xE
sw t3, 0(t0)
lw t3, 0(t0)
ori t3, t3, 0x08
sw t3, 0(t0)
#elif defined(CPUCLK_FROM_XTAL)
la t0, RALINK_DYN_CFG0_REG
lw t3, 0(t0)
li t5, ~((0x0F<<8)|(0xF<<0))
and t3, t3, t5
li t5, (1<<8)|(1<<0)
or t3, t3, t5
sw t3, 0(t0)
lw t3, 0(t0)
li t0, RALINK_SYSCTL_BASE+0x2c
lw t3, 0(t0)
li t4, ~0x0F
and t3, t3, t4
ori t3, t3, 0xD
sw t3, 0(t0)
#else
la t0, RALINK_DYN_CFG0_REG
lw t3, 0(t0)
li t5, ~((0x0F<<8)|(0x0F<<0))
and t3, t3, t5
li t5, (10<<8)|(1<<0)
or t3, t3, t5
sw t3, 0(t0)
la t0, RALINK_SYSCTL_BASE+0x2C
lw t3, 0(t0)
li t4, ~0x0F
and t3, t3, t4
ori t3, t3, 0xC
sw t3, 0(t0)
lw t3, 0(t0)
ori t3, t3, 0x08
sw t3, 0(t0)
#endif
CPLL_DONE:
#endif
/* SDR and DDR initialization: delay 200us
*/
li t0, DELAY_USEC(200+40)
li t1, 0x1
1:
sub t0, t0, t1
bnez t0, 1b
nop
#if defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2)
#if defined(RT6855_FPGA_BOARD)||defined(RT6855_ASIC_BOARD) || \
defined(MT7620_FPGA_BOARD)||defined(MT7620_ASIC_BOARD)
/* Use default SYSCFG1 setting */
#if defined(MT7620_FPGA_BOARD) || defined(MT7620_ASIC_BOARD)
li t1, RALINK_SYSCTL_BASE + 0x14
lw t2, 0(t1)
nop
and t2, ~(0x0FFF<<16)
or t2, (0x260<<16)
sw t2, 0(t1)
nop
#endif
#elif defined (RT6855A_FPGA_BOARD) || defined (RT6855A_ASIC_BOARD)
/* set DRAM IO PAD for DDR2 */
#if defined(ON_BOARD_DDR2)
#if 0
la t0, RALINK_SYSCTL_BASE + 0x4
lw t1, 0(t0)
li t2, 1<<23
or t1, t1, t2
sw t1, 0(t0)
nop
#endif
/*ODT ON*/
#if 1
la t0, RALINK_SYSCTL_BASE + 0x4
lw t1, 0(t0)
li t1, 0x000cc0d4
sw t1, 0(t0)
nop
#endif
#endif /* defined(ON_BOARD_DDR2) */
#elif defined(MT7628_FPGA_BOARD) || defined(MT7628_ASIC_BOARD)
/* set DRAM IO PAD for MT7628IC */
/* DDR LDO Enable */
li t1, RALINK_RGCTRL_BASE+0x100
lw t4, 0(t1)
li t2, (1<<31)
or t4, t4, t2
sw t4, 0(t1)
li t1, RALINK_RGCTRL_BASE+0x10c
lw t4, 0(t1)
#if defined (MT7628_LDO_1P8V)
j LDO_1P8V
nop
#elif defined (MT7628_LDO_2P5V)
j LDO_2P5V
nop
#else
li t1, RALINK_SYSCTL_BASE+0xC
lw t2, 0(t1)
srl t2, t2, 16
andi t2, t2, 0x1
beqz t2, LDO_1P8V /* KN */
li t1, RALINK_SYSCTL_BASE+0x10
lw t3, 0(t1)
andi t3, t3, 0x1
bnez t3, LDO_2P5V
#endif
LDO_1P8V:
li t2, ~(1<<6)
and t4, t4, t2
//ori t4, t4, 0x3 /* 1P88V */
li t1, RALINK_RGCTRL_BASE+0x10c
sw t4, 0(t1)
j DDRLDO_SOFT_START
LDO_2P5V:
/* suppose external DDR1 LDO 2.5V */
li t2, 1<<6
or t4, t4, t2
li t1, RALINK_RGCTRL_BASE+0x10c
sw t4, 0(t1)
DDRLDO_SOFT_START:
li t1, RALINK_RGCTRL_BASE+0x10c
lw t2, 0(t1)
li t3, 1<<16
or t2, t2, t3
sw t2, 0(t1)
li t3, DELAY_USEC(250*50)
LDO_DELAY:
subu t3, t3, 1
bnez t3, LDO_DELAY
nop
li t1, RALINK_RGCTRL_BASE+0x10c
lw t2, 0(t1)
li t3, 1<<18
or t2, t2, t3
sw t2, 0(t1)
SET_RG_BUCK_FPWM:
li t1, RALINK_RGCTRL_BASE+0x104
lw t2, 0(t1)
ori t2, t2, 1<<10
sw t2, 0(t1)
DDR_PAD_CFG:
/* clean CLK PAD */
li t1, RALINK_RGCTRL_BASE+0x704
lw t2, 0(t1)
li t8, 0xFFFFF0F0
and t2, t2, t8
/* clean CMD PAD */
li t1, RALINK_RGCTRL_BASE+0x70c
lw t3, 0(t1)
li t8, 0xFFFFF0F0
and t3, t3, t8
/* clean DQ IPAD */
li t1, RALINK_RGCTRL_BASE+0x710
lw t4, 0(t1)
li t8, 0xFFFFF8FF
and t4, t4, t8
/* clean DQ OPAD */
li t1, RALINK_RGCTRL_BASE+0x714
lw t5, 0(t1)
li t8, 0xFFFFF0F0
and t5, t5, t8
/* clean DQS IPAD */
li t1, RALINK_RGCTRL_BASE+0x718
lw t6, 0(t1)
li t8, 0xFFFFF8FF
and t6, t6, t8
/* clean DQS OPAD */
li t1, RALINK_RGCTRL_BASE+0x71c
lw t7, 0(t1)
li t8, 0xFFFFF0F0
and t7, t7, t8
li t1, RALINK_SYSCTL_BASE+0xC
lw t9, 0(t1)
srl t9, t9, 16
andi t9, t9, 0x1
bnez t9, MT7628_AN_DDR1_PAD
MT7628_KN_PAD:
li t8, 0x00000303
or t2, t2, t8
or t3, t3, t8
or t5, t5, t8
or t7, t7, t8
li t8, 0x00000000
or t4, t4, t8
or t6, t6, t8
j SET_PAD_CFG
MT7628_AN_DDR1_PAD:
li t1, RALINK_SYSCTL_BASE+0x10
lw t1, 0(t1)
andi t1, t1, 0x1
beqz t1, MT7628_AN_DDR2_PAD
li t8, 0x00000C0C
or t2, t2, t8
li t8, 0x00000202
or t3, t3, t8
li t8, 0x00000707
or t5, t5, t8
li t8, 0x00000C0C
or t7, t7, t8
li t8, 0x00000000
or t4, t4, t8
or t6, t6, t8
j SET_PAD_CFG
MT7628_AN_DDR2_PAD:
li t8, 0x00000C0C
or t2, t2, t8
li t8, 0x00000202
or t3, t3, t8
li t8, 0x00000404
or t5, t5, t8
li t8, 0x00000C0C
or t7, t7, t8
//li t8, 0x00000200
li t8, 0x00000000 //ODT off
or t4, t4, t8
or t6, t6, t8
SET_PAD_CFG:
li t1, RALINK_RGCTRL_BASE+0x704
sw t2, 0(t1)
li t1, RALINK_RGCTRL_BASE+0x70c
sw t3, 0(t1)
li t1, RALINK_RGCTRL_BASE+0x710
sw t4, 0(t1)
li t1, RALINK_RGCTRL_BASE+0x714
sw t5, 0(t1)
li t1, RALINK_RGCTRL_BASE+0x718
sw t6, 0(t1)
li t1, RALINK_RGCTRL_BASE+0x71c
sw t7, 0(t1)
#else
/* DDR initialization: reg SYSCFG1[25:16]:
* ODT disabled, LVCMOS=1, half drive, turn ON RT3662 DDR IO ODT as 150 ohm when read DRAM
*/
li t1, RALINK_SYSCTL_BASE + 0x14
lw t2, 0(t1)
nop
and t2, ~(0x3FF<<16)
or t2, (0x361<<16)
sw t2, 0(t1)
nop
#endif
/* DDR initialization: reset pin to 0
*/
#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD)
li t1, RALINK_SYSCTL_BASE + 0x40
#else
li t1, RALINK_SYSCTL_BASE + 0x34
lw t2, 0(t1)
and t2, ~(0x1<<10)
#endif
sw t2, 0(t1)
nop
#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD) || \
defined(MT7628_FPGA_BOARD) || defined(MT7628_ASIC_BOARD)
li t0, DELAY_USEC(200+40)
li t1, 0x1
1:
sub t0, t0, t1
bnez t0, 1b
nop
#endif
/* DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready)
*/
DDR_READY:
li t1, RALINK_MEMCTRL_BASE + 0x44 //DDR_CFG1
lw t0, 0(t1)
nop
and t2, t0, (1<<21)
beqz t2, DDR_READY
nop
/* DDR initialization:
*/
#if defined(RT6855_FPGA_BOARD)||defined(RT6855_ASIC_BOARD) || \
defined(MT7620_FPGA_BOARD)||defined(MT7620_ASIC_BOARD) || \
defined(MT7628_FPGA_BOARD)||defined(MT7628_ASIC_BOARD)
/* fpga/asic: reg DDR_CFG2 -- set bit[30]=0 as DDR1 mode when DDR1
* fpga/asic: reg DDR_CFG2 -- set bit[30]=1 as DDR2 mode when DDR2
* fpga/asic: reg DDR_CFG2 -- set bit[6:4]=3'b011 when DDR1
* fpga/asic: reg DDR_CFG2 -- set bit[6:4]=3'b100 when DDR2
*/
li t1, RALINK_MEMCTRL_BASE + 0x48 //DDR_CFG2
lw t0, 0(t1)
nop
and t0, ~(1<<30)
#if ON_BOARD_DDR2
and t0, ~(7<<4)
or t0, (4<<4)
or t0, (1<<30)
#if defined(MT7620_ASIC_BOARD) || defined(MT7628_ASIC_BOARD)
or t0, (1<<11)
#endif
#elif ON_BOARD_DDR1
and t0, ~(7<<4)
or t0, (3<<4)
#endif
#if defined(MT7628_FPGA_BOARD)
li t0, 0x28000033
#endif
sw t0, 0(t1)
nop
#endif /* defined(RT6855_FPGA_BOARD)||defined(RT6855_ASIC_BOARD) */
/* RT3883 and RT6855 will share below setting, RT3352 no boot from NOR */
/*
* fpga: reg DDR_CFG3 -- disable DLL
* asic: reg DDR_CFG3 -- ODT enable (bit 6,2) = 2'b10 when 6855/3883 DDR2
* fpga/asic: reg DDR_CFG3 -- ODT enable (bit 6,2) = 2'b00 when 6855 DDR1
* fpga/asic: reg DDR_CFG3[10][5:3] = 4'b0000 when 6855 DDR1
*/
li t1, RALINK_MEMCTRL_BASE + 0x4c ////DDR_CFG3
lw t2, 0(t1)
#ifdef ON_BOARD_DDR2
#disable ODT; reference board ok, ev board fail
#if defined(MT7620_ASIC_BOARD) || defined(MT7628_ASIC_BOARD)
and t2, ~(1<<6)
or t2, (1<<2)
#else
#enable ODT; both ok
or t2, (1<<6)
and t2, ~(1<<2)
#endif
#elif ON_BOARD_DDR1
and t2, ~(1<<10)
and t2, ~(7<<3)
#if defined(MT7628_FPGA_BOARD)
and t2, 0
or t2, 0x3
#endif
#endif
#if defined(RT3883_FPGA_BOARD) || defined(RT6855_FPGA_BOARD) || defined(MT7620_FPGA_BOARD) || defined(MT7628_FPGA_BOARD)
or t2, 0x1
#endif
#if (!defined(RT6855A_ASIC_BOARD) && !defined(MT7620_ASIC_BOARD) && !defined(MT7628_ASIC_BOARD))
sw t2, 0(t1)
nop
#endif
#ifdef RALINK_DDR_OPTIMIZATION
/* DDR: set Burst Length=4 in 32 bits dram bus for better performance
* Burst Length=8 in non 32 bits dram bus
*/
li t0, RALINK_MEMCTRL_BASE + 0x48
lw t1, 0(t0)
nop
and t1, 0xffffff88
or t1, (CAS_VALUE<<CAS_OFFSET)
or t1, (BL_VALUE<<BL_OFFSET)
sw t1, 0(t0)
nop
li t0, RALINK_MEMCTRL_BASE + 0x4c
lw t1, 0(t0)
nop
and t1, 0xffffffc7
or t1, (AdditiveLatency_VALUE<<AdditiveLatency_OFFSET)
sw t1, 0(t0)
#endif
#if defined(MT7620_ASIC_BOARD) || defined(MT7628_ASIC_BOARD)
li t0, RALINK_MEMCTRL_BASE + 0x50
lw t1, 0(t0)
li t2, ~(0x01F|0x0F0)
and t1, t1, t2
#if ON_BOARD_DDR2
#if defined (ON_BOARD_256M_DRAM_COMPONENT)
ori t1, t1, 7
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
ori t1, t1, 9
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
ori t1, t1, 9
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
ori t1, t1, 9
#endif
#endif
sw t1, 0(t0)
nop
#elif defined(MT7628_FPGA_BOARD) || defined(MT7620_FPGA_BOARD)
li t0, RALINK_MEMCTRL_BASE + 0x50
li t1, 0x0
sw t1, 0(t0)
nop
#endif
#if defined (RT3352_FPGA_BOARD) || defined (RT3883_FPGA_BOARD) || defined (RT6855_FPGA_BOARD) || defined(MT7620_FPGA_BOARD) || defined(MT7628_FPGA_BOARD)
/* DDR initialization: DDR_CFG0 bit 12:0 (refresh interval) to 0x64
* Note. this may have a bad affect on efficiency if the clock rate is 40MHz
*/
li t1, RALINK_MEMCTRL_BASE + 0x40
lw t2, 0(t1)
nop
and t2, ~(0xfff)
#if defined(ON_BOARD_DDR1)
#if defined(MT7628_FPGA_BOARD) || defined(MT7620_FPGA_BOARD)
li t2, 0x110860f9
#else
li t2, 0x21086141
#endif
#else
or t2, 0x64
#endif
sw t2, 0(t1)
nop
#endif
#if 0
/* data output (DQ) delay */
li t1, RALINK_MEMCTRL_BASE + 0x60
li t2, 0xffffffff
sw t2, 0(t1)
nop
li t1, RALINK_MEMCTRL_BASE + 0x64
li t2, 0xffffffff
sw t2, 0(t1)
nop
#endif
/* DDR initialization: config size and width on reg DDR_CFG1
*/
#if defined(ON_BOARD_DDR2)
#if defined (RT6855_ASIC_BOARD) || defined(MT7620_ASIC_BOARD) || defined(MT7628_ASIC_BOARD)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x222A3323
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x222e2323
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x22322323
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x22362323
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t6, 0x223a2323
#else
DRAM Component not defined
#endif
#elif defined (RT6855_FPGA_BOARD) || defined(MT7620_FPGA_BOARD) || defined(MT7628_FPGA_BOARD)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x122A3121
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x222e2323 //0x122E3121
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x12323121
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x12363121
#endif
#elif defined (RT3352_FPGA_BOARD) || defined(RT3883_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || defined(RT3883_ASIC_BOARD)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x222A3323
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x222E3323
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x22323323
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x22363323
#else
DRAM Component not defined
#endif
#else /* RT6855A setting in below lookup table*/
#endif
#elif defined(ON_BOARD_DDR1)
#if defined(RT6855_ASIC_BOARD) || defined(MT7620_ASIC_BOARD) || defined(MT7628_ASIC_BOARD)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x332A3434
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x222E2324 //use aggressive cfg //0x332e2434
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x33322434
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x33362434
#endif
#elif defined(RT6855_FPGA_BOARD) || defined(MT7620_FPGA_BOARD)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x122A3111
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x222e2113 //0x122E3111
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x12323111
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x12363111
#endif
#elif defined(MT7628_FPGA_BOARD)
#ifdef ON_BOARD_128M_DRAM_COMPONENT
li t6, 0x202A2121
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0x202E2121
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0x20322121
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t6, 0x20362121
#endif
#else /* RT6855A setting in below lookup table*/
#endif
#endif /* end of setting DDR_CFG1 */
#ifdef ON_BOARD_DDR_WIDTH_16
or t6, (1<<17)
and t6, ~(1<<16)
#elif defined (ON_BOARD_DDR_WIDTH_8)
and t6, ~(1<<17)
or t6, (1<<16)
#else
DDR width not defined
#endif
/* CONFIG DDR_CFG1[13:12] about TOTAL WIDTH */
and t6, ~(3<<12)
#ifdef ON_BOARD_32BIT_DRAM_BUS
or t6, (3<<12)
#elif defined (ON_BOARD_16BIT_DRAM_BUS)
or t6, (2<<12)
#else
DRAM bus not defined
#endif
#if !defined(RT6855A_ASIC_BOARD) && !defined(MT7620_ASIC_BOARD) && !defined(MT7628_ASIC_BOARD)
li t5, RALINK_MEMCTRL_BASE + 0x44
sw t6, 0(t5)
nop
j SDRAM_INIT_DOWN
nop
#endif
#if defined(RT6855A_ASIC_BOARD)
/* RT6855A DDR configurations */
/* abstract DRAM_SPEED */
la t0, RALINK_SYSCTL_BASE+0x8C
lw t6, 0(t0)
nop
srl t5, t6, 26
andi t5, t5, 0x1
srl t8, t6, 8
andi t8, t8, 0x3
addiu t7, zero, 2
sub t8, t8, t7
bgez t8, 1f /* Large package size*/
nop
addiu t5, t5, 2 /* t5 is column index, DDR 166MHZ and 125MHZ shoud add 2
ftom DRAM_SPEED for RT6855 case */
1:
#if defined(ON_BOARD_DDR1)
sll t5, t5, 2
lui t0, %hi(DDR1_CFG2_TBL)
ori t0, t0, %lo(DDR1_CFG2_TBL)
addu t0, t0, t5
lw t1, 0(t0)
nop
la t0, RALINK_DDR_CFG2
sw t1, 0(t0)
nop
lui t0, %hi(DDR1_CFG3_TBL)
ori t0, t0, %lo(DDR1_CFG3_TBL)
addu t0, t0, t5
lw t1, 0(t0)
la t0, RALINK_DDR_CFG3
sw t1, 0(t0)
nop
/* DQS delay use table value */
lui t0, %hi(DDR1_CFG4_TBL)
ori t0, t0, %lo(DDR1_CFG4_TBL)
addu t0, t0, t5
lw t1, 0(t0)
nop
#if 0
/* DQS delay use DLL detected value then fixed the delay with a constant delay 8 */
la t0, RALINK_SYSCTL_BASE + 0x18
lw t2, 0(t0)
andi t3, t2, 0x1F
srl t2, t2, 5
addiu t6, zero, 5
mul t0, t2, t6
addu t0, t0, t3
subu t0, t0, 8
div t0, t6
mflo t2
mfhi t3
nop
nop
sll t2, t2, 5
or t2, t2, t3
sll t4, t2, 9
or t2, t2, t4
sll t2, t2, 5
li t3, ~(((0x1FF<<9)|0x1FF)<<5)
and t1, t1, t3
or t1, t1, t2
#endif
la t0, RALINK_DDR_CFG4
sw t1, 0(t0)
nop
#endif
#if defined(ON_BOARD_DDR2)
sll t5, t5, 2
lui t0, %hi(DDR2_CFG2_TBL)
ori t0, t0, %lo(DDR2_CFG2_TBL)
addu t0, t0, t5
lw t1, 0(t0)
nop
la t0, RALINK_DDR_CFG2
sw t1, 0(t0)
nop
lui t0, %hi(DDR2_CFG3_TBL)
ori t0, t0, %lo(DDR2_CFG3_TBL)
addu t0, t0, t5
lw t1, 0(t0)
nop
la t0, RALINK_DDR_CFG3
#if 0
lw t1, 0(t0)
/*enable 100% drive strength*/
and t1, ~(0x1<<1)
#endif
sw t1, 0(t0)
nop
/* DQS delay use table value */
lui t0, %hi(DDR2_CFG4_TBL)
ori t0, t0, %lo(DDR2_CFG4_TBL)
addu t0, t0, t5
lw t1, 0(t0)
nop
#if 0
/* DQS delay use DLL detected value then fixed the delay with a constant delay 8 */
la t0, RALINK_SYSCTL_BASE + 0x18
lw t2, 0(t0)
andi t3, t2, 0x1F
srl t2, t2, 5
addiu t6, zero, 5
mul t0, t2, t6
addu t0, t0, t3
subu t0, t0, 8
div t0, t6
mflo t2
mfhi t3
nop
nop
sll t2, t2, 5
or t2, t2, t3
sll t4, t2, 9
or t2, t2, t4
sll t2, t2, 5
li t3, ~(((0x1FF<<9)|0x1FF)<<5)
and t1, t1, t3
or t1, t1, t2
#endif
la t0, RALINK_DDR_CFG4
sw t1, 0(t0)
nop
#if 0
la t0, RALINK_DDR_CFG9
li t1, 0x88880000
sw t1, 0(t0)
nop
#endif
#endif
2:
#if defined(ON_BOARD_DDR1)
#ifdef ON_BOARD_64M_DRAM_COMPONENT
addiu t4, zero, 1
#elif ON_BOARD_128M_DRAM_COMPONENT
addiu t4, zero, 2
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
addiu t4, zero, 3
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
addiu t4, zero, 4
#else
DRAM Component not defined
#endif
#endif
#if defined(ON_BOARD_DDR2)
#if defined (ON_BOARD_256M_DRAM_COMPONENT)
addiu t4, zero, 3
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
addiu t4, zero, 4
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
addiu t4, zero, 5
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
addiu t4, zero, 6
#else
#error "DRAM Component not defined"
#endif
#endif
srl t3, t6, 24
andi t3, t3, 0x3
subu t3, t3, 2
srl t5, t6, 26
andi t5, t5, 0x1
bgez t8, 1f
nop
addiu t5, t5, 2 /* t5 is column index, DDR 166MZH and 125MHZ shoud add 2
ftom DRAM_SPEED for RT6855 case */
1:
#if defined(ON_BOARD_DDR1)
addiu t6, zero, 4
subu t4, t4, 1
mul t2, t4, t6
nop
addu t2, t2, t5
sll t2, t2, 2
lui t0, %hi(DDR1_CFG0_TBL)
ori t0, t0, %lo(DDR1_CFG0_TBL)
addu t0, t0, t2
lw DDR_CFG0_MIPSREG, 0(t0)
nop
lui t0, %hi(DDR1_CFG1_TBL)
ori t0, t0, %lo(DDR1_CFG1_TBL)
addu t0, t0, t2
lw DDR_CFG1_MIPSREG, 0(t0)
nop
#endif
#if defined(ON_BOARD_DDR2)
addiu t6, zero, 4
subu t4, t4, 3
mul t2, t4, t6
nop
addu t2, t2, t5
sll t2, t2, 2
lui t0, %hi(DDR2_CFG0_TBL)
ori t0, t0, %lo(DDR2_CFG0_TBL)
addu t0, t0, t2
lw DDR_CFG0_MIPSREG, 0(t0)
nop
lui t0, %hi(DDR2_CFG1_TBL)
ori t0, t0, %lo(DDR2_CFG1_TBL)
addu t0, t0, t2
lw DDR_CFG1_MIPSREG, 0(t0)
nop
#endif
2:
la t5, RALINK_DDR_CFG0
sw DDR_CFG0_MIPSREG, 0(t5)
nop
la t5, RALINK_DDR_CFG1
sw DDR_CFG1_MIPSREG, 0(t5)
nop
j SDRAM_INIT_DOWN
nop
#endif /* defined(RT6855A_ASIC_BOARD) */
#if defined(MT7620_ASIC_BOARD) || defined(MT7628_ASIC_BOARD)
#if defined(ON_BOARD_DDR1)
#if defined (ON_BOARD_64M_DRAM_COMPONENT)
addiu t4, zero, 0
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
addiu t4, zero, 1
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
addiu t4, zero, 2
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
addiu t4, zero, 3
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
addiu t4, zero, 4
#else
DRAM Component not defined
#endif
#endif /* defined(ON_BOARD_DDR1) */
#if defined(ON_BOARD_DDR2)
#if defined (ON_BOARD_256M_DRAM_COMPONENT)
addiu t4, zero, 0
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
addiu t4, zero, 1
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
addiu t4, zero, 2
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
addiu t4, zero, 3
#else
#error "DRAM Component not defined"
#endif
#endif /* defined(ON_BOARD_DDR2) */
#if defined(CPLL_FROM_480MHZ)|| defined (CPUCLK_FROM_BPLL)
addiu t6, zero, 1
#else
addiu t6, zero, 0
#endif
sll t2, t4, 1
addu t2, t2, t6
sll t2, t2, 2
#if defined(ON_BOARD_DDR1)
lui t0, %hi(DDR1_CFG2_TBL)
ori t0, t0, %lo(DDR1_CFG2_TBL)
addu t0, t0, t2
lw t7, 0(t0)
nop
lui t0, %hi(DDR1_CFG3_TBL)
ori t0, t0, %lo(DDR1_CFG3_TBL)
addu t0, t0, t2
lw t8, 0(t0)
nop
lui t0, %hi(DDR1_CFG4_TBL)
ori t0, t0, %lo(DDR1_CFG4_TBL)
addu t0, t0, t2
lw t9, 0(t0)
nop
lui t0, %hi(DDR1_CFG0_TBL)
ori t0, t0, %lo(DDR1_CFG0_TBL)
addu t0, t0, t2
lw DDR_CFG0_MIPSREG, 0(t0)
nop
lui t0, %hi(DDR1_CFG1_TBL)
ori t0, t0, %lo(DDR1_CFG1_TBL)
addu t0, t0, t2
lw DDR_CFG1_MIPSREG, 0(t0)
nop
#endif
#if defined(ON_BOARD_DDR2)
lui t0, %hi(DDR2_CFG2_TBL)
ori t0, t0, %lo(DDR2_CFG2_TBL)
addu t0, t0, t2
lw t7, 0(t0)
nop
lui t0, %hi(DDR2_CFG3_TBL)
ori t0, t0, %lo(DDR2_CFG3_TBL)
addu t0, t0, t2
lw t8, 0(t0)
nop
lui t0, %hi(DDR2_CFG4_TBL)
ori t0, t0, %lo(DDR2_CFG4_TBL)
addu t0, t0, t2
lw t9, 0(t0)
nop
lui t0, %hi(DDR2_CFG0_TBL)
ori t0, t0, %lo(DDR2_CFG0_TBL)
addu t0, t0, t2
lw DDR_CFG0_MIPSREG, 0(t0)
nop
lui t0, %hi(DDR2_CFG1_TBL)
ori t0, t0, %lo(DDR2_CFG1_TBL)
addu t0, t0, t2
lw DDR_CFG1_MIPSREG, 0(t0)
nop
#endif
la t0, RALINK_DDR_CFG2
sw t7, 0(t0)
nop
la t0, RALINK_DDR_CFG3
sw t8, 0(t0)
nop
la t0, RALINK_DDR_CFG4
sw t9, 0(t0)
nop
#if defined(ON_BOARD_DDR2)
#if defined(MT7620_ASIC_BOARD)
la t0, RALINK_DDR_CFG10
li t1, 0x40404848
sw t1, 0(t0)
#endif
#endif
#if defined(MT7628_ASIC_BOARD)
li t1, RALINK_SYSCTL_BASE+0xC
lw t9, 0(t1)
srl t9, t9, 16
andi t9, t9, 0x1
beqz t9, 1f
la t0, RALINK_DDR_CFG8
li t1, 0x00008282
sw t1, 0(t0)
la t0, RALINK_DDR_CFG9
li t1, 0x00008383
sw t1, 0(t0)
1:
#endif
la t0, RALINK_DDR_CFG0
sw DDR_CFG0_MIPSREG, 0(t0)
nop
la t0, RALINK_DDR_CFG1
sw DDR_CFG1_MIPSREG, 0(t0)
nop
j SDRAM_INIT_DOWN
nop
#endif /* defined(MT7620_ASIC_BOARD) */
#endif /* defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2) */
#ifdef ON_BOARD_SDR
SDR_INIT:
#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD)
li t1, RALINK_SYSCTL_BASE + 0x40
sw zero, 0(t1)
nop
#endif
/* SDR initialization: SDRAM_CFG0
*/
li t5, SDRAM_CFG0_REG
lw t6, 0(t5)
nop
and t6, 0xF0000000
#ifdef FPGA_BOARD
#ifdef RT2880_FPGA_BOARD
#ifdef RT2880_MP
nop
or t6, 0x01825282
//or t6, 0x01815282
nop
#else /* RT2880_SHUTTLE */
or t6, 0x91825282
//or t6, 0x91815282
#endif
#elif defined(RT6855_FPGA_BOARD) || defined (MT7620_FPGA_BOARD) || defined (MT7628_FPGA_BOARD)
or t6, 0xD1825272
//or t6, 0xD1916292
#else //2883, 3052, 3352, 3883, 5350 fpga
nop
or t6, 0xD1825272
//or t6, 0x01815282
nop
#endif
#else //ASIC_BOARD
#if defined(RT6855_ASIC_BOARD) || defined (MT7620_ASIC_BOARD) || defined (MT7628_ASIC_BOARD)
or t6, 0xD1916292
#else
or t6, 0xD1825272
#endif
#endif
nop
#if (!defined(RT6855A_ASIC_BOARD) && !defined(MT7620_ASIC_BOARD) && !defined(MT7628_ASIC_BOARD))
sw t6, 0(t5)
nop
#endif
li t5, SDRAM_CFG1_REG
#ifdef ASIC_BOARD
/*
* Turn on SDRAM RBC (BIT 29 in SDRAM_CFG1, offset 0x4) in RT3052.
* RT2880 RBC bit is Reserved bit, and change the same value for RT2880 and RT3052
* Original 0x81xx0600 -> 0xa1xx0600
* by bobtseng, 2008.7.7.
*/
#if defined (ON_BOARD_16M_DRAM_COMPONENT)
li t6, 0xa0000668
#elif defined (ON_BOARD_64M_DRAM_COMPONENT)
li t6, 0xa1010600
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t6, 0xa1110600
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0xa1120300
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0xa1220600
#elif defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2)
#else
DRAM Component not defined
#endif
#ifdef ON_BOARD_32BIT_DRAM_BUS
and t6, 0xFEFFFFFF
or t6, (1<<24)
#elif defined ON_BOARD_16BIT_DRAM_BUS
and t6, 0xFEFFFFFF
#else
DRAM bus not defined
#endif
#else /* not ASIC_BOARD */
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t6, 0xa1010096
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t6, 0xa1110096
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t6, 0xa112004B
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t6, 0xa1220096
#else
DRAM Component not defined
#endif
#ifdef ON_BOARD_32BIT_DRAM_BUS
and t6, 0xFEFFFFFF
or t6, (1<<24)
#elif defined (ON_BOARD_16BIT_DRAM_BUS)
and t6, 0xFEFFFFFF
#else
DRAM bus not defined
#endif
#endif
DO_SDRINIT:
nop
#if (!defined(RT6855A_ASIC_BOARD) && !defined(MT7620_ASIC_BOARD) && !defined(MT7628_ASIC_BOARD))
sw t6, 0(t5)
nop
#endif
#if defined(RT6855A_ASIC_BOARD)
move t1, zero /* force to 140Mhz case */
#if defined (ON_BOARD_16M_DRAM_COMPONENT)
addiu t4, zero, 0
#elif defined (ON_BOARD_64M_DRAM_COMPONENT)
addiu t4, zero, 1
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
addiu t4, zero, 2
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
addiu t4, zero, 3
#else
DRAM Component not defined
#endif
lui t0, %hi(SDR_CFG0_TBL)
ori t0, t0, %lo(SDR_CFG0_TBL)
sll t3, t1, 2
addu t0, t0, t3
lw SDRAM_CFG0_MIPSREG, 0(t0)
nop
addiu t3, zero, 2
mul t2, t4, t3
nop
addu t2, t2, t1
sll t2, t2, 2
lui t0, %hi(SDR_CFG1_TBL)
ori t0, t0, %lo(SDR_CFG1_TBL)
addu t0, t0, t2
lw SDRAM_CFG1_MIPSREG, 0(t0)
nop
la t0, SDRAM_CFG0_REG
sw SDRAM_CFG0_MIPSREG, 0(t0)
nop
la t0, SDRAM_CFG1_REG
sw SDRAM_CFG1_MIPSREG, 0(t0)
nop
j WAIT_SDRAM_INIT_DOWN
nop
#endif /* defined(RT6855A_ASIC_BOARD) */
#if defined(MT7620_ASIC_BOARD) || defined(MT7628_ASIC_BOARD)
#if defined (ON_BOARD_64M_DRAM_COMPONENT)
addiu t4, zero, 0
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
addiu t4, zero, 1
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
addiu t4, zero, 2
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
addiu t4, zero, 3
#else
DRAM Component not defined
#endif
li t0, RALINK_SYSCTL_BASE + 0x10
lw t1, 0(t0)
srl t1, t1, 4
andi t1, t1, 0x3
addiu t2, zero, 3
addiu t6, zero, 1
subu t2, t2, t1
movn t6, zero, t2
sll t2, t4, 1
addu t2, t2, t6
sll t2, t2, 2
lui t0, %hi(SDR_CFG0_TBL)
ori t0, t0, %lo(SDR_CFG0_TBL)
addu t0, t0, t2
lw SDRAM_CFG0_MIPSREG, 0(t0)
nop
lui t0, %hi(SDR_CFG1_TBL)
ori t0, t0, %lo(SDR_CFG1_TBL)
addu t0, t0, t2
lw SDRAM_CFG1_MIPSREG, 0(t0)
#if defined(RALINK_SDR_POWERSAVE)
#endif
la t0, SDRAM_CFG0_REG
sw SDRAM_CFG0_MIPSREG, 0(t0)
nop
la t0, SDRAM_CFG1_REG
sw SDRAM_CFG1_MIPSREG, 0(t0)
nop
j WAIT_SDRAM_INIT_DOWN
nop
#endif /* defined(MT7620_ASIC_BOARD) */
WAIT_SDRAM_INIT_DOWN:
la t5, SDRAM_CFG1_REG
lw t6, 0(t5)
nop
and t6, t6, SDRAM_CFG1_SDRAM_INIT_DONE
beqz t6, WAIT_SDRAM_INIT_DOWN
nop
#endif // ON_BOARD_SDR //
SDRAM_INIT_DOWN:
#endif /* #if (TEXT_BASE == 0xBFC00000) || (TEXT_BASE == 0xBF000000) || (TEXT_BASE == 0xBC000000) */
#if defined(RT3883_FPGA_BOARD) || defined(RT3883_ASIC_BOARD)
#ifdef ON_BOARD_DDR2
#if (TEXT_BASE != 0xBFC00000) && (TEXT_BASE != 0xBF000000) && (TEXT_BASE != 0xBC000000)
/* DDR initialization: reg SYSCFG1[25:16]:
* ODT disabled, LVCMOS=1, half drive, turn ON RT3662 DDR IO ODT as 150 ohm when read DRAM
*/
li t1, RALINK_SYSCTL_BASE + 0x14
lw t2, 0(t1)
nop
and t2, ~(0x3FF<<16)
or t2, (0x361<<16)
sw t2, 0(t1)
nop
#endif
#endif
#endif
#ifdef RT3352_ASIC_BOARD
/* adjust the SW reg voltage level higher */
li t1, RALINK_SYSCTL_BASE + 0x88
li t2, 0xECC340
sw t2, 0(t1)
nop
/* set LDODIG 1.24V */
li t1, RALINK_SYSCTL_BASE + 0x8c
li t2, 0x9B82
sw t2, 0(t1)
nop
#if 1
/* RT3352 EVB board with 32bits DDR shall disable this */
/*
* Enable spreading spectrum clock
* SSC_MODUMAG=7: +/-1.00% for center; -2.00% for down
*/
li t1, RALINK_SYSCTL_BASE + 0x54
li t2, 0x71
nop
sw t2, 0(t1)
#endif
#ifdef ON_BOARD_DDR2
#if 0
/* RT3883 EVB board with Nanya 1G DDR shall enable this */
/* data output (DQ) delay */
li t1, RALINK_MEMCTRL_BASE + 0x60
li t2, 0
sw t2, 0(t1)
nop
li t1, RALINK_MEMCTRL_BASE + 0x64
li t2, 0
sw t2, 0(t1)
nop
#endif
#if 0
/* RT3352 EVB board with 32bits DDR shall enable this */
/* data output (DQ) delay */
li t1, RALINK_MEMCTRL_BASE + 0x60
li t2, 0xffffffff
sw t2, 0(t1)
nop
li t1, RALINK_MEMCTRL_BASE + 0x64
li t2, 0xffffffff
sw t2, 0(t1)
nop
#endif
#if 0
/* RT3352 EVB board with 16/32 bits DDR shall enable this */
/*
* DDR_PAD_DRV_1=00 (full drive)
* DDR_PAD_DS=0 (DDR2 differential RX application)
* DDR_PAD_LVCMO=0 (DDR default)
* DDR_PAD_DRV_0=00 (full drive)
*/
li t1, RALINK_SYSCTL_BASE + 0x14
and t2, ~(0x33F00000)
sw t2, 0(t1)
nop
#endif
#endif /* ON_BOARD_DDR2 */
#endif /* RT3352_ASIC_BOARD */
#if defined(ON_BOARD_DDR1) || defined(ON_BOARD_DDR2)
#if defined(RT3883_FPGA_BOARD) || defined(RT3883_ASIC_BOARD)
/* get cpu frequency from SYSCFG0 bit 9:8, and adjust tRFC accordingly
*/
li t0, RALINK_SYSCTL_BASE + 0x10
lw t1, 0(t0)
nop
and t1, (0x3 << 8)
bne t1, (0x3 << 8), tRFC480
nop
/* DDR initialization: DDR_CFG0: adjust tRFC according to size and cpu clock
* for a better performance
* applied for both rom and ram version (SPI and NAND flash)
*/
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t4, 0x2498E4F0
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t4, 0x2498E4F0
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498E4F0
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x249924F0
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x249964F0
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x249924F0
#else
DRAM Component not defined
#endif
j tRFCinit
nop
tRFC480:
bne t1, (0x2 << 8), tRFC250
nop
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t4, 0x2498E4C0
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t4, 0x2498E4C0
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498E4C0
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x249924C0
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x249964C0
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x249924C0
#else
DRAM Component not defined
#endif
j tRFCinit
nop
tRFC250:
#ifdef ON_BOARD_64M_DRAM_COMPONENT
li t4, 0x2498A3B0
#elif defined (ON_BOARD_128M_DRAM_COMPONENT)
li t4, 0x2498A3B0
#elif defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498A3B0
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x2499C3B0
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x249903B0
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x2499A3B0
#else
DRAM Component not defined
#endif
#elif defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD)
#if defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2498E400
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x24992400
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x24996400
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x249A2400
#else
DRAM Component not defined
#endif
#elif defined(RT6855_ASIC_BOARD) || defined (MT7620_ASIC_BOARD) || defined (MT7628_ASIC_BOARD)
#if defined(ON_BOARD_DDR1)
li t4, 0x24218618 //use aggressive cfg //0x35A26500
#elif defined(ON_BOARD_DDR2)
//li t4, 0x35A28410
#if defined (ON_BOARD_256M_DRAM_COMPONENT)
li t4, 0x2419E2E5
#elif defined (ON_BOARD_512M_DRAM_COMPONENT)
li t4, 0x249AA2E5
#elif defined (ON_BOARD_1024M_DRAM_COMPONENT)
li t4, 0x249B42E5
#elif defined (ON_BOARD_2048M_DRAM_COMPONENT)
li t4, 0x249CE2E5
#else
DRAM Component not defined
#endif
#endif
#elif defined(RT6855_FPGA_BOARD) || defined (MT7620_FPGA_BOARD) || defined (MT7628_FPGA_BOARD)
#if defined(ON_BOARD_DDR1)
/* below 0x21086140 is base on CLK = 40Mhz setting */
li t4, 0x21086140
#elif defined(ON_BOARD_DDR2)
/* below 0x21090138 is base on CLK = 40Mhz setting */
li t4, 0x21090138
#endif
#elif defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD)
#else
error "DRAM Component not defined"
#endif
tRFCinit:
#if 0
li t3, RALINK_MEMCTRL_BASE + 0x40
sw t4, 0(t3)
nop
#endif
#if defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD) ||\
defined(MT7620_FPGA_BOARD) || defined(MT7620_ASIC_BOARD) || \
defined(MT7628_FPGA_BOARD) || defined(MT7628_ASIC_BOARD)
#if defined(RALINK_DDR_POWERSAVE)
/* DDR: enable self auto refresh for power saving
* enable it by default for both RAM and ROM version (for CoC)
*/
#if defined(MT7628_FPGA_BOARD) || defined(MT7628_ASIC_BOARD)
li t0, RALINK_MEMCTRL_BASE + 0x14
#else
li t0, RALINK_MEMCTRL_BASE + 0x1C
#endif
lw t1, 0(t0)
nop
and t1, 0xff000000
or t1, 0x01
sw t1, 0(t0)
nop
#if defined(MT7628_FPGA_BOARD) || defined(MT7628_ASIC_BOARD)
li t0, RALINK_MEMCTRL_BASE + 0x10
#else
li t0, RALINK_MEMCTRL_BASE + 0x18
#endif
lw t1, 0(t0)
nop
or t1, 0x10
sw t1, 0(t0)
nop
#endif
#endif // defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD) //
#else // SDR //
#if defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD) || \
defined (MT7620_FPGA_BOARD) || defined (MT7620_ASIC_BOARD) || \
defined (MT7628_FPGA_BOARD) || defined (MT7628_ASIC_BOARD)
#if defined(RALINK_SDR_POWERSAVE)
/* SDR:enable precharge power saving
*/
#if defined(MT7628_FPGA_BOARD) || defined(MT7628_ASIC_BOARD)
li t0, RALINK_MEMCTRL_BASE + 0x14
#else
li t0, RALINK_MEMCTRL_BASE + 0x1C
#endif
lw t1, 0(t0)
nop
and t1, 0xff000000
or t1, 0x01
sw t1, 0(t0)
nop
li t0, RALINK_MEMCTRL_BASE + 0x04
lw t1, 0(t0)
nop
or t1, 0x10000000
sw t1, 0(t0)
nop
#endif // RALINK_MEMORY_POWER_SAVE //
#endif // defined(RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD)
#endif /* defined(ON_BOARD_DDR1)||defined(ON_BOARD_DDR2) */
#if defined(RT3352_FPGA_BOARD) || defined(RT3352_ASIC_BOARD) || \
defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
#if defined (RALINK_CPU_AUTOFREQUENCY)
/* auto freq adjustment 3352,5350 support
*/
li t0, RALINK_SYSCTL_BASE + 0x44
li t1, 0x1f0112
sw t1, 0(t0)
nop
li t0, RALINK_SYSCTL_BASE + 0x3c
li t1, 0x3040101
sw t1, 0(t0)
nop
li t0, RALINK_SYSCTL_BASE + 0x40
li t1, 0x80035f41
sw t1, 0(t0)
nop
#endif
#endif // defined(RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) //
//gpiomode for non 6855A
#if !defined(RT6855A_FPGA_BOARD) && !defined(RT6855A_ASIC_BOARD) && !defined(MT7628_ASIC_BOARD)
li t5, RALINK_SYSCTL_BASE + 0x0060
lw t6, 0(t5)
nop
or t6, 0x03
#if defined (RT2880_ASIC_BOARD) || defined (RT2880_FPGA_BOARD)
/* enable normal function i2c, spi, uartl, jtag, mdio, sdram */
and t6, ~(0x1<<0)
and t6, ~(0x1<<2)
and t6, ~(0x1<<3)
and t6, ~(0x1<<4)
and t6, ~(0x1<<5)
and t6, ~(0x1<<6)
#elif defined(MT7628_FPGA_BOARD) || defined (MT7628_ASIC_BOARD)
/* Need add code for MT7628IC GPIO mode */
#else
/* enable normal function i2c, spi, uartl, jtag, mdio, ge1 */
and t6, ~(0xf<<7)
and t6, ~(0x3<<5)
and t6, ~(0x3)
#if defined(MT7620_FPGA_BOARD) || defined (MT7620_ASIC_BOARD)
and t6, ~(0xf<<16)
/* set PERST_N to GPIO MODE */
or t6, (0x2<<16)
/* set NAND|SD to GPIO MODE */
or t6, (0x2<<18)
#else
/* LNA_G_SHARE_MODE and LNA_A_SHARE_MODE at normal function, not GPIO mode */
and t6, ~(0xf<<16)
#endif
#endif
#if defined(RT3052_ASIC_BOARD) || defined(RT3352_ASIC_BOARD) || defined(RT6855_ASIC_BOARD)
#if defined(P5_MAC_TO_PHY_MODE)
//set mdio pin to normal mode
and t6, ~0x80
#else
//set mdio pin to gpio mode
or t6, 0x80
#endif
#if defined(ON_BOARD_16BIT_DRAM_BUS)
//set SDRAM pin to gpio mode
or t6, 0x100
#endif
#if defined(UARTF_AT_GPIO_FUNC)
//configure UARTF pin to gpio mode (GPIO7~GPIO14)
or t6, 0x1c
#endif
#endif
#if defined(MT7620_ASIC_BOARD)
#if defined(P5_MAC_TO_PHY_MODE)
//set mdio pin to normal mode
and t6, ~(0x2<<7)
#else
//set mdio pin to gpio mode
or t6, (0x2<<7)
#endif
#if defined(UARTF_AT_GPIO_FUNC)
//configure UARTF pin to gpio mode (GPIO7~GPIO14)
or t6, 0x1c
#endif
#endif
#ifdef MAC_TO_VITESSE_MODE
//set spi pin to normal mode
#if defined (RT2880_FGPA_BOARD) || defined (RT2880_ASIC_BOARD)
and t6, ~(1<<2)
#else
and t6, ~(1<<1)
#endif
#endif
#ifdef PCI_AT_GPIO_FUNC
or t6, 1<<7
#endif
#if defined(RT3883_FPGA_BOARD) || defined(RT3883_ASIC_BOARD)
//PCI share mode for NOR flash read/write
#if 0
//old PCI share mode: 3'b010
and t6, ~(7<<11)
or t6, 2<<11
#else
//new PCI share mode: 3'b011
and t6, ~(7<<11)
or t6, 3<<11
#endif
#endif
//set GPIOMODE
nop
sw t6, 0(t5)
nop
#ifdef PCI_AT_GPIO_FUNC
/* output high */
li t5, 0xa0300674
li t6, 0xffffffff
nop
sw t6,0(t5)
nop
li t5, 0xa0300670
li t6, 0xffffffff
nop
sw t6, 0(t5)
nop
#endif
/* SPI_HOLD should not set as GPIO output */
//set all GPIO to output high
li t5, RALINK_PIO_BASE + 0x24
#if defined(MT7620_ASIC_BOARD) || defined(MT7620_FPGA_BOARD)
/* for MT7620 RFB power saving, change UARTF pins to input mode */
li t6, 0x00ff807f
#else
li t6, 0xffffbfff
#endif
nop
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x2C
li t6, 0xffffffff
nop
sw t6, 0(t5)
nop
#if defined(MT7620_ASIC_BOARD) || defined(MT7620_FPGA_BOARD)
#if 0 // set GPIO36(PERST_N) to output mode and pull low
li t0, RALINK_PIO_BASE + 0x4C
lw t1, 0(t0)
li t2, 1<<12
or t1, t1, t2
sw t1, 0(t0)
li t0, RALINK_PIO_BASE + 0x48
lw t1, 0(t0)
li t2, ~(1<<12)
and t1, t1, t2
sw t1, 0(t0)
#endif
#endif
#if defined(RT3052_ASIC_BOARD) || defined (RT3052_FPGA_BOARD)
#if defined(ON_BOARD_16BIT_DRAM_BUS)
//if sdram bus is 16bits,set gpio24~gpio39 to output high
li t6, 0xffff
nop
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x54
li t6, 0xffff
nop
sw t6, 0(t5)
nop
#endif
#endif
#if defined(RT5350_ASIC_BOARD)
// set default LED polarity value for RT5350 REF board
// Active status:
// EPHY_LED0 H: Light
// EPHY_LED1 H: Light
// EPHY_LED2 H: Light
// EPHY_LED3 L: Light
// EPHY_LED4 H: Light
li t5, RALINK_ETH_SW_BASE + 0x168
li t6, 0x17
nop
sw t6, 0(t5)
nop
// set default LED polarity value for RT5350 REF board
li t5, RALINK_11N_MAC_BASE + 0x102c
li t6, 0x40000000
nop
sw t6, 0(t5)
nop
#endif
#if defined(RT2880_ASIC_BOARD)
//turn on power LED (GPIO 12)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<12
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<12
nop
sw t6, 0(t5)
nop
#elif defined(RT2883_ASIC_BOARD)
//turn on power LED (GPIO 8)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<8
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<8
nop
sw t6, 0(t5)
nop
#elif defined(RT3052_ASIC_BOARD)
//turn on power LED (GPIO 9)
li t5, RALINK_PIO_BASE + 0x24
lw t6, 0(t5)
nop
or t6, 1<<9
sw t6, 0(t5)
nop
li t5, RALINK_PIO_BASE + 0x30
li t6, 1<<9
nop
sw t6, 0(t5)
nop
#elif defined(RT3352_ASIC_BOARD)
//turn on power LED (GPIO ?)
#elif defined(RT5350_ASIC_BOARD)
//turn on power LED (GPIO ?)
#elif defined(RT6855_ASIC_BOARD) || defined(MT7620_ASIC_BOARD)
//turn on power LED (GPIO ?)
#elif defined(RT3883_ASIC_BOARD)
//turn on power LED (GPIO ?)
#endif
#endif
/* config SYSCFG or SYSCFG1 register accordingly
*/
#if defined(RT2880_ASIC_BOARD) || defined(RT2880_FPGA_BOARD)
// Need to remap the vector memory to 0x0 if no memory there
li t0, RALINK_SYSCTL_BASE + 0x0010
li t1, 0x00C10084 //prefetch off
sw t1, 0(t0)
#endif
#if defined(RT2883_ASIC_BOARD) || defined(RT2883_FPGA_BOARD)
//set PCIe to RC mode
li t0, RALINK_SYSCTL_BASE + 0x10
lw t1, 0(t0)
nop
or t1, t1, (1 << 23)
sw t1, 0(t0)
nop
#endif
#if defined(RT3883_ASIC_BOARD) || defined(RT3883_FPGA_BOARD)
//FIXME: read from SYSCFG
li t0, RALINK_SYSCTL_BASE + 0x14
lw t2, 0(t0)
nop
and t2, ~(3 << 14) //GE2 to RGMII mode
and t2, ~(3 << 12) //GE1 to RGMII mode
or t2, (1 << 8) //PCIe to RC mode (for ethernet)
or t2, (1 << 7) //PCI to Host mode (for ethernet)
sw t2, 0(t0)
nop
#endif
#if defined(RT2880_FPGA_BOARD) || defined(RT2880_ASIC_BOARD)
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
/* Initialize caches...
*/
bal mips_cache_reset
nop
/* ... and enable them.
*/
li t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG
#endif
/* Set up temporary stack.
*/
li a0, CFG_INIT_SP_OFFSET
//bal mips_cache_lock
nop
li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
la sp, 0(t0)
/* Initialize GOT pointer.
*/
#if 0
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_ - 1f + 4
1:
move gp, ra
lw t1, 0(ra)
add gp, t1
#else
/* winfred: a easier way to get gp value so that mipsel-linux-as can
* assemble correctly without -mips_allow_branch_to_undefined flag
*/
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_
1:
lw gp, 0(ra)
#endif
#if (TEXT_BASE == 0xBFC00000) || (TEXT_BASE == 0xBF000000) || (TEXT_BASE == 0xBC000000)
#if defined (CONFIG_DDR_CAL)
bal lock_dcache
nop
bal fill_icache
nop
li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
la sp, 0(t0)
#endif
#endif
la t9, board_init_f
j t9
nop
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* a0 = addr_sp
* a1 = gd
* a2 = destination address
*/
.globl relocate_code
.ent relocate_code
relocate_code:
#if (TEXT_BASE == 0xBFC00000) || (TEXT_BASE == 0xBF000000) || (TEXT_BASE == 0xBC000000)
#if defined (CONFIG_DDR_CAL)
bal unlock_dcache
nop
#endif
#endif
move sp, a0 /* Set new stack pointer */
li t0, CFG_MONITOR_BASE
la t3, in_ram
lw t2, -12(t3) /* t2 <-- uboot_end_data */
move t1, a2
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
*/
move t6, gp
sub gp, CFG_MONITOR_BASE
add gp, a2 /* gp now adjusted */
sub t6, gp, t6 /* t6 <-- relocation offset */
/*
* t0 = source address
* t1 = target address
* t2 = source end address
*/
/* On the purple board we copy the code earlier in a special way
* in order to solve flash problems
*/
#ifndef CONFIG_PURPLE
1:
lw t3, 0(t0)
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
addu t1, 4 /* delay slot */
#endif
/* If caches were enabled, we would have to flush them here.
*/
/* Jump to where we've relocated ourselves.
*/
addi t0, a2, in_ram - _start
j t0
nop
.word uboot_end_data
.word uboot_end
.word num_got_entries
in_ram:
/* Now we want to update GOT.
*/
lw t3, -4(t0) /* t3 <-- num_got_entries */
addi t4, gp, 8 /* Skipping first two entries. */
li t2, 2
1:
lw t1, 0(t4)
beqz t1, 2f
add t1, t6
sw t1, 0(t4)
2:
addi t2, 1
blt t2, t3, 1b
addi t4, 4 /* delay slot */
/* Clear BSS.
*/
lw t1, -12(t0) /* t1 <-- uboot_end_data */
lw t2, -8(t0) /* t2 <-- uboot_end */
add t1, t6 /* adjust pointers */
add t2, t6
sub t1, 4
1: addi t1, 4
bltl t1, t2, 1b
sw zero, 0(t1) /* delay slot */
move a0, a1
la t9, board_init_r
j t9
move a1, a2 /* delay slot */
.end relocate_code
/* Exception handlers.
*/
romReserved:
b romReserved
romExcHandle:
b romExcHandle
#if defined(RT6855A_ASIC_BOARD)
.global rt6855A_cpu_pll
.ent rt6855A_cpu_pll
rt6855A_cpu_pll:
la t0, RALINK_SYSCTL_BASE + 0x8C
lw t1, 0(t0)
nop
srl t2, t1, 9
andi t2, t2, 0x1
bnez t2, TFBGA_PACKAGE_DOWN
nop
srl t2, t1, 26
andi t2, t2, 0x1
beqz t2, LQFP_PACKAGE_DOWN
nop
LQFP_PACKAGE_UP:
/* 500Mhz up to 560Mhz */
la t0, RALINK_SYSCTL_BASE+0x1D0
addiu t3, zero, 100-1 /* t3=DIVF */
li t4, 2<<8 /* t4=DIVQ */
//addiu t6, zero, 0 /* t6=DIVR */
li t6, ~((0x0FF<<16)|(0x7<<8)|0x1F)
1:
lw t8, 0(t0)
nop
and t8, t8, t6
or t8, t8, t4
sll t7, t3, 16
or t8, t8, t7
sw t8, 0(t0)
nop
/* wait at least 50 usec for PLL lock */
li t5, ((50*(500+50))/3)
3:
subu t5, t5, 1
bgtz t5, 3b
nop
addiu t3, t3, 1
addiu t7, zero, 112-1
subu t8, t7, t3
bgez t8, 1b
nop
j PLL_DONE
nop
LQFP_PACKAGE_DOWN:
/* 500Mhz down to 420Mhz */
la t0, RALINK_SYSCTL_BASE+0x1D0
addiu t3, zero, 100-1 /* t3=DIVF */
li t4, 2<<8 /* t4=DIVQ */
//addiu t6, zero, 0 /* t6=DIVR */
li t6, ~((0x0FF<<16)|(0x7<<8)|0x1F)
1:
lw t8, 0(t0)
nop
and t8, t8, t6
or t8, t8, t4
sll t7, t3, 16
or t8, t8, t7
sw t8, 0(t0)
nop
/* wait at least 50 usec for PLL lock */
li t5, ((50*(500+50))/3)
3:
subu t5, t5, 1
bgtz t5, 3b
nop
subu t3, t3, 1
addiu t7, zero, 84-1
subu t8, t3, t7
bgez t8, 1b
nop
j PLL_DONE
nop
TFBGA_PACKAGE_DOWN:
/* 665Mhz down to 560Mhz */
la t0, RALINK_SYSCTL_BASE+0x1CC
addiu t3, zero, 133-1 /* t3=DIVF */
li t4, 1<<8 /* t4=DIVQ */
addiu t6, zero, 1 /* t6=DIVR */
li t1, ~((0x0FF<<16)|(0x7<<8)|0x1F)
1:
lw t8, 0(t0)
nop
and t8, t8, t1
or t8, t8, t4
or t8, t8, t6
sll t7, t3, 16
or t8, t8, t7
sw t8, 0(t0)
nop
/* wait at least 50 usec for PLL lock */
li t5, ((50*(700+70))/3)
3:
subu t5, t5, 1
bgtz t5, 3b
nop
subu t3, t3, 1
addiu t7, zero, 120-1
subu t8, t3, t7
bgez t8, 1b
nop
addiu t3, zero, 238-1
li t4, 2<<8
2:
lw t8, 0(t0)
nop
and t8, t8, t1
or t8, t2, t4
or t8, t8, t6
sll t7, t3, 16
or t8, t8, t7
sw t8, 0(t0)
nop
/* wait at least 50 usec for PLL lock */
li t5, ((50*(600+60))/3)
4:
subu t5, t5, 1
bgtz t5, 4b
nop
subu t3, t3, 1*2
addiu t7, zero, 224-1
subu t8, t3, t7
bgez t8, 2b
nop
PLL_DONE:
jr ra
nop
.end rt6855A_cpu_pll
#endif
#if defined(MT7620_ASIC_BOARD) || defined(MT7620_FPGA_BOARD) || defined(MT7628_ASIC_BOARD) || defined(MT7628_FPGA_BOARD)
/************************************************************************************/
/* */
/* void init_cpu_pll(const u16 cpll_param) */
/* cpll_param = a0 = AUX1[12],AUX0[11],MULTI_RATIO[10:8],DIV_RATIO[7:6],SSC[5:0] */
/* */
/************************************************************************************/
.globl init_cpu_pll
.ent init_cpu_pll
init_cpu_pll:
/* check AUX1[12] and AUX0[11] */
la t0, RALINK_CPLLCFG1_REG
lw t1, 0(t0)
li t2, 1<<12
and t2, a0, t2
move t5, zero
li t4, 1<<25 /* t4=1<<25, AUX1 as clock source */
bnez t2, 1f
nop
li t3, 1<<11
and t3, a0, t3
li t4, 1<<24 /* t4=1<<24, AUX0 as clock source */
movz t4, zero, t3
1:
/* Switch clock source from CPU PLL to AUX1 */
la t0, RALINK_CPLLCFG1_REG
lw t1, 0(t0)
li t2, ~(0x3<<24)
and t1, t1, t2
//li t2, 1<<25 /* choose AUX1 XTAL 20/40Mhz for backup clock source */
li t2, 1<<24 /* choose 480Mhz for backup clock source */
movn t2, zero, t4
or t1, t1, t2
or t1, t1, t4
sw t1, 0(t0)
bnez t4, CPLL_EXIT
nop
/* read CPLLCFG0 before SW_CFG = 1 */
la t0, RALINK_CPLLCFG0_REG
lw t1, 0(t0)
/* apply new params */
la t0, RALINK_CPLLCFG0_REG
lw t3, 0(t0)
li t2, 1<<31
or t3, t3, t2
sw t3, 0(t0)
nop
/* Power down CPU PLL */
la t0, RALINK_CPLLCFG1_REG
lw t2, 0(t0)
li t3, 1<<26
or t2, t2, t3
sw t2, 0(t0)
/* Set new CPU PLL freq & SSC */
//la t0, RALINK_CPLLCFG0_REG
//lw t1, 0(t0)
and t2, a0, 0x3F
sll t2, t2, 4
srl t3, a0, 6
and t3, t3, 0x3
sll t3, t3, 10
srl t4, a0, 8
and t4, t4, 0x7
sll t4, t4, 16
or t2, t2, t3
or t2, t2, t4
li t3, ~((0x7<<16)|(0x3<<10)|(0x1F<<4))
and t1, t1, t3
or t1, t1, t2
li t5, 1<<31
or t1, t1, t5
#if 0
la t2, RALINK_SYSCFG0_REG
lw t3, 0(t0)
addiu t4, zero, 0x1
sll t3, t3, 6
and t3, t3, t4
li t5, ~(1<<15)
and t1, t1, t5
li t5, 1<<15
movz t5, zero, t3 /* t3=0, XTAL=20Mhz */
or t1, t1, t5
#endif
la t0, RALINK_CPLLCFG0_REG
sw t1, 0(t0)
nop
/* Power up CPU PLL */
la t0, RALINK_CPLLCFG1_REG
lw t1, 0(t0)
li t2, ~(1<<26)
and t1, t1, t2
sw t1, 0(t0)
nop
/* Polling CPU PLL PD Signal */
la t0, RALINK_CPLLCFG1_REG
li t2, 1<<23
1:
lw t1, 0(t0)
nop
and t1, t1, t2
beqz t1, 1b
nop
/* Switch clock source from CPU_CLK_AUX0/AUX1 to CPU PLL */
la t0, RALINK_CPLLCFG1_REG
lw t1, 0(t0)
li t2, ~(0x3<<24)
and t1, t1, t2
sw t1, 0(t0)
nop
CPLL_EXIT:
jr ra
.end init_cpu_pll
/**********************************************************/
#if defined(MT7620_ASIC_BOARD) || defined(MT7628_ASIC_BOARD)
.text
.global SDR_CFG0_TBL
.align 3
SDR_CFG0_TBL:
/* 150MHZ */ /* 120MHZ */
.word 0x12A263A3, 0x12825282
.word 0x12A263A3, 0x12825282
.word 0x129263A3, 0x12825282
.word 0x11A263A3, 0x11825282
.text
.global SDR_CFG1_TBL
.align 3
SDR_CFG1_TBL:
/* 150MHZ */ /* 120MHZ */
.word 0xF80108E8, 0xF801073F /* 8MB */
.word 0xF81108E8, 0xF811073F /* 16MB */
.word 0xF8120475, 0xF812039F /* 32MB */
.word 0xF8220475, 0xF822039F /* 64MB */
.text
.global DDR1_CFG0_TBL
.align 3
DDR1_CFG0_TBL:
/* 200MHZ */ /* 160MHZ */
.word 0x34A1EB94, 0x239964A1 /* 8MB */
.word 0x34A1EB94, 0x239964A1 /* 16MB */
.word 0x34A1E5CA, 0x239964A1 /* 32MB */
.word 0x3421E5CA, 0x239984A1 /* 64MB */
.word 0x241B05CA, 0x239AB4A1 /* 128MB */
.text
.global DDR1_CFG1_TBL
.align 3
DDR1_CFG1_TBL:
/* 200MHZ */ /* 160MHZ */
.word 0x20262324, 0x20262323 /* 8MB */
.word 0x202A2324, 0x202A2323 /* 16MB */
.word 0x202E2324, 0x202E2323 /* 32MB */
.word 0x20322324, 0x20322323 /* 64MB */
.word 0x20362334, 0x20362333 /* 128MB */
.text
.align 3
/* 200MHZ */ /* 160MHZ */
DDR1_CFG2_TBL:
.word 0x28000033, 0x00000033
.word 0x28000033, 0x00000033
.word 0x28000033, 0x00000033
.word 0x28000033, 0x00000033
.word 0x28000033, 0x00000033
DDR1_CFG3_TBL:
.word 0x00000002, 0x00000002
.word 0x00000002, 0x00000002
.word 0x00000002, 0x00000002
.word 0x00000002, 0x00000002
.word 0x00000002, 0x00000002
DDR1_CFG4_TBL:
.word 0x00000000, 0x00000000
.word 0x00000000, 0x00000000
.word 0x00000000, 0x00000000
.word 0x00000000, 0x00000000
.word 0x00000000, 0x00000000
.text
.global DDR2_CFG0_TBL
.align 3
DDR2_CFG0_TBL:
/* 200MHZ */ /* 160MHZ */
.word 0x2519E2E5, 0x23918250 /* 32MB */
.word 0x249AA2E5, 0x239A2250 /* 64MB */
.word 0x249B42E5, 0x2392A250 /* 128MB */
.word 0x249CE2E5, 0x24140250 /* 256MB */
.text
.global DDR2_CFG1_TBL
.align 3
DDR2_CFG1_TBL:
/* 200MHZ */ /* 160MHZ */
.word 0x222E2323, 0x222E2322 /* 32MB */
.word 0x22322323, 0x22322322 /* 64MB */
.word 0x22362323, 0x22362322 /* 128MB */
.word 0x223A2323, 0x223A2322 /* 256MB */
.text
.align 3
/* 200MHZ */ /* 160MHZ */
DDR2_CFG2_TBL:
.word 0x68000C43, 0x40000A43
.word 0x68000C43, 0x40000A43
.word 0x68000C43, 0x40000A43
.word 0x68000C43, 0x40000A43
.text
.align 3
DDR2_CFG3_TBL:
#if defined(MT7628_ASIC_BOARD)
/* 200MHZ */ /* 160MHZ */
.word 0x00000452, 0x00000452
.word 0x00000452, 0x00000452
.word 0x00000452, 0x00000452
.word 0x00000452, 0x00000452
#else
/* 200MHZ */ /* 160MHZ */
.word 0x00000416, 0x00000416
.word 0x00000416, 0x00000416
.word 0x00000416, 0x00000416
.word 0x00000416, 0x00000416
#endif
.text
.align 3
DDR2_CFG4_TBL:
/* 200MHZ */ /* 160MHZ */
.word 0x0000000A, 0x00000006
.word 0x0000000A, 0x00000008
.word 0x0000000A, 0x00000008
.word 0x0000000A, 0x00000008
#endif
/**********************************************************/
#endif
#if defined(RT6855A_ASIC_BOARD)
.text
.global SDR_CFG0_TBL
.align 3
SDR_CFG0_TBL:
/* 140MHZ */ /* 105MHZ */
.word 0x11925282, 0x11623161
.text
.global SDR_CFG1_TBL
.align 3
SDR_CFG1_TBL:
/* 140MHZ */ /* 105MHZ */
.word 0x8000088B, 0x80000668 /* 2MB */
.word 0x8001088B, 0x80010668 /* 8MB */
.word 0x8011088B, 0x80110668 /* 16MB */
.word 0x80120445, 0x80120334 /* 32MB */
.text
.global DDR1_CFG0_TBL
.align 3
DDR1_CFG0_TBL:
/* 233MHZ */ /* 175MHZ */ /* 166MHZ */ /* 125MHZ */
.word 0x352A2E34, 0x3421AAAF, 0x23998A20, 0x2319279E /* 8MB */
.word 0x352A2E34, 0x3421AAAF, 0x23998A20, 0x2319279E /* 16MB */
.word 0x352A271A, 0x3421A558, 0x2399850E, 0x231923CF /* 32MB */
.word 0x352A271A, 0x3421A558, 0x2399850E, 0x231923CF /* 64MB */
.text
.global DDR1_CFG1_TBL
.align 3
DDR1_CFG1_TBL:
/* 233MHZ */ /* 175MHZ */ /* 166MHZ */ /* 125MHZ */
.word 0x20262424, 0x20262324, 0x20262323, 0x20262223 /* 8MB */
.word 0x202A2424, 0x202A2324, 0x202A2323, 0x202A2223 /* 16MB */
.word 0x202E2424, 0x202E2324, 0x202E2323, 0x202E2223 /* 32MB */
.word 0x20322424, 0x20322324, 0x20322323, 0x20322223 /* 64MB */
.text
.align 3
/* 233MHZ */ /* 175MHZ */ /* 166MHZ */ /* 125MHZ */
DDR1_CFG2_TBL:
.word 0x00000033, 0x00000033, 0x00000033, 0x00000063
DDR1_CFG3_TBL:
.word 0x00000000, 0x00000000, 0x00000000, 0x00000002
DDR1_CFG4_TBL:
.word 0x00000000, 0x00000000, 0x00000000, 0x00000000
.text
.global DDR2_CFG0_TBL
.align 3
DDR2_CFG0_TBL:
/* 233MHZ */ /* 175MHZ */ /* 166MHZ */ /* 125MHZ */
.word 0x35A2438D, 0x2419C2AB, 0x2419A287, 0x231941E7 /* 32MB */
.word 0x35A3238D, 0x241A62AB, 0x241A4287, 0x2319C1E7 /* 64MB */
.word 0x35A3C38D, 0x241AE2AB, 0x241AC287, 0x231A01E7 /* 128MB */
.word 0x35A5E38D, 0x241C62AB, 0x241C2287, 0x231B21E7 /* 256MB */
.text
.global DDR2_CFG1_TBL
.align 3
DDR2_CFG1_TBL:
/* 233MHZ */ /* 175MHZ */ /* 166MHZ */ /* 125MHZ */
.word 0x222E2424, 0x222E2324, 0x222E2324, 0x212E2223 /* 32MB */
.word 0x22322424, 0x22322324, 0x22322324, 0x21322223 /* 64MB */
.word 0x22362424, 0x22362324, 0x22362324, 0x21362223 /* 128MB */
.word 0x223A2424, 0x223A2324, 0x223A2324, 0x213A2223 /* 256MB */
.text
.align 3
/* 233MHZ */ /* 175MHZ */ /* 166MHZ */ /* 125MHZ */
DDR2_CFG2_TBL:
.word 0x68000E43, 0x40000C43, 0x40000C43, 0x40000843
DDR2_CFG3_TBL:
.word 0x10000400, 0x00000400, 0x00000402, 0x00000402
DDR2_CFG4_TBL:
.word 0x0010080C, 0x0000000B, 0x0000000B, 0x0000000B
#endif
#if (TEXT_BASE == 0xBFC00000) || (TEXT_BASE == 0xBF000000) || (TEXT_BASE == 0xBC000000)
#if defined (CONFIG_DDR_CAL)
/* === lock d$ === */
.globl lock_dcache
.ent lock_dcache
lock_dcache:
lui $14, 0x8900 # Get a KSeg0 address for cacheops
move $12, $14
li $10, 4
2:
# Set TagLo registers
li $13, 0x1FFFF800
and $13, $13, $12
ori $13, $13, (0x1<<5)|(0x1<<7)
mtc0 $13, $28, 2
move $9, $12
li $15, 64
li $11, 32
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x9, 0($9)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $9, $11 # Get next line address
addiu $12, 0x800
subu $10, 1
bgtz $10, 2b
nop
jr ra
nop
jr ra
nop
.end lock_dcache
/* === unlock d$ === */
.globl unlock_dcache
.ent unlock_dcache
unlock_dcache:
lui $14, 0x8000 # Get a KSeg0 address for cacheops
move $12, $14
li $10, 4
2:
# Clear TagLo/TagHi registers
mtc0 $0, $28, 2
move $9, $12
li $15, 64
li $11, 32
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0x9, 0($9)
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $9, $11 # Get next line address
subu $10, 1
bgtz $10, 2b
nop
jr ra
nop
.end unlock_dcache
/* === fill I$ === */
.globl fill_icache
.ent fill_icache
fill_icache:
lui $14, %hi(dram_cali) # Get a KSeg0 address for cacheops
addiu $14, %lo(dram_cali)
li $13, 0xDFFFFFFF
and $13, $13, $14
li $15, 512
li $11, 32
# Fill Cache Op
1: cache 0x14, 0($13)
add $15, -1 # Decrement set counter
nop
bne $15, $0, 1b
add $13, $11 # Get next line address
jr ra
nop
.end fill_icache
#endif
#endif
|
MediaTek-Labs/linkit-smart-7688-uboot | 6,388 | cpu/ralink_soc/cache.S | /*
* Cache-handling routined for MIPS 4K CPUs
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
/* 16KB is the maximum size of instruction and data caches on
* MIPS 4K.
*/
#define MIPS_MAX_CACHE_SIZE 0x4000
/*
* cacheop macro to automate cache operations
* first some helpers...
*/
#define _mincache(size, maxsize) \
bltu size,maxsize,9f ; \
move size,maxsize ; \
9:
#define _align(minaddr, maxaddr, linesize) \
.set noat ; \
subu AT,linesize,1 ; \
not AT ; \
and minaddr,AT ; \
addu maxaddr,-1 ; \
and maxaddr,AT ; \
.set at
/* general operations */
#define doop1(op1) \
cache op1,0(a0)
#define doop2(op1, op2) \
cache op1,0(a0) ; \
nop ; \
cache op2,0(a0)
/* specials for cache initialisation */
#define doop1lw(op1) \
lw zero,0(a0)
#define doop1lw1(op1) \
cache op1,0(a0) ; \
lw zero,0(a0) ; \
cache op1,0(a0)
#define doop121(op1,op2) \
cache op1,0(a0) ; \
nop; \
cache op2,0(a0) ; \
nop; \
cache op1,0(a0)
#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
.set noreorder ; \
10: doop##tag##ops ; \
bne minaddr,maxaddr,10b ; \
add minaddr,linesize ; \
.set reorder
/* finally the cache operation macros */
#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
blez n,11f ; \
addu n,kva ; \
_align(kva, n, cacheLineSize) ; \
_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:
#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
_mincache(n, cacheSize); \
blez n,11f ; \
addu n,kva ; \
_align(kva, n, cacheLineSize) ; \
_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:
#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
/*******************************************************************************
*
* mips_cache_reset - low level initialisation of the primary caches
*
* This routine initialises the primary caches to ensure that they
* have good parity. It must be called by the ROM before any cached locations
* are used to prevent the possibility of data with bad parity being written to
* memory.
* To initialise the instruction cache it is essential that a source of data
* with good parity is available. This routine
* will initialise an area of memory starting at location zero to be used as
* a source of parity.
*
* RETURNS: N/A
*
*/
.globl mips_cache_reset
.ent mips_cache_reset
mips_cache_reset:
li t2, CFG_ICACHE_SIZE
li t3, CFG_DCACHE_SIZE
li t4, CFG_CACHELINE_SIZE
move t5, t4
#if 1
li v0, MIPS_MAX_CACHE_SIZE
/* Now clear that much memory starting from zero.
*/
li a0, KSEG1
addu a1, a0, v0
2: sw zero, 0(a0)
sw zero, 4(a0)
sw zero, 8(a0)
sw zero, 12(a0)
sw zero, 16(a0)
sw zero, 20(a0)
sw zero, 24(a0)
sw zero, 28(a0)
addu a0, 32
bltu a0, a1, 2b
nop
#endif
/* Set invalid tag.
*/
mtc0 zero, CP0_TAGLO
/*
* The caches are probably in an indeterminate state,
* so we force good parity into them by doing an
* invalidate, load/fill, invalidate for each line.
*/
/* Assume bottom of RAM will generate good parity for the cache.
*/
li a0, K0BASE
move a2, t2 # icacheSize
move a3, t4 # icacheLineSize
move a1, a2
icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill))
nop
/* To support Orion/R4600, we initialise the data cache in 3 passes.
*/
/* 1: initialise dcache tags.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
nop
/* 2: fill dcache.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheopn(a0,a1,a2,a3,1lw,(dummy))
nop
/*
3: clear dcache tags.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
nop
j ra
nop
nop
.end mips_cache_reset
/*******************************************************************************
*
* dcache_status - get cache status
*
* RETURNS: 0 - cache disabled; 1 - cache enabled
*
*/
.globl dcache_status
.ent dcache_status
dcache_status:
mfc0 v0, CP0_CONFIG
andi v0, v0, 1
j ra
.end dcache_status
/*******************************************************************************
*
* dcache_disable - disable cache
*
* RETURNS: N/A
*
*/
.globl dcache_disable
.ent dcache_disable
dcache_disable:
mfc0 t0, CP0_CONFIG
li t1, -8
and t0, t0, t1
ori t0, t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
j ra
.end dcache_disable
/*******************************************************************************
*
* mips_cache_lock - lock RAM area pointed to by a0 in cache.
*
* RETURNS: N/A
*
*/
#if defined(CONFIG_PURPLE)
# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
#else
# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
#endif
.globl mips_cache_lock
.ent mips_cache_lock
mips_cache_lock:
j KAIKER_0
nop
nop
KAIKER_0:
li a1, K0BASE - CACHE_LOCK_SIZE
addu a0, a1
li a2, CACHE_LOCK_SIZE
li a3, CFG_CACHELINE_SIZE
move a1, a2
j KAIKER_1
nop
nop
KAIKER_1:
j KAIKER_11
nop
nop
KAIKER_11:
icacheop(a0,a1,a2,a3,0x1D)
j KAIKER_2
nop
nop
KAIKER_2:
j ra
.end mips_cache_lock
|
MediaTek-Labs/linkit-smart-7688-uboot | 61,513 | cpu/ralink_soc/start_1004k.S | #include <config.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <rt_mmap.h>
#include <sysdefs.h>
#include <ArchDefs.h>
#include <launch.h>
#define CODE_ALIGN .align 2
#define LEAF(name)\
.##text;\
.##globl name;\
.##ent name;\
name:
#define END(name)\
.##size name,.-name;\
.##end name
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
#define CONFIG_SYS_INIT_SP_OFFSET CFG_INIT_SP_OFFSET
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
#define WAITCODE_IN_RAM 0xA0000D00
#define GIC_SHARED_OFS 0xBFBC0000
#define GIC_SH_WEDGE (GIC_SHARED_OFS | 0x0280)
#define GIC_LOCAL_OFS (GIC_SHARED_OFS | 0x8000)
#define GCR_CONFIG 0xbfbf8000
#define GCR_GIC_BASE 0xbfbf8080
#define GCR_GIC_BASE_VALUE 0x1fbc0000
#define GCR_GIC_STATUS 0xbfbf80d0
#define GCR_CPC_BASE 0xbfbf8088
#define GCR_CPC_STATUS 0xbfbf80f0
#define MALTA_DISP_ADDR 0xbf000410
#define STACK_BASE_ADDR CONFIG_SYS_SDRAM_BASE + CFG_INIT_SP_OFFSET /* fixme: Base on memory size. */
#define STACK_SIZE_LOG2 22 /* 4Mbytes each */
#define CPC_GLOBAL_OFS 0xbfbf0000 /* CPC base address */
#define GCR_CPC_BASE_VALUE 0x1fbf0000 /* CPC base address value */
#define GCR_REG0_BASE_VALUE 0x1c000000 /* CM region 0 base address value */
#define GCR_REG1_BASE_VALUE 0x60000000 /* CM region 1 base address value */
#define GCR_REG2_BASE_VALUE 0x1c000000 /* CM region 2 base address value */
#define GCR_REG3_BASE_VALUE 0x1c000000 /* CM region 3 base address value */
#define GCR_REG0_MASK_VALUE 0x0000fc00 /* CM region 0 mask value 64M */
#define GCR_REG1_MASK_VALUE 0x0000f000 /* CM region 1 mask value 256M */
#define GCR_REG2_MASK_VALUE 0x0000fc00 /* CM region 2 mask value 64M */
#define GCR_REG3_MASK_VALUE 0x0000fc00 /* CM region 3 mask value 64M */
#define RVECENT(f,n) \
b f; nop
#define XVECENT(f,bev) \
b f ; \
li k0,bev
.set noreorder
.globl _start
.text
_start:
RVECENT(reset,0) # U-boot entry point
RVECENT(reset,1) # software reboot
RVECENT(romReserved,2)
RVECENT(romReserved,3)
RVECENT(romReserved,4)
RVECENT(romReserved,5)
RVECENT(romReserved,6)
RVECENT(romReserved,7)
RVECENT(romReserved,8)
RVECENT(romReserved,9)
RVECENT(romReserved,10)
RVECENT(romReserved,11)
RVECENT(romReserved,12)
RVECENT(romReserved,13)
RVECENT(romReserved,14)
RVECENT(romReserved,15)
RVECENT(romReserved,16)
RVECENT(romReserved,17)
RVECENT(romReserved,18)
RVECENT(romReserved,19)
RVECENT(romReserved,20)
RVECENT(romReserved,21)
RVECENT(romReserved,22)
RVECENT(romReserved,23)
RVECENT(romReserved,24)
RVECENT(romReserved,25)
RVECENT(romReserved,26)
RVECENT(romReserved,27)
RVECENT(romReserved,28)
RVECENT(romReserved,29)
RVECENT(romReserved,30)
RVECENT(romReserved,31)
RVECENT(romReserved,32)
RVECENT(romReserved,33)
RVECENT(romReserved,34)
RVECENT(romReserved,35)
RVECENT(romReserved,36)
RVECENT(romReserved,37)
RVECENT(romReserved,38)
RVECENT(romReserved,39)
RVECENT(romReserved,40)
RVECENT(romReserved,41)
RVECENT(romReserved,42)
RVECENT(romReserved,43)
RVECENT(romReserved,44)
RVECENT(romReserved,45)
RVECENT(romReserved,46)
RVECENT(romReserved,47)
RVECENT(romReserved,48)
RVECENT(romReserved,49)
RVECENT(romReserved,50)
RVECENT(romReserved,51)
RVECENT(romReserved,52)
RVECENT(romReserved,53)
RVECENT(romReserved,54)
RVECENT(romReserved,55)
RVECENT(romReserved,56)
RVECENT(romReserved,57)
RVECENT(romReserved,58)
RVECENT(romReserved,59)
RVECENT(romReserved,60)
RVECENT(romReserved,61)
RVECENT(romReserved,62)
RVECENT(romReserved,63)
XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector
RVECENT(romReserved,65)
RVECENT(romReserved,66)
RVECENT(romReserved,67)
RVECENT(romReserved,68)
RVECENT(romReserved,69)
RVECENT(romReserved,70)
RVECENT(romReserved,71)
RVECENT(romReserved,72)
RVECENT(romReserved,73)
RVECENT(romReserved,74)
RVECENT(romReserved,75)
RVECENT(romReserved,76)
RVECENT(romReserved,77)
RVECENT(romReserved,78)
RVECENT(romReserved,79)
XVECENT(romExcHandle,0x280) # bfc00280: R4000 xtlbmiss vector
RVECENT(romReserved,81)
RVECENT(romReserved,82)
RVECENT(romReserved,83)
RVECENT(romReserved,84)
RVECENT(romReserved,85)
RVECENT(romReserved,86)
RVECENT(romReserved,87)
RVECENT(romReserved,88)
RVECENT(romReserved,89)
RVECENT(romReserved,90)
RVECENT(romReserved,91)
RVECENT(romReserved,92)
RVECENT(romReserved,93)
RVECENT(romReserved,94)
RVECENT(romReserved,95)
XVECENT(romExcHandle,0x300) # bfc00300: R4000 cache vector
RVECENT(romReserved,97)
RVECENT(romReserved,98)
RVECENT(romReserved,99)
RVECENT(romReserved,100)
RVECENT(romReserved,101)
RVECENT(romReserved,102)
RVECENT(romReserved,103)
RVECENT(romReserved,104)
RVECENT(romReserved,105)
RVECENT(romReserved,106)
RVECENT(romReserved,107)
RVECENT(romReserved,108)
RVECENT(romReserved,109)
RVECENT(romReserved,110)
RVECENT(romReserved,111)
XVECENT(romExcHandle,0x380) # bfc00380: R4000 general vector
RVECENT(romReserved,113)
RVECENT(romReserved,114)
RVECENT(romReserved,115)
RVECENT(romReserved,116)
RVECENT(romReserved,116)
RVECENT(romReserved,118)
RVECENT(romReserved,119)
RVECENT(romReserved,120)
RVECENT(romReserved,121)
RVECENT(romReserved,122)
RVECENT(romReserved,123)
RVECENT(romReserved,124)
RVECENT(romReserved,125)
RVECENT(romReserved,126)
RVECENT(romReserved,127)
/*
* We hope there are no more reserved vectors!
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
.align 4
reset:
b __reset_vector
nop
/**************************************************************************************
Register use while executing in this file: ("GLOBAL" denotes a common value.)
**************************************************************************************/
#define r1_all_ones $1 /* Will hold 0xffffffff to simplify bit insertion of 1's. GLOBAL! */
#define r2_has_mt_ase $2 /* Core implements the MT ASE. */
#define r3_is_cps $3 /* Core is part of a Coherent Processing System. */
#define r4_temp_data $4 /* scratch, eventually the 1st param for main (a0.) */
#define r5_temp_addr $5 /* scratch, eventually the 2nd param for main (a1.) */
#define r6_temp_dest $6 /* scratch, eventually the 3rd param for main (a2.) */
#define r7_temp_mark $7 /* scratch, eventually the 4th param for main (a3.) */
#define r16_core_num $16 /* Core number. Only core 0 is active after reset. */
#define r17_vpe_num $17 /* MT ASE VPE number that this TC is bound to (0 if non-MT.) */
#define r18_tc_num $18 /* MT ASE TC number (0 if non-MT.) */
#define r19_more_cores $19 /* Number of cores in CPS addition to core 0. GLOBAL! */
#define r20_more_vpes $20 /* Number of vpes in this core in addition to vpe 0. */
#define r21_more_tcs $21 /* Number of tcs in vpe in addition to the first. */
#define r22_gcr_addr $22 /* Uncached (kseg1) base address of the Global Config Registers. */
#define r23_cpu_num $23 /* Unique per vpe "cpu" identifier (CP0 EBase[CPUNUM]). */
#define r24_malta_word $24 /* Uncached (kseg1) base address of Malta ascii display. GLOBAL! */
#define r25_coreid $25 /* Copy of cp0 PRiD GLOBAL! */
#define r26_int_addr $26 /* Interrupt handler scratch address. */
#define r27_int_data $27 /* Interrupt handler scratch data. */
#define r28_global_addr $28 /* Common Address of shared/coherent globals. GLOBAL! */
#define r29_stack_addr $29 /* Unique per vpe stack pointer. */
#define r30_cpc_addr $30 /* Address of CPC register block after cpc_init. 0 indicates no CPC. */
#define r31_return_addr $31 /* Return address for linked branches. */
.macro set_tag TAG_X
#ifdef USE_PIO_DBG
.set noat
la r5_temp_addr, RALINK_PIO_BASE
lw r4_temp_data, 0x20(r5_temp_addr)
li r7_temp_mark, ~((0x7<<6)|(0x1))
and r4_temp_data, r4_temp_data, r7_temp_mark
li r7_temp_mark, ((((\TAG_X)>>1)<<6)|((\TAG_X)&0x1))
or r4_temp_data, r4_temp_data, r7_temp_mark
sw r4_temp_data, 0x20(r5_temp_addr)
.set at
#endif
.endm
/**************************************************************************************
R E S E T E X C E P T I O N H A N D L E R
**************************************************************************************/
.set noreorder # Don't allow the assembler to reorder instructions.
.set noat # Don't allow the assembler to use r1(at) for synthetic instr.
LEAF(__reset_vector)
b check_nmi # Note: Real systems might want to save/dump full context.
mtc0 $0, $9 # Clear cp0 Count (Used to measure boot time.)
# Note: adding code here may conflict with Malta board ID register at 0xbfc0010.
END(__reset_vector)
/**************************************************************************************
B O O T E X C E P T I O N H A N D L E R S
**************************************************************************************/
check_nmi: # Verify we are here due to a reset (and not NMI.)
#if 0 //example code if you need to use LED (GPIO0) to debug some issue.
la t0, 0xbe000600
li t9, 1
sw t9, 0(t0) /* output */
sw t9, 0x40(t0) /* low */
#endif
#ifdef USE_PIO_DBG
la r5_temp_addr, RALINK_PIO_BASE
lw r4_temp_data, 0(r5_temp_addr)
li r7_temp_mark, ~(0x1<<5)
and r4_temp_data, r4_temp_data, r7_temp_mark
li r7_temp_mark, (0x7<<6)|(0x1)
or r4_temp_data, r4_temp_data, r7_temp_mark //output
sw r4_temp_data, 0(r5_temp_addr)
lw r4_temp_data, 0x10(r5_temp_addr)
li r7_temp_mark, ~((0x7<<6)|0x1)
and r4_temp_data, r4_temp_data, r7_temp_mark //not invert
sw r4_temp_data, 0x10(r5_temp_addr)
set_tag 0x0
// USE GPIO0, 6,7,8
la r5_temp_addr, RALINK_GPIOMODE_REG
lw r4_temp_data, 0(r5_temp_addr)
li r7_temp_mark, ~(0x3<<3) //~(0x3<<18)
and r4_temp_data, r4_temp_data, r7_temp_mark
sw r4_temp_data, 0(r5_temp_addr)
#endif
set_tag 0x01
#if 0 // set GPIO19(PERST_N) to output mode and pull low
li t0, 0xbe000600
lw t1, 0(t0)
li t2, 1<<19
or t1, t1, t2
sw t1, 0(t0)
li t0, 0xbe000620
lw t1, 0(t0)
li t2, ~(1<<19)
and t1, t1, t2
sw t1, 0(t0)
#endif
mfc0 r4_temp_data, $12 # Read CP0 Status
srl r4_temp_data, 19 # Shift [NMI] into LSBs.
andi r4_temp_data, r4_temp_data, 1 # Inspect CP0 Config[AT]
beqz r4_temp_data, verify_isa # Branch if this is NOT an NMI exception.
nop
sdbbp # Failed assertion: not NMI.
verify_isa: # Verify device ISA meets code requirements (MIPS32 r2 or later.)
mfc0 r4_temp_data, $16 # Read CP0 Config
srl r4_temp_data, 10 # Shift [AT AR] into LSBs.
andi r7_temp_mark, r4_temp_data, 0x18 # Inspect CP0 Config[AT]
beqz r7_temp_mark, is_mips32 # Branch if executing on MIPS32 ISA.
andi r7_temp_mark, r4_temp_data, 0x07 # Inspect CP0 Config[AR]
sdbbp # Failed assertion: mips32.
is_mips32:
bnez r7_temp_mark, init_vpe_resources # Continue if ISA is MIPS32r2 or later.
nop
sdbbp # Failed assertion mips32r2.
/**************************************************************************************
What is initialized on execution depends on the core/vpe executing it.
(A non-MT device is treated as tc0/vpe0, non-CMP device is treated as core0.)
**************************************************************************************/
init_vpe_resources: # Every "cpu"(vpe) initializes per-vpe resources.
bal init_gpr # Fill register file with dummy value then boot info.
nop
bal init_cp0 # Init CP0 Status, Count, Compare, Watch*, and Cause.
nop
bal init_tlb # Generate unique EntryHi contents per entry pair.
nop
bal init_gic # Configure the global interrupt controller.
nop
bnez r17_vpe_num, init_done # If we are not a vpe0 then we are done.
nop
bnez r16_core_num, init_core_resources # Only core0/vpe0 needs to init systems resources.
nop
set_tag 0x02
init_sys_resources: # We are core0 vpe0.
bal init_cpc # Initialize the CPS CPC (Cluster Power Controller.)
nop
bal init_cm # Initialize the CPS CM (Coherency Manager.)
nop
bal init_mc # Initialize the ROC-it2 MC (Memory Controller.)
nop
bal init_l23u # Initialize the unified L2 and L3 caches (if CCA Override is not available.)
nop
#if 0 //MTK: not used
bal copy_c2_ram # Copy "C" code and data to RAM and zero bss (uncached.)
nop
#endif
bal release_mp # Release other cores to execute this boot code.
nop
set_tag 0x03
init_core_resources: # We are a vpe0.
bal init_icache # Initialize the L1 instruction cache. (Executing using I$ on return.)
nop
set_tag 0x04
bal init_dcache # Initialize the L1 data cache
nop
bal init_l23c # Initialize the unified L2 and L3 caches (if CCA Override is available).
nop
#if 0 // MTK: no thread
bal init_itc # Initialize Inter-Thread Communications unit
nop
#endif
bal join_domain # Join the coherent domain. (OK to use D$ on return.)
nop
#ifdef RALINK_DUAL_VPE_FUN
bal init_vpe1 # Set up MT ASE vpe1 to execute this boot code also.
nop
#endif
init_done:
set_tag 0x05
#if 0 //ignore main
# Prepare for eret to main (sp and gp set up per vpe in init_gpr).
la r31_return_addr, all_done # If main return then go to all_done:.
la r5_temp_addr, main
mtc0 r5_temp_addr, $30 # ErrorEPC
# Prepare arguments for main()
move r4_temp_data, r23_cpu_num # main(arg0) is the "cpu" number (cp0 EBase[CPUNUM].)
move r5_temp_addr, r16_core_num # main(arg1) is the core number.
move r6_temp_dest, r17_vpe_num # main(arg2) is the vpe number.
addiu r7_temp_mark, r20_more_vpes, 1 # main(arg3) is the number of vpe on this core.
eret # Exit reset exception handler for this vpe and start execution of main().
#endif
/**************************************************************************************
**************************************************************************************/
all_done:
notmtcapable:
/*
* MIPSCMP
* Only Core0 carries on from here
* Everybody else waits...
*/
beqz r23_cpu_num,finish_initialisation
nop
othercores:
/* FIXME any other per-CPU initialisation required? */
li t0,KSEG0(CPULAUNCH)
sll t1,r23_cpu_num, LOG2CPULAUNCH
addu t0,t1
/*
* Set CPU online flag
*/
lw t1,LAUNCH_FLAGS(t0)
andi t1, 0
or t1,LAUNCH_FREADY
sw t1,LAUNCH_FLAGS(t0)
/* enable count interrupt in mask, but don't enable interrupts */
mfc0 t2,C0_Status
li t1,M_StatusIM7 /* FIXME should calculate dynamically from Config3.ippti */
or t1,t2
mtc0 t1,C0_Status
li t9, WAITCODE_IN_RAM
jr t9
nop
CODE_ALIGN
waitcode_start:
/*
* Poll CPU go flag
*/
1:
mfc0 t1,C0_Count
addu t1,LAUNCHPERIOD
mtc0 t1,C0_Compare
swwait: /* Software wait */
mfc0 t4,C0_Count
subu t4,t1
bltz t4,swwait
nop
b checklaunch
nop
checklaunch:
lw t1,LAUNCH_FLAGS(t0)
and t1,LAUNCH_FGO
beqz t1, 1b
nop
/* Reset the counter and interrupts to give naive clients a chance */
mtc0 t2,C0_Status
mfc0 t2,C0_Count
subu t2,1
mtc0 t2,C0_Compare
/* we're off */
lw t2,LAUNCH_PC(t0)
lw gp,LAUNCH_GP(t0)
lw sp,LAUNCH_SP(t0)
lw a0,LAUNCH_A0(t0)
move a1,zero
move a2,zero
move a3,zero
ori t1,LAUNCH_FGONE
jr t2
sw t1,LAUNCH_FLAGS(t0)
CODE_ALIGN
waitcode_end:
finish_initialisation:
/* Set up temporary stack */
li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
la sp, 0(t0)
set_tag 0x06
lui t9, %hi(board_init_f)
addiu t9, %lo(board_init_f)
jr t9
nop
/**************************************************************************************
**************************************************************************************/
init_gpr:
# Initialize the general purpose registers and any shadow register sets.
# Although not necessary, register initialization may be useful during boot,
# debug, and simulation when certain ways of initializing registers may not work
# (xor rN, rN, rN for example.)
# Initialize register sets
li $1, 0x0 # (0x0 stands out, kseg2 mapped, odd.)
# Determine how many shadow sets are implemented (in addition to the base register set.)
mfc0 $29, $12, 2 # C0_SRSCtl
ext $30, $29, 26, 4 # S_SRSCtlHSS, W_SRSCtlHSS
next_shadow_set:
# set PSS to shadow set to be initialized
ins $29, $30, 6, 4 # S_SRSCtlPSS, W_SRSCtlPSS
mtc0 $29, $12, 2 # C0_SRSCtl
wrpgpr $1, $1
wrpgpr $2, $1
wrpgpr $3, $1
wrpgpr $4, $1
wrpgpr $5, $1
wrpgpr $6, $1
wrpgpr $7, $1
wrpgpr $8, $1
wrpgpr $9, $1
wrpgpr $10, $1
wrpgpr $11, $1
wrpgpr $12, $1
wrpgpr $13, $1
wrpgpr $14, $1
wrpgpr $15, $1
wrpgpr $16, $1
wrpgpr $17, $1
wrpgpr $18, $1
wrpgpr $19, $1
wrpgpr $20, $1
wrpgpr $21, $1
wrpgpr $22, $1
wrpgpr $23, $1
wrpgpr $24, $1
wrpgpr $25, $1
wrpgpr $26, $1
wrpgpr $27, $1
wrpgpr $28, $1
wrpgpr $29, $1
beqz $30, set_gpr_boot_values
wrpgpr $30, $1
wrpgpr $31, $1 # Don't clobber $31 in set0. Used as r31_return_addr by bal to this code.
b next_shadow_set
add $30, -1
set_gpr_boot_values:
li r1_all_ones, 0xffffffff # Simplify code and improve clarity
mfc0 r4_temp_data, $15, 1 # Read CP0 EBase
ext r23_cpu_num, r4_temp_data, 0, 4 # Extract CPUNum
li r24_malta_word, MALTA_DISP_ADDR # Need for reporting failed assertions.
lui r28_global_addr, %hi(_gp) # All vpe share globals.
addiu r28_global_addr, %lo(_gp)
li r29_stack_addr, STACK_BASE_ADDR # Each vpe gets it's own stack.
ins r29_stack_addr, r23_cpu_num, STACK_SIZE_LOG2, 3
check_mt_ase:
mfc0 r4_temp_data, $16, 1 # C0_Config1
bgez r4_temp_data, no_mt_ase # No Config2 register
mfc0 r4_temp_data, $16, 2 # C0_Config2
bgez r4_temp_data, no_mt_ase # No Config3 register
mfc0 r4_temp_data, $16, 3 # C0_Config3
and r4_temp_data, (1 << 2) # M_Config3MT
beqz r4_temp_data, no_mt_ase
li r2_has_mt_ase, 0
has_mt_ase:
li r2_has_mt_ase, 1
# Every vpe will set up the following to simplify resource initialization.
mfc0 r4_temp_data, $2, 2 # Read CP0 TCBind
ext r17_vpe_num, r4_temp_data, 0, 4 # Extract CurVPE
ext r18_tc_num, r4_temp_data, 21, 8 # Extract CurTC
mfc0 r4_temp_data, $0, 2 # C0_MVPConf0
ext r21_more_tcs, r4_temp_data, 0, 8 # S_MVPConf0PTC, W_MVPConf0PTC (Not used by all vpe.)
b check_cps
ext r20_more_vpes, r4_temp_data, 10, 4 # S_MVPConf0PVPE, W_MVPConf0PVPE (Not used by all vpe.)
no_mt_ase: # This processor does not implement the MIPS32 MT ASE. Set up defaults.
li r17_vpe_num, 0
li r18_tc_num, 0
li r20_more_vpes, 0
li r21_more_tcs, 0
check_cps: # Determine if there is a coherency manager present. (Implementation Dependent.)
mfc0 r25_coreid, $15, 0 # CP0 PRId.
ext r4_temp_data, r25_coreid, 8, 16 # Extract Manuf and Core.
li r7_temp_mark, 0x0199 # MIPS, 1004K
beq r7_temp_mark, r4_temp_data, is_cps
li r7_temp_mark, 0x019a # MIPS, 1074K
beq r7_temp_mark, r4_temp_data, is_cps
nop
is_not_cps: # This processor is not part of a Coherent Processing System. Set up valid defaults.
li r3_is_cps, 0
li r16_core_num, 0
b done_init_gpr
li r19_more_cores, 0
is_cps:
li r3_is_cps, 1
//MTK: access 1fbf8008 will cause excption??
# Verify that we can find the GCRs.
li r5_temp_addr, GCR_CONFIG # KSEG1(GCRBASE)
lw r4_temp_data, 0x0008(r5_temp_addr) # GCR_BASE
ins r5_temp_addr, $0, 29, 3 # Convert KSEG1 to physical address.
ins r4_temp_data, $0, 0, 15 # Isolate physical base address of GCR.
beq r5_temp_addr, r4_temp_data, gcr_found
nop
sdbbp # Can't find GCR. RTL config override of MIPS default?
gcr_found:
# Every vpe will set up the following to simplify resource initialization.
li r22_gcr_addr, GCR_CONFIG
lw r16_core_num, 0x2028(r22_gcr_addr) # Load GCR_CL_ID
lw r4_temp_data, 0(r22_gcr_addr) # Load GCR_CONFIG
#ifdef RALINK_DUAL_CORE_FUN
li r5_temp_addr, RALINK_SYSCTL_BASE
lw r4_temp_data, 0x000c(r5_temp_addr) #CHIP_REV_ID
ext r19_more_cores, r4_temp_data, 17, 1
#else
li r19_more_cores, 0
#endif
done_init_gpr:
jr r31_return_addr
nop
/**************************************************************************************
**************************************************************************************/
init_cp0:
# Initialize Status
li $11, 0x00400404 # (M_StatusIM | M_StatusERL | M_StatusBEV)
mtc0 $11, $12 # C0_Status
# Initialize Watch registers if implemented.
mfc0 $10, $16, 1 # C0_Config1
ext $11, $10, 3, 1 # S_Config1WP, W_Config1WP
beq $11, $0, done_wr
li $11, 0x7 # (M_WatchHiI | M_WatchHiR | M_WatchHiW)
# Clear Watch Status bits and disable watch exceptions
mtc0 $11, $19 # C0_WatchHi0
mfc0 $10, $19 # C0_WatchHi0
bgez $10, done_wr
mtc0 $0, $18 # C0_WatchLo0
mtc0 $11, $19, 1 # C0_WatchHi1
mfc0 $10, $19, 1 # C0_WatchHi1
bgez $10, done_wr
mtc0 $0, $18, 1 # C0_WatchLo1
mtc0 $11, $19, 2 # C0_WatchHi2
mfc0 $10, $19, 2 # C0_WatchHi2
bgez $10, done_wr
mtc0 $0, $18, 2 # C0_WatchLo2
mtc0 $11, $19, 3 # C0_WatchHi3
mfc0 $10, $19, 3 # C0_WatchHi3
bgez $10, done_wr
mtc0 $0, $18, 3 # C0_WatchLo3
mtc0 $11, $19, 4 # C0_WatchHi4
mfc0 $10, $19, 4 # C0_WatchHi4
bgez $10, done_wr
mtc0 $0, $18, 4 # C0_WatchLo4
mtc0 $11, $19, 5 # C0_WatchHi5
mfc0 $10, $19, 5 # C0_WatchHi5
bgez $10, done_wr
mtc0 $0, $18, 5 # C0_WatchLo5
mtc0 $11, $19, 6 # C0_WatchHi6
mfc0 $10, $19, 6 # C0_WatchHi6
bgez $10, done_wr
mtc0 $0, $18, 6 # C0_WatchLo6
mtc0 $11, $19, 7 # C0_WatchHi7
mtc0 $0, $18, 7 # C0_WatchLo7
done_wr:
# Clear WP bit to avoid watch exception upon user code entry, IV, and software interrupts.
mtc0 $0, $13 # C0_Cause: Init AFTER init of CP0 WatchHi/Lo registers.
# Clear timer interrupt. (Count was cleared at the reset vector to allow timing boot.)
mtc0 $0, $11 # C0_Compare
# Set CCA for kseg0 to cacheable (Do not access D$ on CPS untill all cores join coherent domain.)
mfc0 $10, $16 # C0_Config
beqz r3_is_cps, set_kseg0_cca
li $11, 3 //3 # K_CacheAttrC
li $11, 5 # K_CacheAttrCCS
# Cacheable, write-back, write-allocate, coherent, read misses request Shared
set_kseg0_cca:
ins $10, $11, 0, 3 # S_ConfigK0, W_ConfigK0
mtc0 $10, $16 # C0_Config
jr r31_return_addr
nop
/**************************************************************************************
**************************************************************************************/
init_tlb: # Initialize the TLB
check_for_tlb:
# Determine if we have a TLB
mfc0 $11, $16 # C0_Config
ext $11, $11, 7, 3 # S_ConfigMT, W_ConfigMT
li $15, 0x1 # K_ConfigMT_TLBMMU
bne $11, $15, done_init_tlb
mfc0 $10, $16, 1 # C0_Config1
# Check for TLB sharing between vpe.
beqz r2_has_mt_ase, start_init_tlb
nop
beqz r17_vpe_num, start_init_tlb
mfc0 r4_temp_data, $0, 1 # MVPEControl
ext r4_temp_data, r4_temp_data, 3, 1 # MVPEControl[STLB]
bnez r4_temp_data, done_init_tlb # has MT ASE, is not vpe0, is sharing tlb so skip.
nop
start_init_tlb:
# Config1MMUSize == Number of TLB entries - 1
ext $11, $10, 25, 6 # S_Config1MMUSize, W_Config1MMUSize
mtc0 $0, $2 # C0_EntryLo0
mtc0 $0, $3 # C0_EntryLo1
mtc0 $0, $5 # C0_PageMask
mtc0 $0, $6 # C0_Wired
li $12, 0x80000000
next_tlb_entry_pair:
ins $12, r23_cpu_num, 20, 4 # test: add "cpu" number to provide cps unique entries.
mtc0 $11, $0 # C0_Index
mtc0 $12, $10 # C0_EntryHi
ehb
tlbwi
add $12, (2<<13) # Add 8K to the address to avoid TLB conflict with previous entry
bne $11, $0, next_tlb_entry_pair
add $11, -1
done_init_tlb:
jr r31_return_addr
nop
/**************************************************************************************
**************************************************************************************/
init_cpc:
beqz r3_is_cps, done_init_cpc # Skip if non-CPS.
nop
lw r4_temp_data, 0x00f0(r22_gcr_addr) # GCR_CPC_STATUS
andi r4_temp_data, 1
beqz r4_temp_data, done_init_cpc # Skip if CPC is not implemented.
move r30_cpc_addr, $0
li r4_temp_data, (GCR_CPC_BASE_VALUE | 0x1) # Locate CPC at same location YAMON does.
sw r4_temp_data, 0x0088(r22_gcr_addr) # GCR_CPC_BASE
li r30_cpc_addr, CPC_GLOBAL_OFS # Maintain address of CPC register block.
done_init_cpc:
jr r31_return_addr
nop
/**************************************************************************************
**************************************************************************************/
init_gic:
beqz r3_is_cps, done_gic # Skip if non-CPS.
nop
li r5_temp_addr, GCR_GIC_STATUS # Read GCR_GIC_STATUS
lw r4_temp_data, 0(r5_temp_addr)
ext r4_temp_data, r4_temp_data, 0, 1 # Isolate GCR_GIC_STATUS[GIC_EX].
beqz r4_temp_data, done_gic # If no gic then skip.
nop
bnez r23_cpu_num, init_vpe_gic # Only core0 vpe0 inits shared portion.
nop
li r5_temp_addr, GCR_GIC_BASE # Locate and enable GIC where YAMON does.
li r4_temp_data, (GCR_GIC_BASE_VALUE | 1)
sw r4_temp_data, 0(r5_temp_addr)
nop
# Verify gic is 8 "slices" of 8 interrupts giving 40 interrupts.
li r5_temp_addr, GIC_SHARED_OFS
lw r4_temp_data, 0(r5_temp_addr) # GIC_SH_CONFIG
ext r4_temp_data, 16, 8 # NUMINTERRUPTS (actually slices - 1)
li r7_temp_mark, 7
beq r4_temp_data, r7_temp_mark, configure_slices
nop
sdbbp # Failed assertion that gic implements 64 external interrupts.
configure_slices:
li r4_temp_data, 0x00000000
sw r4_temp_data, 0x180(r5_temp_addr) # GIC_SH_TRIG31_0 (Level trigger 0..5)
li r4_temp_data, 0x0000003F
sw r4_temp_data, 0x300(r5_temp_addr) # GIC_SH_RMASK31_0 (disable 0..5)
sw r4_temp_data, 0x100(r5_temp_addr) # GIC_SH_POL31_0 (Active High 0..5)
sw r4_temp_data, 0x380(r5_temp_addr) # GIC_SH_SMASK31_0 (enable 0..5)
# Hardcoded to set up the last 8 of 64 external interrupts (56..63) for IPI.
li r4_temp_data, 0xFF000000
sw r4_temp_data, 0x184(r5_temp_addr) # GIC_SH_TRIG63_32 (edge trigger 56..63)
sw r4_temp_data, 0x304(r5_temp_addr) # GIC_SH_RMASK63_32 (disable 56..63)
sw r4_temp_data, 0x104(r5_temp_addr) # GIC_SH_POL63_32 (Rising Edge 56..63)
sw r4_temp_data, 0x384(r5_temp_addr) # GIC_SH_SMASK63_32 (enable 56..63)
# Initialize configuration of shared interrupts
# Map interrupt source to particular pin (GIC INT6~INT31 to PIN0)
li r4_temp_data, 0x80000000 //source0 to pin0
sw r4_temp_data, 0x500(r5_temp_addr) # GIC_SH_MAP0_PIN
li r4_temp_data, 0x80000000 //source1 to pin0
sw r4_temp_data, 0x504(r5_temp_addr) # GIC_SH_MAP1_PIN
li r4_temp_data, 0x80000004 //source2 to pin4
sw r4_temp_data, 0x508(r5_temp_addr) # GIC_SH_MAP2_PIN
li r4_temp_data, 0x80000003 //source3 to pin3
sw r4_temp_data, 0x50C(r5_temp_addr) # GIC_SH_MAP3_PIN
li r4_temp_data, 0x80000000 //source4 to pin0
sw r4_temp_data, 0x510(r5_temp_addr) # GIC_SH_MAP4_PIN
li r4_temp_data, 0x80000005 //source5 to pin5
sw r4_temp_data, 0x514(r5_temp_addr) # GIC_SH_MAP5_PIN
li r4_temp_data, 0x80000001 //source56 to pin1
sw r4_temp_data, 0x5E0(r5_temp_addr) # GIC_SH_MAP56_PIN
li r4_temp_data, 0x80000001 //source57 to pin1
sw r4_temp_data, 0x5E4(r5_temp_addr) # GIC_SH_MAP57_PIN
li r4_temp_data, 0x80000001 //source58 to pin1
sw r4_temp_data, 0x5E8(r5_temp_addr) # GIC_SH_MAP58_PIN
li r4_temp_data, 0x80000001 //source59 to pin1
sw r4_temp_data, 0x5EC(r5_temp_addr) # GIC_SH_MAP59_PIN
li r4_temp_data, 0x80000002 //source60 to pin2
sw r4_temp_data, 0x5F0(r5_temp_addr) # GIC_SH_MAP60_PIN
li r4_temp_data, 0x80000002 //source61 to pin2
sw r4_temp_data, 0x5F4(r5_temp_addr) # GIC_SH_MAP61_PIN
li r4_temp_data, 0x80000002 //source62 to pin2
sw r4_temp_data, 0x5F8(r5_temp_addr) # GIC_SH_MAP62_PIN
li r4_temp_data, 0x80000002 //source63 to pin2
sw r4_temp_data, 0x5FC(r5_temp_addr) # GIC_SH_MAP63_PIN
#Interrupt map to VPE (1=vpe0, 2=vpe1, 4=vpe2, 8=vpe3)
li r4_temp_data, 1
sw r4_temp_data, 0x2000(r5_temp_addr) # GIC_SH_MAP0_VPE31_0
sw r4_temp_data, 0x2020(r5_temp_addr) # GIC_SH_MAP1_VPE31_0
sw r4_temp_data, 0x2040(r5_temp_addr) # GIC_SH_MAP2_VPE31_0
sw r4_temp_data, 0x2060(r5_temp_addr) # GIC_SH_MAP3_VPE31_0
sw r4_temp_data, 0x2080(r5_temp_addr) # GIC_SH_MAP4_VPE31_0
sw r4_temp_data, 0x20A0(r5_temp_addr) # GIC_SH_MAP5_VPE31_0
sw r4_temp_data, 0x20C0(r5_temp_addr) # GIC_SH_MAP6_VPE31_0
sw r4_temp_data, 0x20E0(r5_temp_addr) # GIC_SH_MAP7_VPE31_0
sw r4_temp_data, 0x2100(r5_temp_addr) # GIC_SH_MAP8_VPE31_0
sw r4_temp_data, 0x2120(r5_temp_addr) # GIC_SH_MAP9_VPE31_0
sw r4_temp_data, 0x2140(r5_temp_addr) # GIC_SH_MAP10_VPE31_0
sw r4_temp_data, 0x2160(r5_temp_addr) # GIC_SH_MAP11_VPE31_0
sw r4_temp_data, 0x2180(r5_temp_addr) # GIC_SH_MAP12_VPE31_0
sw r4_temp_data, 0x21A0(r5_temp_addr) # GIC_SH_MAP13_VPE31_0
sw r4_temp_data, 0x21C0(r5_temp_addr) # GIC_SH_MAP14_VPE31_0
sw r4_temp_data, 0x21E0(r5_temp_addr) # GIC_SH_MAP15_VPE31_0
sw r4_temp_data, 0x2200(r5_temp_addr) # GIC_SH_MAP16_VPE31_0
sw r4_temp_data, 0x2220(r5_temp_addr) # GIC_SH_MAP17_VPE31_0
sw r4_temp_data, 0x2240(r5_temp_addr) # GIC_SH_MAP18_VPE31_0
sw r4_temp_data, 0x2260(r5_temp_addr) # GIC_SH_MAP19_VPE31_0
sw r4_temp_data, 0x2280(r5_temp_addr) # GIC_SH_MAP20_VPE31_0
sw r4_temp_data, 0x22A0(r5_temp_addr) # GIC_SH_MAP21_VPE31_0
sw r4_temp_data, 0x22C0(r5_temp_addr) # GIC_SH_MAP22_VPE31_0
sw r4_temp_data, 0x22E0(r5_temp_addr) # GIC_SH_MAP23_VPE31_0
sw r4_temp_data, 0x2300(r5_temp_addr) # GIC_SH_MAP24_VPE31_0
sw r4_temp_data, 0x2320(r5_temp_addr) # GIC_SH_MAP25_VPE31_0
sw r4_temp_data, 0x2340(r5_temp_addr) # GIC_SH_MAP26_VPE31_0
sw r4_temp_data, 0x2360(r5_temp_addr) # GIC_SH_MAP27_VPE31_0
sw r4_temp_data, 0x2380(r5_temp_addr) # GIC_SH_MAP28_VPE31_0
sw r4_temp_data, 0x23A0(r5_temp_addr) # GIC_SH_MAP29_VPE31_0
sw r4_temp_data, 0x23C0(r5_temp_addr) # GIC_SH_MAP30_VPE31_0
sw r4_temp_data, 0x23E0(r5_temp_addr) # GIC_SH_MAP31_VPE31_0
# Direct GIC_int 56..63 to vpe 0..3
# MIPS Linux convention that last 16 interrupts implemented be set aside for IPI signaling.
# (The actual interrupts are tied low and software sends interrupts via GIC_SH_WEDGE writes.)
li r4_temp_data, 1 # vpe0 is selected for
sw r4_temp_data, 0x2700(r5_temp_addr) # GIC_SH_MAP56_VPE31_0 and
sll r4_temp_data, r4_temp_data, 1 # vpe1 is selected for
sw r4_temp_data, 0x2720(r5_temp_addr) # GIC_SH_MAP57_VPE31_0 and
sll r4_temp_data, r4_temp_data, 1 # vpe2 is selected for
sw r4_temp_data, 0x2740(r5_temp_addr) # GIC_SH_MAP58_VPE31_0 and
sll r4_temp_data, r4_temp_data, 1 # vpe3 is selected for
sw r4_temp_data, 0x2760(r5_temp_addr) # GIC_SH_MAP59_VPE31_0 and
sll r4_temp_data, r4_temp_data, 1 # vpe4 is selected for
li r4_temp_data, 1 # vpe0 is selected for
sw r4_temp_data, 0x2780(r5_temp_addr) # GIC_SH_MAP60_VPE31_0 and
sll r4_temp_data, r4_temp_data, 1 # vpe5 is selected for
sw r4_temp_data, 0x27a0(r5_temp_addr) # GIC_SH_MAP61_VPE31_0 and
sll r4_temp_data, r4_temp_data, 1 # vpe6 is selected for
sw r4_temp_data, 0x27c0(r5_temp_addr) # GIC_SH_MAP62_VPE31_0 and
sll r4_temp_data, r4_temp_data, 1 # vpe7 is selected for
sw r4_temp_data, 0x27e0(r5_temp_addr) # GIC_SH_MAP63_VPE31_0 and
init_vpe_gic:
# Initialize configuration of per vpe interrupts
li r5_temp_addr, GIC_LOCAL_OFS
lw r7_temp_mark, 0x0000(r5_temp_addr) # GIC_VPEi_CFG
map_timer_int:
ext r4_temp_data, r7_temp_mark, 1, 1 # TIMER_ROUTABLE
beqz r4_temp_data, map_perfcount_int
nop
map_perfcount_int:
ext r4_temp_data, r7_temp_mark, 2, 1 # PERFCOUNT_ROUTABLE
beqz r4_temp_data, done_gic
nop
done_gic:
jr r31_return_addr
nop
/**************************************************************************************
Hardcoded Denali Databahn DRAM controller initialization.
**************************************************************************************/
init_mc:
#ifdef UBOOT_ROM
//#define USE_PCIE_SRAM 1
#define FE_SRAM_STACK 0xBE108000
#define RALINK_CLKCFG0_REG (RALINK_SYSCTL_BASE+0x2C)
#define RALINK_RSTCTRL_REG (RALINK_SYSCTL_BASE+0x34)
//set SPI clock to system bus /(5+2)
li t0, RALINK_SPI_BASE + 0x3c
//sw zero, 0(t0)
li t1, ~0x0FFF
lw t2, 0(t0)
and t2, t2, t1
ori t2, t2, 0x5
sw t2, 0(t0)
/* change CPU ratio from 1/A to 1/1 */
li t0, RALINK_DYN_CFG0_REG
li t1, ~(0x0F<<8)
lw t2, 0(t0)
and t2, t2, t1
li t1, 1<<8
or t2, t2, t1
sw t2, 0(t0)
/* enter accessible PSE SRAM */
/* RESET PSE SRAM */
li t0, 0xBE100004
li t1 ,0x1
sw t1, 0(t0)
li t2, 0x333333/3
#if 0
DLY:
subu t2, t2, 1
bgtz t2, DLY
nop
#endif
li t0, 0xBE100004
lw t1, 0(t0)
ori t1, 0x6 //FE_RST_GLO[2:1]=2'b11 (bit2=PSE_RAM mode, bit1=enable)
sw t1, 0(t0)
nop
#ifndef BYPASS_MTK_DDR_CAL
#ifdef USE_PCIE_SRAM
/* enable accessible PCIe SRAM */
li t0, RALINK_RSTCTRL_REG
li t1, 0x7<<24
sw t1, 0(t0)
li t0, RALINK_CLKCFG0_REG
lw t1, 0(t0)
li t2, 1<<17
or t1, t1, t2
sw t1, 0(t0)
li t0, RALINK_RSTCTRL_REG
sw zero, 0(t0)
li t0, 0xBE1400B0
ori t1, t3, 1
sw t1, 0(t0)
#endif
set_tag 0xC
/* move code to SRAM */
li t0, 0xBE00001C
lw t1, 0(t0)
//ori t1, t1, 0x1
li t1, 0x0
sw t1, 0(t0)
lui t0, %hi(uboot_end_data)
addiu t0, t0, %lo(uboot_end_data)
li t1, 0xBE108800
li t3, (24*1024-256-0x800)
1:
lw t2, 0(t0)
sw t2, 0(t1)
addiu t0, t0, 4
addiu t1, t1, 4
subu t3, t3, 4
bgtz t3, 1b
nop
li t0, 0xBE10DFF0
sw r31_return_addr, 0(t0)
li t0, 0xBE10DF00
sw $1, 0(t0)
sw $2, 4(t0)
sw $3, 8(t0)
sw $4, 12(t0)
sw $5, 16(t0)
sw $6, 20(t0)
sw $7, 24(t0)
sw $16,28(t0)
sw $17, 32(t0)
sw $18, 36(t0)
sw $19, 40(t0)
sw $20, 44(t0)
sw $21, 48(t0)
sw $22, 52(t0)
sw $23, 56(t0)
sw $24, 60(t0)
sw $25, 64(t0)
sw $26, 68(t0)
sw $27, 72(t0)
sw $28, 76(t0)
sw $29, 80(t0)
sw $30, 84(t0)
sw $31, 88(t0)
li t9 , 0xBE108800
jalr t9
nop
li t0, 0xBE10DFF0
lw r31_return_addr, 0(t0)
li t0, 0xBE10DF00
lw $1, 0(t0)
lw $2, 4(t0)
lw $3, 8(t0)
lw $4, 12(t0)
lw $5, 16(t0)
lw $6, 20(t0)
lw $7, 24(t0)
lw $16,28(t0)
lw $17, 32(t0)
lw $18, 36(t0)
lw $19, 40(t0)
lw $20, 44(t0)
lw $21, 48(t0)
lw $22, 52(t0)
lw $23, 56(t0)
lw $24, 60(t0)
lw $25, 64(t0)
lw $26, 68(t0)
lw $27, 72(t0)
lw $28, 76(t0)
lw $29, 80(t0)
lw $30, 84(t0)
lw $31, 88(t0)
set_tag 0xE
#ifdef USE_PCIE_SRAM
/* disable accessible PCIe SRAM */
li t0, 0xBE1400B0
lw t1, 0(t0)
li t2, ~0x1
and t1, t1, t2
sw t1, 0(t0)
li t0, RALINK_RSTCTRL_REG
li t1, 0x7<<24
sw t1, 0(t0)
li t0, RALINK_CLKCFG0_REG
lw t1, 0(t0)
li t2, ~(1<<17)
and t1, t1, t2
sw t1, 0(t0)
li t0, RALINK_RSTCTRL_REG
sw zero, 0(t0)
#endif
#else
li sp, FE_SRAM_STACK
sw r31_return_addr, 0(sp)
addiu sp, sp ,4
#if !defined (FPGA_BOARD)
/* change mpll source from CR setting */
li t0, 0xBE00002C
lw t1, 0(t0)
li t2, 1<<23
or t1, t1, t2
sw t1, 0(t0)
set_tag 0xC
lui t9, %hi(mempll_init)
addiu t9, t9, %lo(mempll_init)
jalr t9
nop
MEMPLL_INIT_DONE:
#endif
set_tag 0xD
lui t9, %hi(ddr_initialize)
addiu t9, t9, %lo(ddt_initialize)
jalr t9
nop
set_tag 0xE
DDR_INIT_DONE:
subu sp, sp, 4
lw r31_return_addr, 0(sp)
#endif
/* exit accessible PSE SRAM */
li t0, 0xBE100004
lw t1, 0(t0)
li t2, ~0x6
and t1, t1, t2
ori t1, 1 //reset PSE
sw t1, 0(t0)
#else
// Reset PSE
#if 1
li t0, 0xBE00080C
lw t1, 0(t0)
srl t1, t1, 1
sll t1, t1, 1
sw t1, 0(t0)
li t0, 0xBE100004
lw t1, 0(t0)
li t1, 0x1
sw t1, 0(t0)
#endif
#endif // UBOOT_ROM //
COPY_WAITCODE:
lui t0, %hi(waitcode_start)
addiu t0, t0, %lo(waitcode_start)
lui t1, %hi(waitcode_end)
addiu t1, t1, %lo(waitcode_end)
lui t2, %hi(WAITCODE_IN_RAM)
addiu t2, t2, %lo(WAITCODE_IN_RAM)
1:
lw t3, 0(t0)
sw t3, 0(t2)
addiu t0, t0, 4
addiu t2, t2, 4
bne t0, t1, 1b
nop
jr r31_return_addr
nop
/**************************************************************************************
**************************************************************************************/
#if 0 //done by board_init_r()
copy_c2_ram:
# Copy code and read-only/initialized data from FLASH to (uncached) RAM.
la r5_temp_addr, _zap1
ins r5_temp_addr, r1_all_ones, 29, 1
la r6_temp_dest, _ftext_ram
ins r6_temp_dest, r1_all_ones, 29, 1
la r7_temp_mark, _edata_ram
ins r7_temp_mark, r1_all_ones, 29, 1
beq r6_temp_dest, r7_temp_mark, zero_bss
nop
next_ram_word:
lw r4_temp_data, 0(r5_temp_addr)
sw r4_temp_data, 0(r6_temp_dest)
addiu r6_temp_dest, 4
bne r7_temp_mark, r6_temp_dest, next_ram_word
addiu r5_temp_addr, 4
zero_bss:
la r5_temp_addr, _fbss
ins r5_temp_addr, r1_all_ones, 29, 1
la r7_temp_mark, _end
ins r7_temp_mark, r1_all_ones, 29, 1
beq r5_temp_addr, r7_temp_mark, copy_c2_ram_done
nop
next_bss_word:
sw $0, 0(r5_temp_addr)
addiu r5_temp_addr, 4
bne r5_temp_addr, r7_temp_mark, next_bss_word
nop
copy_c2_ram_done:
# initialize "early" global variable.
la r5_temp_addr, num_cores
ins r5_temp_addr, r1_all_ones, 29, 1 # Uncached kseg1
add r4_temp_data, r19_more_cores, 1
sw r4_temp_data, 0(r5_temp_addr)
jr r31_return_addr
nop
#endif
/**************************************************************************************
**************************************************************************************/
release_mp:
blez r19_more_cores, done_release_mp # If no more cores then we are done.
li r7_temp_mark, 1
beqz r30_cpc_addr, release_next_core # If no CPC then use GCR_CO_RESET_RELEASE
nop # else use CPC Power Up command.
powerup_next_core:
# Send PwrUp command to next core causing execution at their reset exception vector.
move r4_temp_data, r7_temp_mark
sll r4_temp_data, 16
sw r4_temp_data, 0x2010(r30_cpc_addr) # CPC_CL_OTHER
li r4_temp_data, 3 # "PwrUp" power domain command.
sw r4_temp_data, 0x4000(r30_cpc_addr) # CPC_CO_CMD PwrUp
bne r19_more_cores, r7_temp_mark, powerup_next_core
add r7_temp_mark, r7_temp_mark, 1
jr r31_return_addr
nop
release_next_core:
# Release next core to execute at their reset exception vector.
move r4_temp_data, r7_temp_mark
sll r4_temp_data, 16
sw r4_temp_data, 0x2018(r22_gcr_addr) # GCR_CL_OTHER
sw $0, 0x4000(r22_gcr_addr) # GCR_CO_RESET_RELEASE
bne r19_more_cores, r7_temp_mark, release_next_core
add r7_temp_mark, r7_temp_mark, 1
done_release_mp:
jr r31_return_addr
nop
/*
************************************************************************
* C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| MMU Size | IS | IL | IA | DS | DL | DA |Rsvd |W|C|E|F| Config1
* | | | | | | | | | |R|A|P|P|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
/**************************************************************************************
**************************************************************************************/
init_icache:
# Can be skipped if using magic simulation cache flush
# Determine how big the I$ is
mfc0 $10, $16, 1 # C0_Config1
# Isolate I$ Line Size
ext $11, $10, 19, 3 # S_Config1IL, W_Config1IL
# Skip ahead if No I$
beq $11, $0, done_icache
nop
li $14, 2
sllv $11, $14, $11 # Now have true I$ line size in bytes
ext $12, $10, 22, 3 # S_Config1IS, W_Config1IS
li $14, 64
sllv $12, $14, $12 # I$ Sets per way
# Config1IA == I$ Assoc - 1
ext $13, $10, 16, 3 # S_Config1IA, W_Config1IA
add $13, 1
mul $12, $12, $13 # Total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28 # C0_ITagLo
mtc0 $0, $29 # C0_ITagHi
move $15, $12
next_icache_tag:
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
cache 0x8, 0($14) # ICIndexStTag
add $15, -1 # Decrement set counter
bne $15, $0, next_icache_tag
add $14, $11 # Get next line address
done_icache:
# Modify return address to kseg0 which is cacheable (for code linked in kseg1.)
#if !defined (MTK_NAND)
ins r31_return_addr, $0, 29, 1
#endif
jr r31_return_addr
nop
/**************************************************************************************
**************************************************************************************/
init_dcache:
# Isolate D$ Line Size
ext $11, $10, 10, 3 # S_Config1DL, W_Config1DL
# Skip ahead if No D$
beq $11, $0, done_dcache
nop
li $14, 2
sllv $11, $14, $11 # Now have true D$ line size in bytes
ext $12, $10, 13, 3 # S_Config1DS, W_Config1DS
li $14, 64
sllv $12, $14, $12 # D$ Sets per way
# Config1DA == D$ Assoc - 1
ext $13, $10, 7, 3 # S_Config1DA, W_Config1DA
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear TagLo/TagHi registers
mtc0 $0, $28 # C0_TagLo
mtc0 $0, $29 # C0_TagHi
mtc0 $0, $28, 2 # C0_DTagLo
mtc0 $0, $29, 2 # C0_DTagHi
move $15, $12
next_dcache_tag:
# Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
cache 0x9, 0($14) # DCIndexStTag
add $15, -1 # Decrement set counter
bne $15, $0, next_dcache_tag
add $14, $11 # Get next line address
done_dcache:
jr r31_return_addr
nop
/**************************************************************************************
**************************************************************************************/
init_cm:
beqz r3_is_cps, done_cm_init # skip if not a CPS or CM register verification failed.
nop
# Allow each core access to the CM registers (they should only access their local registers.)
li r5_temp_addr, GCR_CONFIG # KSEG1(GCRBASE)
li r4_temp_data, 2 # Start building mask for cores in this cps.
sll r4_temp_data, r4_temp_data, r19_more_cores
addiu r4_temp_data, -1 # Complete mask.
sw r4_temp_data, 0x0020(r5_temp_addr) # GCR_ACCESS
# Check to see if this CPS implements an IOCU.
lw r4_temp_data, 0(r22_gcr_addr) # Load GCR_CONFIG
ext r4_temp_data, r4_temp_data, 8, 4 # Extract NUMIOCU.
beqz r4_temp_data, done_cm_init
lui r4_temp_data, 0xffff
# Disable the CM regions if there is an IOCU.
li r4_temp_data, GCR_REG0_BASE_VALUE # Physical address
sw r4_temp_data, 0x0090(r5_temp_addr) # GCR_REG0_BASE
li r4_temp_data, GCR_REG1_BASE_VALUE # Physical address
sw r4_temp_data, 0x00a0(r5_temp_addr) # GCR_REG1_BASE
li r4_temp_data, GCR_REG2_BASE_VALUE # Physical address
sw r4_temp_data, 0x00b0(r5_temp_addr) # GCR_REG2_BASE
li r4_temp_data, GCR_REG3_BASE_VALUE # Physical address
sw r4_temp_data, 0x00c0(r5_temp_addr) # GCR_REG3_BASE
lw r4_temp_data, 0x0098(r5_temp_addr) # GCR_REG0_MASK
li $11, GCR_REG0_MASK_VALUE
ins r4_temp_data, $11, 16, 16
li $11, 0x2
ins r4_temp_data, $11, 0, 2
sw r4_temp_data, 0x0098(r5_temp_addr) # GCR_REG0_MASK
lw r4_temp_data, 0x00a8(r5_temp_addr) # GCR_REG1_MASK
li $11, GCR_REG1_MASK_VALUE
ins r4_temp_data, $11, 16, 16
li $11, 0x2
ins r4_temp_data, $11, 0, 2
sw r4_temp_data, 0x00a8(r5_temp_addr) # GCR_REG1_MASK
lw r4_temp_data, 0x00b8(r5_temp_addr) # GCR_REG2_MASK
li $11, GCR_REG2_MASK_VALUE
ins r4_temp_data, $11, 16, 16
li $11, 0x2
ins r4_temp_data, $11, 0, 2
sw r4_temp_data, 0x00b8(r5_temp_addr) # GCR_REG2_MASK
lw r4_temp_data, 0x00c8(r5_temp_addr) # GCR_REG3_MASK
li $11, GCR_REG3_MASK_VALUE
ins r4_temp_data, $11, 16, 16
li $11, 0x2
ins r4_temp_data, $11, 0, 2
sw r4_temp_data, 0x00c8(r5_temp_addr) # GCR_REG3_MASK
lw r4_temp_data, 0x0008(r5_temp_addr) # GCR_BASE
ins r4_temp_data, $0, 0, 2
sw r4_temp_data, 0x0008(r5_temp_addr) # GCR_BASE
lw r4_temp_data, 0x0010(r5_temp_addr) # GCR_BASE
li $11, 0x1
ins r4_temp_data, $11, 16, 1
sw r4_temp_data, 0x0010(r5_temp_addr) # GCR_BASE
done_cm_init:
jr r31_return_addr
nop
/**************************************************************************************
**************************************************************************************/
init_itc:
nop
# enhanceme: Add ITC init.
done_init_itc:
jr r31_return_addr
nop
/**************************************************************************************
**************************************************************************************/
join_domain:
beqz r3_is_cps, done_join_domain # If this is not a CPS then we are done.
nop
# Enable coherence and allow interventions from all other cores.
# (Write access enabled via GCR_ACCESS by core 0.)
li $9, 1
sll $9, r19_more_cores
sll $9, 1
addiu $9, -1
or $9, (1<<4)
sw $9, 0x2008(r22_gcr_addr) # GCR_CL_COHERENCE
ehb
# Cores other than core 0 can relinquish write access to CM regs here.
# enhanceme: Use iter-core ITC (1004K MR2 or 1074K) for efficient synchronization.
# (Uncached accesses to GCR_CO_COHERENCE will flood bus but will not slow D$ init.)
move r7_temp_mark, $0
next_coherent_core:
sll r4_temp_data, r7_temp_mark, 16
sw r4_temp_data, 0x2018(r22_gcr_addr) # GCR_CL_OTHER[CoreNum]
busy_wait_coherent_core:
lw r4_temp_data, 0x4008(r22_gcr_addr) # GCR_CO_COHERENCE
beqz r4_temp_data, busy_wait_coherent_core # Busy wait on cores joining.
nop
bne r7_temp_mark, r19_more_cores, next_coherent_core
addiu r7_temp_mark, 1
done_join_domain:
jr r31_return_addr
nop
/*
************************************************************************
* C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) *
************************************************************************
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |M| TU | TS | TL | TA | SU | SS | SL | SA | Config2
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
/**************************************************************************************
**************************************************************************************/
init_l23u:
# Use MR2 CCA Override to allow cached execution of L2/3 init.
# Check for CCA_Override_Enable by writing a one.
beqz r3_is_cps, init_l23
nop
lw r4_temp_data, 0x0008(r22_gcr_addr) # GCR_BASE
li r7_temp_mark, 0x50 # CM_DEFAULT_TARGET Memory
ins r4_temp_data, r7_temp_mark, 0, 8 # CCA Override Uncached enabled
sw r4_temp_data, 0x0008(r22_gcr_addr) # GCR_BASE. Comment to prevent use of CCA Override.
lw r4_temp_data, 0x0008(r22_gcr_addr) # GCR_BASE
ext r4_temp_data, r4_temp_data, 4, 1 # CCA_Override_Enable
bnez r4_temp_data, done_l23 # Skip uncached execution if CCA Override is implemented.
nop
b init_l23
nop
init_l23c:
beqz r3_is_cps, done_l3cache
nop
lw r4_temp_data, 0x0008(r22_gcr_addr) # GCR_BASE
bnez r16_core_num, done_l3cache # Only done from core 0.
ext r4_temp_data, r4_temp_data, 4, 1 # CCA_Override_Enable
beqz r4_temp_data, done_l3cache # Skip cached execution if CCA Override is not implemented.
nop
init_l23:
# L2 Cache initialization routine
# Check L2 cache size
mfc0 $10, $16, 2 # C0_Config2
# Isolate L2$ Line Size
ext $11, $10, 4, 4 # S_Config2SL, W_Config2SL
# Skip ahead if No L2$
beq $11, $0, done_l2cache
nop
li $14, 2
sllv $11, $14, $11 # Now have true L2$ line size in bytes
# Isolate L2$ Sets per Way
ext $12, $10, 8, 4 # S_Config2SS, W_Config2SS
li $14, 64
sllv $12, $14, $12 # L2$ Sets per way
# Isolate L2$ Associativity
# L2$ Assoc (-1)
ext $13, $10, 0, 4 # S_Config2SA, W_Config2SA
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear L23TagLo/L23TagHi registers
mtc0 $0, $28, 4
mtc0 $0, $29, 4
move $15, $12
# L2$ Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0xB, 0($14) # SCIndexStTag
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
done_l2cache:
# Isolate L3$ Line Size
ext $11, $10, 20, 4 # S_Config2TL, W_Config2TL
# Skip ahead if No L3$
beq $11, $0, done_l3cache
nop
li $14, 2
sllv $11, $14, $11 # Now have true L3$ line size in bytes
# Isolate L3$ Sets per Way
ext $12, $10, 24, 4 # S_Config2TS, W_Config2TS
li $14, 64
sllv $12, $14, $12 # L2$ Sets per way
# Isolate L3$ Associativity
# L3$ Assoc (-1)
ext $13, $10, 16, 4 # S_Config2TA, W_Config2TA
add $13, 1
mul $12, $12, $13 # Get total number of sets
lui $14, 0x8000 # Get a KSeg0 address for cacheops
# Clear L23TagLo/L23TagHi registers
mtc0 $0, $28, 4
mtc0 $0, $29, 4
move $15, $12
# L3$ Index Store Tag Cache Op
# Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
1: cache 0xA, 0($14) # TCIndexStTag
add $15, -1 # Decrement set counter
bne $15, $0, 1b
add $14, $11 # Get next line address
done_l3cache:
# disable CCA Override
beqz r3_is_cps, done_l23
nop
lw r4_temp_data, 0x0008(r22_gcr_addr) # GCR_BASE
ins r4_temp_data, $0, 0, 8 # CCA Override disabled
sw r4_temp_data, 0x0008(r22_gcr_addr) # GCR_BASE
done_l23:
#if 0 //MTK: configure L2 cache size
.set at
mfc0 t0, CP0_CONFIG
or t0, (1<<19)
mtc0 t0, CP0_CONFIG
nop
mfc0 t0, CP0_CONFIG,2
move t1 ,t0
and t0,~(0xF << 8)
or t0,(4 <<8) //1024*32*8=256K
// or t0,(3 <<8) //512*32*8=128K
// and t0,~(0xF << 4) //no cache
mtc0 t0, CP0_CONFIG,2
nop
mfc0 t0, CP0_CONFIG
and t0, ~(1<<19)
mtc0 t0, CP0_CONFIG
nop
nop
.set noat
#endif
jr r31_return_addr
nop
/**************************************************************************************
**************************************************************************************/
init_vpe1:
# fixme: a lot of this is now redundant. each vpe init's it's own resources.
# Initializing a vpe should ammount to setting it's lowest numberd bound tc to
# start execution from the reset vector.
# Each vpe will need to set up additional tc bound to it. (No rebinding.)
beqz r21_more_tcs, done_init_vpe1 # If there is no .
nop
beqz r20_more_vpes, done_init_vpe1 # If there is no vpe1 then skip init_vpe1.
nop
# This is executing on TC0 bound to VPE0. Therefore VPEConf0.MVP is set.
# Enter config mode
mfc0 $8, $0, 1 # C0_MVPCtl
or $8, (1 << 1) # M_MVPCtlVPC
mtc0 $8, $0, 1 # C0_MVPCtl
ehb
#define NTCS $10
#define NVPES $11
#define TC $12
# Get number of TC's and VPE's
mfc0 $8, $0, 2 # C0_MVPConf0
ext NTCS, $8, 0, 8 # S_MVPConf0PTC, W_MVPConf0PTC
ext NVPES, $8, 10, 4 # S_MVPConf0PVPE, W_MVPConf0PVPE
# Initialise TC's/VPE's
move TC, $0
nexttc:
# Select TCn
mfc0 $8, $1, 1 # C0_VPECtl
ins $8, TC, 0, 8 # S_VPECtlTargTC, W_VPECtlTargTC
mtc0 $8, $1, 1 # C0_VPECtl
ehb
# Bind TC to next VPE
beqz TC, nextvpe # Don't rebind TC0
nop
# Halt all TC's other than TC0
li $8, 1 # M_TCHaltH
mttc0 $8, $2, 4 # C0_TCHalt
ehb
slt $9, NVPES, TC
bnez $9, 2f # Bind spare TC's to VPElast
move $9, NVPES
# Set XTC for active TC's
mftc0 $8, $1, 2 # C0_VPEConf0
ins $8, TC, 21, 8 # S_VPEConf0XTC, W_VPEConf0XTC
mttc0 $8, $1, 2 # C0_VPEConf0
move $9, TC
2:
# Bind TC to a VPE
mftc0 $8, $2, 2 # C0_TCBind
ins $8, $9, 0, 4 # S_TCBindCurVPE, W_TCBindCurVPE
mttc0 $8, $2, 2 # C0_TCBind
# Set up TCStatus register:
# Disable Coprocessor Usable bits
# Disable MDMX/DSP ASE
# Clear Dirty TC
# not dynamically allocatable
# not allocated
# Kernel mode
# interrupt exempt
# ASID 0
li $8, (1 << 10) # M_TCStatusIXMT
mttc0 $8, $2, 1 # C0_TCStatus
# Initialize the TC's register file
mttgpr $0, $1
mttgpr $0, $2
mttgpr $0, $3
mttgpr $0, $4
mttgpr $0, $5
mttgpr $0, $6
mttgpr $0, $7
mttgpr $0, $8
mttgpr $0, $9
mttgpr $0, $10
mttgpr $0, $11
mttgpr $0, $12
mttgpr $0, $13
mttgpr $0, $14
mttgpr $0, $15
mttgpr $0, $16
mttgpr $0, $17
mttgpr $0, $18
mttgpr $0, $19
mttgpr $0, $20
mttgpr $0, $21
mttgpr $0, $22
mttgpr $0, $23
mttgpr $0, $24
mttgpr $0, $25
mttgpr $0, $26
mttgpr $0, $27
mttgpr $0, $28
mttgpr $0, $29
mttgpr $0, $30
mttgpr $0, $31
nextvpe:
slt $9, NVPES, TC
bnez $9, donevpe # No more VPE's
nop
# Disable multi-threading with TC's
mftc0 $8, $1, 1 # C0_VPECtl
ins $8, $0, 15, 1 # S_VPECtlTE, W_VPECtlTE
mttc0 $8, $1, 1 # C0_VPECtl
beqz TC, 1f
nop
# For VPE1..n
# Clear VPA and set master VPE
mftc0 $8, $1, 2 # C0_VPEConf0
ins $8, $0, 0, 1 # S_VPEConf0VPA, W_VPEConf0VPA
or $8, (1 << 1) # M_VPEConf0MVP
mttc0 $8, $1, 2 # C0_VPEConf0
mfc0 $8, $12 # C0_Status
mttc0 $8, $12 # C0_Status
li $8, 0x12345678
mttc0 $8, $14 # C0_EPC
mttc0 $0, $13 # C0_Cause
mfc0 $8, $16 # C0_Config
mttc0 $8, $16 # C0_Config
mftc0 $8, $15, 1 # C0_EBase
ext $8, $8, 0, 10 # S_EBaseCPUNum, W_EBaseCPUNum
mttgpr $8, r23_cpu_num
# vpe1 of each core can execute cached as it's L1 I$ has already been initialized.
# and the L2$ has been initialized or "disabled" via CCA override.
lui r5_temp_addr, %hi(__reset_vector)
addiu r5_temp_addr, %lo(__reset_vector)
#if !defined (MTK_NAND)
ins r5_temp_addr, $0, 29, 1 # Convert to cached kseg0 address in case we linked to kseg1.
#endif
mttc0 r5_temp_addr, $2, 3 # C0_TCRestart
# Yes.. this is undoing all of the work done above... :)
mftc0 $8, $2, 1 # C0_TCStatus
ins $8, $0, 10, 1 # S_TCStatusIXMT, W_TCStatusIXMT
ori $8, (1 << 13) # M_TCStatusA
mttc0 $8, $2, 1 # C0_TCStatus
mttc0 $0, $2, 4 # C0_TCHalt
mftc0 $8, $1, 2 # C0_VPEConf0
ori $8, 1 # M_VPEConf0VPA
mttc0 $8, $1, 2 # C0_VPEConf0
1:
donevpe:
addu TC, 1
sltu $9, NTCS, TC
beqz $9, nexttc
nop
# Exit config mode
mfc0 $8, $0, 1 # C0_MVPCtl
ori $8, 1 # set MVPControl.EVP will enable execution by vpe1!
ins $8, $0, 1, 1 # S_MVPCtlVPC, W_MVPCtlVPC
mtc0 $8, $0, 1 # C0_MVPCtl
ehb
#undef NTCS
#undef NVPES
#undef TC
done_init_vpe1:
jr r31_return_addr
nop
/**************************************************************************************
**************************************************************************************/
/*
* The CPS has been initialized.
* All vpe on all cores are running main in kernel mode with their own stack and shared globals.
* Each VPE has at least one TC. TCs beyond the number of VPEs are bound to the highest numbered VPE.
*/
#define r4_temp_data $20
#define r5_temp_addr $21
#define r6_temp_dest $22
#define r7_temp_mark $23
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* a0 = addr_sp
* a1 = gd
* a2 = destination address
*/
.globl relocate_code
.ent relocate_code
.set at
relocate_code:
move sp, a0 # set new stack pointer
li t0, CONFIG_SYS_MONITOR_BASE
lui t3, %hi(in_ram)
addiu t3, t3, %lo(in_ram)
lw t2, -12(t3) # t2 <-- uboot_end_data
move t1, a2
move s2, a2 # s2 <-- destination address
/*
* Fix $gp:
*
* New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
*/
move t6, gp
sub gp, CONFIG_SYS_MONITOR_BASE
add gp, a2 # gp now adjusted
sub s1, gp, t6 # s1 <-- relocation offset
/*
* t0 = source address
* t1 = target address
* t2 = source end address
*/
/*
* Save destination address and size for later usage in flush_cache()
*/
move s0, a1 # save gd in s0
move a0, t1 # a0 <-- destination addr
sub a1, t2, t0 # a1 <-- size
1:
lw t3, 0(t0)
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
addu t1, 4
/* If caches were enabled, we would have to flush them here. */
/* a0 & a1 are already set up for flush_cache(start, size) */
//la t9, flush_cache
//jalr t9
//nop
set_tag 0x7
/* Jump to where we've relocated ourselves */
addi t0, s2, in_ram - _start
jr t0
nop
.word _gp
.word _GLOBAL_OFFSET_TABLE_
.word uboot_end_data
.word uboot_end
.word num_got_entries
in_ram:
set_tag 0x8
/*
* Now we want to update GOT.
*
* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
* generated by GNU ld. Skip these reserved entries from relocation.
*/
lw t3, -4(t0) # t3 <-- num_got_entries
lw t4, -16(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
lw t5, -20(t0) # t5 <-- _gp
sub t4, t5 # compute offset
add t4, t4, gp # t4 now holds relocated _G_O_T_
addi t4, t4, 8 # skipping first two entries
li t2, 2
1:
lw t1, 0(t4)
beqz t1, 2f
add t1, s1
sw t1, 0(t4)
2:
addi t2, 1
blt t2, t3, 1b
addi t4, 4
/* Clear BSS */
lw t1, -12(t0) # t1 <-- uboot_end_data
lw t2, -8(t0) # t2 <-- uboot_end
add t1, s1 # adjust pointers
add t2, s1
sub t1, 4
1:
addi t1, 4
bltl t1, t2, 1b
sw zero, 0(t1)
set_tag 0x9
move a0, s0 # a0 <-- gd
lui t9, %hi(board_init_r)
addiu t9, t9, %lo(board_init_r)
#if 1 /* VIOSOFT: FIXME */
lui t8, %hi(_start)
addiu t8, t8, %lo(_start)
sub t9, t8
add t9, s2, t9
#endif /* VIOSOFT */
jr t9
move a1, s2
.end relocate_code
/* Exception handlers */
romReserved:
b romReserved
romExcHandle:
b romExcHandle
|
MediaTek-Labs/linkit-smart-7688-uboot | 5,948 | board/rt2880/memsetup.S | /* FILE_DESC *****************************************************************
//
// Purpose:
// This file contains macros used for memory initialization.
//
// Sp. Notes:
//
// *****************************************************************************/
/*=====================*
* Include Files *
*=====================*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include "include/product.h"
#include "include/mem_map.h"
#include "include/mac.inc"
#include "include/chip_reg_map.h"
/*=====================*
* Defines *
*=====================*/
.set noreorder
// SDRAM Width
#ifdef USE_SDRAM
#ifdef SDRAM32
#define MAC_SDRAM_WIDTH (MAC_SDRAM_WIDTH_32)
#else
#ifdef SDRAM16
#define MAC_SDRAM_WIDTH (MAC_SDRAM_WIDTH_16)
#else
#error "SDRAM width not defined in makefile"
#endif
#endif
#endif
// SRAM Width
#if USE_SRAM
#if SRAM32
#define MAC_SRAM_WIDTH (MAC_WIDTH_32)
#else
#if SRAM16
#define MAC_SRAM_WIDTH (MAC_WIDTH_16)
#else
#error "SRAM width not defined in makefile"
#endif
#endif
#endif
// Configures the SRAM bank. Must be done
// before attempting SRAM reads or writes.
// Setup modedata with 2-clk cas latency, burst length = 4.
//
// Uses registers t0-t1.
//
#ifdef USE_SRAM
#define CONFIG_SRAM() \
\
li t0, MAC_SRAM_CONFIG_REG; \
li t1, ( (1 << MAC_ADDR2CS_SETUP_SHIFT) | \
(1 << MAC_WADDR_SETUP_SHIFT) | \
(1 << MAC_RADDR_SETUP_SHIFT) | \
(1 << MAC_WE_SHIFT) | \
(1 << MAC_OE_SHIFT) | \
(1 << MAC_WHOLD_SHIFT) | \
(1 << MAC_RHOLD_SHIFT) | \
(2 << MAC_BANKTYPE_SHIFT) | \
MAC_SRAM_WIDTH); \
sw t1, 0(t0);
#endif
// Configures the SDRAM bank. Must be done
// before attempting SDRAM reads or writes.
// Setup modedata with 2-clk cas latency, burst length = 4.
// Configure SDRAM2 bank identically.
//
// Uses registers t5-t7.
//
#ifdef USE_SDRAM
#define CONFIG_SDRAM() \
\
li t6, MAC_SDRAM_CONFIG_REG; \
li t7, MAC_SDRAM2_CONFIG_REG; \
j sdram_pgsize_board; \
nop ; \
\
sdram_pgsize_sim: \
li t5, (0 << MAC_PGSIZE_SHIFT); \
j sdram_pgsize_done; \
nop ; \
\
sdram_pgsize_board: \
li t5, (1 << MAC_PGSIZE_SHIFT); \
j sdram_pgsize_done; \
nop ; \
\
sdram_pgsize_done: \
or t5, ( (7 << MAC_REFR_SHIFT) | \
(0 << MAC_ACTIVE_SHIFT) | \
(0 << MAC_PRECHRG_SHIFT) | \
(1 << MAC_NUMROWADR_SHIFT) | \
(1 << MAC_PRECHGOPT_SHIFT) | \
(2 << MAC_PCABIT_SHIFT) | \
(MAC_BANKTYPE_SDRAM << MAC_BANKTYPE_SHIFT) | \
MAC_SDRAM_WIDTH); \
sw t5, 0(t6); \
sw t5, 0(t7); \
li t6, MAC_SDRAM_MODE_REG; \
li t7, MAC_SDRAM2_MODE_REG; \
li t5, ( (2 << MAC_MD_BURSTLEN_SHIFT) | \
(2 << MAC_MD_LATMODE_SHIFT)); \
sw t5, 0(t6); \
sw t5, 0(t7);
// Initializes SDRAM via the memory controller.
// Must be done before attempting to use SDRAM.
// Initializes SDRAM2 as well.
//
// Uses t4-t6.
//
#define INIT_SDRAM() \
\
/* Enable SDRAM Clock */ \
li t6, MAC_SDRAM_CNTL_REG; \
li t4, MAC_CTRL_SDRAMCLK; \
sw t4, 0(t6); \
\
/* Tell the MAC to initialize SDRAM */ \
add t5, t4, MAC_CTRL_SDRAMINI; \
sw t5, 0(t6); \
\
/* Wait for completion of initialization */ \
init_sdram_loop: \
lw t5, 0(t6); \
bne t5, t4, init_sdram_loop; \
nop; /* branch delay slot */ \
\
\
/* Enable SDRAM2 Clock */ \
li t6, MAC_SDRAM2_CNTL_REG; \
li t4, MAC_CTRL_SDRAMCLK; \
sw t4, 0(t6); \
\
/* Tell the MAC to initialize SDRAM2 */ \
add t5, t4, MAC_CTRL_SDRAMINI; \
sw t5, 0(t6); \
\
init_sdram2_loop: \
lw t5, 0(t6); \
bne t5, t4, init_sdram2_loop; \
nop; /* branch delay slot */ \
\
/* Initialize SDRAM Refresh Control register */ \
/* Setup refresh rate */ \
li t6, MAC_SDRAM_REFR_CNTL_REG; \
li t5, ((0x05F << MAC_REFRESH_RATE_SHIFT) | \
(1 << MAC_REFRESH_PRESCALE_SHIFT)); \
sw t5, 0(t6);
#endif
/*=====================*
* External Variables *
*=====================*/
/*=====================*
* External Functions *
*=====================*/
.globl memsetup
.ent memsetup
memsetup:
CONFIG_SDRAM()
INIT_SDRAM()
j ra
nop
.end memsetup
|
MediaTek-Labs/linkit-smart-7688-uboot | 6,127 | board/rt2880/rt2880_init.S | /*=====================*
* Include Files *
*=====================*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include "include/sysc.h"
#include "include/product.h"
#include "include/mem_map.h"
#include "include/mac.inc"
#include "include/chip_reg_map.h"
#include "include/cpu.h"
/*=====================*
* Defines *
*=====================*/
.set noreorder
// Configures the SRAM bank. Must be done
// before attempting SRAM reads or writes.
// Setup modedata with 2-clk cas latency, burst length = 4.
//
// Uses registers t0-t1.
//
#ifdef USE_SRAM
#define CONFIG_SRAM() \
\
li t0, MAC_SRAM_CONFIG_REG; \
li t1, ( (1 << MAC_ADDR2CS_SETUP_SHIFT) | \
(1 << MAC_WADDR_SETUP_SHIFT) | \
(1 << MAC_RADDR_SETUP_SHIFT) | \
(1 << MAC_WE_SHIFT) | \
(1 << MAC_OE_SHIFT) | \
(1 << MAC_WHOLD_SHIFT) | \
(1 << MAC_RHOLD_SHIFT) | \
(2 << MAC_BANKTYPE_SHIFT) | \
MAC_SRAM_WIDTH); \
sw t1, 0(t0);
#endif
/*=====================*
* External Functions *
*=====================*/
.globl soc_init
.ent soc_init
soc_init:
//////////////////////////////////////////
// S T A R T P L L A N D / O R D L L
//////////////////////////////////////////
#ifdef CODE_IN_SDRAM
// If current code is in SDRAM, may have problems reading and executing
// the code if the DLL clock to the SDRAM is changed on the fly.
#else
#ifdef USE_DLL_INIT
// Must enable DLL before enabling PLL. PLL before DLL does not work.
// DLL_INVERT and DLL_PHASE are defined in product.h
li a0, SYSC_BASE
li a1, DLL_INVERT
li a2, DLL_PHASE
// Disable DLL
lw t1, 0x4c(a0) // DLL Cfg Reg : offset 0x4c
li t0, ~DLL_ENABLE
and t1, t1, t0
sw t1, 0x4c(a0)
// Setup Configuration
// cfg = ((uint32)a2 & DLL_PHASE_MASK) << DLL_PHASE_SHIFT;
// cfg |= a1 ? DLL_INVERT_SYSCLK : 0;
andi a2, a2, DLL_PHASE_MASK
sll a2, a2, DLL_PHASE_SHIFT
ori t0, a2, DLL_INVERT_SYSCLK
movn a2, t0, a1 // if (t) d=s
sw a2, 0x4c(a0)
// enable the DLL
lw t0, 0x4c(a0)
ori t0, t0, DLL_ENABLE
sw t0, 0x4c(a0)
// Wait until dll locked
1: lw t0, 0x50(a0) // DLL Stat Reg: offset 0x50
andi t0, t0, DLL_LOCKED
beqz t0, 1b
nop
#else
// Current graphite (rev 2) requires DLL_INVERT_SYSCLK bit to be
// cleared to access SDRAM
// For CODE_IN_SDRAM, bit is cleared by debugger startice.cmd file
li t0, DLL_CONFIG_REG
lw t1, 0(t0)
li t2, ~DLL_INVERT_SYSCLK
and t3, t1, t2
sw t3, 0(t0)
#endif
#endif
#ifdef USE_PLL_INIT
// PLL_DIV and PLL_MULT are defined in product.h
li a0, SYSC_BASE
li a1, (PLL_DIV - 1)
#ifdef USE_DLL_INIT
// Adjust for fact that system clock is divided by two when DLL enabled
li a2, ((PLL_MULT * 2) - 1) // branch delay slot
#else
li a2, (PLL_MULT - 1) // branch delay slot
#endif
//Put PLL control in its POR state. (bypass, ~enable, reset)
lw t0, 0x40(a0) // PLL Ctrl Reg: offset 0x40
ori t0, t0, PLL_BYPASS
sw t0, 0x40(a0)
li t0, PLL_BYPASS | PLL_RESET
sw t0, 0x40(a0)
// Setup configuration
andi a2, a2, PLL_FEEDBACK_NDIV_MASK
sll a2, a2, PLL_FEEDBACK_NDIV_SHIFT
andi a1,a1, PLL_REFCLK_MDIV_MASK
sll a1, a1, PLL_REFCLK_MDIV_SHIFT
or a1, a1, a2
sw a1, 0x44(a0) // PLL Cfg Reg: offset 0x44
// Enable the pll
// ** Must be done in two steps.
// ** Step 1: take pll out of reset state
// ** Step 2: enable pll
// Step 1:
lw t0, 0x40(a0)
li t1, ~PLL_RESET
and t0, t0, t1
sw t0, 0x40(a0)
// Step 2:
lw t0, 0x40(a0)
ori t0, t0, PLL_ENABLE
sw t0, 0x40(a0)
// Wait until pll locked before selecting pll as system clock
1: lw t0, 0x48(a0) // PLL Stat Reg: offset 0x48
andi t0, t0, PLL_LOCKED
beqz t0, 1b
nop
// Select pll clock for system clock
lw t0, 0x40(a0)
li t1, ~PLL_BYPASS
and t0, t0, t1
sw t0,0x40(a0)
#endif
// Configure ROM Bank, which at power-up is initialized in its
// slowest mode.
// Use the current (POR) MAC_WIDTH value, since hardware should always
// have the correct ROM MAC_WIDTH as the POR value.
li t0, MAC_ROM_CONFIG_REG
lw t2, 0(t0)
andi t2, (MAC_WIDTH_MASK << MAC_WIDTH_SHIFT)
#if 0 // DEBUG - ROM set for fastest access
li t1, ( (1 << MAC_BYTE_EN_SHIFT) | \
(1 << MAC_ADDR2CS_SETUP_SHIFT) | \
(1 << MAC_WADDR_SETUP_SHIFT) | \
(1 << MAC_RADDR_SETUP_SHIFT) | \
(1 << MAC_WE_SHIFT) | \
(1 << MAC_OE_SHIFT) | \
(1 << MAC_WHOLD_SHIFT) | \
(1 << MAC_RHOLD_SHIFT) | \
(2 << MAC_BANKTYPE_SHIFT) )
#else // DEBUG - ROM set for slowest access
li t1, ( (0x1 << MAC_BYTE_EN_SHIFT) | \
(0x3 << MAC_ADDR2CS_SETUP_SHIFT) | \
(0x3 << MAC_WADDR_SETUP_SHIFT) | \
(0x3 << MAC_RADDR_SETUP_SHIFT) | \
(0xF << MAC_WE_SHIFT) | \
(0xF << MAC_OE_SHIFT) | \
(0x3 << MAC_WHOLD_SHIFT) | \
(0x3 << MAC_RHOLD_SHIFT) | \
(0x2 << MAC_BANKTYPE_SHIFT) )
#endif
or t1, t2
sw t1, 0(t0)
#ifdef USE_SRAM
CONFIG_SRAM()
#endif
/////////////////////////////
// I N I T P A L M P A K
/////////////////////////////
#ifdef REMAPPED_VECTOR_MEM
// Need to remap the vector memory to 0x0 if no memory there
li t0, CPU_CONFIG_REG
lw t1, 0(t0)
ori t1, REMAP_VECTMEM
sw t1, 0(t0)
#endif
#ifdef REMAPPED_SDRAM
// -OR- remap the first 2MB of sdram to 0x0
// NOTE: If both REMAPPED_VECTOR_MEM and REMAPPED_SDRAM are defined,
// software can setup for both, but hardware will give vector_mem
// precedence and remap it to 0x0.
li t0, CPU_CONFIG_REG
lw t1, 0(t0)
ori t1, REMAP_SDRAM2VEC
sw t1, 0(t0)
kaiker
#endif
j ra
nop
.end soc_init
|
merlinepedra/DarkFlippers-unleashed-firmware | 12,159 | firmware/targets/f7/startup_stm32wb55xx_cm4.s | /**
******************************************************************************
* @file startup_stm32wb55xx_cm4.s
* @author MCD Application Team
* @brief STM32WB55xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2019-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* start address for the .MB_MEM2 section. defined in linker script */
.word _sMB_MEM2
/* end address for the .MB_MEM2 section. defined in linker script */
.word _eMB_MEM2
/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
.macro INIT_BSS start, end
ldr r0, =\start
ldr r1, =\end
movs r3, #0
bl LoopFillZerobss
.endm
/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
.macro INIT_DATA start, end, src
ldr r0, =\start
ldr r1, =\end
ldr r2, =\src
movs r3, #0
bl LoopCopyDataInit
.endm
.section .text.data_initializers
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
bx lr
FillZerobss:
str r3, [r0]
adds r0, r0, #4
LoopFillZerobss:
cmp r0, r1
bcc FillZerobss
bx lr
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system intitialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
INIT_DATA _sdata, _edata, _sidata
/* Zero fill the bss segments. */
INIT_BSS _sbss, _ebss
INIT_BSS _sMB_MEM2, _eMB_MEM2
/* Call static constructors */
bl __libc_init_array
/* Call the application s entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word TAMP_STAMP_LSECSS_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word C2SEV_PWR_C2H_IRQHandler
.word COMP_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word PKA_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word LPUART1_IRQHandler
.word SAI1_IRQHandler
.word TSC_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word CRS_IRQHandler
.word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
.word IPCC_C1_RX_IRQHandler
.word IPCC_C1_TX_IRQHandler
.word HSEM_IRQHandler
.word LPTIM1_IRQHandler
.word LPTIM2_IRQHandler
.word LCD_IRQHandler
.word QUADSPI_IRQHandler
.word AES1_IRQHandler
.word AES2_IRQHandler
.word RNG_IRQHandler
.word FPU_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word DMA2_Channel6_IRQHandler
.word DMA2_Channel7_IRQHandler
.word DMAMUX1_OVR_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_LSECSS_IRQHandler
.thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak C2SEV_PWR_C2H_IRQHandler
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak TSC_IRQHandler
.thumb_set TSC_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
.thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
.weak IPCC_C1_RX_IRQHandler
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
.weak IPCC_C1_TX_IRQHandler
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
.weak HSEM_IRQHandler
.thumb_set HSEM_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LCD_IRQHandler
.thumb_set LCD_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak AES1_IRQHandler
.thumb_set AES1_IRQHandler,Default_Handler
.weak AES2_IRQHandler
.thumb_set AES2_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
metux/xorg-xserver | 1,923 | hw/xfree86/os-support/solaris/solaris-amd64.S | / Copyright (c) 2005, Oracle and/or its affiliates.
/
/ Permission is hereby granted, free of charge, to any person obtaining a
/ copy of this software and associated documentation files (the "Software"),
/ to deal in the Software without restriction, including without limitation
/ the rights to use, copy, modify, merge, publish, distribute, sublicense,
/ and/or sell copies of the Software, and to permit persons to whom the
/ Software is furnished to do so, subject to the following conditions:
/
/ The above copyright notice and this permission notice (including the next
/ paragraph) shall be included in all copies or substantial portions of the
/ Software.
/
/ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
/ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
/ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
/ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
/ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
/ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
/ DEALINGS IN THE SOFTWARE.
#ifdef INLINE_ASM
#define FUNCTION_START(f,n) .inline f,n
#define FUNCTION_END(f) .end
#else
#define _ASM
#include <sys/asm_linkage.h>
#define FUNCTION_START(f,n) ENTRY(f)
#define FUNCTION_END(f) ret; SET_SIZE(f)
#endif
FUNCTION_START(inb,4)
movq %rdi, %rdx
xorq %rax, %rax
inb (%dx)
FUNCTION_END(inb)
FUNCTION_START(inw,4)
movq %rdi, %rdx
xorq %rax, %rax
inw (%dx)
FUNCTION_END(inw)
FUNCTION_START(inl,4)
movq %rdi, %rdx
xorq %rax, %rax
inl (%dx)
FUNCTION_END(inl)
FUNCTION_START(outb,8)
movq %rdi, %rdx
movq %rsi, %rax
outb (%dx)
FUNCTION_END(outb)
FUNCTION_START(outw,8)
movq %rdi, %rdx
movq %rsi, %rax
outw (%dx)
FUNCTION_END(outw)
FUNCTION_START(outl,8)
movq %rdi, %rdx
movq %rsi, %rax
outl (%dx)
FUNCTION_END(outl)
|
metux/xorg-xserver | 1,944 | hw/xfree86/os-support/solaris/solaris-ia32.S | / Copyright (c) 2004, Oracle and/or its affiliates.
/
/ Permission is hereby granted, free of charge, to any person obtaining a
/ copy of this software and associated documentation files (the "Software"),
/ to deal in the Software without restriction, including without limitation
/ the rights to use, copy, modify, merge, publish, distribute, sublicense,
/ and/or sell copies of the Software, and to permit persons to whom the
/ Software is furnished to do so, subject to the following conditions:
/
/ The above copyright notice and this permission notice (including the next
/ paragraph) shall be included in all copies or substantial portions of the
/ Software.
/
/ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
/ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
/ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
/ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
/ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
/ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
/ DEALINGS IN THE SOFTWARE.
#ifdef INLINE_ASM
#define FUNCTION_START(f,n) .inline f,n
#define FUNCTION_END(f) .end
#else
#define _ASM
#include <sys/asm_linkage.h>
#define FUNCTION_START(f,n) ENTRY(f)
#define FUNCTION_END(f) ret; SET_SIZE(f)
#endif
FUNCTION_START(inb,4)
movl (%esp), %edx
xorl %eax, %eax
inb (%dx)
FUNCTION_END(inb)
FUNCTION_START(inw,4)
movl (%esp), %edx
xorl %eax, %eax
inw (%dx)
FUNCTION_END(inw)
FUNCTION_START(inl,4)
movl (%esp), %edx
xorl %eax, %eax
inl (%dx)
FUNCTION_END(inl)
FUNCTION_START(outb,8)
movl (%esp), %edx
movl 4(%esp), %eax
outb (%dx)
FUNCTION_END(outb)
FUNCTION_START(outw,8)
movl (%esp), %edx
movl 4(%esp), %eax
outw (%dx)
FUNCTION_END(outw)
FUNCTION_START(outl,8)
movl (%esp), %edx
movl 4(%esp), %eax
outl (%dx)
FUNCTION_END(outl)
|
metux/xorg-xserver | 3,102 | hw/xfree86/os-support/solaris/sun_inout.s | / $XFree86: xc/programs/Xserver/hw/xfree86/os-support/sunos/sun_inout.s,v 1.1 2001/05/28 02:42:31 tsi Exp $
/
/ Copyright 1994-2001 The XFree86 Project, Inc. All Rights Reserved.
/
/ Permission is hereby granted, free of charge, to any person obtaining a copy
/ of this software and associated documentation files (the "Software"), to deal
/ in the Software without restriction, including without limitation the rights
/ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
/ copies of the Software, and to permit persons to whom the Software is
/ furnished to do so, subject to the following conditions:
/
/ The above copyright notice and this permission notice shall be included in
/ all copies or substantial portions of the Software.
/
/ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
/ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
/ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
/ XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
/ IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
/ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/
/ Except as contained in this notice, the name of the XFree86 Project shall not
/ be used in advertising or otherwise to promote the sale, use or other
/ dealings in this Software without prior written authorization from the
/ XFree86 Project.
/
/
/ File: sun_inout.s
/
/ Purpose: Provide inb(), inw(), inl(), outb(), outw(), outl() functions
/ for Solaris x86 using the ProWorks compiler by SunPro
/
/ Author: Installed into XFree86 SuperProbe by Doug Anson (danson@lgc.com)
/ Portions donated to XFree86 by Steve Dever (Steve.Dever@Eng.Sun.Com)
/
/ Synopsis: (c callable external declarations)
/ extern unsigned char inb(int port);
/ extern unsigned short inw(int port);
/ extern unsigned long inl(int port);
/ extern void outb(int port, unsigned char value);
/ extern void outw(int port, unsigned short value);
/ extern void outl(int port, unsigned long value);
/
.file "sunos_inout.s"
.text
.globl inb
.globl inw
.globl inl
.globl outb
.globl outw
.globl outl
/
/ unsigned char inb(int port);
/
.align 4
inb:
movl 4(%esp),%edx
subl %eax,%eax
inb (%dx)
ret
.type inb,@function
.size inb,.-inb
/
/ unsigned short inw(int port);
/
.align 4
inw:
movl 4(%esp),%edx
subl %eax,%eax
inw (%dx)
ret
.type inw,@function
.size inw,.-inw
/
/ unsigned long inl(int port);
/
.align 4
inl:
movl 4(%esp),%edx
inl (%dx)
ret
.type inl,@function
.size inl,.-inl
/
/ void outb(int port, unsigned char value);
/
.align 4
outb:
movl 4(%esp),%edx
movl 8(%esp),%eax
outb (%dx)
ret
.type outb,@function
.size outb,.-outb
/
/ void outw(int port, unsigned short value);
/
.align 4
outw:
movl 4(%esp),%edx
movl 8(%esp),%eax
outw (%dx)
ret
.type outw,@function
.size outw,.-outw
/
/ void outl(int port, unsigned long value);
/
.align 4
outl:
movl 4(%esp),%edx
movl 8(%esp),%eax
outl (%dx)
ret
.type outl,@function
.size outl,.-outl
|
metux/xorg-xserver | 3,946 | hw/xfree86/os-support/solaris/solaris-sparcv8plus.S | /* Copyright (c) 2004, Oracle and/or its affiliates.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifdef INLINE_ASM
#define FUNCTION_START(f,n) .inline f,n
#define FUNCTION_END(f) .end
#else
#define _ASM
#include <sys/asm_linkage.h>
#define FUNCTION_START(f,n) ENTRY(f)
#define FUNCTION_END(f) retl; nop; SET_SIZE(f)
#endif
/* Converted from common/compiler.h gcc inline format to Sun cc inline
* format by Kenjiro Tsuji
*
* The value 0x88 means ASI_PRIMARY_LITTLE.
* The store or load to/from the address space will be done
* as little-endian. In the original xrog code, the value
* is defined as the macro ASI_PL.
*
* In the original xorg code, "membar #StoreStore|#StoreLoad"
* is directly implemented as an instruction "0x8143e00a".
*
*/
FUNCTION_START(outb, 0)
stba %o1, [%o0] 0x88
membar #StoreStore|#StoreLoad
FUNCTION_END(outb)
FUNCTION_START(outw, 0)
stha %o1, [%o0] 0x88
membar #StoreStore|#StoreLoad
FUNCTION_END(outw)
FUNCTION_START(outl, 0)
sta %o1, [%o0] 0x88
membar #StoreStore|#StoreLoad
FUNCTION_END(outl)
FUNCTION_START(inb, 0)
lduba [%o0] 0x88, %o0
FUNCTION_END(inb)
FUNCTION_START(inw, 0)
lduha [%o0] 0x88, %o0
FUNCTION_END(inw)
FUNCTION_START(inl, 0)
lda [%o0] 0x88, %o0
FUNCTION_END(inl)
FUNCTION_START(xf86ReadMmio8, 0)
lduba [%o0 + %o1] 0x88, %o0
FUNCTION_END(xf86ReadMmio8)
FUNCTION_START(xf86ReadMmio16Be, 0)
lduh [%o0 + %o1], %o0
FUNCTION_END(xf86ReadMmio16Be)
FUNCTION_START(xf86ReadMmio16Le, 0)
lduha [%o0 + %o1] 0x88, %o0
FUNCTION_END(xf86ReadMmio16Le)
FUNCTION_START(xf86ReadMmio32Be, 0)
ld [%o0 + %o1], %o0
FUNCTION_END(xf86ReadMmio32Be)
FUNCTION_START(xf86ReadMmio32Le, 0)
lda [%o0 + %o1] 0x88, %o0
FUNCTION_END(xf86ReadMmio32Le)
FUNCTION_START(xf86WriteMmio8, 0)
stba %o2, [%o0 + %o1] 0x88
membar #StoreStore|#StoreLoad
FUNCTION_END(xf86WriteMmio8)
FUNCTION_START(xf86WriteMmio16Be, 0)
sth %o2, [%o0 + %o1]
membar #StoreStore|#StoreLoad
FUNCTION_END(xf86WriteMmio16Be)
FUNCTION_START(xf86WriteMmio16Le, 0)
stha %o2, [%o0 + %o1] 0x88
membar #StoreStore|#StoreLoad
FUNCTION_END(xf86WriteMmio16Le)
FUNCTION_START(xf86WriteMmio32Be, 0)
st %o2, [%o0 + %o1]
membar #StoreStore|#StoreLoad
FUNCTION_END(xf86WriteMmio32Be)
FUNCTION_START(xf86WriteMmio32Le, 0)
sta %o2, [%o0 + %o1] 0x88
membar #StoreStore|#StoreLoad
FUNCTION_END(xf86WriteMmio32Le)
FUNCTION_START(xf86WriteMmio8NB, 0)
add %o0, %o1, %o0
stba %o2, [%o0] 0x88
FUNCTION_END(xf86WriteMmio8NB)
FUNCTION_START(xf86WriteMmio16BeNB, 0)
sth %o2, [%o0 + %o1]
FUNCTION_END(xf86WriteMmio16BeNB)
FUNCTION_START(xf86WriteMmio16LeNB, 0)
stha %o2, [%o0 + %o1] 0x88
FUNCTION_END(xf86WriteMmio16LeNB)
FUNCTION_START(xf86WriteMmio32BeNB, 0)
st %o2, [%o0 + %o1]
FUNCTION_END(xf86WriteMmio32BeNB)
FUNCTION_START(xf86WriteMmio32LeNB, 0)
sta %o2, [%o0 + %o1] 0x88
FUNCTION_END(xf86WriteMmio32LeNB)
|
MichaelBell/rp1-hacking | 1,098 | oneshot/start.s | .cpu cortex-m3
.thumb
.syntax unified
.section .boot,"ax"
.align 2
.thumb_func
.globl _entry
_entry:
/* Unpatch the hook */
push {r4,r5,r6,r7,lr}
ldr r6, =0x200007c8
ldr r7, =0xf04f281f
str r7, [r6]
/* Setup UART 1 */
ldr r2, =0x40034000 // UART0 SET BASE
movs r1, #0x1b
str r1, [r2, #0x24] // Set divisor to 115200 baud
movs r1, #0x8
str r1, [r2, #0x28]
movs r1, #0x70
str r1, [r2, #0x2c] // UART LCR_H. Enable FIFOs, 8 bits, 1 stop, no parity
mov r1, #0x101
str r1, [r2, #0x30] // UART CR: Enable, transmit only
mov r1, #0x82 // Function 2 (UART1)
ldr r2, =0x400d0000
str r1, [r2, #0x4] // GPIO 0
mov r1, #0x16 // Pads
ldr r2, =0x400f0000
str r1, [r2, #0x4] // GPIO 0
/* Clear bss */
ldr r4, =__bss_start__
ldr r5, =__bss_end__
cmp r4, r5
bge 1f
movs r6, #0
mov r7, r6
_bss_loop:
stmia r4!, {r6,r7}
cmp r4, r5
blt _bss_loop
1:
/* Call main */
bl main
pop {r4,r5,r6,r7,lr}
/* Resume to patched function */
b 0x200007c8
|
michalsc/Emu68-tools | 1,846 | VideoCore.card/src/vpu/block_copy.s | #
# Copyright © 2021 Michal Schulz <michal.schulz@gmx.de>
# https://github.com/michalsc
#
# This Source Code Form is subject to the terms of the
# Mozilla Public License, v. 2.0. If a copy of the MPL was not distributed
# with this file, You can obtain one at http://mozilla.org/MPL/2.0/.
#
# Copy block of memory using VPU - This function does not support overlap!
# Arguments:
# r0 : start address of surce
# r1 : start address of destination
# r2 : block length in bytes
mov r3, 64
cmp r2, 4096
bcs smaller_than_4K
loop:
vld HY(0++, 0), (r0+=r3) REP 64
add r0, 4096
sub r2, 4096
cmp r2, 4096
vst HY(0++, 0), (r1+=r3) REP 64
add r1, 4096
bcc loop
smaller_than_4K:
cmp r2, 1024
bcs smaller_than_1K
loop2: vld HY(0++, 0), (r0+=r3) REP 16
add r0, 1024
sub r2, 1024
cmp r2, 1024
vst HY(0++, 0), (r1+=r3) REP 16
add r1, 1024
bcc loop2
smaller_than_1K:
cmp r2, 256
bcs smaller_than_256
loop3: vld HY(0++, 0), (r0+=r3) REP 4
add r0, 256
sub r2, 256
cmp r2, 256
vst HY(0++, 0), (r1+=r3) REP 4
add r1, 256
bcc loop3
smaller_than_256:
cmp r2, 64
bcs smaller_than_64
loop4: vld HY(0, 0), (r0)
add r0, 64
sub r2, 64
cmp r2, 64
vst HY(0, 0), (r1)
add r1, 64
bcc loop4
smaller_than_64:
cmp r2, 4
bcs smaller_than_4
loop5: ld r4, (r0)
st r4, (r1)
add r0, 4
add r1, 4
sub r2, 4
cmp r2, 4
bcc loop5
smaller_than_4:
cmp r2, 0
beq exit
ldb r4, (r0)
stb r4, (r1)
add r0, 1
add r1, 1
sub r2, 1
b smaller_than_4
exit: rts |
MinGiKYUNG/compiler_class | 3,778 | 2wk/example1/main.S | .file "main.c"
.intel_syntax noprefix
# GNU C23 (Rev8, Built by MSYS2 project) version 15.2.0 (x86_64-w64-mingw32)
# compiled by GNU C version 15.2.0, GMP version 6.3.0, MPFR version 4.2.2, MPC version 1.3.1, isl version isl-0.27-GMP
# GGC heuristics: --param ggc-min-expand=100 --param ggc-min-heapsize=131072
# options passed: -masm=intel -mtune=generic -march=nocona -g -O0
.text
.Ltext0:
.cfi_sections .debug_frame
.file 0 "C:/Users/mingi/compiler_playground/example1" "main.c"
.globl main
.def main; .scl 2; .type 32; .endef
.seh_proc main
main:
.LFB101:
.file 1 "main.c"
.loc 1 3 16
.cfi_startproc
push rbp #
.seh_pushreg rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
mov rbp, rsp #,
.seh_setframe rbp, 0
.cfi_def_cfa_register 6
sub rsp, 48 #,
.seh_stackalloc 48
.seh_endprologue
# main.c:3: int main(void) {
.loc 1 3 16
call __main #
# main.c:4: int r = 3+4;
.loc 1 4 9
mov DWORD PTR -4[rbp], 7 # r,
# main.c:5: return 0;
.loc 1 5 16
mov eax, 0 # _2,
# main.c:6: }
.loc 1 6 1
add rsp, 48 #,
pop rbp #
.cfi_restore 6
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE101:
.seh_endproc
.Letext0:
.section .debug_info,"dr"
.Ldebug_info0:
.long 0x104
.word 0x5
.byte 0x1
.byte 0x8
.secrel32 .Ldebug_abbrev0
.uleb128 0x2
.ascii "GNU C23 15.2.0 -masm=intel -mtune=generic -march=nocona -g -O0\0"
.byte 0x1d
.byte 0x3
.long 0x31647
.secrel32 .LASF0
.secrel32 .LASF1
.quad .Ltext0
.quad .Letext0-.Ltext0
.secrel32 .Ldebug_line0
.uleb128 0x1
.byte 0x1
.byte 0x6
.ascii "char\0"
.uleb128 0x1
.byte 0x8
.byte 0x7
.ascii "long long unsigned int\0"
.uleb128 0x1
.byte 0x8
.byte 0x5
.ascii "long long int\0"
.uleb128 0x1
.byte 0x2
.byte 0x7
.ascii "short unsigned int\0"
.uleb128 0x1
.byte 0x4
.byte 0x5
.ascii "int\0"
.uleb128 0x1
.byte 0x4
.byte 0x5
.ascii "long int\0"
.uleb128 0x1
.byte 0x4
.byte 0x7
.ascii "unsigned int\0"
.uleb128 0x3
.ascii "main\0"
.byte 0x1
.byte 0x3
.byte 0x5
.long 0xb7
.quad .LFB101
.quad .LFE101-.LFB101
.uleb128 0x1
.byte 0x9c
.uleb128 0x4
.ascii "r\0"
.byte 0x1
.byte 0x4
.byte 0x9
.long 0xb7
.uleb128 0x2
.byte 0x91
.sleb128 -20
.byte 0
.byte 0
.section .debug_abbrev,"dr"
.Ldebug_abbrev0:
.uleb128 0x1
.uleb128 0x24
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3e
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x11
.byte 0x1
.uleb128 0x25
.uleb128 0x8
.uleb128 0x13
.uleb128 0xb
.uleb128 0x90
.uleb128 0xb
.uleb128 0x91
.uleb128 0x6
.uleb128 0x3
.uleb128 0x1f
.uleb128 0x1b
.uleb128 0x1f
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x7
.uleb128 0x10
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x3
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x39
.uleb128 0xb
.uleb128 0x27
.uleb128 0x19
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x7c
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x4
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x39
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.byte 0
.section .debug_aranges,"dr"
.long 0x2c
.word 0x2
.secrel32 .Ldebug_info0
.byte 0x8
.byte 0
.word 0
.word 0
.quad .Ltext0
.quad .Letext0-.Ltext0
.quad 0
.quad 0
.section .debug_line,"dr"
.Ldebug_line0:
.section .debug_str,"dr"
.section .debug_line_str,"dr"
.LASF1:
.ascii "C:\\Users\\mingi\\compiler_playground\\example1\0"
.LASF0:
.ascii "main.c\0"
.def __main; .scl 2; .type 32; .endef
.ident "GCC: (Rev8, Built by MSYS2 project) 15.2.0"
|
miretskiy/simba | 4,585 | internal/ffi/syso_amd64.s | // Code generated by gen_trampolines; DO NOT EDIT.
//go:build amd64
// +build amd64
#include "textflag.h"
// func sum_u8_32_raw() uint32
TEXT ·sum_u8_32_raw(SB), NOSPLIT, $0-20
MOVQ ptr+0(FP), DI
MOVQ n+8(FP), SI
CALL sum_u8_32(SB)
MOVL AX, ret+16(FP)
RET
// func sum_u8_64_raw() uint32
TEXT ·sum_u8_64_raw(SB), NOSPLIT, $0-20
MOVQ ptr+0(FP), DI
MOVQ n+8(FP), SI
CALL sum_u8_64(SB)
MOVL AX, ret+16(FP)
RET
// func sum_u8_16_raw() uint32
TEXT ·sum_u8_16_raw(SB), NOSPLIT, $0-20
MOVQ ptr+0(FP), DI
MOVQ n+8(FP), SI
CALL sum_u8_16(SB)
MOVL AX, ret+16(FP)
RET
// func is_ascii32_raw() uint8
TEXT ·is_ascii32_raw(SB), NOSPLIT, $0-17
MOVQ ptr+0(FP), DI
MOVQ n+8(FP), SI
CALL is_ascii32(SB)
MOVB AL, ret+16(FP)
RET
// func is_ascii64_raw() uint8
TEXT ·is_ascii64_raw(SB), NOSPLIT, $0-17
MOVQ ptr+0(FP), DI
MOVQ n+8(FP), SI
CALL is_ascii64(SB)
MOVB AL, ret+16(FP)
RET
// func is_ascii16_raw() uint8
TEXT ·is_ascii16_raw(SB), NOSPLIT, $0-17
MOVQ ptr+0(FP), DI
MOVQ n+8(FP), SI
CALL is_ascii16(SB)
MOVB AL, ret+16(FP)
RET
// func validate_u8_lut32_raw() uint8
TEXT ·validate_u8_lut32_raw(SB), NOSPLIT, $0-25
MOVQ ptr+0(FP), DI
MOVQ n+8(FP), SI
MOVQ lut+16(FP), DX
CALL validate_u8_lut32(SB)
MOVB AL, ret+24(FP)
RET
// func validate_u8_lut64_raw() uint8
TEXT ·validate_u8_lut64_raw(SB), NOSPLIT, $0-25
MOVQ ptr+0(FP), DI
MOVQ n+8(FP), SI
MOVQ lut+16(FP), DX
CALL validate_u8_lut64(SB)
MOVB AL, ret+24(FP)
RET
// func validate_u8_lut16_raw() uint8
TEXT ·validate_u8_lut16_raw(SB), NOSPLIT, $0-25
MOVQ ptr+0(FP), DI
MOVQ n+8(FP), SI
MOVQ lut+16(FP), DX
CALL validate_u8_lut16(SB)
MOVB AL, ret+24(FP)
RET
// func map_u8_lut32_raw()
TEXT ·map_u8_lut32_raw(SB), NOSPLIT, $0-32
MOVQ src+0(FP), DI
MOVQ n+8(FP), SI
MOVQ dst+16(FP), DX
MOVQ lut+24(FP), CX
CALL map_u8_lut32(SB)
RET
// func map_u8_lut64_raw()
TEXT ·map_u8_lut64_raw(SB), NOSPLIT, $0-32
MOVQ src+0(FP), DI
MOVQ n+8(FP), SI
MOVQ dst+16(FP), DX
MOVQ lut+24(FP), CX
CALL map_u8_lut64(SB)
RET
// func map_u8_lut16_raw()
TEXT ·map_u8_lut16_raw(SB), NOSPLIT, $0-32
MOVQ src+0(FP), DI
MOVQ n+8(FP), SI
MOVQ dst+16(FP), DX
MOVQ lut+24(FP), CX
CALL map_u8_lut16(SB)
RET
// func eq_u8_masks32_raw() uintptr
TEXT ·eq_u8_masks32_raw(SB), NOSPLIT, $0-40
MOVQ src+0(FP), DI
MOVQ n+8(FP), SI
MOVBLZX needle+16(FP), DX
MOVQ out+24(FP), CX
CALL eq_u8_masks32(SB)
MOVQ AX, ret+32(FP)
RET
// func eq_u8_masks64_raw() uintptr
TEXT ·eq_u8_masks64_raw(SB), NOSPLIT, $0-40
MOVQ src+0(FP), DI
MOVQ n+8(FP), SI
MOVBLZX needle+16(FP), DX
MOVQ out+24(FP), CX
CALL eq_u8_masks64(SB)
MOVQ AX, ret+32(FP)
RET
// func eq_u8_masks16_raw() uintptr
TEXT ·eq_u8_masks16_raw(SB), NOSPLIT, $0-40
MOVQ src+0(FP), DI
MOVQ n+8(FP), SI
MOVBLZX needle+16(FP), DX
MOVQ out+24(FP), CX
CALL eq_u8_masks16(SB)
MOVQ AX, ret+32(FP)
RET
// func noop_raw()
TEXT ·noop_raw(SB), NOSPLIT, $0-0
CALL noop(SB)
RET
// func crc32_update_32_raw() uint32
TEXT ·crc32_update_32_raw(SB), NOSPLIT, $0-24
MOVQ ptr+0(FP), DI
MOVQ n+8(FP), SI
MOVL init+16(FP), DX
CALL crc32_update_32(SB)
MOVL AX, ret+24(FP)
RET
// func crc32_update_64_raw() uint32
TEXT ·crc32_update_64_raw(SB), NOSPLIT, $0-24
MOVQ ptr+0(FP), DI
MOVQ n+8(FP), SI
MOVL init+16(FP), DX
CALL crc32_update_64(SB)
MOVL AX, ret+24(FP)
RET
// func crc32_combine_raw() uint32
TEXT ·crc32_combine_raw(SB), NOSPLIT, $0-20
MOVL crc1+0(FP), DI
MOVL crc2+4(FP), SI
MOVQ len2+8(FP), DX
CALL crc32_combine(SB)
MOVL AX, ret+16(FP)
RET
// func trampoline_sanity_raw() uintptr
TEXT ·trampoline_sanity_raw(SB), NOSPLIT, $0-56
MOVQ ptr+0(FP), DI
MOVQ n+8(FP), SI
MOVL val32+16(FP), DX
MOVBLZX val8+20(FP), CX
MOVQ val64+24(FP), R8
MOVQ f64bits+32(FP), R9
SUBQ $8, SP
MOVL f32bits+40(FP), AX
MOVL AX, 0(SP)
CALL trampoline_sanity(SB)
ADDQ $8, SP
MOVQ AX, ret+48(FP)
RET
// func trampoline_echo_raw()
TEXT ·trampoline_echo_raw(SB), NOSPLIT, $0-56
MOVQ ptr+0(FP), DI
MOVQ n+8(FP), SI
MOVL v32+16(FP), DX
MOVBLZX v8+20(FP), CX
MOVQ v64+24(FP), R8
MOVQ f64bits+32(FP), R9
SUBQ $16, SP
MOVL f32bits+40(FP), AX
MOVL AX, 0(SP)
MOVQ out+44(FP), AX
MOVQ AX, 8(SP)
CALL trampoline_echo(SB)
ADDQ $16, SP
RET
|
miretskiy/simba | 4,458 | internal/ffi/syso_arm64.s | // Code generated by gen_trampolines; DO NOT EDIT.
//go:build arm64
// +build arm64
#include "textflag.h"
// func sum_u8_32_raw() uint32
TEXT ·sum_u8_32_raw(SB), NOSPLIT, $0-20
MOVD ptr+0(FP), R0
MOVD n+8(FP), R1
CALL sum_u8_32(SB)
MOVW R0, ret+16(FP)
RET
// func sum_u8_64_raw() uint32
TEXT ·sum_u8_64_raw(SB), NOSPLIT, $0-20
MOVD ptr+0(FP), R0
MOVD n+8(FP), R1
CALL sum_u8_64(SB)
MOVW R0, ret+16(FP)
RET
// func sum_u8_16_raw() uint32
TEXT ·sum_u8_16_raw(SB), NOSPLIT, $0-20
MOVD ptr+0(FP), R0
MOVD n+8(FP), R1
CALL sum_u8_16(SB)
MOVW R0, ret+16(FP)
RET
// func is_ascii32_raw() uint8
TEXT ·is_ascii32_raw(SB), NOSPLIT, $0-17
MOVD ptr+0(FP), R0
MOVD n+8(FP), R1
CALL is_ascii32(SB)
MOVBU R0, ret+16(FP)
RET
// func is_ascii64_raw() uint8
TEXT ·is_ascii64_raw(SB), NOSPLIT, $0-17
MOVD ptr+0(FP), R0
MOVD n+8(FP), R1
CALL is_ascii64(SB)
MOVBU R0, ret+16(FP)
RET
// func is_ascii16_raw() uint8
TEXT ·is_ascii16_raw(SB), NOSPLIT, $0-17
MOVD ptr+0(FP), R0
MOVD n+8(FP), R1
CALL is_ascii16(SB)
MOVBU R0, ret+16(FP)
RET
// func validate_u8_lut32_raw() uint8
TEXT ·validate_u8_lut32_raw(SB), NOSPLIT, $0-25
MOVD ptr+0(FP), R0
MOVD n+8(FP), R1
MOVD lut+16(FP), R2
CALL validate_u8_lut32(SB)
MOVBU R0, ret+24(FP)
RET
// func validate_u8_lut64_raw() uint8
TEXT ·validate_u8_lut64_raw(SB), NOSPLIT, $0-25
MOVD ptr+0(FP), R0
MOVD n+8(FP), R1
MOVD lut+16(FP), R2
CALL validate_u8_lut64(SB)
MOVBU R0, ret+24(FP)
RET
// func validate_u8_lut16_raw() uint8
TEXT ·validate_u8_lut16_raw(SB), NOSPLIT, $0-25
MOVD ptr+0(FP), R0
MOVD n+8(FP), R1
MOVD lut+16(FP), R2
CALL validate_u8_lut16(SB)
MOVBU R0, ret+24(FP)
RET
// func map_u8_lut32_raw()
TEXT ·map_u8_lut32_raw(SB), NOSPLIT, $0-32
MOVD src+0(FP), R0
MOVD n+8(FP), R1
MOVD dst+16(FP), R2
MOVD lut+24(FP), R3
CALL map_u8_lut32(SB)
RET
// func map_u8_lut64_raw()
TEXT ·map_u8_lut64_raw(SB), NOSPLIT, $0-32
MOVD src+0(FP), R0
MOVD n+8(FP), R1
MOVD dst+16(FP), R2
MOVD lut+24(FP), R3
CALL map_u8_lut64(SB)
RET
// func map_u8_lut16_raw()
TEXT ·map_u8_lut16_raw(SB), NOSPLIT, $0-32
MOVD src+0(FP), R0
MOVD n+8(FP), R1
MOVD dst+16(FP), R2
MOVD lut+24(FP), R3
CALL map_u8_lut16(SB)
RET
// func eq_u8_masks32_raw() uintptr
TEXT ·eq_u8_masks32_raw(SB), NOSPLIT, $0-40
MOVD src+0(FP), R0
MOVD n+8(FP), R1
MOVBU needle+16(FP), R2
MOVD out+24(FP), R3
CALL eq_u8_masks32(SB)
MOVD R0, ret+32(FP)
RET
// func eq_u8_masks64_raw() uintptr
TEXT ·eq_u8_masks64_raw(SB), NOSPLIT, $0-40
MOVD src+0(FP), R0
MOVD n+8(FP), R1
MOVBU needle+16(FP), R2
MOVD out+24(FP), R3
CALL eq_u8_masks64(SB)
MOVD R0, ret+32(FP)
RET
// func eq_u8_masks16_raw() uintptr
TEXT ·eq_u8_masks16_raw(SB), NOSPLIT, $0-40
MOVD src+0(FP), R0
MOVD n+8(FP), R1
MOVBU needle+16(FP), R2
MOVD out+24(FP), R3
CALL eq_u8_masks16(SB)
MOVD R0, ret+32(FP)
RET
// func noop_raw()
TEXT ·noop_raw(SB), NOSPLIT, $0-0
CALL noop(SB)
RET
// func crc32_update_32_raw() uint32
TEXT ·crc32_update_32_raw(SB), NOSPLIT, $0-24
MOVD ptr+0(FP), R0
MOVD n+8(FP), R1
MOVW init+16(FP), R2
CALL crc32_update_32(SB)
MOVW R0, ret+24(FP)
RET
// func crc32_update_64_raw() uint32
TEXT ·crc32_update_64_raw(SB), NOSPLIT, $0-24
MOVD ptr+0(FP), R0
MOVD n+8(FP), R1
MOVW init+16(FP), R2
CALL crc32_update_64(SB)
MOVW R0, ret+24(FP)
RET
// func crc32_combine_raw() uint32
TEXT ·crc32_combine_raw(SB), NOSPLIT, $0-20
MOVW crc1+0(FP), R0
MOVW crc2+4(FP), R1
MOVD len2+8(FP), R2
CALL crc32_combine(SB)
MOVW R0, ret+16(FP)
RET
// func trampoline_sanity_raw() uintptr
TEXT ·trampoline_sanity_raw(SB), NOSPLIT, $0-56
MOVD ptr+0(FP), R0
MOVD n+8(FP), R1
MOVW val32+16(FP), R2
MOVBU val8+20(FP), R3
MOVD val64+24(FP), R4
MOVD f64bits+32(FP), R5
MOVW f32bits+40(FP), R6
CALL trampoline_sanity(SB)
MOVD R0, ret+48(FP)
RET
// func trampoline_echo_raw()
TEXT ·trampoline_echo_raw(SB), NOSPLIT, $0-56
MOVD ptr+0(FP), R0
MOVD n+8(FP), R1
MOVW v32+16(FP), R2
MOVBU v8+20(FP), R3
MOVD v64+24(FP), R4
MOVD f64bits+32(FP), R5
MOVW f32bits+40(FP), R6
MOVD out+48(FP), R7
CALL trampoline_echo(SB)
RET
|
Misaka-xiaolan/STM32_USB_Audio_Card | 12,523 | Code/startup_stm32g431xx.s | /**
******************************************************************************
* @file startup_stm32g431xx.s
* @author MCD Application Team
* @brief STM32G431xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word RTC_TAMP_LSECSS_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word 0
.word ADC1_2_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word FDCAN1_IT0_IRQHandler
.word FDCAN1_IT1_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word 0
.word 0
.word LPTIM1_IRQHandler
.word 0
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word 0
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word 0
.word 0
.word UCPD1_IRQHandler
.word COMP1_2_3_IRQHandler
.word COMP4_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word CRS_IRQHandler
.word SAI1_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word RNG_IRQHandler
.word LPUART1_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word DMAMUX_OVR_IRQHandler
.word 0
.word 0
.word DMA2_Channel6_IRQHandler
.word 0
.word 0
.word CORDIC_IRQHandler
.word FMAC_IRQHandler
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_TAMP_LSECSS_IRQHandler
.thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak UCPD1_IRQHandler
.thumb_set UCPD1_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_IRQHandler
.thumb_set COMP4_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak DMAMUX_OVR_IRQHandler
.thumb_set DMAMUX_OVR_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak CORDIC_IRQHandler
.thumb_set CORDIC_IRQHandler,Default_Handler
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
|
Misaka-xiaolan/STM32_USB_Audio_Card | 19,260 | Code/MDK-ARM/startup_stm32g431xx.s | ;*******************************************************************************
;* @File Name : startup_stm32g431xx.s
;* @Author : MCD Application Team
;* @Brief : Vector table for MDK-ARM toolchain
;*******************************************************************************
;* Description : STM32G431xx Mainstream devices vector table for
;* MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x0
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD 0 ; Reserved
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD UCPD1_IRQHandler ; UCPD1
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_IRQHandler ; COMP4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CRS_IRQHandler ; CRS Interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CORDIC_IRQHandler ; CORDIC
DCD FMAC_IRQHandler ; FMAC
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT RTC_TAMP_LSECSS_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT UCPD1_IRQHandler [WEAK]
EXPORT COMP1_2_3_IRQHandler [WEAK]
EXPORT COMP4_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT DMAMUX_OVR_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT CORDIC_IRQHandler [WEAK]
EXPORT FMAC_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
RTC_TAMP_LSECSS_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
ADC1_2_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
FDCAN1_IT0_IRQHandler
FDCAN1_IT1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
LPTIM1_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
UCPD1_IRQHandler
COMP1_2_3_IRQHandler
COMP4_IRQHandler
CRS_IRQHandler
SAI1_IRQHandler
FPU_IRQHandler
RNG_IRQHandler
LPUART1_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
DMAMUX_OVR_IRQHandler
DMA2_Channel6_IRQHandler
CORDIC_IRQHandler
FMAC_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
missimer/x86-64-kernel-boot | 3,313 | kernel/boot.S | #include "arch/x86_64/gdt.h"
#include "arch/x86_64/mmu.h"
#include "kernel.h"
#include "sizes.h"
#include "multiboot2.h"
#include "arch/x86_64/msr.h"
.SET HEADER_LENGTH, header_end - header_start
.SET CHECKSUM, -(MULTIBOOT2_HEADER_MAGIC + MULTIBOOT_ARCHITECTURE_I386 + HEADER_LENGTH)
.section .multiboot
header_start:
.long MULTIBOOT2_HEADER_MAGIC
.long MULTIBOOT_ARCHITECTURE_I386
.long HEADER_LENGTH
.long CHECKSUM
// multiboot tags go here
.short MULTIBOOT_HEADER_TAG_END
.short 0 // flags, none set
.long 8 // size, including itself (short + short + long)
header_end:
.code32
.section .bss
.comm pml4, PML4_SIZE, PML4_ALIGNMENT
.comm low_pdpt, PDPT_SIZE, PDPT_ALIGNMENT
.comm high_pdpt, PDPT_SIZE, PDPT_ALIGNMENT
.comm low_page_directory_table, PAGE_DIRECTORY_SIZE, PAGE_DIRECTORY_ALIGNMENT
.comm high_page_directory_table, PAGE_DIRECTORY_SIZE, PAGE_DIRECTORY_ALIGNMENT
.comm tmp_stack, KERNEL_BOOT_STACK_SIZE, KERNEL_BOOT_STACK_ALIGNMENT
.data
.align GDT_TABLE_ALIGNMENT
gdt_table:
.8byte GDT_FIRST_ENTRY
.8byte GDT_KERNEL_ENTRY
gdt_table_end:
.skip (GDT_TABLE_SIZE - (gdt_table_end - gdt_table))
gdt_ptr:
.short GDT_TABLE_SIZE - 1
.long gdt_table
.section .text
.global _start
.type _start, @function
_start:
movl $tmp_stack + KERNEL_BOOT_STACK_SIZE, %esp
movl $low_pdpt, %eax
or $(MMU_PRESENT | MMU_WRITABLE), %eax
movl %eax, pml4 + (PML4_ADDR_TO_ENTRY_INDEX(KERNEL_PHYSICAL_START) * PML4_ENTRY_SIZE)
movl $high_pdpt, %eax
or $(MMU_PRESENT | MMU_WRITABLE), %eax
movl %eax, pml4 + (PML4_ADDR_TO_ENTRY_INDEX(KERNEL_VIRTUAL_START) * PML4_ENTRY_SIZE)
movl $low_page_directory_table, %eax
or $(MMU_PRESENT | MMU_WRITABLE), %eax
movl %eax, low_pdpt + (PDPT_ADDR_TO_ENTRY_INDEX(KERNEL_PHYSICAL_START) * PDPT_ENTRY_SIZE)
movl $high_page_directory_table, %eax
or $(MMU_PRESENT | MMU_WRITABLE), %eax
movl %eax, high_pdpt + (PDPT_ADDR_TO_ENTRY_INDEX(KERNEL_VIRTUAL_START) * PDPT_ENTRY_SIZE)
mov $0, %ecx
movl $_kernel_physical_end, %esi
shrl $TWO_MEGABYTES_SHIFT, %esi
addl $1, %esi
page_directory_table_loop:
movl $TWO_MEGABYTES, %eax
mul %ecx
or $(MMU_PRESENT | MMU_WRITABLE | MMU_PDE_TWO_MB), %eax
movl %eax, low_page_directory_table(, %ecx, PAGE_DIRECTORY_ENTRY_SIZE)
movl %eax, high_page_directory_table(, %ecx, PAGE_DIRECTORY_ENTRY_SIZE)
inc %ecx
cmp %esi, %ecx
jne page_directory_table_loop // if not equal redo loop
movl $pml4, %eax
movl %eax, %cr3
movl $KERNEL_CR4, %eax
movl %eax, %cr4
movl $MSR_EFER, %ecx
rdmsr
or $MSR_EFER_LME, %eax
wrmsr
movl $KERNEL_CR0, %eax
movl %eax, %cr0
lgdt gdt_ptr
ljmp $(KERNEL_GDT_ENTRY * GDT_ENTRY_SIZE), $_start64
cli
hlt
.code64
.global _start64
.type _start64, @function
_start64:
// Setup segment selectors
movw $0, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %fs
movw %ax, %gs
movw %ax, %ss
call Kernel_Main
// Should never reach here
cli
hlt
1:
jmp 1b
|
mist64/final_cartridge | 2,645 | bank3/freezer_reset.s | ;*****************************************************************************
; Final Cartridge III reconstructed source code
;
; This file implements the functions of the reset menu of the freezer
;*****************************************************************************
.setcpu "6502x"
.include "../core/kernal.i"
.include "../core/fc3ioreg.i"
.include "persistent.i"
.import _jmp_bank,_enable_fcbank0,_disable_fc3rom_set_01
.importzp __FREEZERZP_START__,__FREEZERZP_SIZE__
.import __freezer_restore_1_LOAD__,__freezer_restore_1_SIZE__
.import __freezer_restore_2_RUN__,__freezer_restore_2_SIZE__
.importzp freezer_mem_a,freezer_mem_a_val,freezer_mem_b,freezer_mem_b_val
.import monitor
.import freezer_screenshot_prepare
.segment "freezer_monitor"
init_load_and_basic_vectors = $8021
.global freezer_goto_monitor
freezer_goto_monitor:
ldx #$FF
txs
jsr IOINIT_direct
jsr RESTOR_direct
lda #$00
tay
: sta $0002,y ; Clear zeropage
sta $0200,y ; Clear $02xx
iny
bne :-
ldx #<$A000
ldy #>$A000
jsr $FD8D ; Set top, bottom of memory and screen base
jsr CINT_direct
jsr $E453 ; Routine: Set BASIC vectors (case 0x300..case 0x309)
jsr $E3BF ; Routine: Set USR instruction and memory for BASIC
lda #>(monitor-1)
pha
lda #<(monitor-1)
pha
lda #>(init_load_and_basic_vectors-1)
pha
lda #<(init_load_and_basic_vectors-1)
pha
jmp _enable_fcbank0
.segment "freezer_reset"
.global freezer_zero_fill
freezer_zero_fill:
ldy #$00
sty $AC
lda #$08
sta $AD
lda #$33
sei
sta $01
tya
: sta ($AC),y
iny
bne :-
inc $AD
bne :-
c64_reset:
lda #>(START-1)
pha
lda #<(START-1)
pha
lda #$37
sta $01
jmp _enable_fcbank0
.global write_mg87_and_reset
write_mg87_and_reset:
ldx #sizeof_MG87 - 1
: lda MG87,x
sta $CFFC,x
dex
bpl :-
bmi c64_reset ; always
MG87: .byte "MG87"
sizeof_MG87 = .sizeof(MG87)
;
; Got to the printer settings menu
;
.global freezer_goto_settings
freezer_goto_settings:
ldy #__FREEZERZP_SIZE__ - 1
lda freezer_mem_a_val
: sta (freezer_mem_a),y
dey
bpl :-
ldy #<__freezer_restore_1_SIZE__ - 1
lda freezer_mem_b_val
: sta (freezer_mem_b),y
dey
bpl :-
jmp freezer_screenshot_prepare ; $A000
|
mist64/final_cartridge | 10,515 | bank3/desktop_helper2.s | ;*****************************************************************************
; Final Cartridge III reconstructed source code
;
; After the user has reordered the entries in a directory using the desktop,
; this code writes back the directory to disk in the desired order.
;*****************************************************************************
.setcpu "6502x"
.include "../core/kernal.i"
.include "../core/fc3ioreg.i"
.include "persistent.i"
.import load_ae_rom_hidden
.import __diredit_cmds_LOAD__,__diredit_cmds_RUN__,__diredit_cmds_SIZE__
.segment "desktop_helper_2"
.global W9200
W9200:
jsr write_directory_back_to_disk
lda #fcio_nmi_line | fcio_bank_0
jmp _jmp_bank
.global fill_loop
write_directory_back_to_disk:
; Fill $A000..$BFFF with #$00
lda #>$A000
sta $AD
ldx #$20 ; Fill $2000 bytes
lda #$00
tay
sta $AC
fill_loop:
: sta ($AC),y
iny
bne :-
inc $AD
dex
bne :-
; Copy directory editing commands to low RAM
ldx #<(__diredit_cmds_SIZE__-1)
: lda __diredit_cmds_LOAD__,x
sta $0202,x
dex
bpl :-
jsr open_hash_on_chan_2
lda #$00
sta $AC
sta $AE
sta $C1
lda #>$A000
sta $AD
: jsr send_read_block
jsr send_seek_0
jsr read_sector_from_chan_2
inc $AD ; Increasepointer for next sector
cpx #$00 ; End of directory?
beq directory_read_complete
cpx #18 ; Not on track 18?
bne close ; Then blast off.
cmp #19 ; Sector >= 19?
bcs close ; Then blast off.
jsr nibble2ascii
; Store sector number in command
stx read_block+10
sta read_block+11
lda $AD
cmp #$B0 ; Do not read beyond $B000
bcc :-
close:
jsr close_chn2
lda #$80 ; DEVICE NOT PRESENT ERROR
sta $90 ; Statusbyte ST of I/O KERNAL
rts
directory_read_complete:
;
; The old directory is stored at $A000. Now build the new directory
; at $B000.
;
lda #>$B000
sta $C2
lda $0200
sta $C3
lda $0201
sta $C4
; Count the number of dir entries
ldy #$00
sty $AE
sty $0200
lda #>$A000
sta $AF
ldy #$02 ; Get file type
@1: jsr _load_ae_rom_hidden
bpl :+ ; If slot not in use, skip.
inc $0200 ; Count a dir entry.
: jsr next_dir_entry
bcc @1 ; Last dir entry?
next_file:
; We search the entire directory for every file name, so start at $A000
lda #>$A000
sta $AF
ldy #<$A000
sty $AE
; Y=0
lda ($C3),y
tax
bne :+ ; All files processed?
jmp write_dir_to_disk ; Then write dir to disk.
: jsr inc_c3c4_beyond_z
txa
bmi insert_line ; Do we need to insert a line?
dec $0200
process_dir_entry:
ldy #$02 ; Get file type
jsr _load_ae_rom_hidden
bpl entry_not_found
; Adjust pointer to file name
lda #$05
ora $AE
sta $AE
; Compare file name
ldy #$00
: lda ($C3),y
beq :+
jsr _load_ae_rom_hidden
cmp ($C3),y
bne entry_not_found ; File name not equal
iny
cpy #$11 ; If desktop passes too long file name (should not occur)
bne :-
beq no_space_left
: cpy #$10
beq :+
jsr _load_ae_rom_hidden
cmp #$A0 ; First character beyond file name must be white space ($A0)
bne entry_not_found
: ; We found the file name in the directory
iny
tya
jsr add_to_c3c4
ldy #$00
lda $AE
and #$F0 ; Reset pointer to start of file entry
sta $AE
; Copy the entry to destination
lda #$00
sta ($C1),y
iny
sta ($C1),y
iny
: jsr _load_ae_rom_hidden
sta ($C1),y
iny
cpy #$20
bne :-
inc_dest_ptr:
; Increase destination pointer
tya
clc
adc $C1
sta $C1
bcc next_file
inc $C2
lda $C2
cmp #>$C000 ; Destination buffer full?
bcc next_file
no_space_left:
@c: jmp close
entry_not_found:
jsr next_dir_entry
bcs no_space_left
jmp process_dir_entry
.global next_dir_entry
next_dir_entry:
lda $AE
and #$F0
clc
adc #$20
sta $AE
bcc :+
inc $AF
: lda $AF
cmp $AD
rts
insert_line:
ldy #$FF
jsr inc_c3c4_beyond_z
ldy #$00
: lda dirline,y
sta ($C1),y
iny
cpy #$20
bne :-
beq inc_dest_ptr ; Always
write_dir_to_disk:
lda $0200
bne no_space_left
; Start at sector 1
lda #'0'
sta write_block+10
lda #'1'
sta write_block+11
lda $C1
bne :+
dec $C2 ; Prevent writing an empty sector
: lda #<$B000
sta $AE
lda #>$B000
sta $AF
lda #$02
sta $AC
next_sector:
ldy #$00
lda $AF
cmp $C2
bcs :+
lda #18
sta ($AE),y
iny
lda $AC
sta ($AE),y
bne not_last_sector
: tya
; Last sector, Y=0
.global store_a_ff_to_ae
store_a_ff_to_ae:
sta ($AE),y
lda #$FF
iny
sta ($AE),y
.global not_last_sector
not_last_sector:
lda $AC
sec
sbc #$01
jsr nibble2ascii
; Store sector number
stx write_block+10
sta write_block+11
jsr send_seek_0
jsr send_256byte_to_channel_2
jsr send_write_block
lda $AF
cmp $C2
bcs :+
inc $AF
inc $AC
jmp next_sector
; Now do the BAM.
; This is a simplistic algorithm: All sectors in track 18 are initially
; assumed used. We have the number of sectors used in $AC, so a 0 is
; shifted in $AC times.
: lda #19 ; Track 18 has 19 sectors
sec
sbc $AC
sta $C1
lda #$FF
sta $C2
sta $C3
sta $C4
: clc
rol $C2
rol $C3
rol $C4
dec $AC
bne :-
lda $C4
and #$07
sta $C4
; Update the BAM. Update commands for sector 0
lda #'0'
sta read_block+10
sta read_block+11
sta write_block+10
sta write_block+11
jsr send_read_block
jsr send_seek_72 ; BAM for track 18 at offset 72
lda #$62
jsr listen_second
ldx #$00
: lda $C1,x
jsr IECOUT
inx
cpx #4
bne :-
jsr UNLSTN
jsr send_write_block
; Send an "I" to command channel to make the drive reread the directory.
lda #$6F
jsr listen_second
lda #'I'
jsr IECOUT
jsr UNLSTN
jmp close_chn2
send_256byte_to_channel_2:
lda #$62
jsr listen_second
ldy #$00
: jsr _load_ae_rom_hidden
jsr IECOUT
iny
bne :-
jmp UNLSTN
;
; Reads a sector from channel 2.
;
; The 254 bytes payload of a sector are stored in ($AC)+2 onwards.
; Pointer $AC/$AD is not increased
;
; Returns:
;
; A - Link to next sector
; X - Link to next track
;
read_sector_from_chan_2:
lda #$62
jsr talk_second
ldy #$02
jsr IECIN
tax
jsr IECIN
pha
: jsr IECIN
sta ($AC),y
iny
bne :-
jsr UNTALK
pla
rts
open_hash_on_chan_2:
lda #$00
sta $90
lda #$F2
jsr listen_second
lda $90
bmi except_exit
lda #'#'
jsr IECOUT
jmp UNLSTN
close_chn2:
lda #$E2
jsr listen_second
jmp UNLSTN
listen_second:
pha
lda $BA ; Current device number
jsr LISTEN
pla
jmp SECOND
talk_second:
pha
lda $BA ; Current device number
jsr TALK
pla
jmp TKSA
send_read_block:
ldx #<(read_block - __diredit_cmds_RUN__)
.byte $2c
send_write_block:
ldx #<(write_block - __diredit_cmds_RUN__)
.byte $2c
send_seek_0:
ldx #<(seek_0 - __diredit_cmds_RUN__)
.byte $2c
send_seek_72:
ldx #<(seek_72 - __diredit_cmds_RUN__)
lda #$6F ; Listen channel 15
jsr listen_second
: lda __diredit_cmds_RUN__,x
beq :+
jsr IECOUT
inx
bne :-
: jsr UNLSTN
; Check for error omn cmd channel 15
lda #$6F
jsr talk_second
jsr IECIN
pha
: cmp #$0D
beq :+
jsr IECIN
bne :-
: jsr UNTALK
pla
cmp #$30
beq _rts2
except_exit:
; Error condition. Pull return address and abort directory write back.
pla
pla
jmp close
inc_c3c4_beyond_z:
; Search for a 0 byte
: iny
lda ($C3),y
bne :-
iny
tya
add_to_c3c4:
; Add the number of bytes to $C3/$C4
clc
adc $C3
sta $C3
bcc _rts2
inc $C4
_rts2: rts
;
; Convert a nibble (actually a number 0..19) to ASCII with fixed with.
;
; IN: A - Nibble
;
; OUT: A - Least significant digit
; X - Most sigificant digit
;
.proc nibble2ascii
ldx #'0'
cmp #$0A
bcc :+
inx
sbc #$0A
: ora #'0'
rts
.endproc
dirline:
.byte $00, $00, $80, $12, $00, '-', '-', '-'
.byte '-', '-', '-', '-', '-', '-', '-', '-'
.byte '-', '-', '-', '-', '-', $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.segment "diredit_cmds"
read_block: .asciiz "U1:2 0 18 01" ; Read block on channel 2 from drive 0, track 18 sector 1
write_block: .asciiz "U2:2 0 18 01" ; Write block on channel 2 to drive 0, track 18 sector 1
seek_0: .asciiz "B-P 2 0" ; Seek channel 2 to position 0
seek_72: .asciiz "B-P 2 72" ; Seek channel 2 to position 72
|
mist64/final_cartridge | 18,664 | bank3/freezer_backup.s | ;*****************************************************************************
; Final Cartridge III reconstructed source code
;
; This file implements the backup functionality of the freezer
;*****************************************************************************
.setcpu "6502x"
.include "../core/kernal.i"
.include "../core/fc3ioreg.i"
.include "persistent.i"
.import __tape_backup_loader_LOAD__,__tape_backup_loader_SIZE__
.import __disk_backup_loader_LOAD__,__disk_backup_loader_SIZE__
.import __zp_load_mem_1_LOAD__,__zp_load_mem_1_SIZE__
.import __zp_load_mem_2_LOAD__,__zp_load_mem_2_SIZE__
.importzp __zp_load_mem_1_RUN__,__zp_load_mem_2_RUN__
.importzp tmpvar1,tmpptr_a,spritexy_backup
.import write_mg87_and_reset
.segment "backup_disk"
.global freezer_backup_disk
freezer_backup_disk:
lda #$00
sta $D015 ; Disable sprites
sta $D418 ; Mute sound
ldy #$06
jsr set_1541_sector_interleave
jsr open_fc
lda #<__disk_backup_loader_LOAD__
sta tmpptr_a
lda #>__disk_backup_loader_LOAD__
sta tmpptr_a+1
ldy #0
@1: lda (tmpptr_a),y
jsr IECOUT
inc tmpptr_a
bne :+
inc tmpptr_a+1
: lda tmpptr_a
cmp #<(__disk_backup_loader_LOAD__ + __disk_backup_loader_SIZE__)
lda tmpptr_a+1
sbc #>(__disk_backup_loader_LOAD__ + __disk_backup_loader_SIZE__)
bcc @1
; Backup the zero page
ldx #$00
@2: lda $00,x
cpx #spritexy_backup ; ???? No backup of sprite 2 x coord?
bne :+
lda #$00
: jsr IECOUT
inx
bne @2
; Backup the stack
: lda $0100,x
jsr IECOUT
inx
bne :-
; Backup the colour RAM
: lda $DA00,x ; Color RAM
jsr st_high_nibble
lda $D800,x ; Color RAM
jsr st_low_nibble
inx
bne :-
: lda $DB00,x ; Color RAM
jsr st_high_nibble
lda $D900,x ; Color RAM
jsr st_low_nibble
inx
bne :-
; Backup VIC-II registers
: lda $D000,x ; Position X sprite 0
jsr IECOUT
inx
cpx #$2F
bne :-
; Backup $0400..$0402
ldx #$00
: lda $0400,x ; Video matrix (25*40)
jsr IECOUT
inx
cpx #$03
bne :-
jsr file_close_ch1
sei
; Install the zp_load_mem* routines into zeropage
ldx #<__zp_load_mem_1_SIZE__-1
: lda __zp_load_mem_1_LOAD__,x
sta __zp_load_mem_1_RUN__,x
dex
bpl :-
; Backup $FFFD..$FFFF
lda #<$FFFD
sta tmpptr_a
lda #>$FFFD
sta tmpptr_a+1
ldy #$02
lda #$33
sta $01
: jsr zp_load_tmpptr_a
sta $009B,y
dey
bpl :-
; Compress the memory
jsr backup_compress_ram
lda $99
sta tmpptr_a
lda $9A
sta tmpptr_a+1
ldx #<__zp_load_mem_2_SIZE__-1
: lda __zp_load_mem_2_LOAD__,x
sta __zp_load_mem_2_RUN__,x
dex
bpl :-
lda tmpptr_a
sta $96
lda tmpptr_a+1
sta $97
sec
lda #$00
sbc tmpptr_a
sta $9E
lda #$00
sbc tmpptr_a+1
clc
adc #$04
sta $9F
ldx #$37
stx $01
jsr open_minusfc
ldx #$00
; Backup page $0200
: lda $0200,x
jsr IECOUT
inx
bne :-
; Backup page $0300
: lda $0300,x
jsr IECOUT
inx
bne :-
; X=0
; Backup some variables
: lda $9B,x
jsr IECOUT
inx
cpx #$05
bne :-
ldy #<$0400
sty tmpptr_a
lda #>$0400
sta tmpptr_a+1
@3: jsr $00A6
jsr IECOUT
inc tmpptr_a
bne :+
inc tmpptr_a+1
: lda tmpptr_a
cmp $96
lda tmpptr_a+1
sbc $97
bcc @3
jsr file_close_ch1
ldy #$0A
jsr set_1541_sector_interleave
jmp write_mg87_and_reset
.segment "backup_disk_2"
st_high_nibble:
asl
asl
asl
asl
sta $A5
rts
st_low_nibble:
and #$0F
ora $A5
jmp IECOUT
open_fc:
lda #$F1 ; OPEN channel 1
jsr listen_second
jmp send_fc
open_minusfc:
lda #$F1
jsr listen_second
lda #$2D
jsr IECOUT
send_fc:
lda #'F'
jsr IECOUT
lda #'C'
jsr IECOUT
jsr UNLSTN
lda #$61 ; LISTEN channel 1
listen_second:
pha
lda #$08
jsr LISTEN
pla
jmp SECOND
;
; Set 1541 sector interleave to value in Y
;
.proc set_1541_sector_interleave
lda #$6F ; Talk to channel 15
jsr listen_second
ldx #sizeof_interleave_write - 1
: lda interleave_write,x
jsr IECOUT
dex
bpl :-
tya
jsr IECOUT
jmp UNLSTN
.endproc
interleave_write: .byte $01,$00,$69,'W','-','M'
sizeof_interleave_write = .sizeof(interleave_write)
file_close_ch1:
jsr UNLSTN
lda #$e1
jsr listen_second ; Close channel 1
jmp UNLSTN
sei
lda #$33
sta $01
ldy #$00
sty $C3
lda #$01
sta $C4
tya
: sta ($C3),y
iny
bne :-
inc $C4
bne :-
lda #$37
sta $01
jmp START ; KERNAL RESET routine
.segment "backup_compress"
;
; Compress the C64's memory from $0403 to $FFFD using Run Length Encoding
;
;
; Compressed stream opcodes:
;
; $00 nn aa bb cc ... Copy $nn bytes to output (<256 bytes)
; $01 nn oo aa bb cc ... Copy $oonn bytes to output (>=256 bytes)
; $02 oo nn xx Copy a run of $oonn bytes with value xx to output (<256 bytes)
; nn xx (nn>$02) Copy a run of $nn bytes with value xx to output (>=256 byte)
backup_compress_ram:
lda #>$0403 ; RAM compression starts at $0403
sta $97
sta tmpptr_a+1
sta $9A
ldy #$00
sty $99
lda #<$0403 ; RAM compression starts at $0403
sta $96 ; Source ptr1
sta tmpptr_a ; Source ptr2
ldy #$00
ldx #$00
; Find at least 4 equal bytes in sequence
@find_run_of_4:
ldy #$00
jsr zp_load_96 ; Load a byte from RAM
sta $98 ; Open files number/Index of files table
: iny
jsr zp_load_96 ; Load another byte from RAM
cmp $98 ; Same as previous?
bne @1
cpy #4
bne :-
beq @found4
@1: jsr incptrchkend
bcc @find_run_of_4 ; Not end of memory? Then continue
@found4:
ldy #$00
ldy #$00
; Compute the different between $96/$97 and tmpptr_a and store in $98
sec
lda $96
sbc tmpptr_a
tax
lda $97
sbc tmpptr_a+1
sta $98
bne @st_big_unmodified
txa
beq @count_run ; Jump if low bytes equal
; Store <256 bytes up until the run unmodified
lda #$00
jsr zp_store_a_99
txa
jsr zp_store_a_99
@2: jsr zp_load_tmpptr_a_inc_ptr2
jsr zp_store_a_99
dex
@6: bne @2
jsr chkend
bcc @count_run
rts
; Store >=256 bytes up until the run unmodified
@st_big_unmodified:
lda #$01
jsr zp_store_a_99
txa
pha
jsr zp_store_a_99
lda $98
jsr zp_store_a_99
ldx #$00
: jsr zp_load_tmpptr_a_inc_ptr2
jsr zp_store_a_99
inx
bne :-
dec $98
bne :-
pla
tax
clc
bcc @6
@count_run:
jsr zp_load_96
sta $98
: jsr incptrchkend
bcs :+
jsr zp_load_96
cmp $98
beq :-
: ; Compute the length of the run
sec
lda $96
sbc tmpptr_a
tax
lda $97
sbc tmpptr_a+1
pha
; Copy $96/$97 into tmpptr_a
lda $96
sta tmpptr_a
lda $97
sta tmpptr_a+1
pla
bne @stbigrun
txa
@stsmallrun:
jsr zp_store_a_99
lda $98
jsr zp_store_a_99
jsr chkend
bcs _rts
jmp @find_run_of_4
@stbigrun:
pha
lda #$02
jsr zp_store_a_99
txa
jsr zp_store_a_99
pla
bne @stsmallrun
incptrchkend:
inc $96
bne chkend
inc $97
chkend:
lda $96
cmp #<$FFFD
lda $97
sbc #>$FFFD
; This will underflow if $96/$97 < $FFFD, thus C=1 if at end of memory.
_rts:
rts
.proc zp_store_a_99
sta ($99),y
inc $99
bne :+
inc $9A
: rts
.endproc
.proc zp_load_tmpptr_a_inc_ptr2
jsr zp_load_tmpptr_a
inc tmpptr_a
bne :+
inc tmpptr_a+1
: rts
.endproc
.segment "zp_load_mem_1"
.proc zp_load_96
inc $01
lda ($96),y
dec $01
rts
.endproc
.proc zp_load_tmpptr_a
inc $01
lda (tmpptr_a),y
dec $01
rts
.endproc
.segment "zp_load_mem_2"
.proc zp_load_tmpptr_b
lda #$0C
sta $01
lda (tmpptr_a),y
pha
lda #$0F
sta $01
pla
rts
.endproc
.segment "disk_backup_loader"
.incbin "disk_backload/backup_loader.prg"
.segment "freezer_backup_tape"
turbotape_tape_program_header:
.word $0801 ; Load address of program
.word $105a ; End address of program
.byte $00
.byte "FC"
.global freezer_backup_tape
freezer_backup_tape:
lda #$00 ; Disable all sprites
sta $D015
lda #<__tape_backup_loader_LOAD__
sta tmpptr_a
lda #>__tape_backup_loader_LOAD__
sta tmpptr_a+1
jsr tape_prepare
jsr tape_write_header_fast ; Sets Y=0
lda #$01 ; Indicates that we are writing a BASIC program to tape
jsr tape_write_byte_fast
ldx #$08
: lda turbotape_tape_program_header,y
jsr tape_write_byte_fast
ldx #$07 ; Reload pulse length
iny
cpy #$07 ; 8 bits written?
bne :- ; No, then loop
ldy #$00
: lda #$20 ; Write the value $20 $B8 times to fill the header
jsr tape_write_byte_fast
ldx #$07 ; Reload pulse length
iny
cpy #$B9 ; $B8 times
bne :-
; Write the loader to tape
jsr tape_write_header_fast ; Write another header ; sets Y=0
tya
jsr tape_write_byte_fast ; Write a 0 byte
ldx #$07 ; Reload pulse length
@1: lda (tmpptr_a),y ; Get a byte from the loader
jsr tape_write_byte_fast
ldx #$03 ; Reload pulse length (compensated for extra instructions)
inc tmpptr_a ; Increase low byte of pointer
bne :+ ; Next byte
inc tmpptr_a+1 ; Increase high byte of pointer
dex ; Compensate for extra instructions
dex
: lda tmpptr_a
cmp #<(__tape_backup_loader_LOAD__ + __tape_backup_loader_SIZE__)
lda $92
sbc #>(__tape_backup_loader_LOAD__ + __tape_backup_loader_SIZE__)
bcc @1
; Write the zeropage to tape
ldx #$02
: lda $0000,y
jsr tape_write_byte_fast
ldx #$07
iny
bne :-
; Write the stack to tape
: lda $0100,y
jsr tape_write_byte_fast
ldx #$07
iny
bne :-
; Write the colour RAM to tape
sty tmpptr_a ; Y already 0
lda #$D8 ; $D800
sta tmpptr_a+1
ldx #$04
: lda (tmpptr_a),y ; Load a byte from colour RAM
jsr tape_write_byte_fast
ldx #$08
iny
bne :-
ldx #$03
inc tmpptr_a+1
lda tmpptr_a+1
cmp #$DC ; End of colour RAM ?
bne :-
; Save the VIC-II registers to tape
: lda $D000,y
jsr tape_write_byte_fast
ldx #$07
iny
cpy #$2F
bne :-
; Save $0400..$0402 to tape
ldy #$00
: lda $0400,y ; Video matrix (25*40)
jsr tape_write_byte_fast
ldx #$07
iny
cpy #$03
bne :-
; Save checksum to tape
lda $A4
inx
jsr tape_write_byte_fast
jsr tape_finnish
; Install the zp_load_mem* routines into zeropage
ldx #<__zp_load_mem_1_SIZE__-1
: lda __zp_load_mem_1_LOAD__,x
sta __zp_load_mem_1_RUN__,x
dex
bpl :-
; Retrieve the vectors from $FFFD
ldy #$02
lda #<$FFFD
sta tmpptr_a
lda #>$FFFD
sta tmpptr_a+1
lda #$33
sta $01
: jsr zp_load_tmpptr_a
sta $009B,y
dey
bpl :-
jsr backup_compress_ram
lda $99
sta tmpptr_a
lda $9A
sta tmpptr_a+1
ldx #<__zp_load_mem_2_SIZE__-1
: lda __zp_load_mem_2_LOAD__,x
sta __zp_load_mem_2_RUN__,x
dex
bpl :-
lda tmpptr_a
sta $96
lda tmpptr_a+1
sta $97
; Negate tmpptr_a, add $0400 and store in $9e/$9f
sec
lda #0
sbc tmpptr_a
sta $9E
lda #0
sbc tmpptr_a+1
clc
adc #$04
sta $9F
lda #$37
sta $01
jsr tape_prepare
sty tmpptr_a
lda #$04
sta tmpptr_a+1
; Write a turbo tape header
jsr tape_write_header_fast
tya
jsr tape_write_byte_fast
ldx #$08
: lda $009B,y
jsr tape_write_byte_fast
ldx #$06
iny
cpy #$05
bne :-
; Backup the compressed memory
ldy #$00
ldx #$07
@2: jsr zp_load_tmpptr_b
sta tmpvar1
lda #$08
sta $A3
: asl tmpvar1
lda $01
and #$F7
jsr tape_half_pulse
ldx #$11
ora #$08
jsr tape_half_pulse
ldx #$0E
dec $A3
bne :-
ldx #$03
inc tmpptr_a
bne :+
dex
dex
inc tmpptr_a+1
: lda tmpptr_a
cmp $96
lda tmpptr_a+1
sbc $97
bcc @2
jsr tape_finnish
lda #$37
sta $01
jsr tape_prepare
jsr tape_write_header_fast
tya
jsr tape_write_byte_fast
ldx #$08
; Write the $0200 page
: lda $0200,y
jsr tape_write_byte_fast
ldx #$07
iny
bne :-
; Write the $0300 page
: lda $0300,y
jsr tape_write_byte_fast
ldx #$07
iny
bne :-
jsr tape_finnish
jmp write_mg87_and_reset
;
; Wait for a button press on tape, disable the screen and start the tape motor
;
tape_prepare:
lda #$10 ; Bit 4 is cassette sense
: bit $01
bne :- ; Not presset? Then loop
lda $01
and #$07 ; Enable tape motor
sta $01
lda #$0B
sta $D011 ; Disable screen (normal value of $d011 is $1b)
ldy #0 ; Do a delay loop, because VIC-II only stops bad lines
: inx ; at the next frame.
bne :-
iny
bne :-
rts
;
; Enable the screen, and stop the tape motor
;
tape_finnish:
lda #$1B ; Enable screen
sta $D011
lda $01
ora #$20 ; Bit 5 is tape motor
sta $01
rts
;
; Write the Turbotape header to tape. A Turbotape header consists of 256 times the value
; 2. This is the pilot tone that allows synchronization. However, the following routine
; writes 5 * 247 times a 2, so the header is longer than the original turbotape program.
; Then the bytes 9,8,7,6,5,4,3,2,1 are written. This allows the reader to differentiate
; between a valid header and not just some random sequence of twos.
;
; Y=0 on return, code depends on this.
;
tape_write_header_fast:
lda #$05 ; 5 times 247
sta $A5
ldy #$00 ; Start at 0 and count down
: lda #$02 ; Write a 2 to tape
jsr tape_write_byte_fast
ldx #$07 ; Lenth of the low pase
dey
cpy #$09 ; Did we write 247 bytes?
bne :- ; No, then loop
ldx #$05 ; Length of the low phase (slightly lower because
; we did exec more instructions).
dec $A5
bne :-
: tya
jsr tape_write_byte_fast
ldx #$07 ; Length of the low phase
dey
bne :-
dex ; Length of low phase to to 5 to account for extra
; instructions
dex
sty $A4 ; Y=0
rts
ldx #$08
;
; Write the byte in A to tape
;
tape_write_byte_fast:
sta tmpvar1 ; Store the byte to write
eor $A4 ; Update checksum
sta $A4
lda #8 ; 8 Bits to write
sta $A3
: asl tmpvar1 ; Shift a bit out
lda $01
and #$F7 ; Write the low pulse phase
jsr tape_half_pulse
ldx #17 ; Length of pulse
ora #$08 ; Write the high pulse phase
jsr tape_half_pulse
ldx #14 ; Length of pulse
dec $A3 ; Count down number of bits
bne :- ; More bits to write? Then loop.
rts
;
; Do either the high or low phase of the pulse.
; C contains the bit to write to tape
; 0 = 176 us pulse
; 1 = 256 us pulse
;
; A contains the value to write to $01, either bit 3 set or reset depending
; on wheter to write the high or low phase.
;
tape_half_pulse:
: dex
bne :-
bcc @1
ldx #$0B
: dex
bne :-
@1: sta $01
rts
.segment "tape_backup_loader"
.incbin "tape_backload/backup_loader.prg",2
|
mist64/final_cartridge | 5,972 | bank3/persistent.s | ; --------ø--------------------------------------------------------
; I/O Area ROM
; ----------------------------------------------------------------
; This is a max. 512 byte section that lives at $1E00-$1FFF of
; bank 0 of the ROM, and will also be mapped into the I/O extension
; area at $DE00-$DFFF, so it's always visible.
; It contains soms trampolines to be able to switch from/to Ultimax
; mode for the freezer and contains the autofire code for the joystick
.setcpu "6502x"
.include "../core/fc3ioreg.i"
.include "../core/kernal.i"
.import freezer_init
.import freezer_exec_menu
.import freezer_update_spritepointers
.import show_view_menu
;.import freezer_exec_bank
.segment "romio1l"
;
;
; ROMIO1 area ($DE00)
;
;
fc_bank_id:
.byte fcio_bank_3|fcio_nmi_line
;
; Jump into a bank of the FC3 ROM
;
; Jumps to a routine in the FC3 ROM of which the address is on the stack
; and the bank number in A.
;
.global _jmp_bank
_jmp_bank:
sta fcio_reg
rts
.global _enable_fcbank0
_enable_fcbank0: ; $DE05
pha
lda #fcio_bank_0|fcio_c64_16kcrtmode|fcio_nmi_line
a_to_fcio_pla:
sta fcio_reg
pla
rts
; _disable_fc3rom: Hides the FC3 ROMS from memory
; _disable_fc3rom_set_01: Stores Y into $01 and hides the FC3 ROMS from memory
;
.global _disable_fc3rom_set_01
_disable_fc3rom_set_01:; $DE0D
sty $01
.global _disable_fc3rom
_disable_fc3rom: ; $DE0F
pha
lda #fcio_bank_0|fcio_c64_crtrom_off|fcio_nmi_line
bne a_to_fcio_pla ; always taken
; padding
.byte $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.byte $FF,$FF,$FF,$FF
;
; Do an "lda($AE),y" with ROMs disabled and interrupts off
;
.global _load_ae_rom_hidden
_load_ae_rom_hidden: ; $de20
sei
lda #$35
sta $01
lda ($AE),y
pha
lda #$37
sta $01
pla
cli
rts
.segment "romio1h"
.global _freezer_upd_sprptr_16k
_freezer_upd_sprptr_16k:
lda #fcio_bank_3|fcio_c64_16kcrtmode
sta fcio_reg
jsr freezer_update_spritepointers ; jump into bank 3
ultimax_bank3_rts:
lda #fcio_bank_3|fcio_c64_ultimaxmode
sta fcio_reg
rts
;
; Go to ultimax mode, execute the freezer menu and return to 16K mode
;
.global freezer_ultimax_exec_menu
freezer_ultimax_exec_menu:
jsr ultimax_bank3_rts
jsr freezer_exec_menu
bank3_16kmode:
ldx #fcio_bank_3|fcio_c64_16kcrtmode
stx fcio_reg
rts
;
; Go to 16k mode, execute $bc5b and return to ultimax mode
;
.global _show_view_menu
_show_view_menu:
jsr bank3_16kmode
jsr show_view_menu
jsr ultimax_bank3_rts
jmp freezer_exec_menu
;
; Go to ultimax mode, execute $fbe4 and return to 16K mode
;
.global ultimax_fbe4
ultimax_fbe4:
jsr ultimax_bank3_rts
jsr $FBE4
jmp bank3_16kmode
;
; Go to ultimax mode, execute $fb98 and return to 16K mode
;
.global ultimax_highlight_selected_menu
ultimax_highlight_selected_menu:
jsr ultimax_bank3_rts
jsr $FB98
jmp bank3_16kmode
.segment "romio2l"
.global autofire_ldy_dc01
autofire_ldy_dc01:
pha
tya
jsr autofire_lda_dc01
autofire_ldy_exit:
tay
pla
cpy #0
rts
.global autofire_ldx_dc01
autofire_ldx_dc01:
pha
txa
jsr autofire_lda_dc01
autofire_ldx_exit:
tax
pla
cpx #0
rts
.global autofire_ldy_dc00
autofire_ldy_dc00:
pha
tya
jsr autofire_lda_dc00
jmp autofire_ldy_exit
.global autofire_ldx_dc00
autofire_ldx_dc00:
pha
txa
jsr autofire_lda_dc00
jmp autofire_ldx_exit
cpy #$01
beq autofire_lda_dc01
bne autofire_lda_dc00
cpx #$01
beq autofire_lda_dc01
.global autofire_lda_dc00
autofire_lda_dc00:
lda $DC00 ; Data port A #1: keyboard, joystick, paddle, optical pencil
jmp autofire_chkbutton
.global autofire_lda_dc01
autofire_lda_dc01:
lda $DC02 ; Data direction register port A #1
pha
lda #$00
sta $DC02 ; Data direction register port A #1
lda $DC01 ; Data port B #1: keyboard, joystick, paddle
sta $0122 ; Save to tmp location in stack memory
pla
sta $DC02 ; Data direction register port A #1
lda $0122 ; Load from tmp location
pha
and #$10 ; Fire button pressed?
beq autofire_button_pressed
pla
lda $DC01 ; Data port B #1: keyboard, joystick, paddle
rts
lda $0122
autofire_chkbutton:
pha
and #$10 ; Fire button pressed?
beq autofire_button_pressed
pla_rts:
pla
rts
autofire_button_pressed:
lda $0120
bne autofire_signal
dec $0121
bne pla_rts
lda #$02
sta $0120
sta $0121
bne pla_rts ; Always
autofire_signal:
dec $0121
beq autofire_signal_press
pla
ora #$10 ; Unpress the button
rts
autofire_signal_press:
lda #$00
sta $0120
lda #$01
sta $0121
pla
rts
.global freezer_set_c64and_fc3_rts
freezer_set_c64and_fc3_rts:
sta fcio_reg
sty $01
rts
.segment "romio2h"
.global t_freezer_init
t_freezer_init:
stx fcio_reg
sta $DD0D ; Interrupt control register CIA #2
jmp freezer_init ; Continue freezer init in 16K crt mode
bank1_jump:
lda #fcio_bank_1 | fcio_c64_crtrom_off |fcio_nmi_line ; goto_desktop
sta fcio_reg ; Execution continues in bank 1
reset_c64:
jmp START ; Routine: Startup
|
mist64/final_cartridge | 27,995 | bank3/mysterycode.s | ;****************************
; This code is not fully understood yet
;
; Its purpose seems to be reading and writing the directory.
;****************************
.setcpu "6502x"
.include "../core/kernal.i"
.include "../core/fc3ioreg.i"
.include "persistent.i"
.import store_a_ff_to_ae,fill_loop
.import __diredit_cmds_LOAD__,__diredit_cmds_RUN__,__diredit_cmds_SIZE__
.import W9200
.import not_last_sector
.import next_dir_entry
.segment "mysterycode"
.byte $b0,$90,$da
W915D:
jsr next_dir_entry+1 ; ??????!!
lda #$80
sta $90 ; Statusbyte ST of I/O KERNAL
rts
lda #$B0
sta $C2
lda $0200
sta $C3
lda $0201
sta $C4
W9173:
lda #>$A000
sta $AF
ldy #<$A000
sty $AE
lda ($C3),y
tax
bne :+
jmp fill_loop
: jsr store_a_ff_to_ae
txa
bpl :+
jmp W9200
W918C:
: ldy #$02
jsr _load_ae_rom_hidden
bpl @2
lda #$05
ora $AE
sta $AE
ldy #$00
: lda ($C3),y
beq :+
jsr _load_ae_rom_hidden
cmp ($C3),y
bne @2
iny
cpy #$11
bne :-
beq @1
: cpy #$10
beq :+
jsr _load_ae_rom_hidden
cmp #$A0
bne @2
: iny
tya
jsr not_last_sector
ldy #$00
lda $AE
and #$F0
sta $AE
lda #$00
sta ($C1),y
iny
sta ($C1),y
iny
: jsr _load_ae_rom_hidden
sta ($C1),y
iny
cpy #$20
bne :-
tya
clc
adc $C1
sta $C1
bcc W9173
inc $C2
lda $C2
cmp #$C0
bcc W9173
@1:
jmp W915D
@2:
lda $AE
and #$F0
clc
adc #$20
sta $AE
bcc :+
inc $AF
: lda $AF
cmp $AD
bcs @1
jmp W918C
.segment "mysterybytes"
; These bytes might just be some random padding, because the screenshot code starts at exactly $9500.
; This might also be code, but it doesn't look like it would be actually executable code.
.byte $15, $03, $a0, $00, $84, $ac, $84, $ae
.byte $a9, $0c, $85, $ad, $a9, $c0, $85
.segment "junk0"
.byte $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF
.byte $FF, $FF, $FF, $FF, $FF, $FF, $1C
.segment "ramcode"
; Installed to zeropage at $0060
WA421:
jmp $1D48
jmp $1D58
jsr $154D
jmp $B603
lda #$0D
jsr $1599
jsr $1CDA
jsr $1D58
jsr $137A
jsr $1CAD
jmp $B603
jsr $18DA
jsr $1EB1
bcs @1
ldx #$6E
ldy #$11
lda #$49
jsr _enable_fcbank0
txa
beq :+
jmp $18D4
: jsr $12BF
@1: ldx #$FB ; init stack?
txs
lda #$58
jsr _enable_fcbank0
nop
nop
nop
jmp $8003 ; warmstart ??
.segment "mysterybytes2"
.byte $cd
.byte $19,$a1,$19,$ef,$19,$47,$1a,$66
.byte $1a,$52,$1a,$5a,$1a,$73,$1a,$5d
.byte $1a,$96,$1a,$88,$1a,$71,$10,$21
.byte $14,$27,$1a,$d0,$1f,$dd,$1f
.segment "ramcode2"
;WA489
jsr $148D
sec
lda $0DC1
sbc $9F
sta $0DC1
bcs :+
dec $0DC2
: rts
jsr $148D
clc
lda $0DC1
adc $9F
WE4A4:
sta $0DC1
bcc :+
inc $0DC2
: rts
lda $0E04
bpl :+
clc
adc #$01
: and #$0F
sec
adc $5700,x
sta $9F
rts
lda $0DC1
cmp #$2A
bcc :+
lda $0DC2
cmp #$01
: rts
sei
: lda $D012
cmp #$FB
bcc :-
cli
rts
ldy #$01
clc
lda #$2A
adc $0DBE
tax
bcc :+
iny
: sty $FA
ldy $0DBF
lda #$03
jsr _enable_fcbank0
ldx $FE
ldy $FF
stx $0DC7
sty $0DC8
rts
WE4F6:
ldy #$00
lda ($8B),y
sta ($35),y
tax
tya
iny
sta ($35),y
inc $8B
bne :+
inc $8C
: inc $35
bne :+
inc $36
: rts
rts
ldy #$00
lda ($8B),y
cmp #$0D
beq WE4F6
rts
WE518:
lda $8B
bne :+
dec $8C
: dec $8B
lda $35
bne :+
dec $36
: dec $35
ldy #$00
lda ($35),y
sta ($8B),y
tax
tya
sta ($35),y
rts
dec $36
ldy #$FF
lda ($35),y
inc $36
cmp #$0D
beq WE518
rts
lda $A3
bpl :+
clc
adc #$01
: and #$0F
sta $96
ldy #$00
sty $0DC1
sty $0DC2
@1: lda ($C3),y
beq @x
tax
sec
lda $5700,x
adc $96
adc $0DC1
sta $0DC1
bcc :+
inc $0DC2
: iny
bne @1
@x: rts
ldy #0
lda #$FF
sta ($35),y
tya
iny
sta ($35),y
inc $35
bne :+
inc $36
: rts
lda $35
bne :+
dec $36
: dec $35
ldy #$00
lda ($35),y
tax
tya
sta ($35),y
rts
inc $8B
bne :+
inc $8C
: clc
rts
dec $36
ldy #$00
: dey
lda ($35),y
cmp #$FF
bne :-
tya
eor #$FF
tax
sta $C3
inc $36
ldy $36
sec
lda $35
sbc $C3
sta $C3
bcs :+
dey
: sty $C4
rts
ldy #0
sta ($35),y
inc $35
bne :+
inc $36
: tya
sta ($35),y
rts
sec
lda #$2A
sbc $0DC1
sta $8D
lda #$01
sbc $0DC2
sta $8E
jsr $165E
bcs @2
jsr $1C5C
lda $8E
rts
@2: jsr $1C74
lda $8E
rts
WA5E7:
jsr $14F8
jsr $1469
lda #$01
sta $0DCA
bne @1
jsr $14F8
jsr $1469
lda #$00
sta $0DCA
beq :+
lda #$FF
sta $0DCA
: jsr $14F8
jsr $1469
inc $0DCA
cpx #$20
bne :-
lda $0DCA
bne :+
inc $0DCA
bne @1
: jsr $14D6
@1: jsr $154D
jsr $1323
jsr $1CDA
lda $0DC9
cmp $0DCB
bne :+
jsr $1DF5
dec $0DC9
ldy $0DC9
lda $0DE6,y
sta $0DBF
: jsr $1D58
inc $0DC9
ldy $0DC9
lda $0DE6,y
sta $0DBF
lda $8B
sta $0DCD,y
lda #$00
sta $0DC1
sta $0DC2
lda $0DCA
sta $8E
beq WE66D
: jsr $14D6
jsr $147B
dec $8E
bne :-
WE66D:
jsr $1CAD
jmp $14B5
ldx $0DCA
beq @xc
dec $36
ldy #$FE
bne :+
ldx $0DCA
beq @xc
dec $36
ldy #$FF
: lda ($35),y
cmp #$20
beq @xs
dey
dex
bne :-
inc $36
@xc: clc
rts
@xs: inc $36
sec
rts
lda $35
cmp #$01
bne @rts
beq :+
lda $35
bne @rts
: lda $36
cmp #$58
@rts: rts
WE6AA:
jsr $1681
beq WE6D4
jsr $14F8
cpx #$20
bcc WE6CB
cpx #$7E
bcc WE6AA
txa
eor #$A0
cmp #$61
bcc WE6CB
cmp #$7E
bcs WE6CB
ldy #$00
sta ($8B),y
beq WE6AA
WE6CB:
cpx #$0D
beq WE6AA
jsr $156F
bcc WE6AA
WE6D4:
jmp $154D
lda #$00
sta $0DC9
sta $0DCA
sta $0DC1
sta $0DC2
ldx $0E01
ldy $0E02
stx $0DBE
sty $0DBF
rts
WE6F2:
jsr $15A7
beq WE720
jsr $14D6
txa
beq WE71D
cpx #$0D
beq WE71D
inc $0DCA
jsr $147B
lda $A6
cmp $0DC2
bcc WE717
bne WE6F2
lda $0DC1
cmp $A5
bcc WE6F2
WE717:
jsr $1469
dec $0DCA
WE71D:
jsr $14F8
WE720:
rts
WE721:
lda $0DCA
beq @x
jsr $14F8
txa
dec $0DCA
jsr $1469
lda $0DC2
cmp $A6
bcc @x
bne WE721
lda $A5
cmp $0DC1
bcc WE721
@x: rts
lda $0DC2
cmp $A6
bcc WE6F2
bne WE721
lda $A5
cmp $0DC1
bcs WE6F2
bcc WE721
cpy $0DC9
bcs WE7B8
sty $F7
sec
lda $0DC9
sbc $F7
WE760:
sta $F7
inc $F7
lda #$00
sta $A5
@3: jsr $14F8
cpx #$FF
bne @3
jsr $156F
jsr $1681
beq @4
ldy $0DC9
lda $8B
ldx $A5
bne @1
cmp $0DCD,y
beq @2
inc $A5
@1: lda #$00
sta $0DCD,y
@2: dec $F7
beq @4
dec $0DC9
ldy $0DC9
lda $0DE6,y
sta $0DBF
bne @3
@4: jsr $154D
dec $0DC9
jsr $1D58
inc $0DC9
lda #$00
sta $0DCA
sta $0DC1
sta $0DC2
jmp $14B5
WE7B8:
sec
tya
sbc $0DC9
sta $F7
WE7BF:
jsr $15A7
beq @1
: jsr $14D6
jsr $147B
dec $8E
bne :-
@1: ldy #$00
lda ($8B),y
beq WE760
jsr $14EF
jsr $154D
lda #$00
sta $0DCA
WE7DF:
sta $0DC1
sta $0DC2
inc $0DC9
ldy $0DC9
lda $0DE6,y
sta $0DBF
dec $F7
bne WE7BF
jmp $14B5
lda $0DC0
beq WE80C
asl
tax
lda $1447,x
sta $A4
lda $1448,x
sta $A5
jmp ($00A4)
WE80C:
jmp $1CAD
sta $A3
sta $A6
stx $A4
sty $A5
WE817:
ldy #$06
lda ($A4),y
cmp #$23
bne :+
iny
lda ($A4),y
cmp $A3
bne WE84C
beq WE82F
: iny
lda ($A4),y
cmp $A3
beq WE840
WE82F:
ldy #$00
lda ($A4),y
tax
iny
lda ($A4),y
stx $A4
sta $A5
bne WE817
ldy $A6
rts
WE840:
ldy #$06
lda ($A4),y
ora #$02
sta ($A4),y
ldy #$09
bne WE856
WE84C:
ldy #$06
lda ($A4),y
and #$FD
sta ($A4),y
ldy #$0A
WE856:
lda ($A4),y
pha
ldy #$08
lda ($A4),y
sta $A3
ldy #$02
lda ($A4),y
tax
iny
lda ($A4),y
stx $A4
sta $A5
ldy $A3
pla
sta ($A4),y
ldy $A6
rts
lda $B6
cmp #$08
bcs WE891
lda $B5
WE87B:
bne :+
jsr $18C3
lda #$00
sta $0DC0
lda #$3C
jsr _enable_fcbank0
jsr $18CC
jsr $17D8
: rts
WE891:
ldy #$00
lda $B6
ldx $0DCB
inx
: cmp $0DE6,y
bcc WE8A4
iny
dex
bpl :-
ldy #$00
WE8A4:
tya
beq @1
dey
sec
ldx $B5
lda $B4
sbc $0E01
bcs :+
dex
bpl :+
lda #$00
tax
: sta $A5
stx $A6
sta $0DC3
stx $0DC4
cpy $0DC9
beq :+
jsr $1733
lda $0DC3
ldx $0DC4
sta $A5
stx $A6
: jsr $1721
jsr $1323
jsr $1CAD
@1: lda $03C8
beq @1
rts
lda #$50
jsr _enable_fcbank0
jsr $18DA
rts
jsr $18D4
lda #$57
jmp _enable_fcbank0
lda #$43
sta $D015 ; Sprites Abilitator
rts
lda #$03
sta $D015 ; Sprites Abilitator
rts
ldy #$FF
lda $0E02
: iny
sta $0DE6,y
clc
adc $0E03
cmp #$BC
bcc :-
sty $0DCB
iny
lda #$C8
sta $0DE6,y
rts
sei
ldx #<$EA31
ldy #>$EA31
stx $0314 ; Vector: Hardware Interrupt (IRQ)
sty $0315 ; Vector: Hardware Interrupt (IRQ)
lda #$F0
sta $D01A ; IRQ mask register
cli
rts
sei
ldx #<$DE21
ldy #>$DE21
stx $0314 ; Vector: Hardware Interrupt (IRQ)
sty $0315 ; Vector: Hardware Interrupt (IRQ)
lda #$F1
sta $D01A ; IRQ mask register
cli
rts
ldx #$FF
lda $1070
ldy $0DBD
cpy #$08
bcc WE94E
tay
beq WE968
WE94E:
ldx #$5F
ldy #$10
sta $8D
stx $8E
sty $8F
lda $0DBD
sta $F7
ldx #$00
ldy #$58
lda #$53
jsr _enable_fcbank0
ldx $8F
WE968:
stx $0DFF
ldx $AE
ldy $AF
stx $0DC3
sty $0DC4
rts
ldx #$FF
lda $1070
ldy $0DBD
cpy #$08
bcc WE985
tay
beq WE9B4
WE985:
ldx #$5F
ldy #$10
sta $8D
stx $8E
sty $8F
ldx $8B
ldy $8C
stx $A8
sty $A9
lda #$A8
sta $F7
ldx #$FF
ldy #$7F
lda $0DBD
sta $AA
lda #$54
jsr _enable_fcbank0
ldx #$00
lda $0DBD
cmp #$08
bcc WE9B4
ldx $8F
WE9B4:
stx $0DFF
rts
WE9B8:
jsr $14D6
txa
bne WE9B8
jmp $14F8
jsr $1679
beq @x1
@l: jsr $18DA
jsr $16B7
jsr $14B5
jsr $1323
jsr $1CAD
ldy $0DCB
lda #$00
: sta $0DCD,y
dey
bpl :-
jsr $168A
jsr $B609
jsr $1323
jsr $18D4
@x1: rts
jsr $1EB1
bcs @5
jsr $1AFD
txa
beq :+
rts
: jsr $12BF
@5: jsr $1A03
ldx #$00
stx $C6
ldy #$58
stx $35
sty $36
jsr $154D
jmp $19F9
ldx $0DC3
ldy $0DC4
stx $35
sty $36
ldx #$FF
ldy #$7F
stx $8B
sty $8C
bne @l
ldx #$05
ldy #$10
lda #$02
jsr _enable_fcbank0
ldx #$9A
ldy #$B3
lda #$08
jsr _enable_fcbank0
ldx #$9F
ldy #$10
lda #$02
jsr _enable_fcbank0
ldx #$9A
ldy #$B3
lda #$08
jmp _enable_fcbank0
lda $0E04
eor #$10
sta $0E04
sta $A3
and #$10
beq @4
ldy #$6E
: lda #$06
sta $5710,y
dey
bpl :-
bmi @3
@4: jsr $1123
@3: jmp $19A6
lda $0E04
eor #$80
sta $0E04
clc
bcc :+
lda $0E04
: sta $A3
jmp $19A6
jsr $18E0
jsr $18DA
jsr $1A03
jmp $19A6
lda $0E05
eor #$01
sta $0E05
sta $8F
jmp $19A6
jsr $168A
jsr $18C3
jsr $18FB
jsr $1B30
jsr $190D
jsr $18CC
jmp $19A6
lda $0DFF
beq :+
jsr $1AF4
jmp $19DC
: jmp $19EF
jsr $18C3
jsr $1EFB
jsr $18CC
jsr $1CAD
lda $0DC0
cmp #$02
bne @2
rts
@2: jsr $168A
lda #$00
sta $0DFF
jsr $18C3
jsr $1956
jsr $18CC
lda $0DFF
beq :+
jsr $1AF4
: jmp $19A6
lda #$80
pha
lda #$0B
pha
ldy $DE00
lda #$40
jmp _jmp_bank
ldx #$03
jsr $1AC6
lda $90 ; Statusbyte ST of I/O KERNAL
bmi :+
ldx #$00
lda $0200
cmp #$30
bne :+
lda $0201
cmp #$30
beq @1
: dex
@1: stx $8F
stx $0DFF
rts
jsr $18DA
WEB17:
ldx #$39
ldy #$11
bne WEB48
jsr $18DA
ldx #$92
ldy #$11
bne WEB48
jsr $18DA
ldx #$BA
ldy #$11
bne WEB48
jsr $18DA
ldx #$F7
ldy #$11
bne WEB48
jsr $18DA
ldx #$40
ldy #$12
bne WEB48
jsr $18DA
ldx #$67
ldy #$12
WEB48:
lda #$49
jsr _enable_fcbank0
jmp $18D4
lda #$00
sta $90 ; Statusbyte ST of I/O KERNAL
jsr $FF90 ; Routine: Control KERNAL messages
ldx #$0B
WEB59:
jsr $1AC6
ldx #$0B
jsr $1AC6
lda $90 ; Statusbyte ST of I/O KERNAL
bmi WEB9B
jsr $1B85
tya
beq WEB9B
ldy #$00
sty $A6 ; Pointer: I/O Buffer of tape
@1: lda ($8B),y
cmp #$0D
beq WEB8B
cmp #$5F
bne :+
lda #$0C
: sta $0200
ldx #$0C
jsr $1AC6
inc $A6
ldy $A6
dec $A4
bne @1
WEB8B:
lda #$0D
sta $0200
ldx #$0C
jsr $1AC6
jsr $1BB4
jmp $1B45
WEB9B:
ldx #$0D
jsr $1AC6
lda #$C0
jmp $FF90 ; Routine: Control KERNAL messages
lda $0E00
sta $A4
ldy #$00
sty $A8
@4: lda ($8B),y
beq @5
iny
cmp #$0D
beq @5
ldx $0E05
beq :+
cmp #$20
bne @6
: sty $A8
@6: dec $A4
bne @4
ldy $A8
bne @5
ldy $0E00
bne @5
@5: sty $A4
sty $A8
rts
clc
lda $8B
adc $A8
sta $8B
bcc :+
inc $8C
: rts
ldx #$00
ldy #$00
lda #$02
jsr _enable_fcbank0
lda #$C8
sta $F9
lda #$05
jsr _enable_fcbank0
lda #$01
sta $FA
ldx #$3F
ldy #$00
lda #$03
jsr _enable_fcbank0
lda #$05
jsr _enable_fcbank0
ldx #$00
ldy #$C7
lda #$02
jsr _enable_fcbank0
ldx #$9F
stx $F8
lda #$04
jsr _enable_fcbank0
ldx #$9F
ldy #$C7
lda #$02
jsr _enable_fcbank0
lda #$04
jsr _enable_fcbank0
rts
lda $A3
bpl :+
clc
adc #$01
: and #$0F
sta $96
ldy #$00
sty $9E
sty $9F
sty $C4
@l: lda ($8B),y
tax
beq @1
cmp #$0D
beq @1
tax
sec
lda $5700,x
adc $96
adc $9E
sta $9E
bcc :+
inc $9F
: iny
@1: lda $8F
beq :+
cpx #$21
bcs @3
: lda $8E
cmp $9F
bcc @x
bne @2
lda $9E
cmp $8D
beq @2
bcs @x
@2: sty $C4
@3: txa
beq @y
cpx #$0D
beq @y
bne @l ; always
@x: ldy $C4
ldx #$01
rts
@y: ldx #$00
rts
jsr $1C05
tya
bne :+
txa
beq :+
lda #$00
sta $8F
jsr $1C05
lda $0E05
sta $8F
: sty $8E
rts
jsr $1C05
sty $8E
rts
kungfu:
ldy #$00
sty $8D
lda $8E
beq @rts
: lda ($8B),y
tax
cmp #$0D
beq @rts
lda #$19
jsr _enable_fcbank0
inc $8D
ldy $8D
cpy $8E
bcc :-
@rts: rts
shogun:
ldy $8E
lda ($8B),y
cmp #$0D
bne :+
inc $8E
: clc
lda $8B
adc $8E
sta $8B
bcc :+
inc $8C
: rts
clc
lda #$31
adc $0DBF
sta $D00D ; Position Y sprite 6
clc
lda #$17
adc $0DBE
adc $0DC1
tay
bcs WECE7
lda $0DC2
beq WECEE
WECE7:
lda $D010 ; Position X MSB sprites 0..7
ora #$40
bne WECF3
WECEE:
lda $D010 ; Position X MSB sprites 0..7
and #$BF
WECF3:
sta $D010 ; Position X MSB sprites 0..7
sty $D00C ; Position X sprite 6
rts
ldx #$7B
lda #$19
jsr _enable_fcbank0
sec
lda $0DC7
sbc $FE
sta $A4
lda $0DC8
sbc $FF
bmi @rts
beq :+
lda #$20
: lsr $A4
lsr $A4
lsr $A4
ora $A4
sta $A4
lda $FE
and #$07
sta $A7
eor #$07
sta $A5
lda $FF
sta $A8
ldy #$00
jsr $1D28
ldx $A8
inx
stx $FF
lda $FE
tax
and #$F8
sta $FE
txa
and #$07
sta $A5
eor #$07
sta $A7
ldy #$40
lda $A4
sta $A6
@2: lda #$00
ldx $A5
@1: sta ($FE),y
iny
bne :+
inc $FF
: dex
bpl @1
tya
clc
adc $A7
bcc :+
inc $FF
: tay
dec $A6
bpl @2
@rts: rts
ldx $8B
ldy $8C
stx $0DC5
sty $0DC6
jsr $1C97
jmp $1D62
ldx $8B
ldy $8C
stx $0DC5
sty $0DC6
lda $0DBF
ldx $0DC7
ldy $0DC8
sta $0DB8
stx $0DB9
sty $0DBA
lda $0DC9
sta $0DCC
ldy $0DCC
cpy $0DCB
beq WEDE3
iny
inc $0DCC
lda $8B
beq :+
cmp $0DCD,y
beq WEDE3
: sta $0DCD,y
lda $0DE6,y
sta $0DBF
jsr $14B5
ldx $0DBE
ldy $0DBF
lda #$02
jsr _enable_fcbank0
ldx #$2A
ldy #$01
stx $8D
sty $8E
jsr $1C5C
jsr $1C7A
jsr $1CDA
ldy #$00
lda ($8B),y
beq :+
jsr $1C97
: jmp $1D7A
WEDE3:
lda $0DB8
ldx $0DB9
ldy $0DBA
sta $0DBF
stx $0DC7
sty $0DC8
ldx $0DC5
ldy $0DC6
stx $8B
sty $8C
rts
samurai:
lda $0DCB
sta $A4
lda #$2A
lsr
lsr
lsr
ldx #$01
beq :+
ora #$20
: sta $F7
inc $F7
rts
ninja:
lda $0E02
sta $C3
jsr $1DE0
@3: lda $0E03
sta $A9
@2: ldx $0E01
ldy $C3
lda #$02
jsr _enable_fcbank0
ldx $FE
ldy $FF
stx $A7
sty $A8
ldx #$00
ldy $0E03
lda #$0C
jsr _enable_fcbank0
ldx $FE
ldy $FF
stx $A5
sty $A6
inc $C3
ldy #$00
ldx $F7
@1: lda ($A5),y
sta ($A7),y
tya
clc
adc #$08
tay
bne :+
inc $A6
inc $A8
: dex
bne @1
dec $A9
bne @2
dec $A4
bne @3
ldy $0DCB
lda #$00
sta $0DCD,y
rts
ldy $0DCB
lda $0DE6,y
sta $C3
jsr $1DE0
@5: lda $0E03
sta $A9
@6: dec $C3
ldx $0E01
ldy $C3
lda #$02
jsr _enable_fcbank0
ldx $FE
ldy $FF
stx $A7
sty $A8
ldx #$00
ldy $0E03
lda #$0C
jsr _enable_fcbank0
ldx $FE
ldy $FF
stx $A5
sty $A6
ldy #$00
ldx $F7
@4: lda ($A7),y
sta ($A5),y
tya
clc
adc #$08
tay
bne :+
inc $A6
inc $A8
: dex
bne @4
dec $A9
bne @6
dec $A4
bne @5
ldx $0DCB
dex
: lda $0DCD,x
sta $0DCE,x
dex
bpl :-
rts
lda $35
cmp #$01
bne :+
lda $36
cmp #$58
bne :+
lda $8B
cmp #$FF
bne :+
lda $8C
cmp #$7F
bne :+
sec
rts
: clc
rts
WEEED:
ldx #$A0
ldy #$46
sty $A3
stx $A4
ldx #$50
ldy #$3C
jmp _enable_fcbank0
WEEFC:
ldx #$50
ldy #$3C
lda #$02
jsr _enable_fcbank0
ldx #$A0
ldy #$46
rts
sec
lda $B4
sbc $C000
sta $9F
sec
lda $B6
sbc $C001
sta $96
rts
lda #$4B
jsr $1ECD
jsr $1EDC
lda #$08
jsr _enable_fcbank0
; ????
ldx #$51
ldy #$3D
lda #$02
jsr _enable_fcbank0
ldx #$9E
ldy #$44
lda #$06
jsr _enable_fcbank0
ldx #$50
ldy #$3C
stx $C000
sty $C001
ldx #$EE
ldy #$0F
WEF48:
lda #$23
jsr _enable_fcbank0
ldx $C014
ldy $C015
bne WEF48
; ?????
ldx #$5F
ldy #$53
lda #$02
jsr _enable_fcbank0
ldx #$82
ldy #$0A
lda #$09
jsr _enable_fcbank0
jsr $1EDC
lda #$09
jsr _enable_fcbank0
jsr $1F5C
lda #$4C
jsr $1ECD
lda #$00
sta $C6
rts
WEF7C:
ldx #$50
ldy #$3C
stx $C000
sty $C001
@1: lda $03C8
bne @1
jsr $1EEA
ldx #$EE
ldy #$0F
: lda #$22
jsr _enable_fcbank0
lda #$35
jsr _enable_fcbank0
bcs :+
ldx $C014
ldy $C015
bne :-
beq @1
: ldy #$1E
: lda $0100,y
sta $5790,y
dey
bpl :-
lda #$37
jsr _enable_fcbank0
ldy #$1E
: lda $5790,y
sta $0100,y
dey
bpl :-
ldy #$0F
lda ($9B),y
cmp #$03
bne :+
lda $03C8
sta $D00D ; Position Y sprite 6
beq WEF7C
: sta $0DC0
ldy #$FF
WEFD8:
iny
lda $104E,y
cmp #$61
bcc :+
cmp #$7B
bcs :+
eor #$20
: sta $105F,y
tax
bne WEFD8
sty $1070
rts
jsr $1B18
txa
bne :+
jsr $10F0
jsr $19EF
: rts
jmp $1B21
.segment "mysterybytes3"
.byte $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $00, $00, $00, $00, $00, $00, $00, $00
.byte $33, $33, $33, $33, $33, $33, $33, $33
.byte $33, $33, $33, $33, $33, $33, $33, $33
.byte $00
.segment "mysterybytes4"
.byte $00, $00, $00, $00, $FF, $FF, $FF, $FF
.byte $00, $00, $00, $00, $FF, $FF, $FF, $FF
.byte $00, $00, $00, $00, $FF, $FF, $FF, $FF
.byte $00, $00, $00, $00, $FF, $FF, $FF, $FF
.byte $00, $00, $00, $00, $FF, $FF, $FF, $FF
.byte $00, $00, $00, $00, $FF, $FF, $FF, $FF
.byte $00, $00, $00, $00, $FF, $FF, $FF, $FF
.byte $00, $00
.segment "mysterybytes5"
.byte $FF, $FF, $FF, $00, $00, $00, $00, $FF
.byte $F7, $FF, $FF, $00, $00, $00, $00, $FF
.byte $FF, $FF, $FF, $00, $00, $00, $00, $FF
.byte $FF, $FF, $FF, $00, $00, $00, $00, $FF
.byte $FF, $FF, $FF, $00, $00, $00, $00, $FF
.byte $FF, $FF, $FF, $00, $00, $00, $00, $FF
.byte $FF, $FF, $FF, $00, $00, $00, $00, $FF
.byte $FF, $FF, $FF, $00, $00, $00, $00, $FF
.byte $FF, $FF, $FF, $00, $00, $00, $00, $FF
.byte $FF, $FF, $FF, $00, $00
|
mist64/final_cartridge | 9,806 | bank3/freezer_game.s | ;*****************************************************************************
; Final Cartridge III reconstructed source code
;
; This file implements the functions of the game menu of the freezer
;*****************************************************************************
.setcpu "6502x"
.include "../core/kernal.i"
.include "../core/fc3ioreg.i"
.include "persistent.i"
.import _jmp_bank,_enable_fcbank0,_disable_fc3rom_set_01
.import freezer_set_c64and_fc3_rts
.import freezer_ultimax_exec_menu
.import autofire_lda_dc01,autofire_ldx_dc01,autofire_ldy_dc01
.import autofire_lda_dc00,autofire_ldx_dc00,autofire_ldy_dc00
.import __romio2l_RUN__
.importzp __FREEZERZP_START__,__FREEZERZP_SIZE__
.import __tape_backup_loader_LOAD__,__tape_backup_loader_SIZE__
.import __disk_backup_loader_LOAD__,__disk_backup_loader_SIZE__
.importzp __zp_load_mem_1_RUN__,__zp_load_mem_2_RUN__
.import __freezer_restore_1_LOAD__,__freezer_restore_1_SIZE__
.import __freezer_restore_2_RUN__,__freezer_restore_2_SIZE__
.import __memswap_LOAD__
.importzp __memswap_RUN__,__memswap_SIZE__
.importzp tmpptr_a,tmpvar1
.segment "freezer_game_swap"
swap_8000_4000:
ldy #$80 ; Swap from $8000
.byte $2c ; bit $xxxx (3 byte nop)
swap_c000_4000:
ldy #$c0
ldx #__memswap_SIZE__-1
: lda __memswap_LOAD__,x
sta __memswap_RUN__,x
dex
bpl :-
sty <(swap_zpcode_ptr2+1)
ldx #$40 ; Number of pages
lda #$34 ; Hide ROM
ldy #$00
sei
jmp swap_zpcode
.segment "memswap":zeropage
.proc swap_zpcode
sta $01
: lda (ptr1),y ; load a byte from $4000+
pha ; and save to stack
lda (ptr2),y ; load a byte from $8000+ or $c000+
sta (ptr1),y ; store into $4000x
pla ; restore saved byte
sta (ptr2),y ; save into $8000+ or $c000+
iny ; inc low byte
bne :-
inc <(ptr1+1) ; inc high byte of $4000 pointer
inc <(ptr2+1) ; inc high byte of $8000/$c000 pointer
dex ; dec page counter
bne :- ; loop until all pages have been swapped
lda #$37 ; BASIC, KERNAL and IO visible
sta $01
rts
ptr1: .word $4000
ptr2: .word $8000
.endproc
swap_zpcode_ptr2 = swap_zpcode::ptr2 ; Necessary because ca65 only knows scope after it has been defined.
.segment "freezer_game"
; These are the opcodes for
; lda absolute
; ldx absolute
; ldy absolute
; lda absolute,x
; lda absolute,y
load_abs_opcodes: .byte $ad,$ae,$ac,$bd,$b9
; These are the opcodes for
; lda #imm
; ldx #imm
; ldy #imm
load_imm_opcodes: .byte $a9,$a2,$a0
autofire_traps:
.byte <autofire_lda_dc01,<autofire_ldx_dc01,<autofire_ldy_dc01
.byte <autofire_lda_dc00,<autofire_ldx_dc00,<autofire_ldy_dc00
.byte $2a,$24
.global freezer_joyswap
freezer_joyswap:
jsr joyswap_patch_code_0200
jsr swap_8000_4000
jsr joyswap_patch_code_4000
jsr swap_8000_4000
jsr swap_c000_4000
jsr joyswap_patch_code_4000
jsr swap_c000_4000
ldy #$35
jmp _disable_fc3rom_set_01
.global freezer_autofire
freezer_autofire:
jsr autofire_patch_code_0200
jsr swap_8000_4000
jsr autofire_patch_code_4000
jsr swap_8000_4000
jsr swap_c000_4000
jsr autofire_patch_code_4000
jsr swap_c000_4000
lda #$02
sta $0120
sta $0121
lda #fcio_c64_crtrom_off|fcio_nmi_line|fcio_bank_3
ldy #$35 ; ROM hidden, I/O visible
jmp freezer_set_c64and_fc3_rts
.global freezer_sprite_I,freezer_sprite_II
freezer_sprite_I:
lda #$1E
.byte $2c
freezer_sprite_II:
lda #$1F
sta tmpvar1
jsr sprite_patch_code_0200
jsr swap_8000_4000
jsr sprite_patch_code_4000
jsr swap_8000_4000
jsr swap_c000_4000
jsr sprite_patch_code_4000
jsr swap_c000_4000
ldy #$35 ; IO only
jmp _disable_fc3rom_set_01
autofire_patch_code_0200:
lda #$02 ; High byte of start pointer
.byte $2c ; bit $xxxx (3 byte nop)
autofire_patch_code_4000:
lda #$40 ; High byte of start pointer
sta tmpptr_a+1
ldy #$00 ; Low byte of start pointer
sty tmpptr_a
@1: ldx #.sizeof(load_abs_opcodes)
ldy #0
lda (tmpptr_a),y ; Load a byte from RAM
: dex ; All opcodes checked?
bmi @4 ; Then jump to prepare for next byte
cmp load_abs_opcodes,x ; Compare with an opcode
bne :- ; Not equal, then next opcpde
; Byte matches a load opcode
iny
lda (tmpptr_a),y ; Load next byte from RAM (should be low byte of absolute address)
beq @2 ; 0? CIA port A is low byte $00.
cpx #$03 ; Was it a load with index?
bcs @4 ; If yes, it's not what we are looking for
cmp #$01 ; 1? CIA port B is low byte $01
bne @4
@2: sta tmpvar1 ; Store low byte
iny
lda (tmpptr_a),y ; Load next byte from RAM (should be high byte of absolute address)
cmp #$DC ; $DCxx is CIA 1
bne @4
ldy #$00 ; Point back to opcode
lda #$20 ; Opcode of JSR absolute
sta (tmpptr_a),y ; Replace opcode with JSR (code will JSR into trap)
iny
lda tmpvar1 ; Restore low byte
bne @3 ; If 1 then no need to add table index
; It was a load from CIA port A
txa
clc
adc #3 ; Traps for port A start at 3 in table
tax
@3: lda autofire_traps,x ; Load low byte of pointer to trap
sta (tmpptr_a),y ; Patch into instruction
iny
lda #>__romio2l_RUN__ ; $DFxx
sta (tmpptr_a),y ; Patch into instruction
@4:
inc tmpptr_a ; inc low byte of pointer
bne @1
inc tmpptr_a+1 ; inc high byte of pointer
lda tmpptr_a+1
cmp #$80 ; cartridge rom starts at $8000
bcc @1 ; when we arrive here, stop scanning
rts
joyswap_patch_code_0200:
lda #$02 ; High byte of start pointer
.byte $2c ; bit $xxxx (3 byte nop)
joyswap_patch_code_4000:
lda #$40 ; High byte of start pointer
sta tmpptr_a+1
lda #$00 ; Low byte of start pointer
sta tmpptr_a
@1: ldx #$03 ; Check 3 opcodes
ldy #0
lda (tmpptr_a),y ; Load a byte from RAM
@2: dex
bmi @3
cmp load_abs_opcodes,x
bne @2
iny
lda (tmpptr_a),y ; Load next byte from RAM (should be low byte of absolute address)
sta tmpvar1 ; Store low byte
cmp #$04
bcs @3
iny
lda (tmpptr_a),y ; Load next byte from RAM (should be high byte of absolute address)
cmp #$DC ; $DCxx is CIA 1
bne @3
dey
lda tmpvar1 ; Restore low byte
eor #$01 ; Swap $dc01 with $dc00 to swap joystick port
sta (tmpptr_a),y ; Patch into instruction
@3: inc tmpptr_a
bne @1
inc tmpptr_a+1
lda tmpptr_a+1
cmp #$80 ; cartridge rom starts at $8000
bcc @1 ; when we arrive here, stop scanning
rts
sprite_patch_code_0200:
lda #$02 ; High byte of start pointer
.byte $2c ; bit $xxxx (3 byte nop)
sprite_patch_code_4000:
lda #$40 ; High byte of start pointer
sta tmpptr_a+1
lda #$00 ; Low byte of start pointer
sta tmpptr_a
@1: ldx #$03 ; Check 3 opcodes
ldy #0
lda (tmpptr_a),y ; Load a byte from RAM
@2: dex
bmi @4
cmp load_abs_opcodes,x
bne @2
iny
lda (tmpptr_a),y ; Load next byte from RAM (should be low byte of absolute address)
cmp tmpvar1 ; Is low byte the relevant sprite collision register?
bne @4
@3: iny
lda (tmpptr_a),y ; Load next byte from RAM (should be high byte of absolute address)
cmp #>$D000 ; $D0xx is VIC-II
bne @4
lda load_imm_opcodes,x
ldy #0
sta (tmpptr_a),y ; Patch opcode into memory
tya
iny
sta (tmpptr_a),y ; Change into LDx #0
lda #$EA ; NOP
iny
sta (tmpptr_a),y ; Place nop in memory
@4: inc tmpptr_a
bne @1
inc tmpptr_a+1
lda tmpptr_a+1
cmp #$80
bcc @1
rts
|
mist64/final_cartridge | 77,026 | bank3/freezer_menu.s | ;*****************************************************************************
; Final Cartridge III reconstructed source code
;
; This file contains the NMI interrupt handler for the frezer. The actual
; NMI occurs in bank 0, but the NMI handler is duplicated in both banks and
; the NMI handler in bank 0 quickly changes to bank 3 to continue.
;
; This file also contains the graphics and code for the freezer menu and
; the graphics and code for the screenshot preview function in the freezer.
;
;*****************************************************************************
.setcpu "6502x"
.include "persistent.i"
.include "../core/fc3ioreg.i"
.importzp ciareg_backup
.importzp viciireg_backup
.importzp spritexy_backup
.importzp colram_backup
.macro MonoSpriteLine tribyte
.byte tribyte >> 16, ( tribyte >> 8) & 255, tribyte & 255
.endmacro
freezer_prepare = $DFE0
.segment "freezer_graphics"
freezer_screenram:
.byte 5, 6, 7, 8, 9, 10, 11, 12
.byte 13, 14, 15, 16, 17, 18, 19, 20
.byte 21, 22, 23, 24, 25, 26, 27, 28
.byte 29, 30, 31, 32, 33, 34, 35, 36
.byte 37, 38, 39, 11, 11, 11, 11, 11
; ▉▉▉░░░░▉▉▉▉░░▉▉▉▉░░░▉▉░▉▉▉░▉░▉▉▉░▉░░░░▉▉▉▉▉▉▉▉▉▉
; ▉▉▉░▉▉▉░▉▉░▉▉░▉▉░▉▉▉░▉░▉▉░▉▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉▉▉▉▉
; ▉▉▉░▉▉▉░▉░▉▉▉▉░▉░▉▉▉▉▉░▉░▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉▉▉▉▉
; ▉▉▉░░░░▉▉░▉▉▉▉░▉░▉▉▉▉▉░░▉▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉▉▉▉▉
; ▉▉▉░▉▉▉░▉░░░░░░▉░▉▉▉▉▉░▉░▉▉▉░▉▉▉░▉░░░░▉▉▉▉▉▉▉▉▉▉
; ▉▉▉░▉▉▉░▉░▉▉▉▉░▉░▉▉▉░▉░▉▉░▉▉░▉▉▉░▉░▉▉▉▉▉▉▉▉▉▉▉▉▉
; ▉▉▉░░░░▉▉░▉▉▉▉░▉▉░░░▉▉░▉▉▉░▉▉░░░░▉░▉▉▉▉▉▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
freezer_bar_charset:
.byte %11100001, %11101110, %11101110, %11100001, %11101110, %11101110, %11100001, %11111111
.byte %11100111, %11011011, %10111101, %10111101, %10000001, %10111101, %10111101, %11111111
.byte %10001101, %01110101, %01111101, %01111100, %01111101, %01110101, %10001101, %11111111
.byte %11010111, %10110111, %01110111, %11110111, %01110111, %10110111, %11011000, %11111111
.byte %01000011, %01011101, %01011101, %01011101, %01000011, %01011111, %01011111, %11111111
.byte %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111
; ▉▉▉▉▉▉▉▉▉▉▉▉░░░▉▉▉▉░░▉▉▉░▉▉▉▉▉░▉░░░░▉▉▉▉▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉░▉▉▉░▉▉░▉▉░▉▉░░▉▉▉░░▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉░▉▉▉▉▉░▉▉▉▉░▉░▉░▉░▉░▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉░▉▉░░▉░▉▉▉▉░▉░▉▉░▉▉░▉░░░▉▉▉▉▉▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉░▉▉▉░▉░░░░░░▉░▉▉▉▉▉░▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉░▉▉▉░▉░▉▉▉▉░▉░▉▉▉▉▉░▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉░░░▉▉░▉▉▉▉░▉░▉▉▉▉▉░▉░░░░▉▉▉▉▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
.byte %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111
.byte %11110001, %11101110, %11101111, %11101100, %11101110, %11101110, %11110001, %11111111
.byte %11100111, %11011011, %10111101, %10111101, %10000001, %10111101, %10111101, %11111111
.byte %01111101, %00111001, %01010101, %01101101, %01111101, %01111101, %01111101, %11111111
.byte %00001111, %01111111, %01111111, %00011111, %01111111, %01111111, %00001111, %11111111
.byte %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111
; ▉▉▉▉▉▉▉▉▉▉▉▉░░░▉▉▉░░░▉▉░▉▉▉▉░░░▉▉░░░░▉▉▉░░░░▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉░▉▉▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉░▉▉▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉░▉░▉▉▉░▉▉░░░▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉░▉▉▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉░▉░░░░▉▉▉▉▉▉░▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉▉░▉▉▉░▉░▉▉░▉▉▉▉▉▉░▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉░░░▉▉▉░░░▉▉░░░▉▉░░░▉▉░▉▉▉░▉░░░░▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
.byte %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111
.byte %11110001, %11101110, %11101111, %11101111, %11101111, %11101110, %11110001, %11111111
.byte %11000110, %10111010, %10111010, %10111010, %10111010, %10111010, %11000110, %11111111
.byte %11110001, %11101110, %11101110, %11101110, %11101110, %11101110, %00110001, %11111111
.byte %10000111, %10111010, %10111010, %10111011, %10000111, %10110111, %10111010, %11111111
.byte %00001111, %11111111, %11111111, %00011111, %11101111, %11101111, %00011111, %11111111
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░░░░▉▉░░░░▉▉░▉░▉▉▉▉░▉░░░░░▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░▉▉▉░▉░▉▉▉░▉░▉░░▉▉▉░▉▉▉░▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░▉▉▉░▉░▉▉▉░▉░▉░▉░▉▉░▉▉▉░▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░▉▉▉░▉░▉▉▉░▉░▉░▉▉░▉░▉▉▉░▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░░░░▉▉░░░░▉▉░▉░▉▉▉░░▉▉▉░▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░▉▉▉▉▉░▉▉░▉▉░▉░▉▉▉▉░▉▉▉░▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░▉▉▉▉▉░▉▉▉░▉░▉░▉▉▉▉░▉▉▉░▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
.byte %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111
.byte %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111
.byte %11100001, %11101110, %11101110, %11101110, %11100001, %11101111, %11101111, %11111111
.byte %10000110, %10111010, %10111010, %10111010, %10000110, %10110110, %10111010, %11111111
.byte %10111101, %10011101, %10101101, %10110101, %10111001, %10111101, %10111101, %11111111
.byte %00000111, %11011111, %11011111, %11011111, %11011111, %11011111, %11011111, %11111111
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░░░░▉▉░░░░▉▉░░░░▉░░░░▉░░░░░▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░▉▉▉░▉░▉▉▉▉░▉▉▉▉▉░▉▉▉▉▉▉░▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░▉▉▉░▉░▉▉▉▉░▉▉▉▉▉░▉▉▉▉▉▉░▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░▉▉▉░▉░░░▉▉▉░░░▉▉░░░▉▉▉▉░▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░░░░▉▉░▉▉▉▉▉▉▉▉░▉░▉▉▉▉▉▉░▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░▉▉░▉▉░▉▉▉▉▉▉▉▉░▉░▉▉▉▉▉▉░▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░▉▉▉░▉░░░░▉░░░░▉▉░░░░▉▉▉░▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
.byte %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111
.byte %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111
.byte %11100001, %11101110, %11101110, %11101110, %11100001, %11101101, %11101110, %11111111
.byte %10000110, %10111101, %10111101, %10001110, %10111111, %10111111, %10000100, %11111111
.byte %00010000, %11110111, %11110111, %00110001, %11010111, %11010111, %00110000, %11111111
.byte %10000011, %11101111, %11101111, %11101111, %11101111, %11101111, %11101111, %11111111
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░░░░▉░▉▉▉░▉░▉░░░░░▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░▉▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░▉▉▉▉▉░▉░▉▉░▉▉▉░▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░░░▉▉▉▉░▉▉▉░▉▉▉░▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░▉▉▉▉▉░▉░▉▉░▉▉▉░▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░▉▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉░░░░▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
.byte %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111
.byte %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111
.byte %11100001, %11101111, %11101111, %11100011, %11101111, %11101111, %11100001, %11111111
.byte %01110101, %01110101, %10101101, %11011101, %10101101, %01110101, %01110101, %11111111
.byte %00000111, %11011111, %11011111, %11011111, %11011111, %11011111, %11011111, %11111111
freezer_backup_lb:
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111000011011000010111011 ; ▉▉▉░░░░▉▉░▉▉░░░░▉░▉▉▉░▉▉
MonoSpriteLine %111011101010111110110111 ; ▉▉▉░▉▉▉░▉░▉░▉▉▉▉▉░▉▉░▉▉▉
MonoSpriteLine %111011101010111110101111 ; ▉▉▉░▉▉▉░▉░▉░▉▉▉▉▉░▉░▉▉▉▉
MonoSpriteLine %111011101011000110011111 ; ▉▉▉░▉▉▉░▉░▉▉░░░▉▉░░▉▉▉▉▉
MonoSpriteLine %111011101011111010101111 ; ▉▉▉░▉▉▉░▉░▉▉▉▉▉░▉░▉░▉▉▉▉
MonoSpriteLine %111011101011111010110111 ; ▉▉▉░▉▉▉░▉░▉▉▉▉▉░▉░▉▉░▉▉▉
MonoSpriteLine %111000011010000110111011 ; ▉▉▉░░░░▉▉░▉░░░░▉▉░▉▉▉░▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111000001110011100001100 ; ▉▉▉░░░░░▉▉▉░░▉▉▉░░░░▉▉░░
MonoSpriteLine %111110111101101101110101 ; ▉▉▉▉▉░▉▉▉▉░▉▉░▉▉░▉▉▉░▉░▉
MonoSpriteLine %111110111011110101110101 ; ▉▉▉▉▉░▉▉▉░▉▉▉▉░▉░▉▉▉░▉░▉
MonoSpriteLine %111110111011110101110100 ; ▉▉▉▉▉░▉▉▉░▉▉▉▉░▉░▉▉▉░▉░░
MonoSpriteLine %111110111000000100001101 ; ▉▉▉▉▉░▉▉▉░░░░░░▉░░░░▉▉░▉
MonoSpriteLine %111110111011110101111101 ; ▉▉▉▉▉░▉▉▉░▉▉▉▉░▉░▉▉▉▉▉░▉
MonoSpriteLine %111110111011110101111100 ; ▉▉▉▉▉░▉▉▉░▉▉▉▉░▉░▉▉▉▉▉░░
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111000011110000110110000 ; ▉▉▉░░░░▉▉▉▉░░░░▉▉░▉▉░░░░
MonoSpriteLine %111011111110111010101111 ; ▉▉▉░▉▉▉▉▉▉▉░▉▉▉░▉░▉░▉▉▉▉
MonoSpriteLine %111011111110111010101111 ; ▉▉▉░▉▉▉▉▉▉▉░▉▉▉░▉░▉░▉▉▉▉
MonoSpriteLine %111000111110111010110001 ; ▉▉▉░░░▉▉▉▉▉░▉▉▉░▉░▉▉░░░▉
.byte $EF
freezer_backup_rb:
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %001111111111111111111111 ; ░░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %011111111111111111111111 ; ░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %001111111111111111111111 ; ░░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %101110111111111111111111 ; ▉░▉▉▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %101101111111111111111111 ; ▉░▉▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %101011111111111111111111 ; ▉░▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %100111111111111111111111 ; ▉░░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
.byte $AF
freezer_backup_lo:
MonoSpriteLine %111011111110111010111110 ; ▉▉▉░▉▉▉▉▉▉▉░▉▉▉░▉░▉▉▉▉▉░
MonoSpriteLine %111011111110111010111110 ; ▉▉▉░▉▉▉▉▉▉▉░▉▉▉░▉░▉▉▉▉▉░
MonoSpriteLine %111011111110000110100001 ; ▉▉▉░▉▉▉▉▉▉▉░░░░▉▉░▉░░░░▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111000011110000011100111 ; ▉▉▉░░░░▉▉▉▉░░░░░▉▉▉░░▉▉▉
MonoSpriteLine %111011111111101111011011 ; ▉▉▉░▉▉▉▉▉▉▉▉▉░▉▉▉▉░▉▉░▉▉
MonoSpriteLine %111011111111101110111101 ; ▉▉▉░▉▉▉▉▉▉▉▉▉░▉▉▉░▉▉▉▉░▉
MonoSpriteLine %111000111111101110111101 ; ▉▉▉░░░▉▉▉▉▉▉▉░▉▉▉░▉▉▉▉░▉
MonoSpriteLine %111011111111101110000001 ; ▉▉▉░▉▉▉▉▉▉▉▉▉░▉▉▉░░░░░░▉
MonoSpriteLine %111011111111101110111101 ; ▉▉▉░▉▉▉▉▉▉▉▉▉░▉▉▉░▉▉▉▉░▉
MonoSpriteLine %111011111111101110111101 ; ▉▉▉░▉▉▉▉▉▉▉▉▉░▉▉▉░▉▉▉▉░▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
.byte $00
freezer_backup_ro:
MonoSpriteLine %101011111111111111111111 ; ▉░▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %101101111111111111111111 ; ▉░▉▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %101110111111111111111111 ; ▉░▉▉▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000011000011111111111111 ; ░░░░▉▉░░░░▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %011101011111111111111111 ; ░▉▉▉░▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %011101011111111111111111 ; ░▉▉▉░▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %011101000111111111111111 ; ░▉▉▉░▉░░░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000011011111111111111111 ; ░░░░▉▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %011111011111111111111111 ; ░▉▉▉▉▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %011111000011111111111111 ; ░▉▉▉▉▉░░░░▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
.byte $00
freezer_game_lb:
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111100001000011000011010 ; ▉▉▉▉░░░░▉░░░░▉▉░░░░▉▉░▉░
MonoSpriteLine %111011111011101011101011 ; ▉▉▉░▉▉▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉
MonoSpriteLine %111011111011101011101011 ; ▉▉▉░▉▉▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉
MonoSpriteLine %111100011011101011101011 ; ▉▉▉▉░░░▉▉░▉▉▉░▉░▉▉▉░▉░▉▉
MonoSpriteLine %111111101000011000011011 ; ▉▉▉▉▉▉▉░▉░░░░▉▉░░░░▉▉░▉▉
MonoSpriteLine %111111101011111011011011 ; ▉▉▉▉▉▉▉░▉░▉▉▉▉▉░▉▉░▉▉░▉▉
MonoSpriteLine %111000011011111011101011 ; ▉▉▉░░░░▉▉░▉▉▉▉▉░▉▉▉░▉░▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111100001000011000011010 ; ▉▉▉▉░░░░▉░░░░▉▉░░░░▉▉░▉░
MonoSpriteLine %111011111011101011101011 ; ▉▉▉░▉▉▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉
MonoSpriteLine %111011111011101011101011 ; ▉▉▉░▉▉▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉
MonoSpriteLine %111100011011101011101011 ; ▉▉▉▉░░░▉▉░▉▉▉░▉░▉▉▉░▉░▉▉
MonoSpriteLine %111111101000011000011011 ; ▉▉▉▉▉▉▉░▉░░░░▉▉░░░░▉▉░▉▉
MonoSpriteLine %111111101011111011011011 ; ▉▉▉▉▉▉▉░▉░▉▉▉▉▉░▉▉░▉▉░▉▉
MonoSpriteLine %111000011011111011101011 ; ▉▉▉░░░░▉▉░▉▉▉▉▉░▉▉▉░▉░▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111011000110111011000 ; ▉▉▉▉▉▉░▉▉░░░▉▉░▉▉▉░▉▉░░░
MonoSpriteLine %111111010111010111010111 ; ▉▉▉▉▉▉░▉░▉▉▉░▉░▉▉▉░▉░▉▉▉
MonoSpriteLine %111111010111010111010111 ; ▉▉▉▉▉▉░▉░▉▉▉░▉░▉▉▉░▉░▉▉▉
MonoSpriteLine %111111010111011010111000 ; ▉▉▉▉▉▉░▉░▉▉▉░▉▉░▉░▉▉▉░░░
.byte $FD
freezer_game_rb:
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000010000111101111111111 ; ░░░░▉░░░░▉▉▉▉░▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %101110111111101111111111 ; ▉░▉▉▉░▉▉▉▉▉▉▉░▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %101110111111101111111111 ; ▉░▉▉▉░▉▉▉▉▉▉▉░▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %101110001111101111111111 ; ▉░▉▉▉░░░▉▉▉▉▉░▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %101110111111101111111111 ; ▉░▉▉▉░▉▉▉▉▉▉▉░▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %101110111111101111111111 ; ▉░▉▉▉░▉▉▉▉▉▉▉░▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %101110000111101111111111 ; ▉░▉▉▉░░░░▉▉▉▉░▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000010000111101011111111 ; ░░░░▉░░░░▉▉▉▉░▉░▉▉▉▉▉▉▉▉
MonoSpriteLine %101110111111101011111111 ; ▉░▉▉▉░▉▉▉▉▉▉▉░▉░▉▉▉▉▉▉▉▉
MonoSpriteLine %101110111111101011111111 ; ▉░▉▉▉░▉▉▉▉▉▉▉░▉░▉▉▉▉▉▉▉▉
MonoSpriteLine %101110001111101011111111 ; ▉░▉▉▉░░░▉▉▉▉▉░▉░▉▉▉▉▉▉▉▉
MonoSpriteLine %101110111111101011111111 ; ▉░▉▉▉░▉▉▉▉▉▉▉░▉░▉▉▉▉▉▉▉▉
MonoSpriteLine %101110111111101011111111 ; ▉░▉▉▉░▉▉▉▉▉▉▉░▉░▉▉▉▉▉▉▉▉
MonoSpriteLine %101110000111101011111111 ; ▉░▉▉▉░░░░▉▉▉▉░▉░▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %010111110111001110000111 ; ░▉░▉▉▉▉▉░▉▉▉░░▉▉▉░░░░▉▉▉
MonoSpriteLine %110111110110110110111011 ; ▉▉░▉▉▉▉▉░▉▉░▉▉░▉▉░▉▉▉░▉▉
MonoSpriteLine %110111110101111010111011 ; ▉▉░▉▉▉▉▉░▉░▉▉▉▉░▉░▉▉▉░▉▉
MonoSpriteLine %110110110101111010111011 ; ▉▉░▉▉░▉▉░▉░▉▉▉▉░▉░▉▉▉░▉▉
.byte $55
freezer_game_lo:
MonoSpriteLine %111111010111011101111111 ; ▉▉▉▉▉▉░▉░▉▉▉░▉▉▉░▉▉▉▉▉▉▉
MonoSpriteLine %111111000111011101111111 ; ▉▉▉▉▉▉░░░▉▉▉░▉▉▉░▉▉▉▉▉▉▉
MonoSpriteLine %111000111000111101110000 ; ▉▉▉░░░▉▉▉░░░▉▉▉▉░▉▉▉░░░░
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111110011101110100000110 ; ▉▉▉▉▉░░▉▉▉░▉▉▉░▉░░░░░▉▉░
MonoSpriteLine %111101101101110111011101 ; ▉▉▉▉░▉▉░▉▉░▉▉▉░▉▉▉░▉▉▉░▉
MonoSpriteLine %111011110101110111011101 ; ▉▉▉░▉▉▉▉░▉░▉▉▉░▉▉▉░▉▉▉░▉
MonoSpriteLine %111011110101110111011101 ; ▉▉▉░▉▉▉▉░▉░▉▉▉░▉▉▉░▉▉▉░▉
MonoSpriteLine %111000000101110111011101 ; ▉▉▉░░░░░░▉░▉▉▉░▉▉▉░▉▉▉░▉
MonoSpriteLine %111011110101110111011101 ; ▉▉▉░▉▉▉▉░▉░▉▉▉░▉▉▉░▉▉▉░▉
MonoSpriteLine %111011110110000111011110 ; ▉▉▉░▉▉▉▉░▉▉░░░░▉▉▉░▉▉▉▉░
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
.byte $FF
freezer_game_ro:
MonoSpriteLine %010101010100000010000111 ; ░▉░▉░▉░▉░▉░░░░░░▉░░░░▉▉▉
MonoSpriteLine %010011100101111010111111 ; ░▉░░▉▉▉░░▉░▉▉▉▉░▉░▉▉▉▉▉▉
MonoSpriteLine %110111110101111010111111 ; ▉▉░▉▉▉▉▉░▉░▉▉▉▉░▉░▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %001100001010000110000111 ; ░░▉▉░░░░▉░▉░░░░▉▉░░░░▉▉▉
MonoSpriteLine %110101111010111010111111 ; ▉▉░▉░▉▉▉▉░▉░▉▉▉░▉░▉▉▉▉▉▉
MonoSpriteLine %110101111010111010111111 ; ▉▉░▉░▉▉▉▉░▉░▉▉▉░▉░▉▉▉▉▉▉
MonoSpriteLine %110100011010111010001111 ; ▉▉░▉░░░▉▉░▉░▉▉▉░▉░░░▉▉▉▉
MonoSpriteLine %110101111010000110111111 ; ▉▉░▉░▉▉▉▉░▉░░░░▉▉░▉▉▉▉▉▉
MonoSpriteLine %110101111010110110111111 ; ▉▉░▉░▉▉▉▉░▉░▉▉░▉▉░▉▉▉▉▉▉
MonoSpriteLine %001101111010111010000111 ; ░░▉▉░▉▉▉▉░▉░▉▉▉░▉░░░░▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
.byte $00
freezer_colors_lb:
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111000011110011110001101 ; ▉▉▉░░░░▉▉▉▉░░▉▉▉▉░░░▉▉░▉
MonoSpriteLine %111011101101101101110101 ; ▉▉▉░▉▉▉░▉▉░▉▉░▉▉░▉▉▉░▉░▉
MonoSpriteLine %111011101011110101111101 ; ▉▉▉░▉▉▉░▉░▉▉▉▉░▉░▉▉▉▉▉░▉
MonoSpriteLine %111000011011110101111100 ; ▉▉▉░░░░▉▉░▉▉▉▉░▉░▉▉▉▉▉░░
MonoSpriteLine %111011101000000101111101 ; ▉▉▉░▉▉▉░▉░░░░░░▉░▉▉▉▉▉░▉
MonoSpriteLine %111011101011110101110101 ; ▉▉▉░▉▉▉░▉░▉▉▉▉░▉░▉▉▉░▉░▉
MonoSpriteLine %111000011011110110001101 ; ▉▉▉░░░░▉▉░▉▉▉▉░▉▉░░░▉▉░▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111000011000110000110000 ; ▉▉▉░░░░▉▉░░░▉▉░░░░▉▉░░░░
MonoSpriteLine %111011110111010111010111 ; ▉▉▉░▉▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉▉
MonoSpriteLine %111011110111010111010111 ; ▉▉▉░▉▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉▉
MonoSpriteLine %111000110111010111010001 ; ▉▉▉░░░▉▉░▉▉▉░▉░▉▉▉░▉░░░▉
MonoSpriteLine %111011110111010000110111 ; ▉▉▉░▉▉▉▉░▉▉▉░▉░░░░▉▉░▉▉▉
MonoSpriteLine %111011110111010110110111 ; ▉▉▉░▉▉▉▉░▉▉▉░▉░▉▉░▉▉░▉▉▉
MonoSpriteLine %111011111000110111010000 ; ▉▉▉░▉▉▉▉▉░░░▉▉░▉▉▉░▉░░░░
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111000011100011000011000 ; ▉▉▉░░░░▉▉▉░░░▉▉░░░░▉▉░░░
MonoSpriteLine %111011101011101011101011 ; ▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉▉░▉░▉▉
MonoSpriteLine %111011101011101011101011 ; ▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉▉░▉░▉▉
MonoSpriteLine %111000011011101011101011 ; ▉▉▉░░░░▉▉░▉▉▉░▉░▉▉▉░▉░▉▉
.byte $EE
freezer_colors_rb:
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %110110001101111010000111 ; ▉▉░▉▉░░░▉▉░▉▉▉▉░▉░░░░▉▉▉
MonoSpriteLine %101101110100111010111011 ; ▉░▉▉░▉▉▉░▉░░▉▉▉░▉░▉▉▉░▉▉
MonoSpriteLine %011101111101011010111011 ; ░▉▉▉░▉▉▉▉▉░▉░▉▉░▉░▉▉▉░▉▉
MonoSpriteLine %111101100101101010111011 ; ▉▉▉▉░▉▉░░▉░▉▉░▉░▉░▉▉▉░▉▉
MonoSpriteLine %011101110101110010111011 ; ░▉▉▉░▉▉▉░▉░▉▉▉░░▉░▉▉▉░▉▉
MonoSpriteLine %101101110101111010111011 ; ▉░▉▉░▉▉▉░▉░▉▉▉▉░▉░▉▉▉░▉▉
MonoSpriteLine %110110001101111010000111 ; ▉▉░▉▉░░░▉▉░▉▉▉▉░▉░░░░▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %110001101111010000111111 ; ▉▉░░░▉▉░▉▉▉▉░▉░░░░▉▉▉▉▉▉
MonoSpriteLine %101110100111010111011111 ; ▉░▉▉▉░▉░░▉▉▉░▉░▉▉▉░▉▉▉▉▉
MonoSpriteLine %101111101011010111011111 ; ▉░▉▉▉▉▉░▉░▉▉░▉░▉▉▉░▉▉▉▉▉
MonoSpriteLine %101100101101010111011111 ; ▉░▉▉░░▉░▉▉░▉░▉░▉▉▉░▉▉▉▉▉
MonoSpriteLine %101110101110010111011111 ; ▉░▉▉▉░▉░▉▉▉░░▉░▉▉▉░▉▉▉▉▉
MonoSpriteLine %101110101111010111011111 ; ▉░▉▉▉░▉░▉▉▉▉░▉░▉▉▉░▉▉▉▉▉
MonoSpriteLine %110001101111010000111111 ; ▉▉░░░▉▉░▉▉▉▉░▉░░░░▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %011000010000111111111111 ; ░▉▉░░░░▉░░░░▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %101011110111011111111111 ; ▉░▉░▉▉▉▉░▉▉▉░▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %101011110111011111111111 ; ▉░▉░▉▉▉▉░▉▉▉░▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %101000110111011111111111 ; ▉░▉░░░▉▉░▉▉▉░▉▉▉▉▉▉▉▉▉▉▉
.byte $AF
freezer_colors_lo:
MonoSpriteLine %111011101011101000011011 ; ▉▉▉░▉▉▉░▉░▉▉▉░▉░░░░▉▉░▉▉
MonoSpriteLine %111011101011101011011011 ; ▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉░▉▉░▉▉
MonoSpriteLine %111000011100011011101000 ; ▉▉▉░░░░▉▉▉░░░▉▉░▉▉▉░▉░░░
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
.byte $FF
freezer_colors_ro:
MonoSpriteLine %101011110000111111111111 ; ▉░▉░▉▉▉▉░░░░▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %101011110110111111111111 ; ▉░▉░▉▉▉▉░▉▉░▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %011000010111011111111111 ; ░▉▉░░░░▉░▉▉▉░▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
.byte $00
freezer_print_lb:
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111100001000010000010000 ; ▉▉▉▉░░░░▉░░░░▉░░░░░▉░░░░
MonoSpriteLine %111011111011111101111101 ; ▉▉▉░▉▉▉▉▉░▉▉▉▉▉▉░▉▉▉▉▉░▉
MonoSpriteLine %111011111011111101111101 ; ▉▉▉░▉▉▉▉▉░▉▉▉▉▉▉░▉▉▉▉▉░▉
MonoSpriteLine %111100011000111101111101 ; ▉▉▉▉░░░▉▉░░░▉▉▉▉░▉▉▉▉▉░▉
MonoSpriteLine %111111101011111101111101 ; ▉▉▉▉▉▉▉░▉░▉▉▉▉▉▉░▉▉▉▉▉░▉
MonoSpriteLine %111111101011111101111101 ; ▉▉▉▉▉▉▉░▉░▉▉▉▉▉▉░▉▉▉▉▉░▉
MonoSpriteLine %111000011000001101111101 ; ▉▉▉░░░░▉▉░░░░░▉▉░▉▉▉▉▉░▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111011101010000101111101 ; ▉▉▉░▉▉▉░▉░▉░░░░▉░▉▉▉▉▉░▉
MonoSpriteLine %111011101010111101111101 ; ▉▉▉░▉▉▉░▉░▉░▉▉▉▉░▉▉▉▉▉░▉
MonoSpriteLine %111011101010111101111101 ; ▉▉▉░▉▉▉░▉░▉░▉▉▉▉░▉▉▉▉▉░▉
MonoSpriteLine %111011101010001101101101 ; ▉▉▉░▉▉▉░▉░▉░░░▉▉░▉▉░▉▉░▉
MonoSpriteLine %111011101010111101010101 ; ▉▉▉░▉▉▉░▉░▉░▉▉▉▉░▉░▉░▉░▉
MonoSpriteLine %111101011010111100111001 ; ▉▉▉▉░▉░▉▉░▉░▉▉▉▉░░▉▉▉░░▉
MonoSpriteLine %111110111010000101111101 ; ▉▉▉▉▉░▉▉▉░▉░░░░▉░▉▉▉▉▉░▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111000011100001000010000 ; ▉▉▉░░░░▉▉▉░░░░▉░░░░▉░░░░
MonoSpriteLine %111011101011111011111101 ; ▉▉▉░▉▉▉░▉░▉▉▉▉▉░▉▉▉▉▉▉░▉
MonoSpriteLine %111011101011111011111101 ; ▉▉▉░▉▉▉░▉░▉▉▉▉▉░▉▉▉▉▉▉░▉
MonoSpriteLine %111011101100011000111101 ; ▉▉▉░▉▉▉░▉▉░░░▉▉░░░▉▉▉▉░▉
.byte $FF
freezer_print_rb:
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %010101111011000111000011 ; ░▉░▉░▉▉▉▉░▉▉░░░▉▉▉░░░░▉▉
MonoSpriteLine %110100111010111010111111 ; ▉▉░▉░░▉▉▉░▉░▉▉▉░▉░▉▉▉▉▉▉
MonoSpriteLine %110101011010111110111111 ; ▉▉░▉░▉░▉▉░▉░▉▉▉▉▉░▉▉▉▉▉▉
MonoSpriteLine %110101101010110011000111 ; ▉▉░▉░▉▉░▉░▉░▉▉░░▉▉░░░▉▉▉
MonoSpriteLine %110101110010111011111011 ; ▉▉░▉░▉▉▉░░▉░▉▉▉░▉▉▉▉▉░▉▉
MonoSpriteLine %110101111010111011111011 ; ▉▉░▉░▉▉▉▉░▉░▉▉▉░▉▉▉▉▉░▉▉
MonoSpriteLine %110101111011000110000111 ; ▉▉░▉░▉▉▉▉░▉▉░░░▉▉░░░░▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %011111111111111111111111 ; ░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
.byte $FF
freezer_print_lo:
MonoSpriteLine %111000011111101011111101 ; ▉▉▉░░░░▉▉▉▉▉▉░▉░▉▉▉▉▉▉░▉
MonoSpriteLine %111011111111101011111101 ; ▉▉▉░▉▉▉▉▉▉▉▉▉░▉░▉▉▉▉▉▉░▉
MonoSpriteLine %111011111000011000011101 ; ▉▉▉░▉▉▉▉▉░░░░▉▉░░░░▉▉▉░▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
.byte $FF
freezer_print_ro:
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
.byte $00
freezer_reset_lb:
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111011101010111011111111 ; ▉▉▉░▉▉▉░▉░▉░▉▉▉░▉▉▉▉▉▉▉▉
MonoSpriteLine %111011001010111011111111 ; ▉▉▉░▉▉░░▉░▉░▉▉▉░▉▉▉▉▉▉▉▉
MonoSpriteLine %111010111010111011111111 ; ▉▉▉░▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉▉▉▉
MonoSpriteLine %111001111010111011111111 ; ▉▉▉░░▉▉▉▉░▉░▉▉▉░▉▉▉▉▉▉▉▉
MonoSpriteLine %111010111010111011111111 ; ▉▉▉░▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉▉▉▉
MonoSpriteLine %111011001010111011111111 ; ▉▉▉░▉▉░░▉░▉░▉▉▉░▉▉▉▉▉▉▉▉
MonoSpriteLine %111011101010001000111111 ; ▉▉▉░▉▉▉░▉░▉░░░▉░░░▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111000000100001000011100 ; ▉▉▉░░░░░░▉░░░░▉░░░░▉▉▉░░
MonoSpriteLine %111111110101111011101011 ; ▉▉▉▉▉▉▉▉░▉░▉▉▉▉░▉▉▉░▉░▉▉
MonoSpriteLine %111111101101111011101011 ; ▉▉▉▉▉▉▉░▉▉░▉▉▉▉░▉▉▉░▉░▉▉
MonoSpriteLine %111111011100011011101011 ; ▉▉▉▉▉▉░▉▉▉░░░▉▉░▉▉▉░▉░▉▉
MonoSpriteLine %111110111101111000011011 ; ▉▉▉▉▉░▉▉▉▉░▉▉▉▉░░░░▉▉░▉▉
MonoSpriteLine %111101111101111011011011 ; ▉▉▉▉░▉▉▉▉▉░▉▉▉▉░▉▉░▉▉░▉▉
MonoSpriteLine %111000000100001011101100 ; ▉▉▉░░░░░░▉░░░░▉░▉▉▉░▉▉░░
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111100011000011011111011 ; ▉▉▉▉░░░▉▉░░░░▉▉░▉▉▉▉▉░▉▉
MonoSpriteLine %111011101011101001110010 ; ▉▉▉░▉▉▉░▉░▉▉▉░▉░░▉▉▉░░▉░
MonoSpriteLine %111011111011101010101010 ; ▉▉▉░▉▉▉▉▉░▉▉▉░▉░▉░▉░▉░▉░
MonoSpriteLine %111011111000011011011010 ; ▉▉▉░▉▉▉▉▉░░░░▉▉░▉▉░▉▉░▉░
.byte $EF
freezer_reset_rb:
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %011111000010101110111111 ; ░▉▉▉▉▉░░░░▉░▉░▉▉▉░▉▉▉▉▉▉
MonoSpriteLine %101111011110101110111111 ; ▉░▉▉▉▉░▉▉▉▉░▉░▉▉▉░▉▉▉▉▉▉
MonoSpriteLine %101111011110101110111111 ; ▉░▉▉▉▉░▉▉▉▉░▉░▉▉▉░▉▉▉▉▉▉
MonoSpriteLine %101111000110101110111111 ; ▉░▉▉▉▉░░░▉▉░▉░▉▉▉░▉▉▉▉▉▉
MonoSpriteLine %101111011110101110111111 ; ▉░▉▉▉▉░▉▉▉▉░▉░▉▉▉░▉▉▉▉▉▉
MonoSpriteLine %101111011110101110111111 ; ▉░▉▉▉▉░▉▉▉▉░▉░▉▉▉░▉▉▉▉▉▉
MonoSpriteLine %011111001110100010001111 ; ░▉▉▉▉▉░░▉▉▉░▉░░░▉░░░▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000111110111111111111111 ; ░░░▉▉▉▉▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111100111111111111111 ; ▉▉▉▉▉▉▉░░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111010111111111111111 ; ▉▉▉▉▉▉░▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000110110111111111111111 ; ░░░▉▉░▉▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
.byte $E8
freezer_reset_lo:
MonoSpriteLine %111011111011101011111010 ; ▉▉▉░▉▉▉▉▉░▉▉▉░▉░▉▉▉▉▉░▉░
MonoSpriteLine %111011101011101011111010 ; ▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉▉▉▉░▉░
MonoSpriteLine %111100011000011011111011 ; ▉▉▉▉░░░▉▉░░░░▉▉░▉▉▉▉▉░▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
.byte $FF
freezer_reset_ro:
MonoSpriteLine %111010000011111111111111 ; ▉▉▉░▉░░░░░▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111011110111111111111111 ; ▉▉▉░▉▉▉▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000111110111111111111111 ; ░░░▉▉▉▉▉░▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
.byte $00
freezer_exit_lb:
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111000011011101011110111 ; ▉▉▉░░░░▉▉░▉▉▉░▉░▉▉▉▉░▉▉▉
MonoSpriteLine %111011101011101001110111 ; ▉▉▉░▉▉▉░▉░▉▉▉░▉░░▉▉▉░▉▉▉
MonoSpriteLine %111011101011101010110111 ; ▉▉▉░▉▉▉░▉░▉▉▉░▉░▉░▉▉░▉▉▉
MonoSpriteLine %111011101011101011010111 ; ▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉░▉░▉▉▉
MonoSpriteLine %111000011011101011100111 ; ▉▉▉░░░░▉▉░▉▉▉░▉░▉▉▉░░▉▉▉
MonoSpriteLine %111011011011101011110111 ; ▉▉▉░▉▉░▉▉░▉▉▉░▉░▉▉▉▉░▉▉▉
MonoSpriteLine %111011101100001011110111 ; ▉▉▉░▉▉▉░▉▉░░░░▉░▉▉▉▉░▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111011111011000110111101 ; ▉▉▉░▉▉▉▉▉░▉▉░░░▉▉░▉▉▉▉░▉
MonoSpriteLine %111001110010111010011101 ; ▉▉▉░░▉▉▉░░▉░▉▉▉░▉░░▉▉▉░▉
MonoSpriteLine %111010101010111010101101 ; ▉▉▉░▉░▉░▉░▉░▉▉▉░▉░▉░▉▉░▉
MonoSpriteLine %111011011010111010110101 ; ▉▉▉░▉▉░▉▉░▉░▉▉▉░▉░▉▉░▉░▉
MonoSpriteLine %111011111010111010111001 ; ▉▉▉░▉▉▉▉▉░▉░▉▉▉░▉░▉▉▉░░▉
MonoSpriteLine %111011111010111010111101 ; ▉▉▉░▉▉▉▉▉░▉░▉▉▉░▉░▉▉▉▉░▉
MonoSpriteLine %111011111011000110111101 ; ▉▉▉░▉▉▉▉▉░▉▉░░░▉▉░▉▉▉▉░▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111000011000011000010111 ; ▉▉▉░░░░▉▉░░░░▉▉░░░░▉░▉▉▉
MonoSpriteLine %111011101011110111110110 ; ▉▉▉░▉▉▉░▉░▉▉▉▉░▉▉▉▉▉░▉▉░
MonoSpriteLine %111011101011110111110101 ; ▉▉▉░▉▉▉░▉░▉▉▉▉░▉▉▉▉▉░▉░▉
MonoSpriteLine %111011101000111000110011 ; ▉▉▉░▉▉▉░▉░░░▉▉▉░░░▉▉░░▉▉
.byte $EE
freezer_exit_rb:
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %010000011000110000111111 ; ░▉░░░░░▉▉░░░▉▉░░░░▉▉▉▉▉▉
MonoSpriteLine %011101110111010111011111 ; ░▉▉▉░▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉
MonoSpriteLine %011101110111010111011111 ; ░▉▉▉░▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉
MonoSpriteLine %011101110111010111011111 ; ░▉▉▉░▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉
MonoSpriteLine %011101110111010000111111 ; ░▉▉▉░▉▉▉░▉▉▉░▉░░░░▉▉▉▉▉▉
MonoSpriteLine %011101110111010110111111 ; ░▉▉▉░▉▉▉░▉▉▉░▉░▉▉░▉▉▉▉▉▉
MonoSpriteLine %011101111000110111011111 ; ░▉▉▉░▉▉▉▉░░░▉▉░▉▉▉░▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %010000011000110000111111 ; ░▉░░░░░▉▉░░░▉▉░░░░▉▉▉▉▉▉
MonoSpriteLine %111101110111010111011111 ; ▉▉▉▉░▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉
MonoSpriteLine %111101110111010111011111 ; ▉▉▉▉░▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉
MonoSpriteLine %111101110111010111011111 ; ▉▉▉▉░▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉
.byte $F7
freezer_exit_lo:
MonoSpriteLine %111011101011111111010101 ; ▉▉▉░▉▉▉░▉░▉▉▉▉▉▉▉▉░▉░▉░▉
MonoSpriteLine %111011101011111111010110 ; ▉▉▉░▉▉▉░▉░▉▉▉▉▉▉▉▉░▉░▉▉░
MonoSpriteLine %111000011000010000110111 ; ▉▉▉░░░░▉▉░░░░▉░░░░▉▉░▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
.byte $FF
freezer_exit_ro:
MonoSpriteLine %111101110111010000111111 ; ▉▉▉▉░▉▉▉░▉▉▉░▉░░░░▉▉▉▉▉▉
MonoSpriteLine %111101110111010111111111 ; ▉▉▉▉░▉▉▉░▉▉▉░▉░▉▉▉▉▉▉▉▉▉
MonoSpriteLine %011101111000110111111111 ; ░▉▉▉░▉▉▉▉░░░▉▉░▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %111111111111111111111111 ; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
MonoSpriteLine %000000000000000000000000 ; ░░░░░░░░░░░░░░░░░░░░░░░░
.byte $00
freezer_action2:
lda $02
bmi :+
jmp freezer_action3
: jmp freezer_loop
.segment "view_graphics"
.byte 5, 6, 7, 8, 9, 10, 11, 12
.byte 13, 14, 15, 5, 16, 17, 18, 19
.byte 20, 5, 16, 17, 18, 21, 28, 5
.byte 16, 17, 18, 22, 28, 5, 16, 17
.byte 18, 23, 28, 24, 25, 26, 28, 28
; ▉▉░░░░▉▉▉░░░▉▉░░░░▉▉░░░░▉▉░░░░▉░░░░▉▉▉▉▉
; ▉▉░▉▉▉░▉░▉▉▉░▉░▉▉▉░▉░▉▉▉░▉░▉▉▉▉░▉▉▉░▉▉▉▉
; ▉▉░▉▉▉░▉░▉▉▉░▉░▉▉▉░▉░▉▉▉░▉░▉▉▉▉░▉▉▉░▉▉▉▉
; ▉▉░░░░▉▉░▉▉▉░▉░▉▉▉░▉░▉▉▉░▉░░░▉▉ ▉▉▉░▉▉▉▉
; ▉▉░▉▉▉░▉░▉▉▉░▉░░░░▉▉░▉▉▉░▉░▉▉▉▉░░░░▉▉▉▉▉
; ▉▉░▉▉▉░▉░▉▉▉░▉░▉▉░▉▉░▉▉▉░▉░▉▉▉▉░▉▉░▉▉▉▉▉
; ▉▉░░░░▉▉▉░░░▉▉░▉▉▉░▉░░░░▉▉░░░░▉░▉▉▉░▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
.byte %11000011, %11011101, %11011101, %11000011, %11011101, %11011101, %11000011, %11111111
.byte %10001100, %01110101, %01110101, %01110101, %01110100, %01110101, %10001101, %11111111
.byte %00110000, %11010111, %11010111, %11010111, %00110111, %10110111, %11010000, %11111111
.byte %11000010, %01011110, %01011110, %01000110, %01011110, %01011110, %11000010, %11111111
.byte %00011111, %11101111, %11101111, %11101111, %00011111, %11011111, %11101111, %11111111
; ▉▉░░░░▉▉░░░▉▉░░░░▉▉░░░░▉▉░░░▉▉░▉▉▉▉░▉░░░░▉▉▉▉▉▉▉
; ▉▉░▉▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉▉▉░▉▉▉░▉░░▉▉▉░▉░▉▉▉░▉▉▉▉▉▉
; ▉▉░▉▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉▉▉░▉▉▉▉▉░▉░▉▉░▉░▉▉▉░▉▉▉▉▉▉
; ▉▉░░░▉▉░▉▉▉░▉░▉▉▉░▉░░░▉▉░▉▉░░▉░▉▉░▉░▉░▉▉▉░▉▉▉▉▉▉
; ▉▉░▉▉▉▉░▉▉▉░▉░░░░▉▉░▉▉▉▉░▉▉▉░▉░▉▉▉░░▉░▉▉▉░▉▉▉▉▉▉
; ▉▉░▉▉▉▉░▉▉▉░▉░▉▉░▉▉░▉▉▉▉░▉▉▉░▉░▉▉▉▉░▉░▉▉▉░▉▉▉▉▉▉
; ▉▉░▉▉▉▉▉░░░▉▉░▉▉▉░▉░░░░▉▉░░░▉▉░▉▉▉▉░▉░░░░▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
.byte %11000011, %11011110, %11011110, %11000110, %11011110, %11011110, %11011111, %11111111
.byte %00011000, %11101011, %11101011, %11101011, %11101000, %11101011, %00011011, %11111111
.byte %01100001, %10101111, %10101111, %10100011, %01101111, %01101111, %10100001, %11111111
.byte %10001101, %01110100, %01111101, %01100101, %01110101, %01110101, %10001101, %11111111
.byte %11101000, %11101011, %01101011, %10101011, %11001011, %11101011, %11101000, %11111111
.byte %01111111, %10111111, %10111111, %10111111, %10111111, %10111111, %01111111, %11111111
; ▉░░░▉▉▉░░░▉▉░▉▉▉▉░░░▉▉░░░░▉▉▉░░░▉▉▉▉▉▉▉▉
; ░▉▉▉░▉░▉▉▉░▉░▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉▉▉
; ░▉▉▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉░▉░▉▉▉░▉░▉▉░░▉▉▉▉▉▉▉
; ░▉▉▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉░▉░▉▉▉░▉░▉░▉░▉▉▉▉▉▉▉
; ░▉▉▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉░▉░░░░▉▉░░▉▉░▉▉▉▉▉▉▉
; ░▉▉▉░▉░▉▉▉░▉░▉▉▉░▉▉▉░▉░▉▉░▉▉░▉▉▉░▉▉▉▉▉▉▉
; ▉░░░▉▉▉░░░▉▉░░░▉▉░░░▉▉░▉▉▉░▉▉░░░▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
.byte %10001110, %01110101, %01111101, %01111101, %01111101, %01110101, %10001110, %11111111
.byte %00110111, %11010111, %11010111, %11010111, %11010111, %11010111, %00110001, %11111111
.byte %10001100, %01110101, %01110101, %01110101, %01110100, %01110101, %10001101, %11111111
.byte %00111000, %11010111, %11010110, %11010101, %00110011, %10110111, %11011000, %11111111
.byte %11111111, %01111111, %01111111, %01111111, %01111111, %01111111, %11111111, %11111111
; ░░▉▉▉▉░▉
; ▉▉░▉▉░░▉
; ▉▉░▉▉▉░▉
; ▉▉░▉▉▉░▉
; ░░▉▉▉▉░▉
; ▉░▉▉▉▉░▉
; ▉▉░▉▉░░░
; ▉▉▉▉▉▉▉▉
.byte %00111101, %11011001, %11011101, %11011101, %00111101, %10111101, %11011000, %11111111
; ░░▉▉▉░░▉
; ▉▉░▉░▉▉░
; ▉▉░▉▉▉▉░
; ▉▉░▉▉▉░▉
; ░░▉▉▉░▉▉
; ▉░▉▉░▉▉▉
; ▉▉░▉░░░░
; ▉▉▉▉▉▉▉▉
.byte %00111001, %11010110, %11011110, %11011101, %00111011, %10110111, %11010000, %11111111
; ░░▉▉░░░░
; ▉▉░▉▉▉▉░
; ▉▉░▉▉▉▉░
; ▉▉░▉▉░░▉
; ░░▉▉▉▉▉░
; ▉░▉▉▉▉▉░
; ▉▉░▉░░░▉
; ▉▉▉▉▉▉▉▉
.byte %00110000, %11011110, %11011110, %11011001, %00111110, %10111110, %11010001, %11111111
; ▉▉░░░░▉░▉▉▉░▉░▉░░░░░▉▉▉▉
; ▉▉░▉▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉▉
; ▉▉░▉▉▉▉▉░▉░▉▉░▉▉▉░▉▉▉▉▉▉
; ▉▉░░░▉▉▉▉░▉▉▉░▉▉▉░▉▉▉▉▉▉
; ▉▉░▉▉▉▉▉░▉░▉▉░▉▉▉░▉▉▉▉▉▉
; ▉▉░▉▉▉▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉▉
; ▉▉░░░░▉░▉▉▉░▉░▉▉▉░▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉▉
.byte %11000010, %11011110, %11011111, %11000111, %11011111, %11011110, %11000010, %11111111
.byte %11101010, %11101011, %01011011, %10111011, %01011011, %11101011, %11101011, %11111111
.byte %00001111, %10111111, %10111111, %10111111, %10111111, %10111111, %10111111, %11111111
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
.byte %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
.byte %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
.byte %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
.byte %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ▉▉▉▉▉▉▉▉
; ░▉▉▉▉▉▉▉
.byte %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %11111111, %01111111
.segment "freezer_menu"
; $F900
freezer_exec_menu:
sei
ldx #$00 ; Initialize DDR to make sure we can read keyboard
stx $DC03 ; DDR B
dex
stx $DC02 ; DDR A
stx $05
lda #$80
sta $DC0E ; Initialize timer A
sta $DC0F ; Initialize timer B
lda #$7B ; Switch the VIC-II to illegal bitmap mode 1
sta $D011 ; VIC control register
lda $DD00
and #$FC ; Switch the VIC-II to bank 3
sta $DD00
; We want a raster interrupt on scanline 1
lda #$01
sta $D012
sta $D01A
sta $D019
lda #$FF
sta $02
jsr colram_topline_green
; Screen RAM at $F000, charset at $F000
lda #$CC
sta $D018 ; VIC memory control register
; Black background
lda #$00
sta $D021
; Delay loop
ldy #$00
: dey
bne :-
WF942:
jsr colram_topline_green
ldy $03 ; Currently selected pull-down menu
; Under normal circumstances we initiallize $03 (currently selected menu)
; with zero (backup menu), but in case we return from PRINT/VIEW $03
; already contains #$03 (print menu), so we leave it as it is.
cpy #$03 ; Print menu?
beq WF951
ldy #$00
sty $03
menu_changed:
ldy $03
WF951:
jsr show_selected_menu
lda #$00
sta $D418 ; Set volume to 0 to create a pop on the speakers
cli
freezer_loop:
lda #$FF
sta $DC00 ; Deselect all keyboard lines
ldx #$10
: lda $DC01 ; Read gamee port 2
cmp #$FF
bne :+ ; Joystick action? Then jump
dex
bne :-
lda $DC00 ; Data port A #1: keyboard, joystick, paddle, optical pencil
cmp #$FF
bne :+
jmp keyaction
: cmp $04 ; Joystick changed?
beq freezer_loop
jsr joyaction
bcc jmp_freezer_action ; Button pressed? Then jump
txa
beq :+
bpl leftright
jmp left
: tya
beq :+
bpl updown
jmp up
: jmp freezer_loop
keyaction:
lda #$FE ; Select keyboard column H
sta $DC00
: lda $DC01
cmp $DC01 ; Wait for keyboard change
bne :-
cmp $04 ; Changeed to previous value?
beq freezer_loop
sta $04
cmp #$F7 ; F7 pressed?
beq jmp_freezer_action
ldx #$BF ; Select keyboard column B
stx $DC00
ldx $DC01
cmp #$7F ; CRSR UP/DOWN presset?
beq updown
cmp #$FB ; CRSR LEFT/RIGHT presset?
beq leftright
jmp freezer_loop
jmp_left:
jmp left
jmp_freezer_action:
jmp freezer_action1
updown:
cpx #$EF ; Right shift prsseed?
beq jmp_up
jmp down
leftright:
cpx #$EF ; Left shift pressed?
beq jmp_left
jmp right
jmp_up:
jmp up
;F9D2
;
; In/out
; y = Current menu
; x = Current item in menu
;
joyaction_16k = joyaction & $BFFF
joychanged_16k = joychanged & $BFFF
joyaction:
lda $DC00 ; Data port A #1: keyboard, joystick, paddle, optical pencil
cmp $04 ; Jump Vector: real-integer conversion
bne joychanged
lda $DC01 ; Data port B #1: keyboard, joystick, paddle
cmp $04 ; Jump Vector: real-integer conversion
bne joychanged
ldx #$00
ldy #$00
sec
rts
joychanged:
sta $04
ldy #$00
ldx #$00
lsr ; C = UP (0=active)
bcs :+
dey
: lsr ; C = Down (0=active)
bcs :+
iny
: lsr ; C = Left (0=active)
bcs :+
dex
: lsr ; C = Right (0=active)
bcs :+
inx
: lsr ; C = Fire button (0=press)
rts
right:
ldy $03
lda #$FF
sta $02
lda #$0F
sta $D418 ; Select volume and filter mode
iny
sty $03
cpy #$06
bne jmp_menu_changed
WFA10:
ldx #$FF
stx $02
jmp WF942
down:
ldy $03
inc $02
WFA1B:
lda $02
ldx #$0F
stx $D418 ; Select volume and filter mode
cmp #$04
bcc WFA32
WFA26:
ldx #$FF
stx $02
jsr colram_topline_green
lda #$00
sta $D015 ; Sprites Abilitator
WFA32:
cpy #$02
bcc WFA3A
cmp #$03
bcs WFA26
WFA3A:
jsr colram_topline_green
jmp_menu_changed:
jmp menu_changed
up:
dec $02
bmi WFA3A
ldy $03
jmp WFA1B
WFA49:
lda $02
sta $05
inc $03
lda #$01
sta $02
jmp WF951
;
; User has selected an option in the freezer menu with fire button or F7.
;
; Looks like some code had to be patched into binary code that did
; already exist here.
freezer_action1:
jmp freezer_action2
nop
freezer_action3:
ldy $03 ; Currently open menu
cpy #$02
beq WFA49
lda menu_action_offset,y
; An overcomplicated way to compute A:=A+$02 :
tay
ldx $02
: iny
dex
bpl :-
tya
jmp freezer_complete_action
;$FA6E
left:
dec $03
beq WFA10
bmi WFA10
dec $03 ; Right will increase it again
jsr colram_topline_green
jmp right
show_selected_menu:
lda #$0F
sta $D418 ; Set volume to max to cause speaker pop
lda #$C8 ; Screen is 40 columns wide
sta $D016
sei
jsr _freezer_upd_sprptr_16k ; Sprite pointers are in RAM, 16K mode is needed
cli
lda #$00
sta $D01B ; Sprite-background screen priority
sta $D01D ; (2X) horizontal expansion (X) sprite 0..7
sta $D01C ; Set multicolor mode for sprite 0..7
sta $D017 ; (2X) vertical expansion (Y) sprite 0..7
ldy $03 ; Currently selected drop-down menu
cpy #$04
bcc :+
lda #$28 ; Reset menu has right sprites on xpos>255
cpy #$05
bcc :+
lda #$3C ; Exit menu has all sprites on xpos>255
: sta $D010 ; Position X MSB sprites 0..7
lda freezer_menus_xpositions,y
sta $D004 ; Position X sprite 2
sta $D008 ; Position X sprite 4
clc
adc #24 ; Sprite is 24 px wide, next one 24px to the right
sta $D006 ; Position X sprite 3
sta $D00A ; Position X sprite 5
lda #58 ; Y position of top sprites of menu
sta $D005 ; Position Y sprite 2
sta $D007 ; Position Y sprite 3
lda #79 ; Bottom sprites 21 px below top sprites
sta $D009 ; Position Y sprite 4
sta $D00B ; Position Y sprite 5
ldx $02
bpl :+
jsr highlight_selected_menu
: lda #$3C
sta $D015 ; Sprites Abilitator
rts
freezer_menus_xpositions:
.byte $18, $50, $80, $B8, $E8, $18
selected_item_rasterlines:
.byte $39, $41, $49, $51
menu_horz_pos:
.byte $01, $08, $0E, $15, $1B, $21, $27
unknown1:
.byte $01, $06, $0C, $12, $18
WFAEF:
.byte $1E, $24, $29
menu_action_offset:
.byte $00, $04, $08, $0B, $0E, $11
selected_item_wait_iters:
.byte $1E, $16, $16, $13
selected_item_endwait:
.byte $13, $12, $10, $10
freezer_irq_handler:
sei
pha
txa
pha
tya
pha
lda #$CC
sta $D018 ; VIC memory control register
lda #$1B ; text mode, 25 lines, yscroll=3
sta $D011 ; VIC control register
: lda $D012 ; Reading/Writing IRQ balance value
cmp #$39
bcc :-
cpx $01 ; Wait some cyles
ldx #$09
: dex
bne :-
ldx #$1C
stx $D018 ; VIC memory control register
ldx #$0A
: dex
bne :-
nop
lda #$7B ; invalid bitmap mode 1, 25 lines, yscroll=3
sta $D011 ; VIC control register
nop
nop
ldx $02 ; selected item
bmi WFB67
beq WFB44
: lda $D012 ; Reading/Writing IRQ balance value
cmp selected_item_rasterlines,x
bcc :-
ldy selected_item_wait_iters,x
: dey
bne :-
WFB44:
nop
lda #$01 ; white
sta $D029 ; Color sprite 2
sta $D02A ; Color sprite 3
sta $D02B ; Color sprite 4
sta $D02C ; Color sprite 5
lda selected_item_rasterlines,x
clc
adc #$07
WFB59:
cmp $D012 ; Reading/Writing IRQ balance value
bcc WFB61
jmp WFB59
WFB61:
ldy selected_item_endwait,x
: dey
bne :-
WFB67:
ldx #$0D ; light green
stx $D029 ; Color sprite 2
stx $D02A ; Color sprite 3
stx $D02B ; Color sprite 4
stx $D02C ; Color sprite 5
lda #$01 ; next raster irq at raster line 1
sta $D012 ; Reading/Writing IRQ balance value
: lda $D012 ; wait until raster line 96
cmp #$60
bcc :-
lda #$01
sta $D019 ; Interrupt indicator register
pla
tay
pla
tax
pla
rti
;
; Make set the first line of the colour RAM to light_green
;
; $FB8C
colram_topline_green_16k = colram_topline_green & $BFFF
colram_topline_green:
ldx #40-1
: lda #13 ; Light-green
sta $D800,x ; Color RAM
dex
bpl :-
inx
rts
; $FB98
highlight_selected_menu:
jsr colram_topline_green
ldy $03
clc
lda menu_horz_pos,y
tax
sbc menu_horz_pos+1,y
eor #$FF
tay
cpy #$07
bcc :+
dey
: lda #1 ; White
: sta $D7FF,x
inx
dey
bne :-
rts
;$FBB7
freezer_complete_action:
sei
pha
ldy #$A0
ldx #$00
: dex
bne :-
dey
bne :-
: lda $DC01 ; Data port B #1: keyboard, joystick, paddle
cmp $04
beq :-
: lda $DC00 ; Data port A #1: keyboard, joystick, paddle, optical pencil
cmp $04
beq :-
pla
cmp #$0D
bne :+
; Disable all sprites
lda #$00
sta $D015 ; Sprites Abilitator
jmp _show_view_menu
: ldx #$00
stx $D01A ; IRQ mask register
rts
;
; Draw the menu during raster interrupt
;
WFBE4:
; Screen RAM and charset at $F800
ldx #$EE
stx $D018 ; VIC memory control register
; Wait until raster line 58 (first visible line is 51)
: lda $D012
cmp #57
bcc :-
; Wait some cycles
nop
ldx #$09
: dex
bne :-
; Scroll down 1 line
lda #$1C
sta $D011 ; VIC control register
; Wait some cycles
ldx #$0A
: dex
bne :-
; Illegal bitmap mode 1, keep the scroll down
lda #$7C
sta $D011 ; VIC control register
rts
.segment "freezer_menu_16k"
; $BC40
freezer_update_spritepointers:
ldy $03
ldx freezer_spritepointers_base,y
stx $C7FA
inx
stx $C7FB
inx
stx $C7FC
inx
stx $C7FD
rts
freezer_spritepointers_base:
.byte $C5, $C9, $CD, $D1, $D5, $D9
; $BC5B
show_view_menu:
sei
lda $0314
pha
lda $0315
pha
lda #<view_irq_handler2
sta $0314 ; Vector: Hardware Interrupt (IRQ)
lda #>view_irq_handler2
sta $0315 ; Vector: Hardware Interrupt (IRQ)
lda viciireg_backup + $01 ; $D011 backup
pha
ora #$03 ; Reset screen scroll?
and #$7B
sta viciireg_backup + $01
ldx #4
: lda $AC,x
sta $D020,x ; Border color
dex
bpl :-
jsr colram_topline_green_16k
lda $05
bmi @1
cmp #$01
beq :+
eor #$02
: sta $03
lda #$FF
sta $05
jmp @2
@1: inc $05
ldy #$0D
sty $03
jsr ultimax_highlight_selected_menu
ldy #$06
sty $03
; Interrupt on raster line 2
@2: lda #$02
sta $D012 ; Reading/Writing IRQ balance value
lda #$3F
sta $02
jsr restore_sprites
; Enable raster interrupt
lda #$01
sta $D019
sta $D01A
: cli
jmp :- ; Infinite loop!
WBCBC:
sei
; Background black
lda #$00
sta $D021
; 25 line mode
lda #$C8
sta $D016
; Set VIC-II to bank 3
lda $DD00
and #$FC
sta $DD00
jsr ultimax_fbe4
;WBCD2
show_frozen_screen:
; Restore VIC-II bank
lda ciareg_backup + $10 ; $DD00 backup
sta $DD00
lda viciireg_backup + $08 ; $D018 backup
sta $D018 ; VIC memory control register
lda viciireg_backup + $11 ; $D021 backup
sta $D021 ; Background 0 color
lda viciireg_backup + $06 ; $D016 backup
sta $D016 ; VIC control register
nop
nop
inc viciireg_backup + $01 ; $D011 backup, scroll 1 line down
lda viciireg_backup + $01
sta $D011 ; VIC control register
dec viciireg_backup + $01 ; scroll back up
lda $02
cmp #$F0 ; VIC-II line 240?
bcc :+
; Show original sprites
lda viciireg_backup + $05 ; $D015 backup
sta $D015 ; Sprites Abilitator
: rts
;
; This raster interrupt runs in 16K mode and thus has to use
; the vector at $0314.
;
view_irq_handler2:
sei ; Unnecessary, interrupts are already
; disabled by the CPU.
lda $D012
cmp #$01 ; Raster line 1?
beq rline1 ; Then jump
WBD05:
lda $D011
ora #$60 ; Invalid bitmap mode 1 + screen disabled
sta $D011
lda #$00
sta $D015 ; Disable sprites
lda $05
bpl :+
jmp WBD98
: beq :+
dec $05
: lda #$FF ; Deselect the keyboard
sta $DC00
ldx #$20
: dex
lda $DC01 ; Read joystick 2
cmp #$FF
bne :+ ; No activity? Then jump.
dex
bne :- ; Next attempt to read joystick.
beq stickinactive ; No joystick
: jsr joychanged_16k
jmp WBD3F
WBD37:
lda #$FF ; Deselect the keyboard
sta $DC00
jsr joyaction_16k
WBD3F:
lda $05
bne WBD55
bcc WBD98 ; Firebutton pressed
txa ; Left/right status
beq WBD55 ; No change
bmi view_left ; Left
jmp view_right ; Right
rline1:
; Switch to normal text mode to display menu bar
lda #$1B
sta $D011
jmp WBE22
WBD55:
tya ; Up/down status
beq WFD5D ; No change
bmi view_up ; Up
jmp view_down ; Down
WFD5D:
jmp WBE0A
view_left:
dec $03 ; Decrease selected menu
bpl WFDB4
inc $03 ; Can't go left of leftmost menu
beq WFDB4
view_right:
cpx #$EF
beq view_left
lda $03
cmp #$06
bcs WFDEC
inc $03
bne WBDF0
stickinactive:
lda #$FE ; Select keyboard column H
sta $DC00
lda $DC01
ldx #$BF ; Select keyboard column B
stx $DC00
ldx $DC01
cmp #$7F ; CRSR UP/DN
beq view_down
ldy $05
bne WBD37
cmp #$FB ; CRSR L/R
beq view_right
cmp #$F7 ; F7
bne WBD37
sta $04
WBD98:
inc $05
ldx $03
beq WFDAF
cpx #$06
beq WFDBD
WFDA2:
cpx #$02
bne :+
lda $9D
and #$20
bne WFDB7
: dex
beq WFDC0
WFDAF:
inc $D020,x ; Border color
inc $AC,x
WFDB4:
jmp WBDF0
WFDB7:
lda $03
pha
jmp WBE65
WFDBD:
jmp exit_infinite_loop
WFDC0:
lda $03
pha
jmp WBE69
view_down:
cpx #$EF ; Right shift?
beq view_up
lda #$50
sta $04
inc $02 ; Increase current y position
lda $02
cmp #$F8 ; Don't go beyond line 248
bcs WFE1F
bne WBE0A
view_up:
; Disable all sprites:
lda #$00
sta $D015
dec $02 ; Decrease current y position
inc $04
lda $02
cmp #$3E ; Top reached? (line 62)
beq exit_infinite_loop ; Then exit
bcs WBE0A
jmp WBE0A
WFDEC:
lda #$00
sta $03
WBDF0:
lda #$0F
sta $D418 ; Select volume and filter mode
lda #$0B
sta $05
jsr colram_topline_green_16k
lda $03
pha
clc
adc #$07
sta $03
jsr ultimax_highlight_selected_menu
pla
sta $03
WBE0A:
lda #$01 ; Next raster interrupt on scanline 1
sta $D012 ; Reading/Writing IRQ balance value
WBE0F:
lda #$01
sta $D019 ; Interrupt indicator register
sta $D01A ; IRQ mask register
lda #$00
sta $D418 ; Select volume and filter mode
jmp $EA7E ; Pull registers from stack and RTI
WFE1F:
jmp WBF39
; BE22
WBE22:
; Disable all sprites
lda #$00
sta $D015
jsr WBCBC
lda $02
pha
and #$0F
cmp #$04
beq :+
cmp #$0C
beq :+
pla
sta $D012 ; Next raster interrupt at end of visible area
jmp WBE0F
: pla
: cmp $D012 ; Reading/Writing IRQ balance value
bne :-
nop
nop
jmp WBD05
;
; Exits the inifite loop at the end of show_view_menu
;
exit_infinite_loop:
ldy #$03
sty $03
tsx
inx
inx
inx
inx
inx
inx
txs
pla
sta viciireg_backup + $01
pla
sta $0315
pla
sta $0314
rts
vicii_bank_base:
.byte $c0,$80,$40,$00
WBE65:
lda #$FE
sta $03
WBE69:
lda $06
pha
lda viciireg_backup + $01
and #$20 ; Bitmap mode?
beq inc_colour_ram ; Jump if text mode
lda #$00
sta $04
lda $D018
and #$F0
lsr
lsr
sta $05
lda ciareg_backup + $10 ; $DD00 backup
and #$03 ; Get VIC-II bank
tax
lda vicii_bank_base,x
clc
adc $05
sta $05
ldy #$00
ldx #$04
@1: lda ($04),y
pha
sei ; Not necessary?
lda $03
cmp #$FE
bne :+
pla
pha
and #$F0
sta $06
pla
and #$0F
adc #$01
ora $06
jmp @2
: pla
pha
and #$0F
sta $06
pla
clc
and #$F0
adc #$10
ora $06
; Screen is 1000 bytes, $3E8, so stop when X=1 and Y=$E8
@2: cpx #$01
bne :+
cpy #$E8
beq exit_colour
: sta ($04),y
iny
bne @1
inc $05
dex
bne @1
jmp exit_colour
;
; Adjust the foreground colour by increasing all values in colour ram
;
inc_colour_ram:
ldx #$00
: inc $D800,x ; Color RAM
inc $D900,x ; Color RAM
inc $DA00,x ; Color RAM
inc $DB00,x ; Color RAM
dex
bne :-
ldx #$0F
: inc colram_backup,x
dex
bpl :-
exit_colour:
jsr colram_topline_green_16k
pla
sta $06
pla
sta $03
cli
jmp WBDF0
;$BEF2
restore_sprites:
sei
ldx #$07
: lda spritexy_backup,x
sta $D004,x
dex
bpl :-
lda viciireg_backup + $00
sta $D010 ; Position X MSB sprites 0..7
lda viciireg_backup + $07
sta $D017 ; (2X) vertical expansion (Y) sprite 0..7
ldx #$03
: lda viciireg_backup + $0A,x
sta $D01A,x
lda viciireg_backup + $19,x
sta $D029,x
dex
bpl :-
lda viciireg_backup + $15
sta $D025 ; Multicolor animation 0 register
lda viciireg_backup + $16
sta $D026 ; Multicolor animation 1 register
rts
;$BF21
;
; Dead code???
;
jsr show_frozen_screen
ldx #23
: lda $DBE8,x ; Color RAM
sta $D800,x ; Color RAM
dex
bpl :-
ldx #15
: lda colram_backup,x
sta $D818,x ; Color RAM
dex
bpl :-
WBF39:
lda #$F8
sta $02
jmp WBE0A
jmp $2000
.segment "freezer"
freezer_nmi_handler:
sei
pha
lda $00
pha
lda #$2F
sta $00 ; default value of processor port DDR
lda $01 ; save cpu port
ora #$20 ; cassette motor off - but don't store
pha
lda #$37 ; init cpu port
sta $01 ; 6510 I/O register
; Activate Ultimax mode and bank 3, NMI line stays active
lda #fcio_bank_3|fcio_c64_ultimaxmode
sta fcio_reg ; NMI = 1, GAME = 1, EXROM = 0
lda $DC0B ; Day time clock #1: Hour+[indicator AM/PM]
lda $DD0B ; Day time clock #2: Hour+[indicator AM/PM]
txa
pha
tya
pha
lda $02A1
pha
ldx #10
: lda $02,x
pha
dex
bpl :-
lda $DD0E ; Control register A of CIA #2
pha
lda $DD0F ; Control register B of CIA #2
pha
lda #$00
sta $DD0E ; Control register A of CIA #2
sta $DD0F ; Control register B of CIA #2
lda #$7C ; Stored into $DD0D
ldx #fcio_bank_3|fcio_c64_16kcrtmode ; Stored info $FFFF
jmp t_freezer_init
.segment "freezer_vectors"
.addr freezer_nmi_handler, freezer_nmi_handler, freezer_irq_handler
|
mist64/final_cartridge | 24,985 | bank3/freezer_entry.s | ;*****************************************************************************
; Final Cartridge III reconstructed source code
;
; The NMI interruprs handler that is executed in Ultimax mode, switches
; back to 16K mode and then calls freezer_init in this file. Here the actual
; freezing is done, then the routine to display the menu is called. The
; menu code is not inside this file.
;
; After the user has made a selction from the file menu, control is returned
; to this file and a jump is made to the routine that executes the command.
;*****************************************************************************
.setcpu "6502x"
.include "../core/kernal.i"
.include "../core/fc3ioreg.i"
.include "persistent.i"
.import _jmp_bank,_enable_fcbank0,_disable_fc3rom_set_01
.import freezer_set_c64and_fc3_rts
.import freezer_ultimax_exec_menu
.import autofire_lda_dc01,autofire_ldx_dc01,autofire_ldy_dc01
.import autofire_lda_dc00,autofire_ldx_dc00,autofire_ldy_dc00
.import __romio2l_RUN__
.importzp __FREEZERZP_START__,__FREEZERZP_SIZE__
.import __tape_backup_loader_LOAD__,__tape_backup_loader_SIZE__
.import __disk_backup_loader_LOAD__,__disk_backup_loader_SIZE__
.import __zp_load_mem_1_LOAD__,__zp_load_mem_1_SIZE__
.import __zp_load_mem_2_LOAD__,__zp_load_mem_2_SIZE__
.importzp __zp_load_mem_1_RUN__,__zp_load_mem_2_RUN__
.import __freezer_restore_1_LOAD__,__freezer_restore_1_SIZE__
.import __freezer_restore_2_RUN__,__freezer_restore_2_SIZE__
.import __memswap_LOAD__
.importzp __memswap_RUN__,__memswap_SIZE__
.import pset
.import freezer_goto_settings,freezer_zero_fill,write_mg87_and_reset
.import freezer_sprite_I,freezer_sprite_II,freezer_autofire,freezer_joyswap
.import freezer_backup_disk,freezer_backup_tape
.import freezer_goto_monitor
.segment "freezer_zeropage":zeropage
.global tmpptr_a,tmpvar1,spritexy_backup
.global freezer_mem_a,freezer_mem_a_val,freezer_mem_b,freezer_mem_b_val
.global spritexy_backup,viciireg_backup,colram_backup,ciareg_backup
ciareg_backup: .res 32
tmpvar1: .res 1
tmpptr_a: .res 2
tmpvar2: .res 1
spritexy_backup: .res 8 ; Backup sprite 2..5 x/y coord ($D004..$D00B)
viciireg_backup: .res 25 ; VIC-II registers from $D010
spritecol_backup: .res 4
spriteptr_backup: .res 4
colram_backup: .res 16 ; Back for last 16 bytes of 1st line of colour RAM
zp2345_backup: .res 4
freezer_mem_a: .res 2
freezer_mem_a_val: .res 1
freezer_mem_b: .res 2
freezer_mem_b_val: .res 1
.segment "freezer_entry_1"
.global freezer_init
freezer_init:
; Install loadram, routine at $0005
ldx #$06
: lda loadram,x
sta $05,x
dex
bpl :-
ldx $02A0
inx
cpx $02A2
bne :+
inx
: stx $02A1
ldx #<$E000
lda #>$E000
ldy #__FREEZERZP_SIZE__ ; Find some memory for zero page backup
jsr freezer_find_memory
lda $02
clc
adc #__FREEZERZP_SIZE__
tax
lda $03
adc #$00
ldy #<__freezer_restore_1_SIZE__
jsr freezer_find_memory
;
; THis is a bit of a weird method... location of first memory region
; was not save, so the same block of memory again.
;
ldx #<$E000
lda #>$E000
ldy #__FREEZERZP_SIZE__
jsr freezer_find_memory
ldy #$00
; Backup the zeropage area that the freezer will use into the found memory
: lda __FREEZERZP_START__,y ; Lo Byte #1 (rounding)
sta ($02),y
iny
cpy #<__FREEZERZP_SIZE__
bne :-
lda $02 ; Low byte of found memory
sta freezer_mem_a ; keep it for later
lda $03 ; High byte of found memory
sta freezer_mem_a+1 ; keep it for later
lda $04 ; value of the found memory
sta freezer_mem_a_val ; keep it for later
; Save the NMI vector on the stack
lda $0318 ; Vector: Not maskerable Interrupt (NMI)
pha
lda $0319 ; Vector: Not maskerable Interrupt (NMI)
pha
lda #<temp_nmi_handler
sta $0318 ; Vector: Not maskerable Interrupt (NMI)
lda #>temp_nmi_handler
sta $0319 ; Vector: Not maskerable Interrupt (NMI)
; Backup the contents of the CIA registers and initalize them with correct
; values for the freezer.
ldx #$1F
@nextreg:
lda $DCF0,x ; Backup the cia registers
sta ciareg_backup,x
txa
and #$0F
cmp #$02 ; Is it a port DATA register?
bcc @dec_loop ; Yes, then no backup
cmp #$04 ; Not port data nor ddr register?
bcs @1 ; Then jump to further register tests
lda #$FF ; Initialize DDRs with $ff
sta $DCF0,x
bne @dec_loop
@1:
cmp #$0E ; Is it a timer control register?
bcc @2 ; Then jump to further register tests
lda #$10 ; Initialize control register with $10
sta $DCF0,x
@2:
cmp #$08 ; Is it a timer value ?
bcs @dec_loop ; No, then go on
cmp #$04 ; Is it a timer value ?
bcc @dec_loop ; No, then go on
and #$01 ; Init both timers with $0001
eor #$01
sta $DCF0,x
@dec_loop:
dex
bpl @nextreg
; Clear interrupt flags of both CIAs by reading from their ICR
ldx #$00
lda $DCFD,x
ldx #$10
lda $DCFD,x
; The interrupt mask inside the ICR of the CIA cannot be read, because reading the
; register has a different meaning. Both CIA's won't be restored on return, but cleared
lda #0
sta ciareg_backup + $0d
sta ciareg_backup + $1d
; Handle CIA timers...
ldx #$01 ; Start with timer B
@nexttimer:
; Start the timer in one shot mode on both CIAs
lda #$19
sta $DC0E,x ; Control register A of CIA #1
sta $DD0E,x ; Control register A of CIA #2
txa
pha ; Push timer number
asl ; Timer number *2
bne @3 ; Jump if timer A
lda #$01
@3:
sta tmpvar2 ; 1 for timer A, 2 for timer B
ldx #0
.byte $2c ; bit $xxxx, skip next instruction
@nextcia_1:
ldx #$10
@4: lda $DCFD,x ; load ICR
tay
and tmpvar2 ; Wait for timer underflow
beq @4
tya
bpl @5 ; Interrupt occured? No, then @5
ora $7D,x ; OR ISR into $7D/8D
sta $7D,x
@5: dex
bmi @nextcia_1
pla ; Restore cia number
tax
dex
bpl @nexttimer
; Delay loop
ldy #0
@6: inx
bne @6
iny
bne @6
; X=0
.byte $2c ; bit $xxxx, skip next instruction
@nextcia_2:
ldx #$10
lda #$7F ; Disable all interrupt sources
sta $DCFD,x
ldy ciareg_backup + $D,x ; Did an interrupt occur
bmi @7 ; Then skip
lda #$7F
sta ciareg_backup + $D,x
@7: dex
bmi @nextcia_2
; Restore the NMI vector
pla
sta $0319
pla
sta $0318 ; Vector: Not maskerable Interrupt (NMI)
; Value of $dd0e/$dd0f was pushed on stack by NMI handler and set to 0
; before the CIA registers could be backed up, so correct this:
pla
sta ciareg_backup + $1f
pla
sta ciareg_backup + $1e
lda $04 ; Value in found memory area
pha ; Save for later
lda $02 ; Lo byte of found memory area
pha ; Save for later
clc
adc #$67
tax
lda $03 ; Lo byte of found memory area
pha ; Save for later
adc #$00
; A/X now points to end of found memory area
ldy #<__freezer_restore_1_SIZE__
jsr freezer_find_memory ; Find another memory area of $5c bytes
lda $02
sta freezer_mem_b ; Store high byte of area
lda $03 ;
sta freezer_mem_b+1 ; Store low byte of area
lda $04 ; Value found in memory area
sta freezer_mem_b_val ; Save for later
; Install the freezer restore routine in the second memory area found and
; do live patching.
ldy #<__freezer_restore_1_SIZE__ - 1
: lda freezer_restore_mem_cia_vic,y
sta ($02),y
dey
bpl :-
; Do some live patching of the freezer restore routine
pla
ldy #<(r1 + 2 -__freezer_restore_1_LOAD__)
sta ($02),y
ldy #<(r2 + 2 -__freezer_restore_1_LOAD__)
sta ($02),y
pla
dey
sta ($02),y
ldy #<(r1 + 1 -__freezer_restore_1_LOAD__)
sta ($02),y
pla
ldy #<(r3 + 1 -__freezer_restore_1_LOAD__)
sta ($02),y
pla
sta tmpptr_a
pla
sta tmpptr_a+1
lda $04
tay
ldx #$FF
: inx
pla
sta $04,x
cpx #8
bne :-
; C=1 because X=8
tya
tax
pla
ldy #<(r4 + 1 -__freezer_restore_1_LOAD__)
sta ($02),y
pla
ldy #<(r5 + 1 -__freezer_restore_1_LOAD__)
sta ($02),y
txa
ldy #<(r6 + 1 -__freezer_restore_1_LOAD__)
sta ($02),y
; The freezer restore routine will RTS to the
; current stack pointer - #$12
; C is still 1
tsx
lda #$01
pha
txa
sbc #$12
pha
; Patch loading the original value of the stack pointer
tsx
txa
ldy #<(r7 + 1 -__freezer_restore_1_LOAD__)
sta ($02),y
; Push a small routine on the stack that will overwrite
; the restore routine with the original value.
ldx #<sizeof_freezer_restore_fill_area - 1
: lda freezer_restore_fill_area,x
pha
dex
bpl :-
; push the location of the restore routine
lda $03
pha
lda $02
pha
lda #$9D ; Opcode for sta absolute,x
pha
lda $D01A ; IRQ mask register
ldy #<(r8 + 1 -__freezer_restore_1_LOAD__)
sta ($02),y
lda $D015 ; Sprites Abilitator
ldy #<(r9 + 1 -__freezer_restore_1_LOAD__)
sta ($02),y
; Disable VIC-II interrupts and ack pending ones
ldx #$00
stx $D01A ; IRQ mask register
dex
ldy #$FF
sty $D019 ; Interrupt indicator register
; The line where to generate a raster interrupt cannot be read because
; $D012/$D011 return the current raster line. Therefore we wait until a
; raster interrupt *condition* occurs to obtain the this value.
@8: lda $D011 ; VIC control register
bpl @10
inx
cpx #$04
beq @12
@9: lda $D019 ; Interrupt indicator register
and #$01
bne @11
bit $D011 ; VIC control register
bmi @9
@10: lda $D019 ; Interrupt indicator register
and #$01
beq @8
@11: lda $D011 ; VIC control register
ldy $D012
@12: pha
tya
pha
ldy #<(r11 + 1 -__freezer_restore_1_LOAD__)
pla
sta ($02),y
ldy #<(r10 + 1 -__freezer_restore_1_LOAD__)
pla
sta ($02),y
ldy #<(r12 + 1 -__freezer_restore_1_LOAD__)
lda ciareg_backup + $0e
ora #$10
sta ($02),y
ldy #<(r13 + 1 -__freezer_restore_1_LOAD__)
lda ciareg_backup + $0f
ora #$10
sta ($02),y
ldy #<(r14 + 1 -__freezer_restore_1_LOAD__)
lda ciareg_backup + $1e
ora #$10
sta ($02),y
ldy #<(r15 + 1 -__freezer_restore_1_LOAD__)
lda ciareg_backup + $1f
ora #$10
sta ($02),y
; No idea... restore code has been patched with the backed up values
; ciareg_backup + $0e/$0f/$1e/$1f can in principle be reused for other
; purposes, but I cannot find any code that does this, so why clear
; them then?
ldx #$01
lda #$00
: sta ciareg_backup + $0e,x
sta ciareg_backup + $1e,x
dex
bpl :-
sec
lda $02
sbc #$01
tay
lda $03
sbc #$00
pha
tya
pha
tsx
stx tmpvar2
lda tmpptr_a
sta $02
lda tmpptr_a+1
sta $03
ldx #.sizeof(spritexy_backup) - 1
: lda $D004,x ; Position X sprite 2
sta spritexy_backup,x
dex
bpl :-
ldx #.sizeof(viciireg_backup) - 1
: lda $D010,x
sta viciireg_backup,x
dex
bpl :-
ldx #.sizeof(spritecol_backup) - 1
: lda $D029,x ; Color sprite 2
sta spritecol_backup,x
dex
bpl :-
ldx #.sizeof(spriteptr_backup) - 1
: lda $C7FA,x
sta spriteptr_backup,x ; Current secondary address
dex
bpl :-
ldx #$17
; Backup the first 24 bytes of colour RAM to unused colour RAM
: lda $D800,x ; Color RAM
sta $DBE8,x ; Color RAM
dex
bpl :-
; Backup the last 16 bytes of colour RAM to zeropage RAM
ldx #.sizeof(colram_backup) - 1
: lda $D818,x ; Color RAM
sta colram_backup,x
dex
bpl :-
ldx #.sizeof(zp2345_backup) - 1
: lda $02,x
sta zp2345_backup,x
dex
bpl :-
;
; Show the Freezer menu and let the user make a selection
;
jsr freezer_ultimax_exec_menu
tay
sei
lda #$0F
sta $D418 ; Select volume and filter mode
ldx #.sizeof(zp2345_backup) - 1
: lda zp2345_backup,x
sta $02,x
dex
bpl :-
ldx #.sizeof(spritexy_backup) - 1
: lda spritexy_backup,x
sta $D004,x ; Position X sprite 2
dex
bpl :-
ldx #.sizeof(viciireg_backup) - 1
: lda viciireg_backup,x
sta $D010,x
dex
bpl :-
ldx #.sizeof(spritecol_backup) - 1
: lda spritecol_backup,x
sta $D029,x ; Color sprite 2
dex
bpl :-
ldx #.sizeof(spriteptr_backup) - 1
: lda spriteptr_backup,x
sta $C7FA,x
dex
bpl :-
ldx #$17
: lda $DBE8,x ; Color RAM
sta $D800,x ; Color RAM
dex
bpl :-
ldx #.sizeof(colram_backup) - 1
: lda colram_backup,x
sta $D818,x
dex
bpl :-
tsx
stx tmpvar2
tya
tax
; This is a routine that is executed after a backup has been loaded and this routine
; will finalize the loading. Since temp variables at $A6 are no longer needed, this
; routine can now be installed.
ldy #freezer_restore_0300_size-1
: lda freezer_restore_0300,y
sta $00A6,y
dey
bpl :-
ldy #$00
sty $02A1
sty $D01A ; IRQ mask register
sty spritexy_backup ; ???
sty $A3
sty $DD03 ; Data direction register port A #2
lda #$7F
sta $D019 ; Interrupt indicator register
lda #$3F
sta $DD02 ; Data direction register port A #2
lda $80 ; CHRGET (Introduce a char) subroutine
and #$07
ora #$10
sta $DD00 ; Data port A #2: serial bus, RS-232, VIC memory
dex
beq freezer_backup_disk_near
dex
beq freezer_jmp_backup_tape
dex
beq freezer_backup_disk_near
dex
beq freezer_jmp_backup_tape
dex
beq freezer_jmp_sprite_I
dex
beq freezer_jmp_sprite_II
dex
beq freezer_jmp_joyswap
dex
beq freezer_jmp_autofire
dex ; color menu handled inside menu; no further action
dex ; color menu handled inside menu; no further action
dex ; color menu handled inside menu; no further action
dex
beq freezer_settings
dex
dex
beq freezer_pset
dex
beq freezer_final_kill
dex
beq freezer_jmp_zero_fill
dex
beq freezer_cbm64
dex
beq freezer_run
dex
beq freezer_monitor
dex
beq freezer_goto_desktop
bne freezer_run
freezer_monitor:
jmp freezer_goto_monitor
freezer_goto_desktop:
jmp write_mg87_and_reset
freezer_jmp_zero_fill:
jmp freezer_zero_fill
freezer_cbm64:
lda #>(START-1)
pha
lda #<(START-1)
pha
jmp _enable_fcbank0
freezer_final_kill:
; Jump to RESET vector in KERNAL
lda #>(START-1)
pha
lda #<(START-1)
pha
; ROM bank 0, C64 in normal mode, NMI line released and disable FC3 hardware:
lda #fcio_bank_0|fcio_c64_crtrom_off|fcio_nmi_line|fcio_kill
jmp _jmp_bank
freezer_pset:
jsr call_pset_in_bank0
jmp freezer_run
call_pset_in_bank0:
lda #>pset
pha
lda #<pset
pha
jmp _enable_fcbank0
freezer_jmp_joyswap:
jmp freezer_joyswap
freezer_settings:
jmp freezer_goto_settings
freezer_jmp_backup_tape:
jmp freezer_backup_tape
freezer_jmp_autofire:
jmp freezer_autofire
freezer_jmp_sprite_I:
jmp freezer_sprite_I
freezer_run:
ldy #$35
jmp $DE0D
freezer_jmp_sprite_II:
jmp freezer_sprite_II
freezer_backup_disk_near:
.segment "freezer_restore_0"
;
; This routine is stored into the zero page at $00a6
; If a backup is loaded, the loader jumps to this routine in the (restored) zero page
;
.proc freezer_restore_0300
: jsr IECIN
sta $0300,y
iny
bne :-
lda #$08
jsr LISTEN
lda #$E0
jsr SECOND
jsr UNLSTN
dec $01
rts
.endproc
freezer_restore_0300_size = .sizeof(freezer_restore_0300)
.assert freezer_backup_disk = freezer_backup_disk_near, error, "backup_disk must follow freezer_entry_1"
.segment "freezer_restore_1"
;
; This routine is copied to ram at second memory area found by freezer
; It is live patched.
;
freezer_restore_mem_cia_vic:
r4: lda #$FF
sta $02A1
sei
; Restore the CIA registers
ldx #$20
: lda ciareg_backup-1,x
sta $DCEF,x
dex
bne :-
r1: lda $0100,x ; live patched by freezer entry code
sta $70,x ; Lo Byte #1 (rounding)
r3: lda #$04
r2: sta $0100,x ; live patched by freezer entry code
inx
cpx #__FREEZERZP_SIZE__
bne r1
r9: lda #$FF
sta $D015 ; Sprites Abilitator
r10: lda #$FF
sta $D011 ; Screen control register
r11: lda #$FF
sta $D012 ; Raster interrupt line
r8: lda #$FF
sta $D01A ; IRQ mask register
r12: lda #$FF
sta $DC0E ; Control register A of CIA #1
r13: lda #$FF
sta $DC0F ; Control register B of CIA #1
r14: lda #$FF
sta $DD0E ; Control register A of CIA #2
r15: lda #$FF
sta $DD0F ; Control register B of CIA #2
ldx #$8F
lda $DC0D ; Interrupt control register CIA #1
lda $DD0D ; Interrupt control register CIA #2
stx $D019 ; Interrupt indicator register
r5: ldy #$FF
r7: ldx #$FF
txs
ldx #<__freezer_restore_1_SIZE__ - 1
r6: lda #$FF ; Value to overwrite restore routine with
rts ; Jump to restore routine phase 2 (located on stack)
.segment "freezer_restore_2"
;
; This routine is copied to the stack by freezer
; It is live patched.
;
freezer_restore_l1:
sta $0100,x ; Live patched by address of memory area
freezer_restore_fill_area:
dex
bpl freezer_restore_l1
pla
tax
pla
sta $01
pla
sta $00
pla
rti
sizeof_freezer_restore_fill_area = __freezer_restore_2_SIZE__ - (freezer_restore_fill_area - __freezer_restore_2_RUN__)
.segment "freezer_entry_2"
;
; freezer_find_memory -- Find y consecutive bytes in memory with the same value
;
; This routine is used to find memory that the freezer can use. It searches ram
; for y consecutive bytes with the same value, so these bytes can be easily
; run-length encoded.
;
; In:
; - A - High byte of start address
; - X - Low byte of start address
; - Y - Number of bytes to find
;
; Out:
; - $02/$03 - Pointer to memory area
restart_at_0201:
lda #$02
ldx #$01
.byte $2c ; 3 byte nop
freezer_find_memory:
sty $0c ; store number of bytes
stx $02 ; store lo byte of addr
sta $03 ; store hi byte of addr
lda #$33 ; BASIC CHARROM KERNAL
sta $01
jsr $0005 ; load a byte from RAM at ($02),y
sta $04 ; save the byte
ldy #$00 ; begin at the start of tye pointer
@nextbyte:
iny
cpy $0C ; end reached?
beq @exit ; yes
jsr $0005 ; load a byte from RAM at ($02),y
cmp $04 ; same as last byte?
beq @nextbyte ; yes, tnen loop
sta $04 ; it's not equal, save the byte
tya
clc
adc $02 ; Add index where unequal to the pointer
sta $02
bcc @no_overflow
inc $03 ; carry to high byte
lda $03 ; end of memory reached?
beq restart_at_0201 ; then restart at $0201
cmp #$D0 ; I/O area reached?
beq @io_area_reached
@no_overflow:
ldy #$00
beq @nextbyte
@io_area_reached:
; This code is mysterious, because by storing $33 into $01, the code above
; made I/O invisible and thus reading $d018 makes no sense. It looks like
; the code checks wether screen ram is <$d000 or >=$e000. If yes, the screen
; ram is used as freezer memory. If no, the stack is used as a last resort.
;
; The first $C3 bytes of the screen buffer or stack is cleared, which is
; mysterious as well, since if consecutive bytes are found, nothing is
; cleared
;
lda $D018 ; VIC memory control register
and #$F0
lsr
lsr
sta $03 ; Jump Vector: real-integer conversion
lda $DD00 ; Data port A #2: serial bus, RS-232, VIC memory
and #$03
eor #$03
lsr
ror
ror
ora $03 ; Jump Vector: real-integer conversion
cmp #$D0
bcc @screen_ok
cmp #$E0
bcs @screen_ok
lda #$01 ; Use stack as last resort
@screen_ok:
sta $03
ldy #0
sty $02 ; Low byte to zero
tya
: sta ($02),y ; Clear the byte
iny
cpy #$C3 ; End reached?
bne :-
@exit:
lda #$37 ; Normal memory config
sta $01
rts
.segment "freezer_entry_3"
loadram:
; $01 contains $33 i.e. BASIC CHARROM KERNAL visble
inc $01 ; $01 contains $34, 100% RAM
lda ($02),y
dec $01 ; re-enable ROM
rts
temp_nmi_handler:
rti
|
mist64/final_cartridge | 33,539 | bank3/screenshot.s | ;*****************************************************************************
;
; This code has to do with creating screenshots. The code in the segment
; "screenshotcode" is copied to $5000 when a screenshot is printed.
;
; The code in segment "printersettings" prepares the screen shot and then
; jumps to the printer settings window that is located in bank 2.
;
;*****************************************************************************
.setcpu "6502x"
.include "../core/kernal.i"
.include "../core/fc3ioreg.i"
.include "persistent.i"
.import __screenshotcode_RUN__, __screenshotcode_LOAD__,__screenshotcode_SIZE__
.import __copycode_LOAD__,__copycode_RUN__,__copycode_SIZE__
.import __ramload_LOAD__,__ramload_RUN__,__ramload_SIZE__
print_graphmode_val := $30
print_horizontal_size := $31
print_vertical_size := $32
print_sideways_flag := $35
print_color_flag := $36
print_8p24p_flag := $37
; $00 Epson
; $40 NEC P
; $80 CBM
printer_type_flags := $3C
; $00 = Commodore
; $01 = Centronics
; $02 = RS-323
printer_interface := $0200
; $00 = CBM Compatible
; $01 = EPSON Compatible
; $02 = NEC P Series
printer_type := $0201
; $00 = yes
; $01 = no
print_colors := $0202
; $00 = no
; $01 = yes
print_sideways := $0203
; horizontal size - 1
print_horz_size := $0204
; vertical size - 1
print_vert_size := $0205
; $00 = 8P Single Density
; $01 = 8P Double Density
; $02 = 8P High Speed, DD
; $03 = 8P Quadruple Density
; $04 = 8P CRT Graphics
; $05 = 8P CRT Graphics II
; $06 = 24P Single Density
; $07 = 24P Double Density
; $08 = 24P CRT Graphics II
; $09 = Triple Density
print_graphmode := $0206
; $00 = no
; $01 = yes
print_invert := $0207
.segment "screenshotcode"
; $9500
sei
lda #<$EA31
sta $0314 ; Vector: Hardware Interrupt (IRQ)
lda #>$EA31
sta $0315 ; Vector: Hardware Interrupt (IRQ)
ldx #$00
stx $D01A ; IRQ mask register
;
; Backup zero page to $7000
;
ldx #$02
: lda $00,x
sta $7000,x
inx
bne :-
; Hide the FC3
lda #fcio_nmi_line | fcio_c64_crtrom_off | fcio_bank_0
sta fcio_reg
lda $0B21 ; $D021 backup
and #$0F
sta $0B21
lda $0B16 ; $D016 backup
and #$10 ; Isolate multi-colour bit
asl
asl
asl
sta $50 ; Multi-colour flag $00=off $80=on
lda $0B11 ; $D011 backup
and #$20 ; Isolate
asl
asl
sta $26 ; Bitmap modee flag $00=off $80=on
;
; Swap memory from $0C00..$1BFF with $C000..$CFFF
;
ldy #$00
sty $AC
sty $AE
lda #$0C
sta $AD
lda #$C0
sta $AF
ldx #$10
: lda ($AC),y
pha
lda ($AE),y
sta ($AC),y
pla
sta ($AE),y
iny
bne :-
inc $AD
inc $AF
dex
bne :-
; Settings from settings screen
ldx printer_type
beq @1
dex
beq @2
lda #$40 ; NEC P series printer
.byte $2c ; BIT $xxxx, skip next instruction
@1: lda #$80 ; Commodore MPS printer
.byte $2c ; BIT $xxxx, skip next instruction
@2: lda #$00 ; EPSON printer
sta printer_type_flags
lda #$00
ldx print_colors
bne :+
lda #$80
: sta print_color_flag
lda #$00
ldx print_sideways
beq :+
lda #$80
: sta print_sideways_flag
ldx print_horz_size
inx
stx print_horizontal_size
ldx print_vert_size
inx
stx print_vertical_size
lda #$00
ldx print_graphmode
cpx #$06
bcc :+
lda #$80
: sta print_8p24p_flag ; 8P/24P flag
lda printer_graphmodes,x
sta print_graphmode_val
lda print_invert
beq :+
lda #$FF
: sta $25
ldx #$08
bit printer_type_flags
bpl @4
dex
lda #$E0
ldy #$01
bit print_color_flag
bpl :+
lda #$80
ldy #$02
: sta $40
sty $41
lda #$FF
sta $46
@4: stx $3D
lda print_horizontal_size
bit print_sideways_flag
bpl :+
lda print_vertical_size
: sta $29
bit print_color_flag
bmi :+
jsr routine1
: bit print_sideways_flag ; Sideways printing?
bmi @3 ; Then jump
jsr routine2
jsr routine3
jsr routine4
jsr routine5
@map_in_bank_2:
;
; Printing has finished, now return to the settings screen
;
; Map in FC3 bank 2
lda #fcio_nmi_line | fcio_bank_2
sei
sta fcio_reg
lda #<$DE21
sta $0314
lda #>$DE21
sta $0315
;
; Swap memory from $0C00..$1BFF with $C000..$CFFF
;
ldy #$00
sty $AC
sty $AE
lda #$0C
sta $AD
lda #$C0
sta $AF
ldx #$10
: lda ($AC),y
pha
lda ($AE),y
sta ($AC),y
pla
sta ($AE),y
iny
bne :-
inc $AD
inc $AF
dex
bne :-
;
; Copy to $7000 back to zero page
;
ldx #$02
: lda $7000,x
sta $00,x
inx
bne :-
inx
stx $D01A ; IRQ mask register
cli
rts
@3: jsr routine4
jsr routine3
jsr routine2
jsr routine6
jmp @map_in_bank_2
routine2:
ldx print_vertical_size
lda #$C8
sta $33
lda #$00
sta $34
@1: dex
beq _rts
lda $33
clc
adc #$C8
sta $33
lda $34
adc #$00
sta $34
jmp @1
routine4:
ldx print_horizontal_size
lda #$40
sta $33
lda #$01
sta $34
@1: dex
beq _rts
lda $33
clc
adc #$40
sta $33
lda $34
adc #$01
sta $34
jmp @1
_rts: rts
routine3:
ldx #$00
stx $43
stx $44
ldx $33
ldy $34
: sec
stx $45
txa
sbc #$07
tax
tya
sbc #$00
tay
bcc :+
inc $43
bne :-
inc $44
bne :-
: lda #$00
ldx $45
beq @1
: sec
rol
dex
bne :-
@1: sta $45
rts
routine21:
lda $43
bne :+
dec $44
bpl :+
rts
: dec $43
lda $43
ora $44
bne :+
lda $45
sta $46
: lda #$00
rts
print_digit_at_17:
ldy #$11
.byte $2c
print_digit_at_18:
ldy #$12
eor #$30
pha
clc
jsr PLOT
pla
jmp BSOUT
routine1:
; Clear $6000..$6AFF
lda #$00
tay
sta $48
ldx #>$6000
stx $49
ldx #$0B
: sta ($48),y
iny
bne :-
inc $49
dex
bne :-
ldx print_vertical_size
: clc
adc print_horizontal_size
dex
bne :-
stx $52
ldx #$04
pha
: asl
rol $52
dex
bne :-
sta $51
pla
asl
sta $47
ldx #$00
stx $3B
ldx #$04
: asl
rol $3B
dex
bne :-
clc
adc #$00
sta $3A
lda $3B
adc #$60
sta $3B
ldx #$0F
@2: lda tabel4,x
tay
beq @3
lda #$00
sta $48
sta $49
@1: clc
adc $47
sta $48
bcc :+
inc $49
: dey
bne @1
ldy #$04
: lsr $49
ror
dey
bne :-
@3: sta end_of_text,x
dex
bpl @2
ldy #$0F
@5: lda end_of_text,y
beq @4
jsr routine7
: lda #$01
sta ($48),y
jsr add_10_to_48w
dex
beq @4
lda #$01
sta ($53),y
jsr routine9
dex
bne :-
@4: dey
bpl @5
lda print_horizontal_size
asl
asl
asl
asl
ldx #$10
bit print_sideways_flag
bpl :+
tax
lda #$10
: sta $27
stx $28
rts
routine7:
sta $11
lda #$00
sta $48
clc
adc $51
sta $53
lda #$60
sta $49
adc $52
sta $54
sec
lda $3A
sbc $53
sta $53
lda $3B
sbc $54
lsr
sta $54
ror $53
lda $53
and #$F0
clc
adc #$00
sta $53
lda #$60
adc $54
sta $54
clc
lda $53
adc $51
sta $53
lda $54
adc $52
sta $54
ldx #$00
stx $39
lda $47
dex
: sec
inx
sta $10
sbc $11
bcs :-
lda $10
beq :+
inx
: txa
ldx #4
: asl
rol $39
dex
bne :-
sta $38
lda $39
ldx $11
rts
add_10_to_48w:
clc
lda $48
adc #$10
sta $48
lda $49
adc #$00
sta $49
rts
routine9:
clc
lda $53
adc #$10
sta $53
lda $54
adc #$00
sta $54
lda $53
cmp $3A
lda $54
sbc $3B
bcc :+
lda #$00
clc
adc $51
sta $53
lda #$60
adc $52
sta $54
: rts
zero_48w:
ldy #$00
sty $48
sty $49
rts
routine38:
inc $48
bne :+
inc $49
: lda $48
cmp #$80
lda $49
sbc #$02
rts
W981C:
jsr c3w_to_c1w
jsr zero_48w
LL3: jsr zero_3ew
: jsr routine13
jsr routine14
bcc @1
jsr routine15
jsr routine17
bne :-
jsr routine38
bcs W534E
@1: jsr routine37
bne LL3
jsr routine23
lda $DC01 ; Data port B #1: keyboard, joystick, paddle
cmp #$7F
beq W534E
jsr routine24
bne LL3
W534E:
jsr close_all
lda #$01
ldy #$0A
jsr routine22
lda #$0D
jsr BSOUT
jmp close_all
routine5:
jsr routine20
jsr routine39
bit printer_type_flags
bpl W986E
; Commodore MPS
bit print_color_flag
bmi W981C
W986E:
bit print_color_flag
bpl :+
lda #$0A
jsr BSOUT
: lda $06
sta $07
lda #$00
sta $10
W987F:
lda #$00
sta $11
W9883:
lda $10
jsr routine32
jsr zero_3ew
W988B:
jsr routine36
lda $07
sta $06
jsr c3w_to_c1w
@4: jsr routine13
jsr routine37
bne :+
jsr routine23
: inx
cpx $3D
bne @4
jsr routine31
beq :+
lda $C2
cmp #$FD
bcc @4
: jsr routine14
bcc @1
jsr routine29
@1: jsr routine17
bne W988B
bit print_color_flag
bpl @2
inc $11
lda $11
cmp #$02
bne W9883
inc $10
lda $10
cmp #$07
bne W987F
@2: jsr c1w_to_c3w
bit printer_type_flags
bpl @3
; Commodore MPS
jsr routine21
bpl W986E
bmi W98E5
@3: ; Epson/NEC P
lda $C4
cmp #$FD
bcc W986E
W98E5:
jsr print_cr
bit print_color_flag
bpl :+
; Set printing colour to black
lda #'r'
jsr print_esc_char
lda #$00 ; Black
jsr BSOUT
: jmp print_done
routine24:
inc $02
lda $02
cmp #200
rts
W9900:
sty $09
jsr zero_48w
@1: jsr c3w_to_c1w
jsr zero_3ew
sty $02
ldy $09
: jsr routine13
jsr routine14
bcc :+
jsr routine15
jsr routine16
jsr routine24
bcc :-
: jsr routine38
bcs :+
lda $DC01 ; Data port B #1: keyboard, joystick, paddle
cmp #$7F
beq :+
jsr routine30
bne @1
jsr routine17
sty $09
bne @1
: jmp W534E
routine6:
jsr routine20
jsr routine40
ldy #$00
bit printer_type_flags
bpl :+
bit print_color_flag
bmi W9900
W994D:
: sty $09
lda $03
sta $05
lda $06
sta $07
bit print_color_flag
bpl @4
lda #$0A
jsr BSOUT
lda #$00
sta $10
@3:
lda #$00
sta $11
@4:
lda $10
jsr routine32
jsr c3w_to_c1w
jsr zero_3ew
sty $02
@2: ldy $09
lda $05
sta $03
lda $07
sta $06
jsr $54D4
@1: jsr routine13
jsr routine30
bne :+
jsr routine17
: inx
cpx $3D
bne @1
jsr routine31
beq :+
cpy #$A0
bcc @1
: jsr routine14
bcc :+
jsr routine29
: jsr routine16
jsr routine24
bne @2
bit print_color_flag
bpl :+
inc $11
lda $11
cmp #$02
bne @4
inc $10
lda $10
cmp #$07
bne @3
: bit printer_type_flags
bpl :+
jsr routine21
bpl W994D
bmi W99D1
: cpy #$A0
bcs W99D1
jmp W994D
W99D1:
jmp W98E5
routine36:
; $0B00 is VIC-II register backup. Weird code.
lda #$00
ldx #$1A
: sta $0B30,x
dex
bpl :-
ldx #$03
: sta $38,x
dex
bne :-
stx $38
rts
routine31:
bit print_color_flag
bmi W9A11
bit $50
bpl W9A0C
tya
pha
ldy #$00
ldx $38
: lda $0053,y
eor $25
jsr routine18
sta $0B30,x
inx
iny
cpy $29
bne :-
pla
tay
jmp W9A1F
W9A0C:
lda $9E
eor $25
.byte $2c
W9A11:
lda $9E
jsr routine18
pha
lda $38
and #$03
tax
pla
sta $39,x
W9A1F:
lda print_8p24p_flag
beq @x
ldx #$00
lda $38
clc
adc #$09
sta $38
cmp #$1B
@x: rts
routine18:
bit printer_type_flags
bpl @x
stx $24
ldx #7
sta $9E
: lsr $9E
rol
dex
bne :-
and $46
ora #$80
ldx $24
@x: rts
routine29:
bit print_color_flag
bmi routine15
bit $50
bpl routine15
@1: lda $0B2F,x
jsr BSOUT
bit print_8p24p_flag
bpl :+
lda $0B38,x
jsr BSOUT
lda $0B41,x
jsr BSOUT
: dex
bne @1
rts
routine15:
lda $39
jsr BSOUT
bit print_8p24p_flag
bpl :+
lda $3A
jsr BSOUT
lda $3B
jsr BSOUT
: dex
bne routine15
rts
zero_3ew:
ldy #$00
sty $3E
sty $3F
rts
routine14:
lda $29
sta $42
bit printer_type_flags
bpl @1
lda $40
sec
sbc $3E
tax
lda $41
sbc $3F
bcc @rts
pha
lda $3E
clc
adc $42
sta $3E
bcc :+
inc $3F
: pla
bne @1
clc
txa
beq @rts
cpx $42
bcc @2
@1: ldx $42
@2: sec
@rts: rts
routine40:
ldy #$60
lda #$7C
ora #$80
bne :+
routine39:
ldy #$00
lda #$80
: sty $C3
sta $C4
ldx #$00
stx $02
stx $03
stx $05
stx $06
dex
stx $04
rts
lda $AF
jsr W9AE3
sta $AF
lda $AE
jsr W9AE3
sta $AE
lda $9E
W9AE3:
bit printer_type_flags
bpl reverse_bits_A
lsr
and $04
ora #$80
rts
reverse_bits_A:
pla
sta $FD
ldx #8
: lsr $FD
rol
dex
bne :-
rts
routine37:
inc $06
lda $06
cmp print_vertical_size
bcc :+
lda #$00
sta $06
: rts
routine30:
inc $06
lda $06
cmp print_horizontal_size
bcc :+
lda #$00
sta $06
: rts
bit $50
bmi W9B1F
routine17:
lda $03
eor #$10
sta $03
bne W9B20
W9B1F:
iny
W9B20:
cpy #$A0
rts
W9B23:
tax
lda tabel2,x
sta $39
rts
tabel2:
.byte $00,$01,$04,$03,$04,$05,$06,$07
.byte $02,$02,$02,$00,$01,$05,$03,$01
W9B3A:
bit printer_type_flags
bmi W9B23
ldx $11
beq @1
tax
lda tabel3,x
cmp $10
sec
bcs @2
@1: tax
lda tabel3+$10,x
cmp $10
sec
@2: beq :+
clc
: rol $9E
rts
tabel3:
.byte $00, $10, $01, $02, $01, $06, $02, $04
.byte $05, $01, $01, $10, $10, $06, $02, $10
.byte $10, $10, $01, $10, $02, $06, $02, $10
.byte $10, $00, $10, $10, $10, $10, $10, $10
routine13:
sei
lda #$34 ; Disable ROM
sta $01
tya
pha
txa
pha
lda $03
cmp #$10
lda ($C1),y
bcc :+
lsr
lsr
lsr
lsr
: and #$0F
jsr routine25
lda #$37 ; Enable ROM
sta $01
pla
tax
pla
tay
cli
rts
routine25:
bit print_color_flag
bmi W9B3A
bit $50
bpl W9BEB
pha
lda #$00
sta $48
lda #$60
sta $49
lda $03
beq :+
lda $48
clc
adc $51
sta $48
lda $49
adc $52
sta $49
: ldx $06
beq @3
@1: lda $48
clc
adc $27
sta $48
bcc :+
inc $49
: dex
bne @1
@3: pla
tay
ldx $29
@2: lda ($48),y
clc
beq :+
sec
: rol $52,x
lda $48
clc
adc $28
sta $48
bcc :+
inc $49
: dex
bne @2
rts
W9BEB:
bit $26
bpl @3
sta $51
lda #$00
sta $48
lda #$40
sta $49
@1: sec
sbc #$05
bcc @2
pha
clc
lda $48
adc #$28
sta $48
bcc :+
inc $49
: pla
jmp @1
@2: tya
lsr
lsr
tay
lda ($48),y
and #$0F
cmp $51
clc
bcc @4
@3: cmp $0B21
clc
@4: beq :+
sec
: rol $9E
rts
c1w_to_c3w:
lda $C1
sta $C3
lda $C2
sta $C4
rts
c3w_to_c1w:
lda $C3
sta $C1
lda $C4
sta $C2
rts
routine23:
lda $C1
clc
adc #$A0
sta $C1
bcc :+
inc $C2
: rts
routine16:
lda $C1
sec
sbc #$A0
sta $C1
bcs :+
dec $C2
: rts
routine20:
jsr routine34
bcs except_close_all
bit printer_type_flags
bmi W9C7D ; CBM printer
bvc W9C69
lda #$1C
jsr BSOUT
lda #'3'
jsr BSOUT
lda #'/'
jmp BSOUT
W9C69:
lda #'3' ; Set line spacing
jsr print_esc_char
lda #23 ; 23/180 inch
jsr BSOUT
lda #'A' ; Set line spacing
jsr print_esc_char
lda #$08 ; 8/60 inch
jmp BSOUT
W9C7D:
bit print_color_flag
bmi maybe_set_size
lda #$08 ; 8/60 inch (or enter graphics mode when called via label for CBM printers)
jmp_bsout:
jmp BSOUT
print_cr:
lda #$0D
bne jmp_bsout
except_close_all:
pla
pla
jmp close_all
maybe_set_size:
; This ESC 'C' command is supported by the CBM MCS-801 and is used for
; "scan mode bit image printing".
;
; On the MCS-820 and MPS-1550C ESC 'C sets the page length like Epson.
lda #'C'
jsr print_esc_char ;
bit print_sideways_flag
bpl :+
jsr routine26
jmp routine19
: jsr routine19
routine26:
lda print_vertical_size
ldx #'2'
ldy #'0'
cmp #$01
beq out_2c0 ;'200'
ldx #'4'
cmp #$02
beq out_2c0 ;'400'
ldx #'6'
cmp #$03
beq out_2c0 ;'600'
ldy #'4' ;'640'
bne out_2c0
routine19:
lda print_horizontal_size
ldx #'3'
ldy #'2'
cmp #$01
beq out_2c0
ldx #'6'
ldy #'4'
out_2c0:
txa
jsr BSOUT
tya
jsr BSOUT
lda #'0'
jmp BSOUT
print_esc_char:
pha
lda #$1B
jsr BSOUT
pla
bne jmp_bsout
routine32:
bit print_color_flag
bpl :+
; Set printing colour to A
pha
lda #'r'
jsr print_esc_char
pla
jsr BSOUT
: lda $DC01
cmp #$7F ; Check for run/stop
beq print_abort
jsr print_cr
bit printer_type_flags
bmi W5855
lda print_graphmode_val
cmp #$04
bcs W581F
lda $DC0C
beq :+
cmp #'7'
bcs :+
cmp #'0'
bcs W581F
: lda print_graphmode_val
cmp #$02
bcs :+
adc #$4B
.byte $2C ; Skip next instruction
: adc #$56
jsr print_esc_char
jmp W5829
W581F:
lda #'*'
jsr print_esc_char
lda print_graphmode_val
jsr BSOUT
W5829:
lda $33
jsr BSOUT
lda $34
jmp BSOUT
print_abort:
pla
pla
print_done:
jsr print_cr
bit printer_type_flags
bmi @mps
bit print_color_flag
bpl close_all
; Set colour to black
lda #'r'
jsr print_esc_char
lda #$00
.byte $2C ; Skip next instruction
@mps: lda #$0F ; Exit graphics mode, single width text printing
jsr BSOUT
close_all:
jsr CLALL
lda #$01
jsr CLOSE
W5855:
rts
routine34:
lda #$01
ldy #$01
bit printer_type_flags
bpl :+
dey
routine22:
: ldx #4 ; Device 4 = printer
jsr SETLFS
lda #0
jsr SETNAM
jsr OPEN
ldx #1
jmp CKOUT
printer_graphmodes:
.byte $00, $01, $02, $03, $04, $06, $20, $21
.byte $26, $27
tabel4:
.byte $10, $00, $0B, $03, $09, $05
.byte $0D, $01, $0A, $0E, $06, $0C, $07, $02
.byte $08, $04
end_of_text:
.segment "printersettings"
; AE000
.global freezer_screenshot_prepare
freezer_screenshot_prepare:
ldx #<__copycode_SIZE__ - 1
: lda __copycode_LOAD__,x
sta <__copycode_RUN__,x ; DATA current line number
dex
bpl :-
ldy #$00
; Compute VIC-II base adress
lda $DD00 ; Data port A #2: serial bus, RS-232, VIC memory
and #$03
eor #$03
sta $C8
lsr
ror
ror
sta $AD
ldx #>$4000
stx $AF
; Copy the VIC-II bank to $4000..$7FFF
lda #$34
jsr copy_x_pages
lda $D011
and #$20 ; Charset not needed in bitmap mode
bne @1
lda $C8
bne @1 ; Charset only needed in bank 0?? Wrong! :)
lda $D018 ; VIC memory control register
and #$0E
cmp #$04 ; Charset at $1000
beq :+
cmp #$06 ; Or $1800?
bne @1
: ; Copy the character ROM to $5000.
lda #>$D000
sta $AD
lda #>$5000
sta $AF
ldx #$10
lda #$33
jsr __copycode_LOAD__ ; Ugly!
@1: ; Copy the colour RAM to $1800
lda #>$D800
sta $AD
lda #>$1800
sta $AF
ldx #$04
lda #$37
jsr __copycode_LOAD__ ; Ugly!
; Y=0
; Backup the VIC-II to $0B00
: lda $D000,y
sta $0B00,y
iny
bne :-
lda $0B11
and #$20
sta $C7 ; bitmap mode flag
lda $0B16
and #$10
asl
sta $AC ; 40 column flag
ldx #$00
stx $C1
stx $C3
stx $CE ; Character line counter
lda $0B18
tax
and #$F0
lsr
lsr
ora #$40
sta $C2 ; ($C1) = pointer to screen RAM
txa
and #$08
ora #$10
lsr
ldy $C7
bne :+
txa
and #$0E
ora #$10
lsr
: sta $C8 ; $10|bitmap / $10|charset
lda #>$1800 ; colour RAM pointer
sta $C4
lda $0B23 ; background colour 2
sta $B4
lda $0B22 ; background colour 1
sta $B5
lda #$00
sta $B2
lda #$80
sta $B3
lda #>$1900
sta $CD
; VIC-II bank to $4000..$7FFF
lda $DD00 ; Data port A #2: serial bus, RS-232, VIC memory
and #$FC
ora #$02
sta $DD00 ; Data port A #2: serial bus, RS-232, VIC memory
lda #$33
sta $01
bne @4 ; Always!
@2: lda #$00
sta $CE ; Character line counter
lda $C1
clc
adc #40 ; Move one line down
sta $C1
sta $C3
bcc @4
inc $C2
inc $C4
lda $C7
beq @4
inc $C8
@4: lda #$00
sta $CF
@3: lda $C8 ; Copy charset location
sta $CA
ldy $CF
lda ($C3),y
ldx $C7
bne :+
ldx $AC
beq :+
and #$07
tax
lda ($C3),y
and #$08
sta $03
txa
: and #$0F
sta $B6
jsr read_pixel_byte
lda #$80
sta $AE
jsr WA234
inc $CF
lda $CF
cmp #40
bcc @3
inc $CE
lda $CE
cmp #$08
bne @4
dec $CD
bne @2
jsr WA27D
lda #$37
sta $01 ; 6510 I/O register
ldx #$FF
sei
txs
cld
jsr $FDA3 ; IOINIT inside KERNAL
lda #$00
tay
: sta $0002,y
sta $0200,y
sta $0300,y
iny
bne :-
jsr $FD15 ; Routine RESTOR of KERNAL
ldx #$00
ldy #$A0
jsr $FE2D ; SETTOP inside KERNAL
lda #$08
sta $0282 ; Pointer: Memory base for Operative System
lda #$04
sta $0288 ; Top of memory screen (page)
jsr $FF5B ; Routine CINT of KERNAL
jsr $E453 ; Routine: Set BASIC vectors (case 0x300..case 0x309)
jsr $E3BF ; Routine: Set USR instruction and memory for BASIC
; Backup $C000..$CFFF to $0C00
ldy #$00
sty $AC
sty $AE
lda #>$C000
sta $AD
lda #>$0C00
sta $AF
ldx #$10
: lda ($AC),y
sta ($AE),y
iny
bne :-
inc $AD
inc $AF
dex
bne :-
; Copy the screenshot code to $5000
lda #>__screenshotcode_LOAD__
sta $AD
lda #>__screenshotcode_RUN__
sta $AF
ldx #(>__screenshotcode_SIZE__) + 2 ; copy one page too much
: lda ($AC),y
sta ($AE),y
iny
bne :-
inc $AD
inc $AF
dex
bne :-
; Copy the screen RAM to $4000
lda $0B18 ; Backup of $D018
and #$F0
lsr
lsr
clc
adc #$40
sta $AD
lda #>$4000
sta $AF
ldy #<$4000
sty $AC
sty $AE
ldx #$04
: lda ($AC),y
sta ($AE),y
iny
bne :-
inc $AD
inc $AF
dex
bne :-
lda #>$8017 ; init_vectors_goto_psettings
pha
lda #<$8017
pha
jmp _enable_fcbank0
WA1BA:
lda $AC
bne @5
lda $C7
bne @3
@1: lda $B0
and $AE
bne @2
lda $0B21 ; Backup of $D021
.byte $2c ; Skip next instruction
@2: lda $B6
rts
@3: lda $B0
and $AE
bne @4
lda $B4
rts
@4: lda $B5
rts
@5: lda $C7
bne @6
lda $03
beq @1
@6: jsr WA1E9
asl $AE
rts
WA1E9:
lda $B0
tax
and $AE
bne @2
lsr $AE
txa
and $AE
beq @1
lda $B5
rts
@1: lda $0B21
rts
@2: lsr $AE
txa
and $AE
beq @3
lda $B6
rts
@3: lda $B4
rts
;
; $A20B
;
read_pixel_byte:
lda ($C1),y ; Get byte from screen RAM
ldx $C7
beq :+ ; Text mode? Jump
; Bitmap mode... byte contains colours
sta $B4 ; Background colour
lsr
lsr
lsr
lsr
sta $B5 ; Foreground colour
tya
clc
adc $C1
bcc :+
inc $CA
: ldx #3
: asl
rol $CA
dex
bne :-
ora $CE ; Character scan line
sta $C9
ldy #$00
lda ($C9),y ; Read a byte from character ROM or the bitmap
sta $B0
rts
WA234:
jsr WA1BA
and #$0F
pha
lsr $AE
ldx $AC
beq @2
ldx $C7
bne @1
ldx $03
beq @2
@1: lsr $AE
pha
@2: bcc WA234
ldy #3
: pla
asl
asl
asl
asl
sta $02
pla
ora $02
sta ($B2),y
dey
bpl :-
lda $B2
clc
adc #$04
sta $B2
bcc :+
inc $B3
lda $B3
and #$0F
bne :+
lda $01
pha
lda #$37
sta $01
inc $D020 ; Border color
pla
sta $01
: rts
WA27D:
lda #$80
sta $02
lda #$07
sta $03
lda #$F8
sta $C1
ldx #<__ramload_SIZE__ -1
: lda __ramload_LOAD__,x
sta <__ramload_RUN__,x
dex
bpl :-
@5: lda $0B15
and $02
beq @4
lda $0B1B
and $02
bne @4
jsr WA2FB
lda #$00
sta $33
@2: jsr WE363
lda $08
cmp #$C8
bcs @3
jsr WA3AB
lda $06
sta $30
lda $07
sta $31
lda #$00
sta $32
@1: lda $31
beq :+
lda $30
cmp #$40
bcs @6
: lda $32
ldy $0B
cpy #$18
beq :+
lsr
: tay
lda $0040,y
beq @6
jsr stuff37a_to_lhnibble_of_3e
@6: inc $30
bne :+
inc $31
: inc $32
lda $32
cmp $0B
bcc @1
@3: inc $08
inc $33
lda $33
cmp $0A
bcc @2
@4: lsr $02
dec $03
bpl @5
rts
WA2FB:
lda #$01
sta $05
ldx #$06
ldy $03
lda ($C1),y
: asl
rol $05
dex
bne :-
sta $04
lda $03
asl
tay
sec
lda $0B01,y
sbc #$32
sta $08
sec
lda $0B00,y
sbc #$18
sta $06
ldx #$00
lda $0B10
and $02
beq :+
inx
: txa
sbc #$00
sta $07
lda $0B1C
and $02
sta $09
ldx #$15
lda $0B17 ; Backup of $D017
and $02
beq :+
ldx #$2A
: stx $0A
ldx #$18
lda $0B1D ; Backup of $D01D
and $02
beq :+
ldx #$30
: stx $0B
lda $0B25 ; Backup of $D025
sta $38
ldy $03
lda $0B27,y
sta $39
lda $0B26
sta $3A
rts
WE363:
lda $33
ldx $0A
cpx #$15
beq :+
lsr
bcs @rts
: ldy #$00
: lda ($04),y
sta $000C,y
iny
cpy #$03
bne :-
tya
clc
adc $04
sta $04
bcc :+
inc $05
: ldx #$00
@1: asl $0E
rol $0D
rol $0C
lda #$00
bcc :+
lda #$02
: ldy $09
bne @2
@3: sta $40,x
inx
cpx #$18
bne @1
@rts: rts
@2: asl $0E
rol $0D
rol $0C
adc #$00
sta $40,x
inx
bne @3
WA3AB:
lda #<$8000
sta $3E
lda #>$8000
sta $3F
ldy $08
beq @rts
@1: clc
lda $3E
adc #$A0
sta $3E
bcc :+
inc $3F
: dey
bne @1
@rts: rts
stuff37a_to_lhnibble_of_3e:
tax
lda $37,x
and #$0F
tax
lda $31
lsr
lda $30
ror
tay
jsr load_3e_rom_hidden ; preserves C
bcs WE3E2
and #$F0
sta $3C
txa
ora $3C
WE3DF:
sta ($3E),y
rts
WE3E2:
and #$0F
sta $3C
txa
asl
asl
asl
asl
ora $3C
jmp WE3DF
.segment "ramload"
load_3e_rom_hidden:
lda #$34
sta $01
lda ($3E),y
dec $01
rts
.segment "copycode"
copy_x_pages:
sta $01
copy_ac_ec:
sty $AC
sty $AE
: lda ($AC),y
sta ($AE),y
iny
bne :-
inc $AD
inc $AF
dex
bne :-
lda #$37
sta $01
rts
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.