repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
4ms/stm32mp1-baremetal | 5,306 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/lib/memcpy.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* linux/arch/arm/lib/memcpy.S
*
* Author: Nicolas Pitre
* Created: Sep 28, 2005
* Copyright: MontaVista Software, Inc.
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#define LDR1W_SHIFT 0
#define STR1W_SHIFT 0
.macro ldr1w ptr reg abort
W(ldr) \reg, [\p... |
4ms/stm32mp1-baremetal | 4,596 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/lib/uldivmod.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2010, Google Inc.
*
* Brought in from coreboot uldivmod.S
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
* A, Q = r0 + (r1 << 32)
* B, R = r2 + (r3 << 32)
* A / B = Q ... R
*/
A_0 .req r0
A_1 .req r1
B_0 .req r2
B_1 .req r3
C_0 .req r4
C_1 .r... |
4ms/stm32mp1-baremetal | 3,947 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/lib/crt0_arm_efi.S | /* SPDX-License-Identifier: GPL-2.0+ OR BSD-2-Clause */
/*
* crt0-efi-arm.S - PE/COFF header for ARM EFI applications
*
* Copright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
*
* This file is taken and modified from the gnu-efi project.
*/
#include <asm-generic/pe.h>
.section .text.head
/*
* Magic "MZ... |
4ms/stm32mp1-baremetal | 6,637 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/lib/vectors.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* vectors - Generic ARM exception table code
*
* Copyright (c) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (c) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (c) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
* Co... |
4ms/stm32mp1-baremetal | 5,110 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/lib/crt0_64.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* crt0 - C-runtime startup Code for AArch64 U-Boot
*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* (C) Copyright 2012
* Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <config.h>
#include <asm-offsets.h>
#include <asm/macro.h>
#include <linux/l... |
4ms/stm32mp1-baremetal | 2,928 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/lib/relocate_64.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - common relocation function for AArch64 U-Boot
*
* (C) Copyright 2013
* Albert ARIBAUD <albert.u.boot@aribaud.net>
* David Feng <fenghua@phytium.com.cn>
*/
#include <asm-offsets.h>
#include <config.h>
#include <elf.h>
#include <linux/linkage.h>
#include <asm... |
4ms/stm32mp1-baremetal | 1,579 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/lib/vectors_m.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015
* Kamil Lulko, <kamil.lulko@gmail.com>
*/
#include <config.h>
#include <asm/assembler.h>
#include <linux/linkage.h>
.type __hard_fault_entry, %function
__hard_fault_entry:
mov r0, sp @ pass auto-saved registers as argument
b do_hard_fault
.type __m... |
4ms/stm32mp1-baremetal | 1,836 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/lib/ccn504.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015 Freescale Semiconductor
*
* Extracted from gic_64.S
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/macro.h>
/*************************************************************************
*
* void ccn504_add_masters_to_dvm(CCI_MN_BASE, ... |
4ms/stm32mp1-baremetal | 2,354 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/lib/memset.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* linux/arch/arm/lib/memset.S
*
* Copyright (C) 1995-2000 Russell King
*
* ASM optimised string functions
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
.text
.align 5
.syntax unified
#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) && !defined(MEMSET_NO_THUMB_BUI... |
4ms/stm32mp1-baremetal | 5,062 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/lib/gic_64.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* GIC Initialization Routines.
*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
#include <asm/gic.h>
#include <asm/macro.h>
/*********************************************************... |
4ms/stm32mp1-baremetal | 5,407 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/lib/crt0.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* crt0 - C-runtime startup Code for ARM U-Boot
*
* Copyright (c) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <config.h>
#include <asm-offsets.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
* This file handles the target-independent stages... |
4ms/stm32mp1-baremetal | 3,895 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/lib/crt0_aarch64_efi.S | /* SPDX-License-Identifier: GPL-2.0+ OR BSD-2-Clause */
/*
* crt0-efi-aarch64.S - PE/COFF header for aarch64 EFI applications
*
* Copright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
*
*
* This file is taken and modified from the gnu-efi project.
*/
#include <asm-generic/pe.h>
.section .text.head
/*
... |
4ms/stm32mp1-baremetal | 8,771 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/lib/lib1funcs.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines
*
* Author: Nicolas Pitre <nico@fluxnic.net>
* - contributed to gcc-3.4 on Sep 30, 2003
* - adapted for the Linux kernel on Oct 2, 2003
*/
/*
* Copyright 1995, 1996, 1998, 1999, 2000, 2003 Free Softwa... |
4ms/stm32mp1-baremetal | 2,196 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/lib/debug.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* linux/arch/arm/kernel/debug.S
*
* Copyright (C) 1994-1999 Russell King
*
* 32-bit debugging code
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
.text
/*
* Some debugging routines (useful if you've got MM problems and
* printk isn't working). For DEB... |
4ms/stm32mp1-baremetal | 3,677 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/mach-exynos/sec_boot.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013 Samsung Electronics
* Akshay Saraswat <akshay.s@samsung.com>
*/
#include <config.h>
#include <asm/arch/cpu.h>
.globl relocate_wait_code
relocate_wait_code:
adr r0, code_base @ r0: source address (start)
adr r1, code_end @ r1: source addre... |
4ms/stm32mp1-baremetal | 1,392 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/mach-mvebu/lowlevel_spl.S | /* SPDX-License-Identifier: GPL-2.0+ */
#include <config.h>
#include <linux/linkage.h>
ENTRY(save_boot_params)
stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */
ldr r12, =CONFIG_SPL_BOOTROM_SAVE
str sp, [r12]
b save_boot_params_ret
ENDPROC(save_boot_params)
ENTRY(return_to_bootrom)
ldr r12, =CONFIG_SPL_... |
4ms/stm32mp1-baremetal | 2,202 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/mach-tegra/psci.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014, NVIDIA
* Copyright (C) 2015, Siemens AG
*
* Authors:
* Thierry Reding <treding@nvidia.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*/
#include <linux/linkage.h>
#include <asm/macro.h>
#include <asm/psci.h>
.pushsection ._secure.text, "ax"
.arch... |
4ms/stm32mp1-baremetal | 1,951 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/mach-mediatek/mt7629/lowlevel_init.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 MediaTek Inc.
*/
#include <linux/linkage.h>
#include <asm/proc-armv/ptrace.h>
#define WAIT_CODE_SRAM_BASE 0x0010ff00
#define SLAVE_JUMP_REG 0x10202034
#define SLAVE1_MAGIC_REG 0x10202038
#define SLAVE1_MAGIC_NUM 0x534c4131
#define GIC_CPU_BASE 0x103... |
4ms/stm32mp1-baremetal | 12,571 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/mach-omap2/omap3/lowlevel_init.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Board specific setup info
*
* (C) Copyright 2008
* Texas Instruments, <www.ti.com>
*
* Initial Code by:
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*/
#include <config.h>
#include <asm/arch/mem.h>
#include <asm/arch/clocks_omap3.h... |
4ms/stm32mp1-baremetal | 2,918 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Secure entry function for CPU Core #1
*
* (C) Copyright 2016
* Texas Instruments, <www.ti.com>
*
* Author :
* Harinarayan Bhatta <harinarayan@ti.com>
*/
#include <config.h>
#include <asm/arch/omap.h>
#include <asm/omap_common.h>
#include <linux/linkage.h>
.arch_ext... |
4ms/stm32mp1-baremetal | 1,199 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/mach-imx/mx7/psci-suspend.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/armv7.h>
#include <asm/psci.h>
.pushsection ._secure.text, "ax"
.arch_extension sec
.globl v7_invalidate_l1
v7_invalidate_l1:
mov r0, #0
mcr p15, 2, r0, c0, c0, 0
mrc p15, 1, r0, c... |
4ms/stm32mp1-baremetal | 1,255 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/mach-imx/imx8m/lowlevel_init.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017 NXP
*/
#include <config.h>
.align 8
.global rom_pointer
rom_pointer:
.space 256
/*
* Routine: save_boot_params (called after reset from start.S)
*/
.global save_boot_params
save_boot_params:
/* The firmware provided ATAG/FDT address can be found in r... |
4ms/stm32mp1-baremetal | 9,285 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/mach-imx/mx5/lowlevel_init.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*/
#include <config.h>
#include <asm/arch/imx-regs.h>
#include <generated/asm-offsets.h>
#include <linux/linkage.h>
.section ".text.init", "x"
.macro init_arm_e... |
4ms/stm32mp1-baremetal | 5,149 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/armv7/cache_v7_asm.S | /* SPDX-License-Identifier: GPL-2.0+ */
#include <config.h>
#include <linux/linkage.h>
#include <linux/sizes.h>
#include <asm/system.h>
#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
#define ARM(x...)
#define THUMB(x...) x
#else
#define ARM(x...) x
#define THUMB(x...)
#endif
/*
* v7_flush_dcache_all()
*
* Flush the whole... |
4ms/stm32mp1-baremetal | 9,096 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/armv7/psci.S | /*
* Copyright (C) 2013,2014 - ARM Ltd
* Author: Marc Zyngier <marc.zyngier@arm.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the ho... |
4ms/stm32mp1-baremetal | 10,454 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/armv7/start.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
*
* Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>... |
4ms/stm32mp1-baremetal | 5,656 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/armv7/nonsec_virt.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* code for switching cores into non-secure state and into HYP mode
*
* Copyright (c) 2013 Andre Przywara <andre.przywara@linaro.org>
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/gic.h>
#include <asm/armv7.h>
#include <asm/proc-armv/ptrace.h>
.arch_exte... |
4ms/stm32mp1-baremetal | 1,257 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/armv7/smccc-call.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015, Linaro Limited
*/
#include <linux/linkage.h>
#include <asm/opcodes-sec.h>
#include <asm/opcodes-virt.h>
#ifdef CONFIG_EFI_LOADER
.section .text.efi_runtime
#endif
#define UNWIND(x...)
/*
* Wrap c macros in asm macros to delay expansion until after... |
4ms/stm32mp1-baremetal | 1,501 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/armv7/lowlevel_init.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* A lowlevel_init function that sets up the stack to call a C function to
* perform further init.
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Author :
* Aneesh V <aneesh@ti.com>
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.... |
4ms/stm32mp1-baremetal | 2,810 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/arm926ejs/start.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM926EJS CPU-core
*
* Copyright (c) 2003 Texas Instruments
*
* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyrig... |
4ms/stm32mp1-baremetal | 2,428 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/arm946es/start.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM926EJS CPU-core
*
* Copyright (c) 2003 Texas Instruments
*
* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyrig... |
4ms/stm32mp1-baremetal | 1,657 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/arm720t/start.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM720 CPU-core
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
*/
#include <asm-offsets.h>
#include <config.h>
/*
***********************************************************************... |
4ms/stm32mp1-baremetal | 2,783 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/arm1176/start.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM1176 CPU-core
*
* Copyright (c) 2007 Samsung Electronics
*
* Copyright (C) 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*
* 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
* 2007-09-21 - Adde... |
4ms/stm32mp1-baremetal | 2,432 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/arm1136/start.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for OMP2420/ARM1136 CPU-core
*
* Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de... |
4ms/stm32mp1-baremetal | 2,525 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/sa1100/start.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for SA1100 CPU
*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
*/
#inclu... |
4ms/stm32mp1-baremetal | 6,046 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/armv8/cache.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* This file is based on sample code from ARMv8 ARM.
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/macro.h>
#include <asm/system.h>
#include <linux/linkage.h>
/*
* void __asm_dcache_level(level... |
4ms/stm32mp1-baremetal | 4,382 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/armv8/exceptions.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/ptrace.h>
#include <asm/macro.h>
#include <linux/linkage.h>
/*
* AArch64 exception vectors:
* We have four types of exceptions:
* - synchronous: tra... |
4ms/stm32mp1-baremetal | 1,131 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/armv8/transition.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
#include <asm/macro.h>
.pushsection .text.armv8_switch_to_el2, "ax"
ENTRY(armv8_switch_to_el2)
switch_el x6, 1f, 0f, 0f
0:
cmp x5, #ES_T... |
4ms/stm32mp1-baremetal | 9,297 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/armv8/psci.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Author: Hongbo Zhang <hongbo.zhang@nxp.com>
* This file implements LS102X platform PSCI SYSTEM-SUSPEND function
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/psci.h>
#include <asm/secure.h>
/* Default PSC... |
4ms/stm32mp1-baremetal | 8,322 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/armv8/start.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
#include <asm/macro.h>
#include <asm/armv8/mmu.h>
/*************************************************************************
*
* Startup... |
4ms/stm32mp1-baremetal | 1,208 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/armv8/smccc-call.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015, Linaro Limited
*/
#include <linux/linkage.h>
#include <linux/arm-smccc.h>
#include <generated/asm-offsets.h>
#ifdef CONFIG_EFI_LOADER
.section .text.efi_runtime
#endif
.macro SMCCC instr
.cfi_startproc
\instr #0
ldr x4, [sp]
stp x0, x1, [x4, #ARM... |
4ms/stm32mp1-baremetal | 1,052 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/armv8/lowlevel_init.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* A lowlevel_init function that sets up the stack to call a C function to
* perform further init.
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
ENTRY(lowlevel_init)
/*
* Setup a temporary stack. Global data is not available yet.
*/
#if de... |
4ms/stm32mp1-baremetal | 1,430 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/armv8/sec_firmware_asm.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 NXP Semiconductor, Inc.
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/system.h>
#include <asm/macro.h>
WEAK(_sec_firmware_entry)
/*
* x0: Secure Firmware entry point
* x1: Exception return address Low
* x2: Exception return address... |
4ms/stm32mp1-baremetal | 2,388 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/arm920t/start.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM920 CPU-core
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
*/
#include <asm-offsets.h>
#include <common.h>
#include <config.h>
/... |
4ms/stm32mp1-baremetal | 4,898 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/pxa/start.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for XScale CPU-core
*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
* C... |
4ms/stm32mp1-baremetal | 5,253 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/armv7/ls102xa/psci.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2015 Freescale Semiconductor, Inc.
* Author: Wang Dongsheng <dongsheng.wang@freescale.com>
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/armv7.h>
#include <asm/arch-armv7/generictimer.h>
#include <asm/psci.h>
#define RCPM_TWAITSR 0x04C
#de... |
4ms/stm32mp1-baremetal | 2,810 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/arm926ejs/mxs/start.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM926EJS CPU-core
*
* Copyright (c) 2003 Texas Instruments
*
* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
*
* Copyright (c) 2001 Marius Groger <mag@sysgo.de>
* Copyright (c) 2002 Alex Zupke <azu@sysgo.de>
* Copyrig... |
4ms/stm32mp1-baremetal | 1,694 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/arm926ejs/spear/start.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for ARM926EJS CPU-core
*
* Copyright (c) 2003 Texas Instruments
*
* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyrig... |
4ms/stm32mp1-baremetal | 2,744 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2006
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*/
#include <config.h>
/*
* platform specific initializations are already done in Xloader
* Initializations already done include
* DDR, PLLs, IP's clock enable and reset release etc
*/
.globl ... |
4ms/stm32mp1-baremetal | 1,892 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/arm926ejs/mx27/relocate.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - i.MX27-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
/*
* The i.MX27 SoC is very specific with respect to exceptions: it
* does not... |
4ms/stm32mp1-baremetal | 12,413 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014-2015 Freescale Semiconductor
* Copyright 2019 NXP
*
* Extracted from armv8/start.S
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/gic.h>
#include <asm/macro.h>
#include <asm/arch-fsl-layerscape/soc.h>
#ifdef CONFIG_MP
#include <asm/a... |
4ms/stm32mp1-baremetal | 10,486 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Low-level initialization for EP93xx
*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
* Copyright (C) 2013
* Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
*
* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
* Copyright (C) 2006 Cirrus L... |
4ms/stm32mp1-baremetal | 3,729 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/mach-uniphier/arm32/lowlevel_init.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2012-2015 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
#include <config.h>
#include <linux/linkage.h>
#include <linux/sizes.h>
#include <asm/system.h>
ENTRY(lowlevel_init)
m... |
4ms/stm32mp1-baremetal | 3,982 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/mach-uniphier/arm32/debug_ll.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* On-chip UART initializaion for low-level debugging
*
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*/
#include <linux/serial_reg.h>
#include <linux/linkage.h>
#include "../bcu/bcu-regs.h"
#include "../sc-regs.h"
#include "../sg-regs.h"
#if ... |
4ms/stm32mp1-baremetal | 6,439 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/mach-at91/arm926ejs/lowlevel_init.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Memory Setup stuff - taken from blob memsetup.S
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
*
* Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
* Copyright (C) 2009 Jean-Christ... |
4ms/stm32mp1-baremetal | 3,620 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/mach-at91/arm920t/lowlevel_init.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
*
* Modified for the at91rm9200dk board by
* (C) Copyright 2004
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*/
#include <conf... |
4ms/stm32mp1-baremetal | 4,327 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/include/asm/arch-mx6/mx6_plugin.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*/
#include <config.h>
#ifdef CONFIG_ROM_UNIFIED_SECTIONS
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
#define ROM_VERSION_OFFSET 0x80
#else
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0xC0
#define ROM_VERSION_... |
4ms/stm32mp1-baremetal | 3,595 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/include/asm/arch-mx35/lowlevel_macro.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
*
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
*/
#include <asm/arch/imx-regs.h>
#include <generated/asm-offsets.h>
#include <asm/macro.h>
/*
* AIPS setup - Only setup MPROTx registers.
* The PACR defa... |
4ms/stm32mp1-baremetal | 2,770 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/include/asm/arch-mx7/mx7_plugin.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*/
#include <config.h>
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
#define ROM_VERSION_OFFSET 0x80
#define ROM_API_HWCNFG_SETUP_OFFSET 0x08
plugin_start:
push {r0-r4, lr}
imx7_ddr_setting
imx7_cl... |
4ms/stm32mp1-baremetal | 2,437 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 NXP
*/
#include <config.h>
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
#define ROM_VERSION_OFFSET 0x80
#define ROM_API_HWCNFG_SETUP_OFFSET 0x08
plugin_start:
push {r0-r4, lr}
imx7ulp_ddr_setting
imx7ulp_clock_gating
imx7ulp_qos_... |
530154436/cpp_learning | 1,093 | csapp/ch05.s | .text
.cstring
lC0:
.ascii "%d\12\0"
.text
.globl _main
_main:
LFB1:
pushq %rbp
LCFI0:
movq %rsp, %rbp
LCFI1:
subq $16, %rsp
movl -4(%rbp), %eax
leal 1(%rax), %edx
movl %edx, -4(%rbp)
movl %eax, %esi
leaq lC0(%rip), %rdi
movl $0, %eax
call _printf
movl $0, %eax
leave
LCFI2:
ret
LFE1:
.section __TEXT,... |
530154436/cpp_learning | 3,074 | csapp/ch03/exer.s | .text
.globl _vec_length
_vec_length:
LFB0:
pushq %rbp
LCFI0:
movq %rsp, %rbp
LCFI1:
movq %rdi, -8(%rbp)
movq -8(%rbp), %rax
movl (%rax), %eax
popq %rbp
LCFI2:
ret
LFE0:
.globl _get_vec_element
_get_vec_element:
LFB1:
pushq %rbp
LCFI3:
movq %rsp, %rbp
LCFI4:
movq %rdi, -24(%rbp)
movl %esi, -28(%rbp)
movq... |
530154436/cpp_learning | 8,466 | csapp/ch05/p347_程序优化方法.s | .text
.globl _new_vec
_new_vec:
LFB3:
pushq %rbp
LCFI0:
movq %rsp, %rbp
LCFI1:
subq $32, %rsp
movq %rdi, -24(%rbp)
movl $16, %edi
call _malloc
movq %rax, -8(%rbp)
cmpq $0, -8(%rbp)
jne L2
movl $0, %eax
jmp L3
L2:
movq -8(%rbp), %rax
movq -24(%rbp), %rdx
movq %rdx, (%rax)
cmpq $0, -24(%rbp)
jle L4
mov... |
530154436/cpp_learning | 1,301 | csapp/ch03/p142/control.s | .text
.globl _absdiff
_absdiff:
LFB0:
cmpq %rsi, %rdi
jge L2
movq %rsi, %rax
subq %rdi, %rax
ret
L2:
movq %rdi, %rax
subq %rsi, %rax
ret
LFE0:
.globl _goto_absdiff
_goto_absdiff:
LFB1:
cmpq %rsi, %rdi
jl L5
movq %rdi, %rax
subq %rsi, %rax
ret
L5:
movq %rsi, %rax
subq %rdi, %rax
L6:
ret
LFE1:
.globl ... |
530154436/cpp_learning | 2,577 | csapp/ch03/3_10/buffer_overflow.s | .text
.globl _gets
_gets:
LFB4:
pushq %rbp
LCFI0:
movq %rsp, %rbp
LCFI1:
subq $32, %rsp
movq %rdi, -24(%rbp)
movq -24(%rbp), %rax
movq %rax, -8(%rbp)
jmp L2
L4:
movq -8(%rbp), %rax
leaq 1(%rax), %rdx
movq %rdx, -8(%rbp)
movl -12(%rbp), %edx
movb %dl, (%rax)
L2:
call _getchar
movl %eax, -12(%rbp)
cmpl $... |
530154436/cpp_learning | 5,940 | csapp/code/perf/clock.s | .file "clock.c"
.version "01.01"
gcc2_compiled.:
.data
.align 4
.type cyc_hi,@object
.size cyc_hi,4
cyc_hi:
.long 0
.align 4
.type cyc_lo,@object
.size cyc_lo,4
cyc_lo:
.long 0
.text
.align 4
.globl access_counter
.type access_counter,@function
access_counter:
pushl %ebp
movl %esp,%ebp
pushl %edi
p... |
530154436/cpp_learning | 1,640 | csapp/code/conc/badcnt.s | .file "badcnt.c"
.text
.globl thread
.type thread, @function
thread:
.LFB92:
.cfi_startproc
movq (%rdi), %rcx
testq %rcx, %rcx
jle .L2
movl $0, %eax
.L3:
movq cnt(%rip), %rdx
addq $1, %rdx
movq %rdx, cnt(%rip)
addq $1, %rax
cmpq %rcx, %rax
jne .L3
.L2:
movl $0, %eax
ret
.cfi_endproc
.LFE92:
.size thr... |
530154436/cpp_learning | 2,061 | csapp/code/conc/goodcnt.s | .file "goodcnt.c"
.text
.globl thread
.type thread, @function
thread:
.LFB92:
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl (%rdi), %ebp
testl %ebp, %ebp
jle .L2
movl $0, %ebx
.L3:
movl... |
4ms/stm32mp1-baremetal | 1,114 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/arm/mach-tegra/tegra186/cache.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2016, NVIDIA CORPORATION.
*/
#include <config.h>
#include <linux/linkage.h>
#define SMC_SIP_INVOKE_MCE 0x82FFFF00
#define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11)
#define MCE_SMC_ROC_FLUSH_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 14)
#define MCE_SMC_ROC_C... |
530154436/cpp_learning | 3,919 | csapp/code/asm/linked-list.O1.s | .file "linked-list.c"
.text
.globl new_list_ele
.type new_list_ele, @function
new_list_ele:
pushq %rbx
movq %rdi, %rbx
movl $16, %edi
call malloc
movq %rbx, (%rax)
movq $0, 8(%rax)
popq %rbx
ret
.size new_list_ele, .-new_list_ele
.globl array_to_list_addtail
.type array_to_list_addtail, @function
array_t... |
530154436/cpp_learning | 4,001 | csapp/code/asm/linked-list.Og.s | .file "linked-list.c"
.text
.globl new_list_ele
.type new_list_ele, @function
new_list_ele:
pushq %rbx
movq %rdi, %rbx
movl $16, %edi
call malloc
movq %rbx, (%rax)
movq $0, 8(%rax)
popq %rbx
ret
.size new_list_ele, .-new_list_ele
.globl array_to_list_addtail
.type array_to_list_addtail, @function
array_t... |
530154436/cpp_learning | 1,904 | csapp/code/asm/450-bufdemo.s | .file "450-bufdemo.c"
.text
.globl gets
.type gets, @function
gets:
.LFB34:
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movq %rdi, %rbx
jmp .L2
.L4:
movb %al, (%rbx)
leaq 1... |
530154436/cpp_learning | 3,027 | csapp/code/asm/020-fragments.s | moveg:
/* $begin 020-moveg-sa 0 */
movabsq $0x0011223344556677, %rax # %rax = 0011223344556677 # line:asm:moveg:init
movb $-1, %al # %rax = 00112233445566FF # line:asm:moveg:movb
movw $-1, %ax # %rax = 001122334455FFFF # line:asm:moveg:movw
movl $-1, %eax ... |
530154436/cpp_learning | 1,787 | csapp/code/asm/480-charbuf.s | .file "480-charbuf.c"
.text
.globl len
.type len, @function
len:
.LFB56:
.cfi_startproc
movl $0, %eax
movq $-1, %rcx
repnz; scasb
notq %rcx
leaq -1(%rcx), %rax
ret
.cfi_endproc
.LFE56:
.size len, .-len
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%ld"
.text
.globl iptoa
.type iptoa, @funct... |
530154436/cpp_learning | 3,909 | csapp/code/asm/linked-list.s | .file "linked-list.c"
.text
.p2align 4,,15
.globl new_list_ele
.type new_list_ele, @function
new_list_ele:
.LFB12:
.cfi_startproc
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl $16, %edi
call malloc
movq %rbx, (%rax)
movq $0, 8(%rax)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_... |
530154436/cpp_learning | 2,230 | csapp/code/asm/460-bufovf.s | .file "460-bufovf.c"
.text
.globl gets
.type gets, @function
gets:
.LFB34:
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movq %rdi, %rbx
jmp .L2
.L4:
movb %al, (%rbx)
leaq 1(... |
4ms/stm32mp1-baremetal | 2,405 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/xtensa/lib/misc.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Miscellaneous assembly functions.
*
* Copyright (C) 2001 - 2007 Tensilica Inc.
* Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
*
* Chris Zankel <chris@zankel.net>
*/
#include <linux/linkage.h>
#include <asm/asmmacro.h>
#include <asm/cacheasm.h>
/*
* void _... |
4ms/stm32mp1-baremetal | 13,741 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/xtensa/cpu/start.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2008 - 2013 Tensilica Inc.
* (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
*/
#include <config.h>
#include <asm/asmmacro.h>
#include <asm/cacheasm.h>
#include <asm/regs.h>
#include <asm/arch/tie.h>
#include <asm-offsets.h>
/*
* Offsets into the th... |
4ms/stm32mp1-baremetal | 6,657 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/x86/lib/bios_asm.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* From coreboot x86_asm.S, cleaned up substantially
*
* Copyright (C) 2009-2010 coresystems GmbH
*/
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include "bios.h"
#define SEG(segment) $segment * X86_GDT_ENTRY_SIZE
/*
* This is the interrupt handler stub c... |
530154436/cpp_learning | 23,473 | csapp/code/mem/matmult-test/mm.s | .file "mm.c"
.text
.p2align 4,,15
.globl ijk
.type ijk, @function
ijk:
.LFB39:
.cfi_startproc
testl %ecx, %ecx
jle .L11
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
leal -1(%rcx), %r11d
vxorpd %xmm2, %xmm2, %xmm2
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
leaq 8(%rdi,%r11,8), %r8
ad... |
4ms/stm32mp1-baremetal | 1,040 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/x86/lib/crt0_ia32_efi.S | /* SPDX-License-Identifier: BSD-3-Clause */
/*
* crt0-efi-ia32.S - x86 EFI startup code.
*
* Copyright (C) 1999 Hewlett-Packard Co.
* Contributed by David Mosberger <davidm@hpl.hp.com>.
* All rights reserved.
*/
.text
.align 4
.globl _start
_start:
pushl %ebp
movl %esp,%ebp
pushl 12(%ebp) # copy "image... |
4ms/stm32mp1-baremetal | 1,850 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/x86/cpu/start_from_spl.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* 32-bit x86 Startup Code when running from SPL. This is the startup code in
* U-Boot proper, when SPL is used.
* Copyright 2018 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
*/
#include <config.h>
.section .text.start
.code32
.globl _start
.type _start, @fun... |
4ms/stm32mp1-baremetal | 7,765 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/x86/cpu/start.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* U-Boot - x86 Startup Code
*
* This is always the first code to run from the U-Boot source. To spell it out:
*
* 1. When TPL (Tertiary Program Loader) is enabled, the boot flow is
* TPL->SPL->U-Boot and this file is used for TPL. Then start_from_tpl.S is used
* for SP... |
4ms/stm32mp1-baremetal | 1,240 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/x86/cpu/call32.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
*/
#include <asm/global_data.h>
#include <asm/msr-index.h>
#include <asm/processor-flags.h>
/*
* rdi - 32-bit code segment selector
* rsi - target address
* rdx - table address (0 if none)... |
4ms/stm32mp1-baremetal | 1,661 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/x86/cpu/wakeup.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
*
* From coreboot src/arch/x86/wakeup.S
*/
#include <acpi_s3.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#define RELOCATED(x) ((x) - __wakeup + WAKEUP_BASE)
#define CODE_SEG (X86_GDT_ENTRY_16BIT_CS *... |
4ms/stm32mp1-baremetal | 4,514 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/x86/cpu/sipi_vector.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015 Google, Inc
*
* Taken from coreboot file of the same name
*/
/*
* The SIPI vector is responsible for initializing the APs in the sytem. It
* loads microcode, sets up MSRs, and enables caching before calling into
* C code
*/
#include <asm/global_da... |
4ms/stm32mp1-baremetal | 2,856 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/x86/cpu/start16.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* U-Boot - x86 Startup Code
*
* (C) Copyright 2008-2011
* Graeme Russ, <graeme.russ@gmail.com>
*
* (C) Copyright 2002,2003
* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
*/
#include <asm/global_data.h>
#include <asm/processor-flags.h>
#define BOOT_SEG 0xfff... |
4ms/stm32mp1-baremetal | 2,530 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/x86/lib/fsp1/fsp_car.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*/
#include <config.h>
#include <asm/post.h>
.globl car_init
car_init:
/*
* Note: ebp holds the BIST value (built-in self test) so far, but ebp
* will be destroyed through the FSP call, thus we have to test the
* B... |
4ms/stm32mp1-baremetal | 5,617 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/x86/cpu/intel_common/car.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2014 Google, Inc
*
* From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
* Copyright (C) 2007-2008 coresystems GmbH
* Copy... |
4ms/stm32mp1-baremetal | 1,139 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/x86/cpu/i386/setjmp.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* Written by H. Peter Anvin <hpa@zytor.com>
* Brought in from Linux v4.4 and modified for U-Boot
* From Linux arch/um/sys-i386/setjmp.S
*/
#define _REGPARM
/*
* The jmp_buf is assumed to contain the following, in order:
* %ebx
* %esp
* %ebp
* %esi
* %edi
* <return ... |
4ms/stm32mp1-baremetal | 2,245 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/x86/cpu/i386/call64.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014 Google, Inc
* Copyright (C) 1991, 1992, 1993 Linus Torvalds
*
* Parts of this copied from Linux arch/x86/boot/compressed/head_64.S
*/
#include <asm/global_data.h>
#include <asm/msr-index.h>
#include <asm/processor-flags.h>
.code32
.globl cpu_call64... |
4ms/stm32mp1-baremetal | 2,247 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/x86/cpu/quark/car.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*/
#include <config.h>
#include <asm/pci.h>
#include <asm/post.h>
#include <asm/arch/quark.h>
#include <asm/arch/msg_port.h>
.globl car_init
car_init:
post_code(POST_CAR_START)
/*
* Quark SoC contains an embedded 512... |
4ms/stm32mp1-baremetal | 1,634 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/mips/mach-jz47xx/start.S | // SPDX-License-Identifier: GPL-2.0+
/*
* Startup Code for MIPS32 XBURST CPU-core
*
* Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
*/
#include <config.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
#include <asm/cache.h>
#include <mach/jz4780.h>
... |
4ms/stm32mp1-baremetal | 1,691 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/mips/mach-mscc/lowlevel_init_luton.S | /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2018 Microsemi Corporation
*/
#include <asm/asm.h>
#include <asm/regdef.h>
#define BASE_MACRO 0x600a0000
#define REG_OFFSET(t, o) (t + (o*4))
#define REG_MACRO(x) REG_OFFSET(BASE_MACRO, x)
#define BIT(nr) (1 << (nr))
#define MACRO_CTRL_PLL5... |
4ms/stm32mp1-baremetal | 11,070 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/mips/lib/cache_init.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Cache-handling routined for MIPS CPUs
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
#include... |
4ms/stm32mp1-baremetal | 3,891 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/mips/lib/genex.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 2002, 2007 Maciej W. Rozycki
* Copyright (C) 2001, 2012 MIPS Technologies, Inc. All rights reserved.
*/
#include <asm/asm.h>
#include <asm/regdef.h>
#... |
4ms/stm32mp1-baremetal | 5,261 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/mips/cpu/start.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Startup Code for MIPS32 CPU-core
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#ifndef CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SYS_INIT_SP_ADDR (... |
4ms/stm32mp1-baremetal | 6,107 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/mips/mach-mtmips/lowlevel_init.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* (c) 2018 Stefan Roese <sr@denx.de>
*
* This code is mostly based on the code extracted from this MediaTek
* github repository:
*
* https://github.com/MediaTek-Labs/linkit-smart-uboot.git
*
* I was not able to find a specific license or other developers
* copyrights ... |
4ms/stm32mp1-baremetal | 4,298 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/mips/mach-ath79/qca956x/qca956x-ddr-tap.S | // SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Rosy Song <rosysong@rosinson.com>
*
* Based on QSDK
*/
#include <config.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <mach/ar71xx_regs.h>
.set noreorder
LEAF(ddr_tap_tuning)
li a0, 0... |
4ms/stm32mp1-baremetal | 6,733 | third-party/u-boot/u-boot-stm32mp1-baremetal/arch/mips/mach-ath79/ar933x/lowlevel_init.S | /* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
* Based on Atheros LSDK/QSDK and u-boot_mod project
*/
#include <config.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <mach/ar71xx_regs.h>
#define SE... |
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