repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
0intro/plan9 | 2,342 | sys/src/ape/lib/ap/mips/memmove.s | TEXT memmove(SB), $0
JMP move
TEXT memcpy(SB), $0
move:
MOVW R1, s1+0(FP)
MOVW n+8(FP), R3 /* R3 is count */
MOVW R1, R4 /* R4 is to-pointer */
SGT R0, R3, R5
BEQ R5, ok
MOVW (R0), R0 /* abort if negative count */
ok:
MOVW s2+4(FP), R5 /* R5 is from-pointer */
ADDU R3,R5, R7 /* R7 is end from-pointe... |
0intro/plan9 | 1,678 | sys/src/ape/lib/ap/mips/memcmp.s | TEXT memcmp(SB), $0
MOVW R1, 0(FP)
/*
* performance:
* alligned about 1.0us/call and 17.4mb/sec
* unalligned is about 3.1mb/sec
*/
MOVW n+8(FP), R3 /* R3 is count */
MOVW s1+0(FP), R4 /* R4 is pointer1 */
MOVW s2+4(FP), R5 /* R5 is pointer2 */
ADDU R3,R4, R6 /* R6 is end pointer1 */
/*
* if not at leas... |
0intro/plan9 | 1,202 | sys/src/ape/lib/ap/mips/strcpy.s | TEXT strcpy(SB), $0
MOVW s2+4(FP),R2 /* R2 is from pointer */
MOVW R1, R3 /* R3 is to pointer */
/*
* align 'from' pointer
*/
l1:
AND $3, R2, R5
ADDU $1, R2
BEQ R5, l2
MOVB -1(R2), R5
ADDU $1, R3
MOVB R5, -1(R3)
BNE R5, l1
RET
/*
* test if 'to' is also alligned
*/
l2:
AND $3,R3, R5
BEQ R5, l4
/*
... |
0intro/plan9 | 12,756 | sys/src/9/omap/l.s | /*
* ti omap3530 SoC machine assist
* arm cortex-a8 processor
*
* loader uses R11 as scratch.
* R9 and R10 are used for `extern register' variables.
*
* ARM v7 arch. ref. man. §B1.3.3 that we don't need barriers
* around moves to CPSR.
*/
#include "arm.s"
/*
* MCR and MRC are counter-intuitively named.
* M... |
0intro/plan9 | 4,906 | sys/src/9/omap/cache.v7.s | /*
* cortex arm arch v7 cache flushing and invalidation
* shared by l.s and rebootcode.s
*/
TEXT cacheiinv(SB), $-4 /* I invalidate */
MOVW $0, R0
MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall /* ok on cortex */
ISB
RET
/*
* set/way operators, passed a suitable set/way value in R0.
*/
TEXT cache... |
0intro/plan9 | 1,298 | sys/src/9/omap/lproc.s | #include "mem.h"
#include "arm.h"
/*
* This is the first jump from kernel to user mode.
* Fake a return from interrupt.
*
* Enter with R0 containing the user stack pointer.
* UTZERO + 0x20 is always the entry point.
*
*/
TEXT touser(SB), 1, $-4
/* store the user stack pointer into the USR_r13 */
MOVM.DB.W... |
0intro/plan9 | 2,628 | sys/src/9/omap/arm.s | /*
* omap3530 machine assist, definitions
* cortex-a8 processor
*
* loader uses R11 as scratch.
*/
#include "mem.h"
#include "arm.h"
#undef B /* B is for 'botch' */
#define KADDR(pa) (KZERO | ((pa) & ~KSEGM))
#define PADDR(va) (PHYSDRAM | ((va) & ~KSEGM))
#define L1X(va) (((((va))>>20) & 0x0fff)<<2)
#... |
0intro/plan9 | 5,909 | sys/src/9/omap/lexception.s | /*
* arm exception handlers
*/
#include "arm.s"
#undef B /* B is for 'botch' */
/*
* exception vectors, copied by trapinit() to somewhere useful
*/
TEXT vectors(SB), 1, $-4
MOVW 0x18(R15), R15 /* reset */
MOVW 0x18(R15), R15 /* undefined instr. */
MOVW 0x18(R15), R15 /* SWI & SMC */
MOVW 0x18(R15), R1... |
0intro/plan9 | 4,859 | sys/src/9/omap/rebootcode.s | /*
* omap3530 reboot code
*
* must fit in 11K to avoid stepping on PTEs; see mem.h.
*
* R11 is used by the loader as a temporary, so avoid it.
*/
#include "arm.s"
/*
* Turn off MMU, then copy the new kernel to its correct location
* in physical memory. Then jump to the start of the kernel.
*/
/* main(PADDR(... |
0intro/plan9 | 17,449 | sys/src/9/pcboot/l.s | /*
* non-startup assembly-language assist
*/
#include "mem.h"
#include "/sys/src/boot/pc/x16.h"
#undef DELAY
#define PADDR(a) ((a) & ~KZERO)
#define KADDR(a) (KZERO|(a))
/*
* Some machine instructions not handled by 8[al].
*/
#define OP16 BYTE $0x66
#define DELAY BYTE $0xEB; BYTE $0x00 /* JMP .+2 */
#define CP... |
0intro/plan9 | 4,884 | sys/src/9/pcboot/l16r.s | /*
* Protected-mode bootstrap, to be jumped to by a Primary Bootstrap Sector.
* Load with -H3 -R4 -T0xNNNNNNNN to get a binary image with no header.
* Note that the processor is in 'real' mode on entry, so care must be taken
* as the assembler assumes protected mode, hence the sometimes weird-looking
* code to ass... |
0intro/plan9 | 8,369 | sys/src/9/pcboot/l32v.s | #include "/sys/src/boot/pc/x16.h"
#include "mem.h"
#define KB 1024
#define MB (1024*1024)
#define WRMSR BYTE $0x0F; BYTE $0x30 /* WRMSR, argument in AX/DX (lo/hi) */
#define RDTSC BYTE $0x0F; BYTE $0x31 /* RDTSC, result in AX/DX (lo/hi) */
#define RDMSR BYTE $0x0F; BYTE $0x32 /* RDMSR, result in AX/DX (lo/hi) *... |
0intro/plan9 | 5,701 | sys/src/9/pcboot/ldecomp.s | /*
* Bootstrap loader decompressor. Starts at 0x10000 (where pbs puts it)
* or 0x7c00 (where pxe puts it) and memmoves kernel (immediately following)
* into standard kernel location.
*/
#include "mem.h"
#include "/sys/src/boot/pc/x16.h"
#undef BIOSCALL /* we don't know what evil the bios gets up to */
#define BI... |
0intro/plan9 | 7,084 | sys/src/9/pcboot/realmode0.s | #include "mem.h"
#include "/sys/src/boot/pc/x16.h"
#undef DELAY
#define PADDR(a) ((a) & ~KZERO)
#define KADDR(a) (KZERO|(a))
/*
* Some machine instructions not handled by 8[al].
*/
#define OP16 BYTE $0x66
#define DELAY BYTE $0xEB; BYTE $0x00 /* JMP .+2 */
#define CPUID BYTE $0x0F; BYTE $0xA2 /* CPUID, argument i... |
0intro/plan9 | 6,272 | sys/src/9/pcboot/l32p.s | #include "mem.h"
#define KB 1024
#define MB (1024*1024)
/*
* Some machine instructions not handled by 8[al].
*/
#define DELAY BYTE $0xEB; BYTE $0x00 /* JMP .+2 */
#define FARJUMP(s, o) BYTE $0xEA; /* far jump to ptr32:16 */\
LONG $o; WORD $s
#define NOP BYTE $0x90
#define HLT BYTE $0xF4
/*
* Macro for c... |
0intro/plan9 | 17,538 | sys/src/9/kw/l.s | /*
* sheevaplug machine assist
* arm926ej-s processor at 1.2GHz
*
* loader uses R11 as scratch.
* R9 and R10 are used for `extern register' variables.
*
* ARM v7 arch. ref. man. (I know, this is v5) §B1.3.3 that
* we don't need barriers around moves to CPSR. The ARM v6 manual
* seems to be silent on the subje... |
0intro/plan9 | 1,298 | sys/src/9/kw/lproc.s | #include "mem.h"
#include "arm.h"
/*
* This is the first jump from kernel to user mode.
* Fake a return from interrupt.
*
* Enter with R0 containing the user stack pointer.
* UTZERO + 0x20 is always the entry point.
*
*/
TEXT touser(SB), 1, $-4
/* store the user stack pointer into the USR_r13 */
MOVM.DB.W... |
0intro/plan9 | 1,904 | sys/src/9/kw/arm.s | /*
* sheevaplug machine assist, definitions
* arm926ej-s processor at 1.2GHz
*
* loader uses R11 as scratch.
*/
#include "mem.h"
#include "arm.h"
#undef B /* B is for 'botch' */
#define PADDR(a) ((a) & ~KZERO)
#define KADDR(a) (KZERO|(a))
#define L1X(va) (((((va))>>20) & 0x0fff)<<2)
#define MACHADDR (L1-M... |
0intro/plan9 | 5,909 | sys/src/9/kw/lexception.s | /*
* arm exception handlers
*/
#include "arm.s"
#undef B /* B is for 'botch' */
/*
* exception vectors, copied by trapinit() to somewhere useful
*/
TEXT vectors(SB), 1, $-4
MOVW 0x18(R15), R15 /* reset */
MOVW 0x18(R15), R15 /* undefined instr. */
MOVW 0x18(R15), R15 /* SWI & SMC */
MOVW 0x18(R15), R1... |
0intro/plan9 | 4,052 | sys/src/9/kw/rebootcode.s | /*
* sheevaplug reboot code
*
* R11 is used by the loader as a temporary, so avoid it.
*/
#include "arm.s"
/*
* Turn off MMU, then copy the new kernel to its correct location
* in physical memory. Then jump to the start of the kernel.
*/
/* main(PADDR(entry), PADDR(code), size); */
TEXT main(SB), 1, $-4
MOVW... |
0intro/plan9 | 20,740 | sys/src/9/rb/l.s | /*
* mips 24k machine assist for routerboard rb450g
*/
#include "mem.h"
#include "mips.s"
#define SANITY 0x12345678
NOSCHED
/*
* Boot only processor
*/
TEXT start(SB), $-4
MOVW $setR30(SB), R30
PUTC('9', R1, R2)
DI(0)
MOVW sanity(SB), R1
CONST(SANITY, R2)
SUBU R1, R2, R2
BNE R2, insane
NOP
MOVW R0, M... |
0intro/plan9 | 1,030 | sys/src/9/rb/initreboot.s | /*
* mips 24k machine assist for routerboard rb450g (minimal for reboot)
*/
#include "mem.h"
#include "mips.s"
NOSCHED
TEXT _main(SB), $0
MOVW $setR30(SB), R30
JMP main(SB)
/* target for JALRHB in BARRIERS */
TEXT ret(SB), $-4
JMP (R22)
NOP
TEXT setsp(SB), $-4
MOVW R1, SP
RETURN
TEXT coherence(SB), $-4
B... |
0intro/plan9 | 2,589 | sys/src/9/rb/mips.s | /*
* mips 24k machine assist
*/
#undef MASK
#define MASK(w) ((1<<(w))-1)
#define SP R29
#define NOP NOR R0, R0, R0
#define CONST(x,r) MOVW $((x)&0xffff0000), r; OR $((x)&0xffff), r
/* a mips 24k erratum requires a NOP after; experience dictates EHB before */
#define ERET EHB; WORD $0x42000018; NOP
#define RETUR... |
0intro/plan9 | 18,757 | sys/src/9/teg2/l.s | /*
* tegra 2 SoC machine assist
* dual arm cortex-a9 processors
*
* ARM v7 arch. ref. man. §B1.3.3 says that we don't need barriers
* around writes to CPSR.
*
* LDREX/STREX use an exclusive monitor, which is part of the data cache unit
* for the L1 cache, so they won't work right if the L1 cache is disabled.
*... |
0intro/plan9 | 5,687 | sys/src/9/teg2/cache.v7.s | /*
* cortex arm arch v7 cache flushing and invalidation
* included by l.s and rebootcode.s
*/
TEXT cacheiinv(SB), $-4 /* I invalidate */
MOVW $0, R0
MTCP CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall /* ok on cortex */
ISB
RET
/*
* set/way operators, passed a suitable set/way value in R0.
*/
TEXT ca... |
0intro/plan9 | 4,084 | sys/src/9/teg2/arm.s | /*
* nvidia tegra 2 machine assist, definitions
* dual-core cortex-a9 processor
*
* R9 and R10 are used for `extern register' variables.
* R11 is used by the loader as a temporary, so avoid it.
*/
#include "mem.h"
#include "arm.h"
#undef B /* B is for 'botch' */
#define KADDR(pa) (KZERO | ((pa) & ~KSEGM... |
0intro/plan9 | 8,905 | sys/src/9/teg2/lexception.s | /*
* arm exception handlers
*/
#include "arm.s"
#undef B /* B is for 'botch' */
/*
* exception vectors, copied by trapinit() to somewhere useful
*/
TEXT vectors(SB), 1, $-4
MOVW 0x18(R15), R15 /* reset */
MOVW 0x18(R15), R15 /* undefined instr. */
MOVW 0x18(R15), R15 /* SWI & SMC */
MOVW 0x18(R15), R1... |
0intro/plan9 | 4,750 | sys/src/9/teg2/rebootcode.s | /*
* arm v7 reboot code
*
* must fit in 11K to avoid stepping on PTEs; see mem.h.
* cache parameters are at CACHECONF.
*/
#include "arm.s"
/*
* All caches but L1 should be off before calling this.
* Turn off MMU, then copy the new kernel to its correct location
* in physical memory. Then jump to the start of ... |
0intro/plan9 | 20,641 | sys/src/9/ppc/l.s | #include "mem.h"
/* use of SPRG registers in save/restore */
#define SAVER0 SPRG0
#define SAVER1 SPRG1
#define SAVELR SPRG2
#define SAVEXX SPRG3
#ifdef ucuconf
/* These only exist on the PPC 755: */
#define SAVER4 SPRG4
#define SAVER5 SPRG5
#define SAVER6 SPRG6
#define SAVER7 SPRG7
#endif /* ucuconf */
/* special in... |
0intro/9legacy | 4,949 | sys/src/nboot/zynq/ddr.s | #define OUTPUT_EN (3<<9)
#define DCI_EN (7<<4)
#define INP_VREF (1<<1)
#define INP_DIFF (2<<1)
TEXT ddriob(SB), $-4
WORD $(OUTPUT_EN) // DDRIOB_ADDR0
WORD $(OUTPUT_EN) // DDRIOB_ADDR1
WORD $(OUTPUT_EN | DCI_EN | INP_VREF) // DDRIOB_DATA0
WORD $(OUTPUT_EN | DCI_EN | INP_VREF) // DDRIOB_DATA1
WORD $(OUTPUT_EN | DCI... |
0intro/9legacy | 6,004 | sys/src/nboot/zynq/fsbl.s | #include "mem.h"
#define Rb R10
#define SET(R, V) MOVW $(V), R0 ; MOVW R0, (R)(Rb)
#define RMW(r, m, v) MOVW (r)(Rb), R0; BIC $(m), R0; ORR $(v), R0; MOVW R0, (r)(Rb)
TEXT _start(SB), $-4
WORD $0xea000006
MOVW $abort(SB), R15
MOVW $abort(SB), R15
MOVW $abort(SB), R15
MOVW $abort(SB), R15
MOVW $abort(SB), R15
M... |
0intro/9legacy | 5,567 | sys/src/nboot/efi/pe64.s | TEXT mzhdr(SB), 1, $0
BYTE $'M'; BYTE $'Z'
WORD $0 /* e_cblp UNUSED */
WORD $0 /* e_cp UNUSED */
WORD $0 /* e_crlc UNUSED */
WORD $0 /* e_cparhdr UNUSED */
WORD $0 /* e_minalloc UNUSED */
WORD $0 /* e_maxalloc UNUSED */
WORD $0 /* e_ss UNUSED */
WORD $0 /* e_sp UNUSED */
WORD $0 /* e_csum UNUSED */
... |
0intro/9legacy | 4,225 | sys/src/nboot/efi/pe32.s | TEXT mzhdr(SB), 1, $0
BYTE $'M'; BYTE $'Z'
WORD $0 /* e_cblp UNUSED */
WORD $0 /* e_cp UNUSED */
WORD $0 /* e_crlc UNUSED */
WORD $0 /* e_cparhdr UNUSED */
WORD $0 /* e_minalloc UNUSED */
WORD $0 /* e_maxalloc UNUSED */
WORD $0 /* e_ss UNUSED */
WORD $0 /* e_sp UNUSED */
WORD $0 /* e_csum UNUSED */
... |
0intro/9legacy | 10,805 | sys/src/nboot/bitsy/l.s | #include "mem.h"
/*
* Entered here from Compaq's bootldr with MMU disabled.
*/
TEXT _start(SB), $-4
MOVW $setR12(SB), R12 /* load the SB */
_main:
/* SVC mode, interrupts disabled */
MOVW $(PsrDirq|PsrDfiq|PsrMsvc), R1
MOVW R1, CPSR
/* disable the MMU */
MOVW $0x130, R1
MCR CpMMU, 0, R1, C(CpControl), C... |
0intro/9legacy | 2,185 | sys/src/nboot/bitsy/il.s | #include "mem.h"
/*
* Entered here from Compaq's bootldr. First relocate to
* the location we're linked for and then copy back the
* decompressed kernel.
*
* All
*/
TEXT _start(SB), $-4
MOVW $setR12(SB), R12 /* load the SB */
MOVW $1, R0 /* dance to make 5l think that the magic */
MOVW $1, R1 /* numbe... |
0intro/9legacy | 4,746 | sys/src/nboot/pc/l.s | #include "x16.h"
#include "mem.h"
#undef ORB
#define DATA32SEL SELECTOR(1, SELGDT, 0)
#define EXEC32SEL SELECTOR(2, SELGDT, 0)
#define DATA16SEL SELECTOR(3, SELGDT, 0)
#define EXEC16SEL SELECTOR(4, SELGDT, 0)
#define SEGSS BYTE $0x36
#define SEGES BYTE $0x26
#define FARRET BYTE $0xCB
TEXT origin(SB), $0
CLI
CLR(r... |
0intro/9legacy | 6,234 | sys/src/nboot/pc/mbr.s | /*
* Hard disc boot block. Loaded at 0x7C00, relocates to 0x0600:
* 8a mbr.s; 8l -o mbr -l -H3 -T0x0600 mbr.8
*/
#include "x16.h"
#include "mem.h"
/*#define FLOPPY 1 /* test on a floppy */
#define TRACE(C) PUSHA;\
CLR(rBX);\
MOVB $C, AL;\
LBI(0x0E, rAH);\
BIOSCALL(0x10);\
POPA
/*
* We keep data on... |
0intro/9legacy | 5,272 | sys/src/nboot/pc/pbs.s | #include "x16.h"
#include "mem.h"
#define RELOC 0x7c00
TEXT _magic(SB), $0
BYTE $0xEB; BYTE $0x58; /* jmp .+ 0x58 (_start0x5A) */
BYTE $0x90 /* nop */
TEXT _version(SB), $0
BYTE $0x00; BYTE $0x00; BYTE $0x00; BYTE $0x00;
BYTE $0x00; BYTE $0x00; BYTE $0x00; BYTE $0x00
TEXT _sectsize(SB), $0
BYTE $0x00; BYTE $... |
0intro/9legacy | 1,092 | sys/src/nboot/pc/a20.s | #include "x16.h"
#undef ORB
TEXT a20test(SB), $0
LONG $1234567
TEXT a20check(SB), $0
MOVL $10000, CX
_loop:
LEAL a20test(SB), AX
MOVL (AX), BX
ADDL $12345, BX
MOVL BX, (AX)
ORL $(1<<20), AX
MOVL (AX), AX
CMPL AX, BX
JNZ _done
LOOP _loop
RET
_done:
/* return directly to caller of a20() */
ADDL $4, SP
X... |
0intro/plan9 | 11,000 | sys/src/9/mtx/l.s | #include "mem.h"
/* use of SPRG registers in save/restore */
#define SAVER0 SPRG0
#define SAVER1 SPRG1
#define SAVELR SPRG2
#define SAVEXX SPRG3
/* special instruction definitions */
#define BDNZ BC 16,0,
#define BDNE BC 0,2,
#define TLBIA WORD $((31<<26)|(307<<1))
#define TLBSYNC WORD $((31<<26)|(566<<1))
/* on so... |
0intro/plan9 | 1,476 | sys/src/9/mtx/inb.s | #include "mem.h"
#define BDNZ BC 16,0,
#define BDNE BC 0,2,
TEXT inb(SB), $0
OR $IOMEM, R3
MOVBZ (R3), R3
RETURN
TEXT insb(SB), $0
MOVW v+4(FP), R4
MOVW n+8(FP), R5
MOVW R5, CTR
OR $IOMEM, R3
SUB $1, R4
insb1:
MOVBZ (R3), R7
MOVBU R7, 1(R4)
BDNZ insb1
RETURN
TEXT outb(SB), $0
MOVW v+4(FP), R4
OR $IOME... |
0intro/plan9 | 1,493 | sys/src/9/pc/ptclbsum386.s | TEXT ptclbsum(SB), $0
MOVL addr+0(FP), SI
MOVL len+4(FP), CX
XORL AX, AX /* sum */
TESTL $1, SI /* byte aligned? */
MOVL SI, DI
JEQ _2align
DECL CX
JLT _return
MOVB 0x00(SI), AH
INCL SI
_2align:
TESTL $2, SI /* word aligned? */
JEQ _32loop
CMPL CX, $2 /* less than 2 bytes? */
JLT _1dreg
SUB... |
0intro/plan9 | 1,527 | sys/src/9/pc/apmjump.s | /*
* Far call, absolute indirect.
* The argument is the offset.
* We use a global structure for the jump params,
* so this is *not* reentrant or thread safe.
*/
#include "mem.h"
#define SSOVERRIDE BYTE $0x36
#define CSOVERRIDE BYTE $0x2E
#define RETF BYTE $0xCB
GLOBL apmjumpstruct+0(SB), $8
TEXT fortytwo(SB),... |
0intro/plan9 | 30,391 | sys/src/9/pc/l.s | #include "mem.h"
#include "/sys/src/boot/pc/x16.h"
#undef DELAY
#define PADDR(a) ((a) & ~KZERO)
#define KADDR(a) (KZERO|(a))
/*
* Some machine instructions not handled by 8[al].
*/
#define OP16 BYTE $0x66
#define DELAY BYTE $0xEB; BYTE $0x00 /* JMP .+2 */
#define CPUID BYTE $0x0F; BYTE $0xA2 /* CPUID, argument i... |
0intro/plan9 | 3,037 | sys/src/9/pc/apbootstrap.s | /*
* Start an Application Processor. This must be placed on a 4KB boundary
* somewhere in the 1st MB of conventional memory (APBOOTSTRAP). However,
* due to some shortcuts below it's restricted further to within the 1st
* 64KB. The AP starts in real-mode, with
* CS selector set to the startup memory address/16;
... |
0intro/9legacy | 1,085 | sys/src/ape/lib/ap/power/atom.s | TEXT _xinc(SB),$0 /* void _xinc(long *); */
TEXT ainc(SB),$0 /* long ainc(long *); */
MOVW R3, R4
xincloop:
LWAR (R4), R3
ADD $1, R3
DCBT (R4) /* fix 405 errata cpu_210 */
STWCCC R3, (R4)
BNE xincloop
RETURN
TEXT _xdec(SB),$0 /* long _xdec(long *); */
TEXT adec(SB),$0 /* long adec(long *); */
MOVW R3, R4
xd... |
0intro/9legacy | 1,211 | sys/src/ape/lib/ap/power/memset.s | TEXT memset(SB),$0
#define BDNZ BC 16,0,
MOVW R3, p+0(FP) /* R3 is pointer */
/*
* performance:
* about 100mbytes/sec (8k blocks) on a 603/105 without L2 cache
* drops to 40mbytes/sec (10k blocks) and 28mbytes/sec with 32k blocks
*/
MOVW n+8(FP), R4 /* R4 is count */
CMP R4, $0
BLE ret
MOVW c+4(FP), R5 /... |
0intro/9legacy | 2,479 | sys/src/ape/lib/ap/power/memmove.s | #define BDNZ BC 16,0,
TEXT memmove(SB), $0
BR move
TEXT memcpy(SB), $0
move:
/*
* performance:
* (tba)
*/
MOVW R3, s1+0(FP)
MOVW n+8(FP), R9 /* R9 is count */
MOVW R3, R10 /* R10 is to-pointer */
CMP R9, $0
BEQ ret
BLT trap
MOVW s2+4(FP), R11 /* R11 is from-pointer */
/*
* if no more than 16 bytes... |
0intro/9legacy | 1,493 | sys/src/ape/lib/ap/power/memcmp.s | TEXT memcmp(SB), $0
#define BDNZ BC 16,0,
MOVW R3, s1+0(FP) /* R3 is pointer1 */
/*
* performance:
* 67mb/sec aligned; 16mb/sec unaligned
*/
MOVW n+8(FP), R4 /* R4 is count */
MOVW s2+4(FP), R5 /* R5 is pointer2 */
/*
* let LSW do the work for 4 characters or less; aligned and unaligned
*/
CMP R4, $0
B... |
0intro/9legacy | 3,748 | sys/src/ape/lib/ap/power/vlop.s | #define BDNZ BC 16,0,
/*
* 64/64 division adapted from powerpc compiler writer's handbook
*
* (R3:R4) = (R3:R4) / (R5:R6) (64b) = (64b / 64b)
* quo dvd dvs
*
* Remainder is left in R7:R8
*
* Code comment notation:
* msw = most-significant (high-order) word, i.e. bits 0..31
* lsw = least-significant (low-orde... |
0intro/9legacy | 2,877 | sys/src/ape/lib/ap/386/atom.s | TEXT ainc(SB), 1, $-4 /* int ainc(int*); */
MOVL arg+0(FP), BX
MOVL $1, AX
LOCK; BYTE $0x0f; BYTE $0xc1; BYTE $0x03/* XADDL AX, (BX) */
ADDL $1, AX /* overflow if -ve or 0 */
RET
TEXT adec(SB), 1, $-4 /* int adec(int*); */
MOVL arg+0(FP), BX
MOVL $-1, AX
LOCK; BYTE $0x0f; BYTE $0xc1; BYTE $0x03/* XADD... |
0intro/9legacy | 1,282 | sys/src/ape/lib/ap/sparc/memset.s | TEXT memset(SB),$0
/*
* performance:
* (tba)
*/
MOVW R7, 0(FP)
MOVW n+8(FP), R9 /* R9 is count */
MOVW p+0(FP), R10 /* R10 is pointer */
MOVW c+4(FP), R11 /* R11 is char */
ADD R9,R10, R12 /* R12 is end pointer */
/*
* if not at least 4 chars,
* dont even mess around.
* 3 chars to guarantee any
* rou... |
0intro/9legacy | 2,430 | sys/src/ape/lib/ap/sparc/memmove.s | TEXT memmove(SB), $0
JMP move
TEXT memcpy(SB), $0
move:
/*
* performance:
* (tba)
*/
MOVW R7, s1+0(FP)
MOVW n+8(FP), R9 /* R9 is count */
MOVW R7, R10 /* R10 is to-pointer */
SUBCC R0,R9, R0
BGE ok
MOVW 0(R0), R0
ok:
MOVW s2+4(FP), R11 /* R11 is from-pointer */
ADD R9,R11, R13 /* R13 is end from-... |
0intro/9legacy | 1,715 | sys/src/ape/lib/ap/sparc/memcmp.s | #define Bxx BE
TEXT memcmp(SB), $0
/*
* performance:
* (tba)
*/
MOVW R7, 0(FP)
MOVW n+8(FP), R9 /* R9 is count */
MOVW s1+0(FP), R10 /* R10 is pointer1 */
MOVW s2+4(FP), R11 /* R11 is pointer2 */
ADD R9,R10, R12 /* R12 is end pointer1 */
/*
* if not at least 4 chars,
* dont even mess around.
* 3 char... |
0intro/9legacy | 1,115 | sys/src/ape/lib/ap/sparc/strcpy.s | TEXT strcpy(SB), $0
MOVW R7, 0(FP)
MOVW s1+0(FP), R9 /* R9 is to pointer */
MOVW s2+4(FP), R10 /* R10 is from pointer */
/*
* test if both pointers
* are similarly word aligned
*/
XOR R9,R10, R7
ANDCC $3,R7, R0
BNE una
/*
* make byte masks
*/
MOVW $0xff, R17
SLL $8,R17, R16
SLL $16,R17, R13
SLL $24,... |
0intro/9legacy | 5,379 | sys/src/ape/lib/ap/sparc/muldiv.s | /*
* ulong
* _udiv(ulong num, ulong den)
* {
* int i;
* ulong quo;
*
* if(den == 0)
* *(ulong*)-1 = 0;
* quo = num;
* if(quo > 1<<(32-1))
* quo = 1<<(32-1);
* for(i=0; den<quo; i++)
* den <<= 1;
* quo = 0;
* for(; i>=0; i--) {
* quo <<= 1;
* if(num >= den) {
* num -= den;
* qu... |
0intro/9legacy | 2,423 | sys/src/ape/lib/ap/sparc/vlop.s | TEXT _mulv(SB), $0
MOVW u1+8(FP), R8
MOVW u2+16(FP), R13
MOVW R13, R16 /* save low parts for later */
MOVW R8, R12
/*
* unsigned 32x32 => 64 multiply
*/
CMP R13, R8
BLE mul1
MOVW R12, R13
MOVW R16, R8
mul1:
MOVW R13, Y
ANDNCC $0xFFF, R13, R0
BE mul_shortway
ANDCC R0, R0, R9 /* zero partial product ... |
0intro/9legacy | 1,551 | sys/src/ape/lib/ap/riscv64/atom.s | /*
* RISC-V atomic operations
* assumes A extension
*/
#define LINK R1
#define SP R2
#define ARG 8
#define SYNC WORD $0xf /* FENCE */
#define LRW(rs2, rs1, rd) \
WORD $((2<<27)|( 0<<20)|((rs1)<<15)|(2<<12)|((rd)<<7)|057)
#define SCW(rs2, rs1, rd) \
WORD $((3<<27)|((rs2)<<20)|((rs1)<<15)|(2<<12)|((rd)<<7)|057)... |
0intro/9legacy | 1,558 | sys/src/ape/lib/ap/riscv/atom.s | /*
* RISC-V atomic operations
* assumes A extension
*/
#define LINK R1
#define SP R2
#define ARG 8
#define SYNC WORD $0xf /* FENCE */
#define LRW(rs2, rs1, rd) \
WORD $((2<<27)|( 0<<20)|((rs1)<<15)|(2<<12)|((rd)<<7)|057)
#define SCW(rs2, rs1, rd) \
WORD $((3<<27)|((rs2)<<20)|((rs1)<<15)|(2<<12)|((rd)<<7)|057)... |
0intro/9legacy | 1,258 | sys/src/ape/lib/ap/riscv/memset.s | TEXT memset(SB),$12
MOVW R8, s1+0(FP)
MOVW n+8(FP), R10 /* R10 is count */
MOVW p+0(FP), R11 /* R11 is pointer */
MOVW c+4(FP), R12 /* R12 is char */
ADD R10,R11, R13 /* R13 is end pointer */
/*
* if not at least 4 chars,
* dont even mess around.
* 3 chars to guarantee any
* rounding up to a word
* boun... |
0intro/9legacy | 1,888 | sys/src/ape/lib/ap/riscv/memmove.s |
TEXT memcpy(SB), $-4
TEXT memmove(SB), $-4
MOVW R8, s1+0(FP)
MOVW n+8(FP), R9 /* count */
BEQ R9, return
BGT R9, ok
MOVW $0, R9
ok:
MOVW s1+0(FP), R11 /* dest pointer */
MOVW s2+4(FP), R10 /* source pointer */
BLTU R11, R10, back
/*
* byte-at-a-time forward copy to
* get source (R10) aligned.
*/
f1:
A... |
0intro/9legacy | 1,250 | sys/src/ape/lib/ap/riscv/strcpy.s | TEXT strcpy(SB), $0
MOVW s2+4(FP),R9 /* R9 is from pointer */
MOVW R8, R10 /* R10 is to pointer */
/*
* align 'from' pointer
*/
l1:
AND $3, R9, R12
ADD $1, R9
BEQ R12, l2
MOVB -1(R9), R12
ADD $1, R10
MOVB R12, -1(R10)
BNE R12, l1
RET
/*
* test if 'to' is also aligned
*/
l2:
AND $3,R10, R12
BEQ R12... |
0intro/9legacy | 1,401 | sys/src/ape/lib/ap/arm/atom.s | #define DMB MCR 15, 0, R0, C7, C10, 5
#define CLREX WORD $0xf57ff01f
#define LDREX(a,r) WORD $(0xe<<28|0x01900f9f | (a)<<16 | (r)<<12)
/* `The order of operands is from left to right in dataflow order' - asm man */
#define STREX(v,a,r) WORD $(0xe<<28|0x01800f90 | (a)<<16 | (r)<<12 | (v)<<0)
/*
* int cas(ulong *p, ul... |
0intro/9legacy | 4,198 | sys/src/ape/lib/ap/arm/memmove.s | TS = 0
TE = 1
FROM = 2
N = 3
TMP = 3 /* N and TMP don't overlap */
TMP1 = 4
TEXT memcpy(SB), $-4
B _memmove
TEXT memmove(SB), $-4
_memmove:
MOVW R(TS), to+0(FP) /* need to save for return value */
MOVW from+4(FP), R(FROM)
MOVW n+8(FP), R(N)
ADD R(N), R(TS), R(TE) /* to end pointer */
CMP R(FROM), R(TS)
B... |
0intro/9legacy | 1,639 | sys/src/ape/lib/ap/arm/div.s | Q = 0
N = 1
D = 2
CC = 3
TMP = 11
TEXT save<>(SB), 1, $0
MOVW R(Q), 0(FP)
MOVW R(N), 4(FP)
MOVW R(D), 8(FP)
MOVW R(CC), 12(FP)
MOVW R(TMP), R(Q) /* numerator */
MOVW 20(FP), R(D) /* denominator */
CMP $0, R(D)
BNE s1
MOVW -1(R(D)), R(TMP) /* divide by zero fault */
s1: RET
TEXT rest<>(SB), 1, $0
MOVW 0(F... |
0intro/9legacy | 1,278 | sys/src/ape/lib/ap/spim64/memset.s | TEXT memset(SB), $0
MOVV R1, 0(FP)
/*
* performance:
* about 1us/call and 28mb/sec
*/
MOVW n+16(FP), R3 /* R3 is count */
MOVV p+0(FP), R4 /* R4 is pointer */
MOVW c+8(FP), R5 /* R5 is char */
ADDVU R3,R4, R6 /* R6 is end pointer */
/*
* if not at least 4 chars,
* dont even mess around.
* 3 chars to g... |
0intro/9legacy | 3,515 | sys/src/ape/lib/ap/spim64/memmove.s | TEXT memmove(SB), $0
JMP move
TEXT memcpy(SB), $0
move:
MOVV R1, s1+0(FP)
MOVW n+16(FP), R3 /* R3 is count */
MOVV R1, R4 /* R4 is to-pointer */
SGT R0, R3, R5
BEQ R5, ok
MOVW (R0), R0 /* abort if negative count */
ok:
MOVV s2+8(FP), R5 /* R5 is from-pointer */
ADDVU R3,R5, R7 /* R7 is end from-point... |
0intro/9legacy | 1,151 | sys/src/ape/lib/ap/spim64/strcpy.s | TEXT strcpy(SB), $0
MOVV s2+8(FP),R2 /* R2 is from pointer */
MOVV R1, R3 /* R3 is to pointer */
/*
* align 'from' pointer
*/
l1:
AND $3, R2, R5
ADDVU $1, R2
BEQ R5, l2
MOVB -1(R2), R5
ADDVU $1, R3
MOVB R5, -1(R3)
BNE R5, l1
RET
/*
* test if 'to' is also alligned
*/
l2:
AND $3,R3, R5
BEQ R5, l4
/... |
0intro/9legacy | 1,102 | sys/src/ape/lib/ap/amd64/atom.s | TEXT ainc(SB), 1, $0 /* long ainc(long *); */
ainclp:
MOVL (RARG), AX /* exp */
MOVL AX, BX
INCL BX /* new */
LOCK; CMPXCHGL BX, (RARG)
JNZ ainclp
MOVL BX, AX
RET
TEXT adec(SB), 1, $0 /* long adec(long*); */
adeclp:
MOVL (RARG), AX
MOVL AX, BX
DECL BX
LOCK; CMPXCHGL BX, (RARG)
JNZ adeclp
MOVL BX, AX
RET... |
0intro/9legacy | 1,270 | sys/src/ape/lib/ap/spim/memset.s | TEXT memset(SB),$12
MOVW R1, 0(FP)
/*
* performance:
* about 1us/call and 28mb/sec
*/
MOVW n+8(FP), R3 /* R3 is count */
MOVW p+0(FP), R4 /* R4 is pointer */
MOVW c+4(FP), R5 /* R5 is char */
ADDU R3,R4, R6 /* R6 is end pointer */
/*
* if not at least 4 chars,
* dont even mess around.
* 3 chars to gua... |
0intro/9legacy | 2,342 | sys/src/ape/lib/ap/spim/memmove.s | TEXT memmove(SB), $0
JMP move
TEXT memcpy(SB), $0
move:
MOVW R1, s1+0(FP)
MOVW n+8(FP), R3 /* R3 is count */
MOVW R1, R4 /* R4 is to-pointer */
SGT R0, R3, R5
BEQ R5, ok
MOVW (R0), R0 /* abort if negative count */
ok:
MOVW s2+4(FP), R5 /* R5 is from-pointer */
ADDU R3,R5, R7 /* R7 is end from-pointe... |
0intro/9legacy | 1,710 | sys/src/ape/lib/ap/spim/memcmp.s | TEXT memcmp(SB), $0
MOVW R1, 0(FP)
/*
* performance:
* alligned about 1.0us/call and 17.4mb/sec
* unalligned is about 3.1mb/sec
*/
MOVW n+8(FP), R3 /* R3 is count */
MOVW s1+0(FP), R4 /* R4 is pointer1 */
MOVW s2+4(FP), R5 /* R5 is pointer2 */
ADDU R3,R4, R6 /* R6 is end pointer1 */
JMP out // XXX lit... |
0intro/9legacy | 1,143 | sys/src/ape/lib/ap/spim/strcpy.s | TEXT strcpy(SB), $0
MOVW s2+4(FP),R2 /* R2 is from pointer */
MOVW R1, R3 /* R3 is to pointer */
/*
* align 'from' pointer
*/
l1:
AND $3, R2, R5
ADDU $1, R2
BEQ R5, l2
MOVB -1(R2), R5
ADDU $1, R3
MOVB R5, -1(R3)
BNE R5, l1
RET
/*
* test if 'to' is also alligned
*/
l2:
AND $3,R3, R5
BEQ R5, l4
/*
... |
0intro/plan9 | 5,329 | sys/src/9/bcm/l.s | /*
* Broadcom bcm2835 SoC, as used in Raspberry Pi
* arm1176jzf-s processor (armv6)
*/
#include "arm.s"
TEXT _start(SB), 1, $-4
/*
* load physical base for SB addressing while mmu is off
* keep a handy zero in R0 until first function call
*/
MOVW $setR12(SB), R12
SUB $KZERO, R12
ADD $PHYSDRAM, R12
MOVW ... |
0intro/plan9 | 6,276 | sys/src/9/bcm/lexception.s | /*
* arm exception handlers
*/
#include "arm.s"
/*
* exception vectors, copied by trapinit() to somewhere useful
*/
TEXT vectors(SB), 1, $-4
MOVW 0x18(R15), R15 /* reset */
MOVW 0x18(R15), R15 /* undefined instr. */
MOVW 0x18(R15), R15 /* SWI & SMC */
MOVW 0x18(R15), R15 /* prefetch abort */
MOVW 0x18(R1... |
0intro/9legacy | 1,270 | sys/src/ape/lib/ap/mips/memset.s | TEXT memset(SB),$12
MOVW R1, 0(FP)
/*
* performance:
* about 1us/call and 28mb/sec
*/
MOVW n+8(FP), R3 /* R3 is count */
MOVW p+0(FP), R4 /* R4 is pointer */
MOVW c+4(FP), R5 /* R5 is char */
ADDU R3,R4, R6 /* R6 is end pointer */
/*
* if not at least 4 chars,
* dont even mess around.
* 3 chars to gua... |
0intro/9legacy | 2,342 | sys/src/ape/lib/ap/mips/memmove.s | TEXT memmove(SB), $0
JMP move
TEXT memcpy(SB), $0
move:
MOVW R1, s1+0(FP)
MOVW n+8(FP), R3 /* R3 is count */
MOVW R1, R4 /* R4 is to-pointer */
SGT R0, R3, R5
BEQ R5, ok
MOVW (R0), R0 /* abort if negative count */
ok:
MOVW s2+4(FP), R5 /* R5 is from-pointer */
ADDU R3,R5, R7 /* R7 is end from-pointe... |
0intro/9legacy | 1,678 | sys/src/ape/lib/ap/mips/memcmp.s | TEXT memcmp(SB), $0
MOVW R1, 0(FP)
/*
* performance:
* alligned about 1.0us/call and 17.4mb/sec
* unalligned is about 3.1mb/sec
*/
MOVW n+8(FP), R3 /* R3 is count */
MOVW s1+0(FP), R4 /* R4 is pointer1 */
MOVW s2+4(FP), R5 /* R5 is pointer2 */
ADDU R3,R4, R6 /* R6 is end pointer1 */
/*
* if not at leas... |
0intro/9legacy | 1,202 | sys/src/ape/lib/ap/mips/strcpy.s | TEXT strcpy(SB), $0
MOVW s2+4(FP),R2 /* R2 is from pointer */
MOVW R1, R3 /* R3 is to pointer */
/*
* align 'from' pointer
*/
l1:
AND $3, R2, R5
ADDU $1, R2
BEQ R5, l2
MOVB -1(R2), R5
ADDU $1, R3
MOVB R5, -1(R3)
BNE R5, l1
RET
/*
* test if 'to' is also alligned
*/
l2:
AND $3,R3, R5
BEQ R5, l4
/*
... |
0intro/plan9 | 2,516 | sys/src/9/bcm/rebootcode.s | /*
* armv6 reboot code
*/
#include "arm.s"
/*
* Turn off MMU, then copy the new kernel to its correct location
* in physical memory. Then jump to the start of the kernel.
*/
/* main(PADDR(entry), PADDR(code), size); */
TEXT main(SB), 1, $-4
MOVW $setR12(SB), R12
/* copy in arguments before stack gets unmappe... |
0intro/9legacy | 12,756 | sys/src/9/omap/l.s | /*
* ti omap3530 SoC machine assist
* arm cortex-a8 processor
*
* loader uses R11 as scratch.
* R9 and R10 are used for `extern register' variables.
*
* ARM v7 arch. ref. man. §B1.3.3 that we don't need barriers
* around moves to CPSR.
*/
#include "arm.s"
/*
* MCR and MRC are counter-intuitively named.
* M... |
0intro/9legacy | 4,906 | sys/src/9/omap/cache.v7.s | /*
* cortex arm arch v7 cache flushing and invalidation
* shared by l.s and rebootcode.s
*/
TEXT cacheiinv(SB), $-4 /* I invalidate */
MOVW $0, R0
MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall /* ok on cortex */
ISB
RET
/*
* set/way operators, passed a suitable set/way value in R0.
*/
TEXT cache... |
0intro/9legacy | 1,298 | sys/src/9/omap/lproc.s | #include "mem.h"
#include "arm.h"
/*
* This is the first jump from kernel to user mode.
* Fake a return from interrupt.
*
* Enter with R0 containing the user stack pointer.
* UTZERO + 0x20 is always the entry point.
*
*/
TEXT touser(SB), 1, $-4
/* store the user stack pointer into the USR_r13 */
MOVM.DB.W... |
0intro/plan9 | 1,130 | sys/src/libc/power/atom.s | TEXT ainc(SB),$0 /* long ainc(long *); */
MOVW R3, R4
xincloop:
LWAR (R4), R3
ADD $1, R3
DCBT (R4) /* fix 405 errata cpu_210 */
STWCCC R3, (R4)
BNE xincloop
RETURN
TEXT adec(SB),$0 /* long adec(long *); */
MOVW R3, R4
xdecloop:
LWAR (R4), R3
ADD $-1, R3
DCBT (R4) /* fix 405 errata cpu_210 */
STWCCC R... |
0intro/9legacy | 2,628 | sys/src/9/omap/arm.s | /*
* omap3530 machine assist, definitions
* cortex-a8 processor
*
* loader uses R11 as scratch.
*/
#include "mem.h"
#include "arm.h"
#undef B /* B is for 'botch' */
#define KADDR(pa) (KZERO | ((pa) & ~KSEGM))
#define PADDR(va) (PHYSDRAM | ((va) & ~KSEGM))
#define L1X(va) (((((va))>>20) & 0x0fff)<<2)
#... |
0intro/plan9 | 1,211 | sys/src/libc/power/memset.s | TEXT memset(SB),$0
#define BDNZ BC 16,0,
MOVW R3, p+0(FP) /* R3 is pointer */
/*
* performance:
* about 100mbytes/sec (8k blocks) on a 603/105 without L2 cache
* drops to 40mbytes/sec (10k blocks) and 28mbytes/sec with 32k blocks
*/
MOVW n+8(FP), R4 /* R4 is count */
CMP R4, $0
BLE ret
MOVW c+4(FP), R5 /... |
0intro/plan9 | 2,479 | sys/src/libc/power/memmove.s | #define BDNZ BC 16,0,
TEXT memmove(SB), $0
BR move
TEXT memcpy(SB), $0
move:
/*
* performance:
* (tba)
*/
MOVW R3, s1+0(FP)
MOVW n+8(FP), R9 /* R9 is count */
MOVW R3, R10 /* R10 is to-pointer */
CMP R9, $0
BEQ ret
BLT trap
MOVW s2+4(FP), R11 /* R11 is from-pointer */
/*
* if no more than 16 bytes... |
0intro/plan9 | 1,493 | sys/src/libc/power/memcmp.s | TEXT memcmp(SB), $0
#define BDNZ BC 16,0,
MOVW R3, s1+0(FP) /* R3 is pointer1 */
/*
* performance:
* 67mb/sec aligned; 16mb/sec unaligned
*/
MOVW n+8(FP), R4 /* R4 is count */
MOVW s2+4(FP), R5 /* R5 is pointer2 */
/*
* let LSW do the work for 4 characters or less; aligned and unaligned
*/
CMP R4, $0
B... |
0intro/9legacy | 5,909 | sys/src/9/omap/lexception.s | /*
* arm exception handlers
*/
#include "arm.s"
#undef B /* B is for 'botch' */
/*
* exception vectors, copied by trapinit() to somewhere useful
*/
TEXT vectors(SB), 1, $-4
MOVW 0x18(R15), R15 /* reset */
MOVW 0x18(R15), R15 /* undefined instr. */
MOVW 0x18(R15), R15 /* SWI & SMC */
MOVW 0x18(R15), R1... |
0intro/plan9 | 3,748 | sys/src/libc/power/vlop.s | #define BDNZ BC 16,0,
/*
* 64/64 division adapted from powerpc compiler writer's handbook
*
* (R3:R4) = (R3:R4) / (R5:R6) (64b) = (64b / 64b)
* quo dvd dvs
*
* Remainder is left in R7:R8
*
* Code comment notation:
* msw = most-significant (high-order) word, i.e. bits 0..31
* lsw = least-significant (low-orde... |
0intro/9legacy | 4,859 | sys/src/9/omap/rebootcode.s | /*
* omap3530 reboot code
*
* must fit in 11K to avoid stepping on PTEs; see mem.h.
*
* R11 is used by the loader as a temporary, so avoid it.
*/
#include "arm.s"
/*
* Turn off MMU, then copy the new kernel to its correct location
* in physical memory. Then jump to the start of the kernel.
*/
/* main(PADDR(... |
0intro/9legacy | 17,441 | sys/src/9/pcboot/l.s | /*
* non-startup assembly-language assist
*/
#include "mem.h"
#include "/sys/src/boot/pc/x16.h"
#undef DELAY
#define PADDR(a) ((a) & ~KZERO)
#define KADDR(a) (KZERO|(a))
/*
* Some machine instructions not handled by 8[al].
*/
#define OP16 BYTE $0x66
#define DELAY BYTE $0xEB; BYTE $0x00 /* JMP .+2 */
#define CP... |
0intro/9legacy | 4,884 | sys/src/9/pcboot/l16r.s | /*
* Protected-mode bootstrap, to be jumped to by a Primary Bootstrap Sector.
* Load with -H3 -R4 -T0xNNNNNNNN to get a binary image with no header.
* Note that the processor is in 'real' mode on entry, so care must be taken
* as the assembler assumes protected mode, hence the sometimes weird-looking
* code to ass... |
0intro/9legacy | 8,462 | sys/src/9/pcboot/l32v.s | #include "/sys/src/boot/pc/x16.h"
#include "mem.h"
#define KB 1024
#define MB (1024*1024)
#define WRMSR BYTE $0x0F; BYTE $0x30 /* WRMSR, argument in AX/DX (lo/hi) */
#define RDTSC BYTE $0x0F; BYTE $0x31 /* RDTSC, result in AX/DX (lo/hi) */
#define RDMSR BYTE $0x0F; BYTE $0x32 /* RDMSR, result in AX/DX (lo/hi) *... |
0intro/9legacy | 5,701 | sys/src/9/pcboot/ldecomp.s | /*
* Bootstrap loader decompressor. Starts at 0x10000 (where pbs puts it)
* or 0x7c00 (where pxe puts it) and memmoves kernel (immediately following)
* into standard kernel location.
*/
#include "mem.h"
#include "/sys/src/boot/pc/x16.h"
#undef BIOSCALL /* we don't know what evil the bios gets up to */
#define BI... |
0intro/9legacy | 7,084 | sys/src/9/pcboot/realmode0.s | #include "mem.h"
#include "/sys/src/boot/pc/x16.h"
#undef DELAY
#define PADDR(a) ((a) & ~KZERO)
#define KADDR(a) (KZERO|(a))
/*
* Some machine instructions not handled by 8[al].
*/
#define OP16 BYTE $0x66
#define DELAY BYTE $0xEB; BYTE $0x00 /* JMP .+2 */
#define CPUID BYTE $0x0F; BYTE $0xA2 /* CPUID, argument i... |
0intro/plan9 | 1,279 | sys/src/libc/386/atom.s | TEXT ainc(SB), $0 /* long ainc(long *); */
MOVL addr+0(FP), BX
ainclp:
MOVL (BX), AX
MOVL AX, CX
INCL CX
LOCK
BYTE $0x0F; BYTE $0xB1; BYTE $0x0B /* CMPXCHGL CX, (BX) */
JNZ ainclp
MOVL CX, AX
RET
TEXT adec(SB), $0 /* long adec(long*); */
MOVL addr+0(FP), BX
adeclp:
MOVL (BX), AX
MOVL AX, CX
DECL CX
LOCK
... |
0intro/plan9 | 1,250 | sys/src/libc/386/vlop.s | TEXT _mulv(SB), $0
MOVL r+0(FP), CX
MOVL a+4(FP), AX
MULL b+12(FP)
MOVL AX, 0(CX)
MOVL DX, BX
MOVL a+4(FP), AX
MULL b+16(FP)
ADDL AX, BX
MOVL a+8(FP), AX
MULL b+12(FP)
ADDL AX, BX
MOVL BX, 4(CX)
RET
/*
* _mul64by32(uint64 *r, uint64 a, uint32 b)
* sets *r = low 64 bits of 96-bit product a*b; returns hig... |
0intro/9legacy | 6,272 | sys/src/9/pcboot/l32p.s | #include "mem.h"
#define KB 1024
#define MB (1024*1024)
/*
* Some machine instructions not handled by 8[al].
*/
#define DELAY BYTE $0xEB; BYTE $0x00 /* JMP .+2 */
#define FARJUMP(s, o) BYTE $0xEA; /* far jump to ptr32:16 */\
LONG $o; WORD $s
#define NOP BYTE $0x90
#define HLT BYTE $0xF4
/*
* Macro for c... |
0intro/plan9 | 1,282 | sys/src/libc/sparc/memset.s | TEXT memset(SB),$0
/*
* performance:
* (tba)
*/
MOVW R7, 0(FP)
MOVW n+8(FP), R9 /* R9 is count */
MOVW p+0(FP), R10 /* R10 is pointer */
MOVW c+4(FP), R11 /* R11 is char */
ADD R9,R10, R12 /* R12 is end pointer */
/*
* if not at least 4 chars,
* dont even mess around.
* 3 chars to guarantee any
* rou... |
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