repo_id string | size int64 | file_path string | content string |
|---|---|---|---|
xem/nes | 1,491 | nes-test-roms/instr_misc/source/common/build_rom.s | ; Builds program as iNES ROM
; Default is 16K PRG and 8K CHR ROM, NROM (0)
.if 0 ; Options to set before .include "shell.inc":
CHR_RAM=1 ; Use CHR-RAM instead of CHR-ROM
CART_WRAM=1 ; Use mapper that supports 8K WRAM in cart
CUSTOM_MAPPER=n ; Specify mapper number
.endif
.ifndef CUSTOM_MAPPER
.ifdef CART_... |
xem/nes | 5,523 | nes-test-roms/instr_misc/source/common/console.s | ; Scrolling text console with line wrapping, 30x29 characters.
; Buffers lines for speed. Will work even if PPU doesn't
; support scrolling (until text reaches bottom). Keeps border
; along bottom in case TV cuts it off.
;
; Defers most initialization until first newline, at which
; point it clears nametable and makes ... |
xem/nes | 1,096 | nes-test-roms/instr_misc/source/common/text_out.s | ; Text output as expanding zero-terminated string at text_out_base
; The final exit result byte is written here
final_result = $6000
; Text output is written here as an expanding
; zero-terminated string
text_out_base = $6004
bss_res text_out_temp
zp_res text_out_addr,2
init_text_out:
ldx #0
; Put valid data fi... |
xem/nes | 2,024 | nes-test-roms/instr_misc/source/common/ppu.s | ; PPU utilities
bss_res ppu_not_present
; Sets PPUADDR to w
; Preserved: X, Y
.macro set_ppuaddr w
bit PPUSTATUS
setb PPUADDR,>w
setb PPUADDR,<w
.endmacro
; Delays by no more than n scanlines
.macro delay_scanlines n
.if CLOCK_RATE <> 1789773
.error "Currently only supports NTSC"
.endif
delay ((n)*341)/3
.e... |
xem/nes | 4,658 | nes-test-roms/instr_misc/source/common/shell.s | ; Common routines and runtime
; Detect inclusion loops (otherwise ca65 goes crazy)
.ifdef SHELL_INCLUDED
.error "shell.s included twice"
.end
.endif
SHELL_INCLUDED = 1
;**** Special globals ****
; Temporary variables that ANY routine might modify, so
; only use them between routine calls.
temp = <$A
temp2 = <$B... |
xem/nes | 3,437 | nes-test-roms/instr_misc/source/common/delay.s | ; Delays in CPU clocks, milliseconds, etc. All routines are re-entrant
; (no global data). No routines touch X or Y during execution.
; Code generated by macros is relocatable; it contains no JMPs to itself.
zp_byte delay_temp_ ; only written to
; Delays n clocks, from 2 to 16777215
; Preserved: A, X, Y, flags
.macro... |
xem/nes | 1,632 | nes-test-roms/instr_misc/source/common/crc.s | ; CRC-32 checksum calculation
zp_res checksum,4
zp_byte checksum_temp
zp_byte checksum_off_
; Turns CRC updating on/off. Allows nesting.
; Preserved: A, X, Y
crc_off:
dec checksum_off_
rts
crc_on: inc checksum_off_
beq :+
jpl internal_error ; catch unbalanced crc calls
: rts
; Initializes checksum modul... |
xen2/SharpLang | 3,638 | src/SharpLang.Runtime/coreclr/pal/tests/palsuite/composite/synchronization/nativecs_interlocked/hpitinterlock.s | //
// Copyright (c) Microsoft. All rights reserved.
// Licensed under the MIT license. See LICENSE file in the project root for full license information.
//
/*++
Module Name:
interlock.s
Abstract:
Implementation of Interlocked functions (32 and 64 bits) for the HPUX/Itanium
platform. These functions... |
xen2/SharpLang | 1,492 | src/SharpLang.Runtime/coreclr/pal/tests/palsuite/composite/synchronization/nativecs_interlocked/sparcinterloc.s | //
// Copyright (c) Microsoft. All rights reserved.
// Licensed under the MIT license. See LICENSE file in the project root for full license information.
//
/*++
Module Name:
interlock.s
Abstract:
Implementation of Interlocked functions for the SPARC
platform. These functions are processor depen... |
xen2/SharpLang | 3,738 | src/SharpLang.Runtime/coreclr/pal/src/arch/i386/dispatchexceptionwrapper.S | //
// Copyright (c) Microsoft. All rights reserved.
// Licensed under the MIT license. See LICENSE file in the project root for full license information.
//
// ==++==
//
// ==--==
//
// Implementation of the PAL_DispatchExceptionWrapper that is
// interposed between a function that caused a hardware fault
// and PAL... |
xen2/SharpLang | 5,999 | src/SharpLang.Runtime/coreclr/pal/src/arch/i386/tryexcept.s | //
// Copyright (c) Microsoft. All rights reserved.
// Licensed under the MIT license. See LICENSE file in the project root for full license information.
//
// ==++==
//
// ==--==
//
// Implementation of the PAL_TryExcept primitive for MSVC-style
// exception handling.
//
#define ALIGN_UP(x) ((x + 15) & ~15)
#ifde... |
xen2/SharpLang | 6,654 | src/SharpLang.Runtime/coreclr/pal/src/arch/i386/context2.s | //
// Copyright (c) Microsoft. All rights reserved.
// Licensed under the MIT license. See LICENSE file in the project root for full license information.
//
//
// Implementation of _CONTEXT_CaptureContext for the Intel x86 platform.
// This function is processor dependent. It is used by exception handling,
// and is a... |
xen2/SharpLang | 3,990 | src/SharpLang.Runtime/coreclr/pal/src/arch/i386/runfilter.s | //
// Copyright (c) Microsoft. All rights reserved.
// Licensed under the MIT license. See LICENSE file in the project root for full license information.
//
//
// Implementation of the PAL_RunFilter primitive that allows
// to run a filter guarded by a personality routine that can
// deal with nested exceptions.
//
#d... |
xenia-project/xenia | 5,140 | src/xenia/cpu/ppc/testing/instr_rldicr.s | .macro make_full_test_constant dest, a, b, c, d
lis \dest, \a
ori \dest, \dest, \b
sldi \dest, \dest, 32
lis r3, \c
ori r3, r3, \d
clrldi r3, r3, 32
or \dest, \dest, r3
.endm
test_rldicr_1:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicr r3, r4, 24, 0
blr
#_ REGISTER_OUT r3 0x0000000000000000
#_ RE... |
xenia-project/xenia | 9,885 | src/xenia/cpu/ppc/testing/instr_vpkd3d128.s | # vpkd3d128 dest, src, type, mask, shift
# type:
# 0 = PACK_TYPE_D3DCOLOR
# 1 = PACK_TYPE_SHORT_2
# 2 = PACK_TYPE_2_10_10_10
# 3 = PACK_TYPE_FLOAT16_2
# 4 = PACK_TYPE_SHORT_4
# 5 = PACK_TYPE_FLOAT16_4
# mask:
# must not be zero
# 1 = 00000000 00000000 00000000 FFFFFFFF
# 2 = 00000000 00000000 FFFFFFFF... |
xenia-project/xenia | 2,620 | src/xenia/cpu/ppc/testing/instr_mulhwu.s | test_mulhwu_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhwu_1_constant:
li r4, 1
li r5, 0
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhwu_2:
#_ REG... |
xenia-project/xenia | 11,815 | src/xenia/cpu/ppc/testing/instr_adde.s | test_adde_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 3
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0
test_adde_1_constant:
li r4, 1
li r5, 2
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 3
#_ REGISTER_OUT r... |
xenia-project/xenia | 5,237 | src/xenia/cpu/ppc/testing/instr_twi.s | test_twlti_1:
#_ REGISTER_IN r3 24
twlti r3, 16
blr
#_ REGISTER_OUT r3 24
test_twlti_1_constant:
li r3, 24
twlti r3, 16
blr
#_ REGISTER_OUT r3 24
test_twlti_2:
#_ REGISTER_IN r3 24
twlti r3, 0
blr
#_ REGISTER_OUT r3 24
test_twlti_2_constant:
li r3, 24
twlti r3, 0
blr
#_ REGISTER_OUT r... |
xenia-project/xenia | 1,322 | src/xenia/cpu/ppc/testing/instr_vpkuwum128.s | test_vpkuwum128_1:
# {0, 1, 2, 3}
#_ REGISTER_IN v3 [00000000, 00000001, 00000002, 00000003]
# {4, 5, 6, 7}
#_ REGISTER_IN v4 [00000004, 00000005, 00000006, 00000007]
vpkuwum128 v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000000, 00000001, 00000002, 00000003]
#_ REGISTER_OUT v4 [00000004, 00000005, 00000006, 0... |
xenia-project/xenia | 1,176 | src/xenia/cpu/ppc/testing/instr_vpkswss128.s | test_vpkswss128_1:
#_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
#_ REGISTER_IN v4 [00000005, 00000006, 00000007, 00000008]
vpkswss128 v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
#_ REGISTER_OUT v4 [00000005, 00000006, 00000007, 00000008]
#_ REGISTER_OUT v5 [000... |
xenia-project/xenia | 2,294 | src/xenia/cpu/ppc/testing/instr_subfe.s | test_subfe_1:
#_ REGISTER_IN r10 0x00000000000103BF
#_ REGISTER_IN r11 0x00000000000103C0
subfe r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r11 0x00000000000103C0
#_ REGISTER_OUT r3 0x0
#_ REGISTER_OUT r4 1
test_subfe_1_constant:
lis r10, 1
ori r10, r10... |
xenia-project/xenia | 6,691 | src/xenia/cpu/ppc/testing/instr_addme.s | test_addme_1:
#_ REGISTER_IN r4 1
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 1
test_addme_1_constant:
li r4, 1
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 1
test_addme_2:
#_ REGISTER_IN r... |
xenia-project/xenia | 1,304 | src/xenia/cpu/ppc/testing/instr_vpkuwum.s | test_vpkuwum_1:
# {0, 1, 2, 3}
#_ REGISTER_IN v3 [00000000, 00000001, 00000002, 00000003]
# {4, 5, 6, 7}
#_ REGISTER_IN v4 [00000004, 00000005, 00000006, 00000007]
vpkuwum v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000000, 00000001, 00000002, 00000003]
#_ REGISTER_OUT v4 [00000004, 00000005, 00000006, 0000000... |
xenia-project/xenia | 1,136 | src/xenia/cpu/ppc/testing/instr_lvr.s | test_lvr_1:
#_ MEMORY_IN 100010B0 090A0A0B 0C0F120A 0B0C0D0E 0F10130C 0D0E1011 121314FF FFFFFFFF
#_ REGISTER_IN r4 0x100010B7
#_ REGISTER_IN r5 0x10
lvrx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x100010B7
#_ REGISTER_OUT r5 0x10
#_ REGISTER_OUT v3 [00000000, 00000000, 000D0E10, 11121314]
test_lvr_1_constant:... |
xenia-project/xenia | 3,164 | src/xenia/cpu/ppc/testing/instr_divd.s | test_divd_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
divd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
test_divd_1_constant:
li r4, 1
li r5, 2
divd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
# TODO(benvanik): x64 ignore di... |
xenia-project/xenia | 4,465 | src/xenia/cpu/ppc/testing/instr_andc.s | test_andc_1:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
test_andc_1_constant:
li r5, -1
li r25, -1
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0x... |
xenia-project/xenia | 2,503 | src/xenia/cpu/ppc/testing/instr_extsh.s | test_extsh_1:
#_ REGISTER_IN r4 0x0F
extsh r3, r4
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
test_extsh_1_constant:
li r4, 0x0F
extsh r3, r4
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
test_extsh_2:
#_ REGISTER_IN r4 0x7FFF
extsh r3, r4
blr
#_ REGISTER_OUT r3 0x7FFF
#_ R... |
xenia-project/xenia | 1,832 | src/xenia/cpu/ppc/testing/instr_mulhd.s | test_mulhd_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhd_1_constant:
li r4, 1
li r5, 0
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhd_2:
#_ REGISTER... |
xenia-project/xenia | 1,784 | src/xenia/cpu/ppc/testing/instr_mulhdu.s | test_mulhdu_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhdu_1_constant:
li r4, 1
li r5, 0
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhdu_2:
#_ REG... |
xenia-project/xenia | 1,127 | src/xenia/cpu/ppc/testing/instr_vsl.s | test_vsl_1:
#_ REGISTER_IN v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v4 [04040404, 04040404, 04040404, 04040404]
vsl v3, v3, v4
blr
#_ REGISTER_OUT v3 [EFEFEFEF, EFEFEFEF, EFEFEFEF, EFEFEFE0]
#_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
test_vsl_2:
#_ REGISTER_IN v3 [00112... |
xenia-project/xenia | 2,415 | src/xenia/cpu/ppc/testing/instr_vperm.s | test_vperm_1:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v5 [00000000, 00000000, 00000000, 00000000]
vperm v6, v3, v4, v5
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, ... |
xenia-project/xenia | 2,462 | src/xenia/cpu/ppc/testing/instr_sld.s | test_sld_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
sld r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_sld_1_constant:
li r4, 1
li r5, 0
sld r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_sld_2:
#_ REGISTER_IN r4 0xF... |
xenia-project/xenia | 3,563 | src/xenia/cpu/ppc/testing/instr_subfze.s | test_subfze_one_ca_1:
#_ REGISTER_IN r10 0x00000000000103BF
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfze r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r3 0xfffffffffffefc41
#_ REGISTER_OUT r4 0
test_subfze_one_ca_1_constant:
lis r10, 1
ori r10, r10, 0x03... |
xenia-project/xenia | 1,570 | src/xenia/cpu/ppc/testing/instr_vpkuhum128.s | #vpkuhum128 isn't implemented yet
#test_vpkuhum128_1:
# # {0, 1, 2, 3, 4, 5, 6, 7}
# #_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007]
# # {8, 9, 10, 11, 12, 13, 14, 15}
# #_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F]
# vpkuhum128 v5, v3, v4
# blr
# #_ REGISTER_OUT v3 [00000001, 00020003, 0... |
xenia-project/xenia | 3,132 | src/xenia/cpu/ppc/testing/instr_srad.s | test_srad_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_srad_1_constant:
li r4, 1
li r5, 0
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r... |
xenia-project/xenia | 1,232 | src/xenia/cpu/ppc/testing/instr_cntlzw.s | test_cntlzw_1:
#_ REGISTER_IN r5 0
cntlzw r6, r5
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 32
test_cntlzw_1_constant:
li r5, 0
cntlzw r6, r5
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 32
test_cntlzw_2:
#_ REGISTER_IN r5 1
cntlzw r6, r5
blr
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 31
t... |
xenia-project/xenia | 2,779 | src/xenia/cpu/ppc/testing/instr_vrlimi128.s | test_vrlimi128_1:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
vrlimi128 v4, v3, 0, 0
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
test_vrlimi128_2:
#_ R... |
xenia-project/xenia | 2,633 | src/xenia/cpu/ppc/testing/instr_mulld.s | test_mulld_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulld_1_constant:
li r4, 1
li r5, 0
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulld_2:
#_ REGISTER... |
xenia-project/xenia | 2,006 | src/xenia/cpu/ppc/testing/instr_cmpli.s | test_cmpldi_1:
#_ REGISTER_IN r3 0x0000000100000000
cmpldi r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 0x0000000100000000
#_ REGISTER_OUT r12 0x40000000
test_cmpldi_1_constant:
li r3, 1
sldi r3, r3, 32
cmpldi r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 0x0000000100000000
#_ REGISTER_OUT r12 0x40000000
t... |
xenia-project/xenia | 1,158 | src/xenia/cpu/ppc/testing/instr_vpkswss.s | test_vpkswss_1:
#_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
#_ REGISTER_IN v4 [00000005, 00000006, 00000007, 00000008]
vpkswss v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
#_ REGISTER_OUT v4 [00000005, 00000006, 00000007, 00000008]
#_ REGISTER_OUT v5 [00010002,... |
xenia-project/xenia | 1,874 | src/xenia/cpu/ppc/testing/instr_andis.s | test_andis_cr_1:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
andis. r11, r5, 0xCAFE
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xCAFE0000
#_ REGISTER_OUT r12 0x80000000
test_andis_cr_1_constant:
li r5, -1
andis. r11, r5, 0xCAFE
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFF... |
xenia-project/xenia | 7,743 | src/xenia/cpu/ppc/testing/instr_tw.s | test_twlt_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 16
twlt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_twlt_1_constant:
li r3, 24
li r4, 16
twlt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_twlt_2:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 0
twlt r3, r4
blr... |
xenia-project/xenia | 2,276 | src/xenia/cpu/ppc/testing/instr_mulhw.s | test_mulhw_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhw_1_constant:
li r4, 1
li r5, 0
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhw_2:
#_ REGISTER... |
xenia-project/xenia | 4,388 | src/xenia/cpu/ppc/testing/instr_rlwnm.s | test_rlwnm_1:
#_ REGISTER_IN r4 0x12345678
#_ REGISTER_IN r5 24
rlwnm r3, r4, r5, 8, 15
blr
#_ REGISTER_OUT r3 0x00120000
#_ REGISTER_OUT r4 0x12345678
#_ REGISTER_OUT r5 24
test_rlwnm_1_constant:
lis r4, 0x1234
ori r4, r4, 0x5678
li r5, 24
rlwnm r3, r4, r5, 8, 15
blr
#_ REGISTER_OUT r3 0x001... |
xenia-project/xenia | 3,869 | src/xenia/cpu/ppc/testing/instr_slw.s | test_slw_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_slw_1_constant:
li r4, 1
li r5, 0
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_slw_2:
#_ REGISTER_IN r4 0xF... |
xenia-project/xenia | 5,645 | src/xenia/cpu/ppc/testing/instr_rlwinm.s | test_rlwinm_1:
#_ REGISTER_IN r4 0x12345678
rlwinm r3, r4, 24, 8, 15
blr
#_ REGISTER_OUT r3 0x00120000
#_ REGISTER_OUT r4 0x12345678
test_rlwinm_1_constant:
lis r4, 0x1234
ori r4, r4, 0x5678
rlwinm r3, r4, 24, 8, 15
blr
#_ REGISTER_OUT r3 0x00120000
#_ REGISTER_OUT r4 0x12345678
test_rlwinm_2:
... |
xenia-project/xenia | 2,681 | src/xenia/cpu/ppc/testing/instr_vctuxs.s | # 0 * 2^31
test_vctuxs_1:
#_ REGISTER_IN v0 [00000000, 00000000, 00000000, 00000000]
vctuxs v3, v0, 31
blr
#_ REGISTER_OUT v0 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
# -0 ^ 2^31
test_vctuxs_2:
#_ REGISTER_IN v0 [80000000, 80000000, 80000000, 8000... |
xenia-project/xenia | 1,399 | src/xenia/cpu/ppc/testing/instr_vmrghw.s | test_vmrghw_1:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
vmrghw v5, v3, v4
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [00010203, 1... |
xenia-project/xenia | 2,190 | src/xenia/cpu/ppc/testing/instr_subfc.s | test_subfc_1:
#_ REGISTER_IN r10 0x00000000000103BF
#_ REGISTER_IN r11 0x00000000000103C0
subfc r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r11 0x00000000000103C0
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
test_subfc_1_constant:
lis r10, 1
ori r10, r10, ... |
xenia-project/xenia | 2,054 | src/xenia/cpu/ppc/testing/instr_vsel.s | test_vsel_1:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v5 [00000000, 00000000, 00000000, 00000000]
vsel v5, v3, v4, v5
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14... |
xenia-project/xenia | 1,703 | src/xenia/cpu/ppc/testing/instr_vslh.s | test_vslh_1:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
vslh v3, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
test_vslh_2:
#_ REGISTER_IN v3 [FF... |
xenia-project/xenia | 4,311 | src/xenia/cpu/ppc/testing/instr_divw.s | test_divw_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
test_divw_1_constant:
li r4, 1
li r5, 2
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
# TODO(benvanik): x64 ignore di... |
xenia-project/xenia | 7,743 | src/xenia/cpu/ppc/testing/instr_td.s | test_tdlt_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 16
tdlt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_tdlt_1_constant:
li r3, 24
li r4, 16
tdlt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_tdlt_2:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 0
tdlt r3, r4
blr... |
xenia-project/xenia | 1,419 | src/xenia/cpu/ppc/testing/instr_vsro.s | test_vsro_1:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [04040404, 04040404, 04040404, 04040404]
vsro v3, v3, v4
blr
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
test_vsro_2:
#_ REGISTER_IN v3 [00... |
xenia-project/xenia | 2,535 | src/xenia/cpu/ppc/testing/instr_eqv.s | test_eqv_1:
#_ REGISTER_IN r4 0
#_ REGISTER_IN r5 1
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0xfffffffffffffffe
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r5 1
test_eqv_1_constant:
li r4, 0
li r5, 1
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0xfffffffffffffffe
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r5 1
t... |
xenia-project/xenia | 1,817 | src/xenia/cpu/ppc/testing/instr_srawi.s | test_srawi_1:
#_ REGISTER_IN r4 1
srawi r3, r4, 0
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
test_srawi_1_constant:
li r4, 1
srawi r3, r4, 0
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
test_srawi_2:
#_ REGISTE... |
xenia-project/xenia | 2,847 | src/xenia/cpu/ppc/testing/instr_stvew.s | test_stvew_1:
#_ MEMORY_IN 10001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
#_ REGISTER_IN r4 0x10001050
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
stvewx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001050
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ MEMORY_OUT 10001050 00010203 ... |
xenia-project/xenia | 1,219 | src/xenia/cpu/ppc/testing/instr_vpkshss.s | test_vpkshss_1:
#_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007]
#_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F]
vpkshss v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
#_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F]
#_ REGISTER_OUT v5 [00010203,... |
xenia-project/xenia | 6,555 | src/xenia/cpu/ppc/testing/instr_addze.s | test_addze_1:
#_ REGISTER_IN r4 1
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
test_addze_1_constant:
li r4, 1
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
test_addze_2:
#_ REGISTER_IN r... |
xenia-project/xenia | 1,049 | src/xenia/cpu/ppc/testing/instr_vmrglh.s | test_vmrglh_1:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
vmrglh v5, v3, v4
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [08091819, 0... |
xenia-project/xenia | 2,195 | src/xenia/cpu/ppc/testing/instr_vctsxs.s | # 0 * 2^31
test_vctsxs_1:
#_ REGISTER_IN v0 [00000000, 00000000, 00000000, 00000000]
vctsxs v3, v0, 31
blr
#_ REGISTER_OUT v0 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
# -0 ^ 2^31
test_vctsxs_2:
#_ REGISTER_IN v0 [80000000, 80000000, 80000000, 8000... |
xenia-project/xenia | 1,419 | src/xenia/cpu/ppc/testing/instr_vslb.s | test_vslb_1:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
vslb v3, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
test_vslb_2:
#_ REGISTER_IN v3 [FF... |
xenia-project/xenia | 1,703 | src/xenia/cpu/ppc/testing/instr_vslw.s | test_vslw_1:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
vslw v3, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
test_vslw_2:
#_ REGISTER_IN v3 [FF... |
xenia-project/xenia | 3,946 | src/xenia/cpu/ppc/testing/instr_srw.s | test_srw_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_srw_1_constant:
li r4, 1
li r5, 0
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_srw_2:
#_ REGISTER_IN r4 0xF... |
xenia-project/xenia | 2,527 | src/xenia/cpu/ppc/testing/instr_vcmpxxfp.s | test_vcmpxxfp_1:
#_ REGISTER_IN v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_IN v5 [3f800000, 3f800000, 3f800000, 3f800000]
vcmpeqfp. v3, v4, v5
mfocrf r3, 2 # cr6
blr
#_ REGISTER_OUT v3 [ffffffff, ffffffff, ffffffff, ffffffff]
#_ REGISTER_OUT v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ ... |
xenia-project/xenia | 4,625 | src/xenia/cpu/ppc/testing/instr_divwu.s | test_divwu_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
test_divwu_1_constant:
li r4, 1
li r5, 2
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
# TODO(benvanik): x64 ignor... |
xenia-project/xenia | 4,054 | src/xenia/cpu/ppc/testing/instr_sraw.s | test_sraw_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_sraw_1_constant:
li r4, 1
li r5, 0
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r... |
xenia-project/xenia | 1,088 | src/xenia/cpu/ppc/testing/instr_vpermwi128.s | test_vpermwi128_1:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
# to 0,1,2,3
# vpermwi128 v4, v3, 0x1B
.long 0x189B1A10
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_vpermwi128_2:
#_ REGISTER_IN v3 [0001020... |
xenia-project/xenia | 2,399 | src/xenia/cpu/ppc/testing/instr_extsb.s | test_extsb_1:
#_ REGISTER_IN r4 0x0F
extsb r3, r4
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
test_extsb_1_constant:
li r4, 0x0F
extsb r3, r4
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
test_extsb_2:
#_ REGISTER_IN r4 0x7F
extsb r3, r4
blr
#_ REGISTER_OUT r3 0x7F
#_ REGIS... |
xenia-project/xenia | 5,509 | src/xenia/cpu/ppc/testing/instr_addc.s | test_addc_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
addc r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 3
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0
test_addc_1_constant:
li r4, 1
li r5, 2
addc r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 3
#_ REGISTER_OUT r... |
xenia-project/xenia | 5,237 | src/xenia/cpu/ppc/testing/instr_tdi.s | test_tdlti_1:
#_ REGISTER_IN r3 24
tdlti r3, 16
blr
#_ REGISTER_OUT r3 24
test_tdlti_1_constant:
li r3, 24
tdlti r3, 16
blr
#_ REGISTER_OUT r3 24
test_tdlti_2:
#_ REGISTER_IN r3 24
tdlti r3, 0
blr
#_ REGISTER_OUT r3 24
test_tdlti_2_constant:
li r3, 24
tdlti r3, 0
blr
#_ REGISTER_OUT r... |
xenia-project/xenia | 1,817 | src/xenia/cpu/ppc/testing/instr_sradi.s | test_sradi_1:
#_ REGISTER_IN r4 1
sradi r3, r4, 0
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
test_sradi_1_constant:
li r4, 1
sradi r3, r4, 0
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
test_sradi_2:
#_ REGISTE... |
xenia-project/xenia | 3,952 | src/xenia/cpu/ppc/testing/instr_mullw.s | test_mullw_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mullw_1_constant:
li r4, 1
li r5, 0
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mullw_2:
#_ REGISTER... |
xenia-project/xenia | 1,237 | src/xenia/cpu/ppc/testing/instr_vpkshss128.s | test_vpkshss128_1:
#_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007]
#_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F]
vpkshss128 v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
#_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F]
#_ REGISTER_OUT v5 [000... |
xenia-project/xenia | 8,426 | src/xenia/cpu/ppc/testing/ppc_testing_native_thunks.s | /**
******************************************************************************
* Xenia : Xbox 360 Emulator Research Project *
******************************************************************************
* Copyright 2017 Ben Vanik. All rights reserved. ... |
xenia-project/xenia | 1,978 | src/xenia/cpu/ppc/testing/instr_cmpi.s | test_cmpdi_1:
#_ REGISTER_IN r3 0x0000000100000000
cmpdi r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 0x0000000100000000
#_ REGISTER_OUT r12 0x40000000
test_cmpdi_1_constant:
li r3, 1
sldi r3, r3, 32
cmpdi r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 0x0000000100000000
#_ REGISTER_OUT r12 0x40000000
test_... |
xenia-project/xenia | 3,627 | src/xenia/cpu/ppc/testing/instr_subfme.s | test_subfme_one_ca_1:
#_ REGISTER_IN r10 0x00000000000103BF
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfme r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r3 0xfffffffffffefc40
#_ REGISTER_OUT r4 1
test_subfme_one_ca_1_constant:
lis r10, 1
ori r10, r10, 0x03... |
xenia-project/xenia | 2,426 | src/xenia/cpu/ppc/testing/instr_vupkd3d128.s | # vupkd3d128 dest, src, type
# type:
# 0 = PACK_TYPE_D3DCOLOR
# 1 = PACK_TYPE_SHORT_2
# 3 = PACK_TYPE_FLOAT16_2
# 5 = PACK_TYPE_FLOAT16_4
# vupkd3d128 is broken in binutils, so these are hand coded
test_vupkd3d128_d3dcolor:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
# vupkd3d128 v3, v3, 0
... |
xenia-project/xenia | 1,447 | src/xenia/cpu/ppc/testing/instr_vmaddfp.s | test_vmaddfp_1:
#_ REGISTER_IN v4 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
# 1.0, 1.5, 1.1, 1.9
vmaddfp v3, v4, v4, v4
blr
#_ REGISTER_OUT v3 [40000000, 40700000, 4013d70a, 40b051eb]
#_ REGISTER_OUT v4 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
# 2.0, 3.75, 2.31, 5.51
# 40b051eb is actually 5.50999975, no... |
xenia-project/xenia | 2,242 | src/xenia/cpu/ppc/testing/instr_stvr.s | test_stvr_1:
#_ MEMORY_IN 10001040 BE74FCBD BD912ABA BF317BBB BF2D135F
#_ MEMORY_IN 10001050 00000000 00000000 00000000 00000000
#_ REGISTER_IN r4 0x10001040
#_ REGISTER_IN r5 0x10
#_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
stvrx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x10001040
#_ REGISTER... |
xenia-project/xenia | 1,536 | src/xenia/cpu/ppc/testing/instr_addic.s | test_addic_1:
#_ REGISTER_IN r4 1
addic r4, r4, 1
adde r6, r0, r0
blr
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r6 0
test_addic_1_constant:
li r4, 1
addic r4, r4, 1
adde r6, r0, r0
blr
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r6 0
test_addic_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
addic r4, r4, 1
... |
xenia-project/xenia | 2,615 | src/xenia/cpu/ppc/testing/instr_extsw.s | test_extsw_1:
#_ REGISTER_IN r4 0x0F
extsw r3, r4
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
test_extsw_1_constant:
li r4, 0x0F
extsw r3, r4
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
test_extsw_2:
#_ REGISTER_IN r4 0x7FFFFFFF
extsw r3, r4
blr
#_ REGISTER_OUT r3 0x7FFFFFF... |
xenia-project/xenia | 1,243 | src/xenia/cpu/ppc/testing/instr_vsldoi.s | test_vsldoi_1:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v5 [00000000, 00000000, 00000000, 00000000]
vsldoi v5, v3, v4, 0
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213,... |
xenia-project/xenia | 1,482 | src/xenia/cpu/ppc/testing/instr_vpkuhum.s | test_vpkuhum_1:
# {0, 1, 2, 3, 4, 5, 6, 7}
#_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007]
# {8, 9, 10, 11, 12, 13, 14, 15}
#_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F]
vpkuhum v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
#_ REGISTER_OUT v4 [0008000... |
xenia-project/xenia | 1,854 | src/xenia/cpu/ppc/testing/instr_andi.s | test_andi_cr_1:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
andi. r11, r5, 0xCAFE
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0x0000CAFE
#_ REGISTER_OUT r12 0x40000000
test_andi_cr_1_constant:
li r5, -1
andi. r11, r5, 0xCAFE
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF... |
xenia-project/xenia | 4,259 | src/xenia/cpu/ppc/testing/instr_fctixz.s | # Credits: These tests stolen from https://github.com/dolphin-emu/hwtests
# +0
test_fctiwz_1:
#_ REGISTER_IN f0 0x0000000000000000
fctiwz f1, f0
blr
#_ REGISTER_OUT f0 0x0000000000000000
#_ REGISTER_OUT f1 0x0000000000000000
# -0
test_fctiwz_2:
#_ REGISTER_IN f0 0x8000000000000000
fctiwz f1, f0
blr
#... |
xenia-project/xenia | 4,393 | src/xenia/cpu/ppc/testing/instr_and.s | test_and_1:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
and r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
test_and_1_constant:
li r5, -1
li r25, -1
and r11, r5, r25
blr
#_ REGIS... |
xenia-project/xenia | 1,338 | src/xenia/cpu/ppc/testing/instr_addis.s | test_addis_1:
#_ REGISTER_IN r0 1234
#_ REGISTER_IN r4 1
addis r3, r0, 1
blr
#_ REGISTER_OUT r0 1234
#_ REGISTER_OUT r3 0x10000
#_ REGISTER_OUT r4 1
test_addis_1_constant:
li r0, 1234
li r4, 1
addis r3, r0, 1
blr
#_ REGISTER_OUT r0 1234
#_ REGISTER_OUT r3 0x10000
#_ REGISTER_OUT r4 1
test_... |
xenia-project/xenia | 1,127 | src/xenia/cpu/ppc/testing/instr_vsr.s | test_vsr_1:
#_ REGISTER_IN v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v4 [04040404, 04040404, 04040404, 04040404]
vsr v3, v3, v4
blr
#_ REGISTER_OUT v3 [0FEFEFEF, EFEFEFEF, EFEFEFEF, EFEFEFEF]
#_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
test_vsr_2:
#_ REGISTER_IN v3 [00112... |
xenia-project/xenia | 3,943 | src/xenia/cpu/ppc/testing/instr_lvexx.s | test_lvebx_1:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0x10001000
lvebx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001000
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvebx_1_constant:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b ... |
xenia-project/xenia | 1,419 | src/xenia/cpu/ppc/testing/instr_vslo.s | test_vslo_1:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [04040404, 04040404, 04040404, 04040404]
vslo v3, v3, v4
blr
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
test_vslo_2:
#_ REGISTER_IN v3 [00... |
xenia-project/xenia | 2,563 | src/xenia/cpu/ppc/testing/instr_vcmpxxfp128.s | test_vcmpxxfp128_1:
#_ REGISTER_IN v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_IN v5 [3f800000, 3f800000, 3f800000, 3f800000]
vcmpeqfp128. v3, v4, v5
mfocrf r3, 2 # cr6
blr
#_ REGISTER_OUT v3 [ffffffff, ffffffff, ffffffff, ffffffff]
#_ REGISTER_OUT v4 [3f800000, 3f800000, 3f800000, 3f800000]... |
xenia-project/xenia | 2,462 | src/xenia/cpu/ppc/testing/instr_srd.s | test_srd_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
srd r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_srd_1_constant:
li r4, 1
li r5, 0
srd r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_srd_2:
#_ REGISTER_IN r4 0xF... |
xenia-project/xenia | 3,285 | src/xenia/cpu/ppc/testing/instr_add.s | test_add_1:
#_ REGISTER_IN r5 0x00100000
#_ REGISTER_IN r25 0x0000FFFF
add r11, r5, r25
blr
#_ REGISTER_OUT r5 0x00100000
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0010FFFF
test_add_1_constant:
lis r5, 0x10
li r25, -1
clrldi r25, r25, 48
add r11, r5, r25
blr
#_ REGISTER_OUT r5 ... |
xenia-project/xenia | 1,768 | src/xenia/cpu/ppc/testing/instr_subf.s | test_subf_1:
#_ REGISTER_IN r10 0x00000000000103BF
#_ REGISTER_IN r11 0x00000000000103C0
subf r3, r10, r11
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r11 0x00000000000103C0
#_ REGISTER_OUT r3 0x1
test_subf_1_constant:
lis r10, 1
ori r10, r10, 0x03BF
lis r11, 1
ori r11, r11, 0x03C0... |
xenia-project/xenia | 1,977 | src/xenia/cpu/ppc/testing/instr_mulli.s | test_mulli_1:
#_ REGISTER_IN r4 1
mulli r3, r4, 0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_mulli_1_constant:
li r4, 1
mulli r3, r4, 0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_mulli_2:
#_ REGISTER_IN r4 1
mulli r3, r4, 1
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
t... |
xenia-project/xenia | 1,419 | src/xenia/cpu/ppc/testing/instr_stvl.s | test_stvlx_1:
#_ MEMORY_IN 10001040 00000000 00000000 00000000 3F800000
#_ REGISTER_IN r4 0x10001040
#_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
stvlx v3, r4, r0
blr
#_ REGISTER_OUT r4 0x10001040
#_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
#_ MEMORY_OUT 10001040 BE74FCBD B... |
xenia-project/xenia | 5,413 | src/xenia/cpu/ppc/testing/instr_rldicl.s | .macro make_full_test_constant dest, a, b, c, d
lis \dest, \a
ori \dest, \dest, \b
sldi \dest, \dest, 32
lis r3, \c
ori r3, r3, \d
clrldi r3, r3, 32
or \dest, \dest, r3
.endm
test_rldicl_1:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 24, 0
blr
#_ REGISTER_OUT r3 0x6789abcdef012345
#_ RE... |
xenia-project/xenia | 2,111 | src/xenia/cpu/ppc/testing/instr_subfic.s | test_subfic_1:
#_ REGISTER_IN r10 0x00000000000103BF
subfic r3, r10, 0x3C0
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r3 0xffffffffffff0001
#_ REGISTER_OUT r4 0
test_subfic_1_constant:
lis r10, 1
ori r10, r10, 0x03BF
subfic r3, r10, 0x3C0
adde r4, r0, r0
blr
#_... |
xenia-project/xenia | 1,399 | src/xenia/cpu/ppc/testing/instr_vmrglw.s | test_vmrglw_1:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
vmrglw v5, v3, v4
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [08090a0b, 1... |
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