code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module exor2_hvt_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
assign Y = (A & !B) | (!A & B);
endmodule
| 8.545894 |
module inv_18 (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.139984 |
module inv_lvt (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.525807 |
module inv_18_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.154152 |
module inv_25_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.78678 |
module inv_25_hv (
out,
in,
vhi
);
output out;
input in;
input vhi;
assign out = ~in;
endmodule
| 8.012627 |
module inv_33 (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.176543 |
module inv_33_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.220746 |
module inv_33_hv (
out,
in,
vhi
);
output out;
input in;
input vhi;
assign out = ~in;
endmodule
| 7.597145 |
module inv (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.1601 |
module inv_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.514169 |
module inv_hvt (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 8.281121 |
module inv_hvt_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.56117 |
module inv_tri_2_25 (
Y,
A,
T,
Tb
);
output Y;
input A;
input T;
input Tb;
reg Y;
always @(A or T or Tb) begin
if ((T == 1) && (Tb == 0)) Y = !A;
else Y = 1'bz;
end
endmodule
| 7.094936 |
module inv_tri_2_25_g (
Y,
A,
T,
Tb,
gnd_node
);
output Y;
input A;
input T;
input Tb;
input gnd_node;
reg Y;
always @(A or T or Tb or gnd_node) begin
if ((T == 1) && (Tb == 0) && (gnd_node == 0)) Y = !A;
else Y = 1'bz;
end
endmodule
| 6.722643 |
module inv_tri_2_33 (
Y,
A,
T,
Tb
);
output Y;
input A;
input T;
input Tb;
reg Y;
always @(A or T or Tb) begin
if ((T == 1) && (Tb == 0)) Y = !A;
else Y = 1'bz;
end
endmodule
| 6.6963 |
module inv_w_pd_18 (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 6.93581 |
module inv_w_pd_18_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.1415 |
module inv_w_pd_25 (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 8.364532 |
module inv_w_pd_25_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.757096 |
module inv_w_pd_33 (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 6.734843 |
module inv_w_pd_33_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.196124 |
module inv_w_pd (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.238458 |
module inv_w_pd_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.247208 |
module inv_w_pd_hvt (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.624569 |
module inv_w_pd_hvt_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.54807 |
module inv_w_pu_18 (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.189413 |
module inv_w_pu_18_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.656252 |
module inv_w_pu_25 (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 8.695971 |
module inv_w_pu_25_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 8.267087 |
module inv_w_pu_33 (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.210949 |
module inv_w_pu_33_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.820649 |
module inv_w_pu (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.454982 |
module inv_w_pu_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.549095 |
module inv_w_pu_hvt (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.846323 |
module inv_w_pu_hvt_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 8.042685 |
module mux2 (
out,
in0,
in1,
sel
);
output out;
input in0;
input in1;
input sel;
assign out = (sel) ? in1 : in0;
endmodule
| 6.762042 |
module mux2_g (
out,
in0,
in1,
sel,
gnd_node
);
output out;
input in0;
input in1;
input sel;
input gnd_node;
assign out = (sel) ? in1 : in0;
endmodule
| 6.866418 |
module mux2_hvt (
out,
in0,
in1,
sel
);
output out;
input in0;
input in1;
input sel;
assign out = (sel) ? in1 : in0;
endmodule
| 8.126877 |
module mux2_hvt_g (
out,
in0,
in1,
sel,
gnd_node
);
output out;
input in0;
input in1;
input sel;
input gnd_node;
assign out = (sel) ? in1 : in0;
endmodule
| 7.104145 |
module mux3_25 (
out,
in0,
in1,
in2,
sel
);
output out;
input in0;
input in1;
input in2;
input [3:0] sel;
reg out;
always @(sel or in0 or in1 or in2) begin
if (sel == 4'b1001) out = in0;
else if (sel == 4'b1010) out = in1;
else if (sel == 4'b1100) out = in2;
else out... | 6.64393 |
module mux3 (
out,
in0,
in1,
in2,
sel
);
output out;
input in0;
input in1;
input in2;
input [3:0] sel;
reg out;
always @(sel or in0 or in1 or in2) begin
if (sel == 4'b1001) out = in0;
else if (sel == 4'b1010) out = in1;
else if (sel == 4'b1100) out = in2;
else out = ... | 7.29964 |
module nand2_18 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A & B);
endmodule
| 8.085373 |
module nand2_lvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A & B);
endmodule
| 9.305138 |
module nand2_18_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
initial begin
Y = 1;
end
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A & B);
else Y = 1'bz;
endmodule
| 6.739653 |
module nand2_25_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A & B);
else Y = 1'bz;
endmodule
| 6.963533 |
module nand2_33 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A & B);
endmodule
| 8.526801 |
module nand2_33_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A & B);
else Y = 1'bz;
endmodule
| 6.898864 |
module nand2_33_hv (
out,
in1,
in2,
vdd33
);
output out;
input vdd33;
input in1;
input in2;
assign out = ~(in1 & in2);
endmodule
| 8.652404 |
module nand2 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A & B);
endmodule
| 9.113032 |
module nand2_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A & B);
else Y = 1'bz;
endmodule
| 6.789204 |
module nand2_hvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A & B);
endmodule
| 9.392288 |
module nand2_hvt_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A & B);
else Y = 1'bz;
endmodule
| 7.157983 |
module nand3_18 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A & B & C);
endmodule
| 7.560604 |
module nand3_33 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A & B & C);
endmodule
| 8.100182 |
module nand3_33_g (
Y,
A,
B,
C,
gnd_node
);
output Y;
input A;
input B;
input C;
input gnd_node;
reg Y;
always @(A or B or C or gnd_node)
if (gnd_node == 1'b0) Y = ~(A & B & C);
else Y = 1'bz;
endmodule
| 6.623985 |
module nand3 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A & B & C);
endmodule
| 8.175282 |
module nand3_hvt (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A & B & C);
endmodule
| 8.69723 |
module nand4_18 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
assign Y = ~(A & B & C & D);
endmodule
| 7.842592 |
module nand4_25_g (
Y,
A,
B,
C,
D,
gnd_node
);
output Y;
input A;
input B;
input C;
input D;
input gnd_node;
reg Y;
always @(A or B or C or D)
if (gnd_node == 1'b0) Y = ~(A & B & C & D);
else Y = 1'bz;
endmodule
| 6.961719 |
module nand4_33 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
assign Y = ~(A & B & C & D);
endmodule
| 8.403222 |
module nand4_33_g (
Y,
A,
B,
C,
D,
gnd_node
);
output Y;
input A;
input B;
input C;
input D;
input gnd_node;
reg Y;
always @(A or B or C or D)
if (gnd_node == 1'b0) Y = ~(A & B & C & D);
else Y = 1'bz;
endmodule
| 7.303227 |
module nand4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
assign Y = ~(A & B & C & D);
endmodule
| 8.989501 |
module nand4_g (
Y,
A,
B,
C,
D,
gnd_node
);
output Y;
input A;
input B;
input C;
input D;
input gnd_node;
reg Y;
always @(A or B or C or D)
if (gnd_node == 1'b0) Y = ~(A & B & C & D);
else Y = 1'bz;
endmodule
| 6.877974 |
module nand4_hvt (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
assign Y = ~(A & B & C & D);
endmodule
| 8.931189 |
module nand4_hvt_g (
Y,
A,
B,
C,
D,
gnd_node
);
output Y;
input A;
input B;
input C;
input D;
input gnd_node;
reg Y;
always @(A or B or C or D)
if (gnd_node == 1'b0) Y = ~(A & B & C & D);
else Y = 1'bz;
endmodule
| 6.680195 |
module nor2_18 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A | B);
endmodule
| 7.524882 |
module nor2_lvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A | B);
endmodule
| 8.594783 |
module nor2_18_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A | B);
else Y = 1'bz;
endmodule
| 6.636566 |
module nor2_33 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A | B);
endmodule
| 7.614976 |
module nor2_33_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A | B);
else Y = 1'bz;
endmodule
| 6.718455 |
module nor2 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A | B);
endmodule
| 8.297456 |
module nor2_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A | B);
else Y = 1'bz;
endmodule
| 6.75369 |
module nor2_hvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A | B);
endmodule
| 8.725239 |
module nor2_hvt_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A | B);
else Y = 1'bz;
endmodule
| 6.999871 |
module nor3_18 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A | B | C);
endmodule
| 7.205138 |
module nor3_33 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A | B | C);
endmodule
| 7.234638 |
module nor3 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A | B | C);
endmodule
| 7.681855 |
module nor3_hvt (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A | B | C);
endmodule
| 7.780348 |
module nor4_hvt (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
assign Y = ~(A | B | C | D);
endmodule
| 7.961286 |
module oai21x2_18_g (
Y,
A0,
A1,
B0,
gnd_node
);
output Y;
input A0;
input A1;
input B0;
input gnd_node;
reg Y;
always @(A0 or A1 or B0 or gnd_node)
if (gnd_node == 1'b0) begin
if (B0 == 1'b0) begin
Y = 1'b1;
end else begin
Y = !(A0 | A1);
end
... | 6.599237 |
module oai21x2_g (
Y,
A0,
A1,
B0,
gnd_node
);
output Y;
input A0;
input A1;
input B0;
input gnd_node;
reg Y;
always @(A0 or A1 or B0)
if (B0 == 1'b0) begin
Y = 1'b1;
end else begin
Y = !(A0 | A1);
end
endmodule
| 6.538832 |
module clkandnor22_hvt (
y,
a,
b,
c,
d
);
output y;
input a;
input b;
input c;
input d;
assign y = !((a & b) | (c & d));
endmodule
| 7.596161 |
module mux2_4lutx1_hvt_g (
out,
in0,
in1,
sel,
sel_b
);
output out;
input in0;
input in1;
input sel;
input sel_b;
assign out = (sel) ? in1 : in0;
endmodule
| 7.419326 |
module mux2x1_hvt (
out,
in0,
in1,
sel
);
output out;
input in0;
input in1;
input sel;
assign out = (sel) ? in1 : in0;
endmodule
| 8.134428 |
module clut4 (lut4, in0, in1, in2, in3, in0b, in1b, in2b, in3b, cbit);
//the output signal
output lut4;
//the input signals
input in0, in1, in2, in3, in0b, in1b, in2b, in3b;
input [15:0] cbit;
reg lut4;
`ifdef TIMINGCHECK
specify
// delay parameters
specparam
tplh$cbit0$lut4= 1.0,
tphl$c... | 7.764978 |
module cram_cell_3 (
q,
q_b,
bl,
r_gnd,
reset_b,
wl
);
output q;
output q_b;
inout bl;
input r_gnd;
input reset_b;
input wl;
reg q, blreg;
always @(bl or r_gnd or reset_b or wl)
if ((r_gnd == 1'b0) && (reset_b == 1'b0)) q = 1'b0;
else if ((wl == 1'b1) && (bl == 1'b0)) q =... | 6.620075 |
module mux2_defaultHigh (
Y,
A,
S0
);
output Y;
input A;
input S0;
reg Y;
always @(A or S0)
if (S0 == 1'b0) Y = 1'b1;
else Y = A;
endmodule
| 6.905997 |
module osc_logic (
clkin,
smc_oscen,
smc_osc_fsel,
sel_trim
);
input clkin;
input smc_oscen;
input [1:0] smc_osc_fsel;
output [3:0] sel_trim;
//Signal declaration
wire [2:0] in_sel;
wire clkin_buf_b;
wire reset_ff;
wire clkin_buf;
wire clkin_buf_delay;
reg i174q;
reg i238q;
r... | 6.74015 |
module carry_logic_nand (
cout,
carry_in,
a,
a_bar,
b,
b_bar,
vg_en
);
//the output signal
output cout;
//the input signals
input carry_in, a, a_bar, b, b_bar, vg_en;
`ifdef TIMINGCHECK
specify
// delay parameters
specparam
tplh$carry_in$cout= 1.0,
tphl$carry... | 6.500349 |
module nch_na25_macx (
D,
S,
G
);
inout D;
input G, S;
nmos (D, S, G); // D S G
//nmos (S, D, ~G); // D S G
endmodule
| 6.508578 |
module nand3_lvt (
A,
B,
C,
Y
);
input A, B, C;
output Y;
assign Y = ~(A & B & C);
endmodule
| 8.437168 |
module and2p_18_g (
y,
a,
b,
bb,
gnd_node
);
output y;
input a;
input b;
input bb;
input gnd_node;
reg y;
always @(a or b or bb or gnd_node) begin
if ((bb == 1'b1) && (b == 1'b0) && (gnd_node == 0)) y = 1'b0;
else if ((b == 1'b1) && (bb == 1'b0) && (gnd_node == 0)) y = a;
... | 6.576802 |
module anor21_18_g (
Y,
A,
B,
C,
gnd_node
);
output Y;
input A;
input B;
input C;
input gnd_node;
assign Y = ~(C | (B * A));
endmodule
| 7.012558 |
module anor21_25 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(C | (B * A));
endmodule
| 7.251959 |
module anor21_25_g (
Y,
A,
B,
C,
gnd_node
);
output Y;
input A;
input B;
input C;
input gnd_node;
assign Y = ~(C | (B * A));
endmodule
| 7.004077 |
module anor21_33 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(C | (B * A));
endmodule
| 7.02011 |
module anor21_33_g (
Y,
A,
B,
C,
gnd_node
);
output Y;
input A;
input B;
input C;
input gnd_node;
initial begin
Y = 1;
end
reg Y;
always @(A or B or C or gnd_node) assign Y = ~(C | (B * A));
endmodule
| 6.575641 |
module anor21_g (
Y,
A,
B,
C,
gnd_node
);
output Y;
input A;
input B;
input C;
input gnd_node;
initial begin
Y = 1;
end
reg Y;
always @(A or B or C or gnd_node) assign Y = ~(C | (B * A));
endmodule
| 6.575116 |
module anor21_hvt (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
initial begin
Y = 1;
end
reg Y;
always @(A or B or C) assign Y = ~(C | (B * A));
endmodule
| 6.919113 |
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