code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module takes in an array of signed integers and performs the parity polytope projection similarity
transform using f to define the transform.
Doing this for the centered parity polytope projection though.
we assume the fixed point representation has at least one integer bit.
we also assume that the input vector does... | 6.546226 |
module performs L1 penalization when enabled in the admm decoding.
basically looks at the prepenalty and decides whether to add or subtract the
penalty parameter.
*/
`include "2dArrayMacros.v"
module CenteredVariableNodeL1Penalty #
(
parameter TAG_WIDTH = 32,
parameter DATA_WIDTH = 18,
parameter FRACTION_WIDTH =... | 7.458385 |
module centipede_verilator;
reg clk /*verilator public_flat*/;
reg reset /*verilator public_flat*/;
wire [8:0] rgb;
wire csync, hsync, vsync, hblank, vblank;
wire [7:0] audio;
wire [3:0] led /*verilator public_flat*/;
reg [7:0] trakball /*verilator public_flat*/;
reg [7:0] joystick /*verilator... | 6.776918 |
module centisecond (
input [4:0] state,
input is_modify,
input i_plus,
input i_minus,
input i_enable,
input i_clk_0_001s,
output reg o_enable,
output reg [14:0] o_centisecond
);
wire reset = 1;
reg r_enable = 0;
reg r_enable_falling = 0;
initial begin
o_centisecond <= 0;... | 7.477625 |
module top_controller (
LED,
SF_D,
LCD_E,
LCD_RS,
LCD_RW,
motor1,
motor2,
motor_enable,
echo_pin,
trig_pin,
clock,
reset,
speed_udata,
start_mod,
data_in,
Rx_D
);
input clock, reset, start_mod, speed_udata, Rx_D, echo_pin;
input [3:0] data_in;
output... | 6.952172 |
module centre_coords (
input wire clk,
input wire [9:0] x_i,
input wire [9:0] y_i,
output reg signed [9:0] x_o,
output reg signed [9:0] y_o
);
always @(posedge clk) begin
x_o <= x_i - 10'd320;
y_o <= y_i - 10'd240;
end
endmodule
| 6.79477 |
module centroid #(
parameter DATA_WIDTH = 8,
parameter INTERNAL_WIDTH = 32
) (
data_in_x,
data_in_y,
data_enable,
data_end,
centroid_x,
centroid_y,
done,
clk
);
input [DATA_WIDTH-1:0] data_in_x, data_in_y;
input data_enable, data_end;
output reg [DATA_WIDTH-1:0] centroid_x... | 7.888009 |
module
//
///////////////////////////////////////////////////////////////////////////////
module centroid_disp #(parameter HEIGHT=8, WIDTH=8, COLOR=8'hFF) (reset, clk, hcount, vcount, x, y, pixel);
input reset, clk;
input [10:0] hcount, x;
input [9:0] vcount, y;
output reg [7:0] pixel;
always @ (... | 6.711776 |
module ram (
q,
a,
d,
we,
clk
);
output reg [15:0] q;
input [15:0] d;
input [18:0] a;
input we, clk;
(* ram_init_file = "mem_init.mif" *) reg [15:0] mem[0:524288];
always @(posedge clk) begin
if (we) mem[a] <= d;
q <= mem[a];
end
endmodule
| 6.606788 |
module
// DEPARTMENT : Design
// AUTHOR : Shuang Li
// AUTHOR S EMAIL : lishuang@hhic.com
//------------------------------------------------------------------------
// Release history
// VERSION | Date | AUTHOR | DESCRIPTION
// 0.1 | 09/4/23 | Shuang Li | combination logic for ram/rom interface
//... | 8.923686 |
module DIG_D_FF_1bit #(
parameter Default = 0
) (
input D,
input C,
output Q,
output \~Q
);
reg state;
assign Q = state;
assign \~Q = ~state;
always @(posedge C) begin
state <= D;
end
initial begin
state = Default;
end
endmodule
| 7.281973 |
module Mux_2x1_NBits #(
parameter Bits = 2
) (
input [0:0] sel,
input [(Bits - 1):0] in_0,
input [(Bits - 1):0] in_1,
output reg [(Bits - 1):0] out
);
always @(*) begin
case (sel)
1'h0: out = in_0;
1'h1: out = in_1;
default: out = 'h0;
endcase
end
endmodule
| 7.601417 |
module Mux_2x1 (
input [0:0] sel,
input in_0,
input in_1,
output reg out
);
always @(*) begin
case (sel)
1'h0: out = in_0;
1'h1: out = in_1;
default: out = 'h0;
endcase
end
endmodule
| 7.687432 |
module DIG_Mul_unsigned #(
parameter Bits = 1
) (
input [ (Bits-1):0] a,
input [ (Bits-1):0] b,
output [(Bits*2-1):0] mul
);
assign mul = a * b;
endmodule
| 7.903934 |
module CompUnsigned #(
parameter Bits = 1
) (
input [(Bits -1):0] a,
input [(Bits -1):0] b,
output \> ,
output \= ,
output \<
);
assign \> = a > b;
assign \= = a == b;
assign \< = a < b;
endmodule
| 7.589549 |
module DIG_Add #(
parameter Bits = 1
) (
input [(Bits-1):0] a,
input [(Bits-1):0] b,
input c_i,
output [(Bits - 1):0] s,
output c_o
);
wire [Bits:0] temp;
assign temp = a + b + c_i;
assign s = temp[(Bits-1):0];
assign c_o = temp[Bits];
endmodule
| 8.533091 |
module Decoder3 (
output out_0,
output out_1,
output out_2,
output out_3,
output out_4,
output out_5,
output out_6,
output out_7,
input [2:0] sel
);
assign out_0 = (sel == 3'h0) ? 1'b1 : 1'b0;
assign out_1 = (sel == 3'h1) ? 1'b1 : 1'b0;
assign out_2 = (sel == 3'h2) ? 1'b1 : 1'b... | 7.068059 |
module PriorityEncoder3 (
input in0,
input in1,
input in2,
input in3,
input in4,
input in5,
input in6,
input in7,
output reg [2:0] num,
output any
);
always @(*) begin
if (in7 == 1'b1) num = 3'h7;
else if (in6 == 1'b1) num = 3'h6;
else if (in5 == 1'b1) num = 3'h5;
... | 6.599169 |
module CE_DFF (
input C,
input D, // Data In
input E, // Enable
input R, // Reset
output Q, // Output
output nQ // Inverted Output
);
wire Q_temp;
wire s0;
wire s1;
wire s2;
assign s1 = (E | R);
Mux_2x1 Mux_2x1_i0 (
.sel (R),
.in_0(D),
.in_1(1'b0),
.... | 6.759543 |
module Mux_4x1 (
input [1:0] sel,
input in_0,
input in_1,
input in_2,
input in_3,
output reg out
);
always @(*) begin
case (sel)
2'h0: out = in_0;
2'h1: out = in_1;
2'h2: out = in_2;
2'h3: out = in_3;
default: out = 'h0;
endcase
end
endmodule
| 7.426047 |
module Mux_16x1_NBits #(
parameter Bits = 2
) (
input [3:0] sel,
input [(Bits - 1):0] in_0,
input [(Bits - 1):0] in_1,
input [(Bits - 1):0] in_2,
input [(Bits - 1):0] in_3,
input [(Bits - 1):0] in_4,
input [(Bits - 1):0] in_5,
input [(Bits - 1):0] in_6,
input [(Bits - 1):0] in_7,... | 7.907715 |
module Mux_16x1 (
input [3:0] sel,
input in_0,
input in_1,
input in_2,
input in_3,
input in_4,
input in_5,
input in_6,
input in_7,
input in_8,
input in_9,
input in_10,
input in_11,
input in_12,
input in_13,
input in_14,
input in_15,
output reg out
... | 7.562822 |
module Mux_8x1_NBits #(
parameter Bits = 2
) (
input [2:0] sel,
input [(Bits - 1):0] in_0,
input [(Bits - 1):0] in_1,
input [(Bits - 1):0] in_2,
input [(Bits - 1):0] in_3,
input [(Bits - 1):0] in_4,
input [(Bits - 1):0] in_5,
input [(Bits - 1):0] in_6,
input [(Bits - 1):0] in_7,
... | 7.571634 |
module DIG_BitExtenderSingle #(
parameter outputBits = 2
) (
input in,
output [(outputBits - 1):0] out
);
assign out = {outputBits{in}};
endmodule
| 9.667277 |
module Mux_4x1_NBits #(
parameter Bits = 2
) (
input [1:0] sel,
input [(Bits - 1):0] in_0,
input [(Bits - 1):0] in_1,
input [(Bits - 1):0] in_2,
input [(Bits - 1):0] in_3,
output reg [(Bits - 1):0] out
);
always @(*) begin
case (sel)
2'h0: out = in_0;
2'h1: out = in_1;
... | 7.9033 |
module Mux_8x1 (
input [2:0] sel,
input in_0,
input in_1,
input in_2,
input in_3,
input in_4,
input in_5,
input in_6,
input in_7,
output reg out
);
always @(*) begin
case (sel)
3'h0: out = in_0;
3'h1: out = in_1;
3'h2: out = in_2;
3'h3: out = in_3;
... | 7.354699 |
module DIG_BitExtender #(
parameter inputBits = 2,
parameter outputBits = 4
) (
input [(inputBits-1):0] in,
output [(outputBits - 1):0] out
);
assign out = {{(outputBits - inputBits) {in[inputBits-1]}}, in};
endmodule
| 9.667277 |
module Demux3 (
output out_0,
output out_1,
output out_2,
output out_3,
output out_4,
output out_5,
output out_6,
output out_7,
input [2:0] sel,
input in
);
assign out_0 = (sel == 3'h0) ? in : 'd0;
assign out_1 = (sel == 3'h1) ? in : 'd0;
assign out_2 = (sel == 3'h2) ? in :... | 7.440412 |
module DIG_ROM_16X5_AOS (
input [3:0] A,
input sel,
output reg [4:0] D
);
reg [4:0] my_rom[0:15];
always @(*) begin
if (~sel) D = 5'hz;
else D = my_rom[A];
end
initial begin
my_rom[0] = 5'h0;
my_rom[1] = 5'h4;
my_rom[2] = 5'hc;
my_rom[3] = 5'h14;
my_rom[4] = 5'h1c;... | 8.159378 |
module DIG_Register_BUS #(
parameter Bits = 1
) (
input C,
input en,
input [(Bits - 1):0] D,
output [(Bits - 1):0] Q
);
reg [(Bits - 1):0] state = 'h0;
assign Q = state;
always @(posedge C) begin
if (en) state <= D;
end
endmodule
| 8.228131 |
module CE_PRE (
input R,
input C,
input L,
input [7:0] IN,
input [7:0] PR,
output [7:0] Q
);
wire s0;
wire [7:0] s1;
wire s2;
wire s3;
wire s4;
assign s3 = (L | R);
// REG
DIG_Register_BUS #(
.Bits(8)
) DIG_Register_BUS_i0 (
.D (IN),
.C (C),
.en(s3),
... | 6.520074 |
module DIG_Neg #(
parameter Bits = 1
) (
input signed [(Bits-1):0] in,
output signed [(Bits-1):0] out
);
assign out = -in;
endmodule
| 7.822999 |
module DIG_JK_FF #(
parameter Default = 1'b0
) (
input J,
input C,
input K,
output Q,
output \~Q
);
reg state;
assign Q = state;
assign \~Q = ~state;
always @(posedge C) begin
if (~J & K) state <= 1'b0;
else if (J & ~K) state <= 1'b1;
else if (J & K) state <= ~state;
... | 7.329802 |
module CE_JKFF (
input C,
input J,
input K,
input R,
output Q,
output \~Q
);
wire s0;
wire s1;
assign s0 = (J & ~R);
assign s1 = (K | R);
DIG_JK_FF #(
.Default(0)
) DIG_JK_FF_i0 (
.J(s0),
.C(C),
.K(s1),
.Q(Q),
.\~Q (\~Q )
);
endmodule
| 7.241376 |
module CE_EDFF (
input R, // Reset
input C,
input IN, // Input
output Q,
output \~Q
);
wire s0;
wire s1;
Mux_2x1 Mux_2x1_i0 (
.sel (R),
.in_0(IN),
.in_1(C),
.out (s1)
);
assign s0 = ~R;
DIG_D_FF_1bit #(
.Default(0)
) DIG_D_FF_1bit_i1 (
.D(s0),
... | 6.8538 |
module DIG_ROM_8X8_INA (
input [2:0] A,
input sel,
output reg [7:0] D
);
reg [7:0] my_rom[0:4];
always @(*) begin
if (~sel) D = 8'hz;
else if (A > 3'h4) D = 8'h0;
else D = my_rom[A];
end
initial begin
my_rom[0] = 8'h93;
my_rom[1] = 8'h89;
my_rom[2] = 8'h8d;
my_rom[3] = ... | 7.725301 |
module DIG_ROM_2X8_RES (
input [0:0] A,
input sel,
output reg [7:0] D
);
reg [7:0] my_rom[0:1];
always @(*) begin
if (~sel) D = 8'hz;
else D = my_rom[A];
end
initial begin
my_rom[0] = 8'h79;
my_rom[1] = 8'ha9;
end
endmodule
| 8.451676 |
module DIG_ROM_128X8_INST1 (
input [6:0] A,
input sel,
output reg [7:0] D
);
reg [7:0] my_rom[0:64];
always @(*) begin
if (~sel) D = 8'hz;
else if (A > 7'h40) D = 8'h0;
else D = my_rom[A];
end
initial begin
my_rom[0] = 8'h99;
my_rom[1] = 8'h0;
my_rom[2] = 8'h0;
my_ro... | 7.469709 |
module PriorityEncoder2 (
input in0,
input in1,
input in2,
input in3,
output reg [1:0] num,
output any
);
always @(*) begin
if (in3 == 1'b1) num = 2'h3;
else if (in2 == 1'b1) num = 2'h2;
else if (in1 == 1'b1) num = 2'h1;
else num = 2'h0;
end
assign any = in0 | in1 | in2 | ... | 6.599169 |
module DIG_ROM_8X2_PRI (
input [2:0] A,
input sel,
output reg [1:0] D
);
reg [1:0] my_rom[0:7];
always @(*) begin
if (~sel) D = 2'hz;
else D = my_rom[A];
end
initial begin
my_rom[0] = 2'h0;
my_rom[1] = 2'h3;
my_rom[2] = 2'h0;
my_rom[3] = 2'h1;
my_rom[4] = 2'h0;
my_r... | 7.619917 |
module CE_M_CPU (
input R_CPU, // Reset
input C_CPU,
input [7:0] DI_CPU, // Data Input
input nIRQ_CPU, // Interrupt Request
input nNMI_CPU, // Non-Maskable Interrupt
input nABT_CPU, // Abort
input nSOB_CPU, // Set Overflow Bit
input nRDY_CPU, // Ready
input BE_CPU, // Bus Ena... | 6.688177 |
module DIG_D_FF_1bit #(
parameter Default = 0
) (
input D,
input C,
output Q,
output \~Q
);
reg state;
assign Q = state;
assign \~Q = ~state;
always @(posedge C) begin
state <= D;
end
initial begin
state = Default;
end
endmodule
| 7.281973 |
module Mux_2x1_NBits #(
parameter Bits = 2
) (
input [0:0] sel,
input [(Bits - 1):0] in_0,
input [(Bits - 1):0] in_1,
output reg [(Bits - 1):0] out
);
always @(*) begin
case (sel)
1'h0: out = in_0;
1'h1: out = in_1;
default: out = 'h0;
endcase
end
endmodule
| 7.601417 |
module Mux_2x1 (
input [0:0] sel,
input in_0,
input in_1,
output reg out
);
always @(*) begin
case (sel)
1'h0: out = in_0;
1'h1: out = in_1;
default: out = 'h0;
endcase
end
endmodule
| 7.687432 |
module DIG_Mul_unsigned #(
parameter Bits = 1
) (
input [ (Bits-1):0] a,
input [ (Bits-1):0] b,
output [(Bits*2-1):0] mul
);
assign mul = a * b;
endmodule
| 7.903934 |
module CompUnsigned #(
parameter Bits = 1
) (
input [(Bits -1):0] a,
input [(Bits -1):0] b,
output \> ,
output \= ,
output \<
);
assign \> = a > b;
assign \= = a == b;
assign \< = a < b;
endmodule
| 7.589549 |
module DIG_Add #(
parameter Bits = 1
) (
input [(Bits-1):0] a,
input [(Bits-1):0] b,
input c_i,
output [(Bits - 1):0] s,
output c_o
);
wire [Bits:0] temp;
assign temp = a + b + c_i;
assign s = temp[(Bits-1):0];
assign c_o = temp[Bits];
endmodule
| 8.533091 |
module Decoder3 (
output out_0,
output out_1,
output out_2,
output out_3,
output out_4,
output out_5,
output out_6,
output out_7,
input [2:0] sel
);
assign out_0 = (sel == 3'h0) ? 1'b1 : 1'b0;
assign out_1 = (sel == 3'h1) ? 1'b1 : 1'b0;
assign out_2 = (sel == 3'h2) ? 1'b1 : 1'b... | 7.068059 |
module PriorityEncoder3 (
input in0,
input in1,
input in2,
input in3,
input in4,
input in5,
input in6,
input in7,
output reg [2:0] num,
output any
);
always @(*) begin
if (in7 == 1'b1) num = 3'h7;
else if (in6 == 1'b1) num = 3'h6;
else if (in5 == 1'b1) num = 3'h5;
... | 6.599169 |
module DIG_Register_BUS #(
parameter Bits = 1
) (
input C,
input en,
input [(Bits - 1):0] D,
output [(Bits - 1):0] Q
);
reg [(Bits - 1):0] state = 'h0;
assign Q = state;
always @(posedge C) begin
if (en) state <= D;
end
endmodule
| 8.228131 |
module DIG_Sub #(
parameter Bits = 2
) (
input [(Bits-1):0] a,
input [(Bits-1):0] b,
input c_i,
output [(Bits-1):0] s,
output c_o
);
wire [Bits:0] temp;
assign temp = a - b - c_i;
assign s = temp[(Bits-1):0];
assign c_o = temp[Bits];
endmodule
| 7.610127 |
module DIG_JK_FF #(
parameter Default = 1'b0
) (
input J,
input C,
input K,
output Q,
output \~Q
);
reg state;
assign Q = state;
assign \~Q = ~state;
always @(posedge C) begin
if (~J & K) state <= 1'b0;
else if (J & ~K) state <= 1'b1;
else if (J & K) state <= ~state;
... | 7.329802 |
module CE_DFF (
input C,
input D, // Data In
input E, // Enable
input R, // Reset
output Q, // Output
output nQ // Inverted Output
);
wire Q_temp;
wire s0;
wire s1;
wire s2;
assign s1 = (E | R);
Mux_2x1 Mux_2x1_i0 (
.sel (R),
.in_0(D),
.in_1(1'b0),
.... | 6.759543 |
module Mux_4x1 (
input [1:0] sel,
input in_0,
input in_1,
input in_2,
input in_3,
output reg out
);
always @(*) begin
case (sel)
2'h0: out = in_0;
2'h1: out = in_1;
2'h2: out = in_2;
2'h3: out = in_3;
default: out = 'h0;
endcase
end
endmodule
| 7.426047 |
module Mux_16x1_NBits #(
parameter Bits = 2
) (
input [3:0] sel,
input [(Bits - 1):0] in_0,
input [(Bits - 1):0] in_1,
input [(Bits - 1):0] in_2,
input [(Bits - 1):0] in_3,
input [(Bits - 1):0] in_4,
input [(Bits - 1):0] in_5,
input [(Bits - 1):0] in_6,
input [(Bits - 1):0] in_7,... | 7.907715 |
module Mux_16x1 (
input [3:0] sel,
input in_0,
input in_1,
input in_2,
input in_3,
input in_4,
input in_5,
input in_6,
input in_7,
input in_8,
input in_9,
input in_10,
input in_11,
input in_12,
input in_13,
input in_14,
input in_15,
output reg out
... | 7.562822 |
module Mux_8x1_NBits #(
parameter Bits = 2
) (
input [2:0] sel,
input [(Bits - 1):0] in_0,
input [(Bits - 1):0] in_1,
input [(Bits - 1):0] in_2,
input [(Bits - 1):0] in_3,
input [(Bits - 1):0] in_4,
input [(Bits - 1):0] in_5,
input [(Bits - 1):0] in_6,
input [(Bits - 1):0] in_7,
... | 7.571634 |
module DIG_BitExtenderSingle #(
parameter outputBits = 2
) (
input in,
output [(outputBits - 1):0] out
);
assign out = {outputBits{in}};
endmodule
| 9.667277 |
module Mux_4x1_NBits #(
parameter Bits = 2
) (
input [1:0] sel,
input [(Bits - 1):0] in_0,
input [(Bits - 1):0] in_1,
input [(Bits - 1):0] in_2,
input [(Bits - 1):0] in_3,
output reg [(Bits - 1):0] out
);
always @(*) begin
case (sel)
2'h0: out = in_0;
2'h1: out = in_1;
... | 7.9033 |
module Mux_8x1 (
input [2:0] sel,
input in_0,
input in_1,
input in_2,
input in_3,
input in_4,
input in_5,
input in_6,
input in_7,
output reg out
);
always @(*) begin
case (sel)
3'h0: out = in_0;
3'h1: out = in_1;
3'h2: out = in_2;
3'h3: out = in_3;
... | 7.354699 |
module DIG_BitExtender #(
parameter inputBits = 2,
parameter outputBits = 4
) (
input [(inputBits-1):0] in,
output [(outputBits - 1):0] out
);
assign out = {{(outputBits - inputBits) {in[inputBits-1]}}, in};
endmodule
| 9.667277 |
module Demux3 (
output out_0,
output out_1,
output out_2,
output out_3,
output out_4,
output out_5,
output out_6,
output out_7,
input [2:0] sel,
input in
);
assign out_0 = (sel == 3'h0) ? in : 'd0;
assign out_1 = (sel == 3'h1) ? in : 'd0;
assign out_2 = (sel == 3'h2) ? in :... | 7.440412 |
module DIG_ROM_16X5_AOS (
input [3:0] A,
input sel,
output reg [4:0] D
);
reg [4:0] my_rom[0:15];
always @(*) begin
if (~sel) D = 5'hz;
else D = my_rom[A];
end
initial begin
my_rom[0] = 5'h0;
my_rom[1] = 5'h4;
my_rom[2] = 5'hc;
my_rom[3] = 5'h14;
my_rom[4] = 5'h1c;... | 8.159378 |
module CE_PRE (
input R,
input C,
input L,
input [7:0] IN,
input [7:0] PR,
output [7:0] Q
);
wire s0;
wire [7:0] s1;
wire s2;
wire s3;
wire s4;
assign s3 = (L | R);
// REG
DIG_Register_BUS #(
.Bits(8)
) DIG_Register_BUS_i0 (
.D (IN),
.C (C),
.en(s3),
... | 6.520074 |
module DIG_Neg #(
parameter Bits = 1
) (
input signed [(Bits-1):0] in,
output signed [(Bits-1):0] out
);
assign out = -in;
endmodule
| 7.822999 |
module CE_JKFF (
input C,
input J,
input K,
input R,
output Q,
output \~Q
);
wire s0;
wire s1;
assign s0 = (J & ~R);
assign s1 = (K | R);
DIG_JK_FF #(
.Default(0)
) DIG_JK_FF_i0 (
.J(s0),
.C(C),
.K(s1),
.Q(Q),
.\~Q (\~Q )
);
endmodule
| 7.241376 |
module CE_EDFF (
input R, // Reset
input C,
input IN, // Input
output Q,
output \~Q
);
wire s0;
wire s1;
Mux_2x1 Mux_2x1_i0 (
.sel (R),
.in_0(IN),
.in_1(C),
.out (s1)
);
assign s0 = ~R;
DIG_D_FF_1bit #(
.Default(0)
) DIG_D_FF_1bit_i1 (
.D(s0),
... | 6.8538 |
module DIG_ROM_8X8_INA (
input [2:0] A,
input sel,
output reg [7:0] D
);
reg [7:0] my_rom[0:4];
always @(*) begin
if (~sel) D = 8'hz;
else if (A > 3'h4) D = 8'h0;
else D = my_rom[A];
end
initial begin
my_rom[0] = 8'h93;
my_rom[1] = 8'h89;
my_rom[2] = 8'h8d;
my_rom[3] = ... | 7.725301 |
module DIG_ROM_2X8_RES (
input [0:0] A,
input sel,
output reg [7:0] D
);
reg [7:0] my_rom[0:1];
always @(*) begin
if (~sel) D = 8'hz;
else D = my_rom[A];
end
initial begin
my_rom[0] = 8'h79;
my_rom[1] = 8'ha9;
end
endmodule
| 8.451676 |
module DIG_ROM_128X8_INST1 (
input [6:0] A,
input sel,
output reg [7:0] D
);
reg [7:0] my_rom[0:118];
always @(*) begin
if (~sel) D = 8'hz;
else if (A > 7'h76) D = 8'h0;
else D = my_rom[A];
end
initial begin
my_rom[0] = 8'h99;
my_rom[1] = 8'h0;
my_rom[2] = 8'h0;
m... | 7.469709 |
module PriorityEncoder2 (
input in0,
input in1,
input in2,
input in3,
output reg [1:0] num,
output any
);
always @(*) begin
if (in3 == 1'b1) num = 2'h3;
else if (in2 == 1'b1) num = 2'h2;
else if (in1 == 1'b1) num = 2'h1;
else num = 2'h0;
end
assign any = in0 | in1 | in2 | ... | 6.599169 |
module DIG_ROM_8X2_PRI (
input [2:0] A,
input sel,
output reg [1:0] D
);
reg [1:0] my_rom[0:7];
always @(*) begin
if (~sel) D = 2'hz;
else D = my_rom[A];
end
initial begin
my_rom[0] = 2'h0;
my_rom[1] = 2'h3;
my_rom[2] = 2'h0;
my_rom[3] = 2'h1;
my_rom[4] = 2'h0;
my_r... | 7.619917 |
module DIG_PinControl #(
parameter Bits = 2
) (
inout [(Bits-1):0] pin,
input oe,
input [(Bits-1):0] wr,
output [(Bits-1):0] rd
);
assign pin = oe ? wr : {Bits{1'bz}};
assign rd = oe ? wr : pin;
endmodule
| 8.655407 |
module DIG_BlockRAMDualPort #(
parameter Bits = 8,
parameter AddrBits = 4
) (
input [(AddrBits-1):0] A,
input [(Bits-1):0] Din,
input str,
input C,
output [(Bits-1):0] D
);
reg [(Bits-1):0] memory[0:((1 << AddrBits) - 1)];
reg [(Bits-1):0] wData;
assign D = wData;
always @(posedge ... | 9.323278 |
module DIG_Register_BUS #(
parameter Bits = 1
) (
input C,
input en,
input [(Bits - 1):0] D,
output [(Bits - 1):0] Q
);
reg [(Bits - 1):0] state = 'h0;
assign Q = state;
always @(posedge C) begin
if (en) state <= D;
end
endmodule
| 8.228131 |
module DIG_D_FF_1bit #(
parameter Default = 0
) (
input D,
input C,
output Q,
output \~Q
);
reg state;
assign Q = state;
assign \~Q = ~state;
always @(posedge C) begin
state <= D;
end
initial begin
state = Default;
end
endmodule
| 7.281973 |
module Mux_2x1_NBits #(
parameter Bits = 2
) (
input [0:0] sel,
input [(Bits - 1):0] in_0,
input [(Bits - 1):0] in_1,
output reg [(Bits - 1):0] out
);
always @(*) begin
case (sel)
1'h0: out = in_0;
1'h1: out = in_1;
default: out = 'h0;
endcase
end
endmodule
| 7.601417 |
module Mux_2x1 (
input [0:0] sel,
input in_0,
input in_1,
output reg out
);
always @(*) begin
case (sel)
1'h0: out = in_0;
1'h1: out = in_1;
default: out = 'h0;
endcase
end
endmodule
| 7.687432 |
module DIG_Mul_unsigned #(
parameter Bits = 1
) (
input [ (Bits-1):0] a,
input [ (Bits-1):0] b,
output [(Bits*2-1):0] mul
);
assign mul = a * b;
endmodule
| 7.903934 |
module CompUnsigned #(
parameter Bits = 1
) (
input [(Bits -1):0] a,
input [(Bits -1):0] b,
output \> ,
output \= ,
output \<
);
assign \> = a > b;
assign \= = a == b;
assign \< = a < b;
endmodule
| 7.589549 |
module DIG_Add #(
parameter Bits = 1
) (
input [(Bits-1):0] a,
input [(Bits-1):0] b,
input c_i,
output [(Bits - 1):0] s,
output c_o
);
wire [Bits:0] temp;
assign temp = a + b + c_i;
assign s = temp[(Bits-1):0];
assign c_o = temp[Bits];
endmodule
| 8.533091 |
module Decoder3 (
output out_0,
output out_1,
output out_2,
output out_3,
output out_4,
output out_5,
output out_6,
output out_7,
input [2:0] sel
);
assign out_0 = (sel == 3'h0) ? 1'b1 : 1'b0;
assign out_1 = (sel == 3'h1) ? 1'b1 : 1'b0;
assign out_2 = (sel == 3'h2) ? 1'b1 : 1'b... | 7.068059 |
module PriorityEncoder3 (
input in0,
input in1,
input in2,
input in3,
input in4,
input in5,
input in6,
input in7,
output reg [2:0] num,
output any
);
always @(*) begin
if (in7 == 1'b1) num = 3'h7;
else if (in6 == 1'b1) num = 3'h6;
else if (in5 == 1'b1) num = 3'h5;
... | 6.599169 |
module DIG_Sub #(
parameter Bits = 2
) (
input [(Bits-1):0] a,
input [(Bits-1):0] b,
input c_i,
output [(Bits-1):0] s,
output c_o
);
wire [Bits:0] temp;
assign temp = a - b - c_i;
assign s = temp[(Bits-1):0];
assign c_o = temp[Bits];
endmodule
| 7.610127 |
module DIG_JK_FF #(
parameter Default = 1'b0
) (
input J,
input C,
input K,
output Q,
output \~Q
);
reg state;
assign Q = state;
assign \~Q = ~state;
always @(posedge C) begin
if (~J & K) state <= 1'b0;
else if (J & ~K) state <= 1'b1;
else if (J & K) state <= ~state;
... | 7.329802 |
module CE_DFF (
input C,
input D, // Data In
input E, // Enable
input R, // Reset
output Q, // Output
output nQ // Inverted Output
);
wire Q_temp;
wire s0;
wire s1;
wire s2;
assign s1 = (E | R);
Mux_2x1 Mux_2x1_i0 (
.sel (R),
.in_0(D),
.in_1(1'b0),
.... | 6.759543 |
module Mux_4x1 (
input [1:0] sel,
input in_0,
input in_1,
input in_2,
input in_3,
output reg out
);
always @(*) begin
case (sel)
2'h0: out = in_0;
2'h1: out = in_1;
2'h2: out = in_2;
2'h3: out = in_3;
default: out = 'h0;
endcase
end
endmodule
| 7.426047 |
module Mux_16x1_NBits #(
parameter Bits = 2
) (
input [3:0] sel,
input [(Bits - 1):0] in_0,
input [(Bits - 1):0] in_1,
input [(Bits - 1):0] in_2,
input [(Bits - 1):0] in_3,
input [(Bits - 1):0] in_4,
input [(Bits - 1):0] in_5,
input [(Bits - 1):0] in_6,
input [(Bits - 1):0] in_7,... | 7.907715 |
module Mux_16x1 (
input [3:0] sel,
input in_0,
input in_1,
input in_2,
input in_3,
input in_4,
input in_5,
input in_6,
input in_7,
input in_8,
input in_9,
input in_10,
input in_11,
input in_12,
input in_13,
input in_14,
input in_15,
output reg out
... | 7.562822 |
module Mux_8x1_NBits #(
parameter Bits = 2
) (
input [2:0] sel,
input [(Bits - 1):0] in_0,
input [(Bits - 1):0] in_1,
input [(Bits - 1):0] in_2,
input [(Bits - 1):0] in_3,
input [(Bits - 1):0] in_4,
input [(Bits - 1):0] in_5,
input [(Bits - 1):0] in_6,
input [(Bits - 1):0] in_7,
... | 7.571634 |
module DIG_BitExtenderSingle #(
parameter outputBits = 2
) (
input in,
output [(outputBits - 1):0] out
);
assign out = {outputBits{in}};
endmodule
| 9.667277 |
module Mux_4x1_NBits #(
parameter Bits = 2
) (
input [1:0] sel,
input [(Bits - 1):0] in_0,
input [(Bits - 1):0] in_1,
input [(Bits - 1):0] in_2,
input [(Bits - 1):0] in_3,
output reg [(Bits - 1):0] out
);
always @(*) begin
case (sel)
2'h0: out = in_0;
2'h1: out = in_1;
... | 7.9033 |
module Mux_8x1 (
input [2:0] sel,
input in_0,
input in_1,
input in_2,
input in_3,
input in_4,
input in_5,
input in_6,
input in_7,
output reg out
);
always @(*) begin
case (sel)
3'h0: out = in_0;
3'h1: out = in_1;
3'h2: out = in_2;
3'h3: out = in_3;
... | 7.354699 |
module DIG_BitExtender #(
parameter inputBits = 2,
parameter outputBits = 4
) (
input [(inputBits-1):0] in,
output [(outputBits - 1):0] out
);
assign out = {{(outputBits - inputBits) {in[inputBits-1]}}, in};
endmodule
| 9.667277 |
module Demux3 (
output out_0,
output out_1,
output out_2,
output out_3,
output out_4,
output out_5,
output out_6,
output out_7,
input [2:0] sel,
input in
);
assign out_0 = (sel == 3'h0) ? in : 'd0;
assign out_1 = (sel == 3'h1) ? in : 'd0;
assign out_2 = (sel == 3'h2) ? in :... | 7.440412 |
module DIG_ROM_16X5_AOS (
input [3:0] A,
input sel,
output reg [4:0] D
);
reg [4:0] my_rom[0:15];
always @(*) begin
if (~sel) D = 5'hz;
else D = my_rom[A];
end
initial begin
my_rom[0] = 5'h0;
my_rom[1] = 5'h4;
my_rom[2] = 5'hc;
my_rom[3] = 5'h14;
my_rom[4] = 5'h1c;... | 8.159378 |
module CE_PRE (
input R,
input C,
input L,
input [7:0] IN,
input [7:0] PR,
output [7:0] Q
);
wire s0;
wire [7:0] s1;
wire s2;
wire s3;
wire s4;
assign s3 = (L | R);
// REG
DIG_Register_BUS #(
.Bits(8)
) DIG_Register_BUS_i0 (
.D (IN),
.C (C),
.en(s3),
... | 6.520074 |
module DIG_Neg #(
parameter Bits = 1
) (
input signed [(Bits-1):0] in,
output signed [(Bits-1):0] out
);
assign out = -in;
endmodule
| 7.822999 |
module CE_JKFF (
input C,
input J,
input K,
input R,
output Q,
output \~Q
);
wire s0;
wire s1;
assign s0 = (J & ~R);
assign s1 = (K | R);
DIG_JK_FF #(
.Default(0)
) DIG_JK_FF_i0 (
.J(s0),
.C(C),
.K(s1),
.Q(Q),
.\~Q (\~Q )
);
endmodule
| 7.241376 |
module CE_EDFF (
input R, // Reset
input C,
input IN, // Input
output Q,
output \~Q
);
wire s0;
wire s1;
Mux_2x1 Mux_2x1_i0 (
.sel (R),
.in_0(IN),
.in_1(C),
.out (s1)
);
assign s0 = ~R;
DIG_D_FF_1bit #(
.Default(0)
) DIG_D_FF_1bit_i1 (
.D(s0),
... | 6.8538 |
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