code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module SNPS_CLOCK_GATE_HIGH_WeightsBank_476 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_475 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_474 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_473 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_472 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_471 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_470 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_469 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_468 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_467 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_466 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_465 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_464 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_463 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_462 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_461 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_460 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_459 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_458 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_457 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_456 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_455 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_454 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_453 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_452 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_451 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_450 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_449 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_448 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_447 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_446 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_445 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_444 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_443 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_442 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_441 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_440 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_439 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_438 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_437 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_436 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_435 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_434 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_433 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_432 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_431 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_430 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_429 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_428 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_427 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_426 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_425 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_424 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_423 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_422 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_421 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_420 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_419 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_418 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_417 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_416 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_415 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_414 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_413 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_412 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_411 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_410 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_409 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_408 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_407 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_406 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_405 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_404 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_403 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_402 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_401 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_400 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_399 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_398 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_397 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_396 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_395 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_394 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_393 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_392 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_391 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_390 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_389 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_388 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_387 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_386 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_385 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_384 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_383 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_382 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_381 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_380 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_379 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_378 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_377 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TL... | 6.575704 |
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