code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top_LPC_FPGA_DDR3_interface_p0_acv_ldc (
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_HHP_HPS = "false";
input pll_hr_clk;
input pll_dq_clk;
input pll_dqs_clk;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
output afi_clk;
output avl_clk;
output adc_clk;
output adc_clk_cps;
output hr_clk;
wire phy_clk_dqs;
wire phy_clk_dq;
wire phy_clk_hr;
wire phy_clk_dqs_2x;
wire phy_clk_addr_cmd;
wire phy_clk_addr_cmd_cps;
generate
if (IS_HHP_HPS == "true") begin
assign phy_clk_hr = pll_hr_clk;
assign phy_clk_dq = pll_dq_clk;
assign phy_clk_dqs = pll_dqs_clk;
assign phy_clk_dqs_2x = 1'b0;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk ({pll_hr_clk, pll_dq_clk, pll_dqs_clk, 1'b0}),
.outclk({phy_clk_hr, phy_clk_dq, phy_clk_dqs, phy_clk_dqs_2x})
);
end
endgenerate
wire [3:0] leveled_dqs_clocks;
wire [3:0] leveled_hr_clocks;
wire hr_seq_clock;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin(phy_clk_dqs),
.delayctrlin(dll_phy_delayctrl),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
assign afi_clk = leveled_dqs_clocks[0];
cyclonev_leveling_delay_chain leveling_delay_chain_hr (
.clkin(phy_clk_hr),
.delayctrlin(),
.clkout(leveled_hr_clocks)
);
defparam leveling_delay_chain_hr.physical_clock_source = "HR";
assign avl_clk = leveled_hr_clocks[0];
cyclonev_clk_phase_select clk_phase_select_addr_cmd (
.clkin (leveled_dqs_clocks),
.clkout(adc_clk_cps)
);
defparam clk_phase_select_addr_cmd.physical_clock_source = "ADD_CMD";
defparam clk_phase_select_addr_cmd.use_phasectrlin = "false";
defparam clk_phase_select_addr_cmd.phase_setting = ADC_PHASE_SETTING;
defparam clk_phase_select_addr_cmd.invert_phase = ADC_INVERT_PHASE;
cyclonev_clk_phase_select clk_phase_select_hr (
.phasectrlin(),
.phaseinvertctrl(),
.dqsin(),
`ifndef SIMGEN
.clkin(leveled_hr_clocks[0]),
`else
.clkin(leveled_hr_clocks),
`endif
.clkout(hr_seq_clock)
);
defparam clk_phase_select_hr.physical_clock_source = "HR";
defparam clk_phase_select_hr.use_phasectrlin = "false";
defparam clk_phase_select_hr.phase_setting = 0;
assign hr_clk = hr_seq_clock;
generate
if (ADC_INVERT_PHASE == "true") begin
assign adc_clk = ~leveled_dqs_clocks[ADC_PHASE_SETTING];
end else begin
assign adc_clk = leveled_dqs_clocks[ADC_PHASE_SETTING];
end
endgenerate
endmodule
| 7.640876 |
module top_LPC_FPGA_DDR3_interface_p0_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0 (
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif ,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
, .devoe(1'b1)
// synopsys translate_on
);
defparam obuf_ba_0.bus_hold = "false", obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign wire_obuf_ba_oe = {(~wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0 (
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif ,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
, .devoe(1'b1)
// synopsys translate_on
);
defparam obufa_0.bus_hold = "false", obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign wire_obufa_oe = {(~wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0 (
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif ,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign wire_pseudo_diffa_oein = {(~oe_w[0])};
assign dataout = wire_obufa_o, dataout_b = wire_obuf_ba_o, oe_w = 1'b1;
endmodule
| 7.640876 |
module top_LPC_FPGA_DDR3_interface_p0_generic_ddio (
datain,
halfratebypass,
dataout,
clk_hr,
clk_fr
);
parameter WIDTH = 1;
localparam DATA_IN_WIDTH = 4 * WIDTH;
localparam DATA_OUT_WIDTH = WIDTH;
input [DATA_IN_WIDTH-1:0] datain;
input halfratebypass;
input [WIDTH-1:0] clk_hr;
input [WIDTH-1:0] clk_fr;
output [DATA_OUT_WIDTH-1:0] dataout;
generate
genvar pin;
for (pin = 0; pin < WIDTH; pin = pin + 1) begin : acblock
wire fr_data_hi;
wire fr_data_lo;
cyclonev_ddio_out #(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_hi (
.datainhi(datain[pin*4]),
.datainlo(datain[pin*4+2]),
.dataout(fr_data_hi),
.clkhi(clk_hr[pin]),
.clklo(clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel(clk_hr[pin])
);
cyclonev_ddio_out #(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_lo (
.datainhi(datain[pin*4+1]),
.datainlo(datain[pin*4+3]),
.dataout(fr_data_lo),
.clkhi(clk_hr[pin]),
.clklo(clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel(clk_hr[pin])
);
cyclonev_ddio_out #(
.async_mode("none"),
.half_rate_mode("false"),
.sync_mode("none"),
.use_new_clocking_model("true")
) ddio_out (
.datainhi(fr_data_hi),
.datainlo(fr_data_lo),
.dataout(dataout[pin]),
.clkhi(clk_fr[pin]),
.clklo(clk_fr[pin]),
.muxsel(clk_fr[pin])
);
end
endgenerate
endmodule
| 7.640876 |
module top_LPC_FPGA_DDR3_interface_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clr(),
.ena(),
.ir_in(),
.ir_out(),
.jtag_state_cdr(),
.jtag_state_cir(),
.jtag_state_e1dr(),
.jtag_state_sdr(),
.jtag_state_tlr(),
.jtag_state_udr(),
.jtag_state_uir(),
.raw_tck(),
.source_clk(),
.source_ena(),
.tdi(),
.tdo(),
.usr1()
// synopsys translate_on
);
defparam iss_probe_inst.enable_metastability = "NO", iss_probe_inst.instance_id = ID_NAME,
iss_probe_inst.probe_width = WIDTH, iss_probe_inst.sld_auto_instance_index = "YES",
iss_probe_inst.sld_instance_index = 0, iss_probe_inst.source_initial_value = "0",
iss_probe_inst.source_width = 0;
endmodule
| 7.640876 |
module top_LPC_FPGA_DDR3_interface_p0_reset (
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
output ctl_reset_n;
output ctl_reset_export_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
top_LPC_FPGA_DDR3_interface_p0_reset_sync ureset_afi_clk (
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 15;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
top_LPC_FPGA_DDR3_interface_p0_reset_sync ureset_ctl_reset_clk (
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync ({ctl_reset_n, ctl_reset_export_n})
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15;
defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2;
top_LPC_FPGA_DDR3_interface_p0_reset_sync ureset_addr_cmd_clk (
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync(reset_n_addr_cmd_clk)
);
defparam ureset_addr_cmd_clk.RESET_SYNC_STAGES = 15;
defparam ureset_addr_cmd_clk.NUM_RESET_OUTPUT = 1;
top_LPC_FPGA_DDR3_interface_p0_reset_sync ureset_resync_clk (
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
defparam ureset_resync_clk.RESET_SYNC_STAGES = 15;
defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1;
top_LPC_FPGA_DDR3_interface_p0_reset_sync ureset_seq_clk (
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
defparam ureset_seq_clk.RESET_SYNC_STAGES = 15; defparam ureset_seq_clk.NUM_RESET_OUTPUT = 1;
top_LPC_FPGA_DDR3_interface_p0_reset_sync ureset_scc_clk (
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
defparam ureset_scc_clk.RESET_SYNC_STAGES = 15; defparam ureset_scc_clk.NUM_RESET_OUTPUT = 1;
top_LPC_FPGA_DDR3_interface_p0_reset_sync ureset_avl_clk (
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
defparam ureset_avl_clk.RESET_SYNC_STAGES = 2; defparam ureset_avl_clk.NUM_RESET_OUTPUT = 1;
generate
genvar i;
for (i = 0; i < MEM_READ_DQS_WIDTH; i = i + 1) begin : read_capture_reset
top_LPC_FPGA_DDR3_interface_p0_reset_sync #(
.RESET_SYNC_STAGES(15),
.NUM_RESET_OUTPUT (1)
) ureset_read_capture_clk (
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync(reset_n_read_capture[i])
);
end
endgenerate
endmodule
| 7.640876 |
module top_LPC_FPGA_DDR3_interface_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*)
reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i = 0; i < RESET_SYNC_STAGES + NUM_RESET_OUTPUT - 1; i = i + 1) begin : reset_stage
always @(posedge clk or negedge reset_n) begin
if (~reset_n) reset_reg[i] <= 1'b0;
else begin
if (i == 0) reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES) reset_reg[i] <= reset_reg[i-1];
else reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
| 7.640876 |
module MACC (
P,
A,
B,
CARRYIN,
CLK,
RST
);
output reg [47:0] P;
input [24:0] A;
input [17:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK) begin
if (!RST) mult_reg <= 'b0;
else mult_reg <= A * B;
end
always @(posedge CLK) begin
if (!RST) P <= 'b0;
else P <= mult_reg + CARRYIN;
end
endmodule
| 7.194091 |
module top (
input clk,
input rst,
input [24:0] a,
input [17:0] b,
input carryin,
output [47:0] p,
output [47:0] pw
);
MACC u_MACC (
.P(p),
.A(a),
.B(b),
.CARRYIN(carryin),
.CLK(clk),
.RST(rst)
);
MACC u_MACC_1 (
.P(pw),
.A(a),
.B(b),
.CARRYIN(~carryin),
.CLK(~clk),
.RST(~rst)
);
endmodule
| 7.233807 |
module full_adder_1 (
a,
b,
cin,
y,
cout
);
input a, b, cin;
output y, cout;
wire a, b, cin;
wire y, cout;
wire n_0;
AO2NHS g33 (
.A(cin),
.B(n_0),
.C(a),
.D(b),
.Z(cout)
);
F_EOHSX05 g34 (
.A(n_0),
.B(cin),
.Z(y)
);
F_EOHSX05 g35 (
.A(b),
.B(a),
.Z(n_0)
);
endmodule
| 6.657465 |
module top_mdio_slave (
reset,
mdc,
mdio,
dev_addr,
conf_done
);
input reset;
input mdc;
inout mdio;
input [4:0] dev_addr;
output conf_done;
wire VHDL2V_mdio;
wire mdio;
wire conf_done;
wire [4:0] reg_addr; // Address register
wire reg_read; // Read register
wire reg_write; // Write register
wire [15:0] reg_dout; // Data Bus OUT
wire [15:0] reg_din; // Data Bus IN
mdio_slave mdio_c (
.reset(reset),
.mdc(mdc),
.mdio(mdio),
.dev_addr(dev_addr),
.reg_addr(reg_addr),
.reg_read(reg_read),
.reg_write(reg_write),
.reg_dout(reg_din),
.reg_din(reg_dout)
);
mdio_reg_sim reg_c (
.reset(reset),
.clk(mdc),
.reg_addr(reg_addr),
.reg_write(reg_write),
.reg_read(reg_read),
.reg_dout(reg_dout),
.reg_din(reg_din),
.conf_done(conf_done)
);
assign mdio = VHDL2V_mdio;
endmodule
| 6.678564 |
module top (
input [7:0] data_a,
data_b,
input [6:1] addr_a,
addr_b,
input we_a,
we_b,
re_a,
re_b,
clk,
output reg [7:0] q_a,
q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @(posedge clk) begin
if (we_a) begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b) begin
q_a <= ram[addr_a];
end
end
// Port B
always @(posedge clk) begin
if (we_b) begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b) begin
q_b <= ram[addr_b];
end
end
endmodule
| 7.233807 |
module top (
input [7:0] data_a,
data_b,
input [6:1] addr_a,
addr_b,
input we_a,
we_b,
re_a,
re_b,
clk,
output reg [7:0] q_a,
q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @(posedge clk) begin
if (we_a) begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b) begin
q_a <= ram[addr_a];
end
end
// Port B
always @(posedge clk) begin
if (we_b) begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b) begin
q_b <= ram[addr_b];
end
end
endmodule
| 7.233807 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'MEM_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared library for the
// simulation.
//
// You can add any other legal Verilog to this template file, and it appear in
// the verilog module.
`timescale 1 ps / 1 ps
module top;
// RTL wrapper instances for cosim.
dut_cosim dut0();
integer n_cur_time;
initial n_cur_time=0;
reg [63:0] cur_time;
initial cur_time=0;
`include "hub.v"
// Load library and begin co-simulation.
initial begin
// For gate-level simulations we back-annotate the instances with delays
// from the SDF file
// Open the trace file if that's appropriate.
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) )
$dumpfile( "bdw_work/sims/MEM_V/verilog.vcd" );
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) ) begin
$dumpvars( 0, dut0.clk );
$dumpvars( 0, dut0.rst );
$dumpvars( 0, dut0.din_busy );
$dumpvars( 0, dut0.din_vld );
$dumpvars( 0, dut0.din_data );
$dumpvars( 0, dut0.dout_busy );
$dumpvars( 0, dut0.dout_vld );
$dumpvars( 0, dut0.dout_data );
$dumpvars( 4, dut0.dut0 );
end
// If the SystemC shared library will be loaded using +qbSetOption+libdef=libname.so
// from the Verilog simulator's command line, the following line can be left
// out. In order to load the shared library directly from Verilog, uncomment
// the following line using either ther automatically generated SIM_EXEC string,
// or a hard-coded string giving the path to the shared library.
//hubLoadLibrary( "bdw_work/sims/MEM_V/sim_MEM_V.so", "" );
// Begin a co-simulation.
// This task returns after esc_end_cosim() is called from SystemC.
hubStartCosim;
#100 $stop;
end
endmodule
| 7.358787 |
module top_mian (
input clk,
input rst_n,
input rxd,
output txd,
output [7:0] led,
output sdram_clk,
output [11:0] sdram_addr,
output [ 1:0] sdram_ba,
output sdram_cas_n,
output sdram_cke,
output sdram_cs_n,
inout [15:0] sdram_dq,
output [ 1:0] sdram_dqm,
output sdram_ras_n,
output sdram_we_n
);
//wire define
wire clk_100m;
wire clk_100m_shift;
wire locked;
wire sys_rst_n;
//
assign sys_rst_n = rst_n & locked;
assign sdram_clk = clk_100m_shift;
pll u_pll (
.inclk0(clk),
.areset(~rst_n),
.c0 (clk_100m),
.c1 (clk_100m_shift),
.locked(locked)
);
nios u_nios2 (
.clk_clk (clk_100m), // clk.clk
.reset_reset_n(sys_rst_n), // reset.reset_n
.uart_0_rxd (rxd), // uart_0.rxd
.uart_0_txd (txd), // .txd
.gpioa_export (led), // gpioa.export
.sdram_addr (sdram_addr), // sdram.addr
.sdram_ba (sdram_ba), // .ba
.sdram_cas_n(sdram_cas_n), // .cas_n
.sdram_cke (sdram_cke), // .cke
.sdram_cs_n (sdram_cs_n), // .cs_n
.sdram_dq (sdram_dq), // .dq
.sdram_dqm (sdram_dqm), // .dqm
.sdram_ras_n(sdram_ras_n), // .ras_n
.sdram_we_n (sdram_we_n) // .we_n
);
endmodule
| 7.610737 |
module top_minseg (
rst,
inclk,
seg1,
seg10
);
input rst, inclk;
output wire [6:0] seg1, seg10;
wire [5:0] sec_val;
min_cnt counter (
rst,
inclk,
sec_val
);
min_conv converter (
rst,
sec_val,
seg1,
seg10
);
endmodule
| 6.75476 |
module IO_SWITCH (
BCLK,
BRESET,
I_IOA,
D_IOA,
I_IORD,
D_IORD,
D_IOWR,
IO_READY,
GENSTAT,
D_IOBE,
ILO_SIG,
DCWACC,
IO_A,
IO_RD,
IO_WR,
IO_BE,
I_IORDY,
D_IORDY,
STATUS,
ILO
);
input BCLK, BRESET;
input [31:0] I_IOA, D_IOA;
input I_IORD;
input D_IORD, D_IOWR;
input [3:0] D_IOBE;
input IO_READY;
input [2:0] GENSTAT;
input ILO_SIG;
input [1:0] DCWACC;
output [31:0] IO_A;
output IO_RD, IO_WR;
output [3:0] IO_BE;
output I_IORDY;
output D_IORDY;
output [3:0] STATUS;
output ILO;
reg [3:0] STATUS;
reg [1:0] select;
reg ilo_flag;
wire daten;
wire sel_dp;
wire interrupt;
wire ilo_keep;
assign daten = D_IORD | D_IOWR;
// DCACHE has priority.
always @(posedge BCLK or negedge BRESET)
if (!BRESET) select <= 2'b0;
else
casex ({
I_IORD, D_IORD, D_IOWR, IO_READY, ilo_keep, select
})
7'b000xx_00 : select <= 2'b00;
7'b1000x_00 : select <= 2'b11;
7'bx100x_00 : select <= 2'b10;
7'bxx10x_00 : select <= 2'b10;
// the access has in the same cycle a READY !
7'b1001x_00 : select <= 2'b00;
7'bx101x_00 : select <= 2'b00;
7'bxx11x_00 : select <= 2'b00;
// Datea Access
7'bxxx0x_10 : select <= 2'b10;
7'bxxx11_10 : select <= 2'b10; // keep because of Interlocked
7'bxxx10_10 : select <= 2'b00;
// Instruction Access
7'bxxx0x_11 : select <= 2'b11;
7'bxxx1x_11 : select <= 2'b00;
default : select <= 2'b00;
endcase
assign sel_dp = (select == 2'b10) | ((select == 2'b00) & daten);
assign IO_RD = sel_dp ? D_IORD : I_IORD;
assign IO_WR = sel_dp ? D_IOWR : 1'b0;
assign IO_A = sel_dp ? D_IOA : I_IOA;
assign IO_BE = sel_dp ? D_IOBE : 4'b1111; // Instruction read always 32 Bit
assign D_IORDY = sel_dp & IO_READY;
assign I_IORDY = ~sel_dp & IO_READY & I_IORD;
assign interrupt = GENSTAT[1] | GENSTAT[0];
always @(*)
casex ({
sel_dp, daten, interrupt, I_IORD
})
4'b110x: STATUS = 4'hA; // Daten
4'b111x: STATUS = GENSTAT[1] ? 4'h4 : 4'h6; // Int Ack. : End of Int
4'b0xx1: STATUS = 4'h8; // Programm
default: STATUS = {3'd0, GENSTAT[2]}; // WAIT or Inactive
endcase
// +++++++++++ ILO Control ++++++++++++++++++
always @(posedge BCLK)
if (!ILO_SIG) ilo_flag <= 1'b0; // Flag is set at read and cleared with write
else ilo_flag <= (D_IORD & sel_dp) | DCWACC[0] | ilo_keep;
assign ilo_keep = ilo_flag & ~D_IOWR & ~DCWACC[1];
assign ILO = ILO_SIG & ((D_IORD & sel_dp) | DCWACC[0] | ilo_flag | D_IOWR | DCWACC[1]);
endmodule
| 7.495642 |
module MAKE_STAT (
BCLK,
READ,
DACC_OK,
DC_ACC,
DPTE_ACC,
DC_MDONE,
DRAM_WR,
IC_READ,
IACC_OK,
DATA_HOLD,
IC_ACC,
IPTE_ACC,
IC_MDONE,
KOLLISION,
STATSIGS
);
input BCLK;
input READ, DACC_OK;
input DC_ACC, DPTE_ACC, DC_MDONE;
input DRAM_WR;
input IC_READ, IACC_OK, DATA_HOLD;
input IC_ACC, IPTE_ACC, IC_MDONE;
input KOLLISION;
output reg [7:0] STATSIGS;
always @(posedge BCLK) begin
STATSIGS[7] <= KOLLISION; // 7 : from ICACHE : collisions
STATSIGS[6] <= IPTE_ACC; // 6 : Instruction PTE access
STATSIGS[5] <= IC_ACC & IC_MDONE; // 5 : Instruction Memory read
STATSIGS[4] <= IC_READ & IACC_OK & ~DATA_HOLD; // 4 : Instruction read , can be IO-Port too !
STATSIGS[3] <= DRAM_WR; // 3 : Data write
STATSIGS[2] <= DPTE_ACC; // 2 : Data PTE access
STATSIGS[1] <= DC_ACC & DC_MDONE; // 1 : Data Memory read
STATSIGS[0] <= READ & DACC_OK; // 0 : Data read , can be IO-Port too !
end
endmodule
| 6.986283 |
module Top_mod (
clk,
rst,
PWM
);
input clk; //100MHz
input rst;
output PWM;
wire [7:0] pcout; //Program Counter Output
wire [20:0] Instruction; // 21 bit instruction
wire [3:0] valve; // Valve
wire set_bit; // Goes high when valve is set
wire [9:0] delay; // 10 bit delay to be given to valve
wire [2:0] time_unit; // time_unit gives delay in miliseconds, seconds, minutes, hours or days
wire count_done; // count_done goes high when required delay is achieved by the counter
wire delay_start; // delay_start goes high when delay instruction is encountered
wire pchalt; // pchalt goes high when halt instruction is encountered
wire pcclock; // pcclock is a 50Hz clock
wire debug; // debug flag is set high when manual delay is to be given.
dividerforpc div (
.clk_100m(clk),
.rst(rst),
.clk_50Hz(pcclock)
); //Clock divider used to get 50Hz clock from 100MHz board clock
pc pc1 (
.rst(rst),
.clk(pcclock),
.pchalt(pchalt),
.delay(delay_start),
.count_done(count_done),
.pcout(pcout)
); //Program Counter
Inst inst1 (
.Address (pcout),
.ReadData1(Instruction)
); //Instruction Memory
decode_mod dec1 (
.Ins(Instruction),
.debug(debug),
.valve(valve),
.set_bit(set_bit),
.delay(delay),
.pchalt(pchalt),
.delay_start(delay_start),
.time_unit(time_unit)
); //Decode unit
counter cnt1 (
.manual_delay(0),
.debug_flag(debug),
.delay(delay),
.delay_unit(time_unit),
.count_done(count_done),
.clk(clk),
.rst(rst),
.start(delay_start),
.clk_50Hz(pcclock)
); //Counter for delays
Servo_interface si (
.set_bit(set_bit),
.delay_start(delay_start),
.count_done(count_done),
.clk(clk),
.PWM(PWM)
); //PWM for motor control
endmodule
| 7.437425 |
module top_handshakes #(
parameter WIDTH = 8
) (
input clk,
input rst,
input valid_en,
input ready_en,
output m_valid,
output m_ready,
output s_valid,
output s_ready,
input [WIDTH-1:0] m_data_in,
output [WIDTH-1:0] m_data_out,
output [WIDTH-1:0] s_data_in,
output [WIDTH-1:0] s_data_out,
output [7:0] addr
);
/*不打拍;
master master_test(
.clk(clk),
.rst(rst),
.valid_en(valid_en),
.ready(m_ready),
.mdata_in(m_data_in),
.valid(m_valid),
.mdata_out(m_data_out),
.addr(addr)
);
slave slave_test(
.clk(clk),
.rst(rst),
.ready_en(ready_en),
.valid(s_valid),
.sdata_in(s_data_in),
.ready(s_ready),
.sdata_out(s_data_out)
);
assign m_ready=s_ready;
assign s_valid=m_valid;
assign s_data_in=m_data_out;
*/
/*valid打拍;
master master_test(
.clk(clk),
.rst(rst),
.valid_en(valid_en),
.ready(m_ready),
.mdata_in(m_data_in),
.valid(m_valid),
.mdata_out(m_data_out),
.addr(addr)
);
valid_register valid_register_test(
.clk(clk),
.rst(rst),
.m_valid(m_valid),
.m_ready(m_ready),
.m_data (m_data_out),
.s_valid(s_valid),
.s_ready(s_ready),
.s_data(s_data_in)
);
slave slave_test(
.clk(clk),
.rst(rst),
.ready_en(ready_en),
.valid(s_valid),
.sdata_in(s_data_in),
.ready(s_ready),
.sdata_out(s_data_out)
);
*/
/*ready打拍；valid如不打拍，要用组合逻辑输出valid和data;
master master_test(
.clk(clk),
.rst(rst),
.valid_en(valid_en),
.ready(m_ready),
.mdata_in(m_data_in),
.valid(m_valid),
.mdata_out(m_data_out),
.addr(addr)
);
ready_register ready_register_test(
.clk(clk),
.rst(rst),
.m_valid(m_valid),
.m_ready(m_ready),
.m_data(m_data_out),
.s_valid(s_valid),
.s_ready(s_ready),
.s_data (s_data_in)
);
slave slave_test(
.clk(clk),
.rst(rst),
.ready_en(ready_en),
.valid(s_valid),
.sdata_in(s_data_in),
.ready(s_ready),
.sdata_out(s_data_out)
);
*/
//valid和ready都打拍，寄存器输出valid和data;
wire valid_connect;
wire ready_connect;
wire [WIDTH-1:0] data_connect;
master master_test (
.clk(clk),
.rst(rst),
.valid_en(valid_en),
.ready(m_ready),
.mdata_in(m_data_in),
.valid(m_valid),
.mdata_out(m_data_out),
.addr(addr)
);
/*
valid_register valid_register_test(
.clk(clk),
.rst(rst),
.m_valid(m_valid),
.m_ready(m_ready),
.m_data (m_data_out),
.s_valid(valid_connect),
.s_ready(ready_connect),
.s_data(data_connect)
);
ready_register ready_register_test(
.clk(clk),
.rst(rst),
.m_valid(valid_connect),
.m_ready(ready_connect),
.m_data(data_connect),
.s_valid(s_valid),
.s_ready(s_ready),
.s_data (s_data_in)
);
*/
ready_register ready_register_test (
.clk(clk),
.rst(rst),
.m_valid(m_valid),
.m_ready(m_ready),
.m_data(m_data_out),
.s_valid(s_valid),
.s_ready(s_ready),
.s_data(s_data_in)
);
slave slave_test (
.clk(clk),
.rst(rst),
.ready_en(ready_en),
.valid(s_valid),
.sdata_in(s_data_in),
.ready(s_ready),
.sdata_out(s_data_out)
);
endmodule
| 6.842838 |
moduletb.v
// Project Name: Transmitter
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: AASD
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_moduletb;
// Inputs
reg clk;
reg rst;
// Outputs
wire AASD_output;
// Instantiate the Unit Under Test (UUT)
AASD uut (
.AASD_output(AASD_output),
.clk(clk),
.rst(rst)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 8.700732 |
module Top_Module_Block (
data_in,
clk,
interrupt,
reset,
data_out
);
wire [23:0] ins;
wire [7:0] A;
wire [7:0] B;
wire [7:0] Current_Address;
wire [7:0] ans_ex;
wire [7:0] ans_dm;
wire [7:0] ans_wb;
wire [1:0] mux_sel_A;
wire [1:0] mux_sel_B;
wire imm_sel;
output [7:0] data_out;
input [7:0] data_in;
input clk;
input interrupt;
input reset;
wire [7:0] jmp_loc;
wire pc_mux_sel, Stall, Stall_pm, clk;
wire [7:0] DM_data;
wire mem_rw_ex, mem_en_ex, mem_mux_sel_dm;
wire [4:0] op_dec;
wire [3:0] flag_ex;
wire [7:0] imm;
wire [4:0] RW_dm;
PCIM PM (
ins,
Current_Address,
jmp_loc,
pc_mux_sel,
Stall,
Stall_pm,
reset,
clk
);
Data_Memory_Block DM (
ans_dm,
ans_ex,
DM_data,
mem_rw_ex,
mem_en_ex,
mem_mux_sel_dm,
reset,
clk
);
ExecutionBlock EB (
ans_ex,
data_out,
DM_data,
flag_ex,
data_in,
op_dec,
A,
B,
clk,
reset
);
Jump_Control_Block JC (
jmp_loc,
pc_mux_sel,
ins,
Current_Address,
flag_ex,
interrupt,
clk,
reset
);
Stall_Control_Block SC (
Stall,
Stall_pm,
ins,
clk,
reset
);
Register_Bank_Block RB (
A,
B,
clk,
ans_dm,
ans_ex,
ans_wb,
imm,
RW_dm,
mux_sel_A,
mux_sel_B,
imm_sel,
ins
);
Write_Back_Block WB (
ans_wb,
ans_dm,
reset,
clk
);
Dependency_Check_Block DC (
imm,
RW_dm,
op_dec,
mux_sel_A,
mux_sel_B,
imm_sel,
mem_en_ex,
mem_rw_ex,
mem_mux_sel_dm,
ins,
clk,
reset
);
endmodule
| 7.350337 |
module color_top (
input clk,
input frequency,
output reg is_move,
output reg [1:0] move,
output [1:0] filter_out,
output led,
output [1:0] frequency_rate
//output [7:0]blue,
//output [7:0]green
);
//reg is_move;
//reg [1:0]move;
assign frequency_rate = 2'b01;
assign led = 1'b1;
wire [63:0] para_red; //ɫӦIJ
wire [63:0] para_green; //ɫӦIJ
wire [63:0] para_blue; //ɫӦIJ
//ͨalwaysжͬһֵ°
wire [1:0] filter_banlance;
wire [1:0] filter_identify;
wire [10:0] red;
wire [10:0] green;
wire [10:0] blue;
wire ready;
wire ok;
White_Balance w_b (
clk,
frequency,
para_red,
para_green,
para_blue,
filter_banlance,
ready
);
Color_Identify c_i (
clk,
frequency,
ready,
para_red,
para_green,
para_blue,
red,
green,
blue,
filter_identify,
ok
);
//õȷɸѡź
assign filter_out[0] = ready ? filter_identify[0] : filter_banlance[0];
assign filter_out[1] = ready ? filter_identify[1] : filter_banlance[1];
///////////////////////////ok費Ҫ
always @(ok) begin
if(red<100&&green<100&&blue<100)//
begin
move = 2'b11;
is_move = 1;
end
else if(red>180&&green>180&&blue>180)//
begin
is_move = 0;
move = 2'b00;
end
else if(red>green&&red>blue)//
begin
move = 2'b00;
is_move = 1;
end
else if(green>red&&green>blue)//
begin
move = 2'b01;
is_move = 1;
end
else if(blue>red&&blue>green)//
begin
move = 2'b10;
is_move = 1;
end else;
end
endmodule
| 6.642193 |
module top_module_Mario (
input wire clk48, // clock signal, reset signal from switch
output wire SPEAKER
);
`include "../../rom_conversion/parameters/Parameters_Mario_general.vh"
`include "../../rom_conversion/parameters/Parameters_ROM_Mario_0.vh"
`include "../../rom_conversion/parameters/Parameters_ROM_Mario_1.vh"
localparam MID_C_OFFSET = 12;
localparam CHANNEL_0_IDX = 0;
localparam CHANNEL_1_IDX = 1;
wire clk10Mhz;
wire clkTempo;
pll_Mario pll (
.inclk0(clk48),
.c0(clk10Mhz),
.c1(clkTempo)
);
wire [ROMS_number-1:0] channel_out;
assign SPEAKER = (^channel_out[ROMS_number-1:0]);
wire waiting[ROMS_number-1:0];
reg [address_max_bits-1:0] current_msg[ROMS_number-1:0];
wire [note_max_bits-1:0] note[ROMS_number-1:0];
wire note_on[1:0];
wire [delay_max_bits-1:0] delay[ROMS_number-1:0];
reg [note_max_bits-1:0] note_next[ROMS_number-1:0];
reg note_on_next[ROMS_number-1:0];
localparam note_offset_0 = ROM_0_note_min - MID_C_OFFSET;
localparam note_offset_1 = ROM_1_note_min - MID_C_OFFSET;
wire [7:0] note_offset[ROMS_number-1:0];
assign note_offset[0] = note_offset_0;
assign note_offset[1] = note_offset_1;
localparam delay_clocks_per_tick_shift = $clog2(delay_clocks_per_tick) - 1;
genvar i;
generate
for (i = 0; i < ROMS_number; i = i + 1) begin : playnote
playnote channel (
.clk(clk10Mhz),
.out_enable(note_on_next[i]),
.note(note_next[i] + note_offset[i]),
.speaker(channel_out[i])
);
end
for (i = 0; i < ROMS_number; i = i + 1) begin : delay_unit
delay_unit #(
.DELAY_COUNTER_BITS(delay_reg_bits),
.DELAY_BITS(delay_max_bits),
.COUNTER_DIVISION(delay_clocks_per_tick_shift)
) du (
.clk(clkTempo),
.delay(delay[i]),
.waiting(waiting[i]),
.reset(master_reset),
.enable(1)
);
end
//begin : ROM
// ROM_``i`` ns(.clock(waiting[CHANNEL_``i``_IDX]), .address(current_msg[CHANNEL_``i``_IDX]), .q({note_on[CHANNEL_``i``_IDX], note[CHANNEL_``i``_IDX], delay[CHANNEL_``i``_IDX][ROM_``i``_delay_nbit-1:0]}));
//end
endgenerate
ROM_Mario_0 ns (
.clock(waiting[CHANNEL_0_IDX]),
.address(current_msg[CHANNEL_0_IDX]),
.q({note_on[CHANNEL_0_IDX], note[CHANNEL_0_IDX], delay[CHANNEL_0_IDX][ROM_0_delay_nbit-1:0]})
);
ROM_Mario_1 ns1 (
.clock(waiting[CHANNEL_1_IDX]),
.address(current_msg[CHANNEL_1_IDX]),
.q({note_on[CHANNEL_1_IDX], note[CHANNEL_1_IDX], delay[CHANNEL_1_IDX][ROM_1_delay_nbit-1:0]})
);
wire reset;
reg reset_0, reset_1;
wire master_reset;
assign master_reset = reset | ((reset_0 | reset_1) & clkTempo);
reset_unit ru (
.clk (clk10Mhz),
.reset(reset)
);
always @(negedge waiting[CHANNEL_0_IDX]) begin
if (current_msg[CHANNEL_0_IDX] == ROM_0_messages_len) begin
current_msg[CHANNEL_0_IDX] <= 0;
note_on_next[CHANNEL_0_IDX] <= 0;
note_next[CHANNEL_0_IDX] <= 0;
reset_0 <= 1;
end else begin
current_msg[CHANNEL_0_IDX] <= current_msg[CHANNEL_0_IDX] + 1'b1;
note_on_next[CHANNEL_0_IDX] <= note_on[CHANNEL_0_IDX];
note_next[CHANNEL_0_IDX] <= note[CHANNEL_0_IDX];
reset_0 <= 0;
end
end
always @(negedge waiting[CHANNEL_1_IDX]) begin
if (current_msg[CHANNEL_1_IDX] == ROM_1_messages_len) begin
current_msg[CHANNEL_1_IDX] <= 0;
note_on_next[CHANNEL_1_IDX] <= 0;
note_next[CHANNEL_1_IDX] <= 0;
reset_1 <= 1;
end else begin
current_msg[CHANNEL_1_IDX] <= current_msg[CHANNEL_1_IDX] + 1'b1;
note_on_next[CHANNEL_1_IDX] <= note_on[CHANNEL_1_IDX];
note_next[CHANNEL_1_IDX] <= note[CHANNEL_1_IDX];
reset_1 <= 0;
end
end
endmodule
| 7.311771 |
module top_module_mips_v2 (
output [31:0] INST,
output [31:0] out,
output flag,
input RST,
input [4:0] addr,
input CLK,
input write,
output [31:0] ina,
inb,
ALUA,
ALUB
);
// decode INST
reg [4:0] read1, wadd;
reg ALUsrc;
wire [5:0] opcode = INST[31:26];
wire [5:0] funct = INST[5:0];
wire [4:0] read0 = INST[25:21]; //rs
always @(*) begin
if (INST[31:26] == 0) begin // INST=R
read1 = INST[20:16]; //rt
wadd = INST[15:11];
ALUsrc = 0;
end else begin
wadd = INST[20:16]; //rt
ALUsrc = 1;
end
end
// REGISTER
GPR REG (
.REGNUM0(read0),
.REGNUM1(read1),
.REGNUM2(wadd),
.DIN0(out),
.DOUT0(ina),
.DOUT1(inb),
.CLK(CLK),
.WE0(write)
);
// PC
PC PC (
.CLK (CLK),
.RST (RST),
.INST(INST)
);
// ALU
ALU ALU (
.ina(ina),
.inb(inb),
.out(out),
.flag(flag),
.ALUA(ALUA),
.ALUB(ALUB),
.INST(INST),
.opcode(opcode),
.funct(funct),
.ALUsrc(ALUsrc)
);
endmodule
| 6.609881 |
module PC (
input CLK,
input RST,
output [31:0] INST
);
wire write = 1'b0; // dont write..
wire [31:0] data_in = 32'b0;
wire [31:0] data_out;
assign INST = data_out;
wire [4:0] addr;
// call program counter
COUNTER5B COUNTER (
.CLK (CLK),
.addr(addr),
.RST (RST)
);
// call program memory
CPU_REG PMEM (
.addr(addr),
.data_in(data_in),
.data_out(data_out),
.write(write)
);
endmodule
| 7.578567 |
module Top_module_of_color (
input clk,
input frequncy,
output [1:0] filter_select,
output [1:0] frequncy_rate,
output led,
output [9:0] r,
g,
b
);
assign frequncy_rate = 2'b10;
assign led = 1'b1;
wire [63:0] r_time, g_time, b_time;
wire [1:0] filter_balance, filter_identify;
wire ready;
white_balance white_balance_init (
.clk(clk),
.frequncy(frequncy),
.R_time(r_time),
.G_time(g_time),
.B_time(b_time),
.ready(ready),
.filter_select(filter_balance)
);
identify_color identify_color_init (
.clk(clk),
.frequncy(frequncy),
.ready(ready),
.r_time(r_time),
.g_time(g_time),
.b_time(b_time),
.filter_select(filter_identify),
.red(r),
.green(g),
.blue(b)
);
conbine_wire conbine_wire_init (
.ready(ready)
, .filter_select_balance(filter_balance),
.filter_select_identify(filter_identify)
, .filter_select_out(filter_select)
);
endmodule
| 7.014897 |
module_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Top_module_tb;
parameter W = 32;
// Inputs
reg clk;
reg [W-1:0] a;
reg [W-1:0] b;
reg c_in;
reg [2:0] ALOP;
// Outputs
wire [W:0] R0;
wire [W:0] R0_verify;
wire error_flag;
wire zero_flag;
wire overflow_flag;
// Instantiate the Unit Under Test (UUT)
Top_Module uut (
.R0(R0),
.R0_verify(R0_verify),
.clk(clk),
.a(a),
.b(b),
.c_in(c_in),
.ALOP(ALOP)
);
// Assign Error_flag
assign error_flag = ( R0 != R0_verify);
assign zero_flag = (R0 == 0);
assign overflow_flag = (R0[W-1] == 1 && a[W-1] == 0 && b[W-1] == 0) || (R0[W-1] == 0 && a[W-1] == 1 && b[W-1] == 1);
// Verification logic
always@(posedge clk)
begin
if(error_flag)
$display("Error occurs when a = %d, b = %d, c_in = %d\n", a, b, c_in);
end
always #5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
a = 1;
b = 0;
c_in = 0;
ALOP = 0;
// Wait 100 ns for global reset to finish
#100;
a = 1;
b = 1;
c_in = 0;
ALOP = 3'b110;
#100;
a = 0;
b = 1;
c_in = 1;
ALOP = 3'b011;
#100;
a = 45657897;
b = 212321;
c_in = 1;
ALOP = 3'b011;
#100;
a = 20;
b = 5;
c_in = 0;
ALOP = 3'b010;
#100;
a = 4566541;
b = 4565465;
c_in = 0;
ALOP = 3'b000;
#100;
a = 1232154;
b = 5568732;
c_in = 0;
ALOP = 3'b001;
#100;
a = 7565451;
b = 1232145;
c_in = 0;
ALOP = 3'b100;
#100;
// a = 45657878;
// b = 5123215;
a = 2;
b = 1;
c_in = 1;
ALOP = 3'b101;
#100;
a = 32'hffffffff;
b = 32'hffffffff;
//b = 1;
c_in = 0;
ALOP = 3'b110;
end
endmodule
| 6.516961 |
module: Top_Module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Top_Module_Test;
// Inputs
reg [31:0] R2;
reg [31:0] R3;
reg [2:0] ALUOp;
reg clk;
// Outputs
wire [31:0] R0;
// Instantiate the Unit Under Test (UUT)
Top_Module uut (
.R0(R0),
.R2(R2),
.R3(R3),
.ALUOp(ALUOp),
.clk(clk)
);
parameter word_size = 32; // word_size default value = 32
wire [word_size-1:0] ALU_ideal_out;
wire [word_size-1:0] error_bits;
wire error_flag;
// ---- ideal ALU ------
function [word_size:0] ALU_ideal; // include c_out;
input [word_size-1:0] R2, R3;
input [2:0] ALUOp;
begin
case (ALUOp[2:0])
3'h0: ALU_ideal = R2;
3'h1: ALU_ideal = ~R2;
3'h2: ALU_ideal = (R2 + R3);
3'h3: ALU_ideal = (R2 - R3);
3'h4: ALU_ideal = (R2 | R3);
3'h5: ALU_ideal = (R2 & R3);
3'h6: ALU_ideal = (($signed(R2) < $signed(R3))? 1:0);
endcase
end
endfunction
// ---- ideal ALU end------
assign ALU_ideal_out = ALU_ideal(R2, R3, ALUOp);
assign error_bits = ALU_ideal_out^R0; //comparison
assign error_flag = |error_bits;
initial begin
// Initialize Inputs
R2 = 32'b0;
R3 = 32'b0;
ALUOp = 3'b0;
clk = 0;
#100;
// MOV test
R2 = 32'b001010001010011111;
R3 = 32'b110001;
ALUOp = 3'b000;
#100;
// NOT test
R2 = 32'b11000101;
R3 = 32'b1100001001;
ALUOp = 3'b001;
#100;
// ADD test
R2 = 32'b1010101;
R3 = 32'b1010;
ALUOp = 3'b010;
#100;
// ADD test (with negative numbers)
R2 = 2**32-1 - 2**16;
R3 = 2**32-1 - 2**5;
ALUOp = 3'b010;
#100;
// SUB test (R2 > R3)
R2 = 2500;
R3 = 500;
ALUOp = 3'b011;
#100;
// SUB test (R2 < R3)
R2 = 500;
R3 = 2500;
ALUOp = 3'b011;
#100;
// SUB test (R2 = R3)
R2 = 32'b1100010010001;
R3 = 32'b1100010010001;
ALUOp = 3'b011;
#100;
// OR test
R2 = 32'b10010001011000101;
R3 = 32'b110001010010001;
ALUOp = 3'b100;
#100;
// AND test
R2 = 32'b111000001111000011;
R3 = 32'b1100010010110;
ALUOp = 3'b101;
#100;
// SLT test (R2 > R3)
R2 = 32'b1001110001100010100;
R3 = 32'b1100010;
ALUOp = 3'b110;
#100;
// SLT test (R2 = R3)
R2 = 32'b100010010001110001;
R3 = 32'b100010010001110001;
ALUOp = 3'b110;
#100;
// SLT test (R2 < R3)
R2 = 32'b10010010;
R3 = 32'b11010001010110;
ALUOp = 3'b110;
#100;
end
always begin
#50 clk = ~clk;
end
endmodule
| 8.366146 |
module top_module_Yoshi (
input wire clk48, // clock signal, reset signal from switch
output wire SPEAKER
);
`include "../../rom_conversion/parameters/Parameters_Yoshi_general.vh"
`include "../../rom_conversion/parameters/Parameters_ROM_Yoshi_0.vh"
localparam MID_C_OFFSET = 12;
localparam CHANNEL_0_IDX = 0;
localparam CHANNEL_1_IDX = 1;
wire clk10Mhz;
wire clkTempo;
pll_Yoshi pll (
.inclk0(clk48),
.c0(clk10Mhz),
.c1(clkTempo)
);
wire [ROMS_number-1:0] channel_out;
assign SPEAKER = (^channel_out[ROMS_number-1:0]);
wire waiting[ROMS_number-1:0];
reg [address_max_bits-1:0] current_msg[ROMS_number-1:0];
wire [note_max_bits-1:0] note[ROMS_number-1:0];
wire note_on[1:0];
wire [delay_max_bits-1:0] delay[ROMS_number-1:0];
reg [note_max_bits-1:0] note_next[ROMS_number-1:0];
reg note_on_next[ROMS_number-1:0];
localparam note_offset_0 = ROM_0_note_min - MID_C_OFFSET;
wire [7:0] note_offset[ROMS_number-1:0];
assign note_offset[0] = note_offset_0;
localparam delay_clocks_per_tick_shift = $clog2(delay_clocks_per_tick) - 1;
genvar i;
generate
for (i = 0; i < ROMS_number; i = i + 1) begin : playnote
playnote channel (
.clk(clk10Mhz),
.out_enable(note_on_next[i]),
.note(note_next[i] + note_offset[i]),
.speaker(channel_out[i])
);
end
for (i = 0; i < ROMS_number; i = i + 1) begin : delay_unit
delay_unit #(
.DELAY_COUNTER_BITS(delay_reg_bits),
.DELAY_BITS(delay_max_bits),
.COUNTER_DIVISION(delay_clocks_per_tick_shift)
) du (
.clk(clkTempo),
.delay(delay[i]),
.waiting(waiting[i]),
.reset(master_reset),
.enable(1)
);
end
//begin : ROM
// ROM_``i`` ns(.clock(waiting[CHANNEL_``i``_IDX]), .address(current_msg[CHANNEL_``i``_IDX]), .q({note_on[CHANNEL_``i``_IDX], note[CHANNEL_``i``_IDX], delay[CHANNEL_``i``_IDX][ROM_``i``_delay_nbit-1:0]}));
//end
endgenerate
ROM_Yoshi_0 ns (
.clock(waiting[CHANNEL_0_IDX]),
.address(current_msg[CHANNEL_0_IDX]),
.q({note_on[CHANNEL_0_IDX], note[CHANNEL_0_IDX], delay[CHANNEL_0_IDX][ROM_0_delay_nbit-1:0]})
);
wire reset;
reg reset_0;
wire master_reset;
assign master_reset = reset | (reset_0 & clkTempo);
reset_unit ru (
.clk (clk10Mhz),
.reset(reset)
);
always @(negedge waiting[CHANNEL_0_IDX]) begin
if (current_msg[CHANNEL_0_IDX] == ROM_0_messages_len) begin
current_msg[CHANNEL_0_IDX] <= 0;
note_on_next[CHANNEL_0_IDX] <= 0;
note_next[CHANNEL_0_IDX] <= 0;
reset_0 <= 1;
end else begin
current_msg[CHANNEL_0_IDX] <= current_msg[CHANNEL_0_IDX] + 1'b1;
note_on_next[CHANNEL_0_IDX] <= note_on[CHANNEL_0_IDX];
note_next[CHANNEL_0_IDX] <= note[CHANNEL_0_IDX];
reset_0 <= 0;
end
end
endmodule
| 7.799076 |
module top_module_Yoshi2 (
input wire clk48, // clock signal, reset signal from switch
output wire SPEAKER
);
`include "../../rom_conversion/parameters/Parameters_Yoshi2_general.vh"
`include "../../rom_conversion/parameters/Parameters_ROM_Yoshi2_0.vh"
localparam MID_C_OFFSET = 12;
localparam CHANNEL_0_IDX = 0;
wire clk10Mhz;
wire clkTempo;
pll_Yoshi2 pll (
.inclk0(clk48),
.c0(clk10Mhz),
.c1(clkTempo)
);
wire [ROMS_number-1:0] channel_out;
assign SPEAKER = (^channel_out[ROMS_number-1:0]);
wire waiting[ROMS_number-1:0];
reg [address_max_bits-1:0] current_msg[ROMS_number-1:0];
wire [note_max_bits-1:0] note[ROMS_number-1:0];
wire note_on[1:0];
wire [delay_max_bits-1:0] delay[ROMS_number-1:0];
reg [note_max_bits-1:0] note_next[ROMS_number-1:0];
reg note_on_next[ROMS_number-1:0];
localparam note_offset_0 = ROM_0_note_min - MID_C_OFFSET;
wire [7:0] note_offset[ROMS_number-1:0];
assign note_offset[0] = note_offset_0;
localparam delay_clocks_per_tick_shift = $clog2(delay_clocks_per_tick) - 1;
genvar i;
generate
for (i = 0; i < ROMS_number; i = i + 1) begin : playnote
playnote channel (
.clk(clk10Mhz),
.out_enable(note_on_next[i]),
.note(note_next[i] + note_offset[i]),
.speaker(channel_out[i])
);
end
for (i = 0; i < ROMS_number; i = i + 1) begin : delay_unit
delay_unit #(
.DELAY_COUNTER_BITS(delay_reg_bits),
.DELAY_BITS(delay_max_bits),
.COUNTER_DIVISION(delay_clocks_per_tick_shift)
) du (
.clk(clkTempo),
.delay(delay[i]),
.waiting(waiting[i]),
.reset(master_reset),
.enable(1)
);
end
//begin : ROM
// ROM_``i`` ns(.clock(waiting[CHANNEL_``i``_IDX]), .address(current_msg[CHANNEL_``i``_IDX]), .q({note_on[CHANNEL_``i``_IDX], note[CHANNEL_``i``_IDX], delay[CHANNEL_``i``_IDX][ROM_``i``_delay_nbit-1:0]}));
//end
endgenerate
ROM_Yoshi2_0 ns (
.clock(waiting[CHANNEL_0_IDX]),
.address(current_msg[CHANNEL_0_IDX]),
.q({note_on[CHANNEL_0_IDX], note[CHANNEL_0_IDX], delay[CHANNEL_0_IDX][ROM_0_delay_nbit-1:0]})
);
wire reset;
reg reset_0;
wire master_reset;
assign master_reset = reset | (reset_0 & clkTempo);
reset_unit ru (
.clk (clk10Mhz),
.reset(reset)
);
always @(negedge waiting[CHANNEL_0_IDX]) begin
if (current_msg[CHANNEL_0_IDX] == ROM_0_messages_len) begin
current_msg[CHANNEL_0_IDX] <= 0;
note_on_next[CHANNEL_0_IDX] <= 0;
note_next[CHANNEL_0_IDX] <= 0;
reset_0 <= 1;
end else begin
current_msg[CHANNEL_0_IDX] <= current_msg[CHANNEL_0_IDX] + 1'b1;
note_on_next[CHANNEL_0_IDX] <= note_on[CHANNEL_0_IDX];
note_next[CHANNEL_0_IDX] <= note[CHANNEL_0_IDX];
reset_0 <= 0;
end
end
endmodule
| 7.799076 |
module top_mod_test;
reg clk;
reg rst;
wire PWM;
Top_mod uut (
.clk(clk),
.rst(rst),
.PWM(PWM)
);
initial begin
clk = 0;
rst = 1; // Reset
#20;
rst = 0;
#20;
end
always #5 clk = ~clk; // Simulate 100MHz board clock
endmodule
| 6.915848 |
module top_motor_controller (
input wire rst,
input wire clk,
input wire change,
input wire mode,
input wire move,
input wire direction,
input wire step_size,
output wire [3:0] phase_out,
output wire [6:0] ones,
output wire [6:0] tens
);
//internal wires
wire [2:0] speed;
wire pulse;
wire zero_state;
step_motor_controller smc_inst (
.change(change),
.rst(rst),
.clk(clk),
.speed(speed)
);
step_motor_speed sms (
.speed(speed),
.rst(rst),
.clk(clk),
.step_pulse(pulse)
);
speed_display sd (
.speed(speed),
.ones (ones),
.tens (tens)
);
step_motor_mode smm (
.rst(rst),
.mode(mode),
.move(move),
.pulse(pulse),
.zero_state(zero_state)
);
driver_controller dc (
.rst(rst),
.step_pulse(pulse),
.direction(direction),
.step_size(step_size),
.zero_state(zero_state),
.phase_out(phase_out)
);
endmodule
| 8.944112 |
module seven_display #(
parameter INVERT = 1
) (
input [3:0] n,
output [6:0] segments
);
reg [6:0] bits;
assign segments = (INVERT ? ~bits : bits);
always @(n)
case (n)
4'h0: bits = 7'b0111111; // 0
4'h1: bits = 7'b0000110; // 1
4'h2: bits = 7'b1011011; // 2
4'h3: bits = 7'b1001111; // 3
4'h4: bits = 7'b1100110; // 4
4'h5: bits = 7'b1101101; // 5
4'h6: bits = 7'b1111101; // 6
4'h7: bits = 7'b0000111; // 7
4'h8: bits = 7'b1111111; // 8
4'h9: bits = 7'b1100111; // 9
4'hA: bits = 7'b1110111; // A
4'hB: bits = 7'b1111100; // B
4'hC: bits = 7'b0111001; // C
4'hD: bits = 7'b1011110; // D
4'hE: bits = 7'b1111001; // E
4'hF: bits = 7'b1110001; // F
endcase
endmodule
| 7.02946 |
module top_ms #(
parameter GPIO_PINS = 8
) (
input CLK50,
input [3:0] SW,
// UART
input RXD,
output TXD,
// Peripherals
output [7:0] LEDS,
// 3v3 input from the s6 on the de1soc
input S6_3v3,
// SSDs
output [6:0] ssd0,
output [6:0] ssd1,
output [6:0] ssd2,
output [6:0] ssd3,
output [6:0] ssd4,
output [6:0] ssd5
);
//wire [15:0] M_PADDR;
//wire M_PWRITE;
//wire [5-1:0] M_PSELx; // not shared
//wire M_PENABLE;
//wire [15:0] M_PWDATA;
//wire [15:0] M_PRDATA; // input to intercon
//wire M_PREADY; // input to intercon
wire [ 7:0] gpio0;
wire [15:0] gpio1;
wire [ 7:0] gpio2;
vmicro16_soc soc (
.clk (CLK50),
.reset(~SW[0]),
//.M_PADDR (M_PADDR),
//.M_PWRITE (M_PWRITE),
//.M_PSELx (M_PSELx),
//.M_PENABLE (M_PENABLE),
//.M_PWDATA (M_PWDATA),
//.M_PRDATA (M_PRDATA),
//.M_PREADY (M_PREADY),
// UART
.uart_tx(TXD),
.uart_rx(RXD),
// GPIO
.gpio0(LEDS[3:0]),
.gpio1(gpio1),
.gpio2(gpio2),
// DBUG
.dbug0(LEDS[4])
//.dbug1 (LEDS[7:4])
);
assign LEDS[7:5] = {TXD, RXD, S6_3v3};
// SSD displays (split across 2 gpio ports 1 and 2)
wire [3:0] ssd_chars[0:5];
assign ssd_chars[0] = gpio1[3:0];
assign ssd_chars[1] = gpio1[7:4];
assign ssd_chars[2] = gpio1[11:8];
assign ssd_chars[3] = gpio1[15:12];
assign ssd_chars[4] = gpio2[3:0];
assign ssd_chars[5] = gpio2[7:4];
seven_display ssd_0 (
.n(ssd_chars[0]),
.segments(ssd0)
);
seven_display ssd_1 (
.n(ssd_chars[1]),
.segments(ssd1)
);
seven_display ssd_2 (
.n(ssd_chars[2]),
.segments(ssd2)
);
seven_display ssd_3 (
.n(ssd_chars[3]),
.segments(ssd3)
);
seven_display ssd_4 (
.n(ssd_chars[4]),
.segments(ssd4)
);
seven_display ssd_5 (
.n(ssd_chars[5]),
.segments(ssd5)
);
endmodule
| 6.707767 |
module top (
input x,
input y,
input cin,
output A,
output cout
);
assign {cout, A} = cin * y * x;
endmodule
| 7.233807 |
module tristate (
en,
i,
o
);
input en;
input i;
output [1:0] o;
wire [1:0] io;
assign io[0] = (en) ? i : 1'bZ;
assign io[1] = (i) ? en : 1'bZ;
assign io[0] = (~en) ? ~i : 1'bZ;
assign o = io;
endmodule
| 6.741184 |
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en(en),
.i (a),
.o (c)
);
endmodule
| 7.233807 |
module multi_enc_decx2x4 (
// Inputs
clock,
datain,
datain1,
datain1_0,
datain_0,
reset,
// Outputs
dataout,
dataout1,
dataout1_0,
dataout_0
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input clock;
input [127:0] datain;
input [127:0] datain1;
input [127:0] datain1_0;
input [127:0] datain_0;
input reset;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [127:0] dataout;
output [127:0] dataout1;
output [127:0] dataout1_0;
output [127:0] dataout_0;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire clock;
wire [127:0] datain;
wire [127:0] datain1;
wire [127:0] datain1_0;
wire [127:0] datain_0;
wire [127:0] dataout_net_0;
wire [127:0] dataout1_net_0;
wire [127:0] dataout1_0_net_0;
wire [127:0] dataout_0_net_0;
wire reset;
wire [127:0] top_0_dataout;
wire [127:0] top_1_dataout1;
wire [127:0] dataout_net_1;
wire [127:0] dataout1_net_1;
wire [127:0] dataout1_0_net_1;
wire [127:0] dataout_0_net_1;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign dataout_net_1 = dataout_net_0;
assign dataout[127:0] = dataout_net_1;
assign dataout1_net_1 = dataout1_net_0;
assign dataout1[127:0] = dataout1_net_1;
assign dataout1_0_net_1 = dataout1_0_net_0;
assign dataout1_0[127:0] = dataout1_0_net_1;
assign dataout_0_net_1 = dataout_0_net_0;
assign dataout_0[127:0] = dataout_0_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------top
top top_0 (
// Inputs
.clock (clock),
.reset (reset),
.datain (datain),
.datain1 (datain1),
// Outputs
.dataout (top_0_dataout),
.dataout1(dataout1_0_net_0)
);
//--------top
top top_1 (
// Inputs
.clock (clock),
.reset (reset),
.datain (datain_0),
.datain1 (datain1_0),
// Outputs
.dataout (dataout_0_net_0),
.dataout1(top_1_dataout1)
);
//--------top
top top_2 (
// Inputs
.clock (clock),
.reset (reset),
.datain (top_0_dataout),
.datain1 (top_1_dataout1),
// Outputs
.dataout (dataout_net_0),
.dataout1(dataout1_net_0)
);
endmodule
| 7.153212 |
module top (
input [7:0] dataa,
input [7:0] datab,
input clk,
aclr,
clken,
sload,
output reg [15:0] adder_out
);
// Declare registers and wires
reg [15:0] dataa_reg, datab_reg;
reg sload_reg;
reg [15:0] old_result;
wire [15:0] multa;
// Store the results of the operations on the current data
assign multa = dataa_reg * datab_reg;
// Store the value of the accumulation (or clear it)
always @(adder_out, sload_reg) begin
if (sload_reg) old_result <= 0;
else old_result <= adder_out;
end
// Clear or update data, as appropriate
always @(posedge clk or posedge aclr) begin
if (aclr) begin
dataa_reg <= 0;
datab_reg <= 0;
sload_reg <= 0;
adder_out <= 0;
end else if (clken) begin
dataa_reg <= dataa;
datab_reg <= datab;
sload_reg <= sload;
adder_out <= old_result + multa;
end
end
endmodule
| 7.233807 |
module MACC (
P,
A,
B,
CARRYIN,
CLK,
RST
);
output reg [47:0] P;
input [24:0] A;
input [17:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK) begin
if (!RST) mult_reg <= 'b0;
else mult_reg <= A * B;
end
always @(posedge CLK) begin
if (!RST) P <= 'b0;
else P <= mult_reg + CARRYIN;
end
endmodule
| 7.194091 |
module top (
input clk,
input rst,
input [24:0] a,
input [17:0] b,
input carryin,
output [47:0] p
);
MACC u_MACC (
.P(p),
.A(a),
.B(b),
.CARRYIN(carryin),
.CLK(clk),
.RST(rst)
);
endmodule
| 7.233807 |
module MACC (
P,
A,
B,
CARRYIN,
CLK,
RST
);
output reg [47:0] P;
input [15:0] A;
input [17:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK) begin
if (!RST) mult_reg <= 'b0;
else mult_reg <= A * B;
end
always @(posedge CLK) begin
if (!RST) P <= 'b0;
else P <= mult_reg + CARRYIN;
end
endmodule
| 7.194091 |
module top (
input clk,
input rst,
input [15:0] a,
input [17:0] b,
input carryin,
output [47:0] p
);
MACC u_MACC (
.P(p),
.A(a),
.B(b),
.CARRYIN(carryin),
.CLK(clk),
.RST(rst)
);
endmodule
| 7.233807 |
module MACC (
P,
A,
B,
CARRYIN,
CLK,
RST
);
output reg [47:0] P;
input [15:0] A;
input [15:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK) begin
if (!RST) mult_reg <= 'b0;
else mult_reg <= A * B;
end
always @(posedge CLK) begin
if (!RST) P <= 'b0;
else P <= mult_reg + CARRYIN;
end
endmodule
| 7.194091 |
module top (
input clk,
input rst,
input [15:0] a,
input [15:0] b,
input carryin,
output [47:0] p
);
MACC u_MACC (
.P(p),
.A(a),
.B(b),
.CARRYIN(carryin),
.CLK(clk),
.RST(rst)
);
endmodule
| 7.233807 |
module MACC (
P,
A,
B,
CARRYIN,
CLK,
RST
);
output reg signed [31:0] P;
input signed [15:0] A;
input signed [15:0] B;
input CARRYIN;
input CLK;
input RST;
reg signed [31:0] mult_reg;
always @(posedge CLK) begin
if (!RST) mult_reg <= 'b0;
else mult_reg <= A * B;
end
always @(posedge CLK) begin
if (!RST) P <= 'b0;
else P <= mult_reg + CARRYIN;
end
endmodule
| 7.194091 |
module top (
input clk,
input rst,
input signed [15:0] a,
input signed [15:0] b,
input carryin,
output signed [31:0] p
);
MACC u_MACC (
.P(p),
.A(a),
.B(b),
.CARRYIN(carryin),
.CLK(clk),
.RST(rst)
);
endmodule
| 7.233807 |
module top (
input x,
input y,
input cin,
output cout
);
assign cout = cin ? y : x;
endmodule
| 7.233807 |
module top (
input [5:0] S,
input [63:0] D,
output M256
);
assign M256 = D[S];
endmodule
| 7.233807 |
module top (
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
endmodule
| 7.233807 |
module top_new (
input wire CLK100MHZ,
input wire RST_BTN,
input wire BTNC,
input wire vauxp2,
input wire vauxn2,
input wire vauxp3,
input wire vauxn3,
input wire vauxp10,
input wire vauxn10,
input wire vauxp11,
input wire vauxn11,
input wire vp_in,
input wire vn_in,
input wire [1:0] sw,
// output wire [7:0] an,
output wire dp_top_ADC,
output wire [6:0] seg_top_ADC,
output wire [15:0] LED_top,
output wire vga_hs_top, // horizontal sync
output wire vga_vs_top, // vertical sync
output wire [3:0] vga_r_top, // red channels
output wire [3:0] vga_g_top, // green channels
output wire [3:0] vga_b_top, // blue channels
// output wire [6:0] seg_top, // 7-segment segments
output wire [7:0] an_top_ADC // 7-segment anodes
);
wire [6:0] seg_top;
wire an_top;
wire [15:0] dataL_top;
wire [15:0] dataR_top;
XADCdemo top_ADC (
.CLK100MHZ(CLK100MHZ),
.vauxp2(vauxp2),
.vauxn2(vauxn2),
.vauxp3(vauxp3),
.vauxn3(vauxn3),
.vauxp10(vauxp10),
.vauxn10(vauxn10),
.vauxp11(vauxp11),
.vauxn11(vauxn11),
.vp_in(vp_in),
.vn_in(vn_in),
.sw(sw),
.LED(LED_top),
.an(an_top_ADC),
.dp(dp_top_ADC),
.seg(seg_top_ADC),
.dataL(dataL_top),
.dataR(dataR_top)
);
top top_Pong (
.CLK(CLK100MHZ), // 100 Mhz clock
.RST_BTN(RST_BTN), // reset button
.BTN_LR(BTN_LR), // left and right buttons
.BTNC(BTNC), // mode change button
.VGA_HS(vga_hs_top), // horizontal sync
.VGA_VS(vga_vs_top), // vertical sync
.VGA_R(vga_r_top), // red channels
.VGA_G(vga_g_top), // green channels
.VGA_B(vga_b_top), // blue channels
.seg(seg_top), // 7-segment segments
.AN(an_top) // 7-segment anodes
);
// variables for analog2game
wire dataL;
wire dataR;
wire [1:0] BTN_LR; //control button for game, transferred from the analog signal.
analog2game ag (
.CLK100MHZ(CLK100MHZ), //
.vauxp3(dataL_top), //from adc, 16 bit input
.vauxp2(dataR_top), //from adc, 16 bits input
.BTN_LR(BTN_LR) //out to game top module
);
endmodule
| 7.650351 |
module nfu_3_top (
clk,
i_nfu2_out,
i_coef,
i_load_coef,
i_max,
i_min,
i_offset,
o_nfu3_out
);
parameter N = 16;
parameter Tn = 16;
parameter BIT_IDX = 4;
input clk;
input i_load_coef;
input [((2*N)-1):0] i_coef;
input [(Tn*N) - 1 : 0] i_nfu2_out;
// control signals for rounder
input [N-1:0] i_max;
input [N-1:0] i_min;
input [BIT_IDX-1:0] i_offset;
output [(Tn*N) - 1 : 0] o_nfu3_out;
/*
reg i_load_coef_reg;
reg [((2*N)-1):0] i_coef_reg;
reg [ (Tn*N) - 1 : 0 ] i_nfu2_out_reg;
reg [N-1:0] i_max_reg;
reg [N-1:0] i_min_reg;
reg [BIT_IDX-1:0] i_offset_reg;
reg [ (Tn*N) - 1 : 0 ] nfu3_out_reg;
*/
wire [(Tn*N) - 1 : 0] nfu3_out;
////////////////////////////////////////
//assign o_nfu3_out = nfu3_out_reg;
assign o_nfu3_out = nfu3_out;
/*
always @(posedge clk) begin
i_load_coef_reg <= i_load_coef;
i_coef_reg <= i_coef;
i_nfu2_out_reg <= i_nfu2_out;
i_max_reg <= i_max;
i_min_reg <= i_min;
i_offset_reg <= i_offset;
nfu3_out_reg <= nfu3_out;
end
nfu_3 NFU3(
clk,
i_nfu2_out_reg,
i_coef_reg,
i_load_coef_reg,
i_max_reg,
i_min_reg,
i_offset_reg,
nfu3_out
);
*/
nfu_3 NFU3 (
clk,
i_nfu2_out,
i_coef,
i_load_coef,
i_max,
i_min,
i_offset,
nfu3_out
);
endmodule
| 8.072772 |
module top
(
input [2:0] x,
input [2:0] y,
output [5:0] A,
);
assign A = x * y;
endmodule
| 7.039434 |
module top (
input x,
input y,
input cin,
output A,
output cout
);
wire A1, cout1;
assign A1 = ~y + &cin;
assign cout1 = cin ? |y : ^A;
assign A = A1 | y~&cin ~^ A1;
assign cout = cout1 & cin~|y;
endmodule
| 7.233807 |
module top
(
input [7:0] x,
output A,
);
assign A = ^x;
endmodule
| 7.039434 |
module top (
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
always @(posedge cin) A <= o;
assign cout = cin ? y : x;
middle u_mid (
x,
y,
o
);
endmodule
| 7.233807 |
module middle (
input x,
input y,
output o
);
assign o = x + y;
endmodule
| 6.553865 |
module top (
x,
clk,
rst,
arst
);
output x;
reg x;
input clk;
input rst;
input [1:0] arst;
always @(posedge clk, negedge rst) begin : DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end else begin
case (arst)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
| 6.963493 |
module top (
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *)reg foo;
(* anyseq *)reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
always @(posedge x) begin
if ($initstate) A <= 0;
A <= y + cin + too;
end
endmodule
| 7.233807 |
module top_np (
input wire CLK,
input wire RST,
input wire SERIAL_RX,
output reg SERIAL_TX
);
initial begin
$display("Hello World");
$finish;
end
endmodule
| 7.099441 |
module top_nto1_ddr_diff_rx (
input reset, // reset (active high)
input [7:0] datain_p,
datain_n, // lvds data inputs
input clkin_p,
clkin_n, // lvds clock input
output [63:0] dummy_out
); // dummy outputs
// Parameters for serdes factor and number of IO pins
parameter integer S = 8; // Set the serdes factor to 8
parameter integer D = 8; // Set the number of inputs and outputs
parameter integer DS = (D * S) - 1; // Used for bus widths = serdes factor * number of inputs - 1
wire rst;
wire [DS:0] rxd; // Data from serdeses
reg [DS:0] rxr; // Registered Data from serdeses
reg state;
reg bslip;
reg [ 3:0] count;
assign rst = reset ; // active high reset pin
assign dummy_out = rxr ;
// Clock Input. Generate ioclocks via BUFIO2
serdes_1_to_n_clk_ddr_s8_diff #(
.S (S),
.DIFF_TERM ("TRUE")
) // Enable or disable diff termination
inst_clkin (
.clkin_p (clkin_p),
.clkin_n (clkin_n),
.rxioclkp (rxioclkp),
.rxioclkn (rxioclkn),
.rx_serdesstrobe(rx_serdesstrobe),
.rx_bufg_x1 (rx_bufg_x1)
);
// Data Inputs
serdes_1_to_n_data_ddr_s8_diff #(
.S (S),
.D (D),
.DIFF_TERM ("TRUE")
) // Enable or disable diff termination
inst_datain (
.use_phase_detector(1'b1), // '1' enables the phase detector logic
.datain_p (datain_p),
.datain_n (datain_n),
.rxioclkp (rxioclkp),
.rxioclkn (rxioclkn),
.rxserdesstrobe (rx_serdesstrobe),
.gclk (rx_bufg_x1),
.bitslip (bslip),
.reset (rst),
.data_out (rxd),
.debug_in (2'b00),
.debug ()
);
always @ (posedge rx_bufg_x1 or posedge rst) // example bitslip logic, if required
begin
if (rst == 1'b1) begin
state <= 0;
bslip <= 1'b0;
count <= 4'b0000;
end else begin
if (state == 0) begin
if (rxd[63:60] != 4'h3) begin
bslip <= 1'b1; // bitslip needed
state <= 1;
count <= 4'b0000;
end
end else if (state == 1) begin
bslip <= 1'b0; // bitslip low
count <= count + 4'b0001;
if (count == 4'b1111) begin
state <= 0;
end
end
end
end
always @ (posedge rx_bufg_x1) // process received data
begin
rxr <= rxd;
end
endmodule
| 6.934944 |
module top_nto1_ddr_diff_tx (
input reset, // reset (active high)
input refclkin_p,
refclkin_n, // frequency generator clock input
output [7:0] dataout_p,
dataout_n, // lvds data outputs
output clkout_p,
clkout_n
); // lvds clock output
// Parameters for serdes factor and number of IO pins
parameter integer S = 8; // Set the serdes factor
parameter integer D = 8; // Set the number of inputs and outputs
parameter integer DS = (D * S) - 1; // Used for bus widths = serdes factor * number of inputs - 1
wire rst;
reg [DS:0] txd; // Registered Data to serdeses
// Parameters for clock generation
parameter [S-1:0] TX_CLK_GEN = 8'hAA; // Transmit a constant to make a clock
assign rst = reset; // active high reset pin
// Reference Clock Input genertaes IO clocks via 2 x BUFIO2
clock_generator_ddr_s8_diff #(
.S(S)
) inst_clkgen (
.clkin_p (refclkin_p),
.clkin_n (refclkin_n),
.ioclkap (txioclkp),
.ioclkan (txioclkn),
.serdesstrobea (tx_serdesstrobe),
.ioclkbp (),
.ioclkbn (),
.serdesstrobeb (),
.gclk (tx_bufg_x1)
);
always @ (posedge tx_bufg_x1 or posedge rst) // Generate some data to transmit
begin
if (rst == 1'b1) begin
txd <= 64'h3000000000000001;
end else begin
txd <= {txd[63:60], txd[58:0], txd[59]};
end
end
// Transmitter Logic - Instantiate serialiser to generate forwarded clock
serdes_n_to_1_ddr_s8_diff #(
.S(S),
.D(1)
) inst_clkout (
.dataout_p (clkout_p),
.dataout_n (clkout_n),
.txioclkp (txioclkp),
.txioclkn (txioclkn),
.txserdesstrobe(tx_serdesstrobe),
.gclk (tx_bufg_x1),
.reset (rst),
.datain (TX_CLK_GEN)
); // Transmit a constant to make the clock
// Instantiate Outputs and output serialisers for output data lines
serdes_n_to_1_ddr_s8_diff #(
.S(S),
.D(D)
) inst_dataout (
.dataout_p (dataout_p),
.dataout_n (dataout_n),
.txioclkp (txioclkp),
.txioclkn (txioclkn),
.txserdesstrobe(tx_serdesstrobe),
.gclk (tx_bufg_x1),
.reset (rst),
.datain (txd)
);
endmodule
| 6.934944 |
module top_nto1_ddr_se_rx (
input reset, // reset (active high)
input [7:0] datain, // single ended data inputs
input clkin1,
clkin2, // TWO single ended clock input
output [63:0] dummy_out
); // dummy outputs
// Parameters for serdes factor and number of IO pins
parameter integer S = 8; // Set the serdes factor to 8
parameter integer D = 8; // Set the number of inputs and outputs
parameter integer DS = (D * S) - 1; // Used for bus widths = serdes factor * number of inputs - 1
wire rst;
wire [DS:0] rxd; // Data from serdeses
reg [DS:0] rxr; // Registered Data from serdeses
reg state;
reg bslip;
reg [ 3:0] count;
assign rst = reset ; // active high reset pin
assign dummy_out = rxr ;
// Clock Input. Generate ioclocks via BUFIO2
serdes_1_to_n_clk_ddr_s8_se #(
.S(S)
) inst_clkin (
.clkin1 (clkin1),
.clkin2 (clkin2),
.rxioclkp (rxioclkp),
.rxioclkn (rxioclkn),
.rx_serdesstrobe(rx_serdesstrobe),
.rx_bufg_x1 (rx_bufg_x1)
);
// Data Inputs
serdes_1_to_n_data_ddr_s8_se #(
.S (S),
.D (D),
.USE_PD ("TRUE")
) // Enables use of the phase detector - will require 2 input serdes whatever the serdes ratio required
inst_datain (
.use_phase_detector(1'b1), // '1' enables the phase detector logic
.datain (datain),
.rxioclkp (rxioclkp),
.rxioclkn (rxioclkn),
.rxserdesstrobe (rx_serdesstrobe),
.gclk (rx_bufg_x1),
.bitslip (bslip),
.reset (rst),
.data_out (rxd),
.debug_in (2'b00),
.debug ()
);
always @ (posedge rx_bufg_x1 or posedge rst) // example bitslip logic, if required
begin
if (rst == 1'b1) begin
state <= 0;
bslip <= 1'b0;
count <= 4'b0000;
end else begin
if (state == 0) begin
if (rxd[63:60] != 4'h3) begin
bslip <= 1'b1; // bitslip needed
state <= 1;
count <= 4'b0000;
end
end else if (state == 1) begin
bslip <= 1'b0; // bitslip low
count <= count + 4'b0001;
if (count == 4'b1111) begin
state <= 0;
end
end
end
end
always @ (posedge rx_bufg_x1) // process received data
begin
rxr <= rxd;
end
endmodule
| 6.934944 |
module top_nto1_ddr_se_tx (
input reset, // reset (active high)
input refclkin_p,
refclkin_n, // frequency generator clock input
output [7:0] dataout, // single ended data outputs
output clkout
); // single ended clock output
// Parameters for serdes factor and number of IO pins
parameter integer S = 8; // Set the serdes factor
parameter integer D = 8; // Set the number of inputs and outputs
parameter integer DS = (D * S) - 1; // Used for bus widths = serdes factor * number of inputs - 1
wire rst;
reg [DS:0] txd; // Registered Data to serdeses
// Parameters for clock generation
parameter [S-1:0] TX_CLK_GEN = 8'hAA; // Transmit a constant to make a clock
assign rst = reset; // active high reset pin
// Reference Clock Input genertaes IO clocks via 2 x BUFIO2
clock_generator_ddr_s8_diff #(
.S(S)
) inst_clkgen (
.clkin_p (refclkin_p),
.clkin_n (refclkin_n),
.ioclkap (txioclkp),
.ioclkan (txioclkn),
.serdesstrobea (tx_serdesstrobe),
.ioclkbp (),
.ioclkbn (),
.serdesstrobeb (),
.gclk (tx_bufg_x1)
);
always @ (posedge tx_bufg_x1 or posedge rst) // Generate some data to transmit
begin
if (rst == 1'b1) begin
txd <= 64'h3000000000000001;
end else begin
txd <= {txd[63:60], txd[58:0], txd[59]};
end
end
// Transmitter Logic - Instantiate serialiser to generate forwarded clock
serdes_n_to_1_ddr_s8_se #(
.S(S),
.D(1)
) inst_clkout (
.dataout (clkout),
.txioclkp (txioclkp),
.txioclkn (txioclkn),
.txserdesstrobe(tx_serdesstrobe),
.gclk (tx_bufg_x1),
.reset (rst),
.datain (TX_CLK_GEN)
); // Transmit a constant to make the clock
// Instantiate Outputs and output serialisers for output data lines
serdes_n_to_1_ddr_s8_se #(
.S(S),
.D(D)
) inst_dataout (
.dataout (dataout),
.txioclkp (txioclkp),
.txioclkn (txioclkn),
.txserdesstrobe(tx_serdesstrobe),
.gclk (tx_bufg_x1),
.reset (rst),
.datain (txd)
);
endmodule
| 6.934944 |
module top_nto1_pll_16_diff_rx (
input reset, // reset (active high)
input [5:0] datain_p,
datain_n, // lvds data inputs
input clkin_p,
clkin_n, // lvds clock input
output [95:0] dummy_out
); // dummy outputs
// Parameters for serdes factor and number of IO pins
parameter integer S = 16; // Set the serdes factor to 8
parameter integer D = 6; // Set the number of inputs and outputs
parameter integer DS = (D * S) - 1; // Used for bus widths = serdes factor * number of inputs - 1
wire rst;
wire [ DS:0] rxd; // Data from serdeses
reg [ DS:0] rxr; // Registered Data from serdeses
wire bitslip;
wire [S-1:0] clk_iserdes_data;
assign rst = reset ; // active high reset pin
assign dummy_out = rxr ;
// Clock Input.
serdes_1_to_n_clk_pll_s16_diff #(
.S(S),
.CLKIN_PERIOD(16.000),
.PLLD(1),
.PLLX(S),
.BS ("TRUE"), // Parameter to enable bitslip TRUE or FALSE (has to be true for video applications)
.DIFF_TERM("TRUE")
) // Enable or disable diff termination
inst_clkin (
.clkin_p (clkin_p),
.clkin_n (clkin_n),
.rxioclk (rx_bufpll_clk_xn),
.pattern1 (16'h00FF), // pattern to search for
.rx_serdesstrobe(rx_serdesstrobe),
.rx_bufg_pll_x1 (rx_bufg_x1),
.rx_bufg_pll_x2 (rx_bufg_x2),
.bitslip (bitslip),
.reset (rst),
.datain (clk_iserdes_data),
.rx_toggle (rx_toggle),
.rx_bufpll_lckd (rx_bufpll_lckd)
);
// Data Inputs
assign not_bufpll_lckd = ~rx_bufpll_lckd;
serdes_1_to_n_data_s16_diff #(
.S (S),
.D (D),
.DIFF_TERM ("TRUE")
) // Enable or disable diff termination
inst_datain (
.use_phase_detector(1'b1), // '1' enables the phase detector logic
.datain_p (datain_p),
.datain_n (datain_n),
.rxioclk (rx_bufpll_clk_xn),
.rx_serdesstrobe (rx_serdesstrobe),
.rx_bufg_pll_x1 (rx_bufg_x1),
.rx_bufg_pll_x2 (rx_bufg_x2),
.bitslip (bitslip),
.reset (not_bufpll_lckd),
.data_out (rxd),
.rx_toggle (rx_toggle),
.debug_in (2'b00),
.debug ()
);
always @ (posedge rx_bufg_x1) // process received data
begin
rxr <= rxd;
end
endmodule
| 7.222471 |
module top_nto1_pll_16_diff_rx_and_tx (
input reset, // reset (active high)
input [5:0] datain_p,
datain_n, // lvds data inputs
input clkin_p,
clkin_n, // lvds clock input
output [5:0] dataout_p,
dataout_n, // lvds data outputs
output clkout_p,
clkout_n
); // lvds clock output
// Parameters for serdes factor and number of IO pins
parameter integer S = 16; // Set the serdes factor to 8
parameter integer D = 6; // Set the number of inputs and outputs
parameter integer DS = (D * S) - 1; // Used for bus widths = serdes factor * number of inputs - 1
wire rst;
wire [ DS:0] rxd; // Data from serdeses
reg [ DS:0] txd; // Data to serdeses
wire [S-1:0] clk_iserdes_data;
parameter [S-1:0] TX_CLK_GEN = 16'h00FF; // Transmit a constant to make a clock
assign rst = reset; // active high reset pin
// Clock Input. Generate ioclocks via BUFIO2
serdes_1_to_n_clk_pll_s16_diff #(
.S(S),
.CLKIN_PERIOD(16.000),
.PLLD(1),
.PLLX(S),
.BS ("TRUE"), // Parameter to enable bitslip TRUE or FALSE (has to be true for video applications)
.DIFF_TERM("TRUE")
) // Enable or disable diff termination
inst_clkin (
.clkin_p (clkin_p),
.clkin_n (clkin_n),
.rxioclk (rx_bufpll_clk_xn),
.pattern1 (16'h00FF), // pattern to searh for
.rx_serdesstrobe(rx_serdesstrobe),
.rx_bufg_pll_x1 (rx_bufg_x1),
.rx_bufg_pll_x2 (rx_bufg_x2),
.bitslip (bitslip),
.reset (rst),
.datain (clk_iserdes_data),
.rx_toggle (rx_toggle),
.rx_bufpll_lckd (rx_bufpll_lckd)
);
// Data Inputs
assign not_bufpll_lckd = ~rx_bufpll_lckd;
serdes_1_to_n_data_s16_diff #(
.S (S),
.D (D),
.DIFF_TERM ("TRUE")
) // Enable or disable diff termination
inst_datain (
.use_phase_detector(1'b1), // '1' enables the phase detector logic
.datain_p (datain_p),
.datain_n (datain_n),
.rxioclk (rx_bufpll_clk_xn),
.rx_serdesstrobe (rx_serdesstrobe),
.rx_bufg_pll_x1 (rx_bufg_x1),
.rx_bufg_pll_x2 (rx_bufg_x2),
.bitslip (bitslip),
.reset (not_bufpll_lckd),
.data_out (rxd),
.rx_toggle (rx_toggle),
.debug_in (2'b00),
.debug ()
);
always @ (posedge rx_bufg_x1) // process received data
begin
txd <= rxd;
end
// Transmitter Logic - Instantiate serialiser to generate forwarded clock and output data lines
serdes_n_to_1_s16_diff #(
.S(S),
.D(D)
) inst_clk_data_out (
.clkout_p (clkout_p),
.clkout_n (clkout_n),
.dataout_p (dataout_p),
.dataout_n (dataout_n),
.txioclk (rx_bufpll_clk_xn),
.txserdesstrobe(rx_serdesstrobe),
.tx_bufg_pll_x1(rx_bufg_x1),
.tx_bufg_pll_x2(rx_bufg_x2),
.reset (rst),
.datain (txd),
.clkin (TX_CLK_GEN)
); // Transmit a constant to make the clock
endmodule
| 7.222471 |
module top_nto1_pll_16_diff_tx (
input reset, // reset (active high)
input refclkin_p,
refclkin_n, // frequency generator clock input
output [5:0] dataout_p,
dataout_n, // lvds data outputs
output clkout_p,
clkout_n
); // lvds clock output
// Parameters for serdes factor and number of IO pins
parameter integer S = 16; // Set the serdes factor
parameter integer D = 6; // Set the number of inputs and outputs
parameter integer DS = (D * S) - 1; // Used for bus widths = serdes factor * number of inputs - 1
wire rst;
reg [DS:0] txd; // Registered Data to serdeses
// Parameters for clock generation
parameter [S-1:0] TX_CLK_GEN = 16'h00FF; // Transmit a constant to make a clock
assign rst = reset; // active high reset pin
// Reference Clock Input genertaes IO clocks via 2 x BUFIO2
clock_generator_pll_s16_diff #(
.S (S),
.PLLX (S),
.PLLD (1),
.CLKIN_PERIOD(16.000)
) inst_clkgen (
.reset (rst),
.clkin_p (refclkin_p),
.clkin_n (refclkin_n),
.ioclk (tx_bufpll_clk_xn),
.serdesstrobe (tx_serdesstrobe),
.gclk1 (tx_bufg_x1),
.gclk2 (tx_bufg_x2),
.bufpll_lckd (tx_bufpll_lckd)
);
always @ (posedge tx_bufg_x1 or posedge rst) // Generate some data to transmit
begin
if (rst == 1'b1) begin
txd <= 96'h000000000000000000000001;
end else begin
txd <= {txd[95:94] + 2'h1, txd[92:0], txd[93]};
end
end
// Transmitter Logic - Instantiate serialiser to generate forwarded clock and output data lines
serdes_n_to_1_s16_diff #(
.S(S),
.D(D)
) inst_clk_data_out (
.clkout_p (clkout_p),
.clkout_n (clkout_n),
.dataout_p (dataout_p),
.dataout_n (dataout_n),
.txioclk (tx_bufpll_clk_xn),
.txserdesstrobe(tx_serdesstrobe),
.tx_bufg_pll_x1(tx_bufg_x1),
.tx_bufg_pll_x2(tx_bufg_x2),
.reset (rst),
.datain (txd),
.clkin (TX_CLK_GEN)
); // Transmit a constant to make the clock
endmodule
| 7.222471 |
module top_nto1_pll_diff_rx (
input reset, // reset (active high)
input [ 7:0] datain_p,
datain_n, // lvds data inputs
input clkin_p,
clkin_n, // lvds clock input
output [55:0] dummy_out,
output rx_bufg_x1,
output rx_bufpll_lock,
output mon_bitslip
); // dummy outputs
// Parameters for serdes factor and number of IO pins
parameter integer S = 7; // Set the serdes factor to 8
parameter integer D = 8; // Set the number of inputs and outputs
parameter integer DS = (D * S) - 1; // Used for bus widths = serdes factor * number of inputs - 1
wire rst;
wire [DS:0] rxd; // Data from serdeses
reg [DS:0] rxr; // Registered Data from serdeses
reg state;
reg bslip;
reg [ 3:0] count;
wire [ 6:0] clk_iserdes_data;
assign rst = reset ; // active high reset pin
assign dummy_out = rxr ;
// Clock Input. Generate ioclocks via BUFIO2
serdes_1_to_n_clk_pll_s8_diff #(
.S (S),
//.CLKIN_PERIOD (6.700),
.CLKIN_PERIOD(12.5),
.PLLD (1),
.PLLX (S),
.BS ("TRUE")
) // Parameter to enable bitslip TRUE or FALSE (has to be true for video applications)
inst_clkin (
.clkin_p(clkin_p),
.clkin_n(clkin_n),
.rxioclk(rx_bufpll_clk_xn),
//.pattern1 (7'b1100001), // default values for 7:1 video applications
//.pattern2 (7'b1100011),
.pattern1(7'b1100001), // default values for 7:1 video applications
.pattern2(7'b1100011),
.rx_serdesstrobe(rx_serdesstrobe),
.rx_bufg_pll_x1(rx_bufg_x1),
.bitslip(bitslip),
.reset(rst),
.datain(clk_iserdes_data),
.rx_pll_lckd(), // PLL locked - only used if a 2nd BUFPLL is required
.rx_pllout_xs(), // Multiplied PLL clock - only used if a 2nd BUFPLL is required
.rx_bufpll_lckd(rx_bufpll_lckd)
);
// Data Inputs
assign not_bufpll_lckd = ~rx_bufpll_lckd;
assign rx_bufpll_lock = rx_bufpll_lckd;
assign mon_bitslip = bitslip;
serdes_1_to_n_data_s8_diff #(
.S(S),
.D(D)
) inst_datain (
.use_phase_detector(1'b1), // '1' enables the phase detector logic
.datain_p (datain_p),
.datain_n (datain_n),
.rxioclk (rx_bufpll_clk_xn),
.rxserdesstrobe (rx_serdesstrobe),
.gclk (rx_bufg_x1),
.bitslip (bitslip),
.reset (not_bufpll_lckd),
.data_out (rxd),
.debug_in (2'b00),
.debug ()
);
always @ (posedge rx_bufg_x1) // process received data
begin
rxr <= rxd;
end
endmodule
| 7.222471 |
module top_nto1_pll_diff_tx (
input reset, // reset (active high)
input refclkin_p,
refclkin_n, // frequency generator clock input
output [5:0] dataout_p,
dataout_n, // lvds data outputs
output clkout_p,
clkout_n
); // lvds clock output
// Parameters for serdes factor and number of IO pins
parameter integer S = 7; // Set the serdes factor
parameter integer D = 6; // Set the number of inputs and outputs
parameter integer DS = (D * S) - 1; // Used for bus widths = serdes factor * number of inputs - 1
wire rst;
reg [DS:0] txd; // Registered Data to serdeses
// Parameters for clock generation
parameter [S-1:0] TX_CLK_GEN = 7'b1100001; // Transmit a constant to make a clock
assign rst = reset; // active high reset pin
// Reference Clock Input genertaes IO clocks via 2 x BUFIO2
clock_generator_pll_s8_diff #(
.S (S),
.PLLX (7),
.PLLD (1),
.CLKIN_PERIOD(7.000)
) inst_clkgen (
.reset (rst),
.clkin_p (refclkin_p),
.clkin_n (refclkin_n),
.ioclk (tx_bufpll_clk_xn),
.serdesstrobe (tx_serdesstrobe),
.gclk (tx_bufg_x1),
.bufpll_lckd (tx_bufpll_lckd)
);
always @ (posedge tx_bufg_x1 or posedge rst) // Generate some data to transmit
begin
if (rst == 1'b1) begin
txd <= 42'h00000000001;
end else begin
txd <= {txd[40:0], txd[41]};
end
end
// Transmitter Logic - Instantiate serialiser to generate forwarded clock
serdes_n_to_1_s8_diff #(
.S(S),
.D(1)
) inst_clkout (
.dataout_p (clkout_p),
.dataout_n (clkout_n),
.txioclk (tx_bufpll_clk_xn),
.txserdesstrobe(tx_serdesstrobe),
.gclk (tx_bufg_x1),
.reset (rst),
.datain (TX_CLK_GEN)
); // Transmit a constant to make the clock
// Instantiate Outputs and output serialisers for output data lines
serdes_n_to_1_s8_diff #(
.S(S),
.D(D)
) inst_dataout (
.dataout_p (dataout_p),
.dataout_n (dataout_n),
.txioclk (tx_bufpll_clk_xn),
.txserdesstrobe(tx_serdesstrobe),
.gclk (tx_bufg_x1),
.reset (rst),
.datain (txd)
);
endmodule
| 7.222471 |
module fsm (
clock,
reset,
req,
gnt
);
input clock, reset;
input [1:0] req;
output [1:0] gnt;
wire clock, reset;
wire [1:0] req;
reg [1:0] gnt;
parameter SIZE = 3;
parameter IDLE = 3'b001, GNT0 = 3'b010, GNT1 = 3'b100, GNT2 = 3'b101, GNT3 = 3'b111;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @(posedge clock) begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt[0] <= 0;
gnt[1] <= 0;
end else
case (state)
IDLE:
if (req[0] == 1'b1) begin
state <= #1 GNT0;
gnt[0] <= 1;
end else if (req[1] == 1'b1) begin
gnt[1] <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0:
if (gnt[1] == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt[1] <= 0;
state <= #1 IDLE;
end
GNT1:
if (req[1] == 1'b1) begin
state <= #1 GNT2;
gnt[1] <= req[1];
end
GNT2:
if (gnt[0] == 1'b1) begin
state <= #1 GNT1;
gnt[1] <= req[1];
end
default: state <= #1 IDLE;
endcase
end
endmodule
| 7.229634 |
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
wire [1:0] g;
wire [1:0] r;
fsm u_fsm (
.clock(clk),
.reset(rst),
.req (r),
.gnt (g)
);
assign g0 = g[0];
assign g1 = g[1];
assign r[0] = a;
assign r[1] = b;
endmodule
| 7.233807 |
module mux2 (
S,
A,
B,
Y
);
input S;
input A, B;
output reg Y;
reg a_vect[0 +: 8];
reg b_vect[0 -: 8];
//import my_pkg::*;
always @(*) Y = (S) ? B : A;
endmodule
| 7.562788 |
module top (
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
always @(posedge cin) A <= o;
assign cout = cin ? y : x;
middle #(1'b0) u_mid1 (
.x(x),
.o(o),
.y(1'b0)
);
middle #(1'b0) u_mid2 (
.x(x),
.o(o),
.y(1'b1)
);
middle #(1'b0) u_mid3 (
.x(x),
.o(o),
.y(1'bX)
);
middle #(1'b0) u_mid4 (
.x(x),
.o(o),
.y(1'bX)
);
endmodule
| 7.233807 |
module middle (
input x,
input y,
output o
);
parameter Y = 1'b1;
urtl u_urtl (
.x(x),
.o(o),
.y(Y)
);
endmodule
| 6.553865 |
module urtl (
input x,
input y,
output o
);
assign o = x + y;
endmodule
| 6.943731 |
module mux16 (
D,
S,
Y
);
input [15:0] D;
input [3:0] S;
output Y;
parameter D_WIDTH = 8;
parameter S_WIDTH = 3;
localparam L = 6;
assign Y = D[S];
endmodule
| 8.26373 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
mux16 u_mux16 (
.S(S[3:0]),
.D(D[15:0]),
.Y(M16)
);
defparam u_mux16.D_WIDTH = 16; defparam u_mux16.S_DEPTH = 4;
endmodule
| 7.233807 |
module Top (
input wire clk,
output wire LED,
output wire [7:0] SEGMENT,
output wire [3:0] AN
);
wire Qa;
wire Qb;
wire Qc;
wire Qd;
wire [3:0] Hex;
/* module clk_1s at submodules/clk_1s.v */
clk_1s m0 (
.clk(clk),
.clk_1s(clk_1s)
);
/* You need to implement module Counter4b */
Counter4b m1 (
.clk(clk_1s),
.Qa (Qa),
.Qb (Qb),
.Qc (Qc),
.Qd (Qd),
.Rc (LED)
);
assign Hex = {Qd, Qc, Qb, Qa};
// Please replace module below with your module completed in Lab 6
// Pay attention to the correctness of the module name and port name
// NOTE: SEGMENT and Segement are different port names
// BTN[0]: LE, valid with value 0
// BTN[1]: point, light with value 1
// SW[7:4]: AN, light with value 1(AN[i] = ~SW[i+4])
// SW[3:0]: number to display
DispNumber_sch display (
.BTN(2'b00),
.SW({4'b0001, Hex}),
.SEGMENT(SEGMENT),
.AN(AN)
);
endmodule
| 6.64497 |
module Top (
input wire clk,
input wire SW,
output wire LED,
output wire [7:0] SEGMENT,
output wire [3:0] AN
);
wire [15:0] cnt;
wire [3:0] Hex;
wire clk_100ms;
/* module clk_100ms at submodules/clk_1s.v */
clk_100ms clk_div_100ms (
.clk(clk),
.clk_100ms(clk_100ms)
);
/* You need to implement module RevCounter */
RevCounter counter (
.clk(clk_100ms),
.s (SW),
.cnt(cnt),
.Rc (LED)
);
// Please replace module below with your module completed in Lab **7**
// imoprt submodules for module disp_num from your prev. project
disp_num display (
.clk(clk),
.HEXS(cnt),
.LES(4'b0000),
.points(4'b0000),
.RST(1'b0),
.AN(AN),
.Segment(SEGMENT)
);
endmodule
| 6.64497 |
module top (
input wire clk,
input wire ftdi_rx,
output wire ftdi_tx,
input wire board1_rx,
output wire board1_tx,
output reg led = 1'b1,
output wire [13:0] debug_header
);
// Combinatorial logic
assign board1_tx = ftdi_rx;
assign ftdi_tx = board1_rx;
assign debug_header = {11'd0, clk, ftdi_rx, ftdi_tx};
// Module instantiation
always @(posedge clk) begin
// Sequential logic
end
endmodule
| 7.233807 |
module to try patterns.
References:
https://www.improwis.com/tables/video.webt
https://www.kernel.org/doc/Documentation/devicetree/bindings/display/panel/panel-dpi.txt
https://www.waveshare.com/w/upload/4/44/4.3inch-480x272-Touch-LCD-B-UserManual.pdf
https://en.wikipedia.org/wiki/Color_Graphics_Adapter
Full graphic mode:
RGB565 = 16bit
480*272*16 = 2088960 = 255kB ram
GW1N SRAM Capacity(bits): 72 K
Text mode with 8x8 font and CGA color
480/8 = 60
272/8 = 34
16 colors: 4bit
60*34*4 =~ 8kbit
*/
module top (
input XTAL_IN, // 24 MHz
output [4:0] LCD_R,
output [5:0] LCD_G,
output [4:0] LCD_B,
output LCD_HSYNC,
output LCD_VSYNC,
output LCD_CLK,
output LCD_DEN
);
wire [8:0] col;
wire [8:0] lin;
assign LCD_DEN = vactive & hactive;
Gowin_rPLL pll(
.clkin (XTAL_IN), // input clkin 24MHz
.clkout (), // output clkout (not used)
.clkoutd (LCD_CLK) // pixel clock 9.2MHz
);
hcounter hcounter(
.pxclk_i (LCD_CLK), // pixel clock
.hsync_o (LCD_HSYNC), // horizontal sync pulse
.hactive_o (hactive), // horizontal signal in active zone
.col_o (col) // column number
);
vcounter vcounter(
.hsync_i (LCD_HSYNC), // horizontal clock
.vsync_o (LCD_VSYNC), // vertical sync pulse
.vactive_o (vactive), // vertical signal in active zone
.lin_o (lin) // line number
);
/*
// CGA bars
cga cga(
.color_i ({ col[8], lin[7], lin[6], lin[5] }),
.red_o (LCD_R),
.green_o (LCD_G),
.blue_o (LCD_B)
);
*/
// Checkboard 16x16 (30x17)
assign light = ~(col[4]^lin[4]);
cga cga(
.color_i ({ 1'b0, light, light, light }),
.red_o (LCD_R),
.green_o (LCD_G),
.blue_o (LCD_B)
);
endmodule
| 6.565989 |
module lpc_clkgen (
CLKIN_IN,
RST_IN,
CLKIN_IBUFG_OUT,
CLK0_OUT
);
input CLKIN_IN;
input RST_IN;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
wire CLKFB_IN;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
IBUFG CLKIN_IBUFG_INST (
.I(CLKIN_IN),
.O(CLKIN_IBUFG)
);
BUFG CLK0_BUFG_INST (
.I(CLK0_BUF),
.O(CLKFB_IN)
);
DCM DCM_INST (
.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(RST_IN),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(),
.PSDONE(),
.STATUS()
);
defparam DCM_INST.CLK_FEEDBACK = "1X";
defparam DCM_INST.CLKDV_DIVIDE = 2.0; defparam DCM_INST.CLKFX_DIVIDE = 1;
defparam DCM_INST.CLKFX_MULTIPLY = 4; defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam DCM_INST.CLKIN_PERIOD = 30.000; defparam DCM_INST.CLKOUT_PHASE_SHIFT = "FIXED";
defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; defparam DCM_INST.FACTORY_JF = 16'h8080;
defparam DCM_INST.PHASE_SHIFT = -18; defparam DCM_INST.STARTUP_WAIT = "FALSE";
endmodule
| 6.650903 |
module Top_PC_Instr_Display (
input wire W_clk,
W_rst_clk,
output [31:0] W_instr
);
wire W_dived_clk;
wire [31:0] W_pc, W_next_pc;
// don't div clk when simulating...
// ClkDiv clkdiv(
// .clk(W_clk),
// .rst(W_rst_clk),
// .R_dived_clk(W_dived_clk)
// );
assign W_dived_clk = W_clk;
PCAdd4 pcadd4 (
.W_pc(W_pc),
.W_next_pc(W_next_pc)
);
PC pc (
.clk(W_dived_clk),
.rst(W_rst_clk),
.W_next_pc(W_next_pc),
.W_pc(W_pc)
);
Instr_ROM instr_rom (
.clka(W_dived_clk), // input wire clka
.addra(W_pc), // input wire [9 : 0] addra
.douta(W_instr) // output wire [31 : 0] douta
);
// DisplayLED disLED(
// .clk(W_dived_clk),
// .rst(W_rst_display),
// .s(W_instr),
// .seg(W_seg),
// .sel(W_sel_slice)
// );
endmodule
| 8.993854 |
module top_PE_64 (
input CLK,
input RST,
input [ 7:0] io_in_a1,
input [ 18:0] io_in_b1,
input [135:0] io_in_d1,
input io_in_valid1,
input [ 5:0] io_in_control_shift1,
input io_in_control_propagate1,
output reg [ 7:0] io_out_a1,
output reg [ 18:0] io_out_b1,
output reg [135:0] io_out_c1,
output reg io_out_control_propagate1,
output reg [ 5:0] io_out_control_shift1,
output reg io_out_valid1
);
//Inputs
reg [ 7:0] io_in_a;
reg [ 18:0] io_in_b;
reg [135:0] io_in_d;
reg io_in_valid;
reg [ 5:0] io_in_control_shift;
reg io_in_control_propagate;
//Outputs
wire [ 7:0] io_out_a;
wire [ 18:0] io_out_b;
wire [135:0] io_out_c;
wire io_out_control_propagate;
wire [ 5:0] io_out_control_shift;
wire io_out_valid;
always @(posedge CLK) begin
io_in_a <= io_in_a1;
io_in_b <= io_in_b1;
io_in_d <= io_in_d1;
io_in_valid <= io_in_valid1;
io_in_control_shift <= io_in_control_shift1;
io_in_control_propagate <= io_in_control_propagate1;
io_out_a1 <= io_out_a;
io_out_b1 <= io_out_b;
io_out_c1 <= io_out_c;
io_out_control_propagate1 <= io_out_control_propagate;
io_out_control_shift1 <= io_out_control_shift;
io_out_valid1 <= io_out_valid;
end
PE_64 uut ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@165467.2]
.clock(CLK), // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@165468.4]
.RST(RST),
.io_in_a(io_in_a), // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@165470.4]
.io_in_b(io_in_b), // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@165470.4]
.io_in_d(io_in_d), // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@165470.4]
.io_out_a(io_out_a), // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@165470.4]
.io_out_b(io_out_b), //s,d,n,pze,nze[19:0]-- 20 bit
.io_out_c(io_out_c), //sum, carry [19:0], [19:0] -- 38 bit
.io_in_control_propagate (io_in_control_propagate), // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@165470.4]
.io_in_control_shift(io_in_control_shift), // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@165470.4]
.io_out_control_propagate(io_out_control_propagate), // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@165470.4]
.io_out_control_shift(io_out_control_shift), // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@165470.4]
.io_in_valid(io_in_valid), // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@165470.4]
.io_out_valid(io_out_valid) // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@165470.4]
);
endmodule
| 7.357911 |
module top_pe_8x8 (
clk,
in,
filter,
out
);
input clk;
input [127:0] in;
input [17:0] filter;
output [71:0] out;
wire [35:0] out1;
wire [35:0] out2;
wire [35:0] out3;
wire [35:0] out4;
wire [35:0] out5;
wire [35:0] out6;
pe_new_8x8 pe1 (
clk,
in[15:0],
filter[5:0],
out1[11:0]
);
pe_new_8x8 pe2 (
clk,
in[31:16],
filter[11:6],
out1[23:12]
);
pe_new_8x8 pe3 (
clk,
in[47:32],
filter[17:12],
out1[35:24]
);
assign out[11:0] = out1[35:24] + out1[23:12] + out1[11:0];
pe_new_8x8 pe4 (
clk,
in[31:16],
filter[5:0],
out2[11:0]
);
pe_new_8x8 pe5 (
clk,
in[47:32],
filter[11:6],
out2[23:12]
);
pe_new_8x8 pe6 (
clk,
in[63:48],
filter[17:12],
out2[35:24]
);
assign out[23:12] = out2[35:24] + out2[23:12] + out2[11:0];
pe_new_8x8 pe7 (
clk,
in[47:32],
filter[5:0],
out3[11:0]
);
pe_new_8x8 pe8 (
clk,
in[63:48],
filter[11:6],
out3[23:12]
);
pe_new_8x8 pe9 (
clk,
in[79:64],
filter[17:12],
out3[35:24]
);
assign out[35:24] = out3[35:24] + out3[23:12] + out3[11:0];
pe_new_8x8 pe10 (
clk,
in[63:48],
filter[5:0],
out4[11:0]
);
pe_new_8x8 pe11 (
clk,
in[79:64],
filter[11:6],
out4[23:12]
);
pe_new_8x8 pe12 (
clk,
in[95:80],
filter[17:12],
out4[35:24]
);
assign out[47:36] = out4[35:24] + out4[23:12] + out4[11:0];
pe_new_8x8 pe13 (
clk,
in[79:64],
filter[5:0],
out5[11:0]
);
pe_new_8x8 pe14 (
clk,
in[95:80],
filter[11:6],
out5[23:12]
);
pe_new_8x8 pe15 (
clk,
in[111:96],
filter[17:12],
out5[35:24]
);
assign out[59:48] = out5[35:24] + out5[23:12] + out5[11:0];
pe_new_8x8 pe16 (
clk,
in[95:80],
filter[5:0],
out6[11:0]
);
pe_new_8x8 pe17 (
clk,
in[111:96],
filter[11:6],
out6[23:12]
);
pe_new_8x8 pe18 (
clk,
in[127:112],
filter[17:12],
out6[35:24]
);
assign out[71:60] = out6[35:24] + out6[23:12] + out6[11:0];
endmodule
| 6.526746 |
module top_PE_tb;
reg clk_tb;
reg rst_tb;
wire [2:0] pop_out_tb;
top_PE aaa (
.clk(clk_tb),
.rst(rst_tb),
.pop_out(pop_out_tb)
);
always begin
#20 clk_tb = ~clk_tb;
end
initial begin
rst_tb = 1'b0;
clk_tb = 1'b0;
#10 rst_tb = 1'b1;
#10 rst_tb = 1'b0;
#750;
$finish;
end
endmodule
| 7.048279 |
module of the design which forms
rounds and connects KeyExpantion using pipelined
architecture
Owner : Amr Salah
*/
`timescale 1 ns/1 ps
module Top_PipelinedCipher
#
(
parameter DATA_W = 128, //data width
parameter KEY_L = 128, //key length
parameter NO_ROUNDS = 10 //number of rounds
)
(
input clk, //system clock
input reset, //asynch reset
input data_valid_in, //data valid signal
input cipherkey_valid_in, //cipher key valid signal
input [KEY_L-1:0] cipher_key, //cipher key
input [DATA_W-1:0] plain_text, //plain text
output valid_out, //output valid signal
output [DATA_W-1:0] cipher_text //cipher text
);
wire [NO_ROUNDS-1:0] valid_round_key; //all round keys valid signals KeyExpantion output
wire [NO_ROUNDS-1:0] valid_round_data; //all rounds ouput data valid signals
wire [DATA_W-1:0] data_round [0:NO_ROUNDS-1]; //all rounds data
wire valid_sub2shift; //for final round connection
wire valid_shift2key; //
wire [DATA_W-1:0]data_sub2shift; //
wire [DATA_W-1:0]data_shift2key; //
wire [(NO_ROUNDS*DATA_W)-1:0] W; //all round keys
reg[DATA_W-1:0] data_shift2key_delayed; //for delay register
reg valid_shift2key_delayed;
//instantiate Key Expantion which will feed every round with round key
KeyExpantion #(DATA_W,KEY_L,NO_ROUNDS) U_KEYEXP(clk,reset,cipherkey_valid_in,cipher_key,W,valid_round_key);
//due to algorithm,first cipher key will be xored witht plain text
AddRoundKey #(DATA_W)U0_ARK(clk,reset,data_valid_in,cipherkey_valid_in,plain_text,cipher_key,valid_round_data[0],data_round[0]);
//instantiate all rounds , connect them with key expantion
genvar i;
generate
for(i=0;i<NO_ROUNDS-1;i=i+1) begin : ROUND
Round #(DATA_W)U_ROUND(clk,reset,valid_round_data[i],valid_round_key[i],data_round[i],W[(NO_ROUNDS-i)*DATA_W-1:(NO_ROUNDS-i-1)*DATA_W],valid_round_data[i+1],data_round[i+1]);
end
endgenerate
//this is the final round it doesn't contain mixcolumns as declared in fips197 standard document
SubBytes #(DATA_W) U_SUB (clk,reset,valid_round_data[NO_ROUNDS-1],data_round[NO_ROUNDS-1],valid_sub2shift,data_sub2shift);
ShiftRows #(DATA_W) U_SH (clk,reset,valid_sub2shift,data_sub2shift,valid_shift2key,data_shift2key);
AddRoundKey #(DATA_W) U_KEY (clk,reset,valid_shift2key_delayed,valid_round_key[NO_ROUNDS-1],data_shift2key_delayed,W[DATA_W-1:0],valid_out,cipher_text);
/*as the final round has only three stages a delay register should be introduced
to be balanced with key expantion*/
always @(posedge clk or negedge reset)
if(!reset)begin
valid_shift2key_delayed <= 1'b0;
data_shift2key_delayed <= 'b0;
end else begin
if(valid_shift2key)begin
data_shift2key_delayed <= data_shift2key;
end
valid_shift2key_delayed <= valid_shift2key;
end
endmodule
| 8.52834 |
module Top_PipelinedCipher_tb ();
parameter DATA_W = 128; //data width
parameter KEY_L = 128; //key length
parameter NO_ROUNDS = 10; //number of rounds
parameter Clk2Q = 2; //Clk-Q delay
parameter No_Patterns = 284; //number of patterns
reg clk;
reg reset;
reg data_valid_in;
reg cipherkey_valid_in;
reg [KEY_L-1:0] cipher_key;
reg [DATA_W-1:0] plain_text;
wire valid_out;
wire [DATA_W-1:0] cipher_text;
reg dut_error;
reg [DATA_W-1:0] data_expected;
reg [DATA_W-1:0] data_input_vectors[0:No_Patterns-1];
reg [DATA_W-1:0] cipherkey_input_vectors[0:No_Patterns-1];
reg [DATA_W-1:0] output_vectors[0:No_Patterns-1];
integer i;
Top_PipelinedCipher U //connecting DUT
(
.clk(clk),
.reset(reset),
.data_valid_in(data_valid_in),
.cipherkey_valid_in(cipherkey_valid_in),
.cipher_key(cipher_key),
.plain_text(plain_text),
.valid_out(valid_out),
.cipher_text(cipher_text)
);
event terminate_sim;
event reset_enable;
initial begin //reading input data and cipherkey vectors and expected output vectors
$readmemh("topcipher_data_test_inputs.txt", data_input_vectors);
$readmemh("topcipher_key_test_inputs.txt", cipherkey_input_vectors);
$readmemh("topcipher_test_outputs.txt", output_vectors);
end
initial begin
$display("###################################################");
clk = 0;
reset = 1;
data_valid_in = 0;
cipherkey_valid_in = 0;
dut_error = 0; //design error counter
end
always #5 clk = !clk; //clock generator
`ifndef GATES //if not gate simulation
initial begin
$dumpfile("Top_PipelinedCipher.vcd");
$dumpvars;
end
`endif
initial
forever
@(terminate_sim) begin //simulation termination logic
$display("Terminating simulation");
if (dut_error == 0) begin
$display("Simulation Result : PASSED");
end else begin
$display("Simulation Result : FAILED");
end
$display("###################################################");
#1 $stop;
end
event reset_done;
initial //reset logic
forever begin
@(reset_enable);
@(negedge clk) $display("Applying reset");
reset = 0;
data_expected = 'b0;
@(negedge clk) reset = 1;
$display("Came out of Reset");
->reset_done;
end
initial begin
#10->reset_enable;
@(reset_done);
for (i = 0; i < No_Patterns; i = i + 1) begin //apply inputs
@(posedge clk) #Clk2Q data_valid_in = 1; //assert valid signals
cipherkey_valid_in = 1;
plain_text = data_input_vectors[i];
cipher_key = cipherkey_input_vectors[i];
end
@(posedge clk) data_valid_in = 0; //deassert valid signals
cipherkey_valid_in = 0;
end
integer j;
initial
@(reset_done) begin
repeat ((4 * NO_ROUNDS) + 1) begin //waiting for first output (latency)
@(posedge clk);
end
for (j = 0; j < No_Patterns; j = j + 1) begin //assign expected outputs
@(posedge clk) data_expected = output_vectors[j];
end
end
//compare logic
always @(posedge clk) begin
if (valid_out || (!reset)) begin
if (data_expected != cipher_text) begin
$display("DUT ERROR AT TIME%d", $time);
$display("Expected Data value %h, Got Data Value %h", data_expected, cipher_text);
dut_error = 1;
->terminate_sim; //stop simulation when error occures
end
end
if (j == No_Patterns) begin //terminate simulation after the end of output vectors
->terminate_sim;
end
end
endmodule
| 6.741278 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_29 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n1;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n1),
.D (EN),
.Q (net24637)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n1)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_28 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_27 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_26 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_25 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_24 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_23 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_22 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_21 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_20 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_38 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24560, n1;
AND2X1_HVT main_gate (
.A1(net24560),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n1),
.D (EN),
.Q (net24560)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n1)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_37 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24560, n2;
AND2X1_HVT main_gate (
.A1(net24560),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24560)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
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