code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module FPAddSub_PrealignModule (
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] B; // Input B, a 32-bit floating point number
input operation;
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [9:0] ShiftDet;
output [4:0] InputExc; // Input numbers are exceptions
output [`DWIDTH-2:0] Aout;
output [`DWIDTH-2:0] Bout;
output Opout;
// Internal signals // If signal is high...
wire ANaN; // A is a NaN (Not-a-Number)
wire BNaN; // B is a NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [`EXPONENT-1:0] DAB; // ExpA - ExpB
wire [`EXPONENT-1:0] DBA; // ExpB - ExpA
assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
// Put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign DAB = (A[30:23] - B[30:23]) ;
//assign DBA = (B[30:23] - A[30:23]) ;
assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1);
assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1);
assign Sa = A[`DWIDTH-1]; // A's sign bit
assign Sb = B[`DWIDTH-1]; // B's sign bit
assign ShiftDet = {DBA[4:0], DAB[4:0]}; // Shift data
assign Opout = operation;
assign Aout = A[`DWIDTH-2:0];
assign Bout = B[`DWIDTH-2:0];
endmodule
| 7.069212 |
module td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #(
parameter ID = 25,
NUM_STAGE = 5,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 15:0] a_tdata;
wire b_tvalid;
wire [ 15:0] b_tdata;
wire r_tvalid;
wire [ 15:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg ce_r;
wire [dout_WIDTH-1:0] dout_i;
reg [dout_WIDTH-1:0] dout_r;
//------------------------Instantiation------------------
td_fused_top_ap_hadd_3_full_dsp_16 td_fused_top_ap_hadd_3_full_dsp_16_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce_r;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout_i = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @(posedge clk) begin
ce_r <= ce;
end
always @(posedge clk) begin
if (ce_r) begin
dout_r <= dout_i;
end
end
assign dout = ce_r ? dout_i : dout_r;
endmodule
| 6.827284 |
module td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #(
parameter ID = 20,
NUM_STAGE = 4,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 15:0] a_tdata;
wire b_tvalid;
wire [ 15:0] b_tdata;
wire r_tvalid;
wire [ 15:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg ce_r;
wire [dout_WIDTH-1:0] dout_i;
reg [dout_WIDTH-1:0] dout_r;
//------------------------Instantiation------------------
td_fused_top_ap_hmul_2_max_dsp_16 td_fused_top_ap_hmul_2_max_dsp_16_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce_r;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout_i = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @(posedge clk) begin
ce_r <= ce;
end
always @(posedge clk) begin
if (ce_r) begin
dout_r <= dout_i;
end
end
assign dout = ce_r ? dout_i : dout_r;
endmodule
| 6.827284 |
module td_fused_top_ap_hmul_2_max_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wire [15:0] m_axis_result_tdata
);
reg [15:0] a_reg, b_reg, res, res_reg;
always @(posedge aclk) begin
if (aclken) begin
a_reg <= s_axis_a_tdata;
b_reg <= s_axis_b_tdata;
res_reg <= res;
end
end
`ifdef complex_dsp
multiply_fp u_mult_fp (
.a (a_reg),
.b (b_reg),
.out(res)
);
`else
FPMult_16 u_FPMult (
.clk(),
.rst(1'b0),
.a(a_reg),
.b(b_reg),
.result(res),
.flags()
);
`endif
assign m_axis_result_tdata = res_reg;
endmodule
| 6.827284 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
input [`EXPONENT:0] RoundEP; // Normalized exponent + 1
input Sp; // Product sign
input GRS;
input [4:0] InputExc;
// Output Ports
output [`DWIDTH-1:0] Z; // Final product
output [4:0] Flags;
// Internal Signals
wire [`EXPONENT:0] FinalE; // Rounded exponent
wire [`MANTISSA:0] FinalM;
wire [`MANTISSA:0] PreShiftM;
assign PreShiftM = GRS ? RoundMP : RoundM; // Round up if R and (G or S)
// Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow)
assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]);
assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done
assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]}; // Putting the pieces together
assign Flags = InputExc[4:0];
endmodule
| 7.570448 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
output [`MANTISSA:0] RoundM;
output [`MANTISSA:0] RoundMP;
assign RoundE = NormE - 15;
assign RoundEP = NormE - 14;
assign RoundM = NormM;
assign RoundMP = NormM;
endmodule
| 7.947312 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [`EXPONENT-1:0] Ea; // A's exponent
output [`EXPONENT-1:0] Eb; // B's exponent
output [2*`MANTISSA+1:0] Mp; // Mantissa product
output [4:0] InputExc; // Input numbers are exceptions
// Internal signals // If signal is high...
wire ANaN; // A is a signalling NaN
wire BNaN; // B is a signalling NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [`MANTISSA-1:0] Ma;
wire [`MANTISSA-1:0] Mb;
assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
// Check for any exceptions and put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ;
// Take input numbers apart
assign Sa = a[`DWIDTH-1]; // A's sign
assign Sb = b[`DWIDTH-1]; // B's sign
assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception
assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception
// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB];
// assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB];
//assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ;
assign Mp = ({1'b1, a[`MANTISSA-1:0]} * {1'b1, b[`MANTISSA-1:0]});
//We multiply part of the mantissa here
//Full mantissa of A
//Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B
// wire [`ACTUAL_MANTISSA-1:0] inp_A;
// wire [`ACTUAL_MANTISSA-1:0] inp_B;
// assign inp_A = {1'b1, Ma};
// assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]};
// DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp));
endmodule
| 7.427166 |
module td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #(
parameter ID = 37,
NUM_STAGE = 5,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 15:0] a_tdata;
wire b_tvalid;
wire [ 15:0] b_tdata;
wire r_tvalid;
wire [ 15:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg ce_r;
wire [dout_WIDTH-1:0] dout_i;
reg [dout_WIDTH-1:0] dout_r;
//------------------------Instantiation------------------
// Just replace with the hadd, logic is similar enough.
//td_fused_top_ap_hsub_3_full_dsp_16 td_fused_top_ap_hsub_3_full_dsp_16_u (
td_fused_top_ap_hadd_3_full_dsp_16 td_fused_top_ap_hsub_3_full_dsp_16_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce_r;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout_i = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @(posedge clk) begin
ce_r <= ce;
end
always @(posedge clk) begin
if (ce_r) begin
dout_r <= dout_i;
end
end
assign dout = ce_r ? dout_i : dout_r;
endmodule
| 6.827284 |
module td_fused_top_ap_hadd_3_full_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wire [15:0] m_axis_result_tdata
);
reg [15:0] a_reg, b_reg, res, res_reg;
always @(posedge aclk) begin
if (aclken) begin
a_reg <= s_axis_a_tdata;
b_reg <= s_axis_b_tdata;
res_reg <= res;
end
end
`ifdef complex_dsp
adder_fp u_add_fp (
.a (a_reg),
.b (b_reg),
.out(res)
);
`else
FPAddSub u_FPAddSub (
.clk(),
.rst(1'b0),
.a(a_reg),
.b(b_reg),
.operation(1'b0),
.result(res),
.flags()
);
`endif
assign m_axis_result_tdata = res_reg;
endmodule
| 6.827284 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
input EOF;
// Output ports
output [`DWIDTH-1:0] P; // Final result
output [4:0] Flags; // Exception flags
// Internal signals
wire Overflow; // Overflow flag
wire Underflow; // Underflow flag
wire DivideByZero; // Divide-by-Zero flag (always 0 in Add/Sub)
wire Invalid; // Invalid inputs or result
wire Inexact; // Result is inexact because of rounding
// Exception flags
// Result is too big to be represented
assign Overflow = EOF | InputExc[1] | InputExc[0];
// Result is too small to be represented
assign Underflow = NegE & (R | S);
// Infinite result computed exactly from finite operands
assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0];
// Invalid inputs or operation
assign Invalid = |(InputExc[4:2]);
// Inexact answer due to rounding, overflow or underflow
assign Inexact = (R | S) | Overflow | Underflow;
// Put pieces together to form final result
assign P = Z;
// Collect exception flags
assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact};
endmodule
| 7.326377 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round bit
input S; // Sticky bit
input G;
input Sa; // A's sign bit
input Sb; // B's sign bit
input Ctrl; // Control bit (operation)
input MaxAB;
// Output ports
output [`DWIDTH-1:0] Z; // Final result
output EOF;
// Internal signals
wire [ `MANTISSA:0] RoundUpM; // Rounded up sum with room for overflow
wire [`MANTISSA-1:0] RoundM; // The final rounded sum
wire [ `EXPONENT:0] RoundE; // Rounded exponent (note extra bit due to poential overflow )
wire RoundUp; // Flag indicating that the sum should be rounded up
wire FSgn;
wire ExpAdd; // May have to add 1 to compensate for overflow
wire RoundOF; // Rounding overflow
// The cases where we need to round upwards (= adding one) in Round to nearest, tie to even
assign RoundUp = (G & ((R | S) | NormM[0]));
// Note that in the other cases (rounding down), the sum is already 'rounded'
assign RoundUpM = (NormM + 1); // The sum, rounded up by 1
assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM); // Compute final mantissa
assign RoundOF = RoundUp & RoundUpM[`MANTISSA]; // Check for overflow when rounding up
// Calculate post-rounding exponent
assign ExpAdd = (RoundOF ? 1'b1 : 1'b0); // Add 1 to exponent to compensate for overflow
assign RoundE = ZeroSum ? 5'b00000 : (NormE + ExpAdd); // Final exponent
// If zero, need to determine sign according to rounding
assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ;
// Assign final result
assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]};
// Indicate exponent overflow
assign EOF = RoundE[`EXPONENT];
endmodule
| 7.753919 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0] NormM; // Normalized mantissa
output [`EXPONENT:0] NormE; // Adjusted exponent
output ZeroSum; // Zero flag
output NegE; // Flag indicating negative exponent
output R; // Round bit
output S; // Final sticky bit
output FG;
// Internal signals
wire MSBShift; // Flag indicating that a second shift is needed
wire [`EXPONENT:0] ExpOF; // MSB set in sum indicates overflow
wire [`EXPONENT:0] ExpOK; // MSB not set, no adjustment
// Calculate normalized exponent and mantissa, check for all-zero sum
assign MSBShift = PSSum[`DWIDTH]; // Check MSB in unnormalized sum
assign ZeroSum = ~|PSSum; // Check for all zero sum
assign ExpOK = CExp - Shift; // Adjust exponent for new normalized mantissa
assign NegE = ExpOK[`EXPONENT]; // Check for exponent overflow
assign ExpOF = CExp - Shift + 1'b1; // If MSB set, add one to exponent(x2)
assign NormE = MSBShift ? ExpOF : ExpOK; // Check for exponent overflow
assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1]; // The new, normalized mantissa
// Also need to compute sticky and round bits for the rounding stage
assign FG = PSSum[`EXPONENT];
assign R = PSSum[`EXPONENT-1];
assign S = |PSSum[`EXPONENT-2:0];
endmodule
| 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1:0] Stage1;
reg [ `DWIDTH:0] Lvl3;
wire [2*`DWIDTH+1:0] Stage2;
integer i; // Loop variable
assign Stage1 = {MminP, MminP};
always @(*) begin // Rotate {0 | 4 | 8 | 12} bits
case (Shift[3:2])
// Rotate by 0
2'b00: //Lvl2 <= Stage1[`DWIDTH:0];
begin
Lvl2 = Stage1[`DWIDTH:0];
end
// Rotate by 4
2'b01: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-4]; end Lvl2[3:0] <= 0; end
begin
Lvl2[`DWIDTH:(`DWIDTH-4)] = Stage1[3:0];
Lvl2[`DWIDTH-4-1:0] = Stage1[`DWIDTH-4];
end
// Rotate by 8
2'b10: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-8]; end Lvl2[7:0] <= 0; end
begin
Lvl2[`DWIDTH:(`DWIDTH-8)] = Stage1[3:0];
Lvl2[`DWIDTH-8-1:0] = Stage1[`DWIDTH-8];
end
// Rotate by 12
2'b11: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-12]; end Lvl2[11:0] <= 0; end
begin
Lvl2[`DWIDTH:(`DWIDTH-12)] = Stage1[3:0];
Lvl2[`DWIDTH-12-1:0] = Stage1[`DWIDTH-12];
end
endcase
end
assign Stage2 = {Lvl2, Lvl2};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: //Lvl3 <= Stage2[`DWIDTH:0];
begin
Lvl3 = Stage2[`DWIDTH:0];
end
// Rotate by 1
2'b01: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-1]; end Lvl3[0] <= 0; end
begin
Lvl3[`DWIDTH:(`DWIDTH-1)] = Stage2[3:0];
Lvl3[`DWIDTH-1-1:0] = Stage2[`DWIDTH-1];
end
// Rotate by 2
2'b10: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-2]; end Lvl3[1:0] <= 0; end
begin
Lvl3[`DWIDTH:(`DWIDTH-2)] = Stage2[3:0];
Lvl3[`DWIDTH-2-1:0] = Stage2[`DWIDTH-2];
end
// Rotate by 3
2'b11: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-3]; end Lvl3[2:0] <= 0; end
begin
Lvl3[`DWIDTH:(`DWIDTH-3)] = Stage2[3:0];
Lvl3[`DWIDTH-3-1:0] = Stage2[`DWIDTH-3];
end
endcase
end
// Assign outputs
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
// Determine normalization shift amount by finding leading nought
assign Shift = (
Sum[16] ? 5'b00000 :
Sum[15] ? 5'b00001 :
Sum[14] ? 5'b00010 :
Sum[13] ? 5'b00011 :
Sum[12] ? 5'b00100 :
Sum[11] ? 5'b00101 :
Sum[10] ? 5'b00110 :
Sum[9] ? 5'b00111 :
Sum[8] ? 5'b01000 :
Sum[7] ? 5'b01001 :
Sum[6] ? 5'b01010 :
Sum[5] ? 5'b01011 :
Sum[4] ? 5'b01100 : 5'b01101
// Sum[19] ? 5'b01101 :
// Sum[18] ? 5'b01110 :
// Sum[17] ? 5'b01111 :
// Sum[16] ? 5'b10000 :
// Sum[15] ? 5'b10001 :
// Sum[14] ? 5'b10010 :
// Sum[13] ? 5'b10011 :
// Sum[12] ? 5'b10100 :
// Sum[11] ? 5'b10101 :
// Sum[10] ? 5'b10110 :
// Sum[9] ? 5'b10111 :
// Sum[8] ? 5'b11000 :
// Sum[7] ? 5'b11001 : 5'b11010
);
reg [`DWIDTH:0] Lvl1;
always @(*) begin
// Rotate by 16?
Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum;
end
// Assign outputs
assign Mmin = Lvl1; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of smaller number
input MaxAB; // Indicates the larger number (0/A, 1/B)
input OpMode; // Operation to be performed (0/Add, 1/Sub)
// Output ports
output [`DWIDTH:0] Sum; // The result of the operation
output PSgn; // The sign for the result
output Opr; // The effective (performed) operation
assign Opr = (OpMode ^ Sa ^ Sb); // Resolve sign to determine operation
// Perform effective operation
assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, 5'b00000} - {Mmin, 5'b00000}) : ({1'b1, Mmax, 5'b00000} + {Mmin, 5'b00000}) ;
// Assign result sign
assign PSgn = (MaxAB ? Sb : Sa);
endmodule
| 6.632792 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANTISSA:0] Lvl3;
wire [2*`MANTISSA+1:0] Stage2;
integer j; // Loop variable
assign Stage2 = {11'b0, MminP};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[`MANTISSA:0];
// Rotate by 1
2'b01: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+1];
end /*Lvl3[`MANTISSA] <= 0; */
end
// Rotate by 2
2'b10: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+2];
end /*Lvl3[`MANTISSA:`MANTISSA-1] <= 0;*/
end
// Rotate by 3
2'b11: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+3];
end /*Lvl3[`MANTISSA:`MANTISSA-2] <= 0;*/
end
endcase
end
// Assign output
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.969233 |
module FPAddSub_AlignShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [2:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal signals
reg [ `MANTISSA:0] Lvl1;
reg [ `MANTISSA:0] Lvl2;
wire [2*`MANTISSA+1:0] Stage1;
integer i; // Loop variable
always @(*) begin
// Rotate by 16?
//Lvl1 <= Shift[2] ? {17'b00000000000000001, MminP[22:16]} : {1'b1, MminP};
Lvl1 <= Shift[2] ? {11'b0000000000} : {1'b1, MminP};
end
assign Stage1 = {11'b0, Lvl1};
always @(*) begin // Rotate {0 | 4 | 8 | 12} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl2 <= Stage1[`MANTISSA:0];
// Rotate by 4
2'b01: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+4];
end /*Lvl2[`MANTISSA:`MANTISSA-3] <= 0;*/
end
// Rotate by 8
2'b10: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+8];
end /*Lvl2[`MANTISSA:`MANTISSA-7] <= 0;*/
end
// Rotate by 12
2'b11: Lvl2[`MANTISSA:0] <= 0;
//2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[`MANTISSA:`MANTISSA-12] <= 0; end
endcase
end
// Assign output to next shift stage
assign Mmin = Lvl2;
endmodule
| 6.969233 |
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-2:0] B; // Input B, a 32-bit floating point number
input [9:0] ShiftDet;
// Output ports
output [`EXPONENT-1:0] CExp; // Common Exponent
output MaxAB; // Incidates larger of A and B (0/A, 1/B)
output [4:0] Shift; // Number of steps to smaller mantissa shift right
output [`MANTISSA-1:0] Mmin; // Smaller mantissa
output [`MANTISSA-1:0] Mmax; // Larger mantissa
// Internal signals
//wire BOF ; // Check for shifting overflow if B is larger
//wire AOF ; // Check for shifting overflow if A is larger
assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]);
//assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits
//assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits
// Determine final shift value
//assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ;
assign Shift = MaxAB ? ShiftDet[9:5] : ShiftDet[4:0];
// Take out smaller mantissa and append shift space
assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0];
// Take out larger mantissa
assign Mmax = MaxAB ? B[`MANTISSA-1:0] : A[`MANTISSA-1:0];
// Common exponent
assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]);
endmodule
| 6.969233 |
module FPAddSub_PrealignModule (
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] B; // Input B, a 32-bit floating point number
input operation;
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [9:0] ShiftDet;
output [4:0] InputExc; // Input numbers are exceptions
output [`DWIDTH-2:0] Aout;
output [`DWIDTH-2:0] Bout;
output Opout;
// Internal signals // If signal is high...
wire ANaN; // A is a NaN (Not-a-Number)
wire BNaN; // B is a NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [`EXPONENT-1:0] DAB; // ExpA - ExpB
wire [`EXPONENT-1:0] DBA; // ExpB - ExpA
assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
// Put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign DAB = (A[30:23] - B[30:23]) ;
//assign DBA = (B[30:23] - A[30:23]) ;
assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1);
assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1);
assign Sa = A[`DWIDTH-1]; // A's sign bit
assign Sb = B[`DWIDTH-1]; // B's sign bit
assign ShiftDet = {DBA[4:0], DAB[4:0]}; // Shift data
assign Opout = operation;
assign Aout = A[`DWIDTH-2:0];
assign Bout = B[`DWIDTH-2:0];
endmodule
| 7.069212 |
module td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #(
parameter ID = 20,
NUM_STAGE = 4,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 15:0] a_tdata;
wire b_tvalid;
wire [ 15:0] b_tdata;
wire r_tvalid;
wire [ 15:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg ce_r;
wire [dout_WIDTH-1:0] dout_i;
reg [dout_WIDTH-1:0] dout_r;
//------------------------Instantiation------------------
td_fused_top_ap_hmul_2_max_dsp_16 td_fused_top_ap_hmul_2_max_dsp_16_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce_r;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout_i = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @(posedge clk) begin
ce_r <= ce;
end
always @(posedge clk) begin
if (ce_r) begin
dout_r <= dout_i;
end
end
assign dout = ce_r ? dout_i : dout_r;
endmodule
| 6.827284 |
module td_fused_top_ap_hmul_2_max_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wire [15:0] m_axis_result_tdata
);
reg [15:0] a_reg, b_reg, res, res_reg;
always @(posedge aclk) begin
if (aclken) begin
a_reg <= s_axis_a_tdata;
b_reg <= s_axis_b_tdata;
res_reg <= res;
end
end
`ifdef complex_dsp
multiply_fp u_mult_fp (
.a (a_reg),
.b (b_reg),
.out(res)
);
`else
FPMult_16 u_FPMult (
.clk(),
.rst(1'b0),
.a(a_reg),
.b(b_reg),
.result(res),
.flags()
);
`endif
assign m_axis_result_tdata = res_reg;
endmodule
| 6.827284 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
input [`EXPONENT:0] RoundEP; // Normalized exponent + 1
input Sp; // Product sign
input GRS;
input [4:0] InputExc;
// Output Ports
output [`DWIDTH-1:0] Z; // Final product
output [4:0] Flags;
// Internal Signals
wire [`EXPONENT:0] FinalE; // Rounded exponent
wire [`MANTISSA:0] FinalM;
wire [`MANTISSA:0] PreShiftM;
assign PreShiftM = GRS ? RoundMP : RoundM; // Round up if R and (G or S)
// Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow)
assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]);
assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done
assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]}; // Putting the pieces together
assign Flags = InputExc[4:0];
endmodule
| 7.570448 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
output [`MANTISSA:0] RoundM;
output [`MANTISSA:0] RoundMP;
assign RoundE = NormE - 15;
assign RoundEP = NormE - 14;
assign RoundM = NormM;
assign RoundMP = NormM;
endmodule
| 7.947312 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [`EXPONENT-1:0] Ea; // A's exponent
output [`EXPONENT-1:0] Eb; // B's exponent
output [2*`MANTISSA+1:0] Mp; // Mantissa product
output [4:0] InputExc; // Input numbers are exceptions
// Internal signals // If signal is high...
wire ANaN; // A is a signalling NaN
wire BNaN; // B is a signalling NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [`MANTISSA-1:0] Ma;
wire [`MANTISSA-1:0] Mb;
assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
// Check for any exceptions and put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ;
// Take input numbers apart
assign Sa = a[`DWIDTH-1]; // A's sign
assign Sb = b[`DWIDTH-1]; // B's sign
assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception
assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception
// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB];
// assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB];
//assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ;
assign Mp = ({1'b1, a[`MANTISSA-1:0]} * {1'b1, b[`MANTISSA-1:0]});
//We multiply part of the mantissa here
//Full mantissa of A
//Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B
// wire [`ACTUAL_MANTISSA-1:0] inp_A;
// wire [`ACTUAL_MANTISSA-1:0] inp_B;
// assign inp_A = {1'b1, Ma};
// assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]};
// DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp));
endmodule
| 7.427166 |
module td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #(
parameter ID = 45,
NUM_STAGE = 8,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 15:0] a_tdata;
wire b_tvalid;
wire [ 15:0] b_tdata;
wire r_tvalid;
wire [ 15:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg ce_r;
wire [dout_WIDTH-1:0] dout_i;
reg [dout_WIDTH-1:0] dout_r;
//------------------------Instantiation------------------
td_fused_top_ap_hadd_6_full_dsp_16 td_fused_top_ap_hadd_6_full_dsp_16_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce_r;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout_i = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @(posedge clk) begin
ce_r <= ce;
end
always @(posedge clk) begin
if (ce_r) begin
dout_r <= dout_i;
end
end
assign dout = ce_r ? dout_i : dout_r;
endmodule
| 6.827284 |
module td_fused_top_ap_hadd_6_full_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wire [15:0] m_axis_result_tdata
);
reg [15:0] a_reg, b_reg, res, res_reg;
always @(posedge aclk) begin
if (aclken) begin
a_reg <= s_axis_a_tdata;
b_reg <= s_axis_b_tdata;
res_reg <= res;
end
end
`ifdef complex_dsp
adder_fp u_add_fp (
.a (a_reg),
.b (b_reg),
.out(res)
);
`else
FPAddSub u_FPAddSub (
.clk(),
.rst(1'b0),
.a(a_reg),
.b(b_reg),
.operation(1'b0),
.result(res),
.flags()
);
`endif
assign m_axis_result_tdata = res_reg;
endmodule
| 6.827284 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
input EOF;
// Output ports
output [`DWIDTH-1:0] P; // Final result
output [4:0] Flags; // Exception flags
// Internal signals
wire Overflow; // Overflow flag
wire Underflow; // Underflow flag
wire DivideByZero; // Divide-by-Zero flag (always 0 in Add/Sub)
wire Invalid; // Invalid inputs or result
wire Inexact; // Result is inexact because of rounding
// Exception flags
// Result is too big to be represented
assign Overflow = EOF | InputExc[1] | InputExc[0];
// Result is too small to be represented
assign Underflow = NegE & (R | S);
// Infinite result computed exactly from finite operands
assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0];
// Invalid inputs or operation
assign Invalid = |(InputExc[4:2]);
// Inexact answer due to rounding, overflow or underflow
assign Inexact = (R | S) | Overflow | Underflow;
// Put pieces together to form final result
assign P = Z;
// Collect exception flags
assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact};
endmodule
| 7.326377 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round bit
input S; // Sticky bit
input G;
input Sa; // A's sign bit
input Sb; // B's sign bit
input Ctrl; // Control bit (operation)
input MaxAB;
// Output ports
output [`DWIDTH-1:0] Z; // Final result
output EOF;
// Internal signals
wire [ `MANTISSA:0] RoundUpM; // Rounded up sum with room for overflow
wire [`MANTISSA-1:0] RoundM; // The final rounded sum
wire [ `EXPONENT:0] RoundE; // Rounded exponent (note extra bit due to poential overflow )
wire RoundUp; // Flag indicating that the sum should be rounded up
wire FSgn;
wire ExpAdd; // May have to add 1 to compensate for overflow
wire RoundOF; // Rounding overflow
// The cases where we need to round upwards (= adding one) in Round to nearest, tie to even
assign RoundUp = (G & ((R | S) | NormM[0]));
// Note that in the other cases (rounding down), the sum is already 'rounded'
assign RoundUpM = (NormM + 1); // The sum, rounded up by 1
assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM); // Compute final mantissa
assign RoundOF = RoundUp & RoundUpM[`MANTISSA]; // Check for overflow when rounding up
// Calculate post-rounding exponent
assign ExpAdd = (RoundOF ? 1'b1 : 1'b0); // Add 1 to exponent to compensate for overflow
assign RoundE = ZeroSum ? 5'b00000 : (NormE + ExpAdd); // Final exponent
// If zero, need to determine sign according to rounding
assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ;
// Assign final result
assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]};
// Indicate exponent overflow
assign EOF = RoundE[`EXPONENT];
endmodule
| 7.753919 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0] NormM; // Normalized mantissa
output [`EXPONENT:0] NormE; // Adjusted exponent
output ZeroSum; // Zero flag
output NegE; // Flag indicating negative exponent
output R; // Round bit
output S; // Final sticky bit
output FG;
// Internal signals
wire MSBShift; // Flag indicating that a second shift is needed
wire [`EXPONENT:0] ExpOF; // MSB set in sum indicates overflow
wire [`EXPONENT:0] ExpOK; // MSB not set, no adjustment
// Calculate normalized exponent and mantissa, check for all-zero sum
assign MSBShift = PSSum[`DWIDTH]; // Check MSB in unnormalized sum
assign ZeroSum = ~|PSSum; // Check for all zero sum
assign ExpOK = CExp - Shift; // Adjust exponent for new normalized mantissa
assign NegE = ExpOK[`EXPONENT]; // Check for exponent overflow
assign ExpOF = CExp - Shift + 1'b1; // If MSB set, add one to exponent(x2)
assign NormE = MSBShift ? ExpOF : ExpOK; // Check for exponent overflow
assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1]; // The new, normalized mantissa
// Also need to compute sticky and round bits for the rounding stage
assign FG = PSSum[`EXPONENT];
assign R = PSSum[`EXPONENT-1];
assign S = |PSSum[`EXPONENT-2:0];
endmodule
| 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1:0] Stage1;
reg [ `DWIDTH:0] Lvl3;
wire [2*`DWIDTH+1:0] Stage2;
integer i; // Loop variable
assign Stage1 = {MminP, MminP};
always @(*) begin // Rotate {0 | 4 | 8 | 12} bits
case (Shift[3:2])
// Rotate by 0
2'b00: //Lvl2 <= Stage1[`DWIDTH:0];
begin
Lvl2 = Stage1[`DWIDTH:0];
end
// Rotate by 4
2'b01: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-4]; end Lvl2[3:0] <= 0; end
begin
Lvl2[`DWIDTH:(`DWIDTH-4)] = Stage1[3:0];
Lvl2[`DWIDTH-4-1:0] = Stage1[`DWIDTH-4];
end
// Rotate by 8
2'b10: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-8]; end Lvl2[7:0] <= 0; end
begin
Lvl2[`DWIDTH:(`DWIDTH-8)] = Stage1[3:0];
Lvl2[`DWIDTH-8-1:0] = Stage1[`DWIDTH-8];
end
// Rotate by 12
2'b11: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-12]; end Lvl2[11:0] <= 0; end
begin
Lvl2[`DWIDTH:(`DWIDTH-12)] = Stage1[3:0];
Lvl2[`DWIDTH-12-1:0] = Stage1[`DWIDTH-12];
end
endcase
end
assign Stage2 = {Lvl2, Lvl2};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: //Lvl3 <= Stage2[`DWIDTH:0];
begin
Lvl3 = Stage2[`DWIDTH:0];
end
// Rotate by 1
2'b01: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-1]; end Lvl3[0] <= 0; end
begin
Lvl3[`DWIDTH:(`DWIDTH-1)] = Stage2[3:0];
Lvl3[`DWIDTH-1-1:0] = Stage2[`DWIDTH-1];
end
// Rotate by 2
2'b10: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-2]; end Lvl3[1:0] <= 0; end
begin
Lvl3[`DWIDTH:(`DWIDTH-2)] = Stage2[3:0];
Lvl3[`DWIDTH-2-1:0] = Stage2[`DWIDTH-2];
end
// Rotate by 3
2'b11: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-3]; end Lvl3[2:0] <= 0; end
begin
Lvl3[`DWIDTH:(`DWIDTH-3)] = Stage2[3:0];
Lvl3[`DWIDTH-3-1:0] = Stage2[`DWIDTH-3];
end
endcase
end
// Assign outputs
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
// Determine normalization shift amount by finding leading nought
assign Shift = (
Sum[16] ? 5'b00000 :
Sum[15] ? 5'b00001 :
Sum[14] ? 5'b00010 :
Sum[13] ? 5'b00011 :
Sum[12] ? 5'b00100 :
Sum[11] ? 5'b00101 :
Sum[10] ? 5'b00110 :
Sum[9] ? 5'b00111 :
Sum[8] ? 5'b01000 :
Sum[7] ? 5'b01001 :
Sum[6] ? 5'b01010 :
Sum[5] ? 5'b01011 :
Sum[4] ? 5'b01100 : 5'b01101
// Sum[19] ? 5'b01101 :
// Sum[18] ? 5'b01110 :
// Sum[17] ? 5'b01111 :
// Sum[16] ? 5'b10000 :
// Sum[15] ? 5'b10001 :
// Sum[14] ? 5'b10010 :
// Sum[13] ? 5'b10011 :
// Sum[12] ? 5'b10100 :
// Sum[11] ? 5'b10101 :
// Sum[10] ? 5'b10110 :
// Sum[9] ? 5'b10111 :
// Sum[8] ? 5'b11000 :
// Sum[7] ? 5'b11001 : 5'b11010
);
reg [`DWIDTH:0] Lvl1;
always @(*) begin
// Rotate by 16?
Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum;
end
// Assign outputs
assign Mmin = Lvl1; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of smaller number
input MaxAB; // Indicates the larger number (0/A, 1/B)
input OpMode; // Operation to be performed (0/Add, 1/Sub)
// Output ports
output [`DWIDTH:0] Sum; // The result of the operation
output PSgn; // The sign for the result
output Opr; // The effective (performed) operation
assign Opr = (OpMode ^ Sa ^ Sb); // Resolve sign to determine operation
// Perform effective operation
assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, 5'b00000} - {Mmin, 5'b00000}) : ({1'b1, Mmax, 5'b00000} + {Mmin, 5'b00000}) ;
// Assign result sign
assign PSgn = (MaxAB ? Sb : Sa);
endmodule
| 6.632792 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANTISSA:0] Lvl3;
wire [2*`MANTISSA+1:0] Stage2;
integer j; // Loop variable
assign Stage2 = {11'b0, MminP};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[`MANTISSA:0];
// Rotate by 1
2'b01: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+1];
end /*Lvl3[`MANTISSA] <= 0; */
end
// Rotate by 2
2'b10: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+2];
end /*Lvl3[`MANTISSA:`MANTISSA-1] <= 0;*/
end
// Rotate by 3
2'b11: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+3];
end /*Lvl3[`MANTISSA:`MANTISSA-2] <= 0;*/
end
endcase
end
// Assign output
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.969233 |
module FPAddSub_AlignShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [2:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal signals
reg [ `MANTISSA:0] Lvl1;
reg [ `MANTISSA:0] Lvl2;
wire [2*`MANTISSA+1:0] Stage1;
integer i; // Loop variable
always @(*) begin
// Rotate by 16?
//Lvl1 <= Shift[2] ? {17'b00000000000000001, MminP[22:16]} : {1'b1, MminP};
Lvl1 <= Shift[2] ? {11'b0000000000} : {1'b1, MminP};
end
assign Stage1 = {11'b0, Lvl1};
always @(*) begin // Rotate {0 | 4 | 8 | 12} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl2 <= Stage1[`MANTISSA:0];
// Rotate by 4
2'b01: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+4];
end /*Lvl2[`MANTISSA:`MANTISSA-3] <= 0;*/
end
// Rotate by 8
2'b10: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+8];
end /*Lvl2[`MANTISSA:`MANTISSA-7] <= 0;*/
end
// Rotate by 12
2'b11: Lvl2[`MANTISSA:0] <= 0;
//2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[`MANTISSA:`MANTISSA-12] <= 0; end
endcase
end
// Assign output to next shift stage
assign Mmin = Lvl2;
endmodule
| 6.969233 |
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-2:0] B; // Input B, a 32-bit floating point number
input [9:0] ShiftDet;
// Output ports
output [`EXPONENT-1:0] CExp; // Common Exponent
output MaxAB; // Incidates larger of A and B (0/A, 1/B)
output [4:0] Shift; // Number of steps to smaller mantissa shift right
output [`MANTISSA-1:0] Mmin; // Smaller mantissa
output [`MANTISSA-1:0] Mmax; // Larger mantissa
// Internal signals
//wire BOF ; // Check for shifting overflow if B is larger
//wire AOF ; // Check for shifting overflow if A is larger
assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]);
//assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits
//assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits
// Determine final shift value
//assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ;
assign Shift = MaxAB ? ShiftDet[9:5] : ShiftDet[4:0];
// Take out smaller mantissa and append shift space
assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0];
// Take out larger mantissa
assign Mmax = MaxAB ? B[`MANTISSA-1:0] : A[`MANTISSA-1:0];
// Common exponent
assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]);
endmodule
| 6.969233 |
module FPAddSub_PrealignModule (
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] B; // Input B, a 32-bit floating point number
input operation;
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [9:0] ShiftDet;
output [4:0] InputExc; // Input numbers are exceptions
output [`DWIDTH-2:0] Aout;
output [`DWIDTH-2:0] Bout;
output Opout;
// Internal signals // If signal is high...
wire ANaN; // A is a NaN (Not-a-Number)
wire BNaN; // B is a NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [`EXPONENT-1:0] DAB; // ExpA - ExpB
wire [`EXPONENT-1:0] DBA; // ExpB - ExpA
assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
// Put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign DAB = (A[30:23] - B[30:23]) ;
//assign DBA = (B[30:23] - A[30:23]) ;
assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1);
assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1);
assign Sa = A[`DWIDTH-1]; // A's sign bit
assign Sb = B[`DWIDTH-1]; // B's sign bit
assign ShiftDet = {DBA[4:0], DAB[4:0]}; // Shift data
assign Opout = operation;
assign Aout = A[`DWIDTH-2:0];
assign Bout = B[`DWIDTH-2:0];
endmodule
| 7.069212 |
module td_fused_top_tdf11_l2_filters (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd65536;
parameter AddressWidth = 32'd16;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_tdf11_l2_filters_ram td_fused_top_tdf11_l2_filters_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_tdf11_l2_filters_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 16;
parameter MEM_SIZE = 65536;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_tdf11_l2_filters_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 16;
parameter MEM_SIZE = 65536;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #(
parameter ID = 20,
NUM_STAGE = 4,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 15:0] a_tdata;
wire b_tvalid;
wire [ 15:0] b_tdata;
wire r_tvalid;
wire [ 15:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg ce_r;
wire [dout_WIDTH-1:0] dout_i;
reg [dout_WIDTH-1:0] dout_r;
//------------------------Instantiation------------------
td_fused_top_ap_hmul_2_max_dsp_16 td_fused_top_ap_hmul_2_max_dsp_16_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce_r;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout_i = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @(posedge clk) begin
ce_r <= ce;
end
always @(posedge clk) begin
if (ce_r) begin
dout_r <= dout_i;
end
end
assign dout = ce_r ? dout_i : dout_r;
endmodule
| 6.827284 |
module td_fused_top_ap_hmul_2_max_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wire [15:0] m_axis_result_tdata
);
reg [15:0] a_reg, b_reg, res, res_reg;
always @(posedge aclk) begin
if (aclken) begin
a_reg <= s_axis_a_tdata;
b_reg <= s_axis_b_tdata;
res_reg <= res;
end
end
`ifdef complex_dsp
multiply_fp u_mult_fp (
.a (a_reg),
.b (b_reg),
.out(res)
);
`else
FPMult_16 u_FPMult (
.clk(),
.rst(1'b0),
.a(a_reg),
.b(b_reg),
.result(res),
.flags()
);
`endif
assign m_axis_result_tdata = res_reg;
endmodule
| 6.827284 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
input [`EXPONENT:0] RoundEP; // Normalized exponent + 1
input Sp; // Product sign
input GRS;
input [4:0] InputExc;
// Output Ports
output [`DWIDTH-1:0] Z; // Final product
output [4:0] Flags;
// Internal Signals
wire [`EXPONENT:0] FinalE; // Rounded exponent
wire [`MANTISSA:0] FinalM;
wire [`MANTISSA:0] PreShiftM;
assign PreShiftM = GRS ? RoundMP : RoundM; // Round up if R and (G or S)
// Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow)
assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]);
assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done
assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]}; // Putting the pieces together
assign Flags = InputExc[4:0];
endmodule
| 7.570448 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
output [`MANTISSA:0] RoundM;
output [`MANTISSA:0] RoundMP;
assign RoundE = NormE - 15;
assign RoundEP = NormE - 14;
assign RoundM = NormM;
assign RoundMP = NormM;
endmodule
| 7.947312 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [`EXPONENT-1:0] Ea; // A's exponent
output [`EXPONENT-1:0] Eb; // B's exponent
output [2*`MANTISSA+1:0] Mp; // Mantissa product
output [4:0] InputExc; // Input numbers are exceptions
// Internal signals // If signal is high...
wire ANaN; // A is a signalling NaN
wire BNaN; // B is a signalling NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [`MANTISSA-1:0] Ma;
wire [`MANTISSA-1:0] Mb;
assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
// Check for any exceptions and put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ;
// Take input numbers apart
assign Sa = a[`DWIDTH-1]; // A's sign
assign Sb = b[`DWIDTH-1]; // B's sign
assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception
assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception
// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB];
// assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB];
//assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ;
assign Mp = ({1'b1, a[`MANTISSA-1:0]} * {1'b1, b[`MANTISSA-1:0]});
//We multiply part of the mantissa here
//Full mantissa of A
//Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B
// wire [`ACTUAL_MANTISSA-1:0] inp_A;
// wire [`ACTUAL_MANTISSA-1:0] inp_B;
// assign inp_A = {1'b1, Ma};
// assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]};
// DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp));
endmodule
| 7.427166 |
module td_fused_top_mux_42_16_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [15 : 0] din0,
input [15 : 0] din1,
input [15 : 0] din2,
input [15 : 0] din3,
input [ 1 : 0] din4,
output [15 : 0] dout
);
// puts internal signals
wire [ 1 : 0] sel;
// level 1 signals
wire [15 : 0] mux_1_0;
wire [15 : 0] mux_1_1;
// level 2 signals
wire [15 : 0] mux_2_0;
assign sel = din4;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 6.827284 |
module td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #(
parameter ID = 31,
NUM_STAGE = 5,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 15:0] a_tdata;
wire b_tvalid;
wire [ 15:0] b_tdata;
wire r_tvalid;
wire [ 15:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg ce_r;
wire [dout_WIDTH-1:0] dout_i;
reg [dout_WIDTH-1:0] dout_r;
//------------------------Instantiation------------------
td_fused_top_ap_hmul_3_max_dsp_16 td_fused_top_ap_hmul_3_max_dsp_16_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce_r;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout_i = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @(posedge clk) begin
ce_r <= ce;
end
always @(posedge clk) begin
if (ce_r) begin
dout_r <= dout_i;
end
end
assign dout = ce_r ? dout_i : dout_r;
endmodule
| 6.827284 |
module td_fused_top_ap_hmul_3_max_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wire [15:0] m_axis_result_tdata
);
reg [15:0] a_reg, b_reg, res, res_reg;
always @(posedge aclk) begin
if (aclken) begin
a_reg <= s_axis_a_tdata;
b_reg <= s_axis_b_tdata;
res_reg <= res;
end
end
`ifdef complex_dsp
multiply_fp u_mult_fp (
.a (a_reg),
.b (b_reg),
.out(res)
);
`else
FPMult_16 u_FPMult (
.clk(),
.rst(1'b0),
.a(a_reg),
.b(b_reg),
.result(res),
.flags()
);
`endif
assign m_axis_result_tdata = res_reg;
endmodule
| 6.827284 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
input [`EXPONENT:0] RoundEP; // Normalized exponent + 1
input Sp; // Product sign
input GRS;
input [4:0] InputExc;
// Output Ports
output [`DWIDTH-1:0] Z; // Final product
output [4:0] Flags;
// Internal Signals
wire [`EXPONENT:0] FinalE; // Rounded exponent
wire [`MANTISSA:0] FinalM;
wire [`MANTISSA:0] PreShiftM;
assign PreShiftM = GRS ? RoundMP : RoundM; // Round up if R and (G or S)
// Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow)
assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]);
assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done
assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]}; // Putting the pieces together
assign Flags = InputExc[4:0];
endmodule
| 7.570448 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
output [`MANTISSA:0] RoundM;
output [`MANTISSA:0] RoundMP;
assign RoundE = NormE - 15;
assign RoundEP = NormE - 14;
assign RoundM = NormM;
assign RoundMP = NormM;
endmodule
| 7.947312 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [`EXPONENT-1:0] Ea; // A's exponent
output [`EXPONENT-1:0] Eb; // B's exponent
output [2*`MANTISSA+1:0] Mp; // Mantissa product
output [4:0] InputExc; // Input numbers are exceptions
// Internal signals // If signal is high...
wire ANaN; // A is a signalling NaN
wire BNaN; // B is a signalling NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [`MANTISSA-1:0] Ma;
wire [`MANTISSA-1:0] Mb;
assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
// Check for any exceptions and put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ;
// Take input numbers apart
assign Sa = a[`DWIDTH-1]; // A's sign
assign Sb = b[`DWIDTH-1]; // B's sign
assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception
assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception
// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB];
// assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB];
//assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ;
assign Mp = ({1'b1, a[`MANTISSA-1:0]} * {1'b1, b[`MANTISSA-1:0]});
//We multiply part of the mantissa here
//Full mantissa of A
//Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B
// wire [`ACTUAL_MANTISSA-1:0] inp_A;
// wire [`ACTUAL_MANTISSA-1:0] inp_B;
// assign inp_A = {1'b1, Ma};
// assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]};
// DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp));
endmodule
| 7.427166 |
module td_fused_top_mux_816_16_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
din8_WIDTH = 32,
dout_WIDTH = 32
) (
input [15 : 0] din0,
input [15 : 0] din1,
input [15 : 0] din2,
input [15 : 0] din3,
input [15 : 0] din4,
input [15 : 0] din5,
input [15 : 0] din6,
input [15 : 0] din7,
input [15 : 0] din8,
output [15 : 0] dout
);
// puts internal signals
wire [15 : 0] sel;
// level 1 signals
wire [15 : 0] mux_1_0;
wire [15 : 0] mux_1_1;
wire [15 : 0] mux_1_2;
wire [15 : 0] mux_1_3;
// level 2 signals
wire [15 : 0] mux_2_0;
wire [15 : 0] mux_2_1;
// level 3 signals
wire [15 : 0] mux_3_0;
// level 4 signals
wire [15 : 0] mux_4_0;
// level 5 signals
wire [15 : 0] mux_5_0;
// level 6 signals
wire [15 : 0] mux_6_0;
// level 7 signals
wire [15 : 0] mux_7_0;
// level 8 signals
wire [15 : 0] mux_8_0;
// level 9 signals
wire [15 : 0] mux_9_0;
// level 10 signals
wire [15 : 0] mux_10_0;
// level 11 signals
wire [15 : 0] mux_11_0;
// level 12 signals
wire [15 : 0] mux_12_0;
// level 13 signals
wire [15 : 0] mux_13_0;
// level 14 signals
wire [15 : 0] mux_14_0;
// level 15 signals
wire [15 : 0] mux_15_0;
// level 16 signals
wire [15 : 0] mux_16_0;
assign sel = din8;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
assign mux_1_2 = (sel[0] == 0) ? din4 : din5;
assign mux_1_3 = (sel[0] == 0) ? din6 : din7;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
assign mux_2_1 = (sel[1] == 0) ? mux_1_2 : mux_1_3;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0) ? mux_2_0 : mux_2_1;
// Generate level 4 logic
assign mux_4_0 = mux_3_0;
// Generate level 5 logic
assign mux_5_0 = mux_4_0;
// Generate level 6 logic
assign mux_6_0 = mux_5_0;
// Generate level 7 logic
assign mux_7_0 = mux_6_0;
// Generate level 8 logic
assign mux_8_0 = mux_7_0;
// Generate level 9 logic
assign mux_9_0 = mux_8_0;
// Generate level 10 logic
assign mux_10_0 = mux_9_0;
// Generate level 11 logic
assign mux_11_0 = mux_10_0;
// Generate level 12 logic
assign mux_12_0 = mux_11_0;
// Generate level 13 logic
assign mux_13_0 = mux_12_0;
// Generate level 14 logic
assign mux_14_0 = mux_13_0;
// Generate level 15 logic
assign mux_15_0 = mux_14_0;
// Generate level 16 logic
assign mux_16_0 = mux_15_0;
// output logic
assign dout = mux_16_0;
endmodule
| 6.827284 |
module td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2 (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2_ram td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
//initial begin
// $readmemh("./td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2_ram.dat", ram);
//end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_hadd_16ns_16ns_16_8_full_dsp_1 #(
parameter ID = 45,
NUM_STAGE = 8,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 15:0] a_tdata;
wire b_tvalid;
wire [ 15:0] b_tdata;
wire r_tvalid;
wire [ 15:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg ce_r;
wire [dout_WIDTH-1:0] dout_i;
reg [dout_WIDTH-1:0] dout_r;
//------------------------Instantiation------------------
td_fused_top_ap_hadd_6_full_dsp_16 td_fused_top_ap_hadd_6_full_dsp_16_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce_r;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout_i = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @(posedge clk) begin
ce_r <= ce;
end
always @(posedge clk) begin
if (ce_r) begin
dout_r <= dout_i;
end
end
assign dout = ce_r ? dout_i : dout_r;
endmodule
| 6.827284 |
module td_fused_top_ap_hadd_6_full_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wire [15:0] m_axis_result_tdata
);
reg [15:0] a_reg, b_reg, res, res_reg;
always @(posedge aclk) begin
if (aclken) begin
a_reg <= s_axis_a_tdata;
b_reg <= s_axis_b_tdata;
res_reg <= res;
end
end
`ifdef complex_dsp
adder_fp u_add_fp (
.a (a_reg),
.b (b_reg),
.out(res)
);
`else
FPAddSub u_FPAddSub (
.clk(),
.rst(1'b0),
.a(a_reg),
.b(b_reg),
.operation(1'b0),
.result(res),
.flags()
);
`endif
assign m_axis_result_tdata = res_reg;
endmodule
| 6.827284 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
input EOF;
// Output ports
output [`DWIDTH-1:0] P; // Final result
output [4:0] Flags; // Exception flags
// Internal signals
wire Overflow; // Overflow flag
wire Underflow; // Underflow flag
wire DivideByZero; // Divide-by-Zero flag (always 0 in Add/Sub)
wire Invalid; // Invalid inputs or result
wire Inexact; // Result is inexact because of rounding
// Exception flags
// Result is too big to be represented
assign Overflow = EOF | InputExc[1] | InputExc[0];
// Result is too small to be represented
assign Underflow = NegE & (R | S);
// Infinite result computed exactly from finite operands
assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0];
// Invalid inputs or operation
assign Invalid = |(InputExc[4:2]);
// Inexact answer due to rounding, overflow or underflow
assign Inexact = (R | S) | Overflow | Underflow;
// Put pieces together to form final result
assign P = Z;
// Collect exception flags
assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact};
endmodule
| 7.326377 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round bit
input S; // Sticky bit
input G;
input Sa; // A's sign bit
input Sb; // B's sign bit
input Ctrl; // Control bit (operation)
input MaxAB;
// Output ports
output [`DWIDTH-1:0] Z; // Final result
output EOF;
// Internal signals
wire [ `MANTISSA:0] RoundUpM; // Rounded up sum with room for overflow
wire [`MANTISSA-1:0] RoundM; // The final rounded sum
wire [ `EXPONENT:0] RoundE; // Rounded exponent (note extra bit due to poential overflow )
wire RoundUp; // Flag indicating that the sum should be rounded up
wire FSgn;
wire ExpAdd; // May have to add 1 to compensate for overflow
wire RoundOF; // Rounding overflow
// The cases where we need to round upwards (= adding one) in Round to nearest, tie to even
assign RoundUp = (G & ((R | S) | NormM[0]));
// Note that in the other cases (rounding down), the sum is already 'rounded'
assign RoundUpM = (NormM + 1); // The sum, rounded up by 1
assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM); // Compute final mantissa
assign RoundOF = RoundUp & RoundUpM[`MANTISSA]; // Check for overflow when rounding up
// Calculate post-rounding exponent
assign ExpAdd = (RoundOF ? 1'b1 : 1'b0); // Add 1 to exponent to compensate for overflow
assign RoundE = ZeroSum ? 5'b00000 : (NormE + ExpAdd); // Final exponent
// If zero, need to determine sign according to rounding
assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ;
// Assign final result
assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]};
// Indicate exponent overflow
assign EOF = RoundE[`EXPONENT];
endmodule
| 7.753919 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0] NormM; // Normalized mantissa
output [`EXPONENT:0] NormE; // Adjusted exponent
output ZeroSum; // Zero flag
output NegE; // Flag indicating negative exponent
output R; // Round bit
output S; // Final sticky bit
output FG;
// Internal signals
wire MSBShift; // Flag indicating that a second shift is needed
wire [`EXPONENT:0] ExpOF; // MSB set in sum indicates overflow
wire [`EXPONENT:0] ExpOK; // MSB not set, no adjustment
// Calculate normalized exponent and mantissa, check for all-zero sum
assign MSBShift = PSSum[`DWIDTH]; // Check MSB in unnormalized sum
assign ZeroSum = ~|PSSum; // Check for all zero sum
assign ExpOK = CExp - Shift; // Adjust exponent for new normalized mantissa
assign NegE = ExpOK[`EXPONENT]; // Check for exponent overflow
assign ExpOF = CExp - Shift + 1'b1; // If MSB set, add one to exponent(x2)
assign NormE = MSBShift ? ExpOF : ExpOK; // Check for exponent overflow
assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1]; // The new, normalized mantissa
// Also need to compute sticky and round bits for the rounding stage
assign FG = PSSum[`EXPONENT];
assign R = PSSum[`EXPONENT-1];
assign S = |PSSum[`EXPONENT-2:0];
endmodule
| 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1:0] Stage1;
reg [ `DWIDTH:0] Lvl3;
wire [2*`DWIDTH+1:0] Stage2;
integer i; // Loop variable
assign Stage1 = {MminP, MminP};
always @(*) begin // Rotate {0 | 4 | 8 | 12} bits
case (Shift[3:2])
// Rotate by 0
2'b00: //Lvl2 <= Stage1[`DWIDTH:0];
begin
Lvl2 = Stage1[`DWIDTH:0];
end
// Rotate by 4
2'b01: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-4]; end Lvl2[3:0] <= 0; end
begin
Lvl2[`DWIDTH:(`DWIDTH-4)] = Stage1[3:0];
Lvl2[`DWIDTH-4-1:0] = Stage1[`DWIDTH-4];
end
// Rotate by 8
2'b10: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-8]; end Lvl2[7:0] <= 0; end
begin
Lvl2[`DWIDTH:(`DWIDTH-8)] = Stage1[3:0];
Lvl2[`DWIDTH-8-1:0] = Stage1[`DWIDTH-8];
end
// Rotate by 12
2'b11: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-12]; end Lvl2[11:0] <= 0; end
begin
Lvl2[`DWIDTH:(`DWIDTH-12)] = Stage1[3:0];
Lvl2[`DWIDTH-12-1:0] = Stage1[`DWIDTH-12];
end
endcase
end
assign Stage2 = {Lvl2, Lvl2};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: //Lvl3 <= Stage2[`DWIDTH:0];
begin
Lvl3 = Stage2[`DWIDTH:0];
end
// Rotate by 1
2'b01: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-1]; end Lvl3[0] <= 0; end
begin
Lvl3[`DWIDTH:(`DWIDTH-1)] = Stage2[3:0];
Lvl3[`DWIDTH-1-1:0] = Stage2[`DWIDTH-1];
end
// Rotate by 2
2'b10: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-2]; end Lvl3[1:0] <= 0; end
begin
Lvl3[`DWIDTH:(`DWIDTH-2)] = Stage2[3:0];
Lvl3[`DWIDTH-2-1:0] = Stage2[`DWIDTH-2];
end
// Rotate by 3
2'b11: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-3]; end Lvl3[2:0] <= 0; end
begin
Lvl3[`DWIDTH:(`DWIDTH-3)] = Stage2[3:0];
Lvl3[`DWIDTH-3-1:0] = Stage2[`DWIDTH-3];
end
endcase
end
// Assign outputs
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
// Determine normalization shift amount by finding leading nought
assign Shift = (
Sum[16] ? 5'b00000 :
Sum[15] ? 5'b00001 :
Sum[14] ? 5'b00010 :
Sum[13] ? 5'b00011 :
Sum[12] ? 5'b00100 :
Sum[11] ? 5'b00101 :
Sum[10] ? 5'b00110 :
Sum[9] ? 5'b00111 :
Sum[8] ? 5'b01000 :
Sum[7] ? 5'b01001 :
Sum[6] ? 5'b01010 :
Sum[5] ? 5'b01011 :
Sum[4] ? 5'b01100 : 5'b01101
// Sum[19] ? 5'b01101 :
// Sum[18] ? 5'b01110 :
// Sum[17] ? 5'b01111 :
// Sum[16] ? 5'b10000 :
// Sum[15] ? 5'b10001 :
// Sum[14] ? 5'b10010 :
// Sum[13] ? 5'b10011 :
// Sum[12] ? 5'b10100 :
// Sum[11] ? 5'b10101 :
// Sum[10] ? 5'b10110 :
// Sum[9] ? 5'b10111 :
// Sum[8] ? 5'b11000 :
// Sum[7] ? 5'b11001 : 5'b11010
);
reg [`DWIDTH:0] Lvl1;
always @(*) begin
// Rotate by 16?
Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum;
end
// Assign outputs
assign Mmin = Lvl1; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of smaller number
input MaxAB; // Indicates the larger number (0/A, 1/B)
input OpMode; // Operation to be performed (0/Add, 1/Sub)
// Output ports
output [`DWIDTH:0] Sum; // The result of the operation
output PSgn; // The sign for the result
output Opr; // The effective (performed) operation
assign Opr = (OpMode ^ Sa ^ Sb); // Resolve sign to determine operation
// Perform effective operation
assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, 5'b00000} - {Mmin, 5'b00000}) : ({1'b1, Mmax, 5'b00000} + {Mmin, 5'b00000}) ;
// Assign result sign
assign PSgn = (MaxAB ? Sb : Sa);
endmodule
| 6.632792 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANTISSA:0] Lvl3;
wire [2*`MANTISSA+1:0] Stage2;
integer j; // Loop variable
assign Stage2 = {11'b0, MminP};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[`MANTISSA:0];
// Rotate by 1
2'b01: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+1];
end /*Lvl3[`MANTISSA] <= 0; */
end
// Rotate by 2
2'b10: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+2];
end /*Lvl3[`MANTISSA:`MANTISSA-1] <= 0;*/
end
// Rotate by 3
2'b11: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+3];
end /*Lvl3[`MANTISSA:`MANTISSA-2] <= 0;*/
end
endcase
end
// Assign output
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.969233 |
module FPAddSub_AlignShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [2:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal signals
reg [ `MANTISSA:0] Lvl1;
reg [ `MANTISSA:0] Lvl2;
wire [2*`MANTISSA+1:0] Stage1;
integer i; // Loop variable
always @(*) begin
// Rotate by 16?
//Lvl1 <= Shift[2] ? {17'b00000000000000001, MminP[22:16]} : {1'b1, MminP};
Lvl1 <= Shift[2] ? {11'b0000000000} : {1'b1, MminP};
end
assign Stage1 = {11'b0, Lvl1};
always @(*) begin // Rotate {0 | 4 | 8 | 12} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl2 <= Stage1[`MANTISSA:0];
// Rotate by 4
2'b01: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+4];
end /*Lvl2[`MANTISSA:`MANTISSA-3] <= 0;*/
end
// Rotate by 8
2'b10: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+8];
end /*Lvl2[`MANTISSA:`MANTISSA-7] <= 0;*/
end
// Rotate by 12
2'b11: Lvl2[`MANTISSA:0] <= 0;
//2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[`MANTISSA:`MANTISSA-12] <= 0; end
endcase
end
// Assign output to next shift stage
assign Mmin = Lvl2;
endmodule
| 6.969233 |
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-2:0] B; // Input B, a 32-bit floating point number
input [9:0] ShiftDet;
// Output ports
output [`EXPONENT-1:0] CExp; // Common Exponent
output MaxAB; // Incidates larger of A and B (0/A, 1/B)
output [4:0] Shift; // Number of steps to smaller mantissa shift right
output [`MANTISSA-1:0] Mmin; // Smaller mantissa
output [`MANTISSA-1:0] Mmax; // Larger mantissa
// Internal signals
//wire BOF ; // Check for shifting overflow if B is larger
//wire AOF ; // Check for shifting overflow if A is larger
assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]);
//assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits
//assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits
// Determine final shift value
//assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ;
assign Shift = MaxAB ? ShiftDet[9:5] : ShiftDet[4:0];
// Take out smaller mantissa and append shift space
assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0];
// Take out larger mantissa
assign Mmax = MaxAB ? B[`MANTISSA-1:0] : A[`MANTISSA-1:0];
// Common exponent
assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]);
endmodule
| 6.969233 |
module FPAddSub_PrealignModule (
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] B; // Input B, a 32-bit floating point number
input operation;
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [9:0] ShiftDet;
output [4:0] InputExc; // Input numbers are exceptions
output [`DWIDTH-2:0] Aout;
output [`DWIDTH-2:0] Bout;
output Opout;
// Internal signals // If signal is high...
wire ANaN; // A is a NaN (Not-a-Number)
wire BNaN; // B is a NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [`EXPONENT-1:0] DAB; // ExpA - ExpB
wire [`EXPONENT-1:0] DBA; // ExpB - ExpA
assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
// Put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign DAB = (A[30:23] - B[30:23]) ;
//assign DBA = (B[30:23] - A[30:23]) ;
assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1);
assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1);
assign Sa = A[`DWIDTH-1]; // A's sign bit
assign Sb = B[`DWIDTH-1]; // B's sign bit
assign ShiftDet = {DBA[4:0], DAB[4:0]}; // Shift data
assign Opout = operation;
assign Aout = A[`DWIDTH-2:0];
assign Bout = B[`DWIDTH-2:0];
endmodule
| 7.069212 |
module td_fused_top_hmul_16ns_16ns_16_5_max_dsp_1 #(
parameter ID = 31,
NUM_STAGE = 5,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 15:0] a_tdata;
wire b_tvalid;
wire [ 15:0] b_tdata;
wire r_tvalid;
wire [ 15:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg ce_r;
wire [dout_WIDTH-1:0] dout_i;
reg [dout_WIDTH-1:0] dout_r;
//------------------------Instantiation------------------
td_fused_top_ap_hmul_3_max_dsp_16 td_fused_top_ap_hmul_3_max_dsp_16_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce_r;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout_i = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @(posedge clk) begin
ce_r <= ce;
end
always @(posedge clk) begin
if (ce_r) begin
dout_r <= dout_i;
end
end
assign dout = ce_r ? dout_i : dout_r;
endmodule
| 6.827284 |
module td_fused_top_ap_hmul_3_max_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wire [15:0] m_axis_result_tdata
);
reg [15:0] a_reg, b_reg, res, res_reg;
always @(posedge aclk) begin
if (aclken) begin
a_reg <= s_axis_a_tdata;
b_reg <= s_axis_b_tdata;
res_reg <= res;
end
end
`ifdef complex_dsp
multiply_fp u_mult_fp (
.a (a_reg),
.b (b_reg),
.out(res)
);
`else
FPMult_16 u_FPMult (
.clk(),
.rst(1'b0),
.a(a_reg),
.b(b_reg),
.result(res),
.flags()
);
`endif
assign m_axis_result_tdata = res_reg;
endmodule
| 6.827284 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
input [`EXPONENT:0] RoundEP; // Normalized exponent + 1
input Sp; // Product sign
input GRS;
input [4:0] InputExc;
// Output Ports
output [`DWIDTH-1:0] Z; // Final product
output [4:0] Flags;
// Internal Signals
wire [`EXPONENT:0] FinalE; // Rounded exponent
wire [`MANTISSA:0] FinalM;
wire [`MANTISSA:0] PreShiftM;
assign PreShiftM = GRS ? RoundMP : RoundM; // Round up if R and (G or S)
// Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow)
assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]);
assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done
assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]}; // Putting the pieces together
assign Flags = InputExc[4:0];
endmodule
| 7.570448 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
output [`MANTISSA:0] RoundM;
output [`MANTISSA:0] RoundMP;
assign RoundE = NormE - 15;
assign RoundEP = NormE - 14;
assign RoundM = NormM;
assign RoundMP = NormM;
endmodule
| 7.947312 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [`EXPONENT-1:0] Ea; // A's exponent
output [`EXPONENT-1:0] Eb; // B's exponent
output [2*`MANTISSA+1:0] Mp; // Mantissa product
output [4:0] InputExc; // Input numbers are exceptions
// Internal signals // If signal is high...
wire ANaN; // A is a signalling NaN
wire BNaN; // B is a signalling NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [`MANTISSA-1:0] Ma;
wire [`MANTISSA-1:0] Mb;
assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
// Check for any exceptions and put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ;
// Take input numbers apart
assign Sa = a[`DWIDTH-1]; // A's sign
assign Sb = b[`DWIDTH-1]; // B's sign
assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception
assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception
// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB];
// assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB];
//assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ;
assign Mp = ({1'b1, a[`MANTISSA-1:0]} * {1'b1, b[`MANTISSA-1:0]});
//We multiply part of the mantissa here
//Full mantissa of A
//Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B
// wire [`ACTUAL_MANTISSA-1:0] inp_A;
// wire [`ACTUAL_MANTISSA-1:0] inp_B;
// assign inp_A = {1'b1, Ma};
// assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]};
// DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp));
endmodule
| 7.427166 |
module td_fused_top_hsub_16ns_16ns_16_7_full_dsp_1 #(
parameter ID = 113,
NUM_STAGE = 7,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 15:0] a_tdata;
wire b_tvalid;
wire [ 15:0] b_tdata;
wire r_tvalid;
wire [ 15:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg ce_r;
wire [dout_WIDTH-1:0] dout_i;
reg [dout_WIDTH-1:0] dout_r;
//------------------------Instantiation------------------
// Just use hadd instead
//td_fused_top_ap_hsub_5_full_dsp_16 td_fused_top_ap_hsub_5_full_dsp_16_u (
td_fused_top_ap_hadd_6_full_dsp_16 td_fused_top_ap_hadd_6_full_dsp_16_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce_r;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout_i = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @(posedge clk) begin
ce_r <= ce;
end
always @(posedge clk) begin
if (ce_r) begin
dout_r <= dout_i;
end
end
assign dout = ce_r ? dout_i : dout_r;
endmodule
| 6.827284 |
module td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2 (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2_ram td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
//initial begin
// $readmemh("./td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2_ram.dat", ram);
//end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #(
parameter ID = 25,
NUM_STAGE = 5,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 15:0] a_tdata;
wire b_tvalid;
wire [ 15:0] b_tdata;
wire r_tvalid;
wire [ 15:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg ce_r;
wire [dout_WIDTH-1:0] dout_i;
reg [dout_WIDTH-1:0] dout_r;
//------------------------Instantiation------------------
td_fused_top_ap_hadd_3_full_dsp_16 td_fused_top_ap_hadd_3_full_dsp_16_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce_r;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout_i = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @(posedge clk) begin
ce_r <= ce;
end
always @(posedge clk) begin
if (ce_r) begin
dout_r <= dout_i;
end
end
assign dout = ce_r ? dout_i : dout_r;
endmodule
| 6.827284 |
module td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #(
parameter ID = 20,
NUM_STAGE = 4,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 15:0] a_tdata;
wire b_tvalid;
wire [ 15:0] b_tdata;
wire r_tvalid;
wire [ 15:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg ce_r;
wire [dout_WIDTH-1:0] dout_i;
reg [dout_WIDTH-1:0] dout_r;
//------------------------Instantiation------------------
td_fused_top_ap_hmul_2_max_dsp_16 td_fused_top_ap_hmul_2_max_dsp_16_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce_r;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout_i = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @(posedge clk) begin
ce_r <= ce;
end
always @(posedge clk) begin
if (ce_r) begin
dout_r <= dout_i;
end
end
assign dout = ce_r ? dout_i : dout_r;
endmodule
| 6.827284 |
module td_fused_top_ap_hmul_2_max_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wire [15:0] m_axis_result_tdata
);
reg [15:0] a_reg, b_reg, res, res_reg;
always @(posedge aclk) begin
if (aclken) begin
a_reg <= s_axis_a_tdata;
b_reg <= s_axis_b_tdata;
res_reg <= res;
end
end
`ifdef complex_dsp
multiply_fp u_mult_fp (
.a (a_reg),
.b (b_reg),
.out(res)
);
`else
FPMult_16 u_FPMult (
.clk(),
.rst(1'b0),
.a(a_reg),
.b(b_reg),
.result(res),
.flags()
);
`endif
assign m_axis_result_tdata = res_reg;
endmodule
| 6.827284 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
input [`EXPONENT:0] RoundEP; // Normalized exponent + 1
input Sp; // Product sign
input GRS;
input [4:0] InputExc;
// Output Ports
output [`DWIDTH-1:0] Z; // Final product
output [4:0] Flags;
// Internal Signals
wire [`EXPONENT:0] FinalE; // Rounded exponent
wire [`MANTISSA:0] FinalM;
wire [`MANTISSA:0] PreShiftM;
assign PreShiftM = GRS ? RoundMP : RoundM; // Round up if R and (G or S)
// Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow)
assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]);
assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done
assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]}; // Putting the pieces together
assign Flags = InputExc[4:0];
endmodule
| 7.570448 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
output [`MANTISSA:0] RoundM;
output [`MANTISSA:0] RoundMP;
assign RoundE = NormE - 15;
assign RoundEP = NormE - 14;
assign RoundM = NormM;
assign RoundMP = NormM;
endmodule
| 7.947312 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [`EXPONENT-1:0] Ea; // A's exponent
output [`EXPONENT-1:0] Eb; // B's exponent
output [2*`MANTISSA+1:0] Mp; // Mantissa product
output [4:0] InputExc; // Input numbers are exceptions
// Internal signals // If signal is high...
wire ANaN; // A is a signalling NaN
wire BNaN; // B is a signalling NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [`MANTISSA-1:0] Ma;
wire [`MANTISSA-1:0] Mb;
assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
// Check for any exceptions and put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ;
// Take input numbers apart
assign Sa = a[`DWIDTH-1]; // A's sign
assign Sb = b[`DWIDTH-1]; // B's sign
assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception
assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception
// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB];
// assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB];
//assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ;
assign Mp = ({1'b1, a[`MANTISSA-1:0]} * {1'b1, b[`MANTISSA-1:0]});
//We multiply part of the mantissa here
//Full mantissa of A
//Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B
// wire [`ACTUAL_MANTISSA-1:0] inp_A;
// wire [`ACTUAL_MANTISSA-1:0] inp_B;
// assign inp_A = {1'b1, Ma};
// assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]};
// DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp));
endmodule
| 7.427166 |
module td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #(
parameter ID = 37,
NUM_STAGE = 5,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 15:0] a_tdata;
wire b_tvalid;
wire [ 15:0] b_tdata;
wire r_tvalid;
wire [ 15:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg ce_r;
wire [dout_WIDTH-1:0] dout_i;
reg [dout_WIDTH-1:0] dout_r;
//------------------------Instantiation------------------
// Just replace with the hadd, logic is similar enough.
//td_fused_top_ap_hsub_3_full_dsp_16 td_fused_top_ap_hsub_3_full_dsp_16_u (
td_fused_top_ap_hadd_3_full_dsp_16 td_fused_top_ap_hsub_3_full_dsp_16_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce_r;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout_i = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @(posedge clk) begin
ce_r <= ce;
end
always @(posedge clk) begin
if (ce_r) begin
dout_r <= dout_i;
end
end
assign dout = ce_r ? dout_i : dout_r;
endmodule
| 6.827284 |
module td_fused_top_ap_hadd_3_full_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wire [15:0] m_axis_result_tdata
);
reg [15:0] a_reg, b_reg, res, res_reg;
always @(posedge aclk) begin
if (aclken) begin
a_reg <= s_axis_a_tdata;
b_reg <= s_axis_b_tdata;
res_reg <= res;
end
end
`ifdef complex_dsp
adder_fp u_add_fp (
.a (a_reg),
.b (b_reg),
.out(res)
);
`else
FPAddSub u_FPAddSub (
.clk(),
.rst(1'b0),
.a(a_reg),
.b(b_reg),
.operation(1'b0),
.result(res),
.flags()
);
`endif
assign m_axis_result_tdata = res_reg;
endmodule
| 6.827284 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
input EOF;
// Output ports
output [`DWIDTH-1:0] P; // Final result
output [4:0] Flags; // Exception flags
// Internal signals
wire Overflow; // Overflow flag
wire Underflow; // Underflow flag
wire DivideByZero; // Divide-by-Zero flag (always 0 in Add/Sub)
wire Invalid; // Invalid inputs or result
wire Inexact; // Result is inexact because of rounding
// Exception flags
// Result is too big to be represented
assign Overflow = EOF | InputExc[1] | InputExc[0];
// Result is too small to be represented
assign Underflow = NegE & (R | S);
// Infinite result computed exactly from finite operands
assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0];
// Invalid inputs or operation
assign Invalid = |(InputExc[4:2]);
// Inexact answer due to rounding, overflow or underflow
assign Inexact = (R | S) | Overflow | Underflow;
// Put pieces together to form final result
assign P = Z;
// Collect exception flags
assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact};
endmodule
| 7.326377 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round bit
input S; // Sticky bit
input G;
input Sa; // A's sign bit
input Sb; // B's sign bit
input Ctrl; // Control bit (operation)
input MaxAB;
// Output ports
output [`DWIDTH-1:0] Z; // Final result
output EOF;
// Internal signals
wire [ `MANTISSA:0] RoundUpM; // Rounded up sum with room for overflow
wire [`MANTISSA-1:0] RoundM; // The final rounded sum
wire [ `EXPONENT:0] RoundE; // Rounded exponent (note extra bit due to poential overflow )
wire RoundUp; // Flag indicating that the sum should be rounded up
wire FSgn;
wire ExpAdd; // May have to add 1 to compensate for overflow
wire RoundOF; // Rounding overflow
// The cases where we need to round upwards (= adding one) in Round to nearest, tie to even
assign RoundUp = (G & ((R | S) | NormM[0]));
// Note that in the other cases (rounding down), the sum is already 'rounded'
assign RoundUpM = (NormM + 1); // The sum, rounded up by 1
assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM); // Compute final mantissa
assign RoundOF = RoundUp & RoundUpM[`MANTISSA]; // Check for overflow when rounding up
// Calculate post-rounding exponent
assign ExpAdd = (RoundOF ? 1'b1 : 1'b0); // Add 1 to exponent to compensate for overflow
assign RoundE = ZeroSum ? 5'b00000 : (NormE + ExpAdd); // Final exponent
// If zero, need to determine sign according to rounding
assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ;
// Assign final result
assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]};
// Indicate exponent overflow
assign EOF = RoundE[`EXPONENT];
endmodule
| 7.753919 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0] NormM; // Normalized mantissa
output [`EXPONENT:0] NormE; // Adjusted exponent
output ZeroSum; // Zero flag
output NegE; // Flag indicating negative exponent
output R; // Round bit
output S; // Final sticky bit
output FG;
// Internal signals
wire MSBShift; // Flag indicating that a second shift is needed
wire [`EXPONENT:0] ExpOF; // MSB set in sum indicates overflow
wire [`EXPONENT:0] ExpOK; // MSB not set, no adjustment
// Calculate normalized exponent and mantissa, check for all-zero sum
assign MSBShift = PSSum[`DWIDTH]; // Check MSB in unnormalized sum
assign ZeroSum = ~|PSSum; // Check for all zero sum
assign ExpOK = CExp - Shift; // Adjust exponent for new normalized mantissa
assign NegE = ExpOK[`EXPONENT]; // Check for exponent overflow
assign ExpOF = CExp - Shift + 1'b1; // If MSB set, add one to exponent(x2)
assign NormE = MSBShift ? ExpOF : ExpOK; // Check for exponent overflow
assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1]; // The new, normalized mantissa
// Also need to compute sticky and round bits for the rounding stage
assign FG = PSSum[`EXPONENT];
assign R = PSSum[`EXPONENT-1];
assign S = |PSSum[`EXPONENT-2:0];
endmodule
| 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1:0] Stage1;
reg [ `DWIDTH:0] Lvl3;
wire [2*`DWIDTH+1:0] Stage2;
integer i; // Loop variable
assign Stage1 = {MminP, MminP};
always @(*) begin // Rotate {0 | 4 | 8 | 12} bits
case (Shift[3:2])
// Rotate by 0
2'b00: //Lvl2 <= Stage1[`DWIDTH:0];
begin
Lvl2 = Stage1[`DWIDTH:0];
end
// Rotate by 4
2'b01: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-4]; end Lvl2[3:0] <= 0; end
begin
Lvl2[`DWIDTH:(`DWIDTH-4)] = Stage1[3:0];
Lvl2[`DWIDTH-4-1:0] = Stage1[`DWIDTH-4];
end
// Rotate by 8
2'b10: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-8]; end Lvl2[7:0] <= 0; end
begin
Lvl2[`DWIDTH:(`DWIDTH-8)] = Stage1[3:0];
Lvl2[`DWIDTH-8-1:0] = Stage1[`DWIDTH-8];
end
// Rotate by 12
2'b11: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-12]; end Lvl2[11:0] <= 0; end
begin
Lvl2[`DWIDTH:(`DWIDTH-12)] = Stage1[3:0];
Lvl2[`DWIDTH-12-1:0] = Stage1[`DWIDTH-12];
end
endcase
end
assign Stage2 = {Lvl2, Lvl2};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: //Lvl3 <= Stage2[`DWIDTH:0];
begin
Lvl3 = Stage2[`DWIDTH:0];
end
// Rotate by 1
2'b01: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-1]; end Lvl3[0] <= 0; end
begin
Lvl3[`DWIDTH:(`DWIDTH-1)] = Stage2[3:0];
Lvl3[`DWIDTH-1-1:0] = Stage2[`DWIDTH-1];
end
// Rotate by 2
2'b10: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-2]; end Lvl3[1:0] <= 0; end
begin
Lvl3[`DWIDTH:(`DWIDTH-2)] = Stage2[3:0];
Lvl3[`DWIDTH-2-1:0] = Stage2[`DWIDTH-2];
end
// Rotate by 3
2'b11: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-3]; end Lvl3[2:0] <= 0; end
begin
Lvl3[`DWIDTH:(`DWIDTH-3)] = Stage2[3:0];
Lvl3[`DWIDTH-3-1:0] = Stage2[`DWIDTH-3];
end
endcase
end
// Assign outputs
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
// Determine normalization shift amount by finding leading nought
assign Shift = (
Sum[16] ? 5'b00000 :
Sum[15] ? 5'b00001 :
Sum[14] ? 5'b00010 :
Sum[13] ? 5'b00011 :
Sum[12] ? 5'b00100 :
Sum[11] ? 5'b00101 :
Sum[10] ? 5'b00110 :
Sum[9] ? 5'b00111 :
Sum[8] ? 5'b01000 :
Sum[7] ? 5'b01001 :
Sum[6] ? 5'b01010 :
Sum[5] ? 5'b01011 :
Sum[4] ? 5'b01100 : 5'b01101
// Sum[19] ? 5'b01101 :
// Sum[18] ? 5'b01110 :
// Sum[17] ? 5'b01111 :
// Sum[16] ? 5'b10000 :
// Sum[15] ? 5'b10001 :
// Sum[14] ? 5'b10010 :
// Sum[13] ? 5'b10011 :
// Sum[12] ? 5'b10100 :
// Sum[11] ? 5'b10101 :
// Sum[10] ? 5'b10110 :
// Sum[9] ? 5'b10111 :
// Sum[8] ? 5'b11000 :
// Sum[7] ? 5'b11001 : 5'b11010
);
reg [`DWIDTH:0] Lvl1;
always @(*) begin
// Rotate by 16?
Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum;
end
// Assign outputs
assign Mmin = Lvl1; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of smaller number
input MaxAB; // Indicates the larger number (0/A, 1/B)
input OpMode; // Operation to be performed (0/Add, 1/Sub)
// Output ports
output [`DWIDTH:0] Sum; // The result of the operation
output PSgn; // The sign for the result
output Opr; // The effective (performed) operation
assign Opr = (OpMode ^ Sa ^ Sb); // Resolve sign to determine operation
// Perform effective operation
assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, 5'b00000} - {Mmin, 5'b00000}) : ({1'b1, Mmax, 5'b00000} + {Mmin, 5'b00000}) ;
// Assign result sign
assign PSgn = (MaxAB ? Sb : Sa);
endmodule
| 6.632792 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANTISSA:0] Lvl3;
wire [2*`MANTISSA+1:0] Stage2;
integer j; // Loop variable
assign Stage2 = {11'b0, MminP};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[`MANTISSA:0];
// Rotate by 1
2'b01: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+1];
end /*Lvl3[`MANTISSA] <= 0; */
end
// Rotate by 2
2'b10: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+2];
end /*Lvl3[`MANTISSA:`MANTISSA-1] <= 0;*/
end
// Rotate by 3
2'b11: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+3];
end /*Lvl3[`MANTISSA:`MANTISSA-2] <= 0;*/
end
endcase
end
// Assign output
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.969233 |
module FPAddSub_AlignShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [2:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal signals
reg [ `MANTISSA:0] Lvl1;
reg [ `MANTISSA:0] Lvl2;
wire [2*`MANTISSA+1:0] Stage1;
integer i; // Loop variable
always @(*) begin
// Rotate by 16?
//Lvl1 <= Shift[2] ? {17'b00000000000000001, MminP[22:16]} : {1'b1, MminP};
Lvl1 <= Shift[2] ? {11'b0000000000} : {1'b1, MminP};
end
assign Stage1 = {11'b0, Lvl1};
always @(*) begin // Rotate {0 | 4 | 8 | 12} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl2 <= Stage1[`MANTISSA:0];
// Rotate by 4
2'b01: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+4];
end /*Lvl2[`MANTISSA:`MANTISSA-3] <= 0;*/
end
// Rotate by 8
2'b10: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+8];
end /*Lvl2[`MANTISSA:`MANTISSA-7] <= 0;*/
end
// Rotate by 12
2'b11: Lvl2[`MANTISSA:0] <= 0;
//2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[`MANTISSA:`MANTISSA-12] <= 0; end
endcase
end
// Assign output to next shift stage
assign Mmin = Lvl2;
endmodule
| 6.969233 |
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-2:0] B; // Input B, a 32-bit floating point number
input [9:0] ShiftDet;
// Output ports
output [`EXPONENT-1:0] CExp; // Common Exponent
output MaxAB; // Incidates larger of A and B (0/A, 1/B)
output [4:0] Shift; // Number of steps to smaller mantissa shift right
output [`MANTISSA-1:0] Mmin; // Smaller mantissa
output [`MANTISSA-1:0] Mmax; // Larger mantissa
// Internal signals
//wire BOF ; // Check for shifting overflow if B is larger
//wire AOF ; // Check for shifting overflow if A is larger
assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]);
//assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits
//assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits
// Determine final shift value
//assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ;
assign Shift = MaxAB ? ShiftDet[9:5] : ShiftDet[4:0];
// Take out smaller mantissa and append shift space
assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0];
// Take out larger mantissa
assign Mmax = MaxAB ? B[`MANTISSA-1:0] : A[`MANTISSA-1:0];
// Common exponent
assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]);
endmodule
| 6.969233 |
module FPAddSub_PrealignModule (
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] B; // Input B, a 32-bit floating point number
input operation;
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [9:0] ShiftDet;
output [4:0] InputExc; // Input numbers are exceptions
output [`DWIDTH-2:0] Aout;
output [`DWIDTH-2:0] Bout;
output Opout;
// Internal signals // If signal is high...
wire ANaN; // A is a NaN (Not-a-Number)
wire BNaN; // B is a NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [`EXPONENT-1:0] DAB; // ExpA - ExpB
wire [`EXPONENT-1:0] DBA; // ExpB - ExpA
assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
// Put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign DAB = (A[30:23] - B[30:23]) ;
//assign DBA = (B[30:23] - A[30:23]) ;
assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1);
assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1);
assign Sa = A[`DWIDTH-1]; // A's sign bit
assign Sb = B[`DWIDTH-1]; // B's sign bit
assign ShiftDet = {DBA[4:0], DAB[4:0]}; // Shift data
assign Opout = operation;
assign Aout = A[`DWIDTH-2:0];
assign Bout = B[`DWIDTH-2:0];
endmodule
| 7.069212 |
module td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2 (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2_ram td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
//initial begin
// $readmemh("./td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2_ram.dat", ram);
//end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
//initial begin
// $readmemh("./td_fused_top_tdf11_l2_writeOutputs_171_running_sums_2_ram.dat", ram);
//end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2 (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2_ram td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
//initial begin
// $readmemh("./td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2_ram.dat", ram);
//end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
//initial begin
// $readmemh("./td_fused_top_tdf11_l2_writeOutputs_1_running_sums_2_ram.dat", ram);
//end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_mux_416_64_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [63 : 0] din0,
input [63 : 0] din1,
input [63 : 0] din2,
input [63 : 0] din3,
input [15 : 0] din4,
output [63 : 0] dout
);
// puts internal signals
wire [15 : 0] sel;
// level 1 signals
wire [63 : 0] mux_1_0;
wire [63 : 0] mux_1_1;
// level 2 signals
wire [63 : 0] mux_2_0;
// level 3 signals
wire [63 : 0] mux_3_0;
// level 4 signals
wire [63 : 0] mux_4_0;
// level 5 signals
wire [63 : 0] mux_5_0;
// level 6 signals
wire [63 : 0] mux_6_0;
// level 7 signals
wire [63 : 0] mux_7_0;
// level 8 signals
wire [63 : 0] mux_8_0;
// level 9 signals
wire [63 : 0] mux_9_0;
// level 10 signals
wire [63 : 0] mux_10_0;
// level 11 signals
wire [63 : 0] mux_11_0;
// level 12 signals
wire [63 : 0] mux_12_0;
// level 13 signals
wire [63 : 0] mux_13_0;
// level 14 signals
wire [63 : 0] mux_14_0;
// level 15 signals
wire [63 : 0] mux_15_0;
// level 16 signals
wire [63 : 0] mux_16_0;
assign sel = din4;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// Generate level 3 logic
assign mux_3_0 = mux_2_0;
// Generate level 4 logic
assign mux_4_0 = mux_3_0;
// Generate level 5 logic
assign mux_5_0 = mux_4_0;
// Generate level 6 logic
assign mux_6_0 = mux_5_0;
// Generate level 7 logic
assign mux_7_0 = mux_6_0;
// Generate level 8 logic
assign mux_8_0 = mux_7_0;
// Generate level 9 logic
assign mux_9_0 = mux_8_0;
// Generate level 10 logic
assign mux_10_0 = mux_9_0;
// Generate level 11 logic
assign mux_11_0 = mux_10_0;
// Generate level 12 logic
assign mux_12_0 = mux_11_0;
// Generate level 13 logic
assign mux_13_0 = mux_12_0;
// Generate level 14 logic
assign mux_14_0 = mux_13_0;
// Generate level 15 logic
assign mux_15_0 = mux_14_0;
// Generate level 16 logic
assign mux_16_0 = mux_15_0;
// output logic
assign dout = mux_16_0;
endmodule
| 6.827284 |
module td_fused_top_start_for_tdf12_readFilters78_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_start_for_tdf12_readFilters78_U0_shiftReg
U_td_fused_top_start_for_tdf12_readFilters78_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_start_for_tdf12_readFilters78_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
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