| # controller-firmware (FPGA HDL) |
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| ## Dev environment setup |
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| ### Requirements |
| - [Visual Studio Code](https://code.visualstudio.com/) |
| - [Python 3.12](https://www.python.org/downloads/release/python-3123/) |
| - [Vivado 2023.1](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2023-1.html) |
| - [Surfer](https://surfer-project.org/) (optional, used to view HDL sim trace files) |
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| ### Setup (windows/linux) |
| #### 1. Run the "setup project" task in VS Code (Terminal -> Run Task... -> setup project) |
| This will: |
| - Run subst to create a new drive leading to vivado files, this is needed to keep path lengths short (windows only) |
| - Create the python virtual environment |
| - Install required python packages |
| - Create the vivado project |
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| ## Creating new FPGA modules |
| These modules add user-configurable functionality to the controller |
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| ### Register mapping |
| All modules must include a register map object, this will: |
| - Define the module and provide any global settings the it's software driver may need |
| - Define all memory addresses available to the driver |
| - Data types, sizes, and packing if applicable for all memory |
| - Group offsets and alignement in the case of modules that are designed to handle multiple instances of something (ex: 1-32 encoders) |
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| ### Ports |
| All modules must follow the same port format and timing sequence for memory access |
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| #### View [registers2.py](python/src/registers2.py) and [example_module.py](python/src/example_module.py) for more details |
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| ## Commiting changes |
| ### Vivado (only needed for vivado project changes, *not amaranth changes*) |
| #### Run the "save vivado project" task in VS Code (Terminal -> Run Task... -> save vivado project) |
| This will save the vivado project to a .tcl file which is in the repo and can be committed |
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