Add batch 1 (YosysHQ_picorv32, alexforencich_verilog-ethernet, The-OpenROAD-Project_OpenROAD, darklife_darkriscv, corundum_corundum)
f61bac1 verified | // SPDX-License-Identifier: BSD-3-Clause | |
| // Copyright (c) 2024, The OpenROAD Authors | |
| module top ( | |
| input clk, | |
| input in, | |
| output out | |
| ); | |
| wire n1; | |
| BUF_X1 buf1 (.Z(n1)); | |
| BUF_X1 buf2 (.A(n1), .Z(out)); | |
| endmodule | |