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f61bac1 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 | // SPDX-License-Identifier: BSD-3-Clause
// Copyright (c) 2024, The OpenROAD Authors
module top (
input clk,
input in,
output out
);
wire n1;
BUF_X1 buf1 (.Z(n1));
BUF_X1 buf2 (.A(n1), .Z(out));
endmodule
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