The-OpenROAD-Project_OpenROAD/src/README.md

# OpenROAD API

OpenROAD can be run using Tcl, and Python (limited support).
The following commands are used to read and write design data.

````{eval-rst}
.. tabs::

   .. code-tab:: tcl

      read_lef [-tech] [-library] filename
      read_def filename
      write_def [-version 5.8|5.7|5.6|5.5|5.4|5.3] filename
      read_verilog filename
      write_verilog filename
      read_db filename
      write_db filename
      write_abstract_lef filename

   .. code-tab:: python
   
      # read_verilog, write_verilog and write_abstract_lef are not supported in Python.
      read_lef(db: odb.dbDatabase, path: str) -> odb.dbLib
      read_def(tech: odb.dbTech, path: str) -> odb.dbChip
      write_def(block: dbBlock, path: str, version: Optional[odb.defout.Version]) -> int
      read_db(db: odb.dbDatabase, db_path: str) -> odb.dbDatabase
      write_db(db: odb.dbDatabase, db_path: str) -> int

````


Use the Tcl `source` command to read commands from a file.

````{eval-rst}
.. tabs::

   .. code-tab:: tcl

      source [-echo] file

   .. code-tab:: py

      # Source is not supported in Python.
      # Instead run this at the start:
      openroad -python script.py
````

If an error is encountered in a command while reading the command file,
then the error is printed and no more commands are read from the file. If
`file_continue_on_error` is `1` then OpenROAD will continue reading commands
after the error.

If `exit_on_error` is `1` then OpenROAD will exit when it encounters an error.

OpenROAD can be used to make a OpenDB database from LEF/DEF, or Verilog
(flat or hierarchical). Once the database is made it can be saved as a file
with the `write_db` command. OpenROAD can then read the database with the
`read_db` command without reading LEF/DEF or Verilog.

The `read_lef` and `read_def` commands can be used to build an OpenDB database
as shown below. The `read_lef -tech` flag reads the technology portion of a
LEF file.  The `read_lef -library` flag reads the MACROs in the LEF file.
If neither of the `-tech` and `-library` flags are specified they default
to `-tech -library` if no technology has been read and `-library` if a
technology exists in the database.

````{eval-rst}
.. tabs::

   .. code-tab:: tcl

      read_lef liberty1.lef
      read_def reg1.def
      # Write the db for future runs.
      write_db reg1.db


   .. code-tab:: py

      from openroad import Design, Tech
      tech = Tech()
      tech.readLef("liberty1.lef")
      design = Design(tech)
      design.readDef("reg1.def")

      # Write the db for future runs.
      design.writedb("reg1.db")
````

The `read_verilog` command is used to build an OpenDB database as shown
below. Multiple Verilog files for a hierarchical design can be read.
The `link_design` command is used to flatten the design and make a database.


````{eval-rst}
.. tabs::

   .. code-tab:: tcl

      read_lef liberty1.lef
      read_verilog reg1.v
      link_design top
      # Write the db for future runs.
      write_db reg1.db


   .. code-tab:: py

      # Not supported in Python
````

## Example scripts

Example scripts demonstrating how to run OpenROAD on sample designs can
be found in `/test`. Flow tests taking sample designs from synthesizable RTL Verilog
to detail-routed final layout in the open-source technologies Nangate45 and Sky130HD are
shown below.

``` shell
gcd_nangate45.tcl
aes_nangate45.tcl
tinyRocket_nangate45.tcl
gcd_sky130hd.tcl
aes_sky130hd.tcl
ibex_sky130hd.tcl
```

Each of these designs use the common script `flow.tcl`.

## Read database file

To read a database from disk.

``` tcl
read_db filename
```
### Options

| Switch Name | Description |
| ----- | ----- |
| `filename` | Path to the file to be read |

### Examples
```
read_db reg1.db
```

## Write database file

To write a database to disk.

``` tcl
write_db [-compression level] filename
```
### Options

| Switch Name | Description |
| ----- | ----- |
| `-compression` | Gzip compression level. Must be between 0 (no compression) and 9 (best compression). Default is 6. Only applicable if the filename ends with `.gz`. |
| `filename` | Path to the file to be written. If the filename ends with `.gz`, the file will be compressed. |

### Examples
```
write_db reg1.db

# To write a database file with gzip compression.
write_db reg1.db.gz
```

## Abstract LEF Support

OpenROAD contains an abstract LEF writer that can take your current design
and emit an abstract LEF representing the external pins of your design and
metal obstructions.


``` tcl
write_abstract_lef (-bloat_factor bloat_factor|-bloat_occupied_layers) \
		   filename
```
### Options

| Switch Name | Description |
| ----- | ----- |
| `-bloat_factor` | Specifies the bloat factor used when bloating then merging shapes into LEF obstructions. The factor is measured in # of default metal pitches for the respective layer. A factor of `0` will result in detailed LEF obstructions |
| `-bloat_occupied_layers` | Generates cover obstructions (obstructions over the entire layer) for each layer where shapes are present |

### Examples
```
read reg1.db

# Bloat metal shapes by 3 pitches (respectively for every layer) and then merge
write_abstract_lef -bloat_factor 3 reg1_abstract.lef

# Produce cover obstructions for each layer with shapes present
write_abstract_lef -bloat_occupied_layers reg1_abstract.lef
```

## Write CDL netlist

To export the CDL netlist to disk.

``` tcl
write_cdl
  -masters list_of_cdl_files
  [-include_fillers]
  filename
```
### Options

| Switch Name | Description |
| ----- | ----- |
| `-masters` | List of CDL netlist dependencies. |
| `[-include_fillers]` | Export fillers to the CDL netlist |
| `filename` | Path to the file to be written, if the filename ends with `.gz` the file will be compressed using gzip. |

### Examples
```
write_cdl -masters {netlist1.cdl netlist2.cdl ...} -include_fillers netlist.cdl

# To write a database file with gzip compression.
write_cdl -masters {netlist1.cdl netlist2.cdl ...} -include_fillers netlist.cdl.gz
```

### Global Connections

#### Add global connections

The `add_global_connection` command is used to specify how to connect power and ground pins on design instances to the appropriate supplies.

```
add_global_connection -net net_name \
                      [-inst_pattern inst_regular_expression] \
                      -pin_pattern pin_regular_expression \
                      (-power|-ground) \
                      [-region region_name]
```

##### Options

| Switch Name | Description |
| ----- | ----- |
| `-net` | Specifies the name of the net in the design to which connections are to be added |
| `-inst_pattern` | Optional specifies a regular expression to select a set of instances from the design. (Default: .\*) |
| `-pin_pattern` | Species a regular expression to select pins on the selected instances to connect to the specified net |
| `-power` | Specifies that the net it a power net |
| `-ground` | Specifies that the net is a ground net |
| `-region` | Specifies the name of the region for this rule |

##### Examples
```
# Stdcell power/ground pins
add_global_connection -net VDD -pin_pattern {^VDD$} -power
add_global_connection -net VSS -pin_pattern {^VSS$} -ground

# SRAM power ground pins
add_global_connection -net VDD -pin_pattern {^VDDPE$}
add_global_connection -net VDD -pin_pattern {^VDDCE$}
add_global_connection -net VSS -pin_pattern {^VSSE$}
```

#### Perform global connections

The `global_connect` command is used to connect power and ground pins on design instances to the appropriate supplies.

```
global_connect [-force] [-verbose]
```

##### Options

| Switch Name | Description |
| ----- | ----- |
| `-force` | If specified, global connections will overwrite existing connections |
| `-verbose` | If specified, report the number of connections made and skipped. |

#### Clear global connection rules

The `clear_global_connect` command is used remove all defined global connection rules.

```
clear_global_connect
```

#### Report global connection rules

The `report_global_connect` command is used print out the currently defined global connection rules.

```
report_global_connect
```

#### Report cell type usage

The `report_cell_usage` command is used to print out the usage of cells for each type of cell.

```
report_cell_usage [-verbose] [module instance] [-file file] [-stage stage]
```

##### Options

| Switch Name | Description |
| ----- | ----- |
| `-verbose` | Add information about all leaf instances. |
| `module instance` | Report cell usage for a specified module instance. |
| `-file file` | Create cell usage snapshot with the given path to file. |
| `-stage stage` | Attach the stage to the snapshot. |

#### Report Timing Histogram

The `report_timing_histogram` command reports a visualization of the
slack distribution in the design.

```tcl
report_timing_histogram [-num_bins num_bins] [-bin_size bin_size] [-setup|-hold]
```

##### Options

| Switch Name | Description |
| ----- | ----- |
| `-num_bins` | Number of histogram bins to display (default is 10). Mutually exclusive with `-bin_size`. |
| `-bin_size` | Fixed bin size for histogram. Bins are aligned to multiples of bin_size in the user time unit (e.g., nanoseconds). Mutually exclusive with `-num_bins`. |
| `-setup` | Use setup paths (this is the default). |
| `-hold` | Use hold paths. |

#### Report Logic Depth Histogram

The `report_logic_depth_histogram` command reports a visualization of the
logic depth for all constrained endpoints. That is to say, bin the
one logic depth length for the most timing constrained path for each endpoint.
This is not necessarily the deepest path for the endpoint.

```tcl
report_logic_depth_histogram [-num_bins num_bins] [-exclude_buffers] [-exclude_inverters]
```

##### Options

| Switch Name | Description |
| ----- | ----- |
| `-num_bins` | Number of histogram bins to display (default is 10). |
| `-exclude_buffers` | Exclude buffers when counting critical path length. |
| `-exclude_inverters` | Exclude inverters when counting critical path length. |

#### 3D Blox

The `read_3dblox_bmap` command will read the bump map and place the bumps into the current design.

```tcl
read_3dblox_bmap filename
```

##### Options

| Switch Name | Description |
| ----- | ----- |
| `filename` | Path to the bump map. |

## TCL functions

Get the die and core areas as a list in microns: `llx lly urx ury`

```
ord::get_die_area
ord::get_core_area
```

The `place_inst` command is used to place an instance.  If -cell is
given then a new instance may be created as well as placed.

```
place_inst -name inst_name \
           (-origin xy_origin | -location xy_location) \
           [-orientation orientation] \
           [-cell library_cell] \
           [-status status]
```

##### Options

| Switch Name | Description |
| ----- | ----- |
| `-name` | The name of the instance |
| `-orientaton` | The orientation of the instance. Default is R0 |
| `-origin` | The x and y coordinates for where the origin of the instance is placed. |
| `-location` | The x and y coordinates for where the instance is placed. |
| `-cell` | Required if a new instance is to be created. |
| `-status` | The placement status of the instance. Default is PLACED |


## License

BSD 3-Clause License.