text stringlengths 14 100k | source stringclasses 1
value | repo stringclasses 810
values | language stringclasses 13
values |
|---|---|---|---|
<|fim_suffix|>
#endif /* BOARDS_POSIX_NRF_BSIM_SOC_SOC_NRF_COMMON_H */
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/<|fim_middle|>
#ifndef BOARDS_POSIX_NRF_BSIM_SOC_SOC_NRF_COMMON_H
#define BOARDS_POSIX_NRF_BSIM_SOC_SOC_NRF_COMMON_H
/* We reuse the real ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>cr.h>
static inline void soc_secure_read_deviceid(uint32_t deviceid[2])
{
deviceid[0] = nrf_ficr_deviceid_get(NRF_FICR, 0);
deviceid[1] = nrf_ficr_deviceid_get(NRF_FICR, 1);
}
static inline int soc_secure_mem_read(void *dst, void *src, size_t len)
{
(void)memcpy(dst, src, len);
return 0;
}
static i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _BOARD_POSIX_NRF52_BSIM_TIME_MACHINE_H
#define _BOARD_POSIX_NRF52_BSIM_TIME_MACHINE_H
#include "bs_types.h"
#include "time_machine_if.h"
#include <zephyr/toolchain.h>
#ifdef __cplusplus
extern "C" {
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Nordic Semiconductor ASA.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/init.h>
#include <hal/nrf_power.h>
void board_early_init_hook(void)
{
/* If the nrf52840dongle/nrf52840 board target is powered from USB
* (high voltage mode), GPIO output voltage is set ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>gpiote_latency_set(NRF_GPIOTE, NRF_GPIOTE_LATENCY_LOWPOWER);
}
}
<|fim_prefix|>/*
* Copyright (c) 2020 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/init.h>
#include <zephyr/logging/log.h>
#include <hal/nrf_gpiote.h>
LOG_MODULE_REGISTER(nrf5340_audio_dk_nrf53... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018-2021 Nordic Semiconductor ASA.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/devicetree.h>
#include <zephyr/logging/log.h>
#include <soc.h>
#include <hal/nrf_gpio.h>
LOG_MODULE_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>err = gpio_pin_set(port, RESET_GPIO_PIN, 0);
if (err) {
return err;
}
return 0;
}
#endif /* DT_NODE_HAS_STATUS_OKAY(RESET_NODE) */
<|fim_prefix|>/*
* Copyright (c) 2019 Nordic Semiconductor ASA.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/driver... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Aapo Vienamo
*
* SPDX-License-Identifier: Apache-2.0
*/
#inc<|fim_suffix|>_CCS_VDD_PWR_CTRL_INIT_PRIORITY
#error BOARD_CCS_VDD_PWR_CTRL_INIT_PRIORITY must be lower than SENSOR_INIT_PRIORITY
#endif
SYS_INIT(pwr_ctrl_init, POST_KERNEL,
CONFIG_BOARD_CCS_VDD_PWR_CTRL_INIT_PRIOR... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>NFIG_TRUSTED_EXECUTION_SECURE) && defined(CONFIG_SENSOR)
static int setup(void)
{
/* Initialization chain of Thingy:53 board requires some delays before on board
* sensors could be accessed after power up. In particular bme680 and bmm150
* sensors require, 2ms and 1ms power on delay respectively. In ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>)gpio_pin_configure_dt(&simctrl, GPIO_OUTPUT_HIGH);
LOG_INF("External SIM selected");
}
}
<|fim_prefix|>/*
* Copyright (c) 2024 Norik Systems
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/init.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/gpio.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Norik Systems
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/init.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(board_control, CONFIG_OCTOPUS_SOM_CONTROL_LOG_LEVEL);
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>EADY == NVMC_READY_READY_Busy) {
;
}
NRF_UICR->REGOUT0 = (NRF_UICR->REGOUT0 & ~((uint32_t)UICR_REGOUT0_VOUT_Msk)) |
(UICR_REGOUT0_VOUT_3V0 << UICR_REGOUT0_VOUT_Pos);
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
;
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2026 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/platform/hooks.h>
#include <soc.h>
#include <fsl_clock.h>
#if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0)
#define FRDM_IMXRT1186_HAS_NETC_ENABL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ORY_REGION_SIZE_KB(OCRAM2_SHM_SIZE))
#define REGION_HYPER_RAM_BASE_ADDRESS DT_REG_ADDR_BY_IDX(DT_NODELABEL(flexspi), 1)
#define REGION_HYPER_RAM_SIZE \
REGION_CUSTOMED_MEMORY_SIZE(MEMORY_REGION_SIZE_KB(HYPER_RAM_SIZE))
#define REGION_QSPI_FLASH_BASE_ADDRESS DT_REG_ADDR_BY_IDX(DT_NODELAB... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>18),
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD,
FLASH_DUMMY_CYCLES, READ_SDR, FLEXSPI_4PAD, 0x04),
/* Read Status LUTs */
[4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
/* Write Enable LUTs */
[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEX... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __FRDMIMXRT1186_FLEXSPI_NOR_CONFIG__
#define __FRDMIMXRT1186_FLEXSPI_NOR_CONFIG__
#include "fsl_common.h"
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) /* ascii "FCFB" Big Endian */
#define FLEXSPI_CFG_BLK_VERSION (0x560104... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2025 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/init.h>
#include <zephyr/device.h>
#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <fsl_clock.h>
#include <fsl_spc.h>
#include <soc.h>
/* Core clock frequency: 96MHz */
#define CLOCK_INIT_CORE_CLOCK 960... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>egulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
/*!< Set up dividers *... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portc))
RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn);
CLOCK_EnableClock(kCLOCK_GatePORT2);
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portd))
RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
CLOCK_EnableClock(kCLOCK_GatePORT3);
#endif
#if DT_NODE_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2<|fim_suffix|>k Select Decides what input source the lptmr will clock from
*
* 0 <- Reserved
* 1 <- 16K FRO
* 2 <- Reserved
* 3 <- Combination of clocks configured in MRCC_LPTMR0_CLKSEL[MUX] field
*/
#if DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x1
CLOCK_SetupFRO16KClocking(kCL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>er4))
CLOCK_SetClockDiv(kCLOCK_DivCTIMER4, 1u);
CLOCK_AttachClk(kFRO_LF_DIV_to_CTIMER4);
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wwdt0))
CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1u);
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc1))
CLOCK_Set... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2025 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/init.h>
#include <zephyr/device.h>
#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <fsl_clock.h>
#include <soc.h>
/*******************************************************************************
* Definitions
**... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <ze<|fim_suffix|>FES = CONFIG_CLEAR_FUNCTIONAL_RESET_FLAG;
#endif
}
#endif /* CONFIG_BOARD_EARLY_INIT_HOOK */
<|fim_middle|>phyr/platform/hooks.h>
#include <soc.h>
#if CONFIG_BOARD_EARLY_INIT_HOO... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "boot_header.h"
#include "fsl_common.h"
/******************************************************************************
* External references
******************************************************************************/... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_BOOT_HEADER_H_
#define ZEPHYR_INCLUDE_BOOT_H<|fim_suffix|>******************************************************************************/
typedef uint32_t boot_lc_config_t;
extern const boot_lc_config_t lc_conf... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>);
CLOCK_EnableClock(kCLOCK_GatePERIPH_GROUP0);
RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
CLOCK_EnableClock(kCLOCK_GateLPUART0);
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1))
/* Switch PERIPH_GROUP1 to FRO12M */
CLOCK_AttachClk(kFRO12M_to_PERIPH_GROUP1);
/* Set PGRP1CLKDIV ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024-2025 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/init.h>
#include <zephyr/device.h>
#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <fsl_clock.h>
#include <fsl_spc.h>
#include <soc.h>
#if CONFIG_USB_DC_NXP_EHCI
#include "usb_phy.h"
#include "us... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 1U);
CLOCK_AttachClk(kPLL0_to_CTIMER0);
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer1))
CLOCK_SetClkDiv(kCLOCK_DivCtimer1Clk, 1U);
CLOCK_AttachClk(kPLL0_to_CTIMER1);
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer2))
CLOCK_SetClkDiv(kCLOCK_DivCtimer2Clk, 1U);
CLOCK_AttachClk(kPLL0... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2018-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "mcxn_flexspi_nor_config.h"
__attribute__((section(".flexspi_fcb"), used))
#ifndef FLEXSPI_USE_CUSTOM_FCB
#define FLEXSPI_USE_CUSTOM_FCB (0)
#endif
#if FLEXSPI_USE_CUSTOM_FCB
/* FCB for W25Q64 */
const uint8... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>lexspi_lut_seq_t lut_custom_seq[12];
/* [0x1b0-0x1bf] Reserved for future use */
uint32_t reserved4[4];
} flexspi_mem_config_t;
#define NOR_CMD_INDEX_READ CMD_INDEX_READ /* 0 */
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS /* 1 */
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRI... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> FC_STOP_EXE, FC_FLEXSPI_1PAD,
0x00),
[4 * 11 + 0] = FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR,
FC_FLEXSPI_1PAD,
0xC7, FC_STOP_EXE,
FC_FLEXSPI_1PAD,
0x00),
},
},
.pageSize = 0x100,
.sectorSize = 0x1000,
.ipcmdSerialClkFreq = 0,
.blockSize = 0x10000,
.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>mm 1 for Shared Data Out */
SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN(1);
/* Set Receive I2S - Flexcomm 0 SCK, WS from shared signal set 0 */
SYSCTL1->FCCTRLSEL[0] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |
SYSCTL1_FCCTRLSEL_WSINSEL(1);
/* Set Transmit I2S - Flexcomm 1 SCK, WS from ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/**
* Copyright 2024 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <zephyr/devicetree.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/gpio.h>
LOG_MODULE_REGISTER(board_control, CONFIG_BOARD_MIMX93_EVK_LOG_LEVEL);
#if DT_HAS_COMP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>U);
/* Unlock the IERB. It will warm reset whole NETC. */
NETC_PRIV->NETCRR &= ~NETC_PRIV_NETCRR_LOCK_MASK;
while ((NETC_PRIV->NETCRR & NETC_PRIV_NETCRR_LOCK_MASK) != 0U) {
}
/* Lock the IERB. */
NETC_PRIV->NETCRR |= NETC_PRIV_NETCRR_LOCK_MASK;
while ((NETC_PRIV->NETCSR & NETC_PRIV_NETCSR_STATE_M... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: Copyright 2026 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <soc.h>
stati<|fim_suffix|>n 0;
}
/*
* Because platform is using ARM SCMI, drivers like scmi, mbox etc. are
* initial... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2<|fim_suffix|>YS_INIT(board_init, PRE_KERNEL_2, 10);
<|fim_middle|>024-2025 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <soc.h>
static int board_init(void)
{
return 0;
}
/*
* Because platfo... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>= SYSCTL_FCCTRLSEL_SCKINSEL(1) |
SYSCTL_FCCTRLSEL_WSINSEL(1);
#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
/* Select Receive I2S - Flexcomm 6 Data in from shared signal set 0 */
SYSCTL->FCCTRLSEL[6] |= SYSCTL_FCCTRLSEL_DATAINSEL(1);
/* Select Transmit I2S - Flexcomm 7 Data out to shared signal set 0 */... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024-2025 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/init.h>
#include <zephyr/device.h>
#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <fsl_clock.h>
#include <fsl_spc.h>
#include <soc.h>
#if CONFIG_USB_DC_NXP_EHCI
#include "usb_phy.h"
#include "us... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2018-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "mcxn_flexspi_nor_config.h"
__attribute__((section(".flexspi_fcb"), used))
#ifndef FLEXSPI_USE_CUSTOM_FCB
#define FLEXSPI_USE_CUSTOM_FCB (0)
#endif
#if FLEXSP<|fim_suffix|>x00,
0x00, 0x00, 0x0... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2018-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef MCXN_FLEXSPI_NOR_CONFIG_
#define MCXN_FLEXSPI_NOR_CONFIG_
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/* FLEXSPI memory config block related definitions */
#define FLEXSPI_CF... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> so it
* will fetch more data than each AHB burst requires to meet alignment
* requirements
*
* Without this, the FlexSPI will return corrupted data during early
* boot, causing a hardfault. This can also be resolved by enabling
* the instruction cache in very early boot.
*/
FLEXSPI->AHBCR ... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2019-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "evkmimxrt1010_flexspi_nor_config.h"
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR)
__attribute__((section(".boot_hdr.conf"), used))
const flexspi_nor_config_t qspi_flash_config... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2019-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef EVKMIMXRT1011_FLEXSPI_NOR_CONFIG_
#define EVKMIMXRT1011_FLEXSPI_NOR_CONFIG_
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/* FLEXSPI memory config block related definitions */
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2018-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "evkmimxrt1015_flexspi_nor_config.h"
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR)
__attribute__((section(".boot_hdr.conf"), used))
const flexspi_nor_config_t qsp... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2018-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef EVKMIMXRT1015_FLEXSPI_NOR_CONFIG_
#define EVKMIMXRT1015_FLEXSPI_NOR_CONFIG_
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/* FLEXSPI memory config block related definitions */
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
* IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00,
* size: 4
*/
0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
/* #1.34, command: write_value, address:
* IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00,
* size: 4
*/
0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
/* #1.35, command: write_v... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> (0x41)
#define DCD_TAG_HEADER_SHIFT (24)
#define DCD_ARRAY_SIZE 1
#endif /* DCD_ */
<|fim_prefix|>/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef DCD_
#define DCD_
<|fim_middle|>
#include <stdint.h>
#define DCD_TAG_HEADER (0xD... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2018-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "evkmimxrt1020_flexspi_nor_config.h"
#if de<|fim_suffix|>Read LUTs */
[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB,
RADDR_SDR, FLEXSPI_4PAD, 0x18),
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR,... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>sy, 1 - busy flag is 0 when
* flash device is busy
*/
uint16_t busy_bit_polarity;
/* [0x080-0x17f] Lookup table holds Flash command sequences */
uint32_t lookup_table[64];
/* [0x180-0x1af] Customizable LUT Sequences */
flexspi_lut_seq_t lut_custom_seq[12];
/* [0x1b0-0x1bf] Reserved for future us... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>x1F, 0x82, 0x08, 0x00, 0x00, 0x00, 0xE1,
/* #1.84, command: write_value, address:
* IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0xE1,
* size: 4
*/
0x40, 0x1F, 0x82, 0x0C, 0x00, 0x00, 0x00, 0xE1,
/* #1.85, command: write_value, address:
* IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0xE1,
* size: 4... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyr<|fim_suffix|>AY_SIZE 1
#endif /* DCD_ */
<|fim_middle|>ight 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef DCD_
#define DCD_
#include <stdint.h>
#define DCD_TAG_HEADER (0xD2)
#define DCD_VERSION (0x41)
#define DCD_TAG_HEADER_SHIF... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "evkmimxrt1024_flexspi_nor_config.h"
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR)
__attribute__((section(".boot_hdr.conf"), used))
const flexspi_nor_config_t qspi_fla... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef EVKMIMXRT1024_FLEXSPI_NOR_CONFIG_
#define EVKMIMXRT1024_FLEXSPI_NOR_CONFIG_
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/* FLEXSPI memory config block related definitions */
#defi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B,
/* #1.98, command: write_value, address:
* SEMC_BR4, value: 0x90000021, size: 4
*/
0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21,
/* #1.99, command: write_value, address:
* SEMC_BR5, value: 0xA0000019, size: 4
*/
0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef DCD_
#define DCD_
#include <stdint.h>
#d<|fim_suffix|>(24)
#define DCD_ARRAY_SIZE 1
#endif /* DCD_ */
<|fim_middle|>efine DCD_TAG_HEADER (0xD2)
#define DCD_VERSION (0x41)
#define... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "evkmimxrt1040_flexspi_nor_config.h"
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR)
__attribute__((section(".boot_hdr.conf"), used))
const flexspi_nor_config_t qspi_fla... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef EVKMIMXRT1040_FLEXSPI_NOR_CONFIG_
#define EVKMIMXRT1040_FLEXSPI_NOR_CONFIG_
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/* FLEXSPI memory config block related definitions */
#defi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
/* #1.93, command: write_value, address:
* SEMC_BMCR1, value: 0x81, size: 4
*/
0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
/* #1.94, command: write_value, address:
* SEMC_BR0, value: 0x8000001B, size: 4
*/
0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
#endif /* DCD_ */
<|fim_prefix|>/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Id<|fim_middle|>entifier: Apache-2.0
*/
#ifndef DCD_
#define DCD_
#include <stdint.h>
#define DCD_TAG_HEADER (0xD2)
#define DCD_VERSION (0x41)
#define DCD_TAG_HEADER_SHIFT (24)
#define ... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2017-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "evkbimxrt1050_flexspi_nor_config.h"
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR)
__attribute__((section(".boot_hdr.conf"), used))
const flexspi_nor_config_t hyperflash_config... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2017-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef EVKBMIMXRT1050_FLEXSPI_NOR_CONFIG_
#define EVKBMIMXRT1050_FLEXSPI_NOR_CONFIG_
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/* FLEXSPI memory config block related definitions *... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>EXSPI_NOR) */
<|fim_prefix|>/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "evkbimxrt1050_flexspi_nor_config.h"
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR)
__attribute__((section(".boot_hdr.conf"), used))
const f... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_09, value: 0x110F9,
* size: 4
*/
0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9,
/* #1.61, command: write_value, address:
* IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9,
* size: 4
*/
0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9,
/* #1.62, command: write_value, address:
* IOMUXC_SW_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2021 NXP
* All rights reserved.
*
* SPDX-License-Ident<|fim_suffix|>Y_SIZE 1
#endif /* DCD_ */
<|fim_middle|>ifier: Apache-2.0
*/
#ifndef DCD_
#define DCD_
#include <stdint.h>
#define DCD_TAG_HEADER (0xD2)
#define DCD_VERSION (0x41)
#define DCD_TAG_HEADER_SHIFT... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "evkbmimxrt1060_flexspi_nor_config.h"
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR)
__attribute__((section(".boot_hdr.conf"), used))
const flexspi_nor_config_t qspi_flash_config = {... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>4 - Quad,
* 8 - Octal
*/
uint8_t sflash_pad_type;
/* [0x046-0x046] Serial Flash Frequency, device specific
* definitions, See System Boot Chapter for more details
*/
uint8_t serial_clk_freq;
/* [0x047-0x047] LUT customization Enable, it is required if
* the program/erase cannot be done using... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>PI_4PAD, 0x04),
/* Read Status LUTs */
[4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
/* Write Enable LUTs */
[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
0x06, STOP, FLEXSPI_1PAD, 0x0),
/* Erase Sector LUTs */
[4 * 5 + 0] = F... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2018-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef EVKMIMXRT1060_FLEXSPI_NOR_CONFIG_
#define EVKMIMXRT1060_FLEXSPI_NOR_CONFIG_
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/* FLEXSPI memory<|fim_suffix|>cmd_enable;
/* [0x01d-... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2020-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dcd.h"
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR)
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA)
__attribute__((sectio... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef DCD_
#define DCD_
#include <stdint.h>
#define DCD_TAG_HEADER (0xD2)
#define DCD_VERSION (0x41)
#define DCD_TAG_HEADER_SHIFT (24)
#define DCD_ARRAY_SIZE 1
#endif /* DCD_ */
<|endoftext|> | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2018-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "evkmimxrt1064_flexspi_nor_config.h"
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR)
__attribute__((section(".boot_hdr.conf"), used))
const flexspi_nor_config_t qsp... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ting_override;
/* [0x06c-0x06f] DQS pad setting override value */
uint32_t dqs_pad_setting_override;
/* [0x070-0x073] Timeout threshold for read status command */
uint32_t timeout_in_ms;
/* [0x074-0x077] CS deselect interval between two commands */
uint32_t command_interval;
/* [0x078-0x07b] CLK ed... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "dcd.h"
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR)
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_DEVICE_CONFIGURATION_DATA)
__attribute__((section(".bo... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef DCD_
#define DCD_
#include <stdint.h>
#define DCD_TAG_HEADER (0xD2)
#def<|fim_suffix|>
#define DCD_ARRAY_SIZE 1
#endif /* DCD_ */
<|fim_middle|>ine DCD_VERSION (0x41)
#define DCD... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "evkmimxrt1160_flexspi_nor_config.h"
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR)
__attribute__((section(".boot_<|fim_suffix|>efined(CONFIG_NXP_IMXRT_BOOT_HEADER) && d... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2021-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef EVKMIMXRT1160_FLEXSPI_NOR_CONFIG_
#define EVKMIMXRT1160_FLEXSPI_NOR_CONFIG_
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/* FLEXSPI memory config block related definitions */
#define FLEXSP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>mand: write_value, address:
* IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14,
* value: 0x00, 0x08,
* size: 4
*/
0x40, 0x0E, 0x82, 0x8C, 0x00, 0x00, 0x00, 0x08,
/* #1.75, command: write_value, address:
* IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15,
* value: 0x00, 0x08,
* size: 4
*/
0x40, 0x0E, 0x82, 0x90... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ndif /* DCD_ */
<|fim_prefix|>/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef DCD_
#define DCD_
#include <stdint.h>
#def<|fim_middle|>ine DCD_TAG_HEADER (0xD2)
#define DCD_VERSION (0x41)
#define DCD_TAG_HEADER_SHIFT (24)
#define DCD_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2018-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "evkbmimxrt1170_flexspi_nor_config.h"
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CO<|fim_suffix|>x60, STOP, FLEXSPI_1PAD, 0x0),
/* Set Read Register LUTs */
[4 * 12 + 0] = FLEXSP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>XSPI_NOR_CONFIG_ */
<|fim_prefix|>/*
* Copyright 2018-2<|fim_middle|>022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef EVKMIMXRT1170_FLEXSPI_NOR_CONFIG_
#define EVKMIMXRT1170_FLEXSPI_NOR_CONFIG_
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/* FLE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>* 12 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
0xC0, WRITE_SDR, FLEXSPI_1PAD, 0x01),
[4 * 12 + 1] = FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD,
0x00, 0, 0, 0),
},
},
.page_size = 256u,
.sector_size = 4u * 1024u,
.ipcmd_serial_clk_freq = 0x1,
.block_size = 64u * 1024u,
.is_uniform_block_size... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2018-2020, 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef EVKMIMXRT1170_FLEXSPI_NOR_CONFIG_
#define EVKMIMXRT1170_FLEXSPI_NOR_CONFIG_
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/* FLEXSPI memory config block related definitions */
#define ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "xmcd.h"
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI_NOR)
#if defined(XIP_BOOT_HEADER_XMCD_ENABLE) && (XIP_BOOT_HEADER_XMCD_ENABLE == 1)
__attribute__((section(".boot_hdr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 20<|fim_suffix|>endif /* XMCD_ */
<|fim_middle|>22 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef XMCD_
#define XMCD_
#include <stdint.h>
#<|endoftext|> | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/platform/hooks.h>
#include <soc.h>
#if CONFIG_BOARD_EARLY_INIT_HOOK
void board_early_init_hook(void)
{
#if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc))... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h>
#ifdef CONFIG_ARM_MPU_SRAM_WRITE_THROUGH
#define ARM_MPU_SRAM_REGION_ATTR REGION_RAM_WT_ATTR
#else
#define ARM_MPU_SRAM_REGION_ATTR REGION_RAM_ATTR
#en... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2018-2024 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "evkmimxrt1180_flexspi_nor_config.h"
/* clang-format off */
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) && \
defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_BOOT_FLEXSPI... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ed3[2];
/* [0x050-0x053] Size of Flash connected to A1 */
uint32_t sflash_a1_size;
/* [0x054-0x057] Size of Flash connected to A2 */
uint32_t sflash_a2_size;
/* [0x058-0x05b] Size of Flash connected to B1 */
uint32_t sflash_b1_size;
/* [0x05c-0x05f] Size of Flash connected to B2 */
uint32_t sflash... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2022-2023 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/init.h>
#include "fsl_power.h"
#include "fsl_inputmux.h"
#include <zephyr/pm/policy.h>
#include "board.h"
#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP
#include "flash_clock_setup.h"
#endif
/* OTP fuse index. */
#define FR... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>OOT 0x0
__ramfunc int32_t power_manager_set_profile(uint32_t power_profile);
<|fim_prefix|>/*
<|fim_middle|> * Copyright 2023 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#define POWER_PROFILE_FRO192M_900MV 0xFF
#define POWER_PROFILE_FRO96M_800MV 0x1
#define POWER_PROFILE_AFTER_B<|endoftext|> | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2018-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "flash_config.h"
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && (CONFIG_NXP_IMXRT_BOOT_HEADER == 1)
__attribute__((section(<|fim_suffix|>u << FLEXSPI_MISC_OFFSET_DDR_MODE_ENABLE),
.deviceType = kF... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2018-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
*/
#ifndef FLASH_CONFIG_H_
#define FLASH_CONFIG_H_
#include <stdint.h>
#include "fsl_iap.h"
/* FLEXSPI memory config block related defi<|fim_suffix|>D_SAMPLE_CLK_LOOPBACK_FROM_DQS_PAD = 1,
FLEXSPI_READ_S... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>REDSCKSEL(1) |
SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL(1);
#endif
/* Set Receive I2S - Flexcomm 1 SCK, WS from shared signal set 0 */
SYSCTL1->FCCTRLSEL[1] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |
SYSCTL1_FCCTRLSEL_WSINSEL(1);
/* Set Transmit I2S - Flexcomm 3 SCK, WS from shared signal set 0 */
SYSCTL1->... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2020-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "flash_config.h"
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && (CONFIG_NXP_IMXRT_BOOT_HEADER == 1)
__attribute__((section(".flash_conf"), used))
const flexspi_nor_config_t flexspi_config = {
.mem... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef FLASH_CONFIG_
#define FLASH_CONFIG_
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/* FLEXSPI memory config block related definitions */
#define FLASH_CONFIG_BLOCK_TAG (0x4246434... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>RLSET_SHAREDDATASEL(3);
/* Enable Transmit I2S - Flexcomm 3 for Shared Data Out */
SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN(1);
#endif
/* Set Receive I2S - Flexcomm 1 SCK, WS from shared signal set 0 */
SYSCTL1->FCCTRLSEL[1] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |
SYSCTL1_FCCTRLS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>udioPll(&g_audioPllConfig_clock_init); /* 532.48MHZ */
CLOCK_InitAudioPfd(kCLOCK_Pfd1, 24U); /* 399.36MHz */
CLOCK_InitAudioPfd(kCLOCK_Pfd3, 26U); /* Enable Audio PLL PFD3 clock to 368.64MHZ */
CLOCK_EnableAudioPllPfdClkForDomain(kCLOCK_Pfd1, kCLOCK_AllDomainEnable);
CLOCK_EnableAudioPllPf... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> + 0] = FC_XSPI_LUT_SEQ(FC_CMD_SDR, FC_XSPI_1PAD,
0x05, FC_CMD_READ_SDR, FC_XSPI_1PAD, 0x04),
/* Read Status OPI */
[5 * 2 + 0] = FC_XSPI_LUT_SEQ(FC_CMD_DDR, FC_XSPI_8PAD,
0x05, FC_CMD_DDR, FC_XSPI_8PAD, 0xFA),
[5 * 2 + 1] = FC_XSPI_LUT_SEQ(FC_CMD_RADDR_DDR,
FC_XSPI_8PAD, 0x20,... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023, 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*
*/
#ifndef FLASH_CONFIG_H_
#define FLASH_CONFIG_H_
#include <stdint.h>
#include "fsl_common.h"
/* XSPI memory config block related definitions */
#define FC_XSPI_CFG_BLK_TAG (0x42464346UL) /* ascii "FCFB" Big Endian */
#defi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2021-2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <flash_config.h>
__attribute__((section(".flash_conf"), used))
const fc_flexspi_nor_config_t flexspi_config = {
.memConfig = {
.tag = FC_BLOCK_TAG,
.version = FC_BLOCK_VERSION,
.readSamp... | fim | zephyrproject-rtos/zephyr | c |
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