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return ret_val;
}
static void gpio_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
int base_addr = 0x18040000;
if (addr == 0x44){ // This is for UART Multiplexing, skip.
return;
}
write_mmio_mitm(base_addr + addr, val);
return;
}
static const MemoryRegionOps gpio_mmio_ops = {
.read = gpio_mmio_read,
.write = gpio_mmio_write,
.endianness = DEVICE_BIG_ENDIAN
};
// MMIO Callbacks for SPI
static uint64_t spi_mmio_read(void *opaque, hwaddr addr, unsigned size)
{
struct SPI_IO *spi_io = opaque;
switch (addr) {
case 0x0:
return 1;
case 0x8:
break;
case 0xC: // (SPI_READ_DATA_ADDR)
spi_io->cmd = ((spi_io->cmd & 0x0F) << 4 | (spi_io->cmd & 0xF0) >> 4
| (spi_io->cmd & 0xF000) >> 4 | (spi_io->cmd & 0xF00) << 4 |
(spi_io->cmd & 0xF0000) << 4 | (spi_io->cmd & 0xF00000) >> 4 |
(spi_io->cmd & 0xF000000) << 4 | (spi_io->cmd & 0xF0000000) >> 4);
if (spi_io->cmd == 0x9F){
spi_io->cmd = 0;
return 0x1337;
}
break;
default:
break;
}
return 0;
}
static void spi_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
struct SPI_IO *spi_io = opaque;
switch (addr) {
case 0x0:
break;
case 0x8: // (SPI_IO_CONTROL_ADDR)
if ((val == 0x70000) && (spi_io->cmd_in_progress == 0)){
// CS0-2 are high which means disabled
// reset cmd offset and cmd
spi_io->cmd_offset = 0;
spi_io->cmd = 0;
spi_io->cmd_in_progress = 1;
}
else if ((val == 0x70000) && (spi_io->cmd_in_progress == 1)){
spi_io->cmd_in_progress = 0;
break;
}
if ((val & (1 << 8)) && (val & (1 << 18))){
// CS2 is low (active)
// SPI_Clock is high, so grab data value
if (spi_io->cmd_offset == 32){
break;
}
spi_io->cmd |= (val & 1) << spi_io->cmd_offset;
spi_io->cmd_offset++;
}
break;
default:
break;
}
return;
}
static const MemoryRegionOps spi_mmio_ops = {
.read = spi_mmio_read,
.write = spi_mmio_write,
.endianness = DEVICE_BIG_ENDIAN
};
// MMIO Callbacks for DDR
static uint64_t ddr_mmio_read(void *opaque, hwaddr addr, unsigned size)
{
int base_addr = 0x18000000;
int ret_val = 0;
ret_val = read_mmio_mitm(base_addr + addr);
return ret_val;
}
static void ddr_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)