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--[ 1 - Background
--[ 1.1 - Memory Types and Performance Optimizations
Modern CPUs support multiple memory types that are configurable by the OS
and might be configurable by the VMM. These types enforce the cache policy
used. There are cacheable memory types like write-back (WB), write-through
(WT), and write-protect (WP), and uncacheable memory types like uncacheable
(UC) and write-combining (WC).
The standard page created by the OS for userland applications are WB, which
allow values to be cached and are written back to the memory when there is
bandwidth for it and the memory in case is not being actively used and updated.
--[ 1.2 - Write-Combining
Write-Combining (WC) is a memory performance optimization technique, which
allows for the combination of multiple write operations into a single
transaction, which can then be written to memory in a more efficient
manner, reducing the number of bus requests required for the write
operations.
For this, the CPU keeps the modified data of all store operations to a
specific cache line in an internal buffer, until the data can be committed
to the memory. Then, the data is flushed from the buffer and committed to
external memory.
We also note, the __Software Optimization Guide for the AMD Zen4
Microarchitecture (ver. 57647, from January 2023)__ describes in 2.13.3
Write Combine Buffers the improvements to performance made using their
aggressively combined write buffers.
--[ 1.3 - Microarchitectural Buffers
Lots of different microarchitectural structures are used in modern CPUs to
store data in-transit. Many of such structures have been publicly
documented and some of them have been even reverse engineered. At the same
time, there are several prior research exploring the leakage or inference
of data from internal CPU buffers, include Fallout [2], Zombieload [3], and
RIDL [4]. Each of such attacks target a different buffer, e.g. store
buffers, load buffers, and fill buffers.
Since the security community identified such behaviors, mitigations have
been deployed on newer hardware having in mind that such buffers should
also be treated as containing assets in their threat model.
In this work, we have identified an undocumented microarchitectural buffer,
which seems to be handling previously evicted cache entries, when such
entries have been tagged as belonging to uncacheable memory. We are calling
this undocumented microarchitectural structure the _eviction buffer_.
--[ 2 - barbieSparkles
At the high-level, barbieSparkles may load data from unintended evicted
cache entries from the eviction buffer after we change the memory type to
WC. We were able to see this behavior bypassing context boundaries such as
cross threads, cross cores, and even VM host to guest.
--[ 2.1 - Eviction Sets
A precondition for barbieSparkles is that the attacker is able to evict
cache entries from the victim process. There is numerous research in this
area, ranging from reverse engineering cache sets to a more brute-force
style.
--[ 2.2 - Memory Type Change
Normally, only OS and VMM software have permissions to change the memory
type of a specific page. For our proof-of-concept, we use the PTEditor
library [5]. PTEditor is a library that enables modification of page-table
levels, change memory types, and other memory manipulation actions through
user level APIs provided by a Linux Kernel Module.
--[ 2.3 - First Sparkle
Our first sighting of a sparkle occurred by chance, and it was unexpected.
We wanted to check if we can modify the memory type from cacheable memory
and validate a cache poisoning behavior. There are many reasons why a
modern CPU invalidates and poisons cache lines. And if one is playing with
memory types, why not just check also uncacheables one? And there it was,
when changing the memory type of a process from a cacheable one to WC.
Following the first time spotting it, we began our research by implementing
various tests which could give us one or more insights on what and why it
was happening. The first test was not perfect:
---------------------------------------------------------------------------
// Populate the cache with cache lines from a WB page by performing normal
loads
memset(buf_targetsrc, 0x33);
// Load a secret in a buffer by performing normal loads
memset(buf_secret, secret_val);
// Change the memory type of the page to WC
entry.pte = ptedit_apply_mt(entry.pte, wc_mt);
// Read from memory corresponding to an entry in the cache.
targetsrc_val = *(volatile uint32_t*) buf_targetsrc;
---------------------------------------------------------------------------
We could see some sparkle, but it wasn't clear where and why: