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def SETE(cpu, dest):
"""
Sets byte if equal.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.ZF, 1, 0)) |
def SETGE(cpu, dest):
"""
Sets byte if greater or equal.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.SF == cpu.OF, 1, 0)) |
def SETNAE(cpu, dest):
"""
Sets byte if not above or equal.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.CF, 1, 0)) |
def SETNB(cpu, dest):
"""
Sets byte if not below.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.CF == False, 1, 0)) |
def SETNBE(cpu, dest):
"""
Sets byte if not below or equal.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, Operators.AND(cpu.CF == False, cpu.ZF == False), 1, 0)) |
def SETNG(cpu, dest):
"""
Sets byte if not greater.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, Operators.OR(cpu.ZF, cpu.SF != cpu.OF), 1, 0)) |
def SETNLE(cpu, dest):
"""
Sets byte if not less or equal.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, Operators.AND(cpu.ZF == False, cpu.SF == cpu.OF), 1, 0)) |
def SETNO(cpu, dest):
"""
Sets byte if not overflow.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.OF == False, 1, 0)) |
def SETNS(cpu, dest):
"""
Sets byte if not sign.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.SF == False, 1, 0)) |
def SETNZ(cpu, dest):
"""
Sets byte if not zero.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.ZF == False, 1, 0)) |
def SETO(cpu, dest):
"""
Sets byte if overflow.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.OF, 1, 0)) |
def SETP(cpu, dest):
"""
Sets byte if parity.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.PF, 1, 0)) |
def SETPE(cpu, dest):
"""
Sets byte if parity even.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.PF, 1, 0)) |
def SETPO(cpu, dest):
"""
Sets byte if parity odd.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.PF == False, 1, 0)) |
def SETS(cpu, dest):
"""
Sets byte if sign.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.SF, 1, 0)) |
def SETZ(cpu, dest):
"""
Sets byte if zero.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.ZF, 1, 0)) |
def XCHG(cpu, dest, src):
"""
Exchanges register/memory with register.
Exchanges the contents of the destination (first) and source (second)
operands. The operands can be two general-purpose registers or a register
and a memory location. If a memory operand is referenced, the processor's
locking protocol is automatically implemented for the duration of the
exchange operation, regardless of the presence or absence of the LOCK
prefix or of the value of the IOPL.
This instruction is useful for implementing semaphores or similar data
structures for process synchronization.
The XCHG instruction can also be used instead of the BSWAP instruction
for 16-bit operands::
TEMP = DEST
DEST = SRC
SRC = TEMP
:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.
"""
temp = dest.read()
dest.write(src.read())
src.write(temp) |
def LEAVE(cpu):
"""
High level procedure exit.
Releases the stack frame set up by an earlier ENTER instruction. The
LEAVE instruction copies the frame pointer (in the EBP register) into
the stack pointer register (ESP), which releases the stack space allocated
to the stack frame. The old frame pointer (the frame pointer for the calling
procedure that was saved by the ENTER instruction) is then popped from
the stack into the EBP register, restoring the calling procedure's stack
frame.
A RET instruction is commonly executed following a LEAVE instruction
to return program control to the calling procedure::
IF Stackaddress_bit_size = 32
THEN
ESP = EBP;
ELSE (* Stackaddress_bit_size = 16*)
SP = BP;
FI;
IF OperandSize = 32
THEN
EBP = Pop();
ELSE (* OperandSize = 16*)
BP = Pop();
FI;
:param cpu: current CPU.
"""
cpu.STACK = cpu.FRAME
cpu.FRAME = cpu.pop(cpu.address_bit_size) |
def PUSH(cpu, src):
"""
Pushes a value onto the stack.
Decrements the stack pointer and then stores the source operand on the top of the stack.
:param cpu: current CPU.
:param src: source operand.
"""
# http://stackoverflow.com/questions/11291151/how-push-imm-encodes
size = src.size
v = src.read()
if size != 64 and size != cpu.address_bit_size // 2:
v = Operators.SEXTEND(v, size, cpu.address_bit_size)
size = cpu.address_bit_size
cpu.push(v, size) |
def POPF(cpu):
"""
Pops stack into EFLAGS register.
:param cpu: current CPU.
"""
mask = (0x00000001 |
0x00000004 |
0x00000010 |
0x00000040 |
0x00000080 |
0x00000400 |
0x00000800)
val = cpu.pop(16)
eflags_size = 32
cpu.EFLAGS = Operators.ZEXTEND(val & mask, eflags_size) |
def POPFQ(cpu):
"""
Pops stack into EFLAGS register.
:param cpu: current CPU.
"""
mask = 0x00000001 | 0x00000004 | 0x00000010 | 0x00000040 | 0x00000080 | 0x00000400 | 0x00000800
cpu.EFLAGS = (cpu.EFLAGS & ~mask) | cpu.pop(64) & mask |
def INT(cpu, op0):
"""
Calls to interrupt procedure.
The INT n instruction generates a call to the interrupt or exception handler specified
with the destination operand. The INT n instruction is the general mnemonic for executing
a software-generated call to an interrupt handler. The INTO instruction is a special
mnemonic for calling overflow exception (#OF), interrupt vector number 4. The overflow
interrupt checks the OF flag in the EFLAGS register and calls the overflow interrupt handler
if the OF flag is set to 1.
:param cpu: current CPU.
:param op0: destination operand.
"""
if op0.read() != 0x80:
logger.warning("Unsupported interrupt")
raise Interruption(op0.read()) |
def CALL(cpu, op0):
"""
Procedure call.
Saves procedure linking information on the stack and branches to the called procedure specified using the target
operand. The target operand specifies the address of the first instruction in the called procedure. The operand can
be an immediate value, a general-purpose register, or a memory location.
:param cpu: current CPU.
:param op0: target operand.
"""
# TODO FIX 64Bit FIX segment
proc = op0.read()
cpu.push(cpu.PC, cpu.address_bit_size)
cpu.PC = proc |
def RET(cpu, *operands):
"""
Returns from procedure.
Transfers program control to a return address located on the top of
the stack. The address is usually placed on the stack by a CALL instruction,
and the return is made to the instruction that follows the CALL instruction.
The optional source operand specifies the number of stack bytes to be
released after the return address is popped; the default is none.
:param cpu: current CPU.
:param operands: variable operands list.
"""
# TODO FIX 64Bit FIX segment
N = 0
if len(operands) > 0:
N = operands[0].read()
cpu.PC = cpu.pop(cpu.address_bit_size)
cpu.STACK += N |
def JA(cpu, target):
"""
Jumps short if above.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, Operators.AND(cpu.CF == False, cpu.ZF == False), target.read(), cpu.PC) |
def JB(cpu, target):
"""
Jumps short if below.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.CF == True, target.read(), cpu.PC) |
def JBE(cpu, target):
"""
Jumps short if below or equal.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, Operators.OR(cpu.CF, cpu.ZF), target.read(), cpu.PC) |
def JC(cpu, target):
"""
Jumps short if carry.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.CF, target.read(), cpu.PC) |
def JCXZ(cpu, target):
"""
Jumps short if CX register is 0.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.CX == 0, target.read(), cpu.PC) |
def JECXZ(cpu, target):
"""
Jumps short if ECX register is 0.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.ECX == 0, target.read(), cpu.PC) |
def JRCXZ(cpu, target):
"""
Jumps short if RCX register is 0.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.RCX == 0, target.read(), cpu.PC) |
def JG(cpu, target):
"""
Jumps short if greater.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, Operators.AND(cpu.ZF == False, cpu.SF == cpu.OF), target.read(), cpu.PC) |
def JGE(cpu, target):
"""
Jumps short if greater or equal.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, (cpu.SF == cpu.OF), target.read(), cpu.PC) |
def JNB(cpu, target):
"""
Jumps short if not below.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.CF == False, target.read(), cpu.PC) |
def JNE(cpu, target):
"""
Jumps short if not equal.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, False == cpu.ZF, target.read(), cpu.PC) |
def JNG(cpu, target):
"""
Jumps short if not greater.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, Operators.OR(cpu.ZF, cpu.SF != cpu.OF), target.read(), cpu.PC) |
def JNO(cpu, target):
"""
Jumps short if not overflow.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, False == cpu.OF, target.read(), cpu.PC) |
def JNP(cpu, target):
"""
Jumps short if not parity.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, False == cpu.PF, target.read(), cpu.PC) |
def JNS(cpu, target):
"""
Jumps short if not sign.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, False == cpu.SF, target.read(), cpu.PC) |
def JO(cpu, target):
"""
Jumps short if overflow.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.OF, target.read(), cpu.PC) |
def JP(cpu, target):
"""
Jumps short if parity.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.PF, target.read(), cpu.PC) |
def JS(cpu, target):
"""
Jumps short if sign.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.SF, target.read(), cpu.PC) |
def JZ(cpu, target):
"""
Jumps short if zero.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.ZF, target.read(), cpu.PC) |
def LJMP(cpu, cs_selector, target):
"""
We are just going to ignore the CS selector for now.
"""
logger.info("LJMP: Jumping to: %r:%r", cs_selector.read(), target.read())
cpu.CS = cs_selector.read()
cpu.PC = target.read() |
def LOOP(cpu, dest):
"""
Loops according to ECX counter.
Performs a loop operation using the ECX or CX register as a counter.
Each time the LOOP instruction is executed, the count register is decremented,
then checked for 0. If the count is 0, the loop is terminated and program
execution continues with the instruction following the LOOP instruction.
If the count is not zero, a near jump is performed to the destination
(target) operand, which is presumably the instruction at the beginning
of the loop. If the address-size attribute is 32 bits, the ECX register
is used as the count register; otherwise the CX register is used::
IF address_bit_size = 32
THEN
Count is ECX;
ELSE (* address_bit_size = 16 *)
Count is CX;
FI;
Count = Count - 1;
IF (Count 0) = 1
THEN
EIP = EIP + SignExtend(DEST);
IF OperandSize = 16
THEN
EIP = EIP AND 0000FFFFH;
FI;
ELSE
Terminate loop and continue program execution at EIP;
FI;
:param cpu: current CPU.
:param dest: destination operand.
"""
counter_name = {16: 'CX', 32: 'ECX', 64: 'RCX'}[cpu.address_bit_size]
counter = cpu.write_register(counter_name, cpu.read_register(counter_name) - 1)
cpu.PC = Operators.ITEBV(cpu.address_bit_size, counter == 0, (cpu.PC + dest.read()) & ((1 << dest.size) - 1), cpu.PC + cpu.instruction.size) |
def LOOPNZ(cpu, target):
"""
Loops if ECX counter is nonzero.
:param cpu: current CPU.
:param target: destination operand.
"""
counter_name = {16: 'CX', 32: 'ECX', 64: 'RCX'}[cpu.address_bit_size]
counter = cpu.write_register(counter_name, cpu.read_register(counter_name) - 1)
cpu.PC = Operators.ITEBV(cpu.address_bit_size, counter != 0, (cpu.PC + target.read()) & ((1 << target.size) - 1), cpu.PC + cpu.instruction.size) |
def RCL(cpu, dest, src):
"""
Rotates through carry left.
Shifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the
second operand (count operand) and stores the result in the destination operand. The destination operand can be
a register or a memory location; the count operand is an unsigned integer that can be an immediate or a value in
the CL register. In legacy and compatibility mode, the processor restricts the count to a number between 0 and 31
by masking all the bits in the count operand except the 5 least-significant bits.
The RCL instruction shifts the CF flag into the least-significant bit and shifts the most-significant bit into the CF flag.
:param cpu: current CPU.
:param dest: destination operand.
:param src: count operand.
"""
OperandSize = dest.size
count = src.read()
countMask = {8: 0x1f,
16: 0x1f,
32: 0x1f,
64: 0x3f}[OperandSize]
tempCount = Operators.ZEXTEND((count & countMask) % (src.size + 1), OperandSize)
value = dest.read()
if isinstance(tempCount, int) and tempCount == 0:
# this is a no-op
new_val = value
dest.write(new_val)
else:
carry = Operators.ITEBV(OperandSize, cpu.CF, 1, 0)
right = value >> (OperandSize - tempCount)
new_val = (value << tempCount) | (carry << (tempCount - 1)) | (right >> 1)
dest.write(new_val)
def sf(v, size):
return (v & (1 << (size - 1))) != 0
cpu.CF = sf(value << (tempCount - 1), OperandSize)
cpu.OF = Operators.ITE(tempCount == 1,
sf(new_val, OperandSize) != cpu.CF,
cpu.OF) |
def RCR(cpu, dest, src):
"""
Rotates through carry right (RCR).
Shifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the
second operand (count operand) and stores the result in the destination operand. The destination operand can be
a register or a memory location; the count operand is an unsigned integer that can be an immediate or a value in
the CL register. In legacy and compatibility mode, the processor restricts the count to a number between 0 and 31
by masking all the bits in the count operand except the 5 least-significant bits.
Rotate through carry right (RCR) instructions shift all the bits toward less significant bit positions, except
for the least-significant bit, which is rotated to the most-significant bit location. The RCR instruction shifts the
CF flag into the most-significant bit and shifts the least-significant bit into the CF flag.
:param cpu: current CPU.
:param dest: destination operand.
:param src: count operand.
"""
OperandSize = dest.size
count = src.read()
countMask = {8: 0x1f,
16: 0x1f,
32: 0x1f,
64: 0x3f}[OperandSize]
tempCount = Operators.ZEXTEND((count & countMask) % (src.size + 1), OperandSize)
value = dest.read()
if isinstance(tempCount, int) and tempCount == 0:
# this is a no-op
new_val = value
dest.write(new_val)
else:
carry = Operators.ITEBV(OperandSize, cpu.CF, 1, 0)
left = value >> (tempCount - 1)
right = value << (OperandSize - tempCount)
new_val = (left >> 1) | (carry << (OperandSize - tempCount)) | (right << 1)
dest.write(new_val)
cpu.CF = Operators.ITE(tempCount != 0, (left & 1) == 1, cpu.CF)
# for RCR these are calculated before rotation starts
s_MSB = ((new_val >> (OperandSize - 1)) & 0x1) == 1
s_MSB2 = ((new_val >> (OperandSize - 2)) & 0x1) == 1
cpu.OF = Operators.ITE(tempCount == 1,
s_MSB ^ s_MSB2, cpu.OF) |
def ROL(cpu, dest, src):
"""
Rotates left (ROL).
Shifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the
second operand (count operand) and stores the result in the destination operand. The destination operand can be
a register or a memory location; the count operand is an unsigned integer that can be an immediate or a value in
the CL register. In legacy and compatibility mode, the processor restricts the count to a number between 0 and 31
by masking all the bits in the count operand except the 5 least-significant bits.
The rotate left shift all the bits toward more-significant bit positions, except for the most-significant bit, which
is rotated to the least-significant bit location.
:param cpu: current CPU.
:param dest: destination operand.
:param src: count operand.
"""
OperandSize = dest.size
count = src.read()
countMask = {8: 0x1f,
16: 0x1f,
32: 0x1f,
64: 0x3f}[OperandSize]
tempCount = Operators.ZEXTEND((count & countMask) % (OperandSize), OperandSize)
value = dest.read()
newValue = (value << tempCount) | (value >> (OperandSize - tempCount))
dest.write(newValue)
cpu.CF = Operators.ITE(tempCount != 0, (newValue & 1) == 1, cpu.CF)
s_MSB = ((newValue >> (OperandSize - 1)) & 0x1) == 1
cpu.OF = Operators.ITE(tempCount == 1, s_MSB ^ cpu.CF, cpu.OF) |
def SAL(cpu, dest, src):
"""
The shift arithmetic left.
Shifts the bits in the first operand (destination operand) to the left or right by the number of bits specified in the
second operand (count operand). Bits shifted beyond the destination operand boundary are first shifted into the CF
flag, then discarded. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination
operand.
:param cpu: current CPU.
:param dest: destination operand.
:param src: count operand.
"""
OperandSize = dest.size
count = src.read()
countMask = {8: 0x1f,
16: 0x1f,
32: 0x1f,
64: 0x3f}[OperandSize]
tempCount = Operators.ZEXTEND(count & countMask, dest.size)
tempDest = value = dest.read()
res = dest.write(Operators.ITEBV(dest.size, tempCount == 0, tempDest, value << tempCount))
# Should not modify flags if tempcount == 0
MASK = (1 << OperandSize) - 1
SIGN_MASK = 1 << (OperandSize - 1)
cpu.CF = Operators.OR(Operators.AND(tempCount == 0, cpu.CF), Operators.AND(tempCount != 0, (tempDest & (1 << (OperandSize - tempCount)) != 0)))
# OF is only set iff count == 1, and set to XOR(CF, MSB(res))
# OF is only defined for count == 1, but in practice (unit tests from real cpu) its calculated for count != 0
cpu.OF = Operators.ITE(tempCount != 0, (cpu.CF) ^ (((res >> (OperandSize - 1)) & 0x1) == 1), cpu.OF)
cpu.SF = Operators.OR(Operators.AND(tempCount == 0, cpu.SF), Operators.AND(tempCount != 0, (res & SIGN_MASK) != 0))
cpu.ZF = Operators.OR(Operators.AND(tempCount == 0, cpu.ZF), Operators.AND(tempCount != 0, res == 0))
cpu.PF = Operators.OR(Operators.AND(tempCount == 0, cpu.PF), Operators.AND(tempCount != 0, cpu._calculate_parity_flag(res))) |
def SAR(cpu, dest, src):
"""
Shift arithmetic right.
The shift arithmetic right (SAR) and shift logical right (SHR) instructions shift the bits of the destination operand to
the right (toward less significant bit locations). For each shift count, the least significant bit of the destination
operand is shifted into the CF flag, and the most significant bit is either set or cleared depending on the instruction
type. The SHR instruction clears the most significant bit. the SAR instruction sets or clears the most significant bit
to correspond to the sign (most significant bit) of the original value in the destination operand. In effect, the SAR
instruction fills the empty bit position's shifted value with the sign of the unshifted value
:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.
"""
OperandSize = dest.size
countMask = {8: 0x1f,
16: 0x1f,
32: 0x1f,
64: 0x3f}[OperandSize]
count = src.read() & countMask
value = dest.read()
res = Operators.SAR(OperandSize, value, Operators.ZEXTEND(count, OperandSize))
dest.write(res)
SIGN_MASK = (1 << (OperandSize - 1))
# We can't use this one as the 'true' expression gets eagerly calculated even on count == 0 + cpu.CF = Operators.ITE(count!=0, ((value >> Operators.ZEXTEND(count-1, OperandSize)) & 1) !=0, cpu.CF)
# cpu.CF = Operators.ITE(count!=0, ((value >> Operators.ZEXTEND(count-1, OperandSize)) & 1) !=0, cpu.CF)
if issymbolic(count):
# We can't use this one as the EXTRACT op needs the offset arguments to be concrete
# cpu.CF = Operators.ITE(count!=0, Operands.EXTRACT(value,count-1,1) !=0, cpu.CF)
cpu.CF = Operators.ITE(Operators.AND(count != 0, count <= OperandSize), ((value >> Operators.ZEXTEND(count - 1, OperandSize)) & 1) != 0, cpu.CF)
else:
if count != 0:
if count > OperandSize:
count = OperandSize
cpu.CF = Operators.EXTRACT(value, count - 1, 1) != 0
# on count == 0 AF is unaffected, for count > 0, AF is undefined.
# in either case, do not touch AF
cpu.ZF = Operators.ITE(count != 0, res == 0, cpu.ZF)
cpu.SF = Operators.ITE(count != 0, (res & SIGN_MASK) != 0, cpu.SF)
cpu.OF = Operators.ITE(count == 1, False, cpu.OF)
cpu.PF = Operators.ITE(count != 0, cpu._calculate_parity_flag(res), cpu.PF) |
def SHR(cpu, dest, src):
"""
Shift logical right.
The shift arithmetic right (SAR) and shift logical right (SHR)
instructions shift the bits of the destination operand to the right
(toward less significant bit locations). For each shift count, the
least significant bit of the destination operand is shifted into the CF
flag, and the most significant bit is either set or cleared depending
on the instruction type. The SHR instruction clears the most
significant bit.
:param cpu: current CPU.
:param dest: destination operand.
:param src: count operand.
"""
OperandSize = dest.size
count = Operators.ZEXTEND(src.read() & (OperandSize - 1), OperandSize)
value = dest.read()
res = dest.write(value >> count) # UNSIGNED Operators.UDIV2 !! TODO Check
MASK = (1 << OperandSize) - 1
SIGN_MASK = 1 << (OperandSize - 1)
if issymbolic(count):
cpu.CF = Operators.ITE(count != 0,
((value >> Operators.ZEXTEND(count - 1, OperandSize)) & 1) != 0,
cpu.CF)
else:
if count != 0:
cpu.CF = Operators.EXTRACT(value, count - 1, 1) != 0
cpu.ZF = Operators.ITE(count != 0, res == 0, cpu.ZF)
cpu.SF = Operators.ITE(count != 0, (res & SIGN_MASK) != 0, cpu.SF)
# OF is only defined for count == 1, but in practice (unit tests from real cpu) it's calculated for count != 0
cpu.OF = Operators.ITE(count != 0, ((value >> (OperandSize - 1)) & 0x1) == 1, cpu.OF)
cpu.PF = Operators.ITE(count != 0, cpu._calculate_parity_flag(res), cpu.PF) |
def SHLD(cpu, dest, src, count):
"""
Double precision shift right.
Shifts the first operand (destination operand) to the left the number of bits specified by the third operand
(count operand). The second operand (source operand) provides bits to shift in from the right (starting with
the least significant bit of the destination operand).
:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.
:param count: count operand
"""
OperandSize = dest.size
tempCount = Operators.ZEXTEND(count.read(), OperandSize) & (OperandSize - 1)
arg0 = dest.read()
arg1 = src.read()
MASK = ((1 << OperandSize) - 1)
t0 = (arg0 << tempCount)
t1 = arg1 >> (OperandSize - tempCount)
res = Operators.ITEBV(OperandSize, tempCount == 0, arg0, t0 | t1)
res = res & MASK
dest.write(res)
if isinstance(tempCount, int) and tempCount == 0:
pass
else:
SIGN_MASK = 1 << (OperandSize - 1)
lastbit = 0 != ((arg0 << (tempCount - 1)) & SIGN_MASK)
cpu._set_shiftd_flags(OperandSize, arg0, res, lastbit, tempCount) |
def _getMemoryBit(cpu, bitbase, bitoffset):
""" Calculate address and bit offset given a base address and a bit offset
relative to that address (in the form of asm operands) """
assert bitbase.type == 'memory'
assert bitbase.size >= bitoffset.size
addr = bitbase.address()
offt = Operators.SEXTEND(bitoffset.read(), bitoffset.size, bitbase.size)
offt_is_neg = offt >= (1 << (bitbase.size - 1))
offt_in_bytes = offt // 8
bitpos = offt % 8
new_addr = addr + Operators.ITEBV(bitbase.size, offt_is_neg, -offt_in_bytes, offt_in_bytes)
return (new_addr, bitpos) |
def BSF(cpu, dest, src):
"""
Bit scan forward.
Searches the source operand (second operand) for the least significant
set bit (1 bit). If a least significant 1 bit is found, its bit index
is stored in the destination operand (first operand). The source operand
can be a register or a memory location; the destination operand is a register.
The bit index is an unsigned offset from bit 0 of the source operand.
If the contents source operand are 0, the contents of the destination
operand is undefined::
IF SRC = 0
THEN
ZF = 1;
DEST is undefined;
ELSE
ZF = 0;
temp = 0;
WHILE Bit(SRC, temp) = 0
DO
temp = temp + 1;
DEST = temp;
OD;
FI;
:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.
"""
value = src.read()
flag = Operators.EXTRACT(value, 0, 1) == 1
res = 0
for pos in range(1, src.size):
res = Operators.ITEBV(dest.size, flag, res, pos)
flag = Operators.OR(flag, Operators.EXTRACT(value, pos, 1) == 1)
cpu.ZF = value == 0
dest.write(Operators.ITEBV(dest.size, cpu.ZF, dest.read(), res)) |
def BSR(cpu, dest, src):
"""
Bit scan reverse.
Searches the source operand (second operand) for the most significant
set bit (1 bit). If a most significant 1 bit is found, its bit index is
stored in the destination operand (first operand). The source operand
can be a register or a memory location; the destination operand is a register.
The bit index is an unsigned offset from bit 0 of the source operand.
If the contents source operand are 0, the contents of the destination
operand is undefined::
IF SRC = 0
THEN
ZF = 1;
DEST is undefined;
ELSE
ZF = 0;
temp = OperandSize - 1;
WHILE Bit(SRC, temp) = 0
DO
temp = temp - 1;
DEST = temp;
OD;
FI;
:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.
"""
value = src.read()
flag = Operators.EXTRACT(value, src.size - 1, 1) == 1
res = 0
for pos in reversed(range(0, src.size)):
res = Operators.ITEBV(dest.size, flag, res, pos)
flag = Operators.OR(flag, (Operators.EXTRACT(value, pos, 1) == 1))
cpu.PF = cpu._calculate_parity_flag(res)
cpu.ZF = value == 0
dest.write(Operators.ITEBV(dest.size, cpu.ZF, dest.read(), res)) |
def BT(cpu, dest, src):
"""
Bit Test.
Selects the bit in a bit string (specified with the first operand, called the bit base) at the
bit-position designated by the bit offset (specified by the second operand) and stores the value
of the bit in the CF flag. The bit base operand can be a register or a memory location; the bit
offset operand can be a register or an immediate value:
- If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64
of the bit offset operand (modulo size depends on the mode and register size; 64-bit operands
are available only in 64-bit mode).
- If the bit base operand specifies a memory location, the operand represents the address of the
byte in memory that contains the bit base (bit 0 of the specified byte) of the bit string. The
range of the bit position that can be referenced by the offset operand depends on the operand size.
:param cpu: current CPU.
:param dest: bit base.
:param src: bit offset.
"""
if dest.type == 'register':
cpu.CF = ((dest.read() >> (src.read() % dest.size)) & 1) != 0
elif dest.type == 'memory':
addr, pos = cpu._getMemoryBit(dest, src)
base, size, ty = cpu.get_descriptor(cpu.DS)
value = cpu.read_int(addr + base, 8)
cpu.CF = Operators.EXTRACT(value, pos, 1) == 1
else:
raise NotImplementedError(f"Unknown operand for BT: {dest.type}") |
def BTC(cpu, dest, src):
"""
Bit test and complement.
Selects the bit in a bit string (specified with the first operand, called
the bit base) at the bit-position designated by the bit offset operand
(second operand), stores the value of the bit in the CF flag, and complements
the selected bit in the bit string.
:param cpu: current CPU.
:param dest: bit base operand.
:param src: bit offset operand.
"""
if dest.type == 'register':
value = dest.read()
pos = src.read() % dest.size
cpu.CF = value & (1 << pos) == 1 << pos
dest.write(value ^ (1 << pos))
elif dest.type == 'memory':
addr, pos = cpu._getMemoryBit(dest, src)
base, size, ty = cpu.get_descriptor(cpu.DS)
addr += base
value = cpu.read_int(addr, 8)
cpu.CF = value & (1 << pos) == 1 << pos
value = value ^ (1 << pos)
cpu.write_int(addr, value, 8)
else:
raise NotImplementedError(f"Unknown operand for BTC: {dest.type}") |
def POPCNT(cpu, dest, src):
"""
This instruction calculates of number of bits set to 1 in the second
operand (source) and returns the count in the first operand (a destination
register).
Count = 0;
For (i=0; i < OperandSize; i++) {
IF (SRC[ i] = 1) // i'th bit
THEN Count++;
FI;
}
DEST = Count;
Flags Affected
OF, SF, ZF, AF, CF, PF are all cleared.
ZF is set if SRC = 0, otherwise ZF is cleared
"""
count = 0
source = src.read()
for i in range(src.size):
count += Operators.ITEBV(dest.size, (source >> i) & 1 == 1, 1, 0)
dest.write(count)
# Flags
cpu.OF = False
cpu.SF = False
cpu.AF = False
cpu.CF = False
cpu.PF = False
cpu.ZF = source == 0 |
def CMPS(cpu, dest, src):
"""
Compares string operands.
Compares the byte, word, double word or quad specified with the first source
operand with the byte, word, double or quad word specified with the second
source operand and sets the status flags in the EFLAGS register according
to the results. Both the source operands are located in memory::
temp = SRC1 - SRC2;
SetStatusFlags(temp);
IF (byte comparison)
THEN IF DF = 0
THEN
(E)SI = (E)SI + 1;
(E)DI = (E)DI + 1;
ELSE
(E)SI = (E)SI - 1;
(E)DI = (E)DI - 1;
FI;
ELSE IF (word comparison)
THEN IF DF = 0
(E)SI = (E)SI + 2;
(E)DI = (E)DI + 2;
ELSE
(E)SI = (E)SI - 2;
(E)DI = (E)DI - 2;
FI;
ELSE (* doubleword comparison*)
THEN IF DF = 0
(E)SI = (E)SI + 4;
(E)DI = (E)DI + 4;
ELSE
(E)SI = (E)SI - 4;
(E)DI = (E)DI - 4;
FI;
FI;
:param cpu: current CPU.
:param dest: first source operand.
:param src: second source operand.
"""
src_reg = {8: 'SI', 32: 'ESI', 64: 'RSI'}[cpu.address_bit_size]
dest_reg = {8: 'DI', 32: 'EDI', 64: 'RDI'}[cpu.address_bit_size]
base, _, ty = cpu.get_descriptor(cpu.DS)
src_addr = cpu.read_register(src_reg) + base
dest_addr = cpu.read_register(dest_reg) + base
size = dest.size
# Compare
arg1 = cpu.read_int(dest_addr, size)
arg0 = cpu.read_int(src_addr, size)
res = (arg0 - arg1) & ((1 << size) - 1)
cpu._calculate_CMP_flags(size, res, arg0, arg1)
#Advance EDI/ESI pointers
increment = Operators.ITEBV(cpu.address_bit_size, cpu.DF, -size // 8, size // 8)
cpu.write_register(src_reg, cpu.read_register(src_reg) + increment)
cpu.write_register(dest_reg, cpu.read_register(dest_reg) + increment) |
def LODS(cpu, dest, src):
"""
Loads string.
Loads a byte, word, or doubleword from the source operand into the AL, AX, or EAX register, respectively. The
source operand is a memory location, the address of which is read from the DS:ESI or the DS:SI registers
(depending on the address-size attribute of the instruction, 32 or 16, respectively). The DS segment may be over-
ridden with a segment override prefix.
After the byte, word, or doubleword is transferred from the memory location into the AL, AX, or EAX register, the
(E)SI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS
register. (If the DF flag is 0, the (E)SI register is incremented; if the DF flag is 1, the ESI register is decremented.)
The (E)SI register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for
doubleword operations.
:param cpu: current CPU.
:param dest: source operand.
"""
src_reg = {8: 'SI', 32: 'ESI', 64: 'RSI'}[cpu.address_bit_size]
base, _, ty = cpu.get_descriptor(cpu.DS)
src_addr = cpu.read_register(src_reg) + base
size = dest.size
arg0 = cpu.read_int(src_addr, size)
dest.write(arg0)
increment = Operators.ITEBV(cpu.address_bit_size, cpu.DF, -size // 8, size // 8)
cpu.write_register(src_reg, cpu.read_register(src_reg) + increment) |
def MOVS(cpu, dest, src):
"""
Moves data from string to string.
Moves the byte, word, or doubleword specified with the second operand (source operand) to the location specified
with the first operand (destination operand). Both the source and destination operands are located in memory. The
address of the source operand is read from the DS:ESI or the DS:SI registers (depending on the address-size
attribute of the instruction, 32 or 16, respectively). The address of the destination operand is read from the ES:EDI
or the ES:DI registers (again depending on the address-size attribute of the instruction). The DS segment may be
overridden with a segment override prefix, but the ES segment cannot be overridden.
:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.
"""
base, size, ty = cpu.get_descriptor(cpu.DS)
src_addr = src.address() + base
dest_addr = dest.address() + base
src_reg = src.mem.base
dest_reg = dest.mem.base
size = dest.size
# Copy the data
dest.write(src.read())
#Advance EDI/ESI pointers
increment = Operators.ITEBV(cpu.address_bit_size, cpu.DF, -size // 8, size // 8)
cpu.write_register(src_reg, cpu.read_register(src_reg) + increment)
cpu.write_register(dest_reg, cpu.read_register(dest_reg) + increment) |
def SCAS(cpu, dest, src):
"""
Scans String.
Compares the byte, word, or double word specified with the memory operand
with the value in the AL, AX, EAX, or RAX register, and sets the status flags
according to the results. The memory operand address is read from either
the ES:RDI, ES:EDI or the ES:DI registers (depending on the address-size
attribute of the instruction, 32 or 16, respectively)::
IF (byte comparison)
THEN
temp = AL - SRC;
SetStatusFlags(temp);
THEN IF DF = 0
THEN (E)DI = (E)DI + 1;
ELSE (E)DI = (E)DI - 1;
FI;
ELSE IF (word comparison)
THEN
temp = AX - SRC;
SetStatusFlags(temp)
THEN IF DF = 0
THEN (E)DI = (E)DI + 2;
ELSE (E)DI = (E)DI - 2;
FI;
ELSE (* doubleword comparison *)
temp = EAX - SRC;
SetStatusFlags(temp)
THEN IF DF = 0
THEN
(E)DI = (E)DI + 4;
ELSE
(E)DI = (E)DI - 4;
FI;
FI;
FI;
:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.
"""
dest_reg = dest.reg
mem_reg = src.mem.base # , src.type, src.read()
size = dest.size
arg0 = dest.read()
arg1 = src.read()
res = arg0 - arg1
cpu._calculate_CMP_flags(size, res, arg0, arg1)
increment = Operators.ITEBV(cpu.address_bit_size, cpu.DF, -size // 8, size // 8)
cpu.write_register(mem_reg, cpu.read_register(mem_reg) + increment) |
def STOS(cpu, dest, src):
"""
Stores String.
Stores a byte, word, or doubleword from the AL, AX, or EAX register,
respectively, into the destination operand. The destination operand is
a memory location, the address of which is read from either the ES:EDI
or the ES:DI registers (depending on the address-size attribute of the
instruction, 32 or 16, respectively). The ES segment cannot be overridden
with a segment override prefix.
:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.
"""
size = src.size
dest.write(src.read())
dest_reg = dest.mem.base
increment = Operators.ITEBV({'RDI': 64, 'EDI': 32, 'DI': 16}[dest_reg], cpu.DF, -size // 8, size // 8)
cpu.write_register(dest_reg, cpu.read_register(dest_reg) + increment) |
def ANDN(cpu, dest, src1, src2):
"""Performs a bitwise logical AND of inverted second operand (the first source operand)
with the third operand (the second source operand). The result is stored in the first
operand (destination operand).
DEST <- (NOT SRC1) bitwiseAND SRC2;
SF <- DEST[OperandSize -1];
ZF <- (DEST = 0);
Flags Affected
SF and ZF are updated based on result. OF and CF flags are cleared. AF and PF flags are undefined.
"""
value = ~src1.read() & src2.read()
dest.write(value)
cpu.ZF = value == 0
cpu.SF = (value & (1 << dest.size)) != 0
cpu.OF = False
cpu.CF = False |
def SHLX(cpu, dest, src, count):
"""
The shift arithmetic left.
Shifts the bits in the first operand (destination operand) to the left or right by the number of bits specified in the
second operand (count operand). Bits shifted beyond the destination operand boundary are first shifted into the CF
flag, then discarded. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination
operand.
:param cpu: current CPU.
:param dest: destination operand.
:param src: count operand.
"""
OperandSize = dest.size
count = count.read()
countMask = {8: 0x1f,
16: 0x1f,
32: 0x1f,
64: 0x3f}[OperandSize]
tempCount = Operators.ZEXTEND(count & countMask, dest.size)
tempDest = value = src.read()
res = dest.write(Operators.ITEBV(dest.size, tempCount == 0, tempDest, value << tempCount)) |
def SARX(cpu, dest, src, count):
"""
The shift arithmetic right.
:param cpu: current CPU.
:param dest: destination operand.
:param src: count operand.
"""
OperandSize = dest.size
count = count.read()
countMask = {8: 0x1f,
16: 0x1f,
32: 0x1f,
64: 0x3f}[OperandSize]
tempCount = count & countMask
tempDest = value = src.read()
sign = value & (1 << (OperandSize - 1))
while tempCount != 0:
cpu.CF = (value & 0x1) != 0 # LSB
value = (value >> 1) | sign
tempCount = tempCount - 1
res = dest.write(value) |
def PMINUB(cpu, dest, src):
"""
PMINUB: returns minimum of packed unsigned byte integers in the dest operand
see PMAXUB
"""
dest_value = dest.read()
src_value = src.read()
result = 0
for pos in range(0, dest.size, 8):
itema = (dest_value >> pos) & 0xff
itemb = (src_value >> pos) & 0xff
result |= Operators.ITEBV(dest.size, itema < itemb, itema, itemb) << pos
dest.write(result) |
def PXOR(cpu, dest, src):
"""
Logical exclusive OR.
Performs a bitwise logical exclusive-OR (XOR) operation on the quadword
source (second) and destination (first) operands and stores the result
in the destination operand location. The source operand can be an MMX(TM)
technology register or a quadword memory location; the destination operand
must be an MMX register. Each bit of the result is 1 if the corresponding
bits of the two operands are different; each bit is 0 if the corresponding
bits of the operands are the same::
DEST = DEST XOR SRC;
:param cpu: current CPU.
:param dest: destination operand.
:param src: quadword source operand.
"""
res = dest.write(dest.read() ^ src.read()) |
def _PUNPCKL(cpu, dest, src, item_size):
"""
Generic PUNPCKL
"""
assert dest.size == src.size
size = dest.size
dest_value = dest.read()
src_value = src.read()
mask = (1 << item_size) - 1
res = 0
count = 0
for pos in range(0, size // item_size):
if count >= size:
break
item0 = Operators.ZEXTEND((dest_value >> (pos * item_size)) & mask, size)
item1 = Operators.ZEXTEND((src_value >> (pos * item_size)) & mask, size)
res |= item0 << count
count += item_size
res |= item1 << count
count += item_size
dest.write(res) |
def PSHUFW(cpu, op0, op1, op3):
"""
Packed shuffle words.
Copies doublewords from source operand (second operand) and inserts them in the destination operand
(first operand) at locations selected with the order operand (third operand).
:param cpu: current CPU.
:param op0: destination operand.
:param op1: source operand.
:param op3: order operand.
"""
size = op0.size
arg0 = op0.read()
arg1 = op1.read()
arg3 = Operators.ZEXTEND(op3.read(), size)
assert size == 64
arg0 |= ((arg1 >> ((arg3 >> 0) & 3 * 16)) & 0xffff)
arg0 |= ((arg1 >> ((arg3 >> 2) & 3 * 16)) & 0xffff) << 16
arg0 |= ((arg1 >> ((arg3 >> 4) & 3 * 16)) & 0xffff) << 32
arg0 |= ((arg1 >> ((arg3 >> 6) & 3 * 16)) & 0xffff) << 48
op0.write(arg0) |
def PSHUFD(cpu, op0, op1, op3):
"""
Packed shuffle doublewords.
Copies doublewords from source operand (second operand) and inserts them in the destination operand
(first operand) at locations selected with the order operand (third operand).
:param cpu: current CPU.
:param op0: destination operand.
:param op1: source operand.
:param op3: order operand.
"""
size = op0.size
arg0 = op0.read()
arg1 = op1.read()
order = Operators.ZEXTEND(op3.read(), size)
arg0 = arg0 & 0xffffffffffffffffffffffffffffffff00000000000000000000000000000000
arg0 |= ((arg1 >> (((order >> 0) & 3) * 32)) & 0xffffffff)
arg0 |= ((arg1 >> (((order >> 2) & 3) * 32)) & 0xffffffff) << 32
arg0 |= ((arg1 >> (((order >> 4) & 3) * 32)) & 0xffffffff) << 64
arg0 |= ((arg1 >> (((order >> 6) & 3) * 32)) & 0xffffffff) << 96
op0.write(arg0) |
def PMOVMSKB(cpu, op0, op1):
"""
Moves byte mask to general-purpose register.
Creates an 8-bit mask made up of the most significant bit of each byte of the source operand
(second operand) and stores the result in the low byte or word of the destination operand
(first operand). The source operand is an MMX(TM) technology or an XXM register; the destination
operand is a general-purpose register.
:param cpu: current CPU.
:param op0: destination operand.
:param op1: source operand.
"""
arg0 = op0.read()
arg1 = op1.read()
res = 0
for i in reversed(range(7, op1.size, 8)):
res = (res << 1) | ((arg1 >> i) & 1)
op0.write(Operators.EXTRACT(res, 0, op0.size)) |
def PSRLDQ(cpu, dest, src):
"""
Packed shift right logical double quadword.
Shifts the destination operand (first operand) to the right by the number
of bytes specified in the count operand (second operand). The empty high-order
bytes are cleared (set to all 0s). If the value specified by the count
operand is greater than 15, the destination operand is set to all 0s.
The destination operand is an XMM register. The count operand is an 8-bit
immediate::
TEMP = SRC;
if (TEMP > 15) TEMP = 16;
DEST = DEST >> (temp * 8);
:param cpu: current CPU.
:param dest: destination operand.
:param src: count operand.
"""
# TODO(yan): Verify the correctness of truncating SRC like this ( tests
# use '-1' as the value
temp = Operators.EXTRACT(src.read(), 0, 8)
temp = Operators.ITEBV(src.size, temp > 15, 16, temp)
dest.write(dest.read() >> (temp * 8)) |
def MOVZX(cpu, op0, op1):
"""
Moves with zero-extend.
Copies the contents of the source operand (register or memory location) to the destination
operand (register) and zero extends the value to 16 or 32 bits. The size of the converted value
depends on the operand-size attribute::
OP0 = ZeroExtend(OP1);
:param cpu: current CPU.
:param op0: destination operand.
:param op1: source operand.
"""
op0.write(Operators.ZEXTEND(op1.read(), op0.size)) |
def MOVSX(cpu, op0, op1):
"""
Moves with sign-extension.
Copies the contents of the source operand (register or memory location) to the destination
operand (register) and sign extends the value to 16::
OP0 = SignExtend(OP1);
:param cpu: current CPU.
:param op0: destination operand.
:param op1: source operand.
"""
op0.write(Operators.SEXTEND(op1.read(), op1.size, op0.size)) |
def CQO(cpu):
"""
RDX:RAX = sign-extend of RAX.
"""
res = Operators.SEXTEND(cpu.RAX, 64, 128)
cpu.RAX = Operators.EXTRACT(res, 0, 64)
cpu.RDX = Operators.EXTRACT(res, 64, 64) |
def CDQ(cpu):
"""
EDX:EAX = sign-extend of EAX
"""
cpu.EDX = Operators.EXTRACT(Operators.SEXTEND(cpu.EAX, 32, 64), 32, 32) |
def CWDE(cpu):
"""
Converts word to doubleword.
::
DX = sign-extend of AX.
:param cpu: current CPU.
"""
bit = Operators.EXTRACT(cpu.AX, 15, 1)
cpu.EAX = Operators.SEXTEND(cpu.AX, 16, 32)
cpu.EDX = Operators.SEXTEND(bit, 1, 32) |
def RDTSC(cpu):
"""
Reads time-stamp counter.
Loads the current value of the processor's time-stamp counter into the
EDX:EAX registers. The time-stamp counter is contained in a 64-bit
MSR. The high-order 32 bits of the MSR are loaded into the EDX
register, and the low-order 32 bits are loaded into the EAX register.
The processor increments the time-stamp counter MSR every clock cycle
and resets it to 0 whenever the processor is reset.
:param cpu: current CPU.
"""
val = cpu.icount
cpu.RAX = val & 0xffffffff
cpu.RDX = (val >> 32) & 0xffffffff |
def SYSCALL(cpu):
"""
Calls to interrupt procedure.
The INT n instruction generates a call to the interrupt or exception handler specified
with the destination operand. The INT n instruction is the general mnemonic for executing
a software-generated call to an interrupt handler. The INTO instruction is a special
mnemonic for calling overflow exception (#OF), interrupt vector number 4. The overflow
interrupt checks the OF flag in the EFLAGS register and calls the overflow interrupt handler
if the OF flag is set to 1.
:param cpu: current CPU.
"""
cpu.RCX = cpu.RIP
cpu.R11 = cpu.RFLAGS
raise Syscall() |
def MOVLPD(cpu, dest, src):
"""
Moves low packed double-precision floating-point value.
Moves a double-precision floating-point value from the source operand (second operand) and the
destination operand (first operand). The source and destination operands can be an XMM register
or a 64-bit memory location. This instruction allows double-precision floating-point values to be moved
to and from the low quadword of an XMM register and memory. It cannot be used for register to register
or memory to memory moves. When the destination operand is an XMM register, the high quadword of the
register remains unchanged.
:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.
"""
value = src.read()
if src.size == 64 and dest.size == 128:
value = (dest.read() & 0xffffffffffffffff0000000000000000) | Operators.ZEXTEND(value, 128)
dest.write(value) |
def MOVHPD(cpu, dest, src):
"""
Moves high packed double-precision floating-point value.
Moves a double-precision floating-point value from the source operand (second operand) and the
destination operand (first operand). The source and destination operands can be an XMM register
or a 64-bit memory location. This instruction allows double-precision floating-point values to be moved
to and from the high quadword of an XMM register and memory. It cannot be used for register to
register or memory to memory moves. When the destination operand is an XMM register, the low quadword
of the register remains unchanged.
:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.
"""
if src.size == 128:
assert dest.size == 64
dest.write(Operators.EXTRACT(src.read(), 64, 64))
else:
assert src.size == 64 and dest.size == 128
value = Operators.EXTRACT(dest.read(), 0, 64) # low part
dest.write(Operators.CONCAT(128, src.read(), value)) |
def PSUBB(cpu, dest, src):
"""
Packed subtract.
Performs a SIMD subtract of the packed integers of the source operand (second operand) from the packed
integers of the destination operand (first operand), and stores the packed integer results in the
destination operand. The source operand can be an MMX(TM) technology register or a 64-bit memory location,
or it can be an XMM register or a 128-bit memory location. The destination operand can be an MMX or an XMM
register.
The PSUBB instruction subtracts packed byte integers. When an individual result is too large or too small
to be represented in a byte, the result is wrapped around and the low 8 bits are written to the
destination element.
:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.
"""
result = []
value_a = dest.read()
value_b = src.read()
for i in reversed(range(0, dest.size, 8)):
a = Operators.EXTRACT(value_a, i, 8)
b = Operators.EXTRACT(value_b, i, 8)
result.append((a - b) & 0xff)
dest.write(Operators.CONCAT(8 * len(result), *result)) |
def POR(cpu, dest, src):
"""
Performs a bitwise logical OR operation on the source operand (second operand) and the destination operand
(first operand) and stores the result in the destination operand. The source operand can be an MMX technology
register or a 64-bit memory location or it can be an XMM register or a 128-bit memory location. The destination
operand can be an MMX technology register or an XMM register. Each bit of the result is set to 1 if either
or both of the corresponding bits of the first and second operands are 1; otherwise, it is set to 0.
"""
res = dest.write(dest.read() | src.read()) |
def XORPS(cpu, dest, src):
"""
Performs a bitwise logical OR operation on the source operand (second operand) and the destination operand
(first operand) and stores the result in the destination operand. The source operand can be an MMX technology
register or a 64-bit memory location or it can be an XMM register or a 128-bit memory location. The destination
operand can be an MMX technology register or an XMM register. Each bit of the result is set to 1 if either
or both of the corresponding bits of the first and second operands are 1; otherwise, it is set to 0.
"""
res = dest.write(dest.read() ^ src.read()) |
def VORPD(cpu, dest, src, src2):
"""
Performs a bitwise logical OR operation on the source operand (second operand) and second source operand (third operand)
and stores the result in the destination operand (first operand).
"""
res = dest.write(src.read() | src2.read()) |
def VORPS(cpu, dest, src, src2):
"""
Performs a bitwise logical OR operation on the source operand (second operand) and second source operand (third operand)
and stores the result in the destination operand (first operand).
"""
res = dest.write(src.read() | src2.read()) |
def PTEST(cpu, dest, src):
""" PTEST
PTEST set the ZF flag if all bits in the result are 0 of the bitwise AND
of the first source operand (first operand) and the second source operand
(second operand). Also this sets the CF flag if all bits in the result
are 0 of the bitwise AND of the second source operand (second operand)
and the logical NOT of the destination operand.
"""
cpu.OF = False
cpu.AF = False
cpu.PF = False
cpu.SF = False
cpu.ZF = (Operators.EXTRACT(dest.read(), 0, 128) & Operators.EXTRACT(src.read(), 0, 128)) == 0
cpu.CF = (Operators.EXTRACT(src.read(), 0, 128) & ~(Operators.EXTRACT(dest.read(), 0, 128))) == 0 |
def MOVQ(cpu, dest, src):
"""
Move quadword.
Copies a quadword from the source operand (second operand) to the destination operand (first operand).
The source and destination operands can be MMX(TM) technology registers, XMM registers, or 64-bit memory
locations. This instruction can be used to move a between two MMX registers or between an MMX register
and a 64-bit memory location, or to move data between two XMM registers or between an XMM register and
a 64-bit memory location. The instruction cannot be used to transfer data between memory locations.
When the source operand is an XMM register, the low quadword is moved; when the destination operand is
an XMM register, the quadword is stored to the low quadword of the register, and the high quadword is
cleared to all 0s::
MOVQ instruction when operating on MMX registers and memory locations:
DEST = SRC;
MOVQ instruction when source and destination operands are XMM registers:
DEST[63-0] = SRC[63-0];
MOVQ instruction when source operand is XMM register and destination operand is memory location:
DEST = SRC[63-0];
MOVQ instruction when source operand is memory location and destination operand is XMM register:
DEST[63-0] = SRC;
DEST[127-64] = 0000000000000000H;
:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.
"""
# mmx to mmx or mmx to mem
if dest.size == src.size and dest.size == 64:
dest.write(src.read())
# two xmm regs
elif dest.size == src.size and dest.size == 128:
src_lo = Operators.EXTRACT(src.read(), 0, 64)
dest.write(Operators.ZEXTEND(src_lo, 128))
# mem to xmm
elif dest.size == 128 and src.size == 64:
dest.write(Operators.ZEXTEND(src.read(), dest.size))
# xmm to mem
elif dest.size == 64 and src.size == 128:
dest.write(Operators.EXTRACT(src.read(), 0, dest.size))
else:
msg = 'Invalid size in MOVQ'
logger.error(msg)
raise Exception(msg) |
def MOVSD(cpu, dest, src):
"""
Move Scalar Double-Precision Floating-Point Value
Moves a scalar double-precision floating-point value from the source
operand (second operand) to the destination operand (first operand).
The source and destination operands can be XMM registers or 64-bit memory
locations. This instruction can be used to move a double-precision
floating-point value to and from the low quadword of an XMM register and
a 64-bit memory location, or to move a double-precision floating-point
value between the low quadwords of two XMM registers. The instruction
cannot be used to transfer data between memory locations.
When the source and destination operands are XMM registers, the high
quadword of the destination operand remains unchanged. When the source
operand is a memory location and destination operand is an XMM registers,
the high quadword of the destination operand is cleared to all 0s.
:param cpu: current CPU.
:param dest: destination operand.
:param src: source operand.
"""
assert dest.type != 'memory' or src.type != 'memory'
value = Operators.EXTRACT(src.read(), 0, 64)
if dest.size > src.size:
value = Operators.ZEXTEND(value, dest.size)
dest.write(value) |
def MOVSS(cpu, dest, src):
"""
Moves a scalar single-precision floating-point value
Moves a scalar single-precision floating-point value from the source operand (second operand)
to the destination operand (first operand). The source and destination operands can be XMM
registers or 32-bit memory locations. This instruction can be used to move a single-precision
floating-point value to and from the low doubleword of an XMM register and a 32-bit memory
location, or to move a single-precision floating-point value between the low doublewords of
two XMM registers. The instruction cannot be used to transfer data between memory locations.
When the source and destination operands are XMM registers, the three high-order doublewords of the
destination operand remain unchanged. When the source operand is a memory location and destination
operand is an XMM registers, the three high-order doublewords of the destination operand are cleared to all 0s.
//MOVSS instruction when source and destination operands are XMM registers:
if(IsXMM(Source) && IsXMM(Destination))
Destination[0..31] = Source[0..31];
//Destination[32..127] remains unchanged
//MOVSS instruction when source operand is XMM register and destination operand is memory location:
else if(IsXMM(Source) && IsMemory(Destination))
Destination = Source[0..31];
//MOVSS instruction when source operand is memory location and destination operand is XMM register:
else {
Destination[0..31] = Source;
Destination[32..127] = 0;
}
"""
if dest.type == 'register' and src.type == 'register':
assert dest.size == 128 and src.size == 128
dest.write(dest.read() & ~0xffffffff | src.read() & 0xffffffff)
elif dest.type == 'memory':
assert src.type == 'register'
dest.write(Operators.EXTRACT(src.read(), 0, dest.size))
else:
assert src.type == 'memory' and dest.type == 'register'
assert src.size == 32 and dest.size == 128
dest.write(Operators.ZEXTEND(src.read(), 128)) |
def VEXTRACTF128(cpu, dest, src, offset):
"""Extract Packed Floating-Point Values
Extracts 128-bits of packed floating-point values from the source
operand (second operand) at an 128-bit offset from imm8[0] into the
destination operand (first operand). The destination may be either an
XMM register or an 128-bit memory location.
"""
offset = offset.read()
dest.write(Operators.EXTRACT(src.read(), offset * 128, (offset + 1) * 128)) |
def PALIGNR(cpu, dest, src, offset):
"""ALIGNR concatenates the destination operand (the first operand) and the source
operand (the second operand) into an intermediate composite, shifts the composite
at byte granularity to the right by a constant immediate, and extracts the right-
aligned result into the destination."""
dest.write(
Operators.EXTRACT(
Operators.CONCAT(dest.size * 2, dest.read(), src.read()),
offset.read() * 8,
dest.size)) |
def PSLLDQ(cpu, dest, src):
""" Packed Shift Left Logical Double Quadword
Shifts the destination operand (first operand) to the left by the number
of bytes specified in the count operand (second operand). The empty low-order
bytes are cleared (set to all 0s). If the value specified by the count
operand is greater than 15, the destination operand is set to all 0s.
The destination operand is an XMM register. The count operand is an 8-bit
immediate.
TEMP = COUNT;
if (TEMP > 15) TEMP = 16;
DEST = DEST << (TEMP * 8);
"""
count = Operators.ZEXTEND(src.read(), dest.size * 2)
byte_count = Operators.ITEBV(src.size * 2, count > 15, 16, count)
bit_count = byte_count * 8
val = Operators.ZEXTEND(dest.read(), dest.size * 2)
val = val << (Operators.ZEXTEND(bit_count, dest.size * 2))
dest.write(Operators.EXTRACT(val, 0, dest.size)) |
def PSRLQ(cpu, dest, src):
"""Shift Packed Data Right Logical
Shifts the bits in the individual quadword in the destination operand to the right by
the number of bits specified in the count operand . As the bits in the data elements
are shifted right, the empty high-order bits are cleared (set to 0). If the value
specified by the count operand is greater than 63, then the destination operand is set
to all 0s.
if(OperandSize == 64) {
//PSRLQ instruction with 64-bit operand:
if(Count > 63) Destination[64..0] = 0;
else Destination = ZeroExtend(Destination >> Count);
}
else {
//PSRLQ instruction with 128-bit operand:
if(Count > 15) Destination[128..0] = 0;
else {
Destination[0..63] = ZeroExtend(Destination[0..63] >> Count);
Destination[64..127] = ZeroExtend(Destination[64..127] >> Count);
}
}
"""
count = src.read()
count = Operators.ITEBV(src.size, Operators.UGT(count, 63), 64, count)
count = Operators.EXTRACT(count, 0, 64)
if dest.size == 64:
dest.write(dest.read() >> count)
else:
hi = Operators.EXTRACT(dest.read(), 64, 64) >> count
low = Operators.EXTRACT(dest.read(), 0, 64) >> count
dest.write(Operators.CONCAT(128, hi, low)) |
def VPSHUFB(cpu, op0, op1, op3):
"""
Packed shuffle bytes.
Copies bytes from source operand (second operand) and inserts them in the destination operand
(first operand) at locations selected with the order operand (third operand).
:param cpu: current CPU.
:param op0: destination operand.
:param op1: source operand.
:param op3: order operand.
"""
size = op0.size
arg0 = op0.read()
arg1 = op1.read()
arg3 = Operators.ZEXTEND(op3.read(), size)
arg0 |= Operators.ITEBV(size, Operators.EXTRACT(arg3, 7, 1) == 1, 0, (arg1 >> ((arg3 >> 0) & 7 * 8)) & 0xff)
arg0 |= Operators.ITEBV(size, Operators.EXTRACT(arg3, 15, 1) == 1, 0, ((arg1 >> ((arg3 >> 8) & 7 * 8)) & 0xff) << 8)
arg0 |= Operators.ITEBV(size, Operators.EXTRACT(arg3, 23, 1) == 1, 0, ((arg1 >> ((arg3 >> 16) & 7 * 8)) & 0xff) << 16)
arg0 |= Operators.ITEBV(size, Operators.EXTRACT(arg3, 31, 1) == 1, 0, ((arg1 >> ((arg3 >> 24) & 7 * 8)) & 0xff) << 24)
arg0 |= Operators.ITEBV(size, Operators.EXTRACT(arg3, 39, 1) == 1, 0, ((arg1 >> ((arg3 >> 32) & 7 * 8)) & 0xff) << 32)
arg0 |= Operators.ITEBV(size, Operators.EXTRACT(arg3, 47, 1) == 1, 0, ((arg1 >> ((arg3 >> 40) & 7 * 8)) & 0xff) << 40)
arg0 |= Operators.ITEBV(size, Operators.EXTRACT(arg3, 55, 1) == 1, 0, ((arg1 >> ((arg3 >> 48) & 7 * 8)) & 0xff) << 48)
arg0 |= Operators.ITEBV(size, Operators.EXTRACT(arg3, 63, 1) == 1, 0, ((arg1 >> ((arg3 >> 56) & 7 * 8)) & 0xff) << 56)
arg0 |= Operators.ITEBV(size, Operators.EXTRACT(arg3, 71, 1) == 1, 0, ((arg1 >> ((arg3 >> 64) & 7 * 8)) & 0xff) << 64)
arg0 |= Operators.ITEBV(size, Operators.EXTRACT(arg3, 79, 1) == 1, 0, ((arg1 >> ((arg3 >> 72) & 7 * 8)) & 0xff) << 72)
arg0 |= Operators.ITEBV(size, Operators.EXTRACT(arg3, 87, 1) == 1, 0, ((arg1 >> ((arg3 >> 80) & 7 * 8)) & 0xff) << 80)
arg0 |= Operators.ITEBV(size, Operators.EXTRACT(arg3, 95, 1) == 1, 0, ((arg1 >> ((arg3 >> 88) & 7 * 8)) & 0xff) << 88)
arg0 |= Operators.ITEBV(size, Operators.EXTRACT(arg3, 103, 1) == 1, 0, ((arg1 >> ((arg3 >> 96) & 7 * 8)) & 0xff) << 96)
arg0 |= Operators.ITEBV(size, Operators.EXTRACT(arg3, 111, 1) == 1, 0, ((arg1 >> ((arg3 >> 104) & 7 * 8)) & 0xff) << 104)
arg0 |= Operators.ITEBV(size, Operators.EXTRACT(arg3, 119, 1) == 1, 0, ((arg1 >> ((arg3 >> 112) & 7 * 8)) & 0xff) << 112)
arg0 |= Operators.ITEBV(size, Operators.EXTRACT(arg3, 127, 1) == 1, 0, ((arg1 >> ((arg3 >> 120) & 7 * 8)) & 0xff) << 120)
op0.write(arg0) |
def XLATB(cpu):
"""
Table look-up translation.
Locates a byte entry in a table in memory, using the contents of the
AL register as a table index, then copies the contents of the table entry
back into the AL register. The index in the AL register is treated as
an unsigned integer. The XLAT and XLATB instructions get the base address
of the table in memory from either the DS:EBX or the DS:BX registers.
In 64-bit mode, operation is similar to that in legacy or compatibility mode.
AL is used to specify the table index (the operand size is fixed at 8 bits).
RBX, however, is used to specify the table's base address::
IF address_bit_size = 16
THEN
AL = (DS:BX + ZeroExtend(AL));
ELSE IF (address_bit_size = 32)
AL = (DS:EBX + ZeroExtend(AL)); FI;
ELSE (address_bit_size = 64)
AL = (RBX + ZeroExtend(AL));
FI;
:param cpu: current CPU.
:param dest: destination operand.
"""
cpu.AL = cpu.read_int(cpu.RBX + Operators.ZEXTEND(cpu.AL, 64), 8) |
def XLATB(cpu):
"""
Table look-up translation.
Locates a byte entry in a table in memory, using the contents of the
AL register as a table index, then copies the contents of the table entry
back into the AL register. The index in the AL register is treated as
an unsigned integer. The XLAT and XLATB instructions get the base address
of the table in memory from either the DS:EBX or the DS:BX registers.
In 64-bit mode, operation is similar to that in legacy or compatibility mode.
AL is used to specify the table index (the operand size is fixed at 8 bits).
RBX, however, is used to specify the table's base address::
IF address_bit_size = 16
THEN
AL = (DS:BX + ZeroExtend(AL));
ELSE IF (address_bit_size = 32)
AL = (DS:EBX + ZeroExtend(AL)); FI;
ELSE (address_bit_size = 64)
AL = (RBX + ZeroExtend(AL));
FI;
:param cpu: current CPU.
:param dest: destination operand.
"""
cpu.AL = cpu.read_int(cpu.EBX + Operators.ZEXTEND(cpu.AL, 32), 8) |
def constrain(self, constraint):
"""Constrain state.
:param manticore.core.smtlib.Bool constraint: Constraint to add
"""
constraint = self.migrate_expression(constraint)
self._constraints.add(constraint) |
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