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H: Signal becomes undefined when used in process
I'm having problems with this VHDL code where the value of new_state isn't being transferred onto the signal state_cnt and is instead becoming undefined.
What do I need to change in-order to get this to work?
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
entity test_controller is
port (
clk, reset, wr : in std_logic;
wr_data : in std_logic_vector(31 downto 0)
op_a, op_b, op_c : out std_logic_vector(31 downto 0)
);
end test_controller;
architecture rtl of test_controller is
signal busy : std_logic := '0';
signal state_cnt : std_logic_vector(1 downto 0) := "00";
begin
input_proc : process(wr)
variable new_state : integer;
begin
if rising_edge(wr) then
if busy = '0' then
if state_cnt = "00" then
op_a <= wr_data;
new_state := 1;
elsif state_cnt = "01" then
op_b <= wr_data;
new_state := 2;
elsif state_cnt = "10" then
op_c <= wr_data;
busy <= '1';
new_state := 0;
end if;
state_cnt <= conv_std_logic_vector(new_state,2);
end if;
end if;
end process;
end rtl;
Testbench
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
entity tb_test_controller is
end tb_test_controller;
architecture exercise of tb_test_controller is
component test_controller
port (
clk, reset, wr : in std_logic;
wr_data : in std_logic_vector(31 downto 0);
op_a, op_b, op_c : out std_logic_vector(31 downto 0)
);
end component;
signal clk_i : std_logic;
signal reset_i : std_logic;
signal wrdata_i : std_logic_vector(31 downto 0);
signal op_a_i : std_logic_vector(31 downto 0);
signal op_b_i : std_logic_vector(31 downto 0);
signal op_c_i : std_logic_vector(31 downto 0);
signal wr_i : std_logic;
constant CLK_PERIOD : time := 20 ns;
constant DLY : time := CLK_PERIOD*2;
begin
clkmeProc : process
begin
clk_i <= '1';
wait for CLK_PERIOD/2;
clk_i <= '0';
wait for CLK_PERIOD/2;
end process;
resetmeProc : process
begin
wait for DLY;
reset_i <= '1';
wait for CLK_PERIOD;
reset_i <= '0';
wait;
end process;
inputDataProc : process
begin
wait on reset_i until reset_i = '0';
for i in 0 to 10 loop
wrdata_i <= conv_std_logic_vector(i, 32);
wr_i <= '1';
wait for CLK_PERIOD;
wr_i <= '0';
wait for CLK_PERIOD;
end loop;
end process;
DUT : test_controller
port map
(
clk =>clk_i,
reset => reset_i,
wr_data => wrdata_i,
wr => wr_i,
op_a => op_a_i,
op_b => op_b_i,
op_c => op_c_i
);
stimProc : process
begin
wait;
end process;
end exercise;
AI: You're code wasn't quite complete missing the mode out port declarations for op_a, op_b and op_c from entity test_controller.
Apparently using a different simulator and after correcting the discrepancy in your code I get a different answer.
You don't have any tags or real clues whose tool you are using. Your waveform doesn't match the (corrected) code you have posted (and VHDL is supposed to be portable).
The only thing I see wrong here is that your testbench ought to provide a default value forwr_i of '0'. The rising_edge function won't see the transition from 'U' to '1' as a rising edge.
This sort of says you're having tool problems (I trust this VHDL implementation here).
Please provide more information on the tool you're are using and provide waveforms that match your actual code you provide.
In the mean time you might see if Paebbel's change does simulate correctly.
Notice you don't have anything that assigns the value of busy back to a '0'. |
H: What is the real every moment exact situation of an a.c source?
in advance of every discussion, i want to say thanks to this great scientific website that i'm recently getting to know it more and more and i'm really happy with.
sometimes i get stuck with really dumb inquiries of my mind! i'm beginner to electronics though. last day, i was reviewing this simple full-wave-bridge-rectifier, almost for the ninth, or the tenth time in my life, and fortunately, i really have no problem with the operation, i understand it all, but...
but while looking at it, some other question(weird.Q!) sparkled that is this:
when the source is in the positive peak of its signal, and obviously D1 and D2 are forward biased and are conducting, what is the amount of the negative end of the source?!
are the two ends symmetric in their values? e.g. 2V and -2V? so... if yes..., then why we're showing the source voltage in that moment by that positive amount in the figure at all?
or what...?
definitely(or probably...!) it shouldn't have the ground value as well, since the D2 and the D3 are conducting in every half-cycle!
well what is my silly misunderstanding please...!?!?
thank you again ;_)
AI: When D2 is conducting, its anode is at GND (0V), and therefore its cathode will be 0.7 V below this, or -0.7 V.
Same situation when D3 conducts -- at that time, the end of the source connected to it is -0.7 V.
When D1 (or D4) is conducting, the end of the source is VOUT + 0.7 V, so the total voltage at the source is VOUT + 2*0.7 V |
H: Is this sufficient filtering for an mcu?
I'm a software engineering student and an electronics hobbyist, and I am currently designing a circuit using a 80Mhz pic32. I wondering if the noise filtering that I have is acceptable and if it could be improved.
The data sheet says that you can optionally have an inductor(ferrite bead?) between the Vdd and AVdd, would this be a good idea? I will be using the adc for measuring temperatures.
AI: "optionally have an inductor . . or ferrite bead" Sounds like the voice of experience in their recommendation.
Make sure you add bypass capacitors on the Analog side of the ferite bead, or the bead won't help. The ferrite bead acts as a high frequency resistor. The higher the frequency the higher the resistance. But doesn't interfere with your supplying the DC required for the Analog supply.
EDIT : I just noticed your 10K resistor from Digital supply to Analog Supply. Using a resistor there is not a good idea, unless you have some reason for the resistor. A resistor will drop voltage at DC (supply to your Analog). A ferrite bead won't cause voltage drop at DC (which is good). |
H: A question on Thevenin and output impedance
Above figure shows the transformation of a circuit to its Thevenin equivalent. Imagine this is a power supply and A is the + terminal.
In reality the real circuit model is the one on the left side and just before the A terminal I circled the resistance with red color.
On the right side is its Thevenin equivalent and the Thevenin resistance is circled with green color.
I have the following questions:
1-) When one talks about the "output impedance" of this power supply, would you understand the red or green circled resistor?
2-) Lets say you don't know what lies inside the black box. You can measure the Thevenin voltage across A and B terminals by a voltmeter. But is it also possible to quantify the Thevenin resistance Rth(for example by shorting A and B)?
AI: The green circled one represents the output impedance of the whole circuit. the red one is a component of it, but not all.
In theory you could measure the Thevenin resistance by shorting the supply, but if this were a real supply, it would likely protect itself (short circuit protection), and you wouldn't get the correct answer. Even if it didn't protect itself, if it has any nonlinear or active components (opamps, diodes, transistors etc.), the behavior of these devices when shorted might be significantly different (in a non-linear way) from the lightly loaded behavior and so you wouldn't get a good result.
Best approach is to put a light load (say full scale load) on the supply and measure the change in output voltage -- now Rth is deltaVOUT/ILOAD |
H: Shift Registers - How does one pronounce QH'
In the datasheet for the 74HC595 shift register, pin 9 is labeled "QH'" (not to be confused with pin 7, labeled "QH" without the "'"). I understand that this pin outputs the current contents of the register as new data is shifted in for the purpose of daisy-chaining registers, but...
What I'm not sure of is, what would a professional engineer call this pin in verbal conversation with another engineer? Maybe "Dump pin?", or "Exit strategy?", or maybe "Que Aych Huzzahh!" Probably none of the above, which is why I'm asking.
Thanks.
AI: It's basically doing the function of "Serial Out", so you could call it that.
As written it would be "Q" "H" "prime". The ' is likely the prime symbol, something used for many different things, but in logic diagrams it typically indicates that something is a from a different state, or next clock cycle, or as the Wiki article puts it:
x′ generally means something related to or derived from x |
H: Why is the input pin to my multiplexer considered a capacitive load?
I am currently using CD74HC4067 multiplexer in my design.
I had trouble with my input signal and therefore conducted an experiment by measuring the input resistance of my multiplexer as the frequency increases. I noticed that as the frequency is increased from 1 KHz to a final value of 8 MHz that the input resistance decreases with the increase in frequency. I am guessing that therefore this is a capacitive load because impedance = 1/(jwc) where w is the frequency. But why would the input pin be capacitive as opposed to purely resistive for an input pin?
AI: Your mux is CMOS; MOS gates have capacitance [by design]... and a lot of other parasitic ones. But even with BJTs you have parasitic capacitance.
Here's what CMOS analog switch (as would be used in a multiplexer) typically looks like
Image from this book.
Every MOSFET has [parasitic] capacitance between everything and everything basically, so there is a capacitive path from an analog input to... well anything. I'm not actually sure relative to what you've measured it (output, ground?), but doesn't really matter, because some capacitance exists relative to any of these.
In particular all MOSFETs in a CMOS will have capacitance via the bulk substrate:
Someone more versed than me in IC design can probably guess how you've measured it based on the result you've got. |
H: Can I charge a 3.7v Lion with a 4.2v Lipoly charger?
I have some 3.7v (when fully charged) lion batteries that I would like to repurpose. All I have to charge these is a few chargers for some 4.2v lipo (when fully charged) batteries. The specific charger is here. It puts out 100 mA. Would this difference in voltage result in the harming of either my charger or the battery, or would it be safe?
Thanks for your help.
AI: 3.7V is the nominal voltage of the cell. As long as the maximum voltage for the cell is 4.2V or higher and the charge current is equal to or less than the amount recommended in the datasheet (usually 0.8C or less is safe) then you can charge the cell with the charger. |
H: How do I find the power of this circuit?
This is a circuit from one of my texts:
according to the text power in I1 = -12 watts, R1 = +40 watts and V1 = -28 watts.
My take on the circuit:
I'm assuming since current from the current source is flowing into R1 I can just do P=I2/R to get the power at R1 and for the power at V1 I do P=I*V but I don't get how to find I1 without taking power at V1 and subtracting power at R1. Is that the only way to do it?
also is my assumptions right to get the answers the text got?
AI: The voltage across the resistor is
$$V_{R1} = 2\mathrm A \cdot 10 \Omega = 20V$$
with the more positive terminal on the left (since the current from the current source enters the left-most resistor terminal.
Thus, the voltage across the current source (being careful to choose the reference direction such that the current enters the positive labelled terminal per the passive sign convention) is, by KVL:
$$V_{I1} = (V_{V1} - V_{R1})\mathrm V = (14 - 20)\mathrm V = -6\mathrm V$$
The power associated with the current source is then
$$P_{I1} = V_{I1} \cdot I_{I1} = -6\mathrm V \cdot 2\mathrm A = -12\mathrm W$$
By the passive sign convention, when the power is negative, the circuit element is supplying power to the circuit thus, the current source supplies \$12 \mathrm W\$ of power to the circuit.
As a check, the sum of the powers should be zero.
The power delivered to the resistor is:
$$P_{R1} = 20 \mathrm V \cdot 2 \mathrm A = 40 \mathrm W$$
The power associated with the voltage source is
$$P_{V1} = -14 \mathrm V \cdot 2 \mathrm A = -28 \mathrm W$$
The sum of the powers is then
$$P_{I1} + P_{R1} + P_{V_1} = (-12 +40 -28) \mathrm W = 0 \mathrm W$$
as required.
Note that another approach would be to calculate the resistor and voltage source powers using the series current and write, using the fact that the sum of powers is zero:
$$P_{I1} = -(P_{R1} + P_{V1}) = -\left((2\mathrm A)^2 \cdot 10 \Omega - 14\mathrm V \cdot 2\mathrm A)\right) = -12\mathrm W$$
as before. |
H: Is this a viable Voltage Regulator design?
I'd like to power a Raspberry Pi 1.0 Model B and a USB HDD enclosure from a 12V DC, 2.5A power supply. The USB HDD enclosure accepts 12V directly, but doesn't state how much power it consumes. The HDD I intend to put in it states it needs 12V DC, 0.55A and 5V DC, 0.55A. Presumably the USB-SATA controller needs a small amount as well, so I'd round up and say that call comes to 1.2A (0.55A + 0.55A + 0.1A for the USB-SATA). The Raspberry Pi doesn't have a constant consumption, but this FAQ says that a recommended supply would be 5V DC, 1.2A and an average consumption would be 5V DC, 0.5A.
Based on that information, I was going to attempt to use an LM317 to regulate the 12V DC down to 5V DC for the Raspberry Pi. I want to validate a few things.
Short of a full blown switching supply circuit, is there anything better I can do than a voltage regulator?
That I did the power calculations correctly and have enough supply current
Can I simply sum the 5V current and 12V current that the HDD needs?
0.55A @ 12V DC + 0.55A @ 5V DC + 0.1A @ 12V DC = 1.2A @ 12V DC
Can I model the Raspberry Pi as a 10 Ohm load resistor?
5V / 0.5A = 10 Ohm
Should I instead model it at the maximum draw?
5V / 1.2A = 4 1/6 Ohm
That the LM317 will not overheat if I don't use a heatsink
The Raspberry Pi will be on constantly, but will be idle most of the time. Only a single GPIO pin will be used, and it will source very little current (1.6mA on top of what the Raspberry Pi draws).
That I have selected the correct resistors to minimize the power draw from the LM317 circuit itself. I'm using this datasheet.
For my first pass I used really big R2 to minimize the current in the voltage divider controlling the adjustment pin. However, I didn't account for the Iadj current. Although small, multiplying it by a large resistor changed the voltage significantly
The math got pretty messy when I included the Iadj term.
Vo = 1.25(1 + R2/R1) + IadjR2
Vo = I2R2 + I1R1
I2 = Iadj + I1
So that means that...
R1 = (-5R2)/(-4*Vo+5+4IadjR2)
I1 = (Vo-IadjR2)/(R2+R1)
Which gives me enough data to graph I1 as R2 changes. I found the minimum I1 to be at 37.5K Ohm for R2, but that lead to a ridiculously large value for R1. So I compromised at the closest E12 resistor values to 30K Ohm for R2. Which were 33K Ohm for R2 and 56K Ohm for R1. My calculations say that should produce 5.2V DC and only draw 0.02mA for the adjustment resistors.
Is the simulation done by circuit lab close enough to reality that I could build it and have it work
I used the maximum value for Iadj in my calculations (100uA), but the typical value is 46uA. I'm not certain if that is linear to the voltage or current of the LM317. Either way, the math didn't 100% line up with the simulation.
simulate this circuit – Schematic created using CircuitLab
The results of the simulation are below:
Vo = 5.212V DC
I1 = 21.48uA
I2 = 121.5uA
Iload = 521.2mA
Calculations for selected values of R2
Vo 5 V
Iadj 0.0001 A
Vo I2*R2+I1*R1 V Equ 1
Vo 1.25(1+(R2/R1))+Iadj*R2 V Equ 2
I2 I1+Iadj A
R2 (Ohm) R1 (Ohm) Vo (Equ 2) I1 I2 Vo (Equ 1) R2/R1
1.000000E+00 3.333422E-01 5.000000E+00 3.749900E+00 3.750000E+00 5.000000E+00 2.999920E+00
2.000000E+00 6.667022E-01 5.000000E+00 1.874900E+00 1.875000E+00 5.000000E+00 2.999840E+00
5.000000E+00 1.666889E+00 5.000000E+00 7.499000E-01 7.500000E-01 5.000000E+00 2.999600E+00
1.000000E+01 3.334222E+00 5.000000E+00 3.749000E-01 3.750000E-01 5.000000E+00 2.999200E+00
2.000000E+01 6.670224E+00 5.000000E+00 1.874000E-01 1.875000E-01 5.000000E+00 2.998400E+00
5.000000E+01 1.668892E+01 5.000000E+00 7.490000E-02 7.500000E-02 5.000000E+00 2.996000E+00
1.000000E+02 3.342246E+01 5.000000E+00 3.740000E-02 3.750000E-02 5.000000E+00 2.992000E+00
2.000000E+02 6.702413E+01 5.000000E+00 1.865000E-02 1.875000E-02 5.000000E+00 2.984000E+00
5.000000E+02 1.689189E+02 5.000000E+00 7.400000E-03 7.500000E-03 5.000000E+00 2.960000E+00
1.000000E+03 3.424658E+02 5.000000E+00 3.650000E-03 3.750000E-03 5.000000E+00 2.920000E+00
2.000000E+03 7.042254E+02 5.000000E+00 1.775000E-03 1.875000E-03 5.000000E+00 2.840000E+00
5.000000E+03 1.923077E+03 5.000000E+00 6.500000E-04 7.500000E-04 5.000000E+00 2.600000E+00
1.000000E+04 4.545455E+03 5.000000E+00 2.750000E-04 3.750000E-04 5.000000E+00 2.200000E+00
2.000000E+04 1.428571E+04 5.000000E+00 8.750000E-05 1.875000E-04 5.000000E+00 1.400000E+00
3.000000E+04 5.000000E+04 5.000000E+00 2.500000E-05 1.250000E-04 5.000000E+00 6.000000E-01
3.500000E+04 1.750000E+05 5.000000E+00 7.142857E-06 1.071429E-04 5.000000E+00 2.000000E-01
3.600000E+04 3.000000E+05 5.000000E+00 4.166667E-06 1.041667E-04 5.000000E+00 1.200000E-01
3.700000E+04 9.250000E+05 5.000000E+00 1.351351E-06 1.013514E-04 5.000000E+00 4.000000E-02
3.750000E+04 2.760827E+20 5.000000E+00 4.527628E-21 1.000000E-04 5.000000E+00 1.358288E-16
3.300000E+04 5.600000E+04 5.286607E+00 1.910112E-05 1.191011E-04 5.000000E+00 5.892857E-01
Simulation Results:
R1 R2 Vo I1 I2 Iload
56K Ohm 33K Ohm 5.212V 21.48uA 121.5uA 521.2mA
AI: Buy a decent car usb charger. It will (most likely) be a complete 12V to 5V switching regulator, with filtering caps and everything. Better efficiency compared to a linear reg like the LM317.
The LM317 will use Voltage In * Current In = Power Used, part of which will be wasted in heat (Voltage In - Voltage Out) * Current In = Wasted Power. If we plug in the numbers, 12V * 0.75A = 9 Watts, of which (12V - 5V) * 0.75A = 5.25 Watts. That means 5.25 Watts of heat, which will kill a LM317 without a heatsink. And that's only 42% efficient.
A Switching regulator typically has 80~90% efficiency. Since we know you need 3.75 Watts of power on the output (5V * 0.75A), we can figure out the input power. Take the output power, and multiply it by the inverse of the efficiency percentage. 3.75W * (1 / 0.85) = 4.42 Watts of input power. Since we know the input voltage, we can reverse the power formula, that's 4.42W / 12V = 0.37 Amps. So you can use a smaller 12V power supply. And since it's only 15% of wasted heat (in this case 4.42 - 3.75 = 0.67 Watts), a heatsink is rarely needed.
That said, the USB Enclosure will typically have it's only 12V to 5V regulator to power the Hard Drive's 5V rail, so you shouldn't need to calculate for that. |
H: 12V DC Motor Attachments
I have an Arduino that I am running two DC motors off of. I have the L298N motor shield that I am using to power the motors. Now that I have the system hooked up and running, I want to add the next step.
My end goal is that I want to create a robotic 'arm' of sorts and write some code that can move the different 'joints' independently. I just want to be able to code an action directly so I don't need functionality where I manually control the movements.
I've been trying to find DC motor 'attachments' or 'heads' that I can build on top of the motor so when it spins, it will move the piece but I can't seem to find anything that fits the little DC motors (some of the heads are for Servo motors). I'm really attempting to build this from scratch so I'm trying not to use any 'kits' and am trying to learn about the different components that would go into building this. Everything I find seems to point me towards a kit or something which sort of defeats the purpose of building it from scratch.
Are DC motors ok for this or should I be looking into something like a servo motor?
Also, I'm aware there is a robotics stack exchange forum but this seems to fall under this a little better because I'm basically just trying to get an idea of what kinds of attachments can go with a DC motor and what exactly I can be using them for.
Thanks for your help!
AI: Well, first of all, that depends very strongly on which DC motor you're using. There's tons of them, all with different output shaft types and diameter.
Secondly, the attachments you're looking for are unlikely to be found commercially, you'd likely need to manufacture them yourself. This is because of my next point:
A plain DC motor is a poor choice for this system (and, truthfully, many systems). You have effectively no feedback system (that you've mentioned), so you don't know in your code how far the motor has moved. You can estimate with some measurements, but it's usually very inaccurate. You're not going to be able to move the arm in any sort of reliable manner with a plain DC motor. You'll also have no way to "hold in place", as there's no holding torque from an unpowered DC motor.
You likely want to look into small hobby RC servos. They're easy to control with Arduinos, have tons of commercial atttachments, are easy to manufacture custom attachments for without metalwork, and cheap. If you need something higher-power, perhaps a stepper motor will work, but you'll likely have the same issues with finding attachments. |
H: Converting ABC'D to De-Morgans
How would I go about doing this in steps
convert this expression to De-Morgans so that is uses NAND gates Only
AI: Note: This seems like homework (or at least self-learning in the style of homework), so I'm deliberately providing you with the means to solve your problem, rather than the answer itself, although the answer shouldn't be too much of a stretch.
So you have ABC'D using NAND logic only. A quick truth-table review, taken straight from any respectable textbook on boolean logic:
A | B | A & B | A NAND B
--+---+-------+---------
0 | 0 | 0 | 1
0 | 1 | 0 | 1
1 | 0 | 0 | 1
1 | 1 | 1 | 0
That should already help you. Now you certainly don't need DeMorgan to tell you A NAND B is the same as NOT(A & B). The power comes when you combine these truth table building blocks, and now you have a starting point.
Next, what is the truth table of the entire circuit (ABC'D)?
A | B | C | D | ABC'D = (A&B) & (NOT(C)&D)
--+---+---+---+---------------------------
0 | 0 | 0 | 0 | 0
0 | 0 | 0 | 1 | 0
0 | 0 | 1 | 0 | 0
0 | 0 | 1 | 1 | 0
0 | 1 | 0 | 0 | Continue counting in binary...
Once you fill in all 2^4 = 16 states in that truth table, you should have an easy time figuring out how to use the NAND truth table to implement the circuit with NAND logic only. Truth tables are tremendously valuable for problems such as this, and, in fact, could help you derive many of DeMorgan's laws.
Yes, truth tables can be a little tedious, and like many tools, they aren't strictly necessary, but they're also extremely intuitive and reliable, so when you get stuck, that's a good time to start writing out 0s and 1s. For non-trivial problems, you'll have a tough time keeping the logic in your head.
General approach
Generally, when given a complete diagram, you can follow these steps (of course you can skip a step here and there if you know the logic won't suffer):
Study the diagram down to the individual gate and input level
Write out the truth table for each input -> subgroup -> group -> ... -> entire circuit output, either working your way down from the overall circuit, or up from individual gates, or (quite commonly) a little bit of both!
Now you have nicely broken-down truth tables, as well as logic expressions, for the useful partitions of your circuit.
Take your overall truth table / logic expressions and start to factor out parts that you can modify in the requested manner. (e.g., start identifying AND(x,y) gates you can turn into NAND(NAND(x,y))
Now you can reverse the process in #2 with your updated logic.
This will work from small "toy" circuits all the way up to some fairly complicated logic, where more rigorous methods (and likely, software) will be the next progression in your studies. |
H: Power requried for M-ary modulation schemes
When we go for M-ary modulation schemes like QPSK etc, does the transmission power increase with M? Why?
AI: QPSK (quadrature phase shift keying) uses a modulating signal that produces no discernible change in amplitude (or power) because the 4 modulation amplitudes are held constant i.e. they are all on the circumference of a circle: -
This results in a time domain waveform typical of below: -
You can even take this further to 8-psk: -
So, the basic power remains the same for any m-ary purely-PSK system. However, there are variations and these have similar constellation patterns but there is amplitude modulation as well: -
Given that 4 out of the 16 bit combinations are centred further out than the others could mean the average power is greater but, there are also 4 bit combinations that are smaller than the others two so, given that these differences cancel out over time, you could argue that the net power is the same. |
H: How to protect audio device in car amplifier
I want to install amplifier module based on TDA7297 dual bridge amplifier in my car. The kit is based on the low-cost example shown in datasheet (fig. 3, page 5).
Is there any recommended way to protect the input? I don't want to fry my phone because there is spike in the voltage when starting the car or something like that.
AI: Load dumping... be prepared: -
Maxim say: -
The most aggressive of these surges is the so-called "load-dump pulse"
(Figure 1). This transient occurs when the engine is running and the
battery lead is disconnected, due to a poor connection or accidentally
while the alternator is charging the battery. The magnitude of that
transient depends on the alternator's rotational speed and field
excitation at the moment of disconnection. The surge can last several
hundred milliseconds and reach levels of over 100V, which is
potentially lethal to semiconductor circuits.
Do you need to take care of this potential problem? It's up to you. Here's the article.
It offers a few ideas about what to do to protect against load dumps such as the circuit below (obviously using a maxim device): -
So, protect at source and if this can't be done protect as close to the source as possible and if that means the two wires feeding your amp then so be it. |
H: Sending serial signal of HT12A encoder by wire over 25 meters distance
This question has been asked many times, but I couldn't find something regarding sending out serial binary pulses from HT12A encoder over long distance.
The wire will be running beside of AC 220v wires, so will it work efficiently without noises or voltage loss ??
AI: Use a twisted pair (one pair of a cat5e cable) or a shielded twisted pair if you are overly concerned, or convert to optical fiber if you are very overly concerned. 50/60 Hz is hardly ever a problem with unshielded twisted pair in practice.
If you are running one of those "data over power lines" devices in the building you might have more reason to be concerned, as those put high frequency signals on the power lines.
I haven't bothered to look far enough into the data sheet to find likely data rates, but back in the days of modems (current for some folks, still) data signals ran for many miles on UTP cables at rates up to 56 Kb. |
H: Calculation of solar panel and battery
I have a system that consumes 0.497 Ah,
with a voltage of 5V.
I did the calculations to feed the system with solar enegeria:
Watt = 5 * 0.497 = 2.485W
Hours = 48 hours of system use
Total = 149.1W consumption
By calculations I would say I need a solar panel that generates 2.07 ah and a battery 12.42 Ah.
Calculate solar panel:
149.1 / 6 (sun hours) / 12 (system voltage) = 2.07 Ah
Calculate battery:
2.07 * 6 (sun hours) = 12.42
That's right ?
AI: I assume your system "consumes" 0.5 Ampere of current and not 0.5 Amperehours of charge (that would be an unusual measure).
So you have calculated the power of your system to 5 V * 0.5 A = 2.5 W. It will run for 48 hours, so it needs 2.5 W * 48 h = 120 Wh.
So you'd need a battery with 120 Wh, but there is no ideal 5 V battery and no ideal 5 V solar panel.
You chose (I suppose) a 12 V battery and a solar panel with charger for that. And you want to charge the battery in one day so your system can run for two days without recharging.
In an ideal world you need a solar panel of 120 Wh / 6 h = 20 W (that is 12 V with a current rating of 20 W / 12 V = 1.67 A). And a battery with 120 Wh / 12 V = 10 Ah.
But the world is far from ideal:
To get from the 12 V of the battery to 5 V of your system, you'll use a switchmode power supply. Let's say you get a not very well build one (because it's cheap) and it has only an efficiency of 80%. The battery must have more energy to power the losses of the power supply. So with 80% you would need 120 Wh/80% = 150 Wh.
Next thing to consider is that for improved battery life (if that is an issue) you don't want to have it cycle from 0% to 100% often, but more like only from 25% to 90% (or even less). So you only use 65% of the rated capacity. For 150 Wh needed energy you'd use a 230 Wh battery.
The increased need alone now requires the solar panel to deliver at least 25 W. But sizing the solar panel based on peak power and sun hours is asking for trouble (except for some very sunny regions I guess). So to get a better estimate, you look up some statistics of the area where it is supposed to be used. At my place you have a measly 1.5 sun hours in December, and a day is roughly 8.3 hours long. Of course your solar panel will produce some power even when you don't have direct sunlight hitting it, but it's far from the peak power. So maybe it's 100% peak power and 30% power (I made that number up, no idea how much it is) for the rest of the day. So you'd get 25 W * 1.5 h + 30% * 25 W * (8.3-1.5)h = 85 Wh. We need roughly twice that amount. So better go for a 50 W panel.
I haven't even mentioned that you need a maximum power point tracking charger to get that, so the charger will have a certain efficiency which reduces the amount of energy available to charge your battery, think of another 90% efficiency and you need 55 W.
There should be better estimates around on how much solar energy is available. Like this graph:
(taken from Wikipedia by SechWatt)
It shows the total energy produces by a 1 kWp (kilowatt peak) solar panel per month somewhere in northern Germany. The average day (from sunrise to sunset) in December is 7.8 hours there, so you have 20 kWh in December, which averages to 20 kWh / 31 days = 645 Wh per day for a 1 kWp panel. With our needed 150 Wh we end up with a (150 Wh)/(645 Wh) * 1kWp = 232 Wp solar panel. So my estimation of 30% was probably way off.
Note: There should be calculators around for this kind of analysis.
If you plan to use the system for several years without replacing the components, you have to factor ageing in as well (battery capacity reduces, solar panel power reduces). So that makes things even larger.
Conclusion:
Use a battery rated for 230 Wh (12 V / 19.2 Ah), and a 232 Wp solar panel (12 V / 19.3 A), if you want your system to work in December in northern Germany.
If you plan to use it elsewhere, calculate again.
This should only be considered a rough guideline on what should be considered and I wouldn't consider it a complete analysis. |
H: My previous theory was wrong, so why does this work?
Hi I am new to electronics, and I have made a light tripwire using an Arduino Uno. I made this on the idea that electricity follows the path of least resistance, which I now know to be false (https://physics.stackexchange.com/questions/5670/electricity-takes-the-path-of-least-resistance).
False or not however, my tripwire works exactly as I would expect it to.
I programmed my board to sound an alarm if pin 2 reads low voltage
I thought it worked because if the photoresistor has less resistance than the resistor, then it would read high voltage and vice versa. So can anyone explain what is happening?
simulate this circuit – Schematic created using CircuitLab
AI: It's called a voltage divider. "The path" does not change. The current changes, because the total resistance LDR1+R1 changes while the voltage applied remains fixed, so the voltage across R1 (which is what you are measuring at U1 pin 2) changes. |
H: Tune radio with laptop
I want to sintonize (tune) local FM and AM radio stations with my laptop. I know nothing about electronics and thought this was the place to put my question, I don't know any site more relevant to this. What hardware and software do I need?
AI: You can buy the front end of a multiband radio or transceiver (transmit & receive) in a USB dongle, and the rest of the work is done inside the laptop as a Software Defined Radio (SDR).
Here is a list of compatible hardware for this particular software (Gqrx, built on top of GNU Radio)..
This one, for only $22.50, can tune FM radio stations but not AM.
Many of these allow you to transmit as well, but for that in general you would need an FCC ham radio license, unless you were transmitting at very low power (like 100 milliwatts on FM, check regulations before doing so).
Here's a screen capture of the Jawbreaker SDR (one of the more expensive dongles, it covers 30 MHz to 6 GHz) visualizing and tuning the FM radio spectrum: |
H: Electrical resistence between two different terminals
I have to calculate the resistance R_AB, R_AC and R_CD. But I'm confused because there are two different terminal, one on the left and one on the right. Can someone give me a hint how to solve this?
AI: If you were to draw out the circuit with just the terminals mentioned you would get this.
The wood should now be separated from the trees. |
H: OLED is garbled when powered by 3.7 battery but not when powered by USB or variable regulated power source?
I have an esp8266 on a breakout board for programming hooked up to an OLED via GPIO 0 and 2. It works fine if I power it via the FTDI/USB. It also works when I power it at 2.8-3.0V using a desktop variable power supply. But no matter how I connect a battery it won't work. I don't want the breakout board in my final project and I want it to be powered by lipo. I've tried making a voltage divider but the divider did not produce the voltage my calculations indicated.
I have 220 and 550 ohm resistor to bring the 4.04v of the battery down to 2.9v but when connected it takes it down to 1.1v which is not enough to power the esp8266 wifi module. I tried adding a capacitor over the +/- rails to improve the current, but I'm honestly still learning how that works.
The esp8266 works fine at a wider range of currents but the OLED seems to be very sensitive.
How can I get this working with the battery?
AI: Your resistors are limiting the current of all your loads. The OLED module is the most sensitive to such limitations. As stated in the comments, you need a voltage regulator. |
H: Necessary things in LPC1343 basic development board
I have finished my LPC1343 basic development board,just based on specs from datasheet and some referred from microbuilders.eu. I'm unsure if the board design is good or not so I've attached my schematics. Some things I'm concerned about are:
1.Power supply
2.D+ and D- from usb through 33 ohm resistor to chip and additional usb softconnect if necessary
3.Testing LED.
4.Separate switches for RESET and USB ftoggle.
5.12MHz crystal oscillator with 16 pF caps.
My question: Is the board design is good enough to work or will it go wrong? If something is wrong, what is wrong with it?
]3
[]4
AI: There are a few things that I'd point out:
1) As you noted in the below comments, you are using a diode to buck the voltage from a 3.7V battery. I've recommended against that since, as they are used, batteries lose their voltage level so your VCC line will vary depending on how much charge is in the battery. I'd recommend a real power supply over a diode since you'll remove that varied voltage as well as having a real regulated line. You'll need something with a low dropout voltage or brownout detection since your voltage difference between the battery and your required VCC voltage isn't that large.
2) Your USB resistors are fine. Just remember that when you lay your PCB out, that USB uses differential signaling. This means that they need to be length-matched and routed accordingly.
3) LED looks fine
4) Your USB_Ftoggle button isn't necessary. USB_Ftoggle signal is an output.
5) Your crystals capacitors. You have 16pF in place and I'm curious where you got those values. The LPC1343 development board uses 18pF for its 12MHz crystal, which is also recommended in the LPC1343 datasheet in Table 21 on page 61.
One other thing is I'm curious why you have a test point on the D+ signal of your USB but not the D- signal. You can't really use that for anything. |
H: How is FM modulation is achieved using a single BJT
I want to understand how this circuit achieve frequency modulation. The BJT is a 2N3904. I found that millers effect comes into play and varies the frequency of the tank circuit about a center frequency of the tank circuit.
I want to understand this in details and how to design circuits like this. How to calculate the parameters and their roles.
AI: L1 and C1 form a resonant tank circuit - this produces the main frequency of the oscillator. Positive feedback from collector to emitter via C2 ensures oscillation quite close to the natural resonant frequency formed by L1 and C1.
The other factor is the reverse voltage between base and collector. There are components missing on your diagram that bias the base to a nominal voltage of about 2V and that reverse voltage to the collector defines the value of the transistor's internal miller capacitor. This miller capacitor is voltage dependent and with the base voltage variations this capacitor retunes L1 and C1 in sync with the audio signal applied to the base. Hence, the base voltage frequency modulates the oscillator.
It's not a great FM modulator but it does work providing the AC signal at the collector isn't too big in terms of volts peak to peak. |
H: Interfacing 62256 SRAM to low pin-count AVR via latches
I need to add over 20 kBytes of RAM to the small device built around ATMega8. Moreover I'm interested to research whether I can substitute it with ATtiny2313. The goal is roughly speaking to store some fast arriving data there before serving them out through serial interface...
I thought of 62256 chips, but with them I need 15 address lines and 8 data lines - somewhat more than I can spare with any of these two MCUs. Meanwhile the matter is to find the solution with smallest (cheapest) MCU possible, so I'm not ready to switch to some ATMega16 or 32 which, I think, will do the trick. I also have found serial SRAM from Microchip, but it seems the speed will be not sufficient for me...
So I'm thinking of using two (?) octal latches - but I'm afraid I'm reinventing the wheel and here could be easier solution. That's why I'm here. This is my current idea:
I feed the high and low bytes of the address from outputs of two octal latches;
I wire 8 pins (say, PB0..PB7) to both latches and to 8 data lines;
Now I need two more pins to control latches and another two for WE and OE of the SRAM chip.
And here are my questions:
are two latches enough, is it correct I need no latches on data lines?
will 74hct373 be a good choice for latches?
is it ok to slightly swap address lines for high byte (i.e. instead of order A8, A9, A10, A11, A12, A13, A14 wire them as A8, A9, A11, A10, A14, A13, A12 for example to simplify routing)?
perhaps there is another solution (besides larger MCU, latches or serial SRAM) I've missed?
AI: Sounds OK. You are correct, don't put a latch on the Data lines as these are bidirectional. As long as you make sure OE is deasserted when you are programming the address, and you your latch enable lines are never asserted when OE is asserted, then you shouldn't have any problems. It will take additional clock cycles to access the memory, but that's the price you pay for saving pins.
It would basically be something like:
Ensure OE and WE are deasserted
Load address 0..7 onto data lines
Latch into the lower address latch
Load address 8..15 onto data lines
Latch into upper address latch
Either load data onto data lines (for write), or set to input (for read)
Perform operation using OE and WE pins.
Swapping the address lines to the SRAM would be fine - it just means stuff will be stored in a weird order inside the SRAM, but as far as the uC is concerned it will be contiguous. For flash this can be an issue as page accesses would no longer be possible, but SRAM like the 62256 doesn't have that issue as it doesn't use paging. |
H: Christmas lights - how many strands can I connect?
I am putting lights around my house this season, and am finding myself concerned about safety and what the company who makes the bulbs says is safe. I think they are being way over-cautious, because they say we can only connect two strands. But I'm reading different things on the web, and I'm not sure which is correct.
I want to connect six strands of incandescant C9 bulbs, which have 25 bulbs each (150 bulbs total). I've carefully read all the safety instructions, but the only recommendation for how many strands to connect is on the box itself, and it says only two. This is very inconvenient because there will be three extension cords going across our yard and walkway.
I found this equation via Google:
Number of total bulbs = Volts from your outlet X amps on your circuit X 80%/Wattage from a single lamp
So for a 120V outlet, and a 15A circuit, and each bulb having 7W, we should be ok with 205 bulbs.
And so, is it ok to connect all six of these strands, with the above equation in mind? Is the company that makes the lights just being super-cautious so that they don't get sued? What would be the major concern (blowing a fuse, or something else)?
And to clarify previous questions, my lights would in this case be connected in series (if it were possible to safely do so). Each strand is wired in series.
AI: If the strands are connected "in series" - strand A plugs into an outlet, strand B plugs into the end of strand A, strand C plugs into the end of strand B, etc. then all current for all of the strands will have to flow through the wires of strand A, which are probably too small to carry the current of more than two or three strands. If you have eight strands connected "in series", the wires in the first couple of strands will likely overheat and melt the insulation. |
H: Bulb not lighting up if resistor is used
I have a 12v adapter and small bulb of about 3.8v. If i give power to bulb with 12 volt adapter and with 100ohm to 10k ohm it doesn't light up and if i directly give it power without the resistor it fuses.
This is the bulb i have
When i give power to bulb with 9v battery without resistors it light up perfectly fine.
Adapter gives 1.5amp (mentioned on sticker)
How can i light up this bulb with 12volt adapter without blowing(fuse) it up?. I am not much experienced with electronics.
AI: I found a reference to a #13 radio pilot lamp rated at 3.8 volts, 0.3 amp. To operate that lamp from a 12 volt supply, you need a resistor that will drop 8.2 volts at 0.3 amp. Ohm's Law says that a 27 ohm resistor would work.
If your lamp draws a different current, the you would need a different resistor, but 27 ohms should be a good starting point. |
H: Best method of packet transmission between an array of sensor nodes?
Currently I'm working on a project where I'll have an array of four sensor nodes, each with three sensors. These sensor nodes need to send their data back to an ATMega controlled board for processing, display, etc. I had the idea of using some ATTiny85s, one on each sensor node, and use those to collect the data from the various sensors, then package it for transmission. I would like to have only one data wire, one ground wire, and one voltage wire connecting each node.
My question is this: what would be the best protocol for sending these packets of data over one wire? Each sensor node doesn't need to communicate with one another, and the ATMega only needs to accept input from the sensors, not send output too. I have heard of using the OneWire library with ATMega chips before but never on something like an ATTiny85. Or, would it be best to just try and send each packet of data "manually" (they're very small, no bigger than 100 bytes)?
AI: Best option would be either the onewire protocol or perhaps a half duplex UART. With half-duplex UART, all you do is connect all of the UART RX and TX pins to the wire and just keep all of the TX pins tristated except for the one microcontroller that's transmitting. You could run in to contention issues with the half-duplex UART method; onewire does not have this problem as it is open-drain. You shouldn't have any issues with onewire on an attiny85, aside from perhaps a bulky library implementation eating up all the program memory. |
H: Choose between two multimeters
I want to buy one low budget multimeter for regular use. I don't need any high end functions only the basic ones (measure current, voltage and resistance).
I have found these two multimeters (1), (2) in local stores. The first one costs 20 euros and the second one 16.5 euros.
As I want it for electronics projects the specs of both, regarding AC, DC current and voltage measurement, are more than enough for me. The only difference that I see as important is that the first one (the one from Allsun) can measure up to 20MΩ resistance when the second one can measure only up to 2MΩ (if you can see something else in the specs that I should notice feel free to point it out).
My concerns are which one has better build quality, which one is more reliable and which one's manufacturer is more reputable.
Something that I found odd is that while searching online stores, including Ebay and Amazon, I saw that the one from Mastech is very popular and is sold by countless sellers but the one from Allsun is hardly found. Does this mean something about the quality?
All in all which one would you recommend me?
AI: I suppose it's an answer, really:
When choosing a cheap meter, choose the cheaper one. It's not like either one is all that, and you'll have 3.5 more euros... (note: I have good meters and cheap meters - each have a role to play; if or when you want a good meter, that's a different decision.) Some places you don't want to use your good meter (well, I don't want to use MINE anyway.) |
H: Using AC fuse for DC & DC fuse for AC!
Recently I visited a site where I saw that in an inverter AC fuse are use for DC. It is quite odd for me!
Is it ok to use the same?
What are the factors to be considered when we use AC fuse in DC and DC fuse in AC?
AI: I would be worried if it's the other way around because the DC arc is not self-extinguishing like the AC one is at the zero crossing. Trying to be cheap with fuses at one point I realized that even a 0.3A AC fuse can glow for a couple of seconds on DC... And this was 250V AC rated fuse and I was only using at 12V DC.
For an inverter, if the electronics fail short to the DC rail somehow and it "decides" to output DC... I'd be glad the fuse was DC-rated (as long as it's not under-rated in terms of AC voltage). |
H: Power Path Controlling with GPIO and MOSFET
I'm not particularly well acquainted with MOSFET logic design and need some verification on a few things to make sure I've got them correct, and to see if there's any better ways of doing it. I need to control a 12v battery input terminal with a 3V3 logic level from an ARM microcontroller. I've put the following circuit together while digging through some other answers on stack exchange.
Power_Control is the ARM GPIO and operates on 3V3 logic. Q1 is an N channel Mosfet with datasheet. It has V_GS(th) = 2.1, V_GS being either 0, when the GPIO is low and 3.3 when it is high. So I assume that should work, but I honestly don't know if that's how I'm meant to be reading the datasheet. According to my understanding, Enhancement mode NFET should be off when V_GS = 0 and on when V_GS>=V_GS(th) and a Enhancement PFET should be off when V_GS=0 and on when V_GS<=-V_GS(th).
Q2 is a P channel Mosfet with datasheet. It's got max V_GS of +-20V so I assume it's rated to handle my input and it has a V_GS = -3V and it should either be -12 when Q1 is allowed to conduct or 0 when it isn't allowed to conduct. Q2 datasheet doesn't specify it, but I'm assuming it's an enhancement mode. Is that a correct assumption to be making?
Practically speaking, will this circuit work for the desired outcome? Are there better ways to achieve it? Less components, cheaper price or if it would be possible to use 2 of the same channel FET's as it'll save on cost.
AI: It will work. The drain current of 2N7002 at 3V is still around 0.1A... which is ok with the 10K resistor (needing only 1.2mA). But neither turn-on nor turn-off will be very fast. A somewhat marginal design. I'd do a Monte Carlo simulation on it if it were for series production.
You can get high-side switches all in one package these days, if that's what you're looking for. "better ways" depends what you mean by better. More protection for the switch? Cheaper? etc. This was covered to a fair extent in a related question: Switch (Relatively) High Voltage from Logic Level (It's not the same application [different voltages], so I won't call it a duplicate). |
H: Downloading custom audio in musical toys DIY
I am a computer science student and recently interest built into electronics . I want to ask how can i download custom audio in musical toys like this . All i have is this kind of phone toy, Please tell what else i need to purchase to do this DIY.
AI: Not directly to your youtube solution, but hope this helps: When in university I've made such a "toy-music" with AtTiny13 MCU. It is a small 8-pin chip.
You simply need to write the music byte by byte in the form like "note", "duration", "note", "duration" and then provide basic code which fetches bytes one after one and turns on the required tone (with an onboard timer) for specified duration. This appeared to be "as easy as lying" even though I have close to zero experience with MCUs at that time.
To upload new music you simply compile your code again with different array of bytes and write it again to the chip. |
H: buck regulator Vout configuration
I am using the LT3845 buck regulator to step down a voltage from 9 to approx 1.2V.Now, I see that the formula for configuring the Vout is as stated below -
This means I cannot go below 1.231 as Vout. Due to this I change my Vout to 1.3V, this makes my Vout equation as R2 = 0.054*R1.Now, R2 is the upper resistor(conected to the inductor of the buck) and R1 is the lower resistor.
Normally, the upper resistor is higher than the lower one. How is this possible or am I missing something in here please ?
AI: You want an output of 1.3 volts but you must have 1.231 volts across R1. This means R2 has a voltage of 1.3-1.231 volts = 69 mV.
Given that current thru R1 = current thru R2, R2 must be smaller than R1 or, put another way R2 = \$\dfrac{0.069}{1.231}\times R1\$ = \$\dfrac{R1}{17.84}\$ |
H: Why is this Arduino RF Receiver changing value back and forth so much?
So I have a 315Mhz receiver hooked up to an Arduino, and constantly printing the value of the A0 Analog in pin over to the Serial Plotter that is built in to the Arduino software.
This is the graph. You can see at the end there is some data from another 315mhz transmitter.
My question is, why is there so much noise when something is happening? Is this normal? Maybe a bad receiver chip?
AI: Cheap RF receivers don't understand whether data is present or not. They cannot distinguish between noise or data. They don't use a protocol, they don't recognize data frames, payloads or baud rate.
So, when there is no data (aka no strong desired signal) present, the AGC circuit (Automatic gain control) in the receiver keeps raising the gain until something is found and, in the your case it is noise.
When "strong" real data does come along, the AGC rapidly backs-off to avoid saturation of the RF circuits and you get a data output.
Here's an idea of what happens in an FM receiver after the demodulator: -
This uses the terminology of an FM system (data slicer) but applies equally well to an AGC circuit that is constantly trying to find the correct level and only being able to do so after a few bytes of preamble have been received.
For an AM receiver I'd expect a picture like this: -
The left edge of the picture is when the receiver is switched on and the AGC rapidly boosts gain to try and get a decent signal. Noise is dominant here because there is no RF transmission. Along comes a transmission and it takes a little while for the AGC to settle down. Towards the right hand side of the picture, the AGC has stabilized to suit the amplitude of the data carrier and, as you can hopefully see, the noise superimposed on the data has been significantly attenuated due to the AGC.
There are 2 faint dotted lines across the middle of the picture - these are idealized threshold points for reconstructing the data with a comparator using hysteresis. |
H: Why starting current in star-delta starter becomes 1/√3 times that of DOL starter?
I have seen this statement in a question paper. I was asked to prove it but I can not find the logic.
AI: The whole idea is that a smaller voltage is delivered to the motor windings during start up.
The end game is that the motor (or load) is configured as a delta winding formation. In other words, after the load is up and running, each winding receives line voltage.
However, during start-up the windings are put into star formation and each winding will receive 57.7% of the AC voltage.
When starting the motor (above) KM3 and KM1 activate whilst KM2 is deactivated. You should be able to see that KM1 terminates the motor windings into a star point thus the supply voltage to each winding is only 57.7%.
After a short while KM1 deactivates and KM2 activates. This puts all three motor windings into a delta configuration thus each winding receives 100% line voltage.
Here's a picture that shows (or implies) that math: -
Here's the SE question where I borrowed the final picture from. |
H: Pulse on edge of different clock
I have a clock coming from a pin (GMI_CLK). It passes through a PLL and a new clock with 4 times the frequency is generated (Sys_CLK).
Now I need a pulse each time a rising edge of the original clock is detected (Sys_valid).
This works perfect in the simulation.
It has been coded as followed, but both ways generate errors during synthesis:
make_clkvalid: process(sys_clk)
variable GMI_CLK_alt : std_logic;
begin
if rising_edge(sys_clk) then
if GMI_CLK = '1' and GMI_CLK_alt = '0' then
Sys_valid <= '1';
else
Sys_valid <= '0';
end if;
GMI_CLK_alt := GMI_CLK;
end if;
end process make_clkvalid;
[Synth 8-5535] port has illegal connections. It is illegal to have a port connected to an input buffer and other components. The following are the port connections :
Input Buffer:
Port I of instance clkin1_ibufg(IBUF) in module
Other Components:
Port I1 of instance i_43(LUT2) in module GMI_IO
Port I1 of instance i_42(LUT2) in module GMI_IO
Port D of instance GMI_CLK_alt_reg__0(FD) in module GMI_IO
Port D of instance GMI_CLK_alt_reg(FD_1) in module GMI_IO
or like this:
make_clkvalid: process(GMI_CLK, Sys_clk)
begin
if rising_edge(GMI_CLK) then
Sys_valid <= '1';
elsif falling_edge(Sys_clk) then
Sys_valid <= '0';
end if;
end process make_clkvalid;
[Synth 8-27] else clause after check for clock not supported [GMI_IO.vhd":183]
How can I implement it for synthesis?
AI: Your second implementation fails because of what is a common mistake. The code pattern:
if rising_edge(clk_a) then
signal_a <= '1';
elsif falling_edge(clk_b) then
signal_a <= '0';
end if;
Cannot be realised in hardware, because it describes a 1-bit register with two different clock inputs. Such a register does not exist in the FPGA fabric; the closest is a DDR output register which may be present, but even this is intended to be used with a clock and its inverse, not two totally separate clocks.
The first attempt looks more sensible. If you could include the error message that it generates, I will update my answer.
Now that you added the error message, I can see that this has nothing to do with the code snippet you posted. Although the relevant code has not been provided, I think the error here is that you have your GMI clock input connected to an IBUFG, and also to the logic in this module.
The most likely cause of this is that you have created your PLL code using CoreGen. CoreGen will needlessly place a global clock buffer between a clock input pin and a PLL/DCM instance. The result is that when you connect this same pin to something else (i.e. your edge detection circuit), the design cannot be routed because of the structure of the FPGA.
To solve this, all you have to do is remove the BUFG instantiation from the .VHD file that CoreGen created, and then connect what was the input to the BUFG, to the input of the PLL/DCM instance. Synthesis will insert a clock buffer in the appropriate place to allow your design to work.
Per the comment by @TomCarpenter, if the above solves your problem, there is an option in CoreGen to set the input buffer to "None". This avoids modifying the CoreGen output, which could catch someone out later on.
Even better would be to not use CoreGen for something as simple as instantiating a PLL; If you go to Edit > Language Templates > VHDL > Device Primitive Instantiation > Spartan 6 (or whatever) > Clock Components in ISE (it's under Window > Language Templates > etc in Vivado), you can find simple templates for instantiating your PLL, without the hassle / problems of CoreGen (such as the problem that you have seen). |
H: What kind of power management circuit do I need to embedded a rechargeable battery in my electronics project?
I am doing a project where my electronics runs on 5V which I wanted to power from a 7.2v lipo regulated down to that voltage. I'd really like to include the opportunity to charge the lipo without removing it from the project. What kind of circuit/components do I need to do it properly?
Say, would putting a battery charging ic at the battery's terminals in parallel to my system be enough to achieve what I need?
AI: Yes, but adding the device load directly to the charger load could confuse the charger IC. A better idea is to implement the load sharing system described in Microchip's AN1149: "Design A Load Sharing System Power Path Management with Microchip's Stand-Alone Li-Ion Battery Charger". This will run the device off battery power when it is standalone, and switch transparently to wall power when external power is available. |
H: Li-Ion pulse discharge to improve output characteristics
There are many scientific studies done on pulse charging of Lithium-Ion batteries. However, I have found nearly none on pulse-discharging those.
Here is probably one of the few-ones.
This study employs a well know effect of Lithium-Ion batteries to regenerate the voltage after the load was interrupted, thus dramatically increasing the specific energy (Wh/kg).
"Figure shows a Comparison between Constant Current and
Pulse Discharge at 600 A/m. Constant Current discharge
ends at about 2 s while pulsing results in a total on time of
16 s increasing the discharge capacity by 8 times."
It, obviously, won't give any benefit where the constant load is applied to a single battery, however, by distributing the constant load in pulse form within the battery pack should prolong its capacity as well as its lifetime greatly.
Besides the active control needed, I do not see any extra drawback of this approach.
Why didn't it become de-facto standard within the battery-powered device market?
I would really appreciate any reference documentation on this topic.
AI: The article makes it fairly clear that they aren't measuring the working capacity of the cell, but its capacity under abuse (30C in a cell not designed for high discharge) and it's down to 2% of its nominal capacity.
In that context, "pulse discharge" simply reduces the mean discharge rate to (discharge rate * duty cycle) and that "improves" capacity 8-fold, to 16% or about 1/6 of its rated capacity. As an analysis of the chemistry of the cell it's interesting, but still not very impressive.
Duty cycle appears to be 10%, inferred from the time axis (160s) and the quoted discharge time (16s).
So if you attempted to distribute pulses across multiple units to achieve continuous power, you'd need (ignoring the complexities of synchronising and switching between them) 10 of these batteries.
In that context, the interesting question is, how would this solution compare with the lifetime of the same 10 cells operated in parallel, each discharged at a 3C rate and thus subjected to much less abuse? And the article doesn't ask that question.
I don't know, but strongly suspect you can get higher capacity from 10 parallel cells discharged at 3C - provided you pay attention to cell balancing during both charge and discharge.
Still, does this have any merit in applications needing pulse power? Only if it offers benefits over a battery continually discharged at 3C to recharge a capacitor capable of sustaining the pulses. |
H: NTC error propagation: what I missing?
Reading through a Vishay datasheet of a NTC, I found the guide to devise the temperature error:
I don't understand why the errors of X and Y, for the non-approximated formula, were multiplied instead of summed. I am sure it is a silly thing that I forgot.
AI: Both effects are accounted independently. The effect of the B-Tolerance is relative to the actual value already corrected by the X tolerance.
As an example:
Assuming X is 8% and the effect of the B-Tolerance is 10%. The X value would account for +8% and the Y value would have be calculated on the already increased value by the X term. Resulting in +18.8% not the 18% as you expected.At the end of the day, given the range of X and Y, you can approximmate by X+Y, as the equation suggests, withou t big impact in the result.
In Math language:
\$(1+x)(1+y)-1=(x+y)+xy=x+y\$ if \$xy\rightarrow 0\$ |
H: Quick safety question probing 120VAC
I did read several questions about safely probing high AC voltages with an oscilloscope. I had been taught to isolate the scope, which I see now is dangerous. So I think what I should do is then use an isolation transformer between the DUT and the 120VAC wall outlet. My question is then if I want to measure say just the AC voltage waveform can I just connect my ground clip to the isolated neutral and my probe tip to the isolated line? Assuming both probe and scope input can take the voltage?
Or do I need another transformer between isolated neutral and line and the scope?
AI: Use a quality, high impedance, differential probe if your scope doesn't have the capabilities of differential inputs. This is an external device that provides isolation, typically up to 500 or 1000 VDC, and yet delivers a low level (.01 or .001) representation of the input signal.
If you scope does have the capability of differential inputs, Select "A + B", and use those two input channels to measure your signal. Note that you do NOT use common and the probe tip, but only the two probe tips.
Dealing with HV as I do, I much prefer just using the differential isolator for safety sake... It prevents even accidentally touching the (typically) grounded ring at the end of the probe to a live circuit, letting out the magic smoke. |
H: How to match the length of wire for a symmetrical circuit?
I am new to my current job and one design inherited from my predecessor was as follows. I am wondering if this is the best practice to make a symmetrical circuit.
I was told that the two wires (R+ and R-) should keep the same length to make a symmetrical circuit. To do that, the designer put some turns on the layout. It looks weird to me, but wondering if this is a common practice. The frequency in the circuit is up to 1.5GHz.
AI: 1.5 GHz has a wavelength of 20 cm and a golden rule is not to worry too much if there is a line mismatch of less than one tenth of this. That's 2 cm and maybe if the signal were a sq wave you'd be keen to reduce this by another factor of 5 or 7 to account for significant harmonics in the waveform.
So maybe mm precision is needed. You decide! |
H: Using AVRDude to program AtTiny via Arduino-as-ISP
As I understand, I can use Arduino as ISP. Most instructions start with "load ArduinoISP from examples".
But then I want to load existing .hex file to the target chip. E.g.
AvrDude -> ArduinoBoard+ArduinoISP -> targetChip
And I fail miserably to find proper instructions though I believe this is possible and perhaps even already explained somewhere. I could not find instruction mainly because keywords yield instructions on many related but different topics.
I suspect that as Arduino uses avrdude I can sneak how it works when programming via ArduinoISP... At least I'm trying in this direction right now, but I would be glad if someone can help me to save the time.
UPD I've succeeded with the help of the answer below. The last thing to mention - I hate arduino's instruction for giving an image instead of specifying wiring. As I understand it is like:
pin 10 to reset
pin 11 to mosi
pin 12 to miso
pin 13 to sck
AI: Assuming you already have a binary file for flashing, this page may help you. All you need to do is:
Connect the Arduino with loaded ArduinoISP sketch to the target chip
Run AVRDude. Make sure to specify a programmer type. Also note that ArduinoISP will work at lower serial speeds. Example:
avrdude -p m328p -P /dev/ttyACM0 -c avrisp -b 19200 -U flash:w:release.hex |
H: Why are rms values used to calculate power in amplifiers?
I am taking a beginning EE course, and it seems like we just use the given peak voltages to find the current and voltage gains of an amplifier. When it comes to finding the power from its source and the power deliver to its load however, we have to use the Vrms and Irms. Why is this necessary to do, instead of just using the peak of a sinusoidal voltage?
AI: Back in the stony ages, before AC, the power into a load was simply the voltage across the load times the current through it, so if an incandescent lamp with 120 volts across it had a current of 1 ampere through it, the heat and light it was generating were equal to what it was receiving from the generator: 120 watts.
Then, when sinusoidal AC came along, with all of its peaks and valleys, 120 volt peaks were no longer able to drive the lamps to full power, but a sine wave with 170 volt peaks could.
I don't know the genealogy of it, but someone in the mix back then discovered that if one makes a sine table with, say, one degree increments in X and puts 170 volts at 90 degrees, if one took a "sample" by calculating the voltage at every degree and squaring it, added up all the samples, divided that sum by the number of samples taken, and then took the square root of that sum, that Root Mean Square value would cause heating in the load exactly equal to that in the DC case. |
H: Modbus RS485 - Voltage greater than 12V?
I have a boiler (Immergas Eolo Star) which has 2 pins where you can connect either a normal thermostat or a "remote control unit" which can also give more detailed information (self-diagnosis) about the boiler. This made me think that it has implemented some communication protocol over RS485, maybe Modbus and I could connect to it via a RS485 adapter and have fun. Today I got the time to have fun with it but to my surprise the voltage on those pins is (measured) 31.8V DC / 7mA. This confuses me a little since as far as I know, RS485 operates at max 12V.
Do you have any ideas, should I add something between the adapter and the pins so the voltage level should be lower? If so, what should I put there?
Thank you,
P.S.:
Why do I think is working on RS485?
The fact that the "remote control unit" can be connected via the same 2 pin interface as a normal thermostat; also, I've checked that make of boilers and for other boiler family the "remote unit" had clearly specified that it's working on RS485. For mine this is not clearly written somewhere unfortunately.
From the manual I get only this:
"Digital Remote Control Device with climate
chronothermostat function (Fig. 1.6). In addition
to the functions described in the previous
point, the Digital Remote Control panel enables
the user to control all the important information
regarding operation of the appliance and
the heating system with the opportunity of easily intervening on the previously set parameters
without having to go to the place where
the appliance is installed. The Digital Remote
Control panel is provided with self-diagnosis to
display any boiler functioning anomalies. The
climate chronothermostat incorporated into
the remote panel enables the system delivery
temperature to be adjusted to the actual needs
of the room being heated, in order to obtain
the desired room temperature with extreme
precision and therefore with evident saving in
running costs. The chronothermostat is fed
directly by the boiler by means of the same 2
wires used for the transmission of data between
boiler and chronothermostat."
As per installing the remote control unit:
"Digital Remote Control or On/Off chronothermostat
electrical connections (Optional). The
operations described below must be performed after
having removed the voltage from the appliance.
Any thermostat or On/Off environment chronothermostat
must be connected to clamps 40
and 41 eliminating jumper X40 (Fig. 3-2). Make
sure that the On/Off thermostat contact is of the
“clean” type, i.e. independent of the mains supply;
otherwise the electronic adjustment card would
be damaged. The Digital Remote Control must be
connected to clamps 40 e 41 eliminating jumper
X40 on the P.C.B. (in the boiler), (Fig. 3-2)."
Here's the wiring diagram:
https://i.stack.imgur.com/HwYeM.jpg
AI: Based on the information you have provided the 2-pin port is unlikely to support RS485.
Since there is no mention of batteries in the remote control then the two wires are carrying both power and data. RS485 doesn't do than (in any configuration I've seen) and uses a differential pair, usually with a shield.
A 'normal thermostat' (bimetallic strip type) would not be detected on an RS485 network.
More than likely they have implemented their own protocol something like this.
simulate this circuit – Schematic created using CircuitLab
Power is fed out to the remote through a voltage dropping resistor. Let's say that when the remote is not transmitting data that it loads DRC+ enough to pull the voltage down to 20 V. When it transmits data it loads the line even further by connecting a resistor across the wires by a switching transistor. In our example the voltage might drop to 10 V for a '1' and back to 20 V for a '0'. The low voltage may have to be high enough to continue powering the remote - hence the 10 V.
Connecting a regular thermostat would present 31 V on DRC+ when open and 0 V when closed. Additional circuitry must be employed to detect and handle these signals. |
H: Sensing power supply - sensing after the on/off switch
I have a sensing power supply powering a custom build LED light for video. There is an on/off switch after the sensing lines and everything works well. The setup looks like this:
However I'd like to sense the voltage drop after the switch.
As what I have read in the PSU manuals, this configuration will cause current to flow throught the sensing lines when the switch is open and damage the PSU's resistors.
My question is, can the configuration work with a diode placed on the +SENS line to stop current when the switch is open? Like this:
AI: In short, a PSU sense line cannot include a diode in series; nor any other active/passive component, for what it matters. Adding a diode as in the schematic you have depicted will prevent the main current blowing up the internal Rsense of the PSU, however, this will also make also impossible for the PSU to correctly measure the remote voltage at the load.
Sense cables can have very small cross-section area (diameter/gauge), as the sensing current will be very small and the voltage drop negligible. This is always assuming that the PSU is being operated correctly. Most remote sensing PSUs does not allow the main cables to be disconnected separately from the sensing cables. This is precisely the type of PSUs the article from EDN refers to,
http://www.edn.com/electronics-blogs/power-supply-notes/4418253/Power-supply--Remote-Sense--mistakes---remedies
In any case, delving a little bit more into your root needs, I cannot understand why you want "to sense the voltage drop after the switch". Why would you like to break the power circuit but not the sensing lines? That defeats the purpose of the sensing circuit and it's explicitly forbidden in many designs of sensing capable PSUs. |
H: Real device with derivative transfer function
Is there a device that has \$s\$ as its transfer function, that is, a physical system implementing a derivative?
AI: @Ariser already gave you a good answer in the context of electronics: a differentiator implemented with opamps.
From a strictly theoretical point of view (system theory) a system with a transfer function \$H(s)=s\$ is not realizable because it is not causal, i.e. it would have an impulse response which is not zero before the impulse is applied to the input.
See this reference for more information.
Note that the differentiator using an opamp is a true differentiator only if we assume the opamp is ideal. Real opamps have internal circuitry that contributes many higher order poles to the overall transfer function, so the aforementioned circuit will have poles which make its transfer function causal (and also limit its bandwidth, which otherwise would be infinite). |
H: Can you measure the voltage of a capacitor with using an oscilloscope without a function generator?
Can I just use my oscilloscope to measure the voltage across a capacitor or will I need a function generator for that?
For some reason it shows what looks to be like a capacitor charging if I am not mistaken.
Here is the picture of the circuit:
Picture of the simulation:
Trying to reproduce the results I get this:
AI: You can, and you did.
Largely this was possible because you used storage scope.
If you had only an analog scope available, then to keep an image on the screen you would have likely needed to repeat the same experiment over and over, alternately charging and discharging the capacitor using a square wave source.
You also appear to have chosen a small enough resistor that the RC time constant was brief enough to accomplish a full charge during the first tentative contact you (manually?) made. It's quite possible that first tentative contact did not last but rather "bounced" however your scope sweep is so fast that your entire charging process may have occurred between the first tentative contact and any temporary disconnect, as there seems to be no "hesitation" in the charging curve.
And you selected a trigger which well captured the event of interest. |
H: Identifying which diodes are on in a full wave rectifier
For the circuit above, I am looking for which diodes are on during the positive and negative cycle. Is it safe to assume that I should just trace the path of the current based on where the diode is pointing?
For example, during the positive cycle, the current will enter node 1, then goes through D2 and D3. On the other hand, during the negative cycle, it will enter node 3, then D4 until it reaches D1. Is that correct?
AI: Yes, that is correct with regard to which diodes are conducting.
Where the current "enters" and "exits" depends on whether you view current as electron flow (ie. coming from the negative terminal of the current source) or "conventional" current flow (ie. coming from the positive terminal). That's a matter of habit and local customs. Your statement is proper for conventional current flow. |
H: Problem with overvoltage protection circuits limits
I have a circuit which input voltage shouldn't exceed 50 V, I can't use neither of available overvoltage protection circuits because of the limits each have;
Crowbar circuit. While this is a good approach, the fuse in the circuit is 10 A. What if overvoltage condition occurred but the source supply can't provide 10 A to blown the fuse? For example if the input voltage is 60 V and supply can only provide a maximum current of 5 A, that's 300 W on the SCR and fuse is not going to open.
P-channel MOSFET based overvoltage protection. This circuits working condition is depended on the gate voltage and is not a sharp cut off like crowbar circuit. assuming the mosfet have 50 mΩ RDSon with 10 A over it, that's 5 W of power loss, not to mention the price on low RDSon p-channel MOSFETs.
How do I protect the input from overvoltage condition and overcome the problems described? is there a better approach?
Input source can be a battery or power supply of any kind (DC), input voltage shouldn't exceed 50 V and maximum current is limited to 10 A both by a fuse and design.
AI: for example if the input voltage is 60 V and supply can only provide a
maximum current of 5 A, that's 300 W on the SCR and fuse is not going
to open.
That is simultaneously impossible; you can't have 60 volts across a crowbar if the crowbar has activated because the crowbar will clamp the voltage to 1 or 2 volts. So, at 5 amps that might be 5 or 10 watts but, it's more likely that it'll be much more current and, the fuse will blow.
How do I protect the input from overvoltage condition and overcome the
problems described? is there a better approach?
Just simulate it and you'll see that the crowbar circuit has to clamp irrespective of what series resistance the incoming supply has.
From a comment: -
any sort of PSU can be connected to it. maybe it's a 60 V / 3 A PSU,
maybe it's 12 V / 20 A PSU etc.
That puts a different light on things. This device is a 10 amp thermal fuse that operates at 73 °C. If it were thermally bonded to the triac/SCR it should offer some protection against sustained thermal damage on the triac/SCR. The two wires will be in series with the normal 10 amp fuse.
There are probably other variants that "operate" at higher than 73 °C and, maybe you might be able to replace the 10 amp fuse directly if you look into it more deeply. |
H: Voltage supply for an IC circuit
I'm currently working on setting up a logic circuit using ICs (SN74LS08N, HD74LS04P and CD4075BCN) and LEDs. I looked at their datasheets and I found that the maximum voltage supply to the ICs is 5.25V.
Which type of battery should I use as the source?
I currently found 2 solutions on the internet, one is getting a 9V battery with LM7805 voltage regulator IC and the other one is connecting 3 AAA batteries in series.
Which one is better for my circuit?
AI: Just use a 9 volt battery and a 7805 regulator.
You can get a 7805 from wherever you got your logic ICs. Other regulators aren't as commonly available, and other regulators aren't as forgiving as the 7805 (it isn't picky about the surrounding circuit and is pretty rugged electrically.)
9 volt batteries can't deliver enough current to burn things out if you wire something wrong.
It is easy to tell when to replace the battery - when the 7805 output drops below 5V.
Simple and reliable is best if you are just beginning.
I mean, consider what happens if your circuit doesn't work.
If you are using one of the "better" regulators, then they can oscillate if the circuit (input and output capacitance) is wrong. The output voltage will be wrong (and vary thousands of times a second.) How will you find that as a beginner?
If you use a stack of 1.5V batteries, how will you be sure that you didn't get more than 5V long enough to damage something?
Only power the circuit when you are using it (saves battery power.)
Use a new battery when you go to demonstrate it to your instructor.
Buy a bunch of 100 nanofarad capacitors when you buy your 7805. Place one 100nF capacitor across the power supply pins of every IC in the circuit - right at the IC. Everytime a digital IC switches states, it draws a spurt of current. That can cause the voltage at the IC to dip, which can cause the IC to misbehave. The capacitors make up for the little spurts and keep the voltage steady - your circuit will be more reliable. These are known as "decoupling capacitors."
If your circuit doesn't work, you can touch the ICs with your finger. If any IC is noticeably warmer than the others, then you can start looking for wiring problems around that IC. A 9 volt battery can deliver enough current to make things get warm, but not enough to burn your finger (or go bang.) The AA 1.5V cells can easily deliver enough current to burn a finger or worse.
Build your 5V regulator circuit by itself first, and make sure it delivers 5V before you attach any of your logic ICs to it.
The other answers give good advice in general, but you are a student just starting out. Simple and reliable are more important than any other considerations - for now.
As you go further into electronic things, you can look into more sophisticated regulators or other batteries.
For now, do what always works and has a very low chance of going wrong - you aren't yet equipped to deal with problems. |
H: Making a PMOS act as a low voltage drop diode
I would hope to replace my Schottky diode that is acting as a as or diode. I do not like how high voltage drop the Schottky diode is making thus I would like to switch to a MOSFET. And the simplest circuit I could with a MOSFET kind of like this. I do not know if this MOSFET will work
Correct me if I’m wrong on these points which I think is correct.
The MOSFET I have chosen will have a voltage drop of 0.01 V assuming I have a current of 250 mA (the expected current of the load).
With the circuit I have protected both my inputs from reverse voltage inputs. When both inputs are present the higher voltage input cannot go back through the other input.
Is my circuit sufficient? Would there be complimentary components needed?
AI: With the circuit i have protected both my inputs from reverse voltage
inputs.
Yes, reverse protection is functional.
When both inputs are present the higher voltage input cannot go back
through the other input.
When both inputs are present, they will be shorted to each other because both MOSFETs are on and they will conduct current in either direction.
If you want one MOSFET to turn-off when both power inputs are present you need to have extra circuits that monitor supply A and turn off MOSFET B when supply A is present. But, there's an added complication if supply A is valid when below the value of supply B because, switching MOSFET B off will not prevent supply B passing current through MOSFET B's diode to supply A. |
H: Voltage build up in induction generator and its working principle
I had some doubts while reading about working of self excited isolated induction generator .
If principle of operation of self excited isolated induction generator is similar (in a sense that in both cases initial excitation is due to residual flux and after that fields interaction takes place) to DC self excited generators, then why it needs capacitors to operate while in DC
generators there is no such requirement?
And which connection we preferred in case of induction generator, stator and rotor winding in series with load or (stator winding and load) in series and parallel to rotor winding?
(A mathematical explanation would be better or even any answer which does not talk about reactive power is good for me because I read from many websites, and everywhere I found that we need capacitor to provide reactive power but this explanation to me is far from intuitive).
AI: It is similar in theory, but in reality, design measures intended to minimize losses in the magnetic circuit result in reducing the residual magnetism in an induction motor to the point that an induction generator can not build up voltage from residual magnetism.
Induction motor designs are not compatible with connecting the stator winding in series with the rotor winding. In addition, wound rotor machines are very rare compared to squirrel-cage machines.
In reality, self-excited induction generators that are really useful and easy to operate have not been developed. Such machines have been demonstrated, but they generally need to be manually started and manually adjusted for load changes. The voltage tends to vary with load changes. There are people who have found them useful, but their usefulness is quite limited.
The Need For Capacitors
The rotating magnetic fields in an AC motor are the result of alternating current changing the polarity of electromagnets with every cycle of the waveform. That means that the magnetic energy of each magnetic pole must be removed from the electromagnet and replaced with the reverse polarity. That energy is transferred back to the power source and then returned to the motor with the opposite polarity. That means that the power source must have a complementary energy storage capacity, also known as capacitance. The continuous energy transfer is called reactive power.
Capacitors alone can serve that purpose, but the required capacitance varies with load and speed variations. Since starting the motor involves the speed increasing from zero to rated speed, starting is difficult. Starting also represents a big load variation. Other load variations, like switching individual loads on and off, also present a problem. The problems can be seen as voltage variations. It is also possible for an induction generator to loose its field and quit generating. If the generator is pushing power into grid that is capable of regulating the voltage under conditions of varying reactive power, most of the required power can be provided by capacitors at the induction generator location. Induction generators perform well under those conditions. |
H: TDR unexpected results
I am using a signal generator to generate a long square pulse that is fed into a long transmission line consisting of two parallel wires. The transmission line is approximately 1km long. The near end is terminated with a 25\$\Omega\$ resistor, and the far end is unterminated. With an ADC I am sampling the incoming signal.
In the below diagram you can see the square pulse (1) I am feeding into the transmission line.
(2) shows the signal I measured with the ADC. You can see that the first plateau is at U/2. The 2nd plateau is really small and almost not there.
I would have expected a incoming signal like shown in (3). I don't understand why the plateaus shown in (2) are not at the same voltage level.
Does anyone have an idea?
In the diagram I neglected the attenuation of the cable.
AI: When the far-end reflection returns, it causes a source reflection due to mismatch between source and cable impedance.
If you use thinner pulses, you can more easily see what happens: -
The simulation above uses a source impedance of 25 Ω and a line that is 50 Ω with an open far-end. The line is 10 metres long and is loss-less. If I make the pulse 200 ns you see this: -
Now, because you have reflections overlapping the original and reflections overlapping reflections, it becomes that much harder to analyse but, all the information is in there should you be prepared to work at it.
If I made the pulse 300 ns, the picture changes again but, the basic information is all in there: -
To change the cable parameters in microcap you need to access this by double clicking on the transmission line part and editing the line highlighted: -
This line has a length (LEN) of 5 metres with C/m and L/m also stated. |
H: When do you need a complex termination?
The formula for the characteristic impedance is below
So the characteristic impedance is a complex number. But why is a complex termination generally not used?
With complex termination I mean a transmission line terminated by more than just a resistor. Maybe a resistor and a capacitor.
AI: So the characteristic impedance is a complex number. But why is never
a complex termination used?
When \$j\omega\$ is significant, the formula reduces to this: -
$$Z_0 = \sqrt{\dfrac{j\omega L}{j\omega C}} = \sqrt{\dfrac{L}{C}} = \text{resistance}$$
This applies pretty much to frequencies of 1 MHz and greater i.e. the vast majority of RF applications.
At audio frequencies, the equation becomes more complex and is usually approximated to this: -
$$Z_0 = \sqrt{\dfrac{R}{j\omega C}}$$
So, for telephony applications, a complex termination method is used (in order to reduce telephone side-tone) like this: -
New Zealand and the UK use the above complex impedance for terminating a telephone cable in order to optimize the anti-side-tone circuit. Other countries use similar but not identical values.
Generally, a cable will exhibit this type of impedance response: -
At DC (well, 30 Hz) the impedance is determined by the ratio \$\sqrt{\frac{R}{G}}\$ and if R = 1 Ω then, according to the above (taken from wiki), \$\frac{1}{G}\$ has to be 1.6 GΩ and this wouldn't surprise anyone I would think! But, it all gets a little messy at mid-band audio and up to about 100 kHz for most cables. |
H: Auduino: Is the Ground Pin on PWD and Power the same?
I got a MEGA 2560 yesterday for christmas. I'm having fun experimenting with it. But looking at the board there was 2 GND (Ground) Pins in the "POWER" section
As you can see, there is 1 GND pin in PWM and 2 of them in POWER, I really don't know the difference between them, I tried searching about it on google but no forum or article came up that explained this.
Can anyone explain?
AI: There is no difference (practically speaking), they are there mostly for convenience.
You can verify this with a multimeter, measure the continuity (resistance) between the different grounds, you'll see they are at the same potential. |
H: 32 bit multiplication using 16 bit?
Please Note by multiply I don't mean 11 * 11 = 11 But I mean 3*3=9 which is 1001 in binary
I am interested in knowing the following about multiplying numbers:
Let's say I have two 32-bit numbers like this:
A0 * 0B where A,B are 16 bits and 0 is 16 bit zero vector, then How can I perform multiply of these two numbers if I have only 16bit multiplier and 0/16/32 shifter?
For example let's say I have 10101010101010100000000000000000 * 00000000000000001111111101010111 How can I use 16bit multiplier here?
In case I have 0A * 0B then I use what I have to multiply A & B which gives 32 bit answer and I don't need to do anything about it.
In case I have A0 * B0 then I use what I have to multiply A & B which gives 32 bit answer that should appear at the most left so I use shift by 32 bit (the bits moved are filled with zeros)
AI: For 16 bit unsigned numbers A to D, where AB and CD are 32 bit numbers formed by concatenation,
AB * CD = (A*C << 32) + ((B*C + A*D) << 16) + B*D |
H: How to design a switching circuit with minimal voltage drop?
I am using a high side switch with BSS84 MOSFET. This is used to power on and off all the sensor and actuators during deep sleep of the uC. All the sensors are working except the SG90 servo. There is a.vpltage drop from ~3.26V to ~3.04V. Which MOSFET could I use which has a low droupout voltage? Would IRLML2244 fit for this purpose?
AI: You’ll need a device with a low RDSon and a relatively low threshold voltage. You’re currently dropping 230mV although we don’t know how much current the SG90 is drawing when that measurement is made. BSS84 are P-channel FETs and claim an RDSon of 10 ohms, which is very high if you’re going to use one as a power switching device. You might consider a BSS308 with an RDSon of about 0.06 ohm. Either way you’re likely to struggle with an SG90 running at 3.3V as they require 4.8 to 6V. |
H: How to change breadboard power supply output voltage?
I recently bought a 3.3/5v power supply like this. I'm powering it with a fresh 9 volt battery and 9 volt to barrel connector cable. Right now, it's on 3.3 volt mode, and I have no idea how to switch it to 5 volt mode. All the videos I've seen on how to use it don't describe very well how to change the voltage.
AI: Here is a technical document about the device.
Basically you just put the 2 jumpers on the 5V position (bridge the leftmost 2 pins on both jumpers). |
H: BC547 base current and collector current
I am trying to make some simulations of the BC547, but I have some problems.
I adjusted the hfe (beta) to 320 and measured the base current and the collector current as below:
The RMS value of the base current is 33.552uA. RMS value of the the emitter current is 1.17mA.
If we multiply base current by hfe, the result is 10.73mA but Multisim shows it is 1.17mA.
Why are calculation and simulation so different? Are my calculations wrong ?
If I wait some time, the base current becomes 68uA and the emitter current 1.4mA.
The values of the components are as below:
AI: If I wait some time, the base current becomes 68uA and the emitter
current 1.4mA.
This suggests a capacitor in the circuit is taking some time to charge up to a stable DC voltage. In your schematic C1 = 100 mF. This is a very large value (1/10th of a Farad!). 100 μF would be more reasonable.
I simulated your circuit in LTspice using a BC547B (which has HFE of ~300). Here is a plot of Emitter and Collector voltage during the first 200 seconds after switch on.
It takes over 20 seconds for the Emitter voltage (green line) to rise enough to get the transistor out of saturation, and over 100 seconds to reach a stable voltage. The Collector voltage (which looks like a solid area due to the high signal frequency) shows that the input level is too high, causing the output to bang against the supply rails as the transistor turns fully on and off.
The plot below shows Base current (green), voltage across C2 (red) and Collector voltage (blue) over a few cycles of the signal:-
The input signal is so high that the Base-Emitter junction is acting as a rectifier, charging C2 with negative current which reduces the Base bias voltage from ~2 V to ~1.5 V. The output waveform is strongly clipped on both positive and negative peaks, causing massive distortion.
After reducing the input level from 0.125 V to 0.0125 V, it looks much better:-
Now the Base current is continuous (with negligible rectifier action), Base bias voltage has returned to normal, and the output waveform only shows a small amount of distortion.
Why are calculation and simulation so different? Are my calculations
wrong ?
Your calculations are based on a small signal level which doesn't cause significant distortion or change the DC bias level. It also assumes that all capacitors are charged to their final DC values.
When simulating a circuit with potentially large AC voltages it always pays to inspect the waveforms. Average, rms, peak and DC values do not tell the full story and can be hard to interpret.
If some elements may cause significant time delays then simulate for long enough to ensure that the circuit has stabilized. If this takes too long then either change component values to reduce the delay, or set the required initial conditions to skip it. be aware that simulating a small time period may give misleading results. |
H: Battery Power Control with MOSFET - One Button FlipFlop
I cannot get my head around the circuit below of a Flip Flop SR switch using one push button and only MOSFETs:
The image below seems incomplete probably due to a typo (as R3 is not shown) but I believe R3 should connect Vbatt to R4.
The general concept is that with just one Push Button you are able to toggle the MOSFET Q3 ON and OFF.
I understand that from resting position (C1 discharged), the first push on the Button will bring Q1 (and consequently Q2) to conduction, thus charging C1 to Vbatt.
What I do not understand is what happens next if you push again the Button: Does the C1 bring Q1 gate to Vbatt (thus witching it off)?
I spent hours trying to understand but I am honestly lost.
Any help is appreciated.
Bests
AI: Initially, C1 is discharged.
When the button is pressed, the gate of Q1 is pulled low trough C1, turning Q1 on.
This, in turn, turns Q2 on because it's gate is pulled high by Q1.
Q2 keeps Q1 on by pulling Q1's gate low trough R4.
So the 2 FET's keep each other enabled, the circuit is turned on.
When you let go of the button, C1 will charge up trough R1.
So next time you press the button, it will pull Q1's gate high, turning it off.
With Q1 disabled, Q2's gate will now be pulled low by R2, turning it off as well.
C1 can now discharge trough R1 and R2, so next time it's empty again and the cycle can repeat. |
H: Identifying transistors
I have found an old driver board (probably the mid 80's) for stepper motors (rated at 1.25V 3.8A) and I want to rebuild the H-Bridge using the parts on the board and a micro-controller as an input. I have the schematics but the ICs (mainly the transistors) are marked with proprietary numbers (not the typical TIP 120 for example). From the schematics and the board I know that I have PNP darlington (called 3825) and NPN darlington (called 3805) transistors. Having no datasheet for the transistors I built a simple circuit to measure the gain:
Measuring the current between the emitter and the ground I get 0uA. Across the 1M resistor I get 8.89V and 0V across the 1K resistor. Measuring the voltage between the collector and emitter I get 9V.
I added a push button but pressing the button only changes the voltage between 8.99V and 9V (Although I'm not sure my multimeter is that precise).
So where did I miss something?
PS: My multimeter as an hFE function but cannot read gains higher than 999 and my guess is that those have higher gains than that.
AI: Most integrated Darlington pair power transistors have resistors so you would need a realistic current at the base and collector.
You could measure the resistance from base to emitter with an ohmmeter (the higher value of the two polarities, if one is higher, will be the correct one). |
H: Multiple buck converters and their draw
This is another LED pixel project that I'm looking to power in a slighty different way. It's 110no. 5050 SMD pixels on a 300mm x 300mm board.
The long and short of it is that I'll use USB-C Power Delivery to supply 3A at 20V. The logic side of the circuit is all 3.3V, while the LED pixels are 5V. In total I have an absolute maximum of 6.6A worth of pixels.
To keep the PCB low profile, and to allow for better/easier heat disspiation, my idea was to use 3 or 4 integrated buck modules (e.g. TPSM84209) to power groups of pixels.
Is my understanding correct in that:
I can tie all of the grounds together (of the µC, USB-C and buck modules)? In that way, they all share the same reference and it means logic to the pixels will work?
The particular module I've linked (TPSM84209) will output 2A at 5V? My reading of the graphs (for Vin = 24V) suggests that at 2A it's about 80% efficient. Does that mean that if I draw 10W on a buck module, the module will draw 12.5W from the 20V supply, or 1.6A?
What additional drawbacks might there be with using multiple buck converters (aside from increase in cost and complexity)?
AI: I can tie all of the grounds together (of the µC, USB-C and buck modules)? In that way, they all share the same reference and it means logic to the pixels will work
Yes
Does that mean that if I draw 10W on a buck module, the module will draw 12.5W from the 20V supply, or 1.6A?
Yes, for the 12.5W. But
12.5W/20V = 0.625A |
H: The Complex Power from a source V = 200cos(wt) is 200 + j150. The impedance across V is given by what value?
I found the answer using P = V^2/R and by using P = VI*. In both cases, I got the answer as 128 + 96j. But the answer given is 64 + 48j. Which is the correct answer?
AI: When one writes \$V=200\cos(\omega t)\$, \$V\$ is the instantaneous voltage, and 200 is the peak of that voltage. To calculate power you need to use the rms value the voltage, which for a sine wave is \$\frac{1}{\sqrt{2}} = 0.707\$ times the peak voltage.
The failure to use rms value is why the answer you arrived at is twice as large as the correct answer.
The complex power \$S\$ is given by:
\$S = V_{rms}\cdot I_{rms}^*\$
so
\$I_{rms}= \frac{S^*}{V_{rms}^*}\$
The impedance is given by
\$Z = \frac{V}{I} = \frac{V_{rms}}{I_{rms}} = \frac{V_{rms}V_{rms}^*}{S^*}\$
In the given problem,
\$Z = \frac{(\frac{ 200}{\sqrt{2}})^2}{200-j150}= \frac{20000}{200^2+150^2}(200+j150)=\frac{20000}{62500}(200+j150) = 64+j48\$ |
H: 433 MHz Antenna - Balanced Dipole + Balun?
I've got three 433MHz receivers (all the same type) and I would like to increase the range on them (by which I mean the physical distance that the receiver can detect the signal from the transmitter). Changing the antenna on the transmitter (the little key fob/dongle thing) isn't an option for practicality reasons. One of these receivers is unfortunately housed in a sheet metal box (which can't be readily changed), so I would like to get the antenna outside the box, but I'm unsure as to how running it out of the enclosure interacts with the total length of wire used in the antenna itself, (i.e. the length exposed outside the enclosure vs total length to get back to where it is soldered to the receiver).
The receivers currently have short coiled wire antenna (they look like a spring, but are actually coiled wire). Since the receivers are stationary, I can take some liberty with a larger antenna. Googling suggests that a balanced dipole antenna with a balun is the way to go, with 178mm straight wire on each 'leg' (not sure of the right term) on the antenna. The problem is, I don't know the first thing about RF, so I haven't been able to discern what is a good guide for how to construct such an antenna.
Could anyone point me in the direction of a practical guide in this area that is technically sound?
EDIT - Hardware Details:
The transmitter and receivers are Elsema PentaCode series devices:
Transmitter: PCK43302
Receivers: PCR43301RE & PCR43302240R
https://www.elsema.com/pcr43302240r
https://www.elsema.com/pcr43301re
Basic details are on page 3 of this document:
https://www.elsema.com/wp-content/uploads/2019/05/pckmanual.pdf
They're frequency hopping spread spectrum devices, with a freq range of 433.100 to 434.700MHz.
Target range is ~200m, not quite line of site (elevation diff of about 10m over 150m due to small hill that rolls off).
EDIT - Directions to Transmitters:
So, the receiver's are stationary, but the transmitters are mobile. In the case of the gates, they're on access roads, meaning the transmitters can be sending a signal from either side of the gate (so, 180 degrees from each other). This is part of the problem, as a high gain antenna in one direction will hurt the radiation pattern 'out the back' (i.e. from the other direction), which isn't great given that the goal is to open it from both sides. Energy radiated 'to the sides' is wasted though. Is there an antenna design that can help achieve this?
AI: Full size antenna options would be a ¼ λ vertical monopole with one radial or a ½ λ horizontal / vertical dipole.
Holes are to be drilled in the enclosures to lead the elements out.
The ground point on the PCB is to be connected to the metal enclosure.
The unit may be oriented to have the dipole horizontal or vertical. |
H: I have a single phase induction motor, with no capacitor, and can't see the shaded pole. Can you help me understand how it starts or should start?
I have a small single phase, induction motor with no capacitor. It's not missing, so this has got me thinking it should be a shaded pole. However, I don't see the shaded pole and my motor is just humming. If I try to manually spin it, it's very difficult while powered up. What am I missing?
AI: It's a shaded pole motor.
Location of shading rings shown in green
Trouble spinning could be bad bearings if feels like increased friction
If it feels like it's full of molasses it probably some electrical problem in the motor. |
H: Need feedback on my new circuit design
Circuit 1
i am quite new to PCB and circuit designs. I am trying to build two PCB consisting of ESP8266-12E and Shift Register (SN74HC595N) as a core of it and a high voltage relay control circuit. I have designed a low power PCB design to control via manual switchs which can be connected on terminal.
I am using SN74HC595N because there is a ready library for arduino to control, which makes things easier to code.
here is how my PCB looks like:
here the RED tracks are for jumpers i guess, that will help to keep things on single layer PCB.
Circuit 2
To control the high voltage (220V) appliances i kept things on the another PCB. This is a PCB design not executed anything yet. Need professionals feedback to understand in case if i need to improve something in this. Because i know i might have made mistakes while designing. So just to educate myself i am trying to build this PCB Design. I try to keep proper distance between the tracks and keep the expose copper area as well, so i it can allow higher current to flow.
Note: I am not going to build this relay control circuit. As it might be dangerous, just trying to understand where to improve it.
Also one more thing, is it a good idea to keep ground plane around 220v AC supply in relay circuit? Because i have seen in ready modules available in market they keep it, but i am not sure how much it will be helpful.
Here is complete schematic diagram for the same.
Any feedback from your end will be helpful to understand and gain more knowledge.
AFTER UPDATES
As per the suggestions here are the new updates, i try to maintain as much gap as possible on the relay (HV - Circuit 2) board circuit. To keep low voltage component as far as possible.
With circuit 1, i just changed the whole layout basically, to bring 2 layers to make things easy and also to bring more flexibility on the platform. Please feel free to keep the reviews posted.
TOP VIEW of Circuit 1
BOTTOM LAYER VIEW of Circuit 1
Thank you so much for your kind support guys!
AI: It's hard to find useful layout documentation to your ESP8266-12E; but I bet the antenna mustn't be placed above signals, and it's likely it shouldn't be placed above any copper at all. Espressif themselves have reference designs where the antenna should be sticking out from the rest of the board:
It's a good idea to route signals on the top layer, sure, but not because your board is single-layer: every board house I've met will give you the same price for single- and two-sided boards. You want the bottom side to be (almost completely) reserved for a ground plane. You want your decoupling capacitors to be able to take a short current return path – otherwise, they're useless, or worse, they even distribute noise into other systems.
I don't know your relay type, but I think something is very wrong in your component footprint: in all sensible relay designs, the three "high voltage" contacts are on one side, and the lower-voltage coil is on the opposite. So, verify with your relay datasheet how your footprint looks like. That pretty much changes the largest part of your relay board layout, so re-do that (from scratch).
(did I mention datasheets? Save documentation to all your parts with your project; if a part has no datasheet, go to a reputable distributor like farnell or digikey and buy a part with a datasheet instead.)
I don't know your 220 V AC -> 5 V DC supply, but usually, if there is a rectangular box, you can't put a resistor in there – don't R10, R11 collide with the supply?
as your layout software indicates, you've basically split your top-layer ground plane in half on your relay board with the long horizontally running 5V rail. That won't do well, but doesn't matter because I guess you'll be re-doing that layout with the correct relay pinout, anyway.
generally: layout the relay board such that all high voltage is on one side, and that there is absolutely no board copper crossing from the high-voltage side to the low-voltage side. Again, your relay footprints are almost certainly wrong, and that's what makes this harder. Google "PCB Clearance 220V". You never want your high-voltage circuitry to be close to your low-voltage one, and your design doesn't allow for that separation. That also means "no ground plane under your relay's dangerous side".
You're missing decoupling caps at the shift register (it's not what we'd normally call an "IO expander", it's a just a shift register). Adding one close to each relay would also make the whole system more robust.
Your relay board (the other one, too, but here it's a real show-stopper) needs mounting opportunities: some holes to put a screw in, or free edges to slide it into some guide or something. Mounting is necessary, because the bottom of your board will have 220 V contacts sticking out – can't have that flying around, or you will at some point either touch it or have some dirt cause a short and then a fire.
Print out your design in "real" size before ordering it. This is probably smaller than you think it is (always happens to me, still, after years), and since boards are cheap, making things larger is always a good idea |
H: What pull-up or pull-down resistors to use in CMOS logic circuits
I use a lot of "wired or" circuits where rather than using a logic gate in an IC package I simply use diodes (eg. 1n4148) into a destination gate that has a pull-up or pull-down resistor on its input (depending on the logical function I need). I have found this quite reliable and have used as many as 5 diodes (so far) to make such a logical function.
With CMOS circuits I have been delighted that I can do this with very high valued resistors. Where I might use something in the 1K to 5K range in a TTL circuit, I am using up to 100K with CMOS circuits. This of course helps keep current draw down.
My question is "what problems might such an approach expose my circuits to?" Using very high value pull-up/down resistors is something I want to do, but I read one article (from TI) that suggests the 1K to 10K range even for CMOS logic. That seemed counter-intuitive to me. Are there any nasty suprises that may lay in wait for me by using high-valued resistors?
AI: high resistance make the circuit slower and more succeptable to electromagnetic interfereance.
If you circuits are slow and stateless it probably doesn't matter
some stateful parts (like flip-flops) need a certain edge speed and could misbehave if the the edges are too slow. |
H: Parallel LC circuit Q factor inductance role
I'm wondering why Q factor in parallel LCR circuit is proportional of C and inversely proportional to L according to the formula \$Q = R \sqrt{C/L}\$ completely lost here
AI: I'm wondering why Q factor in parallel LCR circuit is proportional of
C and inversely proportional to L
As a slight help, if you considered a resistor in series with an inductor, the Q of that circuit is: -
$$Q_S = \dfrac{\omega L_S}{R_S}$$
But, you have \$L_P\$ and \$R_P\$ and, the \$Q\$ of the parallel combination is: -
$$Q_P = \dfrac{R_P}{\omega L_P}$$
So, \$Q_P\$ is inversely proportional to inductance
For a parallel RC circuit, Q is: -
$$Q_P = R_P\cdot \omega C_P$$
So, \$Q_P\$ is proportional to capacitance.
Now I know it's more complication for an RLC but I didn't want to do half a sheet of math to prove it when you can get a feel for the answer by analysing the parts. |
H: How to calculate measurement error in an exponentially non-linear sensor? (self made pressure sensor)
I'm trying to calculate the measurement error from a home-made pressure sensor which I have in a voltage divider circuit. It has the same negative exponential non-linear resistance characteristics as an NTC thermistor: with increasing force [N] the resistance [ohms] decreases non-linearly. The pressure sensor acts as a variable resistor, and I am measuring the voltage drop across it using an 8bit ADC.
So far, I have taken resistance measurements (with a multimeter accuracy to .1 ohm) of the homemade velostat pressure sensor at exerted forces from 1 to 10 N using a force gauge (with an accuracy of 0.05N), with 5 resistance measurements at each force value. The average of the 5 measurements are graphed below.
My plan to calculate the exerted force [N] is to use a "power function" which is created from the data in Excel and rearrange it to solve for X (force) at a certain Y (resistance). The resistance (Y) is derived from the voltage measured by the ADC.
Is this a good approach, or should I use a lookup table or linear interpolation? (I'm not sure on how to do either of these yet.)
How do I calculate the measurement error from the sensor seeing as resistance changes only a small amount in higher force ranges, and resistance changes a lot (sensitive) at small exerted force ranges?
EDIT: added chart of my resistance measurements with max and min values graphed (the 20 measurements at each value of F [N] not shown in table).
AI: $$V_2=V_{ref}\dfrac{R_t}{R_1+R_t}=V_{ref}(\dfrac{1}{1+\dfrac{R_1}{R_t}})$$
$$V_2=V_{ref}(\dfrac{1}{1+\dfrac{R_1}{244.5x^{-0.941}}})$$
$$R_t=\dfrac{R_1}{\dfrac{V_{ref}}{V_2}-1}$$
$$244.5x^{-0.941}=\dfrac{R_1}{\dfrac{V_{ref}}{V_2}-1}$$
$$x^{-0.941}=\dfrac{R_1}{244.5(\dfrac{V_{ref}}{V_2}-1)}$$
$$-0.941\cdot lnx=ln\dfrac{R_1}{244.5(\dfrac{V_{ref}}{V_2}-1)}$$
$$x=e^(\dfrac{ln\dfrac{R_1}{244.5(\dfrac{V_{ref}}{V_2}-1)}}{-0.941})$$
$$x=\left( \dfrac{R_1}{244.5(\dfrac{V_{ref}}{V_2}-1)} \right) ^\dfrac{1}{-0.941}$$
You can now use the measurements and write the function into partial Taylor series.
$${\displaystyle x_{approx} = f(V_a)+{\frac {f'(V_a)}{1!}}(V_2-V_a)+{\frac {f''(V_a)}{2!}}(V_2-V_a)^{2}+{\frac {f'''(V_a)}{3!}}(V_2-V_a)^{3}+\cdots ,}$$
For each measurement point a, you calculate the 1 to n-th differential (additional LUT table, with fixed numbers) and then you calculate the interpolated value. Using just 1st derivative could be just fine, with 2nd derivative the measurement error will be greater than approximation error, 3rd derivative is an overkill.
If you have some MATLAB, Octave,...you could solve the derivations and calculate numbers. Then you use those pre-calculated values with regard of your calibration points. The only overhead to the CPU is then squaring the (V2-Va).
You could expand/modify the Taylor series for two neighboring points. link
EDIT:
I have searched the net for some symbolic differentiation. First of all in the school books you will usually find a function defined as y=f(x) so lets rearrange
y=(R_1/(244.45*(V_R/x-1)))^(1/-0.941)
where y is the Force, and x is the measured voltage
I have inserted the equation (R_1/(244.45*(V_R/x-1)))^(1/-0.941) into an online solver - www.derivative-calculator.net. I have chosen the values Vref=3.3V, R1=220 ohm.
I did compute the voltage V2 according to equation (1) when Rt=130, according to your graph (function equivalent) it should be at force=2.
V2=3.3* 130/(220+130) = 1,225V
I got this:
The force should be approx. 2, I don't know why is this deviation. The solver also made an simplification of the function:
$$\dfrac{4889^\frac{1000}{941}\left(\frac{V_{ref}}{x}-1\right)^\frac{1000}{941}}{20^\frac{1000}{941}R_1^\frac{1000}{941}}$$
Finally, the 1st derivative is:
$$-\dfrac{50{\cdot}4889^\frac{1000}{941}V_{ref}\left(\frac{V_{ref}}{x}-1\right)^\frac{59}{941}}{941{\cdot}20^\frac{59}{941}R_1^\frac{1000}{941}x^2}$$
Now all you have to do is to insert values.
For example 1st point (F=1; Rt=230), V2=3.3*230/(220+230)= 1.686V. I do insert this value as x, and the value of the 1st derivative is f'(1.686)= -1.37612. The second derivative is 1.737047.
For the small deviation around the 1st point the force could be computed as Taylor series of 2nd order:
$$F_{approx} = 1 - 1.37612\cdot (V_2-1.686V)+0.68806\cdot (V_2-1.686V)^2$$
Calculating the V2 for the 2nd point (F=2; Rt=135) as already before V2=1.225 and inserting into above equation gives F=1.78 |
H: Approximating the dirac delta function on LTspice to find the impulse response of a high pass filter
I have an assignment which requires me to find the impulse response of a high pass filter on LTspice. In order to do this the question suggest feeding a Dirac delta function as an input to a simple high pass filter circuit consisting of 100R resistor and 1uF Capacitor. Now I've tried a triangular pulse and square pulse with a high voltage and minimal rise and fall times but I don't quite get the expectedthe frequency response (the general frequency response of a high pass filter) when I take an FFT of the output voltage.
It would be brilliant if someone could show me the best way to approximate a Dirac delta function on LTspice. Any and all help is appreciated, thanks in advance.
High pass filter with simulation parameters for a square wave input:
AI: The amplitude spectrum of a square pulse input is a sinc-function, and these are the high-frequency lobes that you see in your FFT. Whatever you do, these lobes will always be there. If you make your input pulse too long, these lobes will get in the way of your signal. This basically means that your input signal should be short enough compared to the highest frequency that you wish to capture in your FFT.
The time you simulate will also play an important role on the frequency range of your spectrum. In order to capture down to \$1Hz\$ for example, you will need to simulate at least \$1s\$ of your impulse response.
An lastly, the number of points in your FFT are also important to avoid seeing those artifacts in your FFT. You mainly need to ensure that at least one sampled point is part of your input pulse, and if you make it higher than that you will start to see those lobes at higher frequencies.
The ideal combination would be:
$$T_{stop} = 1/f_{min}$$
$$T_{width,input} = 0.5/f_{max}$$
$$N_{fft} = f_{max} / f_{min}$$
Here, \$T_{stop}\$ is the transient simulation time. \$T_{width,input}\$ is the pulse width of the input voltage source. \$N_{fft}\$ is the number of points to use for the FFT.
And finally, there's numerical errors that can also affect your impulse response. Go as strict as you're comfortable with.
For example:
Use an input pulse of \$10\mu s\$ wide and specify \$1ps\$ rise and fall times to ensure that the simulator also truncates the timestep (\$f_{max} = 50kHz\$).
Simulate with a transient simulation from \$0\$ to \$100ms\$ to get an FFT down to \$10Hz\$ (\$f_{min} = 10Hz\$).
Plot the FFT, but only use \$10\ 000\$ points instead of the default \$262\ 000+\$ points to avoid the high-frequency lobes. You can go higher, but keep in mind that these lobes are because of the non-0 pulse width of the input.
If you are unhappy with the results, make the tolerances stricter by going to the configuration under the tab "SPICE".
For example:
Reltol = 1e-6 (this is the relative tolerance, default is 1e-3)
Trtol = 1e-4 (this is the truncation error tolerance factor, default is 1)
[EDIT] There are a few other things you might need to change.
LTSpice will smoothen out points by default, but this also messes with your FFT. If you take the FFT, make sure the binomial smoothing is set to 1 (3 is the default).
LTSpice uses a modified version of the trapezoidal method, leading to artifacts in the FFT. The regular trapezoidal method may give better results.
If you make the total integration time too big, then numerical errors may dominate.
Here's a screenshot of my results (I didn't normalize the input pulse area though, but that's just a scaling factor): |
H: Mixer LO to IF Isolation vs. 1*LO - 0RF Spur
I am working on a simple digital radio receiver and am confused by the difference between the LO to IF leakage vs. the 1LO - 0RF spur. These two tables in the datasheet of the Analog Devices HMC218B passive mixer are the source of my confusion.
The "Spurious Outputs" table lists the 1LO-0RF as being 3.4 dBc. Working from the test conditions at the bottom of the table, this means that the mixer would have an output spur at a frequency of 5.25 GHz 3.4 dBc below the power of the desired IF output, in this case 100 MHz. If the conversion loss of the mixer is 7 db (as is specified in the 2nd "Electrical Specifications" table), then for a RF power of -10 dBm the IF power at 100 MHz should be -17 dBm, so the power of the 1LO-0RF spur at 5.25 GHz should be -20.4 dBm.
If the LO to IF isolation given in the "Electrical Specifications" table is used to find the power of the LO signal at the IF port, one finds that the power of this unwanted LO at the IF port is -19 dBm. This calculation uses the specified LO to IF isolation from 4-6 GHz to be consistent with the frequencies used in the "Spurious Outputs" table.
The 1.4 dBm difference in 5.25GHz power at the IF port given by the "Spurious Outputs" table and the "Electrical Specifications" table is minor, but in my case the input RF power is around -50 dBm (@ 5.8GHz), not the -10 dBm that is used in these tables. This decrease in RF power significantly changes the calculated LO power at IF depending on which table is used to find the LO at IF power. For example, if the "Spurious Outputs" table is used in conjunction with the conversion loss from 4-6 GHz in the "Electrical Characteristics table" I find that the 1LO-0RF spur should be -60.4 dBm, 3.4 dBc below the -57 dBm IF output at the desired IF. However, if I use an LO power of 13 dBm (the LO power used throughout the datasheet), and I calculate the LO power at IF using the LO to IF isolation given in the "Electrical Specifications" Table, I find that the LO power at IF would be -19 dBm. Which method should I used to find the LO power at IF? Is there a fundamental difference between LO to IF isolation and the 1LO-0RF spur? Perhaps my understanding of dBc is wrong and is throwing off my calculations.
Thanks for your help.
AI: The first table is only usable at an RF power of -10dBm, and only at an LO frequency of 5.25 GHz.
You would expect the power of a 0RF spur to stay constant, regardless of the input RF power, so it's not correct to try to use the first table to take 3.4dB with respect to a different RF input power.
Given that the LO to IF isolation is given as typical 32dB, minimum 15dB, quite a range, I'd say 1.4dB between the two tables is as near as you can expect to spot-on. Note that the 3.4dB is quoted at 5.25 GHz LO, the 32dB isolation is typical over the range 4.5 GHz to 6 GHz.
I see. Even though the values given in the table aren't valid for different RF powers, is it acceptable to use them as general guidelines while frequency planning? For example, some of the spurs are as weak as 90 dBc for the given test conditions. Is it ok to ignore those spurs even though the spur table will change with varying RF power.
The table 1 guidelines are to allow you to quickly eliminate mixers that are 'obviously' wrong for your application, they are not a substitute for proper receiver design. Once you have a shortlist of those that may do, you must then get either more comprehensive figures from the manufacturer, a physical model and test it at your power levels, or ideally do both.
The purpose of table 1 is to give you guidelines as to the levels of spurs to use when doing frequency planning. However, as it's given at one power level only, you will have to use your skill and judgement to estimate what it will be at other power levels.
In general, the nRF product will change at ndB per dB of signal level change, for typical diode mixers, when the signal level is small. When I've used RF mixers, they often have a table 1 taken at two different power levels, which allows you to determine whether signals are still 'small' at that level. For a badly behaved mixer, the spurs may become better or worse as you get to the 'big signal' regime, so extrapolation down to your low signal level is very uncertain.
Whether -90dBc is 'OK to ignore' is down to your application. If you're building an amateur data receiver, almost certainly. If you're building a commercial synthesiser, probably not. If you're building a commercial data receiver, then it's not going to affect your in-band demodulator performance, but what are your blocking specifications? You mention signal levels of -50dBm, which in my experience is low, even for a spectrum analyser, so you probably are pushing the spurious performance. |
H: Why attach sensor output to ground?
I'm getting into electronics (so my terminology may be a little wonky in places), and I'm trying to create a simple setup using a Raspberry Pi 4B, a GPIO extension board, a HC-SR04 sonar sensor, and an LED.
To wire up the sonar, the kit I'm using supplies this diagram:
Most of this makes sense, except for the need for the resistors, and the connection of Echo to GND.
Despite the sensor running using 5V, I'm guessing R2 is to protect GPIO24, since it takes 3v3?
My main question is about R1 and R3, and why Echo is connected to ground at all. My first thought was that this would cause the signal sent from Echo to be lost to ground, but then I realized that the total resistance going to ground is higher than that of the direct path to GPIO24, so most of the electricity will travel along the lower resistance path to the GPIO pin, and some will go to ground.
Is this simply "bleeding off" extra voltage into ground?
AI: R1, R2 and R3 form a voltage divider.
simulate this circuit – Schematic created using CircuitLab
When a 5V signal is applied to the top of the divider (the echo signal), ohm's law states that:
$$\frac{5V}{3000\Omega} = 1.67 mA$$
Will flow trough the resistors to ground. This means there will be a voltage drop of:
$$1.67mA * 1000\Omega = 1.67V $$
Across each resistor.
Since R1 and R3 are in series, their voltage drops add up. So there will be approximately 3.34V on the output to the raspberry pi.
The raspberry pi input has a very high input resistance so that it's effect on loading the divider can safely be ignored in this case. |
H: AC Measurement of a Transistor
I am trying to analyze a transistor circuit. I should find RMS output and input current and voltage. I have made some calculations but I am not sure of whether they are acurate or not.
for input RMS current:
$$
-I_{in} + I_b + \frac{V_{R1} - V_{CC} }{R2} + \frac{V_{R2} - 0}{R_1} = 0 \\ I_{in} = 4.79\mu A
$$
$$
I_{in(rms)} = \frac{I_{in}}{\sqrt 2} = 3.38\mu A
$$
For output voltage:
I thought the voltage gain is around 3.9 so the output voltage should be Vin.Av and it is 1.14V or 1.17V.
For input voltage:
My signal generator's amplitude is 300mVp so the input signal amplitude should be same.
For output current:
the output current should be \$\beta.I_b\$. Thus \$I_{output} = 1.392mA\$
Here the circuit
Ib = 4.8 micro ampere.
hfe(beta) = 290
Signal generator:
Vp = 300mV
f = 400Hz
AI: It's a lot easier to read the schematic, as follows:
simulate this circuit – Schematic created using CircuitLab
You are supposed to determine:
\$V_{\text{B}_\text{RMS}}\$ (at the BJT base, not at the signal source -- includes a DC bias.)
\$I_{\text{IN}_\text{RMS}}\$ (as seen by the signal source -- no DC bias included.)
\$V_{\text{C}_\text{RMS}}\$ (at the BJT collector -- includes a DC bias.)
\$I_{\text{E}_\text{RMS}}\$ (as seen by the BJT emitter -- includes a DC bias.)
(All voltages above are referenced to the schematic ground.)
I would have imagined that you were supposed to find \$V_{\text{OUT}_\text{RMS}}\$ (as shown in the schematic) because it does not include a DC bias and is therefore usually more comparable. I would also have imagined comparing it with \$V_{\text{IN}_\text{RMS}}\$. But, I guess, that's not what you are supposed to do. (The emitter current will also include its DC bias, as well. So I'll just cave in and believe two of your requirements as stated.)
Specifications are as follows:
\$V_{\text{IN}}=300\:\text{mV}_\text{PK}\$, \$f_\text{IN}=400\:\text{Hz}\$
\$h_\text{FE}=290\$ (though I can't tell if this is a specification or an observation you made)
From Nexperia's BC846 series datasheet, I find they specify the part into two \$h_\text{FE}\$ groups: A and B. The \$h_\text{FE}\$ group B says that \$200\le h_\text{FE}\le 450\$ with the typical \$h_\text{FE}= 290\$. Since that typical value from Nexperia just happens to match the number you gave, I'll assume that's where it came from.
The geometric mean is \$\sqrt{200\cdot 450}=300\$ and this means to me that \$h_\text{FE}\$ varies \$\pm 50\%\$ around \$h_\text{FE}=300\$. (Assuming the difference is intentional, there's probably a slight bit of kertosis to the almost-Gaussian distribution that accounts for the typical value being \$h_\text{FE}= 290\$.)
I don't derive the equation for it, but you can find the collector current sensitivity equation here:
$$\begin{align*}
S^{I_\text{C}}_{\beta}=1-\frac{\beta}{\beta+1+\frac{R_\text{TH}}{R_\text{E}}}
\end{align*}$$
In your circuit's case, this is \$\%\,I_\text{C}=S^{I_\text{C}}_{\beta}\cdot \%\,h_\text{FE}\approx \pm 3.68\%\$. So all of your calculations will need to anticipate that collector current variation.
If you include resistor tolerances of say \$2\%\$, then this gets very close to \$\%\,I_\text{C}\approx \pm 4\%\$ due to part variations.
This still avoids issues of temperature as well as part variations of \$V_\text{BE}\$ vs \$I_\text{C}\$. And those will also have an impact on the collector current variation. Depending on the temperature range you want to accept. If you go with the datasheet's total span from \$-55^\circ\,\text{C}\$ to \$150^\circ\,\text{C}\$, then this might be an added \$\pm 10\%\$ or more. So now you might be as much as \$\pm 15\%\$!
Just be aware. There's no point writing down the quiescent collector current with any higher precision than the expected situation allows for.
My thoughts:
The signal generator's output impedance isn't specified. One might choose to assume an ideal signal generator. But from your writing, my gut tells me this isn't the case. So it may be \$50\:\Omega\$, or it may be something else as signal generators often have more than one output impedance available to them.
\$C_2\$ will present a small but significant impedance at \$f_\text{IN}=400\:\text{Hz}\$.
\$V_{\text{B}_\text{RMS}}\$ will be loaded down by \$R_1\$, \$R_2\$, and \$R_4+r_e^{'}\$ (seen through \$h_\text{FE}+1\$). It might also be loaded down further by \$r_o\$ (and inconsequentially by \$R_3\$) if the Early Effect is accounted for.
\$V_{\text{B}_\text{RMS}}\$ will include a DC bias, which will have a very significant impact on the resulting calculation.
\$I_{\text{IN}_\text{RMS}}\$ will be driving the entire input load, but it will not have a DC bias impacting the calculation due to \$C_2\$'s presence.
\$V_{\text{C}_\text{RMS}}\$ will also include a DC bias, which will also have a very significant impact on the resulting calculation.
\$I_{\text{E}_\text{RMS}}\$ will yet again include a DC bias, which will yet again have a very significant impact on the resulting calculation.
The AC component of \$V_{\text{C}}\$ will have to account for the attenuation of the input signal due to the effective impedance divider at the BJT base input node. It will also have to account for the effect of \$r_e^{'}\$. It may also have to take into account \$r_o\$ if the Early Effect must be accounted for.
At this point, I cannot add much to help out as I really don't know enough about the situation, yet. If you add more to the discussion, I may add a few more thoughts to the above. |
H: Help identify part or find replacement for component marked PJ6446. ER1J
I picked up a Behringer Europower Pmp560M. The power unit is starting primary side then shutting down. It has a number of diodes on the back. One has clearly failed and got a little hot and now has some chunky lumps of solder either side.
Anyway it is marked
PJ6446.
ER1J
I have no idea how to look up component numbers besides googling (which got me nowhere.)
I have no idea how you guys manage to take a code like that ^^ and return with a part number, manufacturer, date of creation, designers family pet name etc.
Please give me some tips for future projects.
The board is a power supply and amplifier.
Top of board:
Bottom of board, you can see the 4 diodes to the right of the top separation hole:
The culprit:
AI: Looks like a PANJIT International ER1J , Datasheet.
ER1J is the part number. PJ likely stands for "Panjit" and 6446 is probably a manufacturer specific code like a production date and may differ between parts. |
H: Failing to get low quiescent current on 555 monostable
I put together the basic 555 monostable circuit, but found it drew a bit over 2mA when "off".
To an extent, this makes sense as the 555 effectively has a 15k resistor between VCC and GND. I thought that I could cut power to the 555 when it's off to drop to a really low quiescent current, so I put in the two transistors and associated components up above the IC in the schematic.
While technically a success in that this dropped the quiescent current draw, it only dropped down to 1.76mA. I took a look at a similar question and answer, and the only difference that I think I have in the power setup is that I'm using BJTs instead of MOSFETs. I looked up the datasheet on the PNP (a PN2907, but KiCad didn't have that) and saw the leakage current to be far less than what I'm seeing.
For testing purposes, I replaced the output sub-circuit on the right with just a resistor and LED for an indicator/dummy load. The test setup ran from a 5V breadboard power supply, though the final version is intended to run from a nominal 4.5V (three AA batteries).
Why is this still drawing milli-amps of current and what is the minimal change needed to correct this? (General critique is also welcome, though I intend to stick with through-hole and the 555 for the project at hand.)
Update: Adding the corrected schematic for the sake of others who may come looking.
AI: The LMC555 shown in your schematic is a CMOS type and has 3x 100K resistors rather than 3x 5K resistors in the bipolar 555.
It typically draws around 100uA. The old-fashioned bipolar type draws a couple mA typically (there is current draw in both cases that is in excess of the divider chain).
The leakage in Q3 will be multiplied by the hFE of Q2 so you should have resistor E-B on Q2, but that's not likely to be your problem (it would tend to show up as a latent design error at high temperatures).
I'm thinking that the problem is not shown on your schematic and you have an issue with switching the load with a low-side switch, which is causing sneak paths in your load to ground drawing current. Use a high-side switch and ensure that no inputs to your load are more than few hundred mV above ground. |
H: FL5150 Multi channel dimmer
I'm looking to design a four channel dimmer using the On Semi FL5150/FL5160 dimmer chip.
This will be controlled by a digital signal sent over an isolated I2C interface, with my initial design using the MCP4728 quad channel I2C DAC.
However the reference designs on the datasheet tie the Source pins of the output MOSFET pair to the GND of the dimmer control chip. As I would have to tie the GND of the DAC to each dimmer chip to correctly reference the analog voltage, all four MOSFET pairs would have their Source pins linked, so the circuit would fail to operate as expected (all four channels would operate as one).
Can somebody explain:
why are the Source pins connected to GND ?
is it possible to omit this connection ?
is this connection required for ZC detection, if so could this be provided via a different method ?
NB: this is a different question to FL5150 (LED dimmer) circuit explanation
AI: FL5150 is phase cut dimmer, not a LED dimmer. Output is AC switch. Connection to ground is reference for gate controlling voltage. Then transistor are opened, current goes through diode of one transistor and drain-source the second. Another polarity - transistors switching places. Transistor are controlled by DC signal. The ground is not real earth, it is minus of IC power supply. |
H: Gigabit transceiver with MHz reference clock
I've some experience with Xilinx FPGA generating 10Gb/s over SMA loopback with on-off keying modulation (what scope shows) to perform BER test but the documentation shows it uses a reference clock in MHz level.
How is it possible to generate gigabit line rate especially 10Gb and above with MHz reference clock? Someone told me to look at SerDes but I could not make sense with it. Can somebody please navigate me?
AI: High speed serializers use phased-locked loops (PLLs) or frequency-locked loops (FLLs) to convert a low-frequency reference clock up to the required frequency, which is usually half of the line rate. This is almost universal for a number of reasons.
First, serial line rates need to be rather precise (ppm) so that clock-data recovery can work, and it is rather difficult to make a precision oscillator at many GHz - oscillators at that frequency tend to be either tunable (and hence will be locked to a low-frequency reference...with a PLL) or not particularly precise (percent instead of PPM). Using PLLs also means that a single high-precision oscillator can be used as a reference for many different transceiver channels, even running at different rates.
Additionally, having a reference oscillator at line rate is going to produce all sorts of EMI. Running high frequency signals all over the place can also consume a lot of power, as opposed to generating it near where it is to be used. Not to mention all of the additional constraints for high-frequency design (placement, routing, impedance control, etc.).
Using a PLL also means that changing the line rate is very simple and usually can be done by simply changing some divider settings, which can be done at run time. This permits Ethernet interfaces to easily switch between 1G (1.25 Gbps), 10G (10.3125 Gbps), and 25G (25.78125 Gbps) rates, PCIe to switch between 2.5, 5, and 8 Gbps, etc. Providing separate oscillators for each required line rate would significantly increase the cost and complexity.
The PLL works by using a VCO (or other tunable oscillator) to generate the high frequency, then dividing both the output and the reference, filtering, comparing the two using a phase and frequency detector (PFD), and then continuously adjusting the VCO tuning voltage so that the divided output tracks the divided reference. This has the effect of scaling the reference frequency by a rational fraction. Since the output is locked to the reference, the output frequency will have the same precision as the reference frequency over long time scales. |
H: Does this op-amp circuit have a name?
I got asked to analyze this circuit during a past interview, and truth be told, I still don't have a good understanding on what it is and how it's intended to work.
I understand V+ = Vout/2 and V- is an RC circuit related to Vout.
I assume V+ and V- are meant to be differential.
I also know that the op-amp will adjust Vout to make the voltage at the inverting and non-inverting terminals the same. If you could refer me to this circuit, I'll do my own research and be on my merry way.
AI: It's an opamp-comparator-based relaxation oscillator.
In a nutshell, charging source of the capacitor alternates between +VDD and –VSS, and the frequency of the cycle is determined by the R and C components:
$$
\mathrm{f = \frac{1}{2\cdot \ln(3)\cdot RC}}
$$ |
H: questions about up-sampling and moving from slow to fast clock domain in FPGA
I encountered some questions and problems I asked myself lately and hoped I can get a nice lead here before I start reading long articles without even be sure if it's the right way.
Let's assume I have an FPGA design, where I get ADC data with a sampling rate of 40MHz, so I latching the data from the ADC interface in 40MHz.
but I want to make the DSP inside the FPGA in 100MHz clock speed (for example because I have DDR3 memory interface in the DSP block diagram which working in 400MHz in 4:1 clock rate that means the UI clock of the DDR3 is 100MHz).
The data from the ADC interface which coming in 40MHz rate is 90% of the time valid, which means I need most of it.
So the first question I want to ask, How would you move the data stream from the slow to fast clock domain?
I already made a working mechanism for this, I filled up a FIFO (with 1024 depth) and right after that start to fill the next FIFO ( I used 2 FIFOs),
while the Reading process from the first FIFO starting at the moment the first FIFO is filled, and from this time on, I just read the 1st and then 2nd and 1st and 2nd and so on...
while keep to writing to the 2 FIFOs each at a time.
After I finished to write this block, I asked myself if there is a better way,
I encountered the Interpolation filter using FIR, does Interpolation make this job of moving from slow to fast clock domain for a stream of data?
I also saw the Polyphase filter which seems like also a way to move to a faster sampling rate.
Does its filter which easy to instantiate in FPGA is the right way to move the stream of data to a faster clock domain, or my way with FIFOs is the way to go?
thanks.
AI: So the first question I want to ask, How would you move the data stream from the slow to fast clock domain?
I already made a working mechanism for this, I filled up a FIFO (with 1024 depth) and right after that start to fill the next FIFO ( I used 2 FIFOs),
Exactly like you're doing it: with clock domain crossing FIFOs.
After I finished to write this block, I asked myself if there is a better way,
I encountered the Interpolation filter using FIR, does Interpolation make this job of moving from slow to fast clock domain for a stream of data?
No. I mean, yes, but no.
You want to pass the same samples on to a faster clock, and process them there. Interpolation (and all resampling) actually change the digital signal.
Let's illustrate with an example: Say you want to go from a 40 MHz-sampled signal to 200 MS/s (megasamples per second). What you do is simply insert 4 zeros after each input sample. Because you usually want the "zeros" to not be zeros but represent the analog signal as if it was sampled at 200 MHz to begin with, you apply a low-pass filter (in that application it's called an anti-imaging filter) and get an interpolated signal.
Just because you get 200 million samples per second, however, doesn't mean you need to process them at a throughput of 200 million samples per second, or at a 200 MHz clock rate. You can process them as fast as you want, and if you have enough buffer, also as slow as you want.
Sampling Rate and Clock Rate are not inherently linked.
Think about this in your PC: say, you have an raw PCM audio file, sampled at 44.1 kS/s. You want to encode it as MPEG 4 audio; although the piece of audio might be minutes long, the encoding process takes only seconds: it isn't necessary to bring the audio file to the "processing rate" of your CPU (whatever that rate might be – it really doesn't exist).
Same for your FPGA domain: sure, your higher-clock-domain logic will probably have to idle in between if it's fed samples from a lower-speed ADC, but that just means you can relax, and it's OK if things take more than one clock cycle per sample to work. |
H: Is there a good overview to find connector types?
While taking a look into my overheating B&O speakers, I unfortunately ripped off a connector. Now I need an exact matching replacement, but I did not find it in any online-shop by filtering.
So my more general question is: Do you know a good website/database to find out the type of a connector?
If there is none, can you help me to find the type of the connector in the image below? There are 2x10 rectangular pins with a rough 1mm pitch.
Edited: It is an DF50-20DP-1V by Hirose
AI: since you don't care about every connector that might have existed, but only those you can actually buy, the kind-of-logical-ain't-it answer to your first question (list?) is:
Go to one of the large electronic distributor's websites, click through to the connector listings, and select filters that describe your connector.
Regarding your second question (ID this connector?): a 24-contact mezzanine rectangular connector, photographed very much out of focus ;) (more pixels don't help if they aren't sharp; try photographing at a larger distance next time). I'd do exactly the same: I'd have to go to a distributor website, click through to the rectangular connectors, and peruse the filters until I found few enough potential matches. You can do the same, AND you have the connector (or its remnants) at hand, so you stand a better chance than I do to find the right connector. |
H: Is it possible to make a one-off control FET switch circuit?
I was wondering if anyone knew any circuits such that when a small voltage is applied for a short duration (i.e. 500 ms), a switch transitions from the off-state to the on-state or vice versa for all time even after the voltage ceases to be applied. Doing it as follows would not be possible since $$ V_{G1} > V_{TH} + V_{S1}$$
Is required for the NFET to be in forward-active mode, as well as $$ V_{G2} = V_{S1} > V_{S2} + V_{TH}= V_{G1}+ V_{TH}$$
So in fact
$$ V_{TH} <0 $$
Is required for the second switch to constantly keep the first switch in forward active after the signal voltage is applied.
I have tried variations of this with PFETs and combinations, but I keep running into the same problem explained above. I think that it would work with relays since their switching voltages don't depend on the voltage across the relay. But would it work with FETs?
AI: The circuit you are looking for is called a bistable multivibrator, or flipflop, or latch. It is a variation of the original multivibrator circuit, which is an oscillator. You can buy a flipflop as a low-cost integrated circuit in both bipolar and CMOS technologies, or build one with two transistors.
The basic operation is that once the input signal turns on one transistor, the second transistor works to keep the first one turned on after the input signal is removed.
A critical parameter is the amplitude of the input voltage. Anything over 1 V is easy to deal with. If you want to stay with MOSFETs, then the input must be greater than 2-3 V for most common devices. smaller input voltage changes would require an amplifier or comparator stage in front of the latch.
Another part of the design that must be addressed is how to reset the circuit from the latched to unlatched state. This can be with another signal, a switch, cycling the power to the circuit, etc.
Some of the schematics in this link are of the oscillator circuit, but many are of the latch circuit.
https://images.search.yahoo.com/search/images;_ylt=AwrE19zF3ulf0.IAzgFXNyoA;_ylu=Y29sbwNiZjEEcG9zAzEEdnRpZANDMTMzOV8xBHNlYwNwaXZz?p=bistable+flipflop+circuit&fr2=piv-web |
H: Bootstrap in power amplifier
So I know the theory behind a bootstrap current source in power audio amplifier and understand its operating principle but some things remain uncertain to me.
First - how to divide the collector resistance in voltage amplification stage? I did run some simulations and it's clear, that $$ \frac{R_1}{R_2} $$ ratio actually matters.
When \$R_1>R_2\$:
Gain drops
Crossover distortion becomes apparent (despite the biasing)
voltage across \$R_2\$ is not stable so current from current source does not maintain its value very well (unstable current source)
When \$R_2>R_1\$:
Gain raises
Less distortion
Curernt source very stable
I don't understand why it happens. From the theoretical point of view, it should not matter which resistance is bigger.
Second - how to calculate the open loop gain after applying a bootstrap? Or perhaps I should ask - what's the actual value of collector resistance then? I need this to choose the correct value of \$R_{\text{in}}\$.
Here's the circuit: LINK
Quiescent current - \$3\text{mA}\$
Desired max power - \$5\text{W}\$
Input - \$1\text{V}_{\text{pp}}\$
Total collector resistance - \$3.6\text{k}\Omega\$
AI: Take a look at this example circuit:
As you can see without any input signal (DC condition) the bootstrap capacitor (\$C_1\$) is charged to \$7.85V\$. Also notice that the circuit time constant is very large (\$t = R_X||R_Y * C_1 = 0.544s\$) compared to the audio signal period (\$1/20Hz = 0.05s\$). Thus, we can tell that the capacitor will act just like a \$7.85V\$ DC voltage source (the input signal is changing way too fast to be able to charge/discharge the \$C_1\$ capacitor).
Now let us see what will happen if the output voltage is at a positive peak and equal to \$+10V\$.
The situation is shown here:
As you can see the voltage at \$V_X\$ node is now higher than the supply voltage.
And this is why we can achieve a larger voltage swing at the output for a positive cycle.
Because now the maximum positive voltage at the output can reach:
\$ V_{max} = (V_{CC} - V_{CE(sat)}) ≈ 14.8V \$.
But we have another benefit from the bootstrap capacitor.
Notice, that now the voltage across \$R_Y\$ is almost constant and equal to:
\$ V_{R_Y} = V_{C1} - V_{BE} ≈ 7.15V \$.
And this means that \$R_Y\$ acts just like a constant current source.
For the AC signal, the \$R_Y\$ resistor is seen as a bigger resistor due to Miller's effect. But this time we have positive feedback (non-inverting stage) and the amplifier gain is less than one (voltage follower). So we called it a bootstrapping.
so, the new \$R_Y\$ value is:
$$R_Y = \frac{R_Y}{1 - A}$$
Where \$A\$ is an output stage (voltage follower) gain.
The typical value of output stage voltage gain will be around \$0.9\$. Thus the \$R_Y\$ a resistor will be seen by the VAS stage as a ten times larger resistor.
As for the selection, we typically choose \$R_X = R_Y\$ or sometimes we pick \$R_Y = 2...5 \times R_X\$ to further increase the VAS stage gain.
But the \$R_X\$ value cannot be too low because this increases the size of a bootstrap capacitor.
\$C_1 > \frac{0.16}{F_{LOW} \times R_X||R_Y}\$
Also for the AC signals the\$R_X\$ resistor will appear as a resistor in parallel with \$R_L\$. So another restriction related to the minimum value of a \$R_X\$ resistor, this is why \$R_X >> (20...100)R_L\$ |
H: LTSpice - Inductance simulation
Welcome back on this subject :
I would like to simulate an inductance which varies linearly in function of the current which flows through it. Suppose :
$$L(t) = I_{L}(t)$$
In the simulation for simplicity I used a current source which has a slope of current equal to :
$$\frac{dI_{L}(t)}{dt} = 1$$
So :
$$U_{L}(t) = L(t)\frac{dI_{L}(t)}{dt} = L(t) = I_{L}(t)$$
Finally the expression of the Flux for L should be :
$$Flux(t) = x^2/2$$
Refere to this link for the expression of the flux : LTspice - Simulation of a variable inductance
So here is the simulation :
And here are the result :
What is weird to me is that I have to add a minus sign in the expression of the flux of the inductance. Why ?
Thank you very much.
AI: Inductors have phase in LTspice. If you rotate the inductor 180°, you will no longer need to multiply by -1.
It can also be helpful to use the inductor symbol with a phasing dot. Here is the correct orientation that will remove the need for multiplying by -1: |
H: KiCAD: "Footprint has no courtyard defined" using Arduino shield template
I made an Arduino shield with KiCAD.
When I finished the board in PCBnew, I ran a design rules check.
I got "Footprint has no courtyard defined" on all the mounting holes in the shield template.
This is a picture of the PCB:
This is a picture of the errors, with the mounting holes:
AI: If you look at the other footprints on your photo, there's a thin white border around them. That's most probably the courtyard.
KiCAD uses that layer to check if two different footprints are overlapped. Edit the mounting hole's footprint, select the F.CrtYd and B.CrtYd layers and add a graphic circle large enough to encompass all the island. That will remove the warnings. |
H: Hartley oscillator and feedback fraction
Do we decrease the the feedback fraction and increase the amplification fraction if we increase the value of L2? (similar to Colpitts oscillator where we by changing C2 capacitor)
AI: if we increase the value of L2? (similar to Colpitts oscillator where we by changing C2 capacitor)
Almost -- but you want to decrease the value of L2. If you swapped the capacitors and inductors, then you would, indeed, decrease the value of the corresponding capacitor -- but inductive impedance goes up with increasing inductance, while capacitive impedance goes down with increasing capacitance.
Do we decrease the the feedback fraction and increase the amplification fraction if
It's more complicated than that. For any semi-reasonable starting point you decrease the feedback. But you don't necessarily increase the amplification -- you just increase the amplification that is needed. Just willy-nilly cutting the value of L2 (or adjusting the ratio of L2/L1 while maintaining the same resonance frequency) will eventually leave you with a dead lump of circuit that rings a bit when lightning strikes nearby but never breaks into continuous oscillation. Before that happens, you'll have an unreliable oscillator, or one with poor operating qualities. |
H: DC current source into capacitor - does capacitor voltage rise infinitely?
I would like to check my understanding.
Scenario 1 : Constant Current Source with no parallel resistance
Consider the following circuit,
I = C (dv/dt)
Since, I is constant, dv/dt should be a constant slope and capacitor voltage should continue to rise to infinity with this constant slope.
Scenario 2 : Constant Current Source with parallel resistance
In reality, the current source will have a parallel shunt resistance and as the capacitor voltage rises now due to the 1mA DC current source and through the resistor path, the voltage on the capacitor should not exceed 1.8V due to the voltage drop across the resistor? But won't the ideal current source still be driving 1mA into the capacitor and so the capacitor voltage should still be rising?
AI: But won't the ideal current source still be driving 1mA into the
capacitor and so the capacitor voltage should still be rising?
Your capacitor will charge to a voltage of 101.8 volts (eventually). This is because that is the voltage scenario that causes all the 1 mA to be taken by the 100 kΩ resistor. In other words, when there is 100 volts across the 100 kΩ resistor, the current into that resistor is 1 mA and the circuit voltages stabilize. |
H: How do you calculate negative and postive voltages in a grounded circuit?
This may be a vintage question, I'm not sure. I am self-studying electronics using some old books and came upon the problem below from "Basic Electronics" by RCA Institutes, 1965. The book is fantastic, but some of the terminology and tech is ancient. The answer to the problem in the book is as follows:
The difference in potential between points C and D is 3 Volts. The potential at point B with respect to ground is +1 Volts; at point C 0 Volts; and at point D -3 Volts.
My read of the circuit is that there are 6 volts in the circuit, but I'm confused by the ground at point C. If C is ground and ground is 0 Volts, then it would seem that 6 volts would drop between the positive terminal and point C, meaning that 4 Volts would drop between A and B and 2 Volts between B and C. Similarly, there would be a 6V drop between the source and point C going from the negative pole to ground.
Obviously, I am mistaken, but I'm at a loss as to how to analyze the circuit and pull out the different potentials. I am hoping y'all can shed some light on how they came up with their values.
AI: Ground is just our reference point, against which we measure voltages. Current is not flowing into or out of it (in this example).
Because the resistance above and below the ground point is equal, we know that current passing over these resistances will drop the same amount of voltage.
The total resistance of the circuit is represented between points A and D...this is where 6 V will be dropped.
Point C is midway through this resistance. Therefore, there is 3 V drop between A and C and another 3 V between C and D.
Using Point C as our reference for "zero volts", point D will be -3 V and point A will be +3 V. This, of course, shows our total of 6 V across the whole circuit. |
H: Usage of 3d printer hotend outside of printer
I am trying to repurpose an old hotend of my 3D printer (Link) as an improvised temporary "space heater" to raise the temperature in a small enclousure by 5-10°. I happen to have a 24V 48W power supply lying around, so that is a great fit for the 24V 40W heating tube.
For some simple testing I directly connected the two ends of the heating tube to the 24V PSU. While it worked, after a few seconds I noticed the dust on the tube burning up. Since I was testing in a safe environment I let it continue heating up and after 10 or 20 seconds the stainless steel started to glow red, so I disconnected it. While apparently in terms of ratings everything is fine (fuse of the PSU did not blow), obviously having a red hot glowing and smoking steel tube is not what I intend to have.
I remember from setting up my 3d printer that various parameters have to be configured to properly adjust the PWM control for the hotend, so I took an appropriately rated DC motor controller (VNH5019) and set it to 20% duty cycle. While it didnt heat up so fast it still started smoking after roughly 20 seconds.
I am wondering, how are those ceramic heating tubes normally wired? Heating my 3d printer up to 240° takes 2-3 minutes, the steel tube glowing means it went to like 400° in just a few seconds. Is there some current limiting normally involved? Are they running at super low duty cycle? For both of them: Why not use a heating tube that does not require current limiting/small duty cycle for the working temperatures?
AI: The power supply for the hotend in your printer may not have been able to supply as much power as your power supply. It won't try to heat up too quickly because this can cause overshoot in the temperature. It has no active cooling, so overshoot is very bad. It may also be limited for safety reasons, or to prolong the life of the heater.
Once the hotend is at or even near the set temperature, the duty cycle is very low. This is because you want your idling power to be a small fraction of your total ability to drive. This is so that the control system can quickly and accurately force the unit to stay at the correct temperature. |
H: How to view the implementation on Vivado
im very new to FPGA programming.
Is there a way to view the implementation of a digital logic design on the selected hardware device?
For example exactly how an arithmetic operation is implemented using look up tables and arithmetic circuits on the FPGA?
AI: Yes - you can select either "Open elaborated design" or "open synthesized design" followed by selecting the "schematic" option.
The elaborated design shows the result of RTL elaboration - your input HDL is parsed and lightly processed, but the schematic remains in terms of blocks such as wide muxes, wide logic functions, multipliers, etc. These do not necessarily represent physical elements -- e.g. there's no physical RTL_SUM in the FPGA fabric even though your arithmetic operation might sum a few numbers using the + operator in your HDL.
In contrast, the synthesized design shows the implementation using the FPGA elements themselves -- you will see LUTx, mux, and other FPGA fabric BELs (basic elements). This is still not a precise match -- e.g. an artix-7 will not have LUT4s (4-input lookup tables), but the implementation step will easily map the LUT4 onto the physically-present LUT6s in the fabric.
However, if I recall correctly, not all elements will still be present in the synthesized design. It will contain IBUF and OBUF elements used for the I/O pins, but implementation will perform a little more mapping, configuration, and so on.
Finally, you can use a device-level view -- open the implemented design and go to the device view. You can enable viewing routing resources using a button in the top toolbar that looks like:
You will see all of your device elements, represented on a view of the FPGA fabric itself. Note that it is likely not to scale with the physical silicon in the FPGA chip. |
H: Need pointer on designing low pass filter circuit
I am trying to design a low pass circuit for my project which can cutoff frequency of around 300 kHz. Input and output impedance is 50 ohm.
The values of R4, C3 which are part of the filter can be modified. But how do I size the component and still meet the cutoff frequency?
The circuit will be powered with an AC signal source.Purpose to is filter out all unwanted signal beyond 300kHz
Project requirement:
attenuation or gain in passband = 1.3 dB
ripple in passband for >=2nd order filters (>=0dB) = 0 ripple
stop band f-3dB = BW =300kHz
stop band f-60dB = RC filter
Source impedance= 50 ohm
Load impedance= 50 ohm
Limited to RC filter due to space constraint.
AI: To design a filter, you must specify the parameters;
attenuation or gain in passband
ripple in passband for >=2nd order filters (>=0dB)
stop band f-3dB = BW
stop band f-60dB defines order of filter needed or similar bandstop attenuation spec
Source impedance
Load impedance
In this example, a better design replaces 20 Ohm with 47uH and C = ~4.7nF . Thus attenuation in PB f = 6dB and breakpoint is at -9dB, while impedance remains at 50 Ohms to load in the passband.
Thought experiment
What happens when \$Z_L(f)=2\pi f L= R_S+R_L\$ ? for R=100 total L=53 uH and 47uH is a common 10% value. |
H: resistor package size
I am using EasyEDA to design some PCBs, and I am trying to figure out what package to use for your basic 1/4w resistor. The options are-
R-Alial-0.3
R-Alial-0.4
R-Alial-0.5
R-Alial-0.6
R-Alial-0.8
R-Alial-1.0
R-Alial-1.2
Which one is correct? Thanks!
AI: The correct footprint is the one that your part will conveniently fit into.
I'd guess that the numbers in those footprint names give the distance between pads in inches, and that "Alial" is a typo for "Axial". Based on those guesses, I would use R-Axial-0.4 for 1/4 watt resistors.
Footprint names will vary widely between different PCB programs, and will also depend on the preference of the user.
Place a possible footprint on a board, or look at it in the footprint editor, to determine pad spacing, hole and pad sizes, and other details to see if it meets your requirements. |
H: What is the internal i2c address to CAT24AA16-D
I am interested in using this eeprom for a project. I have used used I2C devices before and usually the datasheet gave the embedded address somewhere. For the life of me I can't seem to find it on their datasheet.
Anyone want to show me where the heck it is? I feel quite silly as I even tried CTRL+F to find keywords on the datasheet.
https://www.onsemi.com/pub/Collateral/CAT24AA16-D.PDF
AI: That EEPROM has a size of 2048 bytes, which requires 11 bits to address.
The datasheet states:
Thus, it says the four most significant bits of the device/slave address byte are "1010", and the next 3 bits are the 3 most significant bits of the memory address to be accessed, with the 8 least significant bits of the memory address to access in the next byte, as clarified here:
So, for example, if you want to access memory address 1365, 10101010101 in binary, the slave address byte would be 1010101X and the address byte would be 01010101. (Where X is the read/write bit). |
H: Counter Flip Flop D no sequence
I have the sequence: 0-3-1-2-3-1.
Making the table for this.
|Present state | Next state | D1| D0 |
| 0 0 | 1 1 | 1 | 1 |
| 0 1 | 1 0 | 1 | 0 |
| 1 0 | 1 1 | 1 | 1 |
| 0 1 | 0 1 | 0 | 1 |
In kmap i get :
D0 = ~Q1 + Q0.
D1 = ~Q0 + ~Q1.
But, my sequence is incorrect when I set up the circuit. What was my mistake? Thank you in advance.
*I don't know if I was clear on the issue, but the image of the sequence
AI: Your last present state in the table should be 11 not 01.
That makes
D0 = ~Qo + Q1 |
H: Powering a 5V LED strip with CR123 Batteries
I bought this 5V battery powered LED strip on amazon for a project of mine. It wants 3 AA batteries. Due to size constraints, I would have difficulty fitting in even 3 AAA batteries. However, 2 CR123A batteries would fit fine. I have heard that LED's are more sensitive to current than voltage. So should I have any problems powering it with CR123 batteries? And also would 1 (3v) or 2 (6v) be preferable?
AI: I have heard that LED's are more sensitive to current than voltage.
These are probably WS2812B LED strips. Their voltage range is typically about 4.0V to 5.5V. The control electronics probably has a similar voltage range.
Exceeding 5.5V is probably not a good idea. They will work with slightly less than 4V, but the constant current drivers may not function properly and the brightness of the LEDs may be noticeably different.
Two 3V batteries in series with a diode in series to drop the voltage slightly would probably work. These strips can draw a lot of current, a 3A diode is probably needed. |
H: Can anyone help identify this mystery integrated circuit?
These were in a box belonging to my grandfather.
I don't know if it's relevant, but he worked at a navy yard. I'm guessing they're around 50 years old. Nothing comes up on google search.
I don't know if it's even considered an IC.
The ICs have the following markings:
CTS 7118 9-43 016-824-001
AI: Most likely a resistor network. This would be an uncommon color for an integrated circuit. CTS doesn't presently make integrated circuits, but they still make resistor networks. I can't decode the part number but their numbering system could have changed in 50 years.
7118 is the date code. It was manufactured in the 18th week of 1971.
https://www.ctscorp.com/connect_product_line/resistor-networks-rc-terminations/ |
H: How does power remain constant when powering devices at different voltages?
As per the below image, increasing the voltage in a circuit with just a resistor results in an increase of current and therefore power.
However if I have a circuit where I am just powering a DC device (say a Wifi Router) which can operate on 12-24VDC, the higher the voltage supplied within that range, the lower the resulting current.
I know the power is staying constant so mathematically it makes sense. It also intuitively makes sense - the router only needs a maximum of 12W to operate, therefore the higher the voltage supplied, the lower the current that is required to generate the energy needed to power the router.
What I don't understand is what is this router doing to reduce the current at higher voltages? Why isn't it acting like a resistor?
Thanks
edit: fixed diagram, thanks user253751
AI: The explanation for the scenario you are presenting is that the Wifi router has a switchmode DC-DC converter (likely a Buck Converter) inside which converts the input voltage of 12-24V into a fixed voltage needed by the other circuitry inside. DC-DC converters have the property that Pout = Pin * eff where Pout is the output power of the converter, Pin is the input power of the converter, and eff is the efficiency of the converter. For switchmode DC-DC converters typical efficiency is 80 percent or more, and only varies slightly with input voltage. For example it might be 82 percent at Vin = 12V and 78 percent at Vin = 24V. I just made up those numbers but they are kind of typical.
The input power is probably not perfectly constant. It is probably a little bit higher at 24 V than it is at 12V because the efficiency is probably a bit lower (if it is a buck converter, which it probably is). |
H: What is the difference between package description and package option?
I am making an ECG sensor schematic on EAGLE and I am concerned if this is something I should be taking into account while designing?
AI: The last part of the part number indicates how the devices are delivered, tape-and-reel, waffle tray etc. The devices themselves are identical. There’s also the commercial vs industrial temperature range, but the footprint and function are the same for both. |
H: How critical is it to declare the manufacturer part number for a component within the BOM?
I've never seen a BOM that explicitly declares manufacturer part numbers for the components (except the obvious ones, like a microcontroller) in any kind of circuit schematics. According to my knowledge, "if part numbers exactly matches, then datasheet of the parts should exactly match and practical performances might match to datasheet or should perform better."
Lately I'm informed that this is not the case and we should provide a manufacturer part number for every part in the circuit, including resistors, capacitors and such.
I do understand that 555-X would have differences from 555, but shouldn't the exact same component codes be compatible between brands?
If not, how would I declare the minimum requirements for the components? How would a client know which parameters were important during the 555 variant selection? How would that client know why I choose for example TI-555 over the rest of the variants, so how would he or she decide if ST-555 would satisfy the circuit's requirements or not?
AI: It obviously depends from the component and what it is used for in a circuit. Take for example a simple 1k resistor in a certain package.
A manufacturing facility would have component engineers that deal with alternative parts, and since they cannot know what the resistor does in a circuit, they also have no clue what kind of resistor they should select. So if you don't specify at least one specific resistor part or multiple different specific parts, they don't take the risk and put just something there, they will ask you for instructions suggest alternatives that you must choose from.
Sometimes, it could be that any 1k resistor with 10% tolerance for a LED is fine, but if it needs to be a precision 1% resistor for some sensitive thing, it makes a difference. Also for high speed AC circuits the resistor material makes a difference, a wirewound resistor won't work while a film resistor would. For low noise a carbon resistor may be out of the question. For high pulse current applications a standard resistor is not acceptable. There are just so many different kinds of 1k resistors, even if you did state the tolerance, package, wattage, and many other things.
And no, the part numbering does not mean that chips with identical part from different manufacturers behave identically under all circumstances. There might be a reason why you chose a specific manufacturer. Or if there is not, then indicate it that it should not matter. But then you should also be sure that any manufacturer is fine, perhaps by looking at datasheets and/or testing the component in the circuit before accepting the use in design.
Sometimes even a same chip but from different batch or with different silicon revision fails to work as intended in a circuit. |
H: Why are these resistors between different nodes assumed to be parallel
I am given a circuit to simplify, and because I got stuck I looked at the solution, but it confuses me.
The circuit is the following:
simulate this circuit – Schematic created using CircuitLab
In the solution, the first step that is done is to combine \$R1, R3, R6\$ into an equivalent resistance \$Ra\$. The solution states the following:
$$ R_a = R_3 + \frac{R_1R_6}{R_1+R_6} $$
This means that \$R_1\$ and \$R_6\$ are assumed to be parallel.
Now I see that \$R_1\$ and \$R_6\$ indeed share the common node \$C\$, but \$R_1\$ lies between \$O\$ and \$C\$, while \$R_6\$ lies between \$C\$ and \$B\$.
At my knowledge-level, I would only assume these resistors to be in parallel if they shared common nodes on both sides, in this case if \$O\$ would equal \$B\$.
This is clearly not the case here. I guess I am missing some theory about resistors in parallel, or I am having some wrong assumptions.
How can it be explained that these two resistors \$R_1\$ and \$R_6\$ can be treated as parallel in this case? Any explanation, as well as references to some related theory is highly welcome.
AI: In the solution, the first step that is done is to combine \$R1, R3, R6\$
into an equivalent resistance \$Ra\$.
If you are trying to find the effective Thevenin impedance looking into nodes A and B whilst ignoring the load resistor RL, then that is exactly what you do. Trying to find an effective resistance means that voltage sources are short circuited (or set to 0 volts) and current sources are made open-circuit: - |
H: Photodiode draws current from op-amp input
I am trying to measure light intensity using a photodiode (S1336-18BQ) connected to an op-amp (LF412CP) in transimpedance amplifier configuration. I couldn't get it to work correctly, so I started searching for problems and have found something very peculiar: there is a current flowing from the negative input of the op-amp. The value of the current is the same order of magnitude as the short-circuit current of the photodiode under the same conditions (~1 µA).
simulate this circuit – Schematic created using CircuitLab
I have very little experience in analog electronics, but I understand that inputs of an op-amp (especially a JFET one) should have very high impedance. I have tried three identical op-amps to ensure that it is not just a damaged chip. Please forgive me if I am asking something obvious.
AI: The op-amp you have chosen (LF412) is unsuitable for the power supply regime you show in your schematic. The input common-mode voltage range is a couple of volts inside the power rails hence putting the non-inverting input to ground (also your negative supply rail) is a mistake - you need bipolar supplies for this op-amp.
In addition, the minimum supply recommended for this op-amp is +/- 5 volts (a span of 10 volts) and you are showing it on a single 5 volt rail: -
This op-amp won't work properly on a single 5 volt rail. |
H: Finding the cut-off frequency of a filter circuit at -3db from transfer function
I am having issue with finding the cutoff frequency from this filter circuit transfer function as i am stuck at the step shown in the picture attached. I am not sure if i have done the steps correctly so please correct me if i have done something wrongly. Thank you for your time!
Updated:
I like to apologize but i realize that i have incorrectly drawn the circuit previously which is why i was having difficulties getting the cut off frequency that i got. I have since corrected my working following Andy Aka methods and Tony suggestions . However i got a very complicated transfer function and was wondering if it could be reduced further or have i done some steps wrongly.
FACT method transfer function done
AI: I am not sure if i have done the steps correctly so please correct me
if i have done something wrongly. Thank you for your time!
I'm ignoring C3 because it's in parallel with C2 and, if you need to incorporate it later, add it to C2 when the derivation is solved. The circuit is shown below: -
A fairly easy way to solve this is to break the problem into smaller pieces by labelling the intermediary node as \$V_x\$. So, the first notable relationship is this: -
$$\dfrac{V_O}{V_x} = \dfrac{1}{1+sC_2R_2}\hspace{1cm} \text{or}\hspace{1cm} V_x = V_O\cdot(1+sC_2R_2)$$
Where \$s = j\omega\$.
The second notable relationship is the ratio \$V_x/V_I\$ but, to uncover that, you need to find the impedance (\$Z_x\$) looking into C1, R2 and C2: -
$$Z_x = \dfrac{\frac{1}{sC_1}\cdot(R_2 + \frac{1}{sC_2})}{R_2 + \frac{1}{sC_1}+\frac{1}{sC_2}}$$
The above reduces to this: -
$$Z_x = \dfrac{1 + sC_2R_2}{sC_1 + sC_2 + s^2C_1C_2R_2}$$
Then start to solve the ratio of \$V_x/V_I\$: -
$$\dfrac{V_x}{V_I} = \dfrac{Z_x}{Z_x + R_1} = \dfrac{1 + sC_2R_2}{1+sC_2R_2+ s(R_1C_1 + R_1C_2) + s^2C_1C_2R_1R_2}$$
Then, remembering the first notable relationship we can "lose" \$V_x\$ and we find this: -
$$\dfrac{V_O}{V_I}= \dfrac{1}{s^2C_1C_2R_1R_2 + s(R_1C_1+R_1C_2+R_2C_2)+1}$$
This is now in a usable form to find the -3 dB point of the filter. |
H: Is it safe to drive a 5V servo using a logic level shift board?
I would like to turn off and on a servo while it is not used. The LV would be 3.3V and the HV would be connected directly to s lithium battery. Could it work if I replace R4 with a servo? What problem I might face?
AI: Use an inverter/level shifter driving the gate of a P-channel FET, and make sure to turn the PWM signal to the servo off when you turn the servo itself off. It'll take a couple more components, but it'll Just Work.
The circuit shown uses a SOT-23 (or smaller) pre-biased transistor and fewer resistors than what you have.
simulate this circuit – Schematic created using CircuitLab |
H: RC integrator: why does it convert a triangular wave into a sine wave?
The output voltage of an RC integrator circuit is proportional to the integral of the input voltage.
This means that a triangular wave should transform into a quadratic curve (since the integral of a linear function is a parabola).
Why does it convert a triangular wave into a sine wave then? What am I missing here?
AI: So, a square wave has harmonics at all odd multiples of the fundamental, with strength diminishing as the number of the harmonic:
$$x_s(t) \simeq \sum_{n = 0}^\infty \frac{\cos 2 \pi (2n + 1) t}{2n + 1}$$
A triangle wave is just the square wave, integrated, with the appropriate constant added to make things tidy:
$$x_\Delta(t) \simeq \sum_{n = 0}^\infty \frac{\sin 2 \pi (2n + 1) t}{(2n + 1)^2}$$
A parabolic wave is the same thing, again:
$$x_p(t) \simeq \sum_{n = 0}^\infty -\frac{\cos 2 \pi (2n + 1) t}{(2n + 1)^3}$$
Because of that cubic in the denominator, the difference between a sine wave and this "pseudo-sine" wave is very small. And it turns out that it's pretty hard to see the deviation on a graph anyway.
If you plot the quadratic pseudo-sine wave on a graph, superimposed on a real sine wave, you'll see the (slight) difference. |
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