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H: AC vs DC refrigerator
I’m looking to purchase a refrigerator for my van. I plan to have an inverter installed and a battery bank. AC refrigerators are much cheaper than DC so I prefer to go that route if possible. The AC refrigerator has a power drawl of roughly 300KWA per year while the DC refrigerator drawls roughly 48W. The battery bank I’m planning is 200A at 12V and the inverter is 3000VA. Can you tell me if I can get away with the AC refrigerator and how much, if any loss I’ll be dealing with?
AI: There isn't enough information in your post to provide a good recommendation. However, I can make some recommendations as follows: a) you want to optimize power efficiency, so choose a refrigerator that is just as large as you need b) the DC refrigerator is indeed a thermoelectric-based system that is extremely inefficient and should be avoided c) you should be able to find DC, compressor-based (refrigerant) refrigerators - this is a good option d) also consider a propane refrigerator. |
H: DAC/ADC Precision & Noise: PD Resistor/Capacitor effect
I'm developing a device that utilizes both ADC and DAC, and I have realized that my DAC output, which is fed into the op amp, is de-facto almost floating, since op amp has high input impedance. Both DAC and ADC are on the MCU now (STM32G071KBT6), although for some time they were discreet components, which doesn't matter much, I guess.
I tried to google some stuff, and only found out that lines that end up with Hi-Z are susceptible for noise, which makes sense to me, but nothing more specific.
Also, some discreet DACs have max output capacitance in datasheet, which is usually of order of 1000pF, some a bit more, some a bit less (others never mention output capacitance).
I tried to google specifically my question, but couldn't find any reasonable answer.
Should I have some large pulldown resistor on DAC output to add it some stability and noise resistance? Some 47k (which are everywhere on my PCB, so another one won't hurt). Why, why not? (I would also really love to be able to go close to 0V output).
What about ADC? My ADC is fed from the voltage divider from the current sense amplifier, total resistance of that one is ~15k (5V->3V3, 4.7k/9.12k to produce 3.299 from 5V to stay in range, will have to account for tolerance too, probably in software).
If I fed my ADC (input) from op amp directly, it would create same problem as with DAC output into op amp. Would I need a pd resistor there? What about capacitor on the ADC line?
Summary of questions:
ADC input: capacitors and pd resistors? Yes/No, when, why?
DAC output: capacitors and pd resistors? Yes/No, when, why?
AI: ADC input:
The output impedance of your voltage divider is given by the parallel value of both resistors, in this case about 3.1k. This is quite a low impedance to drive the ADC, so depending on your application you won't need any capacitor. A pulldown would only load the output of the voltage divider and give you a slightly wrong reading. A capacitor to ground will form a lowpass filter with the output impedance of the divider. You can use this to filter higher frequencies to make sure you are fulfilling the nyquist criteria (sampling rate of ADC at least double of the highest frequency in the signal). *1
DAC output:
While the OpAmp input might be high impedance, the output of the DAC counts as low(-ish) impedance. It is not floating, but driven activly to the ouput voltage.
Simply placing a pull down resistor will only load the output and drop the voltage a little, but yield not much positive. Depending on your signal frequency and your DAC sampling rate you might want to place a series resistor with a capacitor to ground as a lowpass filter (also called reconstruction filter) to eliminate noise from the DAC. If you output only DC (or very low frequencies) that might not be neccessary.
Additional remark: You want your output of the DAC to go as close as possible to ground.
The DAC of your µC has an internal buffer that lowers the output impedance from something like ~18k to something between 2k and 3k. But I would not enable that in your case! You are driving a high impedance OpAmp, so you don't need the low impedance output. And the internal buffer can only go down to about 0.2V, while the DAC itself can drive the output directly to ground.
*1
Wether or not you really need a lowpass filter in front of your ADC depends a little (as it always is) on your exact specs. If the current you measure is almost constant and you are quite sure that the sampling rate of the ADC is faster than any changes in current you probably can skip it. But be aware that incoupling noise or fast changing current waveforms can lead to completly wrong measurements.
If you don't want to take that risk you need the filter. You can follow this procedure to design it:
Set the corner frequency of the filter to \$ f_c \leq \frac{f_s}{2} \$ , with \$f_s \$ beeing the sampling frequency. If your ADC takes one sample every ms, your filter has to cut of at a maximum frequency of 500 Hz.
Choose a reasonable combination of resistor and capacitor, to fulfill \$ f_c = \frac{1}{2 \cdot \pi \cdot RC}\$. Because the input impedance of your ADC is about 50k, you want the signal impedance to be not higher than about a 1/10 of that. If we set R = 5k, this gives us a C of 64nF for 500Hz. I would round to about 100nF. Because the voltage divider already gives you 3.1k you only need to add 1.9k in front of the capacitor.
The above is only a rough estimate. There are two important factors to keep in mind:
The filter has a roll-off, it does not attenuate everything above the corner frequency to 0. The further \$f_c\$ is below \$f_s\$ the better.
Even when the signal impedance is only a 1/10 of the ADCs input impedance you will get some voltage drop (signal impedance and ADC input form a second voltage divider). You have to determine how much you will allow the voltage to drop. This depends on your specs for resolution of the measurement. |
H: Op Amp with capacitive load - Peak Detector
I have been looking into peak detector circuits for something I am designing and looking through Google, the common method seems to be this:
Quite simple really. But, I have an engineer at my work who isn't a fan of this circuit because he says an op amp will struggle to drive a capacitive load, which I know is a thing. So I built the circuit and have been messing around with capacitor values and different op amps, and I can't seem to get the op-amp to start oscillating as he tells me it will. I like this circuit for its simplicity, and surely if you are careful about component selection, these things shouldn't be much of a worry? The engineer has admitted that analog design isn't their strong point, but is still unsure of this circuit.
From what I have seen, it has been used widely (although maybe not so much anymore) and during my testing, it had no problem driving capacitors into the µF range (I tested up to 4.7µF) although I should only need a maximum of 1µF, so I would think this is fine.
I did a bit of looking into op amps and capacitive loads and sure enough, op amps can go into oscillation if trying to drive capacitive loads, and these can sometimes be small values. So why does it not seem to affect this circuit? Or does it, and I am just in fact not seeing it?
Just for clarification, I am not asking for alternative circuits, I just want to know why this configuration seems to be stable with a capacitive load.
AI: I just want to know why this configuration seems to be stable with a
capacitive load.
It's a non-linear circuit that attempts to charge a capacitor when the input voltage exceeds the previously highest input voltage and, there is no basic problem here; it can't go unstable (as I suspect your engineer colleague thinks it will) because it's not a linear amplifier AND, the capacitor is only called into-action when a new high-peak of voltage arrives at the input. That occurs rarely and is of no consequence to stability.
There's a big difference between struggling to drive a capacitive load (which all op-amps suffer from to one extent or the other) and trying to remain stable in the presence of a capacitive load in a linear circuit. This rectifier circuit WILL NOT go unstable unless you have chosen an op-amp that cannot be used in linear unity gain situations (there are a few).
You do need a "light" pull-down resistor in parallel with the capacitor by the way. |
H: Why is the saturation velocity for holes and electrons comparable?
In a semiconductor like GaAs, the saturation velocity for both holes and electrons is on the order of \$10^7\$ cm/s. However, under lower electric fields E, the drift velocity of electrons is much larger than that of holes, since \$v_d = \mu E\$, where the mobility \$\mu\$ of electrons is much greater than holes. Why then are the saturation velocities comparable?
AI: In different semiconductors, different mechanisms are primary drivers of velocity saturation.
In materials without accessible higher bands (Si) this is inelastic scattering of charge carriers with the emission of optical phonons of energy \$E_{optic}\$. This mechanism predicts the saturation velocity \$\sqrt{E_{optic}/2m_{carrier}}\$, \$m_{carrier}\$ is an effective mass of electron/hole. In silicon, effective masses of electrons and holes are close to the free electron mass (\$1.08m_0\$ and \$0.81m_0\$, respectively), and the saturation velocity values are close for both quasiparticles.
In gallium arsenide, the quasi-electron effective mass (\$0.067m_0\$) is seven times less then the hole effective mass (\$0.47m_0\$). This low effective mass achieves for GaAs quasi-electrons a higher saturation velocity value (as compared to Si) at moderate electric field strengths. Notice that, because of much higher mass, the hole velocity at the same moderate electric field strengths is not saturated. This is the reason why we do not have a GaAs analog of Si-MOSFET devices.
As electric field strength grows higher, another mechanism of velocity saturation comes into play and not only brakes the velocity increase as phonon emission does, but even decreases the velocity values. Because of the band interaction, the quasiparticle's dispersion curve (energy vs. wave vector) is no more parabolic, in contrast to simple dispersion curves for free particles (\$ω=\hbar k^2/2m_0\$). As electric field strength grows higher, the impact of this non-parabolicity on the quasiparticle motion becomes more pronounced. At the electric fields high enough, the velocity asymptotically approximates its saturation value \$v_{sat} \sim Wa/2{\hbar}\$, where \$W\$ is the width of the energy band and \$a\$ is the semiconductor lattice constant. As you see, this value does not depend on the quasiparticle effective mass and is identical for both electrons and holes. Notice once more, this explanation is only acceptable for materials with accessible higher bands.
This answer in no way pursues the goal to be essential for your education. I only hope that it provides you with keywords for searches of textbooks and papers on the subject. |
H: Difference between the two Ethernet magnetic topologies
Background
Hello, I'm building up a PCB for a PoE module based on Microchip LAN8720 IC. The recommended schematic is shown in the following figure.
I built up a prototype based on the Waveshare LAN8720 board. This Waveshare board uses an RJ-45 jack with magnetics integrated. The jack they used has a wiring as shown in the following figure. Obviously it doesn't support Power over Ethernet (PoE) with all the spare pins tight together, I had to pick a jack that supports PoE. So I made a decision to use an RJ-45 jack without magnetics and have the magnetics on the outside.
However, I made a mistake in the schematic by not connecting one of the center tap coils (ones next to the common-mode choke) together. (elaborating more on this: the two center taps should be connected to a 75 Ohm resistor each and ground through a 1000pF 3kV capacitor according to the recommended schematic in the figure above. This was the same setup the RJ45 jack with integrated magnetics have. Instead, I omitted this part by mistake and only connected them to the diode bridge for PoE). So the prototype does not work.
Question
I noticed this mistake while I was debugging the circuit and I found several RJ45 jacks with PoE enabled magnetics integrated. (Was too late..) However, I saw a difference in the wiring between PoE enabled jacks and the normal ones. The figure below is a jack with PoE capability and the center taps are first connected to capacitors and then to 75 Ohm resistors (C first then R). This is quiet different from the recommended (R first then C) layout.
My question is, is there a difference between these two topologies (C first then R) and (R first then C).
Intuitively (R first then C) topology used by the normal topology (without PoE) creates a conductive path between the two taps. Is this something to do with power delivery?
-- Update
Question in summary
What could be the difference in these two topologies marked with red boxes? Is there any underlying theory behind the difference? (Thanks @Jason for the insight on power wastage if the PoE topology had resistors connected creating a DC path)
AI: The topology that does not support PoE can have a DC path between center taps, and the resistors at the center taps are for common mode termination. There is no need for the capacitors to break the DC path. A PoE source that detects if the device supports PoE will see that the device has DC termination between pairs and will refuse to give power out. A passive PoE injector that always supplies power will damage the resistors.
The topology that supports PoE must not have a DC path between center taps. A PoE source would properly detect this and passive PoE injector will work too with this device. The resistors will still provide correct common mode termination impedance. |
H: Laplace Domain Representation for Phase Detector
I am trying to model an LTI system and determine the overall transfer function of the system. The setup consists of a laser signal being fed through some filters, amplifiers, etc. represented by transfer function 1 (TF1) which is then mixed with a local oscillator by a phase detector. This mixed signal passes through a few more components represented by transfer function 2 and is then used as an output signal.
The trouble that I am having is with the representation of the local oscillator in the Laplace domain. The mixed signal leaving the phase detector is given by $$U_m = K[\theta_{m}(s)] = K[\theta_{lsr}(s) - \theta_{LO}(s)]$$
Where $\theta_{m}(s)$ is the phase difference between the two signals of the phase detector. How would I represent this phase signal from the local oscillator in the Laplace domain?
simulate this circuit – Schematic created using CircuitLab
AI: If I understand your question correctly, you have two signals having different phases, and you need them translated into Laplace domain:
$$\begin{align}
a(t)&=K_a\cos(\omega_a t+\phi_a)\tag{1} \\
b(t)&=K_b\cos(\omega_b t+\phi_b)\tag{2} \\
\mathcal{L}\Bigl\{a(t)\Bigr\}&=K_a\dfrac{\cos\phi_a s-\omega_a\sin\phi_a}{s^2+\omega_a^2}\tag{3} \\
\mathcal{L}\Bigl\{b(t)\Bigr\}&=K_b\dfrac{\cos\phi_b s-\omega_b\sin\phi_b}{s^2+\omega_b^2}\tag{4}
\end{align}$$
The signal is (3)-(4), and if the frequencies are different it will be a 3rd order transfer function, otherwise it all reduces to a simple difference. |
H: Where are document options in altium 2020
I switched to altium 2020 and I can't find the document options dialog that was previously available in "design / document options". I want to set parameters like in the screenshot (altium 2017).
How should I do?
AI: Open the document you want to see the options for. Open the Properties Panel and go to Parameters. |
H: DS18B20 - is current consumption of pullup resistor relevant for battery powered project
In my project, I'll be using a DS18B20 digital temperature sensor, which requires a pullup resistor of around 4.7k between VCC and the signal.
Please see the datasheet here for reference.
Is there any current flowing over that pullup when my MCU sleeps and no measurement is performed with the DS18B20.
Basically, I have the same general question for I2C sensors, do those regularly draw current or just during operation?
AI: Current exists when there is voltage difference. If you pull a line up to 5V and it sits there, there is no current (ignoring nanoamp or picoamp leakage and stuff). When line goes down in, for example, I2C, then the line is at 0V, but the other side of pullup is still at 5V, so there is current through the pullup. It's important to know the state of the pins when MCU sleeps, which I don't know. If the pins are input during sleep, you can treat it as no current. Which is likely, but you will probably need to measure voltage across pullup resistor when MCU sleeps.
I would expect it to NOT consume any current, but you have to either find or explicitly set pin states in/before sleep mode using datasheet and/or measure voltage across pullup (0V will mean no voltage difference across pullup and thus no current). |
H: Not accurate readings when connecting OpAmp AD822 to ADC MCP3008
for my project, I am using a photodiode, that I connected to the AD822 OpAmp. This OpAmp should then be connected to the MCP3008 ADC. I am reading the data from the MCP3008 with a RaspberryPi. I am however getting weird readings from the ADC. I guess that this is because there is some sort of fluctuations in the voltage coming out of the OpAmp. Below there is a diagram of my wiring as it currently is (I am using the negative side of the 9V battery as ground):
I use single supply voltage for the OpAmp, as I do not have the possibility of dual supply.
If I try to measure the Voltage across the 10kOhm resistor with an multimeter, I get a value of 0V. However, according to my ADC the Voltage input Voltage fluctuates between 0 and 1.7V.
Now, if I disconnect the ADC and remove the 10µF capacitor and connect the 10kOhm resistor directly to ground, I get readings with my multimeter of 0.04V with ambient light and about 05.V if I put my flashlight over the Photodiode. So it seems to be working like that
Am I wiring something wrong? Are my capacitors or resistors wrong / at the wrong place?
Here are the datasheets:
Datasheet Op Amp; Datasheet ADC
Thank you in advance!
EDIT after jusaca response:
EDIT with Solution:
Jusaca, thank you for the decoupling advice and the relation between Rf and Cf.
I have worked on it more and finally realised what the last error was:
I had to connect the negative side of the 9V battery to the ground of the MCP3008 and to the ground of the RaspberryPi. So connecting the entire "ground" side (the bottom line in my diagram) to both the negative side of the battery and the ground of the RaspberryPi and both grounds of the MCP3008! :)
AI: The voltage over the 10k will always be practically 0V, because no current is flowing in the ADC input. You have to measure the voltage over the capacitor (meaning from ADC input to ground) to see the same voltage the ADC is seeing.
The fluctuations you see in the ADC signal indicate that the OpAmp is not in stable operating conditions. As Andy mentions in the comment: You need to decouple the supply voltage with something like 100nF between V+ and V- as close as possible to the supply pins of the OpAmp. This gives a low impedance path for the supply current.
Another common cause of instability with transimpedance amplifiers is a lagging phase due to the capcaitance of the photodiode. If the phase lag approaches 180° the negative feedback becomes positiv feedback and the amplifier may start oscillating.
To compensate for that a feedback capacitance \$C_f\$ is placed in parallel to \$R_f\$. In your case that is the 1300pF. How did you get that value? You need to know the capacitance of the diode as well as the GBW of the OpAmp to calculate a matching \$C_f\$. You can read the details in this TI paper Compensate Transimpedance Amplifiers Intuitively, but the short form is:
\$ C_f = \frac{1}{4 \cdot \pi \cdot R_f \cdot GBW}[1 + \sqrt{1+8 \cdot \pi \cdot R_f \cdot C_D \cdot GBW}] \$
So if your feedback capacitance varys to much from the ideal value that might be the cause of the instabilities you see. |
H: Full-bridge output doesn`t work as expected
I am making a half-bridge amplifier and successfully managed to amplify a sinusoidal wave (simulates a sound signal). When amplified it has almost 100V of amplitude. It has a inductor and a capacitor to create a low-pass filter.
+Sine waveform plot:
After that I duplicated the entire circuit and made some changes to act as the other side of a full-bridge. Basically I just inverted the signal.
It works fine and the -Sine signal has the same amplitude as +Sine but it is inverted.
The following plot displays both outputs.
My plan was to put both outputs into a resistor (simulates a speaker) and it would have a 200V amplitude.
I know those values might not be realistic but at the moment I just want to understand why my assumption doesn`t happen.
When I put both signals into a resistor the amplitudes goes to 120V instead of 200V.
If I plot +Sine and -Sine we can see that they no longer reach 100V.
They now reach 60V each.
Does anyone knows why this happens?
EDIT 1:
I tested a suggestion and deleted the 5ohm resistors. I also change the load resistance to 5ohm.
Unfortunately the voltage at the resistor still has a 120V amplitude.
EDIT 2:
Issue solved and explained by the solution comment from @aconcernedcitizen. I just needed to recalculate my filter values using half of load resistance.
AI: You need to remove the previous loads and redesign your filter. The initial values of 39.8u and 1.6u are for a filter with Q=1 (note: underdamped), considering a load of 5 Ω (V(i)). Combining them into a bridge results in the inductors and capacitors being in series, thus the equivalent values will double for the inductors and halven for the capacitors. The output load will have to be doubled if you want the same response (V(a2,b2)).
If you leave the previous loads there while adding the 8 Ω load, the equivalent load will be the two 5 Ω loads in series, all in parallel with the 8 Ω, or about 4.44 Ω. Combine this with 2*39.8u and 1.6u/2 and you get a filter with a Q=0.446, which is well overdamped (V(a,b)).
If you remove the 5 Ω loads and leave the 8 ω, without modifying the LC values, you get a filter with a Q=0.8 (V(x,y)), and only if you change the load to be 10 Ω you will have the original Q=1 (V(a2,b2)).
Finally, if your intention is to have the load 8 Ω and the filter with Q=1, then you have to recalculate the LC values to be L=31.8u and C=2u (V(p,q)). |
H: 14500 vs 18650 charge circuit
General question: Is the charge circuit/protection circuit the same for a 14500 and 18650 cell?
(I assume so because of the same nominal voltage, but wanted to make sure)
My specific case:
https://www.waveshare.com/wiki/Solar_Power_Manager <- This charge circuit is for 14500 cells, but could i use it to charge 18650 cells with a different batteryholder?
AI: The schematic for that module is here: https://www.waveshare.com/w/upload/d/d2/Solar_Power_Manager_Schematic.pdf
I admit I'm a little concerned looking at it. I only spent two or three minutes looking over the design, but:
The schematic in general looks pretty sloppy, it's pretty clear that the designer was new to Altium (for example: M1 is a dual MOSFET, but has been drawn as a box)
The designer has specified a maximum power point tracking (MPPT) chip (Consonance CN3791) but has not connected it properly. As per the datasheet, the MPPT pin should be fed by a divider from the solar supply, but instead it is grounded through a 10k resistor. This means the MPPT feature won't work.
The designer has, for some reason, placed an LED and resistor directly in parallel with the battery. Thus, even if the battery protection trips, this LED will still be connected to the battery and continue to draw current. Left for long enough, this could over-discharge and permanently kill the cell.
Anyway, yes, you can use this circuit with a 14500. Depending on the recommended charge rate of the 14500 you may need to change the series resistor, though. R1 and R3 in parallel set the charge current. Their equivalent value is 0.11 ohms, so as per the CN3791 datasheet, the charge current is set at about 1.1 amps (\$I_{CH} = \frac{120 mV}{R_{CS}}\$).
The typical 14500 has somewhere in the neighbourhood of 1000 mAh capacity, and the usual recommendation for most lithium ion batteries is to charge at 0.5C max or around 500 mA (consult your specific cell datasheet to confirm). I'd suggest depopulating either R1 or R3, which would set the shunt resistance to 0.22 ohms and thus your charge current to about 550 mA.
EDIT: Sorry, I guess I misread your question. I just saw that this is the reverse case, this charger is designed for a 14500 and you want to use it with an 18650. In that case, yes, you can go ahead and do so without modification (other than the battery holder). I would not change the shunt resistance at all, since around an amp is pretty much perfect for the typical 18650. I'm surprised they are marketing it as a 14500 charger with an 1100 mA (~1C) charge current, that seems a bit irresponsible. |
H: Visualize the Arduino PWM's output by means an oscilloscope
I'd like to visualize the PWM signal from an Arduino Uno board with an oscilloscope.
I'd like to use this layout:
Is this a safe connection?
In other words, might I have problems because the oscilloscope and tha PC's PSU share the same earth ground?
I need to connect the Arduino to the PC by USB cable because I need to run software from the PC to the Arduino.
Update:
I've connected the oscilloscope and it works fine.
When I change the duty cycle percentage (from 0% to 100%) in Matlab/Simulink I can see it directly on the oscilloscope.
AI: Yes, this is exactly how the equipment are supposed to be connected.
Earthed/grounded PC, earthed/grounded scope.
Safest for you and the probed equipment, there is no danger of damage.
Even better if both the PC and the scope are connected to same dual wall socket or same power strip, so it can be sure that they are grounded at the strip or wall socket, instead of long wires within the wall if they are on separate wall sockets. It also guarantees that they are powered from the same mains fuse and mains phase. |
H: Do I need to use a diode when combining two usb 5 volt lines?
I want to use a USB bus powered device with my laptop. However, it draws to much current from the laptop and won't work. Do I need to use a diode(s) if I solder another 5 volt line powered by a wall wart to the original cable?
AI: Yes, you can't connect the two 5V sources directly in parallel. You must somehow isolate your laptop power from the separate power supply. |
H: What does "Driven low/high" mean in terms of electronics?
I keep seeing in specs/manuals to drive a pin high or low, what does that really mean?
For example I'm working with a voltage regulator that has an ENABLE pin that says will switch the board to a low power state when "Driven Low".
AI: You have to read (and sometimes interpret) the datasheet. For a voltage regulator with an ENABLE input (as opposed to an /ENABLE input) the ENABLE input has to be high to enable the regulator. We know that.
What we don't know is what voltage we must apply to the ENABLE pin for it to interpret as a high reliably. We also don't know what happens if we leave the pin open. If there is a specification for "leakage" on the ENABLE pin of << 1uA and no other information we can assume the ENABLE input is very high-impedance and it needs to be connected to something. And we don't know what voltage we must apply to the ENABLE pin for it to interpret as a low reliably. And we don't know the limits of voltage we can safely apply to the pin.
You may also care if there is some hysteresis, how much etc.
If the allowable input voltage includes the maximum Vin for the regulator we can simply tie it to Vin or use a transistor and pullup resistor to switch it. The maximum value of the pullup resistor will be determined by the leakage or internal bias current from the input and practical factors and by the required Vih. If the Vih is low enough (as it often is) we can control it directly from a CMOS output (like an MCU GPIO pin), and we don't need to level shift it up to some fraction of the input voltage. But that needs to be checked.
Take, for example, the HX9193 low power CMOS regulator (any images from datasheet).
This tells us that the regulator will shut down if the pin is left open.
The three columns are labeled min/typ/max here.
The ENABLE pin must be < 0.4V to have the regulator off. Since there is a nominally 1M\$\Omega\$ resistor to ground, we can't inject more than 400nA (and given tolerances, 100-150nA would be a better limit) if we want it to reliably remain off.
To have it turn on, we need to apply at least 1.4V, but we can apply any voltage from 1.4V all the way up to Vin + 0.3V. So we can connect this pin directly to a 3.3V or 1.8V CMOS output and have it control the regulator. The output will sink no current when low, and when high will source a few uA at most. Perfect.
Now compare the TI LP38855 (any images from the datasheet)
Here we see that current is flowing out of the ENABLE pin. That means that if you leave it open the regulator will turn on, opposite of the other part.
We need to give it 1.55V to have it turn on reliably (bold is over temperature) and must pull it down to less than 30mV to have it turn off reliably. Elsewhere it says we can apply 0 to Vin to the ENABLE input (and that it will "survive" 6V under absolute maximum ratings). The latter could be an important rating if Vin could occasionally be 0V while your GPIO is outputting 3.3V.
So we can connect the ENABLE input to a CMOS output 3.3V etc. but it must not drop more than 30mV when sinking 51uA. That's not a really tough requirement, but if the layout was quite bad there could be 20 or 30mV along a trace. The TI part is a much higher current (and 50x more expensive) device, but it would typically be used in something with multilayer boards. |
H: Designing a circuit that outputs variable voltage
Total noob here, I'm looking to implement a circuit to control a fan that has these specifications:
Pin 1 and 3 are DC-
Pin 2 is DC+
Voltage should be from 6 to 16 V
It needs to operate in 70-second cycles
So let's say we're only giving it 6V. For 70 seconds we need to output 6V between pins 1 and 2, then next 70 seconds 6V between pins 3 and 2.
I'm thinking of using simple voltage dividers with resistors for the variable output part, for example 6 resistors and switches for 5 different outputs. Then, using an astable vibrator (relays, capacitors, resistors) for switching the potential from pin 1 to 3.
I'm not sure yet what to use to control the voltage, maybe Arduino but I guess it will come down to switches anyway.
Am I talking nonsense? Is there a right/easier way to do this?
AI: Voltage dividers don't work if the circuit is supposed to provide at least some power. Either the output voltages will vary under load, or you won't find suitable/affordable resistors that can take the power they'd need to dissipate.
A clean solution is to use a variable voltage regulator and feed its reference voltage with a potentiometer (or a digital pot or a DAC if you want to control it digitally). Cheap variable voltage regulators exist on beginner-friendly breakout boards and I suggest you try one of those.
If you understand how your model works, you can replace the potentiometer with a resistor ladder and switches if you prefer discrete voltage levels. |
H: Artifacts in transient analysis
Is there some rigorous treatment of convergence issues in transient analysis?
I am using LTSpice. In transient analysis with maximum time-step is used. Fundamental oscillatory frequency of analysed circuit is under 100MHz.
I undestand that implicit trapezoidal integration can produce nonphysical ringing. On the other hand Gear algorithm of a given order introduce damping which is also nonphysical. So I tried Gear, trapezoidal and modified trapezoidal implicit integration schemes implemented in LTSpice.
But none of the methods can eliminate these micro-transients.
they look like this
and also note, that they start to showing up after some time.
But I have suspect these are not real oscillations. With Gear I got less of these events.
It is quite simple model of circuit with ideal components (low damping). Its unlikely that real-world circuit will have similar properties, but since I am processing large amount of such transients in Matlab, I need to be sure that I can remove these (using wavelet transform reconstruction for example) as they have no significant effect and are purely numerical product.
What is your rule of thumb for situations like this? Whenever modeled circuit contains LC tanks with much lower frequency than its artefact?
EDIT
Using equivalent series resitance of 0.1 ohm for shunt capacitances still produce these transients. One can be spotted right on the startup
AI: First and foremost: SPICE is a numeric solver and all its models only approximate their real life counterparts, if modelled. What you have there is a MESFET which can only try to come close to some real-life counterpart, but who has two of the parameters null, and a bunch of LC filters that, most likely, have no parasitics modelled/added.
Next are the values: nH, pF, and ms simulation time. Now, that's not a problem in itself, you can simulate until the end of time, but it's about the dynamic range involved. You have time constants there that are many magnitudes smaller than the simulation time, and an imposed timestep of 1 ns, which is comparable to the LC values: sqrt(125n*50p)=2.5n.
At this point, I have to ask: what is your purpose when simulating this circuit? I see no startup, no uic, no initial conditions, and all the sources are DC. Yet you are simulating a heavily filtered circuit. If the operating point is what interests you, .OP will do. If a dynamic behaviour is what you're after, then DC sources can hardly be called dynamic.
At any rate, if accuracy is needed, then you need some 1k ... 10k times less time resolution, at least. That means 2.5 ps ... 0.25 ps or less. Are you sure you want to simulate for 10 ms like this?
Why do those oscillations appear? Numerical accuracy, and chaos. Think Lorentz attractor. You have complex feedback in a very complex schematic (transfer function wise). Combine that with nonlinear elements and you get a possible oscillator. Use them with a very linear (and quite ideal) LC network and you get a simulation that can go fast, unless a timestep is imposed -- in this case, 1n is not enough. All you have to do is run the circuit for long enough.
As for the various solvers, the two main contenders are gear and trapezoidal. Gear typically has very strong damping, and it's used where parasitic oscillations are of not needed. It will damp even your ideal LC oscillator. It's inherently stable, which means using it to simulate oscillators is not such a good idea. Maybe switching applications, if transients are of no importance. Trapezoidal is meant to try to reproduce as accurately as possible for a 2nd degree implicit solver, even at the cost of oscillations. And these will come if proper conditions exist: a high order LC network, multiple feedback paths, an uncontrolled timestep, these can contribute.
But, again, your circuit doesn't make sense to be simulated for 10 ms with DC sources. Either choose .OP, or .DC, or use other types of sources that add some dynamics and make sense for choosing .TRAN.
PS: I didn't try to reproduce manually your schmatic. If you can post the source, I'll give it a try, but you have to say first what is the purpose of the simulation. |
H: What kind of diode should I use?
What type of diode is best to use when I want to minimize the voltage drop in a 5V DC circuit with about 1500 milliamps in a THT form factor?
AI: Based on the minimal information given I would probably pick a low Vf Schottky diode rated for at least 10V and 3A. But beware the leakage current if it's important to you.
It's hard to recommend a specific part because we have no idea of your mounting preference, physical constraints, cost goals etc. |
H: Help understanding wiring of capacitor
I just wanted to double check my understanding of the diagram as in my mind the "visual clues" related to the way the cap is drawn seem to contradict the actual instructions of the diagram.
If this capacitor only had 2 connectors on it would it be correct to wire the neutral (black) terminal to the neutral (black) wire?
From a logical POV would I have a single connection joining neutral black, neutral terminal and capacitor to the 1 leg of the capacitor, and the capacitor/grey wire to the other leg?
Another, simpler way of asking this - should all the black wires be connected together on 1 terminal and the grey one on the other?
Assuming the aerator to be a standard single phase AC motor, if the connection is fused (and has an RCD on it), and if the wiring were round the wrong way, would turning the motor on simply trip the fuse or could it damage the motor or capacitor?
In the picture of the Capacitor below, the 2 lugs on the left are connected together and the 2 on the right. (This looks to me to be 90 degrees to the way it has been drawn in the diagram)
AI: Looks like this is what you have there. As long as you have the capacitor in series with at least one motor winding, you should damage anything. If you look at the top terminals on the capacitor, you should see that they make up a small terminal block on each side. This is often used as a way to eliminate the need for additional connectors. In you case, it looks like this is done on the neutral side. Take care when working with mains power. Safety is your friend.
simulate this circuit – Schematic created using CircuitLab |
H: Polarity issue in JFET transistor
I'm wondering what determines the polarity conditions in a JFET - is it that this transistor can only operate when the p-n junction is in reverse biased polarization? If so, what about the states of operation that the transistor can be in? There are three of them, and the polarization mode is only one. Don't they result from additional polarity conditions?
While browsing through various books as well as websites, I came across a statement that says:
"JFET Transistors can only operate with a reverse bias of the p-n junction, so there is only one way of polarization":
-n-type junction
\$ U_{DS} > 0, U_{GS} < 0 \$
-p-type junction
\$ U_{DS} < 0, U_{GS} > 0 \$
But I have also encountered the definition that:
"Depending on how the unipolar transistor is polarized, it can operate in three different areas:
in the cut-off area - when \$ |U_{GS}| > |U_{P}|, U_{DS} \$ - any
in the active region - when \$ |U_{GS}| < |U_{P}|\$ and \$ |U_{DS}|\$ <= \$ |U_{DS} SAT| \$
in the saturation area - when \$ |U_{GS}| \$ < \$ |U_{P}| \$ and \$ |U_{DS}| \$ > \$ |U_{DS} SAT| \$ "
And it says that these areas of operation are methods of polarity at the same time (or more precisely, areas of operation are associated with different methods of polarity, but there is, after all, one) - I completely don't get that!
These definitions are confusing to me. So which one of them is correct? Is there one way to polarize as in the first definition? Does the second definition fit more with the ways of polarity? Could someone please clarify this for me?
AI: Seems to me that you have seen a translation error. It's not that JFETs are 'prohibited' to be polarized, it's just reverse biased. Well, if you bias it directly it doesn't work…
The JFET is a depletion device and in fact it 'pinch off' (block the flow of the current) when the gate is at some voltage below the source (for the N-channel, how much is part dependand). Your second definition has the absolute value signs because for P-channel most signs are reversed.
By the way, be careful: the saturation zone in a FET (junction or MOS) is completely different than the saturation of a BJT (in fact, it's its linear zone…). It's a bad naming that confuses a lot of people.
Up (or Vp) is the pinch off voltage, the threshold of total depletion. If you reverse bias the gate over that, no current passes (there's always some leakage and parasitic stuff, but that's the idea). When the channel is open, the Uds (Vds) determines the kind of response it has on the signal (mostly if amplifies or works like a variable resistor, read the rest of your page) |
H: op amp random pulsing to ground
I have simple circuit with ada4891 op amp. I am using it to demodulate ASK modulated signal. But sometimes op amp is pulsing to ground for no reason. These pulses are short (about 1 us). I have oscilloscope up to 100 Mhz but I did not measured anything on input or in power supply rail. It just randomly jumps down. And now when I am measuring it again it is working normally, but I am scared it will start again. Could you help please? Do you know why it is happening? I have MCU 1.5 cm above. Could MCU somehow disturb op amp?
This is my schematics:
AI: It can be difficult to find random 1us interference particularly when you don’t know where to look.
When this happened in my early days to me I looked around and saw my temperature controlled Weller soldering iron and with a quiet click sound of a relay, I said, that’s it! Radiated EMI pulse from a dry contact inductive load during turn off with dt approaching zero except for air gap capacitance.
Your supply filtering has a ridiculous amount of filtering so the cabling might make the difference on ground shift noise, but the line side mass massive inductance. This of course doesn’t work without some series DCR coil resistance of a few Ohms and with just that R, you don’t need the inductor when your load is on the order of a 1k Ohm. In theory with an ideal L that would produce a Q of 1000 at a couple hundred Hz, which isn’t possible maybe a hundred or so. but that can’t possibly create a 1us pulse, but if you had some motor noise on the supply, it would ring at that frequency and be amplified by 40dB or so with this high Q series LC circuit. So I would prefer a cost reduction and a 1st order RC filter or CMOS LDO if necessary from unknown noise levels but this can be managed by knowing your PSRR and all your load ripple. |
H: Kirochoff's current law on Transmission line equation
In the figure above, for equation 2.1b i.e applying Kirchhoff's current law, why is not the resistance and inductance taken into consideration?
AI: In equation (2.1b) all the terms are current.
There are 3 currents and there is no need to include resistance and inductance because the current through them is known i.e. i(z,t) |
H: LED strip heating troubles
I bought a cheap LED strip and a 12V 5A power supply unit on Aliexpress. After testing it I realised that the LEDs closer to the PSU end get quite hot (around 55°C) while the ones at the other end of the strip don't get hot at all. I'm a bit worried that continuous exposure to this kind of temperatures might change the colour of the paint on the wall over time.
I measured the open circut voltage output of the PSU and it turned out to be slightly higher than it should be (12.2V), so I thought I could lower the voltage a bit by adding a couple of diodes in series with the strip.
I went to the local electronic parts shop and they sold me FR302 diodes which are rated at 100V 3A. I added 2 in series and indeed all the LEDs now are now cold to touch without noticeably losing in brightness. I measured the voltage drop and it turned out to be 0.8V across each diode, and the current drawn by the strip dropped from 1.1A to 0.9A, but here comes a new problem: the diodes get really hot (79°C according to my multimeter).
I can't find much in the diode's datasheet about how hot it should get in these conditions. I can see that it can operate in the -65..+150 range, but my question is: is it normal for the diodes to get this hot in these conditions? Can I avoid it by using a different type of diode? Should I use a different method of lowering the voltage altogether?
I'm also worried that some of my measurements might be wrong, because according to the description on Aliexpress:
Power Consumption (W/m): 7.36W/m
Which I thought should mean that the strip draws 7.36 W/m / 12V * 5m = 3A, whereas I can only see 1.1A on my mulitmeter. Am I wrong in my calculations?
AI: The "wires" on the strip are just thin flat printed circuit board strips, so they lack the plumpness that you need. You can make all the LEDs heat up equally by hooking up the positive at one end and the negative at the other end of the strip, or you can reduce the currents on the super thin built in wires by tapping power in at several places over the length of the strip. The latter is generally the better option although if you wanted to be a snob you could split the strip into multiple sections and do both.
As far as the voltage rating of your LEDs, you have voltage rated LEDS, which waste a bit of power by using a resistor to regulate current per series string. 12.2V isn't far enough over 12V that you'd be putting the LEDs at risk(especially if you add wiring to feed them properly as that lets them age the same), but underpowering them will actually increase their operational life as long as brightness is still adequate. As you've been finding with your diodes, dropping the voltage by wasting the extra power is a non ideal plan. The power your diodes waste is equal to the voltage drop over them multiplied by the current, and with 0.8V over each diode and a significant current, the diode is heated considerably. You need to either cool the diode or divide the wasted power between multiple diodes so each doesn't heat up too much. A better way would be to decrease output voltage, perhaps use a dimmer driver. Your diode can survive the thermal abuse for some period of time, but it's lifetime will be shortened the hotter it gets. |
H: How do I find the power absorbed from the current sources without voltage sources?
Given this circuit, how do I determine the power absorbed from the dependent current sources? I figured out, through KCL, that \$R_{\text{a}} = 4/3 \Omega\$, \$R_{\text{b}} = 6 \Omega\$, \$R_{\text{c}} = 24/7 \Omega\$.
What I'm most confused about is given that P = IV, how can I figure out the voltage of each current source?
AI: First, your numbers for the resistances are all incorrect. Try again.
Secondly, the power is just voltage * current. Use KVL to find the voltage across each current source. For example, the 3A source has 12V + 4V = 16V. The power is thus 48W.
You must pay attention to the polarity. In this case it is 48W produced by the current source. If the voltage was in the opposite direction relative to the current direction the power would be absorbed by the current source. |
H: How do I find R without knowing anything about it?
Given this circuit, how do I find \$R_1\$ and the gain of the gain G of the voltage-controlled current source if \$V_2 = 8\text{ V}\$ and the 20 V voltage source supplies 4 W of power?
I tried using the current divider formula to find \$R_1\$ but ended have having a negative resistance, so I'm pretty sure it's wrong.
AI: Proceed step by step.
Having v2 gives the current in the R1 branch so you can deduce R1 since all voltages are known.
Then having the power you get the total current and you can deduce the dependent current source and so on. |
H: Custom wave frequency for car radio
My car radio doesn't support Bluetooth and I am wondering how to solve this problem so I can play songs from my phone.
The first idea that came to my mind is obviously just to buy a new radio.
However, I am wondering, just for the sake of having fun with electronics, if it was possible to somehow generate radio waves in the frequency range of the car receiver so I could for example connect my phone with an Arduino (e.g. via Bluetooth) and transmit audio in a custom frequency so the car would receive it as if it were regular radio station.
Is this, in theory, possible?
AI: ... if it was possible to somehow generate radio waves in the frequency range of the car receiver, so I could for example connect my phone with Arduino (e.g. via Bluetooth) and transmit audio in a custom frequency so the car would receive it as if it were regular radio station.
Arduino will not help you here. It doesn't, on its own, do Bluetooth, audio or radio frequencies. Its processor is too small and too slow.
Figure 1. Random Bluetooth to FM transmitter from Light in the Box.
These types of devices are readily available and usually contain a Bluetooth receiver and FM transmitter. The one pictured also features USB charging ports and a digital display of the FM channel selected and what appears to be a hands-free phone interface. |
H: LM317 - Why could I not get more than 200 mA from the output?
My task is to heat a coil, with a resistance of approximately 0.8 ohm. I need to make a constant current source to make it work correctly. I want to use LM317T as a constant current source, but I could not get more than 0.2 A. Even when R1 is a 1 ohm resistor. I am using this schematic.
Can you help me please?
AI: You need to add up 3 voltage drops:
The voltage the LM317 needs to work
The voltage across the reference (1.25V for the LM317) which is also the voltage across R1.
The voltage across the 0.8 ohm load.
If you are using a 1 ohm resistor, you are expecting 1.25A, so the 0.8 ohm load will drop 1 volt. The LM317 requires 3V to work. So you need a minimum input voltage of 5.25V at 1.25A.
Note that the LM317 has very poor efficiency in this application. 1.25W is getting to the load, but the input power is 6.5W so the efficiency is < 20%. With a higher than the absolute minimum input voltage it's even worse. The LM317 will need a heat sink to dissipate the several watts safely as well.
If you're making a vaping device, I suspect there are a lot of working circuits out there that will be better. |
H: Do the ground marks in these two circuits have different meanings?
The diodes in both circuits are ideal. I drew the circuit on the right to make a comparison. As the answers given for V and I in the circuit on the left are 1 V and 4 mA, this means D1 and D2 are not conducting while D1 is. I have not really seen a ground mark placed beside the circuit, so I can't be sure what it means. I can only guess, according to the given answers that it means the whole branch D1 is in is connected to the ground, thus meaning there is 0 voltage across D1, is that so?
AI: Look at this,
simulate this circuit – Schematic created using CircuitLab
When on the left you have a full schematic and on the right a simplified one.
And this means that your right schematic is wrong (not equivalent with the left circuit).
simulate this circuit
And here you can read about GND
How to find Voltage based on reference nodes? |
H: 7408 quad-AND with diode latching: sporadic (and undesired) self-latching at power up
As an introduction to electronics, I am still working my way through Charles Platt's Make: Electronics (2nd edition).
This issue is about Experiment 21: A Powerful Combination
In circuit on figure 4-107, a 7408 (quad-AND) is used to implement a simple switch based "password system". The different switches have to be pressed in a given sequence, each switch allowing to change the output of a AND gate to high, thus latching this AND and providing a high input to the sub-sequent AND gate.
(I suppose I am not allowed to post the circuit schematic from the book, as it might be copyrighted material?)
Minimal example
I have been having problems with the resulting circuit sometimes starting in the "unlocked" state, without having to first press the correct sequence of switch. By fault tracing with a voltmeter, it appeared that, sometimes, the different gates are latched in high-output at circuit startup.
Here is a minimal example showing the latching for a single AND gate:
And here is the corresponding schematic (my first, please be indulgent):
simulate this circuit – Schematic created using CircuitLab
About 1 in 5 times when applying 5V to the power bus, the low-power yellow led will light up, without having to first press the switch.
Questions
What could cause this undesired (and erratic) self-latching at startup?
Is there a design flaw in this circuit? (or is there an obvious wiring error in my attempt to build it?)
The book is using 74HC08, where I am using 74HCT08N. Can it lead to the problem?
AI: The power-on state of such a circuit is indeterminate and I'm surprised that this book you're referencing doesn't explain that.
While in the real world, circuits tend to initialize in a certain state MOST of the time, as you've seen, from time-to-time they don't. Why depends on many factors including power supply rise times, any residual charge in circuit elements from the last power-up, and just random processes.
The solution, if you need it to ALWAYS initialize to the same state, is to generate a power-on-reset using a suitable circuit. That will guarantee that it always comes on in the state you desire.
Your circuit is very confusingly drawn but is essentially this:
simulate this circuit – Schematic created using CircuitLab
This design relies on at least one of the inputs to the AND gate being LOW at power on so that the output will also be LOW. But with all digital logic parts there are "undefined" regions where the behavior is unspecified. At power-up this is where you are.
To address this you need to ENSURE that at least one of the inputs is low and one way to do that is by adding a capacitor in parallel with R1. The voltage across a capacitor will be 0V at power on and that will force the output of the AND gate to be a logic 0.
Try something like this. The value of C is not all that critical, try the 10pF and if that doesn't give you the behavior you want, experiment with some other values. |
H: TPS61046 wrong output voltage and high current consumption
I am designing a circuit to control a multiplexed led matrix and for that I am testing two boost circuits. The TPS61046 and the TPS61080.
My idea is that the input voltage is via USB or a Li+ coin cell (probably Li-ion@3.7V).
The attached schematic shows the power supply stage, the ground is common between both boosts but only one is energized at a time and the other is kept disconnected. (possible first error)
Since my priority is to run the TPS61040 due to its size and better performance in the current range I require (10 - 30 mA) I will focus this question to the error I get from it.
When I test its operation supplying it with a laboratory power supply set to 3.7V max 0.1A I get the consumption of 2.4V@0.097A, that is, the TPS61046 is consuming -IMO- an excessive amount of current. I must say that the loads so far have been three leds in parallel, each with a 400 ohms resistor and the other was an Arduino mega. I havent conected the whole circuit due to potential smoke risk.
In the attached picture you can see the PCB layout I made, R10 and R20 are not connected and R21 is a 0Ohm 1/4W resistance, this way FB with Vin ar directly connected, thus 12V can be obtained only with 3 components C_in(C6&C7)= 2x1uF, L(L2)= 10uH, C_out(C5)= 10uF (Datasheet 9.3.1).
Something that can cause another failure (possible second error) is the distance of C_out (C5), which maybe should be closer to Vout, but even so, I think the effect should be reflected in the ripple and not in the difference of the voltage I get to the desired one.
I have checked the continuity between all the pins and the TPS is well soldered. GND-Vin diode shows 0.5V (possible third error). I will also do a re-work on the inductor to be sure there is no short underneath.
Wrap up: Using the TPS61046 I want to get 12V output but I am getting a lower value with a very high current consumption.
SOLUTION: IC wasn't able to start up. By increasing the current limit a little it worked flawlessly.
Thanks, @Andy aka
AI: When I test its operation supplying it with a laboratory power supply
set to 3.7V max 0.1A I get the consumption of 2.4V@0.097A, that is,
the TPS61046 is consuming -IMO- an excessive amount of current.
If your output voltage is meant to be 12 volts and feeding 3 parallel LEDs each with a current limiting resistor of 400 Ω then, each LED will take a current of approximately 10 volts ÷ 400 Ω = 25 mA. With three parallel circuits, that's a loading current of 75 mA.
So, that's an output power of 12 volts x 75 mA = 300 mW.
That's going to require an input power of about 333 mW (taking into account an efficiency of 90%).
So, if your input voltage is 2.4 volts, the current needed from that supply is going to have to be at least 139 mA. Hence, you have set your current limit too low in value for this circuit to start up properly.
Maybe you need to re-examine you current limit setting and be a bit braver.
Also, your L2 inductor; it doesn't look like you fitted the correct one as per your data sheet link. The DS implies a footprint size of 2 mm x 2.5 mm yet, in your picture it looks a little small. |
H: MOSFET R_ds(ON)
I was reading through MOSFETS, and the most prominent parameter is drain source "on" resistance. I am unable to figure out what it is. suppose for a given gate source voltage V_GS we have applied a drain-source voltage which brings saturation to the MOSFET, at this point still the MOSFET approximately works as a resistor? if not what is the resistance between source-drain now? is source drain resistance is only applicable for the linear region only? or is it for any region?
AI: the most prominent parameter is drain source "on" resistance. I am
unable to figure out what it is.
Here's a MOSFET characteristic from wiki: -
Note where the saturation region is and now, if I focus on the linear region (not the saturation region), I can show various values of on-resistance in orange: -
Basically, on-resistance is the slope of each blue curve close to the origin of the above graph.
at this point still the MOSFET approximately works as a resistor?
It's not perfect but, providing your expectation of "linearity" isn't too high, then, in the linear region, it behaves like a voltage controlled variable resistor (where the slope of each orange line above is measured in ohms). |
H: Why can the DLC (data length code) be 0 in CANBUS?
In a lot of document I found out that the DLC can be from 0 to 8, but they don't say what purpose is of DLC being 0.
AI: There are a couple of cases where this is of use.
Keepalive. If there is no data that actually needs to be sent but an indication that a node is active.
Trigger. If a node requests a certain type of data from another node, a specific ID is all that is required for a node to then transmit the needed data. |
H: Can I replace one with the other? L7805CP, L7805CV
Are those chip equal in a circuit?
L7805CP, L7805CV
Can I replace one with the other to try to fix a broken circuit board?
AI: The difference is in packaging. The L7805CP on the left is an all plastic package. the L7805CV, on the right, has a metal tab.
As long as your application doesn't depend on the ground connection on the metal tab, it should work. |
H: I2C Master and Multiple slave configuration: How to cut off capacitance of unused I2C devices
For my application, I plan to use around 5xI2C devices that are wired to one Master device over a cable length of around 1-2m for each (so 10m in total), I can use a low pullup resistor of around 1-2kOhm to battle the parasitic capacitance.
Is there a chance that I do a sort of multiplexing and cut off the capacitances of the unused slave devices? I just want to read out one device at a time.
This I2C Multiplexer PCA9543A seems an option for my needs, please see the datasheet:
Capacitive Load Sharing - Adding more I2C and SMBus devices
on the bus may exceed the 400 pF limitation. The
multiplexers and switches can isolate devices that are not
currently needed to reduce the overall system loading and
maintain the total system load below 400 pF. When active,
the channels act as a wire and the cumulative capacitive
loading of the upstream channel and all active downstream channels
must be considered.
References:
I2C capacitance problem discussed on stackexchange
8 Channel I2C Multiplexer
Adafruit 8Channel Multiplexer
AI: I can't imagine that a device/chip will have an input capacitance any greater than typically 10 pF so, the majority of the capacitance of the system will arise due to the cabling. You can approximately say that cable has 100 pF of capacitance per metre and so 2 metres of interconnecting cable will roughly be 200 pF.
Is there a chance that I do a sort of multiplexing and cut off the
capacitances of the unused slave devices?
If you are that close to your system having problems with too much capacitance, you should try a different approach. 5 devices of (max) 20 pF each is only 100 pF. The cable will be about 200 pF and, the generally accepted capacitance limit for I2C is 400 pF. You should be OK without multiplexers. |
H: Difference in noise levels between inverting and non-inverting inputs of LM386
An article on Hackaday claims that the inverting input of LM386 is less noisy than the non-inverting one:
We’ve also noticed, and we’re not alone, that the inverting input seems to be less noisy than the non-inverting. See how the datasheet applications ground the inverting input (pin 2) and put the signal into pin 3? Do exactly the opposite and you’ll reduce your noise floor even further.
I'm wondering if this is really true, and if so, is this a peculiarity of this particular chip or manifestation of some more general rule?
My understanding of electronics does not allow me to draw any conclusions from the equivalent schematics provided in TI's LM386 datasheet :
Does it sound plausible? Is there a way to measure this in 'home conditions' (i.e. without expensive equipment, oscilloscope and multimeter only?)
AI: Signal to noise ratio at the output of an amplifier circuit depends on:
The noise figure of the chip (stated in the datasheet at a given bias point)
External network (designer needs) which fixes the gain
Temperature
To answer your question:
One can't say that that the inverting input is less noisy.
It depends on the bias point of the chip and on the voltage gain. |
H: Does the STM32F103C8T6 blue pill chip require external resonators?
I am designing a custom PCB with the bluepill MCU, which I want to program over ST link and SWD, which external resonators are a must?
In the standard version, it comes with 32kHz and 8MHz:
https://easyeda.com/r3bers/STM32F103C8T6-Test-Board
EDIT: I only want to use SWD programming (so no USB) and read an ADC signal each min.
More references on this question are provided here:
Link1
Link2
AI: If you just want to load firmware into flash and read ADC then external clock references are not necessary. The chip will work with internal clocks during JTAG/SWD programming and running your firmware. |
H: Configuring the unused pin in CPU
I have just started designing the embedded systems. While designing the CPU and thinking from the reliability point of view I actually had few curiosities
For the unused pins which are tied up to Vcc using a pull up resistor - Lets say there is and fault and we have two conditions a) that is in floating state b) if its short then tied directly to Vcc. I would like to know the effect of both this conditions on the working of CPU and system?
Similarly for the unused pins which are tied up to GND using a pull down resistor - Lets say there is and fault and we have two conditions a) that is in floating state b) if its short then tied directly to GND. I would like to know the effect of both this conditions on the working of CPU and system?
I am using SM320F28335PTPMEP microcontroller for my purpose.
AI: I think your cases 1a and 2a are the same thing.
If the pin is configured as an input, then shorting it to either Vcc or GND is pretty harmless. If it's left floating, then you will get an indeterminate result in reading the pin. The pin will be vulnerable to ESD (electrostatic discharge), but that's unlikely to matter so long as the board isn't touched.
If the pin is configured as an output, leaving it floating is harmless. Forcing it to either Vcc or GND could damage the microprocessor.
Of course, if your board is so poorly made that the pull-up or pull-down resistors are either missing or shorted out, then you probably have much bigger problems to worry about. |
H: Operation of the current limiter circuit
I have been trying to understand the current limiter circuit design. I am having problem decoding them. Could anybody help me understanding this circuit?
Here I_VCC_AUX is 12 V and R247 comes from a monostable multivibrator circuit and the output goes to actuator.
AI: Note the red arrows I've added: -
Because there will be approximately one forward diode drop (0.6 to 0.8 volts) across R243, there has to be a current flowing through R243 that cannot exceed approximately 0.7 volts ÷ 0.5 Ω = 1.4 amps. Hence the circuit current limits at about 1.4 amps.
The signal into R247 is used to turn off the pass transistor i.e. it acts like an enable input. |
H: Confusion - ideal transformer on load
When there is no load connected to the secondary, E is equal to U, and no current flows in an ideal transformer. Now if we connect a load on the secondary of a transformer, the primary will draw a current because E<U (temporarily), why when E gets equal to U the transformer will still be drawing a current "I1" from the mains, doesn't that violate the reason current started flowing in the first place?
I know that the secondary field must be counterbalanced at all times by the primary field, but I have a confusion about the fact that even though there is no potential difference because E=U there is still a current flowing.
Can anyone explain that? And please correct me if I am making any thinking errors.
Image from: DC Machines and Transformers by K Murugesh Kumar
AI: I have a confusion about the fact that even though there is no
potential difference because E=U there is still a current flowing.
The induced voltage is in series with the inductance of the winding and, given that the induced voltage is exactly the same as the applied voltage, there is, in effect, zero volts across the primary inductance. Given that an inductor's inductive reactance is zero when 0 volts is applied to it, the current that flows is this: -
$$\color{red}{\boxed{\dfrac{0 \text{ volts}}{0 \text{ ohms}}}}$$
This is an indeterminate quantity and rightly so.
In other words, for an inductor, you cannot say that zero amps flows just because there is zero volts across it. Another example is the current in an inductor when the applied voltage is a sinewave: -
I've drawn purple circles on the above graph (taken from here). Those purple circles are placed to coincide with the applied voltage across the inductor equalling zero - what do you notice about the current? It's not zero of course.
Another example; take an inductor and applied (say) 1 volt to it then remove it from the supply and instantaneously short it out - does the current fall to zero or does it continue to flow. It's the latter of course and this serves to remind us that the current flowing in an inductor has little to do with the applied voltage currently present.
This however, is always true: -
$$\boxed{V = L\cdot\dfrac{di}{dt}}$$ |
H: Why do we need NMOS transistors for NAND gate?
I have a hard time understanding how gates are built from CMOS transistors. For example, I don't understand why do we need the NMOS transistors if the PMOS transistors will already produce the desired outputs?
if X or Y on both PMOS transistors is 0 , then both transistors will be open and the output will be 0 because there will be no flow of the current
if one of the inputs X or Y will be 1 , then one of the switches will be open and there will be current flow, so the output will be 1.
it is only when both X and Y are 1 the current wont flow.
so, why do I need the NMOS transistors at the bottom then???
AI: if X or Y on both PMOS transistors is 0 , then both transistors will be open and the output will be 0 because there will be no flow of the current.
The output will not be '0', it will be floating.
That will leave any connected devices with a floating input and very susceptible to noise.
The connected devices also have input capacitance and these need to be discharged to drive the inputs to logic 0.
For high-speed logic the inputs must be switched quickly. The way to do this is to pull high and pull low directly.
Figure 1. Note that if we leave X and Y floating that it may be possible for the inputs to float to a stage where both the NMOS and PMOS transistors are partially on resulting in "shoot-through". In this state enough current passes through the devices and they heat up and can burn out. |
H: Best Practices for Using Brass Standoffs Electrically?
I'm working on a project where I am trying to eliminate some cable assembly and connector costs. In my particular project I happen to have three brass standoffs that join together two boards. Board one is the mainboard, containing the power, mcu, and so on. The board I am joining to is essentially a single channel touch sensor. Right now I use JST connectors to get the job done and they work great, but add connector and cable assembly costs. I am contemplating just using the brass standoffs as the electrical connectors (already need to be there) and adding copper pads to both the boards to get the job done.
I understand people do this sort of thing but in researching mechanical solutions it looks like I'd just end up adding cost in terms of washers, since they have to be brass too and are not exactly cheap (washer suggestions welcome, btw) and they bring their own problems.
Is it a terrible idea to try and solve this with some loctite or hot glue? The design won't be subjected to extreme vibration or anything like that.
In general, is using standoffs electrically to be avoided? I would appreciate any sage wisdom on this topic.
AI: It is quite common to connect to chassis trough these connectors, so why not a signal? I kinda like the idea. Integrety-wise it would be a bit shady when considering return currents, current loops and that kind of thing, but as long as you factor that in it could work.
Star washers has been mentioned; I would never ever use star-washers anywhere near a PCB. If used on a PCB it will just dig through the copper, so that will not at all be helpfull. Any star-washer will create a fine metal dust during vibration. Needless to say that can be lethal for a circuit even if the star-washer is on a mechanical assembly nearby. What you want is a copper-beryllium crinkle washers, and probably an ENIG surface-finish on the PCB.
I am not sure if brass is the most ideal standoff material, but how worried you need to be on oxidation depends on the enviorment. |
H: Small-signal output resistance of MOS common-source stage with source degeneration
This is a bit of a long question so bear with me.
In chapter 3 of Razavi's Design of Analog CMOS Integrated Circuits, he introduces the CS stage with source degeneration. He draws the small-signal model and says that the output resistance is as follows (Eqn 3.65):
That makes complete sense to me and I am able to derive that via the small-signal model. Next, Razavi provides another technique to derive the same small-signal output resistance without drawing the small-signal model but rather incorporating it with the large-signal drawing as a means to quickly inspect circuits and gain some intuition. To do this, he applies a ΔV and measures ΔI as shown below,
I understand how he has transitioned from Fig 3.30(a) to (b) and to (c). My confusion is regarding the final step where he calculates the output resistance itself,
I can understand what he is doing but what I don't understand is that as soon as he simplifies the circuit to Fig. 3.30(c), we have a circuit that comprises only of resistors.
Why can you not simply at this stage (Fig 3.30(c)) just write that,
$$ R_{out} = r_o + Rs||\frac{1}{g_m + g_{mb}}$$
Why does this not give the same result as Eqn 3.65?
AI: You are just measuring the total output resistance, in the absence of any stimulus, but the book says (and shows) that you are using \$\Delta V_{RS}\$ as the output of the \$\Delta V\$ input. Which means what you've written is just the denominator. You now have a resistive divider formed by the equivalent \$R_{in}=r_o\$ and \$R_{out}=R_S||\dfrac{1}{g_m+g_{mb}}\$, the latter being the one with \$\Delta V_{RS}\$ across: \$\Delta V_{RS}=\Delta V\dfrac{R_{out}}{R_{in}+R_{out}}=...\$ (I'll let you fill in the blanks; hint -- look at eq. 3.69).
$$\begin{align}
R_{eq}&=R_S||\dfrac{1}{g_m+g_{mb}} \\
&=\dfrac{R_S}{(g_m+g_{mb})R_S+1}\tag{1} \\
\dfrac{\Delta V_{RS}}{\Delta V}&=\dfrac{R_{eq}}{R_{eq}+r_o} \\
&=\dfrac{R_S}{(1+(g_m+g_{mb})R_S)r_o+R_S}\tag{2} \\
\Delta V_{RS}&=\Delta V\dfrac{R_S}{(1+(g_m+g_{mb})R_S)r_o+R_S}\tag{3}
\end{align}$$
This leads to 3.70 and onwards. |
H: Ethernet UTP cable test device, protection for PoE and signal voltages
I’m thinking about designing a device/tool for UTP cable related testing/tracing using an MCU. I just would like to experiment with some ideas involving wire measurements, tone measurements etc. (so not using a PHY, just using my own signaling). But in a live environment (not just having a single cable for yourself) where you could plug-in to a connection that is connected to the network (by accident) I wonder how to protect against voltages present on a live network connection.
So, under normal conditions I would have a cable all to myself (measuring from one side and having some supporting satellite device or resistor network on the other side). But choosing the wrong port by accident in the field is what I’m afraid of (or want to protect against).
As far as I understand the data signals are in the range of -1 to +1 V (2V common mode per pair). And there could be a PoE voltage offset (48V) present.
If a possible PoE power source (PSE) on the line doesn’t detect a magic resistor value (which I will not provide), will it not switch on PoE? So, will I be safe and not have 48V on the line to my device?
Is there also a similar mechanism for the data signal (i.e. if it does not detect a valid communication partner will it not try to put a data signal onto the line)? Or do I have to be prepared to get a signal with an amplitude of 2V?
In other words, do I have to worry about voltages/signals on the wires that could damage my device/MCU and also (!) could I damage other equipment when putting low current, low voltages (or AC signals) on wires when accidentally (not intended) connected to other equipment?
Should I have precautions in place to avoid either of these cases? And if so, is there a simple way to detect that I connected my device to a harmless unconnected cable to do my thing?
AI: It's not in general possible to "sniff" a twisted-pair Ethernet link without disrupting it, or at the very least it adds lots of unnecessary complication. All you want to is to test cables, so let's focus on that. But we can definitely add some bonus features: link discovery is not hard to implement and could be done without using an actual Ethernet PHY.
The scenario where you connect the tester to an unused/disconnect cable run is the baseline. At the minimum you'll want to protect the tester from electrostatic discharges and transients induced into the cable from neighboring mains circuits, or potentially even lightning. And you'll definitely want galvanic isolation at least matching that of the typical network equipment, and for that the best bet is to use what Ethernet nodes use: a 10/100BASE-TX transformer, also called "10/100BASE-TX magnetics".
The magnetics can be attached the RJ-45 jack on your board. Or you can get those two integrated together - transformer inside the jack - called, aptly, a magjack. The transformer isolation provides a potential (galvanic) barrier, but you still need ESD protection, and for that you'll want to look up Ethernet-specific ESD protection solutions, or design one yourself. An existing application circuit (from a datasheet/appnote for an Ethernet PHY) may be a good starting point, and you might end up using it as-is. This would be one example - ESD312 suppressors are used on the secondary side of the transformer, and LC03-3.3BTG suppressors are used on the primary side.
At this point, your device is isolated from DC potentials, so even if there was any PoE voltage present, nothing much will happen. Of course, you could detect PoE PSE (power sourcing equipment) if you wanted to. But that's optional.
The secondary sides of the magnetics (transformers), where a PHY would ordinarily attach, are center-tapped, so you can produce pulses of either polarity using a unipolar supply. That's enough to implement cable-testing functionality: you can transmit a waveform, and receive it, and you can also use an analog input on an MCU to measure the amplitude of that waveform. Since the Ethernet signals are DC-free, there's a minimum allowed frequency to use here in order not to saturate the magnetics. Typically, the magnetics specify the insertion loss from 100kHz up, and also specify their inductance at that frequency, so using a test frequency of 0.1MHz and up would be a good idea, although less may work too (e.g. 64kHz) with higher loss and at a lower maximum current. Of course you'd be terminating both the transmit and receive pairs, so you need to keep that in mind when looking at amplitudes: your driver won't be an ideal voltage source, and most MCU pins are inherently current-limited CMOS drivers and act like current sources.
Now, if you want to detect a link partner, look up the details about so-called link pulses in the various IEEE802 specs - those for 10BASE-TX, 100BASE-TX and 1000BASE-T, you can get an idea of the link partner detection and negotiation of capabilities. Your cable tester could, with probably nothing more than Arduino Mega or Zero, do link negotiation using the relatively slow link pulses, and provide information about the capabilities of the link partner. You could also detect a twin cable tester on the other end of the link, and provide extra capabilities that way - for one, you'd already use an established communications protocol (link autonegotation) that's designed specifically to allow extensibility. You could also detect modern PoE PSE (IEEE 802.3at), since it can be detected over that same digital channel.
To recap: you likely would want to implement a "bog standard" 100BASE-TX circuit up to where an Ethernet PHY would attach (be it a dedicated chip or one integrated in an MCU), and then decide on what to use for the PHY. With a bit of creativity you could probably make the cable testing and link detection/setup work using just the "raw" pins on an MCU, with no active external components, given that modern MCUs have reasonably strong pin drivers, analog inputs, and have timer functions plenty able to receive or transmit link pulses.
You could also use an MCU with a built-in Ethernet PHY, and just do normal link negotiation using that - then your cable tester could not only detect link partners, but could also do actual data transmission tests and detect error rates and such. Since you'd be likely limited to 100BASE-TX speeds that only use 2 out of the 4 pairs, to test all pairs you'd need to detect a twin cable tester of yours (they can be identical), re-negotiate the connection after two pairs are tested, and settle on using the other two pairs. For that, you could use a digital signal switch chip and effectively connect the PHY to the other two pairs. Note here that gigabit (1000BASE-T) magnetics support all 4 pairs for data transmission, while fast ethernet (100BASE-TX) magnetics support usually only two pairs and you would need two of them to use all 4 pairs.
On that note, to test all 4 pairs, you need either:
An RJ-45 jack and two discrete 100BASE-TX magnetics (transformers), or
A 1000BASE-T magjack, or
An RJ-45 jack and 1000BASE-T discrete magnetics.
Speaking of PoE, it wouldn't be a concern unless you wanted to detect the presence of a PSE (power sourcing equipment), or unless you were connecting to powered switch ports that use "legacy" or "dumb" power injection, i.e. not according to the IEEE802 standards. This is sometimes used for security cameras and other devices where due to cost considerations a compliant PD (powered device) implementation would not be feasible. For many such schemes, it's sufficient to use a simple "DVM front-end" without galvanic isolation (DVM stands for Digital VoltMeter). I.e. you'd use a resistor network and some protection components similar to those in digital multimeters to scale the differential voltage between any two center taps on the primary side of the magnetics and feed them to either a stand-alone differential ADC, or to the MCU, while taking care to ensure that the common-mode range on the A/D side is not exceeded. The easiest way to do it may be with reed relays or opto-mos switches, where GND (0V) and ADC-IN (scaled) would be attached to any two pair center-taps.
You'd want to use PoE magnetics or magjacks then, since those are designed to allow terminating all the signal pairs while allowing there to be a DC potential between pairs, and they also provide connections to the center taps of the transformer primaries - since PoE is "sent" down the wire as common-mode potential differences between pairs.
Conformant (i.e. standard) PoE is "inert" until the PSE detects a suitable PD, so if you detect no incoming power but a link partner is present, that would mean that if they are PSE then they are conformant, and then you could look for modern PSE through the autonegotiation channel, and perhaps fall-back to the 802.3af "simple resistor" PD indication. I don't recall offhand whether an 802.3af PSE needs to inform the link partner digitally about its capabilities - if it does, then you could basically forget about it until you get autonegotiation working and determine PSE only at that level. It also depends on how featureful you want your cable tester to be. It's not hard to have some resistors plugged into the circuit using opto-mos switches or similar, so pretending to be a simple PD is not hard. |
H: How to draw sprites using DMA2D with transparency using stm32?
I am using STM32F429I-Discovery board I want to draw sprites on TFT-LCD with transparency on top of background image , I used black color as the transparent color for the images that I want to draw and used DMA2D at blending mode but the black color is not transparent and the sprite was drawn with a black color surrounding it.
the sprite color mode is RGB565 (I have tried ARGB888 also with no hope) .
The code:
void DrawSprite(uint32_t img , uint32_t SprNo , uint32_t w , uint32_t h , int format){
/* Configure the DMA2D Mode, Color Mode and output offset */
Dma2dHandle.Instance = DMA2D;
Dma2dHandle.Init.ColorMode = DMA2D_RGB565;
Dma2dHandle.Init.OutputOffset = 240 - w ;
/* Foreground Configuration */
Dma2dHandle.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
Dma2dHandle.LayerCfg[1].InputAlpha = 0xFF;
Dma2dHandle.LayerCfg[1].InputColorMode = format;
Dma2dHandle.LayerCfg[1].InputOffset = 0;
if(SprNo == BACKGROUND)
{
Dma2dHandle.Init.Mode = DMA2D_M2M ;
}
else
{
Dma2dHandle.Init.Mode = DMA2D_M2M_BLEND ;
/* Foreground Configuration */
Dma2dHandle.LayerCfg[0].AlphaMode = DMA2D_NO_MODIF_ALPHA;
Dma2dHandle.LayerCfg[0].InputAlpha = 0xFF;
Dma2dHandle.LayerCfg[0].InputColorMode = DMA2D_INPUT_RGB565;
Dma2dHandle.LayerCfg[0].InputOffset = Dma2dHandle.Init.OutputOffset;
/* Configure DMA2D Stream source2 address */
WRITE_REG(Dma2dHandle.Instance->BGMAR, (uint32_t)RenderBuffer);
}
/* DMA2D Initialization */
HAL_DMA2D_Init(&Dma2dHandle);
HAL_DMA2D_ConfigLayer(&Dma2dHandle, 1);
if(SprNo != BACKGROUND)
HAL_DMA2D_ConfigLayer(&Dma2dHandle, 0);
/*DMA2D Transfer Start*/
HAL_DMA2D_Start(&Dma2dHandle,(uint32_t) img, (uint32_t)RenderBuffer, w, h );
HAL_DMA2D_PollForTransfer(&Dma2dHandle, 100);}
AI: Neither of the pixel formats you've used so far (RGB565 and RGB888) have Alpha values, so the DMA2D will not treat any of them as transparent. A pixel value of 0 is black, not transparent, so black is what you see.
If you want individual pixels to be transparent when you're manipulating them with the DMA2D 'ChromeArt' accelerator then you need to use a pixel format which includes an Alpha value like ARGB1555, ARGB8888, etc - and set the Alpha value to 0 for the pixels which you want to be transparent.
Your other option is to use the 'Color Keying' feature of the LTDC Display controller - this does not require your pixel format to have an Alpha value, but does require that you use 2 framebuffers in RAM - one for the foreground layer (where you'll place your sprite(s) and another for the background layer.
To do this you would choose a particular color value as the transparent pixel value, and configure the LTDC_L1CKCR (Foreground Layer Color Keying) register for that color.
Then when the LTDC module builds the 'final' image by merging the foreground layer onto the background layer it'll ignore all foreground pixels with that color and show the background pixels instead. |
H: Understanding why an OPA27 is unsuitable for a window comparator and a MC1458DR is better
I'm a junior electronics engineer and have a question about a window comparator circuit I've built:
Circuit Explanation:
The op amps have a tight reference voltage on their non-inverting terminals. U1A pin 3 is set to 5.025V with precision resistors and U1B pin 5 is set to 5V.
The inverting pins of both op-amps are tied to a 0-10V input signal that varies depending on an external system.
The outputs of both op amps are tied to the LED of an opto isolator (U1A output = Anode of the opto-isolator, U1B output = Cathode of the opto-isolator). When the input of the external system providing the 0-10V signal is in the window of 5V - 5.025V, the opto-isolator will be active as U1A pin 1 will be high and U1B pin 7 will be low therefore pulling the opto-isolator to ground.
The Problem:
I originally tried using 2 x OPA27 op amps instead of a dual package MC1458. When I initially tested the circuit, the opto-isolator would not switch and the voltage on the inverting terminals of the OPA27 devices started to "follow" the 0-10V signal (by this I mean as the voltage on the inverting terminals swung linearly between 0-10V, the non-inverting terminals no longer remained at their fixed precision voltages as defined by the resistor ladder).
My question is why did the OPA27 not work in a window comparator configuration while the MC1458 has no problem? The MC1458 is not a comparator. It is, much like the OPA27, a general purpose op-amp. They both have similar Common Mode Rejection but I can't seem to understand why the MC1458 is better for the job (and ultimately, why the MC1458 worked but the OPA27 did not).
Any help would be greatly appreciated - Apologies in advance if anything similar has been asked or if this is a really rookie question.
AI: Understanding the datasheet specs incl. Absolute Maximum and schematic is essential, takes time and well worth the effort.
The lack of input resistance reduces noise and the clamping of inputs protects them from damage as Vbe = -5V reverse max. But it is possible to protect the inputs other ways allowing +/- 30V differential input. |
H: Difference between surface current and current density?
Actually my problem is with the direction of both. I use CST to simulate a patch antenna. I guess that current density is the classic vector field \$ \mathbf{J} \$ (A/m^2) and actually follows the direction of the E-field. In my case, the patch antenna is placed on the yz plane. The current density direction according to the simulation is towards x-direction. On the other hand, the surface current has a completely different direction, actually towards y-direction. Practically, it follows the direction of the input transmission line of the patch antenna. Can you explain to me why they have a completely different direction?
AI: Surface currents and current densities are caused by different effects, so they can be different. Here are some notes:
Current density at DC aligns with electric fields, but at higher frequencies it gets more complicated since time and spatially varying magnetic field also affects current density.
Surface currents are caused by discontinuities in the magnetic field between interfaces (see https://en.m.wikipedia.org/wiki/Interface_conditions_for_electromagnetic_fields).
That said, it's not obvious to me why they would point in different directions, just that it's possible they do since they are caused by different (and complicated) interactions between electric and magnetic fields inside and outside of the antenna.
Adding to that, patch antennas are "weird" in that the dipole or loop is not obvious because there's typically a grounded plane behind them with equal and opposite current, essentially cancelling out the magnetic field and making electric fields confined to the dielectric between the antenna and ground plane. The trick is that the edges have fringing fields that extend out into space that radiate (see https://www.antenna-theory.com/m/antennas/patches/antenna.php). Which, as a receiver, are the fields that couple to the antenna.
So I'm not totally sure of why it would happen in your case, but that there are reasons why it could happen. |
H: Using a ferrite core transformer as an inductor for a boost converter
I am trying to make a boost converter.
I'm stepping up 5V to 12V.
I have all the required components, including a power MOSFET(IRLZ44N), a Schottky diode (SR260) and an astable multivibrator that produces a 71.4kHz square wave for my MOSFET.
I just don't have an inductor, but I have a small ferrite core transformer in my parts bin. I got the transformer from an old SMPS that uses one power transistor to step down the AC.
If I use the secondary winding (winding with low resistance) as an inductor:
Will it work?
Will there be a high voltage at the primary that is unconnected?
The boost converter has a feedback. Will this damage the transformer?
Will my MOSFET and diode get damaged?
AI: Will it work?
It will work as an inductor. However the amount of energy it can store will be a tiny fraction of that a proper inductor of the same physical size can store, because the core is ungapped, built for high permeability rather than high energy storage. You'll need to measure its value to see if it's suitable for your design. Measure the value at a range of currents, you may be surprised at how low the saturation current is. At the saturation current and above, the inductance collapses to a very tiny fraction of its low current value, which could cause a damaging current to flow in your driver.
Will there be a high voltage at the primary that is unconnected?
Yes, the voltage will be proportional to the number of turns on the winding. Having an open circuit high turns winding on the same core will reduce the SRF dramatically from what a single winding would give you. This may or may not cause you trouble at 71 kHz. Having only half the winding volume carrying your inductor current means higher losses than for a proper inductor.
The boost converter has a feedback. Will this damage the transformer?
Without a schematic, nobody will be able to tell you. I'm not sure what 'a feedback' is, or how you have it connected.
Will my MOSFET and diode get damaged?
Maybe. The on time of the 71.4 kHz signal could take the inductor current up beyond its saturation level, and so to very high indeed, which could damage your MOSFET, if your power supply has the current capability. When working with an unknown inductor, you should take baby steps, so measure the current while starting with a current-limited supply and using short pulses. You really need an oscilloscope for this. Note that using short pulses and observing the current with an oscilloscope is the same as 'measuring the inductance at a variety of currents'. |
H: Instrument amplifier REF pin current
I'm using AD7190 to sample 4ch differential voltage, but the AD7190 only has four input pins. To fix that, I use AD8422 to convert four differential signals to four single-ended signals. The schematic I'm using for one channel is down below.
My question is,
(1) I have four channel, can I use one AD8541 to set four REF pin voltage of four AD8422?
(2) How much current of these REF pin usually draws?
(3) I'm using ADR423 voltage reference for AD7190, can I use AD423 ref output and divide it to 0.6V and feed into AD8422 ref pin.
(4) Did I need to enable the buffer mode of the AD7190 input?
Thanks!
AI: I have four channel, can I use one AD8541 to set four REF pin voltage
of four AD8422?
Yes you can providing all four AD8422 InAmps require the same voltage.
How much current of these REF pin usually draws?
Typically the input resistance of the REF inputs is 20 kΩ so that's 50 μA per volt.
I'm using ADR423 voltage reference for AD7190, can I use AD423 ref
output and divide it to 0.6V and feed into AD8422 ref pin.
Well, your schematic shows the reference input voltage to be 996 mV so I'm confused here as to what you require. However, if that was resolved then the voltage divider resistance might get significantly loaded by the REF input's input resistance of 20 kΩ and give you errors. It might be doable but the devil will be in the detail. A buffer amplifier is the probably best solution but that also comes with an error budget such as input offset voltage etc..
Did I need to enable the buffer mode of the AD7190 input?
Buffered mode restricts the possible input voltage range and you haven't said what that is so, it's difficult to say whether you can get away in buffered mode. However, buffered mode does deliver a much smaller input current but, given that you are using InAmps as buffers, it seems unlikely you'll get a benefit from using buffered mode. |
H: How to match RF output of 30 Ω + j10 Ω to microstrip IFA antenna with matching network?
I am designing a 4 layer PCB with an inverted F antenna (similar to image below, ground plane is larger than shown), and need to match the antenna to the source RF pin impedance of 30 + j10 ohms (source IC is an ESP32-D0WDQ6, datasheet here, RF pin impedance in section 2.5 on page 7). I will be designing the antenna using the openEMS simulator software. The frequency will be 2.4 GHz, and my transmission line length is less than 1/8 wavelength at 13mm. My goal is to design everything as ideally as possible with minimal power loss and no compromises on performance, so I am willing to do whatever I have to do in order to achieve that.
In the datasheet in section 3.1.5 on page 16 (image below) it says a pi network should be placed as close to the RF pin as possible, and the transmission line should be set to 50 ohms. I am assuming the antenna should be 50 ohms as well.
"In a four-layer PCB design, the RF trace is routed as shown
highlighted in pink in Figure 18. The characteristic RF impedance must
be 50 Ω. ... π-type matching circuitry should be reserved on the RF
trace and placed close to the chip."
I will design the antenna as close as possible to 50 ohms in the simulator, but when it is placed on the board and in the enclosure, the impedance will almost certainly not be 50 ohms exactly. Because most of the time unless you're really lucky, even by trimming the length arm on the IFA, this still will not match it to the center of the Smith chart as the other dimensions play a role in impedance also, but usually you can get fairly close, or at least closer. I plan on designing a 50 ohm antenna, but drawing it on the PCB with a longer length arm that I will trim to reach nearest to 50 ohms at 2.4 GHz on the actual PCB so it's as close as possible. Then once the antenna is closest to 50 ohms when viewed on a VNA connected to the pad for the last component in the pi filter so as to also include the transmission line in the reading (as shown in image below), then I will match exactly to 50 ohms with the matching network, so basically the trimming of the antenna will be done just to lessen the impedance changes the matching network needs to perform. Let me know if any of this is not the best strategy.
I asked a similar question on matching 30+j10 ohms to 50 ohms, but at the time I didn't realize the ESP32 datasheet says to set the transmission line (and antenna I assume) to 50 ohms, and that was part of my question. I also didn't know that my transmission line would be less than 1/4 wavelength.
Part of the answer to that question provided these details:
If your antenna is 50 Ω and your source is 30 Ω + j10 Ω then, add a
series capacitor of -j10 Ω to cancel out the +j10 Ω effect of the
inductor.
This now means you are trying to match 30 Ω resistive to an antenna of
50 Ω resistive.
Then use an L-pad calculator like this: -
You can double check the formula derivation on that site.
Series inductance needs to be about 1.6 nH Parallel capacitance needs
to be about 1.1 pF Then, if you went back to the start of the problem
and analysed what value of inductance is needed to produce the j10 Ω
in your driver output impedance, you'd calculate it to be 0.663 nH at
2.4 GHz.
This means that you can actually dispense with the added series
capacitor of -j10 Ω (as originally proposed) because you need 1.624 nH
from the above calculator. The upshot of this is that 1.624 nH might
as well be 1.663 nH so, the external series inductor you need to add
is 1 nH.
This answer has pointed out a way to match 30 ohms to 50 ohms with the L-pad network and also factor in the +j10 from the source by subtracting it from the series inductor value, which would match the source output to the antenna input, but what if the antenna isn’t tuned perfectly to 50 ohms? Say you have a 50 ohm reference antenna, but once it is placed on the PCB with components on the board and inside the case or housing which contains it, the impedance will be affected and transformed from 50 ohms to something else. Let's say after trimming, the antenna impedance ends up as 69 Ω + j11 Ω on the Smith chart.
Now here is the main point of my question (along with the next part below)... The answer to my first question already pointed out how to use the L-pad to match 30 Ω + j10 Ω to 50 Ω. But if the antenna impedance is 69 Ω + j11 Ω, I don't understand how to calculate 69 Ω + j11 Ω into the L-pad or pi-filter in order to match the source. If it was just 69 ohms resistive then that would be simple (you would just enter 69 into the calculator for output) but the problem I have is how to factor in the +j11 reactive as well. Would I subtract +j11 from the series inductor, after also subtracting the +j10 from the series inductor to compensate for that value from the source as previously mentioned?
Finally, the ESP32 datasheet mentions to use a pi-filter, I understand that pads for a pi-network would give all options to use different topologies for L-networks, but is there a way to factor all these numbers into a pi-filter using all 3 components that would be an advantage over an L-network filter? The manufacturers of ESP32 use a 3 component CLC (it appears to be CLC from the labels C15 L4 C9) pi-filter on the ESP32 modules as shown in the image below, instead of just using an L-network. So I'm guessing there is a reason for it if they are doing it. Would a pi-filter be more optimal? What would be the most optimal way to do all this? Thanks and any help would be very much appreciated.
UPDATE: @Andy aka and building off of his answer… Regarding the capacitor at the antenna input which compensates for the +j11 reactance from the antenna, I have just never seen that technique used before on an antenna matching network (I'm not an antenna expert, but I have looked at quite a few antenna application notes) and they are not using it on the ESP32 module. Have you ever seen it used on an antenna before on a retail product?
On one hand, It seems like it could be an advantage because you would be canceling out the +j11 before it could have any effects with the purely 50 ohm transmission line. I assume it would have effects anyhow, would the +j11 create any loss or detrimental effect in the transmission line? Even if it is less than 1/8 wavelength?
Is there a way to omit the capacitor at the antenna input, but then factor the +j11 value into the L-pad or pi-filter which is positioned before the transmission line and near the RF pin as shown in the next image? Do you think there would be any advantage to this since they are doing it this way on the module it appears, unless their antenna is perfectly 50 ohms? Or are they possibly just being lazy? Or perhaps maybe the way they are doing it is sufficient, and there would not be any advantage to add an extra capacitor at the antenna input with a short transmission line (although it may not be detrimental either) as long as they simply factor the +j11 into the pi filter? I am simply not aware of these things, what is your opinion?
But if a capacitor is placed at the antenna input, would you first measure with the VNA at the point in the next image to find the antenna impedance, then place the capacitor which is valued according to whatever is the reactance (+j or -j) value (or zero ohm resistor if a perfect reactive match)?
Then once the capacitor is placed, would you measure on the VNA from the last pad on the pi filter as in the next image to get the impedance of the transmission line with the antenna and the capacitor as a package? Then base the L-pad output calculation on that impedance? And should that impedance be purely resistive at this point since the reactance +j11 (or whatever the value) from the antenna has been canceled out? Or possibly could there still be some reactive component involved if you are trying to measure the transmission line, capacitor and the antenna at once?
AI: But if the antenna impedance is 69 Ω + j11 Ω, I don't understand how
to calculate 69 Ω + j11 Ω into the L-pad or pi-filter in order to
match the source.
If your antenna is 69 Ω + j11 Ω then use a series capacitor at the antenna end of the t-line to "tune-out" the +j11 Ω inductance of the antenna. Thus leaving you with purely resistive 69 Ω. If you find you don't need to fit a capacitor, then you can fit a zero-ohm link instead.
Would a pi-filter be more optimal?
With respect to an L-pad, a pi-filter offers more flexibility. An L-pad transforms a low impedance into a higher impedance so, it works in your current situation (where the RF output is 30 Ω and you want to match to 50 Ω). Of course, if you reverse the direction of the L-pad it transforms a high impedance into a low impedance. And, by using a pi-filter, you get the option of bi-directionality in either stepping up, equalling or stepping down an impedance: -
Picture and calculator can be found here.
So, the bottom line is that a pi-filter is built from 2 back-to-back L-pads where the series inductive element (\$L\$) equals \$L_1 + L_2\$ from each individual L-pad. |
H: Maximum voltage divider resistances for sensing LiPo battery voltage over 10bit ADC: is MOhm range working?
I've designed a PCB that should contain as few components as possible but it should have a simple way for measuring the battery voltage using an ADC channel and a simple voltage divider. My current design with 100k-220k division:
Consumes around 12µA, which is still a bit much for my project constraints.
I'd like to use resistances with 10x that value so around 1MOhm-2MOhm. The readings don't have to be accurate, I just want to have a rough estimate of the LiPo voltage to know when it is empty. I guess if there's too little current drawn over the voltage divider, the noise will be a problem for the ADC.
Is there a best practice for my application or some reference on estimating the noise caused by such high resistances?
EDIT: I am using an ATMEGA1284p AVR MCU, which has an input impedance of 100MOhm
Reference1
Reference2
AI: By itself the impedance is too high. The AVR needs the impedance to be 10k or lower, otherwise the sampling capacitor does not have enough time to charge to the measured voltage and conversion result will be inaccurate.
If you put a capacitor at the ADC input pin, that is large enough (e.g. 100nF), it can provide the necessary AC impedance to the ADC input. However it will not affect the DC impedance so the conversion must not happen too often to let the capacitor voltage charge enough via the high impedance resistor divider. |
H: How can I find the slope at Vout/Vin at Vin = 0, from the datasheet about Op-amp?
I'm trying OpenModelica and I'm going to simulate an Op-amp.
(No it's not Windows 95, it's IceWM + Ubuntu 20.04)
But I wonder where I can find the slope Vout/Vin when Vin = 0 in the datahseet?
I have heard that the slope from an Op-amp is so large so not even the datasheet write it out. Is that true? Or can I find it?
Assume that we are using this datasheet:
https://www.mouser.se/datasheet/2/389/cd00001046-1795623.pdf
AI: Look at the large signal voltage gain Avd in the datasheet. 100,000 typical (under the specified conditions).
Also refer to figures 17 and 19 for typical behavior under different conditions. |
H: Frequency domain S11 conversion to time domain TDR
Below we see the S11 plot of a transmission line, the Wikipedia definition of the reflection coefficient as a function of S-params.
As I see it, the S-param frequency domain plot comes from the time domain steady state.
TDR is time domain in every moment from the start (transient).
So how can we convert from S-param (steady state) to TDR (transient)?
AI: You get the time domain TDR by taking the inverse transform of the frequency domain S11 data. This is related to the fact that the impulse response of a network is equal to the Fourier transform of its frequency response. Many Vector Network Analyzers have this function built in and usually labeled "Transform". You can find the details by Googling "convert S11 data to TDR". One good source is: https://cdn.rohde-schwarz.com/pws/dl_downloads/dl_application/application_notes/1ez44/1ez44_0e.pdf. |
H: How can I do two points scaling in electronics? 0.6 V - 3.2 V to 0.0 V - 3.3 V
I'm seeking a solution how to do a two point scaling in electronics. I have tried an Op-amp, but it did not work very well. So I wonder if you have some ideas how to do two point scaling from e.g 0.6 V - 3.2 V to 0.0 V - 3.3 V?
When I apply 4 mA, I what the output to be 0.0 V or very close to 0.0 V.
When I apply 20 mA, I want the output to be 3.3 V or very close to 3.3 V.
The Zener below is a 3.6 V Zener.
Is that possible?
AI: I'm using a STM32 but the ADC reference is 3.3V and when I apply 4mA, then I'm using a lot of the ADC. I don't what to do that. Or is it possible to change the ADC reference for the minimum voltage too?
You're only losing 20% of the range and you have the advantage of a "live zero" which can be used to detect a break in the 4 - 20 mA loop. This is the standard solution taken by industrial PLCs and many of those do that on a 0 - 10 V input by addition of a 250 Ω shunt resistor to give only 5 V at 20 mA. Usually its simplicity wins out over the loss of resolution.
A further advantage in the industrial sensor applications is that sensor faults can be indicated by sending a 3 mA signal, for example.
From the comments:
But isn't 20% a little bit to much? I could detect current loop breaks with 5% waste.
That's for you to decide. You're using a 12-bit / 4096 step ADC. That's a step resolution of 0.02% of full-scale per step. Losing 20% gives you 0.03% of full-scale per step. You're going to have difficulty getting better than 0.1% shunt resistors - see Vishay for example and noise will introduce further problems. Introducing an op-amp to do the offset properly only makes it more difficult.
Figure 1. It appears that the top and bottom of the STM32 ADC are accessible.
The other option is to offset the ADC VREF- to 20% of VREF+. See page 68 of the datasheet.
Added by OP: |
H: Question about diode connected transistor (BJT) with current source
I'm trying to find ΔV for this circuit, but I'm having a bit of trouble doing so. I think the current on the right BJT will be n times greater than the left, but I'm not sure about that either. It looks like a current mirroring circuit to generate a ref voltage that's stable with temperature, but I'm still unsure how to find ΔV.
AI: If I have done my math correctly, to a very good approximation,
$$\Delta V \approx \frac{kT}{q} ln(n) = V_T ln(n)$$
where
k is Boltzman's constant
T is the absolute temperature in Kelvins
n is the ratio between the reverse saturation/leakage currents of the two "diodes".
q is the charge of an electron
\$V_T\$ is the temperature equivalent voltage
Thus, the output voltage will quite accurately reflect the absolute temperature.
The derivation I used is as follows:
For a silicon diode, (and approximately for a diode connected silicon transistor)
$$I_d = I_s(e^{\frac{qV_d}{kT}}-1) \approx I_se^{\frac{qV_d}{kT}} $$
Since the diodes have the same current,
$$I_{s1}e^{\frac{qV_{d1}}{kT}} \approx I_{s2}e^{\frac{qV_{d2}}{kT}}$$
Taking logarithms on both sides
$$ln(I_{s1}) +\frac{qV_{d1}}{kT} \approx ln(I_{s2})+\frac{qV_{d2}}{kT}$$
Rearranging gives
$$ln(\frac{I_{s1}}{I_{s2}}) \approx \frac{qV_{d2}-qV_{d1}}{kT}$$
$$kT \cdot ln(n) \approx q\Delta V$$ |
H: what is the alternative method for time domain reflectometry
I have read that TDR is problematic because if we have many transmission lines in series which cause discontinuity to the source resistance ,then the closer TL's will mask the reading of the far TL from the source, so is when the rise time of the source is larger the TL delay.
So what is the alternative to the TDR? what method is used to overcome those problems and see the impedance at every location of the system?
An example is shown in the picture below. We have 80 Ω, 30 Ω and 50 Ω transmission lines. The 80 Ω and 30 Ω t-lines create masking problem for reading the 50 Ω transmission line: -
AI: You can use a VNA to measure the frequency domain reflection, and use post-processing of the signal to obtain the equivalent TDR trace, as your previous question implies you are already considering. This method will still suffer somewhat from multiple reflections but may be more effective for several reasons:
The VNA stimulus delivers equal power at all frequencies, whereas in TDR the power falls as \$1/f\$, leading to quite weak signals and low SNR at the higher part of the desired frequency band.
The VNA can be set up to average its measurement over a long time at each frequency, improving the SNR dramatically. TDRs can also use multiple-trace averaging, but the amount of averaging that is practical is less than when using a VNA.
The VNA receiver is simply more sensitive than the receiver (oscilloscope input) typically used with a TDR.
That said, if you want to separate the reflections from discontinuities that are very far apart in physical space, with a VNA-based "TDR" measurement, you need to have a VNA capable of measuring at both very low and very high frequencies. Many VNAs have minimum frequencies that might be too high for some systems that could be easily measured with a TDR. |
H: Calculating chip junction temperature based on case temperature
As far as I know one can calculate a chip’s (Diode, Transistor..) junction temperature rise with the consumed power and the thermal resistance Rth.
Is there a way to calculate the junction temperature without the power but based on the temperature measured on the Chip‘s case and Rth or other datasheet values?
The reason for this question is my desire to check the temperature handling on an existing PCB without changing it by my measurements (for example soldering some parts up for current measurments).
AI: There is a way using no air flow with Rjc thermal resistance to estimate active junction temperature.
You must know Pd, Tamb and Rjc to compute Tj or for THT parts if given Rjc, Rca... for j = junction, c= case and a= ambient....and T= temp. SMT parts depend on substrate greatly.
But comparing mounted and uncounted parts could derive these values for Rca using similar small sized parts like 220’C/W in small transistors. (Not tried)
Tj= (Tc-Tamb)*Rca/Rjc+Tamb.. (? Verify?).
Often Only Rja is given due to many differences in substrate material and area so guidelines are given.
Due to latency of thermal mass in power devices you must also know the Safe Operating Area or compute the junction thermal pulse response if an OEM like Rohm provides the RC time constants for each layer of material.
Another active method is to use a pulsed off current to measure the threshold voltage of a PN junction which has a known thermometer characteristic at 1mA. e.g. ~600 mV @ 25’C @ 1mA for Vbe then apply the NTC slope to estimate Tj.
Calibration in boiling water will serve to verify assumptions of a discrete part.
In general the lead temp may be closer to Tj than the epoxy insulated body. This is especially true for Cathodes on epoxy LED’s where the cup-holder is attached while the anode is bonded with a whisker gold wire that is a poor heat conductor and fuses easily yet is almost invisible.
Yet ultimately, if your case temp is too hot to touch > 65’C at room temp, you may have a Tj reliability problem at 40’C ambient. Arrhenius Law states for every 10’C rise the MTBF reduces 50%. There may be exceptions for some materials that this applies every 12’C rise above ambient. |
H: Combinational logic circuit
I was asked to:
Design a combinational logic circuit that has 10 inputs, numbered 0 through to 9, and one output. The output is required to go HIGH whenever any one, or more, of the inputs numbered 2, 5, 6 or 7 go HIGH. The circuit should be free of static hazards.
I know I can use OR of 2,5,6 and 7 and give it's output but I don't know how to check for static hazards and how to remove it? Please help..
Please check if this circuit has static hazards.
AI: There are no static hazards in your circuit because no signal feeds two or more inputs. Put another way, there is only one path, for each input, to the final output.
Not all circuits where there is a signal which feeds two or more inputs, have a static hazard. However, all circuits with static hazards have such signals. |
H: Car battery charger
I'm a student of electrical high school. I have tried this project, to make a car battery charger with an Arduino-powered voltage meter. My problem is that I made some research about making an Arduino voltage meter and I found that I need to connect the v- of my charger to GND on Arduino. I'm not a perfect student and I've been searching for it for an hour now. The question is, can I connect the GND pin to v-, or how can I overcome this problem? Please let me know your honest opinion about the fact if it will work.
Here is my schematic.
I've highlighted the problem area.
It is a car battery charger, so the wanted voltage is somewhat more than 12V.
AI: There’s a few improvements that need to be made.
12V transformer is not enough it needs to be >16V due to the 2x diode drop at high peak currents for a 12V car battery that needs 14.2V to be fully charged.
the battery is like 10 kFarads or more so it must be charge with very low DCR transformer secondary resistance as the resulting charge only happens on peaks of the rectified sine wave and in cars they use 3 phases with 6 diodes for smoother current.
However this is doable but your diodes must be rated for >20 times your average current expected. This is because this will be the actual peak current for <=5% of the peak of the sine and bigger diodes have low resistance and may need a heatsink (insulated)
rather than a LM317 to produce voltage with massive linear power drop, needs a big heatsink. a far better solution is to use a 10 mOhm power NCh FET on the ground side and a 5 mOhm current sensing resistor or >=10A Ammeter to measure the current for 50mV drop to be amplified to 5V to avoid getting hot. Thats a piece of solid copper wire.
you then monitor Current until voltage is reached to regulate or cutoff. |
H: phase between the input voltage and the output voltage?
If I have this circuit, how can I calculate the phase between the input voltage and the output voltage (capacitor voltage)?
Knowing that the signal frequency is 1kHz
AI: Well, the transfer function of this circuit is given by:
$$\underline{\mathscr{H}}\left(\text{j}\omega\right)=\frac{\underline{\text{V}}_{\space\text{out}}\left(\text{j}\omega\right)}{\underline{\text{V}}_{\space\text{in}}\left(\text{j}\omega\right)}=\frac{\frac{1}{\text{j}\omega\text{C}}}{\frac{1}{\text{j}\omega\text{C}}+\text{R}}=\frac{1}{1+\omega\text{CRj}}\tag1$$
So, taking the \$\arg\$ on both sides gives:
$$\arg\left(\underline{\mathscr{H}}\left(\text{j}\omega\right)\right)=\arg\left(\frac{1}{1+\omega\text{CRj}}\right)=\arg\left(1\right)-\arg\left(1+\omega\text{CRj}\right)=$$
$$0-\arctan\left(\frac{\omega\text{CR}}{1}\right)=-\arctan\left(\omega\text{CR}\right)\tag2$$
So, at \$\omega=2\pi\cdot1000\$ we get:
$$\arg\left(\underline{\mathscr{H}}\left(2000\pi\text{j}\right)\right)=-\arctan\left(2000\pi\cdot1000\cdot47\cdot10^{-9}\right)=$$
$$-\arctan\left(\frac{47 \pi }{500}\right)\approx-0.287148\tag3$$ |
H: What is the difference in RISCV between JAL and JALR?
I'm kinda confused on what the difference is between the two instructions and would love a comparison of the two!
AI: JAL saves the next address (program counter +4) to the destination register, adds the immediate value encoded in the instruction to the program counter, and jumps to that address.
JALR saves the next address (program counter +4) to the destination register, adds the immediate value encoded in the instruction to the source register, and jumps to that (even) address.
In other words, while JAL jumps to an address relative to the current instruction, JALR jumps to an even address relative to one stored in a register.
The detailed parts from the technical documentation are these:
Unconditional Jumps
The jump and link (JAL) instruction uses the J-type format, where the J-immediate encodes a
signed offset in multiples of 2 bytes. The offset is sign-extended and added to the pc to form the
jump target address. Jumps can therefore target a ±1 MiB range. JAL stores the address of the
instruction following the jump (pc+4) into register rd. The standard software calling convention
uses x1 as the return address register and x5 as an alternate link register. Plain unconditional jumps (assembler pseudo-op J) are encoded as a JAL with rd=x0.
The indirect jump instruction JALR (jump and link register) uses the I-type encoding. The target
address is obtained by adding the 12-bit signed I-immediate to the register rs1, then setting the
least-significant bit of the result to zero. The address of the instruction following the jump (pc+4)
is written to register rd. Register x0 can be used as the destination if the result is not required. |
H: What are the diode and two capacitors doing in this circuit?
I have an existing circuit from a working design that I am trying to understand in order to apply the understanding to a different circuit I'm building.
We can reduce the scenario to basically two ICs and a handful of discrete components. The first IC is a CPLD, and it is powered by 3.3V from the computer that it is installed in. The second IC is SRAM, and it is powered directly from a 3V coin cell battery. The two chips talk to each other through a couple control signals and a parallel data bus, and I think we can assume for the purposes of this question that the small voltage difference between the two of them is within tolerances for the signals.
The part I am struggling to understand is that the ground connection between the two of them is ultimately shared, but the ground of the SRAM is passed through a circuit involving two capacitors in parallel and a diode between them, before connecting to the shared ground.
My question is- what could that part of the circuit be doing? I'm guessing that it is in some way trying to isolate the ground of the SRAM, possibly to prevent power leakage between the two sides of the circuit. But I'm not sure, and I'm especially unsure of what the diode there is doing.
AI: It is almost certain that the diode is from 3V3 to 3V.
In that position it would power the SRAM usually and the 3V battery is a backup.
You may have swapped ground and supply labels.
High quality [tm] corrected diagram :-) |
H: What is the source of distortion in this simple common-em. Colpitts oscillator waveform?
I took the standard common emitter NPN (3904) amplifier with an LC tank on the base:
(Credit to "Radio Physics and Electronics" on youtube.)
I experimented with R1/R2 thinking it was a gain issue, but it is still there with lower gain to the point where my scope can't trigger in all the noise. I also swept the frequency from 70kHz to 500Khz by changing C1/C2 and L1. Still there.
Here's an image.
Both channels are in DC coupling and I'm probing the output (yellow) and the input prior to the coupling/bypass cap (green) at the base.
It is also there with a 2N2222.
EDIT: See Andy and Enrico's replies below. Reason? Non-linearity of slamming a 2n3904 rail-to-rail. I replaced the the transistor with a 1458 op amp (using a 2426C rail splitter to generate +/-2.5V) and Rf/Ri of 10k/1k .... and presto, a nice clean sinusoid that is more stable over a larger range of CL values.
AI: The source of distortion is the non linearity of the 2N3904.
Usually, oscillators are filtered at the output using selective LC circuits which help remove unwanted frequencies and narrow the spectrum. |
H: Output Resistance of Small-Signal MOSFET Circuit
I have some doubts concerning the calculation of the small-signal output resistance of a common-source stage with source-degeneration. This is related to another question I posted but I have refined my question in detail here as to exactly what is troubling me
The Problem
Calculate the small-signal output resistance of the following circuit including the effect of channel-length modulation and ignoring the body effect.
My Solution
I have two approaches to find the output small-signal resistance, they both involve,
Drawing the small-signal model of the circuit
Zero all independent sources (voltage sources = short, current sources = opens)
Applying a voltage Vx at the output and measure the resulting current Ix flowing.
Output resistance will then be Rout = Vx/Ix
This gives us the following circuit
Now from here on, I have two approaches - the first approach gives me the correct answer, however the second approach gives me an incorrect answer.
Approach 1 (KVL)
Approach 2 (Resistors)
Why does my second approach give me an incorrect answer? I suspect it is something to do with the fact that the ro now only gets a current Ix flowing through it.? Something that didn't sit well with me in the second approach was that after decomposing the current source into a resistor, I had to get rid of the negative sign of the 1/gm. So current flow direction is strange to me too.
EDIT:
Extra Info for Comments:
AI: You've written "Current source whose current depends on voltage across it = resistor".
This is true, as long as the current is linearly proportional to the voltage across the current source.
However, the voltage across that current source is \$V_{ds}\$, while its current is proportional to \$V_{gs}\$. Thus, the current is not proportional to the voltage across the current source, and replacing it with a resistor is invalid. |
H: Magical uses of tunnel diodes
I am studying the working principle of tunnel diode and I am reading for a voltage range it creates a negative differential resistance.
If we have a current source supplying the circuit with some current, if the current is inside the negative differential resistance region, which will be the voltage of the diode, the green voltage , the orange voltage or the blue voltage?
AI: It depends on how you changed the current before:
If the current had not exceed the top (Ipe), then it is the "orange voltage" staying at the first part of the diode IV curve having a positive resistance.
If the current had exceed the top (Ipe) and then had not fallen under the bottom (Iv), then it is another (eg, "blue":) voltage that would stay at the third part of the diode IV curve having a positive resistance.
You will never see the "green voltage" since it is an extremely rapidly changing voltage (in the middle negative resistance region the operating point is unstable and it "jumps" in a horizontal direction).
The "magical use" of this bistable mode of operation is to make the tunnel diode memorize (act as a latch). For this purpose, the tunnel diode is initially biased by a current Iv < Ibias < Ipe. Then, it is toggled by adding or subtracting a sufficient current so that I > Ipe or I < Iv.
See more about the bistable mode of the N-shaped negative differential resistance and particularly, how the diode "jumps", in the related Wikibooks story. |
H: Transforming bike dynamo output to reduce diode bridge loss ratio
I'd like to use a standard 6v/3w bike bottle dynamo to power a 18650 battery charging module TP4056 which also powers some LED's.
Diode bridge rectifier steals 1.4v from the generator. In addition to reduced output voltage, a large portion of period would be without any current (all the time while absolute value of voltage is under 1.4v).
So, could I reduce this inconvenience by attaching a transformer right after generator, to multiply voltage by 4 and attaching output of the transformer to the diode bridge and on to the battery charger?
Would the transformer losses be smaller than the loss of having to use only diode bridge?
Which kind of transformer would fit this purpose?
AI: The bottle-type dynamo has a circumference of under 2 inches, and at
normal cycling speeds (12 mph), assuming it has two pole pairs,
will give AC at about 100 Hz. This is compatible with an AC transformer
of the wall-wart type, but not ideal (because those
transformers typically have 120V-in, 12V out, and you want
circa 6V in...).
Power output is in the 3-5W range for the bicycle lights
and generators of old (with incandescent bulbs).
Another option is to use a voltage-doubler rectifier which lowers the
drop from 1.4V to half that, or less if you use Schottky rectiiers
simulate this circuit – Schematic created using CircuitLab
and use a DC/DC converter (probably a switchmode buck converter) to
deliver suitable charge current to the battery. The light bulb is
just a dummy load for the simulation... |
H: Which datasheet CTR value to use in optocoupler circuit?
I am looking to use the FODM8801C in my circuit: https://www.onsemi.com/pdf/datasheet/fodm8801a-d.pdf
simulate this circuit – Schematic created using CircuitLab
"Vout" node goes into an IC with the following requirements:
Vlow < 0.4V
Vhigh > 2.1V
Max leakage current out of the pin: 8uA
I've chosen the 36k resistor because it provides margin to the 0.4V low threshold when leakage current is taken into account:
8uA * 36k = ~0.29V
Saturation current through Q1 will be:
(12V-0.4V)/36k = 0.32mA
Forward current through D1 is 4.5mA, so the required CTR is
0.32/4.5 = ~7%
When calculating my CTR margin I am confused as to which CTR value I should be taking from the datasheet.
I don't understand what the saturated CTR value means - shouldn't it effectively be 0 since the current is determined by R1 only?
Should I be using the saturated CTR at Vce=0.4V or the linear CTR at Vce=5V?
AI: First, can your IC withstand ~12V on the input? I ask because those are TTL levels and its rare to have a chip that has that capability (outside of LDOs and similar special purpose devices).
The "saturated CTR" is the ratio of the specified output current to the current through the LED required to lower Vce to 400mV. At least that would be my assumption. So for the B bin you would need 1mA/.45 or 2.2mA. The unsaturated CTR is applicable in this case since you don't need Vce to drop to 400mV.
You should also account for temperature extremes and for aging, which might be another 2:1 or 3:1 depending on the LED quality and what temperatures you need to account for.
Your 8uA maximum dark current is also rather optimistic, 40uA or 50uA might be a safer number to use for Vce = 11.6V. |
H: Inductor Polarity Reversal - Flyback Voltage
I have a question about how to intuitively think about the polarity reversal (flyback voltage) that occurs in an inductor when removed from a supply.
Here is my understanding:
When the switch is closed, current flows through the inductor to ground, with a positive voltage across the inductor.
Then, when the switch is opened, I understand that the polarity reverses, but I'm trying to make sense of this fact.
I know that the average value of the voltage across an inductor must be 0. From this perspective, it makes sense that the polarity switches, it was previously positive, and now must be negative to have an average value of 0. However, when thinking about it in terms of maintaining current direction, I can't wrap my head around it.
I know that the inductor will try to resist the change in current flow. So when the switch is closed, it is storing up a magnetic field with the original positive polarity. Then, when the switch opens, the inductor should act in a way to keep the current flowing in the same direction as when the switch was closed. Knowing that current flows from high potential to low potential, it would make sense that the inductor would force a positive voltage across it, to keep the current flowing in the same direction. However, what actually happens is it forces a negative voltage across itself.
Wouldn't flipping the polarity mean that current goes in the opposite direction as before, since it must go from high potential to low potential?
Can someone help clear the confusion for me?
AI: Wouldn't flipping the polarity mean that current goes in the opposite direction as before, since it must go from high potential to low potential?
There is no rule for an inductor that says "[current] must go from high potential to low potential". That is a rule for a resistor.
The rule for an inductor is "the current increases (becomes more positive) with a finite rate of change when the voltage across the terminals is positive and decreases (or becomes more negative) with a finite rate of change when the voltage across the terminals is negative".
Or, mathematically,
$$\frac{dI}{dt}=\frac{V}{L}.$$
If you think about it a bit, this rule explains exactly why the voltage must be negative to get the current in the inductor to change from some positive to zero. |
H: Does this require a larger series resistor?
I am connecting a switch to an input pin on a Nexys A7-100T FPGA development board, like shown in the below image:
The circuit has a 10K pull down resistor (R1 on drawing above) to ground and the FPGA has an internal 200 ohm resistor in series with the input pin (See below image from the FPGA datasheet). I am using pin 1 on the JA PMod connector with the 3.3V and GND pins 5 and 6.
Do I need a larger resistor in series with the FPGA input pin like a 10K? Or is this ok as the FPGA is configured as an input and is high impedance?
AI: The 200 Ohm series resistor is just to protect the input from user error and limits fault current so the clamp diodes can handle higher power overvoltages.
Increasing them to 10K provides more protection at the expense of slower transitions due to the higher RC time constant formed by the series resistor and input capacitance. You could choose to do this for a manual switch that is exposed to ESD and isn't high speed.
The high impedance of the FPGA inputs is so high that the series resistance otherwise doesn't matter as far as DC voltage levels go. |
H: One of the two brown wires to my shower isolator switch is not live. What has caused this please?
My electric shower stopped working. The shower power button didn’t turn on the shower. I then checked the isolator switch on the ceiling. Its red light didn’t turn on when the switch was on. I checked the cabling to the switch. Of the two brown wires, one of them was live (the furthest one in the image) but the other wasn’t. What has caused this please?
AI: That's what I would expect if the switch was broken. There will be one brown and one blue going in to the switch, and one brown and one blue going out to the shower.
If the switch is broken, then the brown going out may never go live. |
H: Is it possible to change the ground voltage level for the ADC/DAC at a STM32F373?
I want to change the ADC and the DAC ground so the ADC begins to measure at e.g 0.64V and the DAC begins to send out voltage at 0.64V.
Is it possible to change VSSA and VSSSD
One issue I found is that VSSA can only be 0V. But 0V just a difference point. We can say that 0.64V is the zero-ground-voltage. Right? Or can't I change VSSA and VSSSD?
Datasheet: https://www.st.com/resource/en/datasheet/stm32f373cc.pdf
AI: In the Absolute maximum ratings section on p. 55 of the linked datasheet the specs tell you, that the voltage difference between different Vss pins can't exceed 50mV. |
H: Differential Opamp: How to cut or reduce current consumption from supply rails
I built a simple differential amplifier using an LM358:
Please find the datasheet here
I want to reduce the current consumption so my idea was:
Use a GPIO pin of my MCU to switch Vdd supply to the opamp
Use large resistors
Try to also switch V1 and V2 but that is not preferred, I end up using too many GPIO pins and I need additional MOSFETs.
AI: Use a GPIO pin of my MCU to switch Vdd supply to the opamp
Bad idea, it is almost never a good idea to switch on/off ICs by removing their supply. That will only work properly if you make sure that all other pins of the IC are also kept low. If only one pin has a higher voltage then that pin will power the chip via the ESD protection diodes. For more extensive explanation, watch this video by Dave from the EEVBlog. In this video Dave demonstrates the effect using a microcontroller, the same principle applies to opamps as well.
Use large resistors
Good idea but watch out that the input biasing current of the opamp is small enough. The LM358 is OK-ish in this respect with a typical input bias current of 10 nA so across a 1 M ohm resistor you'd get a voltage drop of 10 mV.
For a low power application with low currents, you already know that the LM358 is not a good choice, it has a typical quiescent supply current of 300 uA.
With an opamp using CMOS technology you can get much lower than that, also some opamps have an enable input that you could use to switch it off. But if you choose a very low power opamp that might not even be needed.
How to find such an opamp? Again Dave helps, showing us how to do a components search based on certain parameters in this video. |
H: Colpitts Oscillator not working
I am desining a colpitts oscillator to oscillate at around 16Khz. I tried to simulate the circuit in LT spice.
The tank circuit looks right to me but I can't get the circuit to oscillate.Also, the circuit satisfies the berkhausen criterion with $$gain*attenuation = 3.1 (approx)$$.I even tried getting it close to 1 by adjusting the attenutaion but still, it doesn't work.
I think it's something to do with the other capacitors like C1 and C5 or maybe L1.
My book doesn't go into much detail about these components and it mainly focuses on the barkhausen criterion and how to calculate it. I have much confusion, for example, i can make the tank circuit oscillate by choosing other values of inductor and capacitors but there should be a way so that i don't choose a very high or low value of these components.
My questions are-
What other things are to be considered apart from the tank circuit to make these kinds of oscillators work properly?
How to decide which capacitor C1 and C5 to use for the circuit to work properly? if possible please help me with a detailed mathematical explanation.
AI: If you want a better start with a common-emitter Colpitts design try this answer or this answer. I would also advise you to use a much bigger value of inductance (L1 in your circuit) to obtain oscillation at 16 kHz. |
H: What is EMC recommended circuit and is it necessary?
I'm building a power supply with five isolation dc-dc converters, here is their data sheet https://www.cui.com/product/resource/pdqe15-d.pdf
The data sheet mentions a EMC recommended circuit, below a simpler version of the circuit, see below.
Is the EMC circuit necessary? I'm not going to be subjecting the power supply to any magnetic fields.
AI: That 'EMC circuit' is simply a passive filter to avoid propagating switching noise upstream on the power line. Search for "common mode input filter" for details.
For various reasons (entire books have been written on the subject) the DC/DC converter generates electric noise. If it in not suitably suppressed (as in 'recommended because we think it is suitable', not always true) the power cable will radiate noise causing troubles (and an EMC test failure)
If you are doing a one shot circuit for yourself it is not critical, for commercial product it's quite important because such a failure could lead to product recalls. |
H: What mathematical function do I2C falling edges follow, and why?
Consider any standard I2C communication : the falling edges, either on SDA or on SCL, will take a certain amount of time to complete.
What mathematical function do these falling edges follow?
Why do they follow this function, from an electronic point of view?
AI: At the falling edge of an I2C line the trace capacitance is discharged through the low side FET. The FET has a constant gate-source voltage.
This results in the current first beeing almost constant and leveling down to a constant resistance discharge, when the line voltage (which is \$V_{DS}\$) drops below \$V_{GS}-V_{th} \$.
So in the constant current discharge segment the voltage falls linearily and then levels off to the typical RC discharge curve.
But in reality you will have difficulties seeing such a voltage waveform, because the discharge happens almost instantly. Assume a trace capacitance \$C_t\$ of 5 pF. With an \$R_{DS}\$ of \$1~\Omega\$ the RC constant is in the order of 5ps. With lower \$R_{DS}\$ it obviously is even faster.
If you want to be even more precise you might want to add the effect of the pullup resistor, which will still be present. This will result in a minor DC offset. |
H: Direction of N-channel mosfet when replacing the diode in the buck convertor
In a buck-converter with a diode, in the first and second phases (on and of states) current is supposed to flow like the following circuits:
I am looking for a way to replace the diode with a MOSFET and after a few search I came by the following design:
My question is this:
considering the polarity of the N-channel MOSFET, Shouldn't the direction of the MOSFET be like the following circuit instead?
AI: Provided enough Vgs with the correct polarity, the mosfet will conduct both ways, otherwise only through the body diode:
First cycle off, second on:
The circuit you found is the correct one. In the second you switched the symbol for the mosfet without inverting the body diode. |
H: Manually calculated -3dB cut off frequency differs from the simulated value
I have been trying to do experiments with a differential BJT pair.
As the output resistance for the common emitter configuration is R_c (1k), instead of finding the capacitance, I attached a 1pF capacitor. I wanted to find the cut-off frequency of this circuit instead of the one without it.
This is expected to be similar to a single pole system.
My theoretical bandwidth is 1/RC but from the simulation I got about 26MHz.
Is the variation due to the capacitance or some mistake I made while calculating?
AI: From the 2N2222 data sheet: -
1 kΩ and 1 pF produce a 3 dB point of 159 MHz but, when you factor in the typical capacitance of the actual transistor it's going to be below 20 MHz.
You should also take into account the transition frequency too. At 250 MHz (see above) the transistor's β will be unity. At 25 MHz the β will be only 10 and this makes a poor choice if in fact you need gain at tens of MHz. |
H: Grounding an immersion heater
I want to ground a bucket/immersion heater:
should I build a conductive cage around the underwater resistance and connect it to ground?
would it work to just place the ground wire inside the water, maybe close to the heater?
AI: Figure 1. Random immersion heater image from Amazon.
Any immersion heater for your application must have a plug with an earth pin. The earth wire must connect the earth pin directly to the element's protective tube.
This method of earthing when used with appropriate circuit breaker and RCD/ELCB/GFCI protects the user from electric shock. It should not be compromised.
If the unit is supplied with a two-pin plug then don't buy it. |
H: How to even start solving multi-diode problems?
For example, in the circuit below there are 5 diodes constant-voltage-drop diodes, I could have 2^5 circuits to solve. Is there something I'm not paying attention to, that would greatly simplify this problem?
PS: The S1 switch is closed. Problem is asking for Vx.
Thanks!
AI: Is there something I'm not paying attention to, that would greatly
simplify this problem?
Just start simply.
Ask yourself questions about (say) diode D2 which I've marked nodes on called A and B: -
The question you should ask is this: could voltage B be greater than voltage A. Think about it - is it possible that B is greater than A? If you conclude it can't be then you can remove diode D2 from the circuit.
Then ask questions about the likely voltages either side of D4 and simplify the circuit this way. What about D3 - could it be conducting current given its direction and position in the circuit?
Use your eyes and brain. |
H: Diodes on SPI bus data lines and pull-up resistors
Take a look at this schematic provided by Adafruit with a MAX31855 to read a thermocouple.
They use diodes on CLK and CS pins while also pulling them up on VCC.
I would like to ask why the use those diodes?
Maybe as an ESD protection?
And on another note:
Let's say, on the PCB I am currently designing, I have multiple SPI devices on my bus. Should I add those same pull-up resistors on all of the devices or just place them once for the whole bus?
Maybe I should use multiple buses?
Yes, I know about the sink current of my μC and I should adjust the values accordingly if I have to place multiple pull-up resistors. But should I?
AI: They can't protect against ESD strikes but are there to protect against overvoltage.
The connector JP1 is labled breakout, which indicates that the user can connect random stuff to these pins. The diodes protect the inputs against the user supplying the pins with an external voltage. The direction of the diodes only allows a current flow out of the pins, so the user is able to pull the lines low (while pulling them to high is only done by the pullup resistors ob board).
Regarding your second question: It does not make a difference if you use one pullup at only one place or multiple ones with higher values distributed over the bus. Just use one pullup for the whole bus. |
H: Why are V and I out of phase for a resistor in parallel with an inductor for the resistor?
Vth is the voltage across RL so the current through the load should be in phase with Vth. But the current through the load is 1.8A with phase angle of 100.43 degrees and the voltage across it is 72.76V with phase angle of 134 degrees. I am not able to figure out why they are different.
AI: \$V_{th}\$ is the voltage across \$R_L\$
No it isn't.
\$V_{TH}\$ is the open circuit voltage seen at the terminals of \$R_L\$ when \$R_L\$ is disconnected. It will be lower when \$R_L\$ is connected. It's called the Thevenin voltage of the source and it isn't the loaded value; it's the unloaded value.
In other words, the solver of the problem turned the 150 volt source, the 40 Ω resistor and the inductor and capacitor into a new source (\$V_{TH}\$) in series with \$Z_{TH}\$. This was done to the exclusion of \$R_L\$ because this is what you do when you transform a more complex source into a simpler source.
That new source becomes this: -
simulate this circuit – Schematic created using CircuitLab
And clearly, it has an open circuit voltage of \$V_{TH}\$ but will be loaded down when \$R_L\$ is connected. |
H: ESP32-Cam GPIO remote control and video feed
Is it possible to control the ESP32-Cam GPIO from the web? Just like a "normal" ESP32 can create a website with buttons that turn on and off certain GPIOs
Was wondering because I can't find anything on the internet it only shows the normal ESP32
Note: I have ESP32M compatible with CAMERA_MODEL_AI_THINKER, and wanted to transmite video feed from the esp to a website and on the same website having buttons that control the GPIO pins for that esp32-cam
AI: Yes, the ESP32CAM can do all the things that the regular ESP32 can do, you just don't have access to as many GPIO. Only GPIO 2,4,12-16 are broken out to pins on the ESP32-CAM. |
H: How does mouse keep working when the battery is drained?
When battery is drained with time it provides less voltage. Which makes me wonder - how does appliance (like a mouse) keeps working with lower voltage?
Is it because electrical components inside can work with different levels of voltage?
Or there are components that lower the voltage when the battery is full?
Or maybe vice versa - some how the voltage is amplified when the battery is drained?
Or something else?
AI: When battery is drained with time it provides less voltage. Which makes me wonder - how does appliance (like a mouse) keeps working with lower voltage?
Is it because electrical components inside can work with different levels of voltage?
Many types of circuit can be designed to be tolerant of a wide range of voltages. HCMOS logic is rated 2 V to 6 V for instance, though it's much slower at 2 V. Circuits made from cheap transistors can be made to work from 1 V to 30 V, 100 V with the right transistor. However, some components specify a very narrow range of voltages, CPUs for instance need very precise voltages to avoid blowing up the transistors, while still meeting their specified speed.
Or there are components that lower the voltage when the battery is full?
Regulators, especially LDO (low dropout) and buck switching regulators can be used to lower a high battery voltage down to a fixed operating voltage. The latter are rather less wasteful of power than the former. Obviously the regulator itself must tolerate its range of input voltage.
Or maybe vice versa - some how the voltage is amplified when the battery is drained?
This is done, but tends not to be just to cope with a drained battery. It is done to gain the advantages of using a single cell. For instance powering 5 V logic from a single LiPo which can range from 3 V to 4.2 V is an ideal instance to use a boost converter. PP3 9 V batteries tend to be relatively expensive energy for energy, I've seen some data sheets that suggest using their boost converters from 2 AA cells to drive 9 V apparatus much more economically.
Or something else?
I think tolerate it, step down, and step up, cover all the bases.
Different batteries have different characteristics. CR2032 type cells tend to have a relatively flat 3 V throughout their life, this is often taken advantage of to avoid the need for regulators in some low power devices. Alkaline cells at nominally 1.5 V still have a fair amount of energy left when they dip below 1 V, though many consumer items indicate 'dead battery' well before this. The reason is it's cheaper and easier to design a circuit that only works down to (say) 1.3 V. This is another reason why some devices just seem to 'eat batteries'. For the designer, as long as you are paying for the batteries, and there's no proper specification for their lifetime, they can get away with it. The first company I worked for, professional test equipment, the specification when alkaline batteries were used was 'must work down to 0.75 V per cell'. |
H: How to change the final value of several NetLabel at the same time - Altium Designer 21
I need to change the final value of the string in several NetLabel in Altium Designer 21. For example, I need to change RED0_U1 to RED0_U4, RED1_U1 to RED1_U4 and so on. I would like to know if there is a simple way where you can change the value of all similar nets at the same time without having to change one for one.
AI: You can easily do that with the "SCH LIST" panel (right bottom of your Altium window).
1 - Select all your labels.
2 - Open SCH List
3 - Select the column Text
4 - Right click -> Smart Edit
5 - Set your changement
6 - Enjoy |
H: Multiple driver error for SystemVerilog initial value
In my code I have an always_comb block coded as follows:
always_comb
begin
if ( x == 0 )
z = some_value ;
else if ( y == 1 )
z = some_different_value ;
end
some_value and some_different_value.
z is defined and given an initial value ( for simulation purposes ) as follows:
logic z = 42 ;
When I compile - I get an error: "Multiple drivers to always_comb output variable z detected".
Is it a bug in the tool?
AI: Get rid of the end before the else. The compiler is confused about where the first if ends.
Also,
always_comb doesn't allow outside processes to write left-hand side variables (vs. always @ *, which does)
regardless, more than one driver the same wire type is not allowed. The always_comb boils down to an assignment for z, so trying to assign it again outside results in the multi-driver error.
More about all that here: https://www.verilogpro.com/systemverilog-always_comb-always_ff/
And here: https://stackoverflow.com/questions/23101717/difference-among-always-ff-always-comb-always-latch-and-always
Finally, if your intention is for z to have some default value, careful coding style would include it in the body of the if-else statement as the final else. This is clearer for someone else reading your code (or yourself, later.) |
H: Differential and common mode over-range indicator for In-amp
I need some advice with differential and common-mode over-range indication. I have a device with In-amp and I would like to add a Led or buzzer for differential and common-mode over-range indication. I have easy access to all nodes as this In-amp is not an IC but 3 separate op-amps. The device is powered from SMPS with +/- 6.5V rails. My initial thought is to use two window comparators. The first one using Va as input and the second using Vb as input. I would use a potential divider to set Vref_high at approx. 3V and Vref_low at approx. -3V using existing power rail from SMPS (Vref should not drift). One thing I do not like about this solution is the fact that I would have to use an additional quad op-amp IC. I am wondering if there is a simpler solution to my problem.
AI: A "few" resistors and diodes added and only the two extra op. amps. would be acceptable?
The initial idea would be to monitor if any of the 3 op. amp. outputs go above or below the 2 voltage references. It would not be very precise due to the diode voltage drops.
The diodes are available in "pairs": |
H: flyback RCD design
the equation is used to calculate the power of RCD, I know this power is from leakage inductor the inductor energy can use 1/2Li^2 to express, but I don't know how to get this document equation.
Can someone give me some help?
AI: Look at the formula: -
It's energy multiplied by frequency and that energy is the energy dissipated by the clamp circuit per switching cycle. In other words Power = energy x frequency.
And, that energy is \$\frac{1}{2} \cdot V_{CLAMP}\cdot I_P\cdot \Delta_t\$
We also know that power x time = energy hence,
Power = \$\frac{1}{2} \cdot V_{CLAMP}\cdot I_P\$
And this is the average power dissipated by the RC clamp in a switching cycle. It's basically half of "V x I" (power) where \$V_{CLAMP}\$ is constant (as said in the linked document) and the current waveform will be a linearly ramping down current starting at a peak of the initial current dcue to the stored energy in the inductor.
When you multiply those two terms you get an average power of \$\frac{1}{2} \cdot V_{CLAMP}\cdot I_P\$. |
H: DC-DC boost converters in parallel to run DC motor
Our aim was to power the motors of our bot (which were selected according to the torque requirement of our bot) using a single AAA Battery but due to limited time and and the difficulties in international shipment we are stuck with boosters only available in our country.
The boost converter cannot provided the required current to our motor at it's boosted state even though we are pretty sure that our battery can provide more current, as a result the output voltage of the convertor across the motor drops from 5v to about 0.8v. So we though of using a bunch of them in parallel to solve the issue. Using 5 such boost convertors we saw that this drops from 5v to about 3.8v. So naturally adding more of thes in parallel should be sufficenint to spin the motor at out desired rate. But this seems very sketchy. We tested all this only a single motor and connecting two across the whole configuration will obviously result in a larger drop. So even if we increse the number of boosters from 5 to say 10 there should be a limit where adding more of them stops giving us results. We are reallly hoping it is not the case.
What can we expect going forward or is there something that we are missing from this equation. This is pretty much our last hope
Battery : 1.2 volt 800mah
Motor : 12v 200 rpm but we are plannig to use it at about 5-6v
Boost Convertors : 0.9V ~ 5V to 5V 600MA
NOTE : I should have mentioned it from the start but using a single AAA is a rule in our problem statement that we have to follow. Also the motors are fixed according to our torque requiements
AI: When powering circuits from low voltages you have to be very aware of voltage drops that may occur.
The leads from the battery to the circuit should be of heavy gauge, if you use a battery holder it can drop significant voltage (any springs used to contact the battery may be made of steel that has much higher resistivity than copper, I had to add additional wires across the sping on one design I did to minimize the voltage drop).
It is also difficult to measure the current on the low voltage side - a typical DVM may drop up to 200mV on the current range and the meter leads can drop hundreds of millivolts so the combination can lose up to half a volt.
Single-phase boost converters can take much higher peak currents than their average - the peak current can cause the supply voltage to drop below the cutoff limit and prematurely restrict the output current. Good low ESR capacitors close to the boost converter can help. You may need several thousand microfarads of tantalum or polymer capacitors - aluminium electrolytics may not have low enough ESR to help.
Why are you restricting yourself to a single AAA cell? The space taken up by the circuitry may end up as much as an additional cell or maybe use a Li-Ion cell. Its 3.6V terminal voltage will avoid these low voltage issues. |
H: Always-on socket in-between a 2-way switch?
I have access to a power cable that powers devices through a 2-way switch, basically:
Is it possible to add an always-on socket in between using L1, L2 and N?
The problem is that either L1 or L2 is live at a given time and, obviously, they cannot be connected together as that would invalidate the 2-way switch.
Does there exist a device that would pass through L1 and L2 without connecting them together?
AI: If you have the neutral then yes. Use a SPDT relay with the common contact on the socket, NO on L2, NC on L1 and control coils connected to L2&N. When L2 is energized, the contact will switch the socket to L2. The light will flash when the switch transitions but will essentially be "always" on. I'll try to post a schematic when the circuits tools starts working again... Anyone else having trouble with CircuitLab? Until I figure out why CircuitLab isn't working... Digikey Scheme-it will have to do.
Important Edit: Just because it is possible, doesn't mean it should be done. Tapping travelers is not considered best practice. |
H: Diodes circuit confusion
If we have this circuit:
The diode with the lowest forward voltage drop will conduct and turn on while the other will turn off and not conduct current.
If I have this circuit:
Assuming the 2 diodes have the same voltage drop, R1 can be considered to be in parallel to R2 and that's how we solve those circuits.
However in the same case, what if the 2 diodes have different forward voltage drops? Say Vd1>Vd2 which assumption should I take into account?
AI: You'd need to solve the circuit, considering that the current must split, and the resistor voltage drop (V = IR) plus the resistor diode drop match. You may need to use a system of equations to relate all of the things happening simultaneously, such as the following:
Let \$V_x\$ be the voltage at the green probe, \$i_1\$ the current through D1/R2 (top branch), and \$i_2\$ through D2/R1 (bottom branch). I'll keep your assumption that the voltage drop of a forward-biased diode is constant. and furthermore, I will assume that the diodes are all forward-biased (and will check this assumption after solving).
We can relate the voltage drop between the 5V supply and Vx with the currents in the diode-resistor branches, and we can relate the voltage drop across R3 with the current in that branch (i.e. the sum of \$i_1\$ and \$i_2\$).
This gives us:
$$
\begin{align}
V_x &= (i_1 + i_2)R_3\\
5 - V_x &= i_1R_2 + V_{D1}\\
5 - V_x &= i_2R_1 + V_{D2}
\end{align}
$$
This is a system in three equations and three unknowns, and can be solved using your choice of solution technique.
Once you solve it, you must verify that the diodes are, in fact, forward biased (i.e. \$5 - Vx\$ is greater than \$V_{D1}\$ and \$V_{D2}\$). If the assumption is violated, then that diode is actually not forward-biased, and no current flows in that branch; you'll set up the equations and solve them again under that revised assumption.
On the other hand, the constant-drop model is no good in the first schematic you have. The two diodes are in parallel, so their current must split according to the smooth I/V curves associated with each of them. The series resistors added to both branches in the second schematic make the approximation hold significantly better (but still not that well). |
H: Box header to individually crimped wires
I've got an amplifier board that has a 2x10 keyed box header with a pitch of 2.54mm (black connector in photo below). It's designed to take the IDC type connector. I want to connect a few channels of my balanced audio source to this box header.
I think the design of the amplifier board is expecting me to make up a daughter board with another 2x10 keyed box header which is connected by a standard ribbon cable. I don't want to make a PCB up for this, and instead would rather take the balanced audio sources and connect it directly to the box header with some crimped connections that work well with a gauge wire that is larger than typically found in the fragile IDC ribbons. I know I can do this using what is commonly referred to as 'dupont' connectors (like the Harwin M20 series), but the ones I can find aren't keyed (they don't have the little notch that stops the cable being inserted the wrong way).
Is there another connector series that is compatible with this box header (including the key for the notch), that I can use to neatly crimp individual wires?
AI: The actual name for those connectors is not Dupont, Molex, or some other company name that makes thousands of other connectors. What they are called is is 0.100"pitch, 0.063" square headers and receptacles. They are loosely specified group of connectors and the only thing they have in common are the traits I just listed.
So there's your answer I guess. Look for that amongst connector manufacturers. If you search Digikey or Mouser which are more user friendly you should find lots. You can then go to the connector manufacturer's website which isn't so user friendly to find the range of possible options and then go specifically looking for them.
I recommend those from Molex since they seem to have the most variations. They are various combinations of keyed/unkeyed, latching/unlatched, crimped/IDC, single/double row, etc.
Tyco Electronics also makes them too but is rather an unfriendly website to search. 3M probably also makes them. I don't why know they are called Dupont connectors since I have never run into a connector manufacturer named Dupont. But you could obviously go look at them as well.
Being loosely specified, they exist under multiple Molex product lines which are the KK and C-grid series (some of which come in pitches other than 0.100" so be aware).
Since they are loosely specified, there is no guarantee that features like latches and keys will work between manufacturers so it might be a lost cause trying to fit the keys if you have no idea who made the original connectors. Literally the only thing that is guaranteed to be compatible are the square posts and pitch. |
H: How do digital potentiometer data sheets define maxmimum power disipation?
I am new to digital potsentiometers, but I would like to use one in a design.
I have been looking at several digital potetiometer datasheets and I kind of expected to see some kind of maximum power dissipation value that needed to be respected for all settings.
Is that parameter described in a digital potentiometer data sheet in another fashion? Can anyone explain how to understand the upper limit of power dissipation in a digital potentiometer?
AI: I believe the parameter you are looking for is the thermal resistance of the device. Most digital pots do not have a thermal pad so usually Junction to Ambient (θja) is specified. To use θja, you multiply θja by the power dissipated in the device to get the temperature increase in the device.
Lets use the AD5246 as an example. It has a θja of 340°C/W. If we were to apply 5V between the wiper terminal and terminal B and set the resistance to 1K, then the power would be \$5^2/1000=0.025W\$. Next we have multiply by θja: \$0.025*340=8.5\$. So the temperature of the device would increase by 8.5°C i.e. if the ambient temperature was 25°C the temperature of the device would be 33.5°C. This would be fine for the device.
Now lets say we change the resistance to 50instead of 1K. Lets follow the same calculations. \$5^2/50=0.5W\$, \$0.5*340=161°C\$. This is a lot higher than before. For 25°C ambient, the temperature would be 186°C! That is really hot and would definitely burn out the device. The operating temperature of this device is only up to 125°C.
Just some other things to be aware of. You will also have to look up the maximum voltage and current the device can use. For example, the AD5246 can only use up to 5V and have 5mA go into the terminals. In my second example, the current going into the wiper would have been 100mA which would have gone over the maximum rated current anyway.
Digital pots are usually used for low power applications so do not expect to be able to put a ton of power through them like a mechanical pot |
H: Crystal radio receiver
Why is a parallel LC circuit used to filter out the right frequency from the antenna? Shouldn't it be in series?
We have a maximum impedance at resonant frequency if we connect in parallel, so why isn't the signal being blocked?
AI: The selected signal is being blocked - from going to ground, that is.
The LC circuit shorts frequencies outside of the resonance to ground. The resonant frequency is rejected - it doesn't go to ground.
That leaves just the selected frequency available to feed the demodulator.
Since it is a resonant circuit, the selected frequency is higher than if it were just fed straight to the demodulator. |
H: Regarding boost converter and current sink IC operation
I have a doubt regarding the use of a boost converter and a current sink.
This doubt arises based on the following -very simplified- circuit.
Following the attached circuit, the boost will take the incoming 3.7V and provide a constant 12V output at whatever demanded current. Now, in the hypothetical example of having N number of LEDs with N resistors of different values, if I want to maintain a constant current so the LED brightness is constant (neglecting manufacture mismatches,) the most logical idea -IMO- would be to implement a current sink.
In the example, a TLC5940 is used, which will set a fixed current and, as consequence, will make the voltage change to adapt to that current. Would that make a conflict to what the boost is performing?
AI: The TLC5940 doesn't vary the voltage.
It varies the current. It acts like a potentiometer that automatically adjusts its resistance to keep the current constant.
The TLC5940 also uses pulse width modulation to vary the brightness of the LEDs.
You set the maximum current to the LEDs with a single reference resistor, then you can vary the brightness from off (duty cycle 0 percent) to full on (100 percent.)
The only concern you have with the boost converter is that it (and the lithium cell) can provide enough current for all of your LEDs. |
H: Verilog odd behavior with multiple edge detect
So I'm a newbie to Verilog. I decided to purchase a nice board (a Terasic DE0-CV) and teach myself some Verilog. And I'm seeing some strange behavior that I can't explain.
I lifted some code out of an example that drives the 7-seg LEDs. And I have them tied to a register. Whatever the register holds, the LEDs display.
reg [23:0] mSEG7_DIG;
SEG7_LUT_6 u0 ( .oSEG0(HEX0),
.oSEG1(HEX1),
.oSEG2(HEX2),
.oSEG3(HEX3),
.oSEG4(HEX4),
.oSEG5(HEX5),
.iDIG(mSEG7_DIG) );
I made a simple counter to drive the register, like this:
always @(negedge KEY[3]) begin
mSEG7_DIG <= mSEG7_DIG + 1;
end
And that works just fine. Click Key[3] on the board, the counter counts up from zero with each key click. Works like a charm. Sees the edge, increments the register, displays on the LEDs. So next, I wanted to make a way to clear the register to start back from zero. This is the idea I was thinking of.
always @(negedge KEY[3]) begin
mSEG7_DIG <= mSEG7_DIG + 1;
end
always @(negedge KEY[2]) begin
mSEG7_DIG <= 0;
end
This turns out to not be legal, since I have two always blocks trying to drive the same register. But you get where I'm going with this.
So I figure "Ok, I'll make them into one always block, then check the switch levels to see what we're trying to do, increment or clear."
So I did this to start.
always @(negedge KEY[3], negedge KEY[2]) begin
mSEG7_DIG <= mSEG7_DIG + 1;
end
For whatever reason when I do this, the counter counts so fast you can't see it. I've tested it for hardware problems by doing this:
always @(negedge KEY[2]) begin
mSEG7_DIG <= mSEG7_DIG + 1;
end
And that works fine too.
So what am I missing? Why does having two edge dependent signals in my always block's dependency list make it seem to be always true?
Edit: The hint from IanJ - "the synthesis tool doesn't want to make something sensitive to two different edges", and being able to see what synthesis is doing with my code in RTL viewer - this allowed me to solve the problem.
The problem - imagine a CLK line going into a D type flip flop. And you want two signals to control it. But I didn't specify HOW. The synthesis tool would have to be a mind reader to understand my intention. You have to explicitly say how you're triggering. This solves the problem. Full points to IanJ for the tip - that led to this solution.
wire change;
assign change = ~KEY[2] | ~KEY[3];
always @(posedge change) begin
if(~KEY[2]) begin
mSEG7_DIG <= mSEG7_DIG + 1;
end
else begin
mSEG7_DIG <= 0;
end
end
AI: Learning Verilog is one thing. It also good to learn digital design. Modern designs use clocks. The synthesis tool doesn't want to make something sensitive to two different edges.
You should us a clock and either count or reset depending on the input. You should digitally detect the edge to count up.
always @(posedge clock) begin
KEY3_d1 <= KEY[3];
if (!KEY3_d1 && KEY[3]) begin
mSEG7_DIG <= mSEG7_DIG + 1;
else if (KEY[2]) then
mSEG7_DIG <= 0;
end
end |
H: Is there any way to have a diode that have very small resistance from reverse path?
I'm trying to find a way so I will always have close to 0V at the measurement point (above the diode), when I have 0V as input. The -3.3V is a fixed voltage source.
At 0.64V at input, I have -5.7mV at the measurement point. That's OK to me.
At 3.3V at input, I have 2.2V at the measurement point. That's OK to me.
But when I have 0V at input, then I have -271.2mV at the measurement point. That's to much negative!
If the diode have at least 10 Ohm in resistance, then the measurement point would be very close to zero. I what it to happen. But I cannot use a diode. Is there any better way to solve this issue without using a diode, or using a better diode?
Update:
Try this with a 3.6V zener diode. Change the current source from 4-20mA and look at the output. At 4mA, then we have close to zero volt. At 20mA, then we have about 2.2V. OK! But at 0mA, then we have -225mV. That's not OK! It should be low as zero volt as well.
Update:
Here is my solution. Is it good? At 4mA, we have some voltage for the ADC and therefore, we can see that there is a sensor connected.
AI: simulate this circuit – Schematic created using CircuitLab
Figure 1. 4 - 20 mA to 0 - 3.3 V conversion.
Input span: \$5 - 1 = 4\ \mathrm V\$.
Output span: \$ 3.3 - 0 = 3.3 \ \mathrm V \$.
Attenuation: \$ \frac {3.3}4 \$ so let's set R3 = 330 kΩ and that makes R2 = 70 kΩ.
Now fix the offset. The negative voltage has to be low enough that the \$ \frac {3.3}4 \$ divider pulls 1 V to 0 V. That means that
\$ (1 + V_1)\frac {3.3}4 - V_1 = 0 \$
so
\$ 0.175 V_1 = 0.825 \$ and
\$ V_1 = 4.71428 \ \mathrm V \$ (since you need such precision).
Note that R2 and R3 are loading R1 and introducing an error which you will need to correct.
You now have the problem of generating a precision -4.7142 V source.
D1 will only conduct when the input current drops below 4 mA but there may be some reverse leakage current in normal operation so you will need to check the datasheets for that.
By now it should be clear to you why a direct 20% to 100% conversion of the 4 - 20 mA signal just using a 165 Ω resistor is such a good idea. All this complexity is going to add to your calibration nightmare.
You can check the errors by running the simulation on Figure 1 and hover over the various points on the schematic for various values of I1. |
H: CH341A Voltages for an AT45DB041B
First off - I'm fairly new to electronics
I've been probing an AT45DB041B on a mobile printer board using my CH341A
The voltages on the printer board for the AT45DB041B pins are 3v
I just discovered that the CH341A is outputting 5v (Supposedly there's a fix for this)
Is there a chance I might have damaged the AT45DB041B or other components on the printer board?
Cheers
Edit: Not this exact model but some other knockoff (probably)
https://www.amazon.ca/Programmer-CH341A-Burner-EEPROM-Writer/dp/B01D4CXYJE
Edit2: I was using it to try to red data from MOSI/MISO. The CH341A outputs 5v on VCC/MISO/MOSI instead of 3v
AI: CH341 is the name of the Jiangsu Haoheng USB-Serial interface chip used on the board. It is not very useful in describing the board.
The AT45DB041B is an SPI flash memory, 3.6V maximum.
Yes, it's possible to damage the memory chip or the MCU connected to it if the voltages are wrong. It's also possible to cause damage by probes slipping and shorting, ESD etc. If it still works completely it's unlikely you damaged it much. |
H: Current limiting at 100 amps
What options exist for limiting current in this scenario?
I have been searching for an option and it looks like I need to reduce the field on the alternator but I don't understand enough to know if that will work on its own with a DC/DC charger.
At the moment the option seems to be to buy a DC/DC charger that does the number of amps I require (being 0.5C of the LiFePO4))
simulate this circuit – Schematic created using CircuitLab
EDIT: Added information per question/comment
The charger is a CTEK Smartpass120S coupled with a CTEK250SE. The 120S does up to 120Amps in a "passthrough mode". And the 250SE does 20Amps as a proper DC/DC charger and has selectable profiles.
When the battery can take a current of over ~25amps both the 120S and the 250SE are engaged and "doing their respective things". Once the 120S detects that its current is below ~6amps it disengages and then the 250SE continues and applies a proper charging profile.
https://www.ctek.com/au/all-products/leisure-sport/d250se
https://www.ctek.com/uk/products/leisure-sport/smartpass-120s
NB: Interestingly there is no actual digital connection/signalling between the two units. They work in tandem or stand-alone and are designed to work as a pair for up to 140Amps
I don't currently have a LiFePO4 battery connected, I am still using AGM, the most current I have seen my AGM suck up is 75amps, and it's allowed as much as it wants. However, I am migrating to LiFePO4 Cells and I know that they will take all 140AH if they can. So looking for a way to limit that so I have my charging system sorted.
AI: Your charger has built-in current limiting. Adjust that. Every other approach to limit current will confuse your charger. |
H: Op-Amp Input Common Voltage Range for specific gain
This is the circuit I am working on.
I am using this instrumental amplifier AD623 with a gain of 100 using a 1k resistor between pin 1 and 8.
(https://www.analog.com/media/en/technical-documentation/data-sheets/AD623.pdf)
Based on this, my input voltage can swing from -0.05v to 0.05v.
When input voltage is 0.05v the simulation works without problems as I post on the image.
The problem I am having is that when input voltage is -0.05v I get error on simulation and I think is because I exceed specs of the input common voltage of the ic.
I need to understand how can I get correct output voltage based on the input voltage I mention.
(If input voltage is -0.05v output can be any value <5v without problem in this circuit design)
AI: Your gain is set to 101, so you're expecting an output voltage of about 5V. If you look at the datasheet:
The output can only approach 5V for a very narrow range of common mode voltage.
If you give it a -5V rail it will be able to handle a much wider range of inputs for output near the positive rail, as shown in Fig. 32 & 33. |
H: Does an increase in frequency affect a capacitors value?
When looking at an open circuited microstrip line, when the frequency is increased the value of the capacitance is changed.
When looking at an ideal capacitor the value does not change with increased frequency.
If it wasn't an ideal capacitor would the value change?
AI: If your circuit has to work, let's say, at 2.4 GHz, then you have to carefully pick capacitors and inductors that have resonant frequency above 2.4 GHz, for example 3 GHz.
This is the standard way to design RF circuits.
Murata and others characterize their components in frequency. |
H: How this equation of the voltage is attained?
I've may been asking the very easy question.
The each resistor has the same resistance(given by \$r\$).
The textbooks states the following.
\$V_{AB}=r\{i_1+i_2+i_3+(I-i_1)\}\$
How the above equation is attained?
Can anyone tell me some hint(s)? so that I can deduce it in my own.
AI: To find voltage between \$A\$ and \$B\$ , traverse from node B to A through any of the paths, and add all the voltage drops along the way. For instance, you can follow this path:
P.S: Assuming that the circuit and current directions are correct, you will find that the textbook answer is wrong for \$V_{AB}\$. |
H: How to prove that the \$3\$ nodes have the same potentials?
The question of symmetry.
The each resistor has the same resistance(given by \$r\$).
Why a current doesn't flows between the each endpoints of the middle \$2\$ resistors?
The text book only states of it with "symmetry of middle vertical line".
Proving that node \$(1,2),(2,2),(3,2)\$ have the same potentials is enough to show that the above claim is correct I think.
Can anyone tell me some hint(s) to prove the sameness of the potentials? so that I can deduce it in my own.
AI: Imagine node A is at +V for some voltage V and node B is at -V.
There is symmetry about the middle vertical line, so the voltage at 3,2 at 2,2 and at 1,2 is 0V.
Therefore no current flows through the vertical resistors and they can be ignored. |
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