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H: What is the importance of the input and output impedance of a BJT
What is the significance of the input and output impedance in a BJT circuit?
High output impedance means little to no current will flow at the output, why is this important?
AI: The gain of an amplifier, a single device, depends on the GM, the dIout/dVin, also called transconductance. GM is a vacuum tube holdover, meaning conductance-mutual or how the input and output interact.
Knowing the GM, multiply that by the impedance at the output node, and you have the gain of that stage, of that single device.
But you must include ALL the resistances, all the impedances, hanging on the output node. That requires you know the Rload, the R_collector, the slope_of_the_collector_IV_curve, and the capacitive parasitics. All these in parallel affect the gain.
Should you implement a constant-current load on the collector, then the slope of the collector IV curve, described with the name of Early Voltage, or Vearly or just Va, will set the low frequency gain.
Here is a complete bipolar gain-stage, with a resistive Rcollector (not the constant-current load):
simulate this circuit – Schematic created using CircuitLab
What is the bandwidth of this circuit? The lower end is set by the capacitors. The upper end, the Tau, is the 10pF in parallel with Rcollector || R5 || r_early || Rload. If you build this, add 5 or 10pF more, for wiring capacitances. And a scope probe will add 10 ---20pF more. A quick number: 10pF + 4Kohm is 400 nanoSeconds Tau, or 2.5MegaRad/2*pi ~~ 0.4MHz F3dB.
Now, regarding input impedance, given voltage sources have some resistance or impedance, call it Zsource, the Zin of the bipolar will form a Voltage Divider with the Zsource. Darlington bipolars will greatly incread the Zin, and the voltage division becomes
Zsource / (Zsource + Zin)
Also notice the C_collectorbase, of value 10pF, which about right for a 2N3904. The collector end sees the 10pF; the base end sees 10pF * (1 * stage_gain), thus the base Zin (at high frequencies) suffers because of the signal charge being stolen by the C_collectorbase.
Notice the self-biasing, using 220,000 ohms in series, the total being BETA * Rcollector. This rather nicely sets the Vcollector at 4.5 volts +-, allowing a large "linear" swing. But you have to know the BETA rather accurately, if you want VDD/2 as the Qpoint. On the other hand, this method of biasing does give you a fine opamp (inverting input only) with over 100,000 Hz bandwidth. Note the 220,000 Rs do load both the Vin and the Vout. |
H: Output resistance of BJT common emitter circuit
I have found this circuit on a video, he talks about output resistance of the BJT of common emitter amplifier circuit not being infinite but very large so that it must be included in the re model.
In some other websites they do not include Ro for the common emitter re model, should it be included and why?
AI: Consider this I_V plot of a bipolar device
For any base current, you'll have a tilted line. The slope is the inverse (1/R) of the output resistance. This resistance will vary, depending on doping and Ibase. |
H: Light-emitting diode luminous intensity at sub-mA currents
I am trying to find a graph or table that relates the light intensity (either relative, absolute, or total luminous flux) of a light-emitting diode at the low range of drive currents - below 1 mA and ideally down to nA and pA levels.
Most, if not all, datasheets from manufacturers tend to specify output brightness down to 1 mA, but not lower (as usually, it is not application-relevant). I've made an honest effort to parse the literature available to me, but have failed to find a reference for light output over a broader range of currents.
Alternatively, I'm also looking for some first-pass approximation for the relationship of current and light output. At higher currents, the common assumption is a linear dependency. I doubt linearity is maintained at much lower currents, but I am interested in what the curve would be and if it is monotonic and how it can be expressed mathematically.
(N.B. I hesitate whether to ask this at physics.stackexchange.com or here. Hopefully someone with overlapping expertise can chime in!)
AI: Not many manufactures will specify the luminous intensity at low levels because many LEDs have a minimum required current. I have tested some high power 3W LEDs at low currents and the LEDs begin to flicker and turn off at about 10 mA.
There are some LEDs with high luminous intensity and low maximum current (e.g. 20-50 mA) that will emit a measurable intensity at very low currents. One such LED is the high efficacy OSRAM LA E63F which targets the automotive industry. This amber LED has a luminous flux (QV) of 12.7 candela where IV:30°.
At very low current the illuminance (EV), measured in lux (lumens/m²), is 1% of the illuminance at 50 mA.
8) In the range where the line of the graph is broken, you must expect
higher differences between single LEDs within one packing unit.
7) Due to the special conditions of the manufacturing processes of LED,
the typical data or calculated correlations of technical parameters
can only reflect statistical figures. These do not necessarily
correspond to the actual parameters of each single product, which
could differ from the typical data and calculated correlations or the
typical characteristic line. If requested, e.g. because of technical
improvements, these typ. data will be changed without any further
notice.
At higher currents, the common assumption is a linear dependency. I
doubt linearity is maintained at much lower currents,
It's actually the opposite. The current vs. QV is linear at low currents and drops off as the current rises.
As you can see the Cree XP3G has a test current of 350 mA at 100% of rated luminous flux (QV). At 700 mA (2X) the QV is less than 200%. Whereas at 50% test current (175 mA) the QV is 50%.
You can assume the luminous flux will drop at a linear rate as current decreases from the published test current within the operating range of values. |
H: Will these two transistors (BC558A and BC558B) function in the same way?
I'm currently following this guide on making an Arduino OpenTherm Controller. After finding almost all of the parts without any issue; my only question remained with the "PNP transistor" named in the hardware list. As someone who is new to electronics, this did not mean much to me, so I sought out an exact name for this transistor. Elsewhere on the webpage I found this image:
As you can see, it names the transistor as a BC558A. However, after searching online for this transistor I either found few or no results. On the other hand, I found many BC558B transistors like this one so I ordered a pack. After initially thinking that because no specific "PNP transistor" was named; any sort would do, I began to reconsider this which is why I am asking for help.
My question is: Will the BC558B transistor I have ordered function in the same way in the circuit? If not, what would a reasonable alternative to the BC558A transistor be, seeing as it is very hard to find online?
Thank you in advance for any help.
AI: tl;dr For this circuit, it doesn't appear to matter at all. For a precision analog circuit, it may matter if the circuit is dependent on the beta/hFE parameter.
For the BC558 transistor in particular, the datasheet indicates the following behavior for the Hfe parameter:
This parameter relates the collector current to the base current as a ratio. Parts labeled BC558A are guaranteed to have Hfe within one particular range; parts labeled BC558B are guaranteed to have Hfe in a different range. Beyond that, there are no significant differences--they don't have different shelf life, and all of the other datasheet parameters will still hold across these series.
However, based on the circuit shown in your question, this parameter is not strongly relevant; it appears that the transistor is being driven fully-on or fully-off and as a result this parameter has only a weak effect on the circuit's behavior. Moreover, the transistor is attached to optoisolators that themselves have very imprecise characteristics unless binned in the same way.
However, if you are trying to construct an analog circuit where this parameter is important, you may need to select a particular series of this transistor (A, B, or C) and remain within that series. Even then, many analog topologies are designed to be insensitive to certain transistor parameters to avoid this issue. |
H: High Power UV led array for SLA printer
I have a question about a LED array I am designing for a home-made 3D SLA printer. I find the subject of high power led drivers quite confusing but I believe I understand how it works now and I need someone to confirm my findings.
My total LED array will consist of 80, 3W UV LEDs. Their rated direct voltage is 3.2-3.4v and their rated direct current is 700ma.
The LEDs are connected to a large cooling fin with active cooling.
I want to connect them to a 50W constant current power supply at 1500ma, I want to connect them 2 parallel series of 8 LEDs. This would give them 750ma per serie.
I have three questions:
Is my conclusion correct?
Would the LED's be able to sustain the additional 50ma above their rated current?
Would this lead to a shortened lifespan or just kill the LED outright?
AI: Is my conclusion correct?
No. It is very unlikely that the current will be evenly divided between the two strings. I have found with white high power LEDs the mismatch in current typically exceeds 20%
I rad some tests on three Bridglux EB Gen 2 strips wired in parallel. Bridgelux uses "binned" LEDs so the strips Vf are fairly close. I measured each strip individually at 500 mA.
The above strips used binned LED. I made some strips using 16 Luxeon Rebel white LEDs from the same reel. You can expect results similar to 40-60% mismatch like this:
I would recommend using a Texas Instruments
LM3466 Multi-String LED Current Balancer for Use with Constant-Current Power Supplies
Would the LED's be able to sustain the additional 50ma above their
rated current?
Would this lead to a shortened lifespan or just kill the LED outright?
Most high power LED have a "test current" at which they are spec'd. The maximum current is usually higher than the test current.
I doubt an additional 7% current would damage the LEDs. What is more important is that the temperature of the LEDs do not get too hot.
I want to connect them to a 50W constant current power supply at
1500ma, I want to connect them 2 parallel series of 8 LEDs.
Eight 3.5V LEDs would need a 30V CC driver. I would recommend a Mean Well HLG 60H-36A with a current adjustment range of 1000 - 1700 mA or a HLG 60H-36B where the max current can be set with a resistor. |
H: Auxiliary contacts on contactor to power solenoid valve
I'm just trying to introduce cold water in to industrial shredder.
Connected cold water supply to machine. That's not good because when I forget to turn off water it will overflow. I have not seen whats inside machine, but I know there will be a PLC, contactors and +24V power supply.
I'm thinking to install NC solenoid valve 24 V DC and power it from auxiliary contacts on motor contactor. Therefore water will be introduced only when the motor is running. To be more specific, there is three L1, L2, L3 and NO auxiliary contact on top and bottom sides of contactor.
I am thinking to get +24 V DC from power supply which supplies power to PLC, connect it to NO auxiliary contact on contactor, another NO auxiliary contact goes to solenoid valve, then from solenoid valve goes to 0. 0 will be on terminal block somewhere. My concern is that scheme will be safe?
Machine operates outside, temperatures winter from -5 to summer +25.
Water will go (solenoid activated) for about 15 sec, then stop for 15 sec, then start again x4 times. Solenoid will not burn? PLC will not burn? I'm thinking to install Asco Solenoid Valve SCE238D002.24/DC, 2 port , NC, 24 V DC, 1/2 in.
Any help would be appreciated.
AI: simulate this circuit – Schematic created using CircuitLab
Figure 1. SW1 - 3 are the contactor contacts. SW4 is an auxiliary contact.
If the solenoid is adequately rated and the PSU has adequate spare capacity then your plan is fine. Make sure that there is no chance of accidental connection between the mains and DC circuits. Check the 24 V supply voltage with solenoid off and solenoid on. The PLC isn't switching the solenoid so it won't be at risk. |
H: Implementing circuit with d-flipflop in verilog
I'm fairly new to Verilog and I'm currently trying to do a structural implementation of a circuit that consists of an d flipflop, it has inputs x and y, x and y are exclusive or'd and that result is exclusive or'd with the current state, and used as the input to the d flip flop. and it'll use the result state from the flipflop in the next run, etc. But I'm not too sure how to construct it.
The circuit looks like so:
And my code is as follows:
module circ(clk,x,y);
input clk,x,y;
wire state=1'b0;
wire xoy,d;
xor(xoy,x,y);
xor(d,xoy,state);
dff a(d,clk,state);
endmodule
module dff(D,clk,q);
input D,clk;
output q;
reg q;
initial q<=0;
always @ (posedge clk)
begin
q<=D;
end
endmodule
I'm pretty sure the d flip flop code is correct but when I try to test this my d and state values are just x for some reason. When I put in different x and y values in my testbench nothing happens, "state" and "d" just always says it has value "1'hx" in the simulation. Why is this happening and how do I actually assign an value to them?
I'm just not really understanding what you're supposed to do with the state, I'm assuming you need to give it a state at the very first run but if I give it a state isn't it just going to set state to that value every single time that module is accessed?
This is what state looks like on the simulation chart, it just stays red forever:
AI: In your simulator, the initial value of the D flipflop is undefined, hence the behavior of your circuit is undefined. You can take one of two approaches:
Add an initial assignment to the flipflop:
initial q <= 0;
Add a reset signal to the flipflop, and toggle it from your simulation. Your always block should then be:
always @ (posedge clk) begin
if(reset) q <= 0;
else q <= D;
end |
H: What are the symbols in the picture?
Not brilliant pic but bigger
picture from UK vehicle wiring diagram, windscreen wiper motor.
AI: If the symbols have any defined meaning in the auto electrics business I do not know but we can make a few guesses at what they are likely to signal.
Window wiper symbol at the bottom is obvious.
Motor on the right is obvious too. This has three terminals so it represents a two-speed motor and so the controller must be two speed.
Transistor symbol indicates that it is electronic rather than, for example, a bi-metalic strip type for the intermittent function.
Pulse suggests that it has an intermittent wiper function.
Switch with what appears to be a cam actuator probably represents the self-park switch input. When the motor is switched off in motion the cam maintains the park contact until the wiper is in the park position. The contact then opens and stops the motor.
Do you know what components a screen wiper control is composed of please?
Figure 1. A Chrysler intermittent (delay) windshield wiper module undergoing surgery. Source: Siber-Sonic.
A relay to do the heavy switching, some diodes, resistors, capacitors and a transistor. A modern unit would probably use a simple micro-controller.
So if the speed is selected by the stalk I presume that is done by selecting a higher or lower voltage feed. If so then what controls the voltage? a resistor in line somewhere before the stalk?
No, if that were the case there would be only two wires to the motor.
Figure 2. A typical wiper motor circuit. Credit: Jim Mais.
Note that the high-speed connection goes to a third connection on the motor. The internal winding and brush arrangement makes this the high-speed option. |
H: High-side vs low-side reverse polarity protection
I need to make a reverse polarity and over-voltage protection for a fairly powerful device (45W @ 12V input) and after some research I noticed a weird peculiarity. A typical reverse polarity protection circuit is shown below; it uses a p-channel MOSFET in a high-side configuration as a switch.
N-Channel MOSFETs tend to have lower Rdson, they are much more common and usually cheaper, so, as I guess, using a N-Channel MOSFET is preferable. The same schematic also exists with a N-Channel MOSFET, but to put the N-Channel MOSFET in a high-side switch configuration a charge pump or some other type of dc-dc inversion is required (second schematic).
But why not just put the N-channel MOSFET on the low side like on the third circuit? For some reason I've never seen in any device I've put my hands on a protection circuit with a low-side protection. So, my question is:
Why is it preferable to put the protection switch in the high-side configuration rather than the low-side?
*This peculiarity carries onto the over-voltage protection as well. The PMP10737 TI reference board, for example, uses a P-Channel MOSFET for the overvoltage protection; however, to prove my point that N-Channel MOSFET are better for this purpose, the same board uses a N-Channel MOSFET with a complex IC to drive it in the reverse polarity protection! *
simulate this circuit – Schematic created using CircuitLab
AI: It depends on your application.
The main issue with low-side protection is that you are disconnecting your ground reference. Many different systems work on the assumption that the 0V/Ground/Earth is shared between the devices. There can be many obvious and hidden ground connections.
If by way of example you have a circuit that is connected to ground by some other means - such as a USB device connected through shield to a PC which is in turn connected to earth and from earth back to your supply negative terminal. In this scenario, your low-side reverse polarity protection is effectively bypassed through this other current path.
If on the other hand you are using a battery connected only to your device, then there is no harm in doing low-side protection as there are no hidden ground paths that can bypass it.
Switching the high side on the other-hand is usually not an issue, as you would typically connect all the grounds together and have an individual power supply - it's unlikely there will be a hidden path from the power supply positive terminal through another device (*).
(*) not impossible - some systems, e.g. some cars, have positive earth, meaning the positive terminal of the supply is effectively the common terminal (car chassis). |
H: How to design a module that counts logic 1s in multiple inputs in Verilog?
For example, I have two inputs, whose value can be either St1 or St0. The changes of states are synchronous to the same clock, say 1MHz of frequency. I want to design a Verilog module that counts how many St1 have appeared in a certain amount of time.
For instance, within 5ms,
input A is 1 1 0 1 1
input B is 1 0 0 0 1
My problem is that when both signals are 1, how to make sure that the counter +2.
My first thought is just using a case:
reg counter;
wire [1:0] inputs;
assign inputs = {inputA, inputB};
always @(posedge clk)
begin
if(reset)
counter <= 0;
else
begin
case(inputs)
2'b00: counter <= counter;
2'b01, 2'b10: counter <= counter + 1;
2'b11: counter <= counter + 2;
endcase
end
end
But if we have 16 or maybe 32 inputs, is there a method better than writing a very long case?
An additional question is that if these lines are synchronous to clocks with different frequencies, how should we handle the case where multiple lines want to increment 1 to the counter at the same time?
AI: Use a for loop to add up within a cycle. Depending on the clock frequency and number of inputs, you may be able to directly increment the counter or you may have to store the intermediate sum in a register and pipeline adding that to the accumulator on the next cycle.
Handling multiple clocks is a different issue. What you could do is count in each clock domain separately, then dump the counters and synchronize the value every n (say 128) clock cycles into one clock domain where you accumulate all of these counts as they arrive.
I have a little PRBS checker module that does exactly this to count up errors at like 400 MHz, I'll have to dig it up.
Edit: Here we go:
// snip...
reg prbs_invert_reg = 1'b0, prbs_invert_next;
reg prbs_gate_en_reg = 1'b0, prbs_gate_en_next;
reg gate_sync_reg_1 = 1'b0, gate_sync_reg_2 = 1'b0, gate_sync_reg_3 = 1'b0;
always @(posedge output_clk) begin
gate_sync_reg_1 <= gate;
gate_sync_reg_2 <= gate_sync_reg_1;
gate_sync_reg_3 <= gate_sync_reg_2;
end
wire [WIDTH*4-1:0] data_err;
// lfsr_prbs_check #(
// .LFSR_WIDTH(7),
// .LFSR_POLY(7'h41),
// .LFSR_INIT(7'h7f),
// .LFSR_CONFIG("FIBONACCI_FF"),
// .REVERSE(1),
// .INVERT(0),
// .DATA_WIDTH(WIDTH*4),
// .STYLE("AUTO")
// )
// lfsr_prbs_check_inst (
// .clk(output_clk),
// .rst(1'b0),
// .data_in(output_q),
// .data_in_valid(1'b1),
// .data_out(data_err)
// );
lfsr_prbs_check_sel #(
.REVERSE(1),
.DATA_WIDTH(WIDTH*4),
.STYLE("AUTO")
)
lfsr_prbs_check_inst (
.clk(output_clk),
.rst(1'b0),
.select(prbs_select_reg),
.invert(prbs_invert_reg),
.data_in(output_q),
.data_in_valid(1'b1),
.data_out(data_err)
);
// sum errors
// reg [$clog2(WIDTH*4)+1-1:0] cycle_error_count_reg = 0;
// reg [$clog2(WIDTH*4)+1-1:0] cycle_error_count_temp = 0;
// // probably will need to pipeline this
// integer i;
// always @* begin
// cycle_error_count_temp = 0;
// for (i = 0; i < WIDTH*4; i = i + 1) begin
// cycle_error_count_temp = cycle_error_count_temp + data_err[i];
// end
// end
// always @(posedge output_clk) begin
// cycle_error_count_reg <= cycle_error_count_temp;
// end
reg [$clog2(WIDTH*4)+1-1:0] cycle_error_count_reg = 0;
reg [$clog2(WIDTH*2)+1-1:0] cycle_error_count_1_reg = 0;
reg [$clog2(WIDTH*2)+1-1:0] cycle_error_count_2_reg = 0;
reg [$clog2(WIDTH*2)+1-1:0] cycle_error_count_1_temp = 0;
reg [$clog2(WIDTH*2)+1-1:0] cycle_error_count_2_temp = 0;
// probably will need to pipeline this
integer i;
always @* begin
cycle_error_count_1_temp = 0;
cycle_error_count_2_temp = 0;
for (i = 0; i < WIDTH*2; i = i + 1) begin
cycle_error_count_1_temp = cycle_error_count_1_temp + data_err[i];
cycle_error_count_2_temp = cycle_error_count_2_temp + data_err[i+WIDTH*2];
end
end
always @(posedge output_clk) begin
cycle_error_count_1_reg <= cycle_error_count_1_temp;
cycle_error_count_2_reg <= cycle_error_count_2_temp;
cycle_error_count_reg <= cycle_error_count_1_reg + cycle_error_count_2_reg;
end
// accumulate errors, dump every 256 cycles
reg [7:0] count_reg = 8'd0;
reg [8:0] word_count_acc_reg = 0;
reg [8:0] word_count_reg = 0;
reg [8+$clog2(WIDTH*4)+1:0] error_count_acc_reg = 0;
reg [8+$clog2(WIDTH*4)+1:0] error_count_reg = 0;
reg error_count_flag_reg = 0;
always @(posedge output_clk) begin
if (count_reg == 8'd255) begin
count_reg <= 8'd0;
word_count_acc_reg <= 0;
error_count_acc_reg <= 0;
if (!prbs_gate_en_reg || gate_sync_reg_3) begin
word_count_acc_reg <= 1;
error_count_acc_reg <= cycle_error_count_reg;
end
word_count_reg <= word_count_acc_reg;
error_count_reg <= error_count_acc_reg;
error_count_flag_reg <= ~error_count_flag_reg;
end else begin
count_reg <= count_reg + 1;
if (!prbs_gate_en_reg || gate_sync_reg_3) begin
word_count_acc_reg <= word_count_acc_reg + 1;
error_count_acc_reg <= error_count_acc_reg + cycle_error_count_reg;
end
end
end
// synchronize dumped counts to control clock domain
reg flag_sync_reg_1 = 1'b0;
reg flag_sync_reg_2 = 1'b0;
reg flag_sync_reg_3 = 1'b0;
always @(posedge clk) begin
flag_sync_reg_1 <= error_count_flag_reg;
flag_sync_reg_2 <= flag_sync_reg_1;
flag_sync_reg_3 <= flag_sync_reg_2;
end
// snip...
always @* begin
// snip...
cycle_count_next = cycle_count_reg + 1;
if (cycle_count_reg[31] && ~cycle_count_next[31]) begin
cycle_count_next = 32'hffffffff;
end
update_count_next = update_count_reg;
prbs_word_count_next = prbs_word_count_reg;
prbs_error_count_next = prbs_error_count_reg;
if (flag_sync_reg_2 ^ flag_sync_reg_3) begin
update_count_next = update_count_reg + 1;
prbs_word_count_next = word_count_reg + prbs_word_count_reg;
prbs_error_count_next = error_count_reg + prbs_error_count_reg;
// saturate
if (update_count_reg[31] && ~update_count_next[31]) begin
update_count_next = 32'hffffffff;
end
if (prbs_word_count_reg[31] && ~prbs_word_count_next[31]) begin
prbs_word_count_next = 32'hffffffff;
end
if (prbs_error_count_reg[31] && ~prbs_error_count_next[31]) begin
prbs_error_count_next = 32'hffffffff;
end
end
// snip...
end
// snip...
always @(posedge clk) begin
if (rst) begin
// snip...
cycle_count_reg <= 32'd0;
update_count_reg <= 32'd0;
prbs_word_count_reg <= 32'd0;
// snip...
prbs_error_count_reg <= 32'd0;
prbs_select_reg <= 2'b00;
prbs_invert_reg <= 1'b0;
prbs_gate_en_reg <= 1'b0;
// snip...
end else begin
// snip...
cycle_count_reg <= cycle_count_next;
update_count_reg <= update_count_next;
prbs_word_count_reg <= prbs_word_count_next;
// snip...
prbs_error_count_reg <= prbs_error_count_next;
prbs_select_reg <= prbs_select_next;
prbs_invert_reg <= prbs_invert_next;
prbs_gate_en_reg <= prbs_gate_en_next;
// snip...
end
// snip...
end
// snip...
Where this was used, WIDTH was set to 16, so it's doing a PRBS check and error count accumulation of a 64 bit input. And it was running at around 20 Gbps, so output_clk was around 300 MHz. However, it passed timing analysis with a clock constraint of closer to 400 MHz (assuming a data rate of 25 Gbps). The internal clock clk was 125 MHz. The target was a Virtex Ultrascale FPGA. Readout and clearing of the final accumulators is not shown, but the counters are set up to saturate at 0xffffffff if they do not get read out and cleared before overflowing. Clock domain crossing is a simple one-way pulse synchronizer (no two-way handshake) with a copy of the count being directly read from the internal clock domain. This might not be the most robust way to do this, but is simple and it worked fine for the application. |
H: How can I isolate voltage dividers so they aren't interfered with by other parts of the circuit?
I have a small and very basic circuit that PWMs an RGB LED. It has a potentiometer to allow me to set brightness level for night time and a LDR that allows me to detect night time.
I took some measurements of the LDR under various lighting conditions so that I could select a reasonable resistor to put in series with the LDR as a voltage divider.
In practice, however, the readings were not what I expected. If I measure the resistance of the LDR with my multimeter, it's about 1/5th what I had measured when it was not in the circuit.
I selected a 51K Ohm resistor for the LDR divider circuit. My multimeter is also measuring that as 10K Ohm. The potentiometer I'm using for setting the brightness is 10K Ohm, but in circuit it measures as about 3K Ohm.
I'm assuming that these resistances are reduced because they're in parallel with each other, but I can't figure out how to isolate them so that I can get reliable readings for the micro-controller.
I'll do my best to mock up the circuit . . .
simulate this circuit – Schematic created using CircuitLab
Based on some of the comments, I decided I should isolate parts of the circuit to see if I could reproduce the measurements in the full circuit. I built this circuit in a breadboard and the measurements are the same as I mentioned above. That is to say, my expected resistances are reduced by about 66%.
simulate this circuit
AI: This is a bit of an X-Y problem. You cannot accurately measure the resistances involved in the voltage dividers when the circuit is not powered, because the constituent resistors wind up in parallel. For instance, when you attempt to measure the resistance across the LDR, you wind up measuring the resistance of this circuit:
simulate this circuit – Schematic created using CircuitLab
Which, if you do the math gives you:
\$R_{measured} = \frac{1}{ \frac{1}{R_{LDR}} +\frac{1}{ R_{1} + R_{2}} }\$
\$R_{measured} = \frac{1}{ \frac{1}{82k} +\frac{1}{ 51k + 10k} } = 34.97k\Omega\$
That said, this does not mean that the two dividers will interfere with each other in circuit. In that case, as long as the power supply is stable and has low impedance, the voltage across the whole divider can be considered fixed. The typical way that surrounding circuitry interferes with the output of a voltage divider is when enough current is drawn out of the voltage divider to create a meaningful error in the divider.
simulate this circuit
Ideally, the load current on the output of the voltage divider would be zero, and if the voltage divider were connected to the input of an op amp, that would be close enough to true. If, however, we draw a substantial amount of current \$I\$ out of the divider, then we get an error:
If \$I\$ is zero: \$V_{out} = \frac{V}{R_{1}+R_{2}}\times R_{2}\$
If \$I\$ is non-zero: \$V_{out} = (\frac{V}{R_{1}+R_{2}}-I)\times R_{2}\$
(note that the sign of \$I\$ depends on the direction of current flow, so the error could increase or decrease our actual reading)
This shows that the amount of current that flows out of the voltage divider \$(I)\$ needs to be substantially smaller than the current that flows through the divider \$ (\frac{V}{R_{1}+R_{2}})\$ to minimize this error.
Now, you haven't mentioned whether your ADC readings are coming out as you expect, but let's discuss the main potential source of error there anyway. To start with, lets look at what a typical ADC channel looks like, electrically. In this case, it's going to have a sampling capacitor that is temporarily connected to the input for some period of time before the ADC performs the conversion. Something like this:
simulate this circuit
What this means is that during the sampling time, the input mux will have connected the appropriate input channel to the sampling capacitor, and the capacitor will charge (or discharge) towards the input voltage at a rate determined by the capacitance and the impedance of whatever's connected to the selected ADC input (in this case, one of your voltage dividers). In order to get an accurate reading, your sampling time must be some multiple of the time constant of the sampling capacitor and your total input impedance (check the datasheet for details). If your sampling time is inadequate, your ADC readings will be off, because the sampling capacitor does not have adequate time to charge or discharge to the correct voltage.
For this reason, the sampling time on MCU ADCs is typically configurable, as the required sampling time will depend on the nature of the circuitry you're attempting to measure. If you have some really high impedance circuitry, you would probably want to use an op-amp buffer as another answer suggests. However, in your case, this is entirely unnecessary as long as your sampling time is set correctly. |
H: Voltage Matching with Thermistor
I am working on a circuit for a science competition, and one of the tasks is cooling a thing of water to a certain temperature (we are doing about 25C to 18C) and then using that to trigger a circuit. To do this, I am using a PTC thermistor, I have a TTC-103 one. The challenge I am facing is how to set up the circuit, so that when the resistance drops to a specific amount with this thermistor, to trigger another circuit, here a UV light.
One way I thought was just wiring the thermistor in parallel and once the resistance drops, the light can turn on. But with such high resistance still, the light is weak and the circuit is not as cleanly cut off as I would like. Someone suggested a voltage matching circuit, where the resistance drops enough that the voltages are equal. I, however, do not fully understand how I would implement this with a thermistor, so if you could provide me with an example of how to set one up, that would be amazing.
Thank you!
AI: I can give you the below example for starters. Just get rid of the pnp part for avoiding negative current.
*Addition, transistor part is representation of the Darlington pair. |
H: Modifying a buck converter for lower current rating
I have been learning about buck converters and I think I understand the principle of their design. However, I am unsure of how a current rating would be calculated for a particular design.
The schematic below is rated at 3A (Vin=48v; Vout=5v). However, if I want to power a device that requires no more than 500mA, I presume (perhaps naively?) that a 1A rating would be sufficient, being conservative.
I understand that the main contributors to current rating in a buck are the diode, inductor and output capacitor - by reducing the rating of these components I can make a much smaller PCB. So if I use, for instance, a 1A inductor and diode (the two largest components by far), will this affect the function of the circuit, and produce the same 5v output? And would a 1A component confer an overall 1A rating, or should some components be rated more conservatively to handle voltage spikes produced by ripple current?
Many thanks in advance for your wisdom!
AI: You might be better off choosing an IC that is targeted at providing the level of current you're looking for. I haven't looked at this design in detail but it is normal to select an inductor value that results in a peak to peak ripple current of about one third the output current, so the inducance value will be higher. Inductor needs to be rated for peak current. Smaller diode sounds OK. You can no doubt tolerate less capacitance at the output. All these changes will no doubt impact stability. I suggest you systematically work your way through the datasheet design process. |
H: Is this cheap extension cord safely rated for 1625W?
Comparing two cables that I have, a cheap extension cord and an expensive "heavy duty" extension cord, both are rated for the same load.
Is this an inflated rating or is it accurate for the white extension cable?
AI: The difference between the two lies in isolation, not the conductor. Notice how the orange one is for outdoor usage, so it has to have one more layer of isolation.
For the 13 A current rating, AWG 14 would definitively suffice; that's a conductor diameter of 1.6 mm, so really not that much.
Also, the orange one has one conductor more – so, another reason it's thicker. Having seen industrial and event/stage cabling, I'd really not call your orange cable "heavy duty", by the way. It does look like the minimum effort you'd have to go through to rate something for outdoor usage.
So, I don't know why you'd distrust the rating of the white one; it looks fine for indoor usage, even if I don't like this slightly US-typical type of 2-conductor cabling, since it has a tendency to tangle. |
H: How does this serial input DAC work?
This is the datasheet for 6379A:
datasheet
I looked at the timing charts, but I’m still having trouble figuring out how the IC treats the serial input.
Apparently, SI is sampled at positive clock edge, but what indicates the start of the input? I mean where are MSB and LSB? Also, I don’t get what LRCK does either.
Can someone please explain to me, in simple words, how this IC is used?
AI: The converter needs one 16 bit word for both channels, L first and then R. LRCK shows to the converter is there coming in data for L or R. Both words come in MSB first, LSB last.
The output of the converter is made from the last fully inputted L+R word pair. The output changes when the input of the next L+R word pair is started. Both channel outputs change at the same time, because people generally do not want any time delay between L and R signals, the timing must be "sample accurate". |
H: AND Gate Stays Open
I have a very simple circuit on a breadboard with two push-button switches, an AND gate (74LS08), and an LED. I have the two switches hooked up to pins 1 and 2, while the LED goes from 3 to ground. Pin 14 is given 5 volts, while pin 7 goes to ground.
I'm just trying to test to see if the AND gate works and so far it seems as though it doesn't. As soon as I plug in 5 volts to pin 14, I get current through all the output pins, 3, 6, 10, and 13, regardless of what's going on with their respective input pins, even if pin 7 isn't grounded.
Obviously, the LED should only turn on when both switches are switched on, but once 5 volts is supplied to pin 14, it doesn't matter what I do to the buttons. I've tried a couple of the same AND gates from the pack, as well as some OR gates, and they all do it.
AI: It would help if you had added a schematic, but from what I can see, you are missing one vital component. A pull-down resistor. What this does, is it makes sure that the inputs are at 0V when there is no voltage present at the input. Once the button is pressed, you will get your 5V and when both buttons are pressed, you get 5V at both inputs.
As it is right now, your inputs are 'floating' which means they are in a state that is unknown, which the IC could determine as a '1' state, which is why your LED is always on. This will also be why the same is true for all outputs. With these ICs, you should always tie unused inputs to GND via a pull-down resistor.
simulate this circuit – Schematic created using CircuitLab
Look at the above schematic. The top one is how I see your configuration at the moment (please correct me if I am wrong). When there is no voltage applied to the input, it is left with a floating voltage and may not be at 0V.
The bottom one is how it should be. Some pull-down resistors will ensure that when there is no voltage present at the input, they will stay at 0V.
Add these resistors and you should see your problem go away. |
H: What is the name of these little plastic things that protect wires from being cut into by the sharp edges of a drilled hole?
What is the name of these little plastic things that protect wires from being cut into by the sharp edges of a drilled hole?
AI: Summary:
I've been doing a lot of research on this and found several excellent definitions from CableOrganizer that has helped to clarify a lot of the confusion I've been having. I'll lay this out as clearly as I can to cite the differences between grommets and bushings which has made it easier to find the correct part I was looking for.
Is it a grommet or a bushing?
The terms "grommet" and "bushing" are pretty open in terms of their meaning, and depending on their application, but typically both words refer to a piece of material, usually circular in shape, that provides a buffer between two areas that can serve many different purposes, from insulation to vibration resistance to protection from abrasion and friction.1
A grommet is basically just a rubber bumper that protects cables from the hard edges or sharp corners of whatever surface it may be passing between.
What's is the purpose of grommets and bushings?
When running your cables through small openings or around sharp curves you will encounter rough metal or wooden edges that may damage or break your cables. These rubber grommets provide an abrasion resistant cushion around these small openings and sharp edges to protect your wiring.
A bushing is similar to a grommet and serves the function, to protect a cable from damage, but are notably more complex. These additional features can provide extra protection and functionality beyond a simple rubber pass-though.2
Examples of common bushings
PVC Bushings
Other bushings are a bit more complex in their design. Rather than a simple rubber circle, many bushings have different features that help give a little extra protection or added functionality. Non-metallic wire bushings, for example, are essentially similar to rubber grommets, though they're made from PVC and feature a threaded pattern that allows them to install into surfaces more securely.1
Snap Bushings
Snap bushings are so called because they can snap into the surface and lock into place once installed, thanks to the design of the outer edge that allows portions to expand once placed into the desired hole.
Many snap bushings are simple circular pass-throughs, but others feature "wings" or "shutters" which are flaps that help keep cables from being too loose in the pass-through, keeping them centered and also protecting them from too much vibration and shock.1
Snub Bushings
Taking it a step further are snub bushings, which have a thick split opening that will close around a cable once it's snapped into place, securing it and ensuring that it doesn't move. While this provides solid insulation and retention, it also means only a single cable can be properly secured in each bushing, rather than a bundle.1
Open Bushings
An open bushing is a grommet that is not a closed circle, but rather contains a slit that divides the circle when not installed. This allows it to do a few things closed grommets and bushings can't. Cables can be installed with a side-entry method, instead of a feed-through, for example. Additionally, they can be installed into pre-existing holes, or along pre-existing cable runs.1
Steve also mentioned grommet strips, also sometimes referred to as "edging", and can be found with or without adhesive.
What is the identity of the part in the question?
The bushing from my original question ended up being a Heyco snap bushing SB 375-4 (part no. 2030) with an inside diameter of 0.27" (6.8mm). A complete catalog is available online and parts can be sourced from Mouser Electronics.
Note that an inside diameter of 0.27" is an imperial variation with the next closest metric diameter being 7mm which may have a different outter diameter. |
H: Addition and subtraction of binary digits
I have to solve the following exercise :
Extend the circuit of the first part (the first part was an adder of integer numbers of 2 binary digits) in order to execute addition and subtraction of integers numbers of 2 binary digits (AB+-CD). Considering that numbers AB, CD are in 2's complement arithmetic. What does 2's complement mean and how I create the truth table?
AI: Two's complement
See google: Two's Complement
Fragment:
Two's complement is a mathematical operation on binary numbers, best
known for its role in computing as a method of signed number
representation. For this reason, it is the most important example of a
radix complement.
The two's complement of an N-bit number is defined as its complement
with respect to 2N. For instance, for the three-bit number 010, the
two's complement is 110, because 010 + 110 = 1000.
Truth Table
Also called Karnaugh Diagram
See google: Truth Table
A truth table is a mathematical table used in logic—specifically in
connection with Boolean algebra, boolean functions, and propositional
calculus—which sets out the functional values of logical expressions
on each of their functional arguments, that is, for each combination
of values taken by their logical variables (Enderton, 2001). In
particular, truth tables can be used to show whether a propositional
expression is true for all legitimate input values, that is, logically
valid.
You also might have a look at Karnaugh Maps. |
H: Confused about circuit analysis example
This is probably going to seem like a dumb question but how would you calculate the current i1 in this example?
AI: Assuming the 12V voltage source is supposed to be an ideal voltage source it forces 12V across the 4m resistor. It doesn't matter what the 6V source and its resistors do. The voltage across the resistor is 12V and therefore the current through it is fixed by Ohm's law I=V/R.
Any eventual currents caused by the 6V source will be taken into account by I3. |
H: Power Transformer: 110V and 220V input, with two 15V outputs 180 degrees out of phase
I have never designed a power supply before and have a few questions and would appreciate any help.
Firstly, I want to use a transformer that can both take 220V and 110V inputs. Can I use a center tap transformer and for 110V put the coils in series and for 220V only use one coil and leave the second open circuited?
Secondly, I need an output of + and - 15, so do I select a transformer with a center tap secondary and wire the two identical outputs to be 180 degrees out of phase?
Lastly, I cannot find any transformers with these specifications. What I've been looking for is a center tap primary and secondary with a ratio of 15:1
Thank you in advance.
AI: Using a centre-tapped primary usually means that you de-rate the transformer to half power.
Figure 1. Series and parallel connections for split-winding transformer. Image source: Electro-Dan. The linked article discusses torroidal transformers but the principle is the same for standard transformers.
Instead, the common approach due to its flexibility is to use a transformer with two 110 V primaries and two equal secondaries. The primaries can then be wired in series for 220 V operation and parallel for 110 V. Similarly, the secondaries can be wired in parallel for high current or series for higher voltage. The series connection point is, in effect, the secondary centre-tap.
Figure 2. For switching primary voltage by the user you would add a voltage selector switch. Source: Modulus Amplification. |
H: Confusion understanding a transducer manual for wiring
In the Setra Model 270 transducer manual the following instructions are given:
Do they mean that the excitation negative terminal should be separate with the output signal's ground? And the shield is connected to the excitation negative terminal? Is my way of wiring correct below?:
AI: A transducer of this type works best with a differential input amplifier and should preferably not be used with a single-ended input as your diagram implies. Additionally, because the case is likely to be grounded, you have possibly contravened the first requirement - that of NOT applying multiple grounds i.e. your output port is shown with a ground symbol.
If your excitation power supply is fully isolated from ground you can connect the output port negative terminal to ground. However, it will still be preferable to use a differential input if the cable-run can pick-up noise. See this: -
Best shielding against noise will be obtained by connecting the shield
and negative excitation leads.
And this implies to me that you use a grounded excitation power supply and differential (balanced) input measurement amplifier. |
H: Understanding electronic loads
I found an article about electronic loads and tried to simulate the circuit in LTSpice. However it didn't work.
Here is the link to the full article, where I tried to recreate the following figure:
Do you agree that this circuit is wrong and not working!? I'd argue that we have to use an integrator (PI controller) instead of the lone operation amplifier.
AI: There's nothing wrong with the conceptual circuit. It's a simple 1A current sink. If you simulate this with practically any op-amp and a MOSFET such as a 2N7000 it will work fine at relatively low currents (from uA up to say 100mA)
In actual practice at the 1A level it might not be stable without compensation for the MOSFET gate capacitance loading, but that is highly dependent on the op-amp characteristics and on the MOSFET characteristics (in particular Cgs). Here is an op-amp designed to be stable with very heavy capacitive loads, but it's not hard to accomplish with ordinary op-amps by closing the loop for higher frequencies separately from the gate DC. The gate then charges through an isolation resistor but that's not really PI control, as Tim says.
simulate this circuit – Schematic created using CircuitLab |
H: What is the proper procedure to charge a lead acid battery?
I have a 12 V 6 Ah lead acid battery, and have been instructed to charge it using a configurable power source.
They told me I should use a float charge, setting the voltage at a fixed level according to the battery datasheet, and end the charge when the charging current is lower than about 5% C (5% of 6A in this case).
Doing this, I have barely gotten about 80% of the rated capacity. Now, doing some research on my own I've found that what I should really do is a cycle charge, which as I understand it is a constant current charge until voltage reaches a higher level than with the float charge (also specified in the datasheet).
Long story short is, what is the proper way I should charge this kinds of batteries? Should I do constant voltage then constant current, just constant current, whatever? What I really wanna do is understand how to evaluate a given battery.
AI: The bulk of the battery charge would be a constant current (CC) mode to the battery, this only gives you about 70-80% of the battery capacity.
If you want full battery capacity utilization you would then switch to a constant voltage (CV) mode. If you wish to maintain the battery in a charged state you would then switch over to a lower CV float charge mode.
The primary difference between the topping charge and float charge is the latter has a lower voltage, otherwise overcharge will permanently (if done long enough) reduce the battery capacity.
Lead acid battery charging voltage values are temperature sensitive, which can complicate things.
If you have a severely discharged battery, you will need to trickle charge it until it reaches about 75% of the normal battery voltage. In most cases such a battery will have permanently reduced capacity.
Reviewing some integrated battery charge controllers such as Texas Instruments bq24450 or Consonance CN3717 is a good way to get introduced to the pitfalls as well. Tim's recommendation will also give you good info. |
H: Addition of 2 unsigned values in VHDL IEEE numeric_std : why this choice?
In VHDL, the IEEE numeric_std package does not behave as one could expect. The addition of two unsigned values coded on 8 bits is not given on 9 bits, but on 8 bits.
What are the reasons of this choice ?
AI: This "choice" allows the hardware designer to only handle overflow if it makes sense:
Ignore the overflow
function add_ignore_ovf(a : unsigned(7 downto 0), b : unsigned(7 downto 0)) return unsigned(7 downto 0) is
begin
return a + b;
end function;
One time this makes sense for implementing modulo 2 counters.
Handle the overflow
function add_with_ovf(a : unsigned(7 downto 0), b : unsigned(7 downto 0)) return unsigned(8 downto 0) is
variable a_ext, b_ext : unsigned(8 downto 0);
begin
a_ext := '0' & a;
b_ext := '0' & b;
return a_ext + b_ext;
end function; |
H: Can't reach desired voltage on opamp output
I have tried to make signal amplifier just to gain some op-amps knowledge, but unfortunately it doesn't work. It simply doesn't reach desired voltage (set by resistors). I have used my old cellphone headphone audio output as an input for op-amp. The OPA454 was powered by +/-15 VDC from two 5V to 15V step-up conventers. The wiring looks like:
And SSs from scope with different gain. Please see peak-to-peak voltage below graphs:
For some reason it can not exceed 10V peak-to-peak even through it should (based on my poor knowledge). Why it does so? One more thing is that I use adaptor so that it is possible for me to plug OPA454 to breadboard, but I am pretty sure it is designed / soldered correctly. I have tried swapping opamp to another one but it does't change anything. What could be potential issue?
AI: Your Hantek 6022BE scope is clipping at ±5V.
The manual states:
Max. Input +/- 5V(Without external attenuation)
You need a 10× probe if you want to measure voltages outside this range. |
H: How do I calculate the resistor R2 in this current limiter?
How can I calculate the resistor R2 of the above circuit?
I know how to calculate R2 to control the base of Q2 but I don't know what I have to do to take into account the current from the collector of Q1.
I must keep the current consumption low.
AI: Since you already understand how to set \$R_1\$, I'll give that less attention. The question you are asking is about how to set the value of \$R_2\$ and therefore by implication the value of \$I_{R_2}\$. The value of \$I_{R_2}\$ is the key, because you already know the voltage at the base of \$Q_2\$ (\$V_x= 3.3\:\text{V}-V_{\text{BE}_1}-V_{\text{BE}_2}\$.)
simulate this circuit – Schematic created using CircuitLab
The value of \$I_{R_2}\$ must not only include all of the needed recombination current for \$Q_2\$ (which will be approximately \$I_{B_2}=\frac{I_\text{LOAD}}{\beta_2}\$) but it must also include the collector current \$I_{C_1}\$. Since it isn't hard to work out \$I_{B_2}\$, the question has now been transformed into figuring out what \$I_{C_1}\$ is (or should be.) In a sense, we've just swept the problem to a new place. But we still don't have an answer quite yet.
You could just assume that \$0\:\text{A}\le I_{C_1}\le I_{B_2}\$ and set \$R_2=\frac{3.3\:\text{V}-V_{\text{BE}_1}-V_{\text{BE}_2}}{I_{B_2}}\$, where the value of \$I_{B_2}\$ used in that equation depends on the worst case expectation of \$\beta_2\$ and just let \$Q_1\$ "worry" about the details. This works and many people will think no further about it.
The design isn't much affected by the Early Effect, so that can also be neglected.
But the circuit's behavior does depend upon the ability of \$Q_1\$ to "measure" the load current. It does this measurement by "observing" the voltage across \$R_1\$ (where \$V_{R_1}=R_1\cdot\left(I_\text{LOAD}-I_{B_1}+I_{B_2}\right)\$) and comparing that voltage to its own \$V_{\text{BE}_1}\$. But its \$V_{\text{BE}_1}\$ depends on its collector current. If its collector current is allowed to vary widely (BJT variation, temperature, etc.) from circuit to circuit, then to that degree the load current is not as well managed by the design as it might be.
You can't do much about part variations in \$V_\text{BE}\$. They simply will exist and you have to accept those variations here. But there is also a \$60\:\text{mV}\$ change in \$V_{\text{BE}_1}\$ for each 10X change in the collector current of \$Q_1\$. And you can do something about that. So, it improves things (from the perspective of consistency) to diminish collector current variations in \$Q_1\$.
This is achieved by having \$R_2\$ supply still more current than is strictly required by the worst case estimates of the base recombination current of \$Q_2\$. How much more is a matter of judgment. But I'd recommend that it should be at least twice and perhaps three times as much as you'd otherwise estimate. Even more might be better, but the rate of return on further increases gradually gets more and more into subjective arguments. So just pick your factor, do some testing to validate your choice, document the results, and move on.
For example, you might choose:
$$R_2=\frac{3.3\:\text{V}-V_{\text{BE}_1}-V_{\text{BE}_2}}{k\cdot\frac{I_\text{LOAD}}{\beta_{2_\text{MIN}}}}$$
Using \$k=2\$ in order to help minimize the collector current variations in \$Q_1\$.
Whatever you do decide, whether you use \$k=1\$ or \$k=2\$ (or some other value), make sure that you test it with different BJTs (same family, or across a variety of likely family choices) and document your final selection with the experimental results you get. Or do so by using Spice with varying BJT parameters and resistor value variations to bound the likely behavior. (If this is just for hobby use, pick something and go with it. If for educational use in school, do what you think the teacher wants from you.)
This is a secondary effect. Keep that in mind. It's only crucial that \$k\ge 1\$. But \$k=1\$ will work. It's just that using a larger value of \$k\$ tosses away some excess current in exchange for a modest improvement in repeatable performance, one build to another. |
H: Effects of Different AC Adapters On Various Electronics
Long time programmer starting to learn about electrical engineering a little bit. I have a Raspberry Pi, an Arduino, and various simple projects I've soldered together out of kits and schematics friends have given me.
Recently I moved and lost many of my AC adapters. I found I was able to use different ones from other devices. AC adapters from devices such as the original kindle, old accessory USB AC adapters, old and new Apple AC adapters, and many others that do not have a USB input but rather the older style (I forget the name of the connector on the end, some sort of DC power connector Arduino UNO's have one).
So an example of what I'm asking is this: What effect does it have using say an Amazon kindle AC adapter (or any other mismatched brand adapter) with an iPhone lightning to USB cord?
Specifically, my Arduino/Raspberry Pi are using random usb min/micro cables plugged into completely random AC adapters. Most of which have no indication of their specifications. What effect could this have? I have another dubbed a "Fast Charger" that puts out (from what I can tell) 2-3 amps based on the voltage.
Another example would be the Arduino DC power connector, I also have the same connector on a small breadboard power supply. I find anything that fits seems to work in there. What effects might this have?
Thanks
AI: Voltage
Different adaptors have different voltages. You must use the correct voltage (within the margin of error which is hopefully written on both parts). If you don't the consequences could vary from it working, but unreliably, to not working, to immediately and permanently failing, to catching fire.
Polarity
Some connectors, such as the barrel jack connector on the arduino, come in different polarities. e.g. "Center pin positive" and "Center pin negative". Getting that wrong can have similar consequences to the above. Other connectors, such as the various versions of USB, only have one polarity, so it doesn't matter.
Current
The power supply will have a maximum current it can supply, and in some cases also a minimum. The load defines the actual power drawn, and as long as it is in-between the maximum and minimum for the supply, all is well. Otherwise, it will probably just not work. It is in theory possible to damage the supply this way, but that only usually happens with rough and ready supplies, or those designed for building into products, not the ones which come separately.
Isolation and Grounding
For safety reasons, you must not swap isolated and non-isolated power supplies, though from your description all yours will be isolated. You should not swap grounded and non-grounded supplies either, though the consequences there are less severe.
Power supply connectors
It sounds like many of your supplies have USB connectors. That's good, as they will all be 5V, same polarity, isolated, and almost always floating. This is because USB chargers are standardised. The only variation will be in the current they can supply, which hopefully will be written on (watch out for cheap ones with lies written on). And if you try to draw more current than they can supply, they will shut down safely. The ones with the barrel jacks will be more variable, as there isn't a standard. |
H: Programming STM32F407 discovery by the ST-Link V2
I have a STM32F4 Discovery board and a ST-Link/V2 programmer. I want to use my own ST-Link (not the embedded one) for programming and debugging the board.
I faced to a problem that i still haven't been able to solve that. I use ST-LINK Utility software and every thing works correctly if i choose 5 kHz for the Connection settings frequency. Otherwise ST-LINK Utility pops up a
Can not connect to target!
error and it offers me to choose lower frequency. Is the 5 kHz the only frequency that it can works for STM32F407 discovery board and ST-LINK V2 connection?
How can I use others and the error will not be happened again?
AI: I managed to solve that problem. If anybody encounters similar problem, here's what I've done:
According to the ST-LINK V2 User manual , the needed but not enough connections between ST-LINK V2 and MCU is as below:
SWDIO -> PA13
SWDCLK-> PA14
GND -> GND
VAPP(target VCC) -> MCU VDD
User manual also recommends to connect all the GND pins on the ST-LINK V2 to the ground and the problem is actaully here. User manual must emphasize that you must connect all the ST-Link GND pins to the ground for properly connection. And then all the connection frequencies will be available and also target will be detected and could be connected. |
H: What does it mean if my voltage regulator is acting as a wire?
When i connect 24V to my input pin, and connect ground pin to my Ground, it gives a short circuit at the bench power supply. What does this mean? Did i kill my voltage regulator?
AI: Yes, it's probably burned out.
If you don't have the proper capacitors attached to the input and output, it's possible weird things will happen, but 90% chance it's just fried.
Make sure to take a look through the datasheet, and ensure that you're not exceeding any of the absolute maximum ratings. Also if there's an application circuit that shows the caps, try to copy those. |
H: What is a high impedance low level signal?
What is a high impedance low level signal?
(I'm reading the circuit designer's companion by Peter Wilson)
AI: It is a weak signal.
High impedance means that the device or circuit that outputs the signal has a high output impedance. In simplified terms you could think of it as a high value resistor in series with the signal output (or the signal being sent over a long and thin wire). In real life there will also be some reactance and nonlinearity.
Low level in this context simply means that the signal has a low amplitude. This could be a result of the high impedance signal being fed into a low impedence input, but the way it's phrased, I think it's more likely to be an intrinsic property of the signal in question. |
H: What battery should I use in a remote control for a score marker?
I need help in choosing the right battery for my project.
I built a ping pong score marker for my school two years ago.
It is separated in two parts:
The score marker. It has the displays, an Arduino Mega and the drivers for the displays.
The control. It has the buttons to reset, go to the next set, and add or deduct a point to each player.
The control is connected to the score marker with a Ethernet cable.
Now I want to improve it by making the control wireless.
I need a battery that hold the charge for long periods of time.
The batteries only need to provide 45 mA at most.
I'm thinking to choose the 18650. Is it the right choice, or should I go for a LiPo, those that are commonly used in RC airplanes?
AI: The battery choice depends on how you intend to implement the wireless communication between the control unit and the score marker.
There are several options you can opt for, but you are mostly limited by the range you require.
It is clear that you will only need to transmit to the score market only when you press a button, therefore the controller can go into a sleep or deep sleep mode in the meanwhile, extending quite considerably the battery life.
Here are a few options:
The simplest solution is ag ate opener remote running at 433MHz which usually have 4 buttons. These remotes usually run on a CR2032, which will last years, It is extremely cheap, you can potentially hack one of these if 4 buttons are enough.
NRF24L01 - it uses 2.4GHz frequency, and it can be quite good low power mode but you will need another MCU to manage the buttons, data to transmit, and power management. Even with that, a good AA battery would work for a good part of a year, as long as you manage smartly the sleep modes.
The datasheet of the NRF24L01 states at page 21 that the current consumption is 900 nA in Power Down more and 26 uA in Standby. If you use an Arduino Pro mini, with the appropriate modifications (such as removing the LED), you can take the current consumption as well in the uA range.
I would avoid WiFi and Bluetooth, as they introduce a lot of unnecessary complications in a project that requires a low bandwidth and some range.
If you are keen on using rechargeable batteries, then you can use them, but I would stay away from 18650 because they are rather bulky for a remote. I would rather go for smaller ones in a rectangular form factor, such as the ones they use for flying small drones, which have a capacity of 500-1000mAh. These batteries are still overkill, but can work, as long as you choose a type with a low self discharge rate. |
H: regarding the sampling frequence
In my project I am using PIC32MX250F128B controller and 23LC1024 SRAM. I have written a code to sample the analog signal from the vibration sensor. For this I am triggering my ADC with the help of timer 3 and have set the sampling freq at 20khz. First I checked my system by giving 50Hz sine wave to a vibration sensor and took the analog samples from there. At that time I was getting the data as my set sampling frequency (20 khz). But when I checked my system to collect vibration data from the motor(with same sensor) my sampling frequency has reduced to only about 200 samples per second. My code is such as I am sampling one data and then displaying that data through serial monitor then again I am sampling data and displaying it. I have attached my code here. Can someone please help me why I am losing this much sampling frequency? Thank you.
#include <p32xxxx.h> // include chip specific header file
#include <plib.h> // include peripheral library functions
#include <stdlib.h>
// Configuration Bits
#pragma config FNOSC = FRCPLL // Internal Fast RC oscillator (8 MHz) w/ PLL
#pragma config FPLLIDIV = DIV_2 // Divide FRC before PLL (now 4 MHz)
#pragma config FPLLMUL = MUL_20 // PLL Multiply (now 80 MHz)
#pragma config FPLLODIV = DIV_2 // Divide After PLL (now 20 MHz)
// DEVCFG1
#pragma config FSOSCEN = OFF // Secondary Oscillator Enable (Disabled)
#pragma config IESO = OFF // Internal/External Switch Over (Disabled)
#pragma config POSCMOD = OFF // Primary Oscillator Configuration (Primary osc disabled)
#pragma config OSCIOFNC = ON // CLKO Output Signal Active on the OSCO Pin (Disabled)
#pragma config FPBDIV = DIV_2 // Peripheral Clock Divisor (Pb_Clk is Sys_Clk/1)
#pragma config FCKSM = CSECME // Clock Switching and Monitor Selection (Clock Switch Enable, FSCM Enabled)
#pragma config WDTPS = PS1 // Watchdog Timer Postscaler (1:1)
#pragma config WINDIS = OFF // Watchdog Timer Window Enable (Watchdog Timer is in Non-Window Mode)
#pragma config FWDTEN = OFF // Watchdog Timer Enable (WDT Disabled (SWDTEN Bit Controls))
#pragma config FWDTWINSZ = WINSZ_75 // Watchdog Timer Window Size (Window Size is 75%)
// DEVCFG0
#pragma config JTAGEN = OFF // JTAG Enable (JTAG Disabled)
#pragma config ICESEL = ICS_PGx1 // ICE/ICD Comm Channel Select (Communicate on PGEC1/PGED1)
#pragma config PWP = OFF // Program Flash Write Protect (Disable)
#pragma config BWP = OFF // Boot Flash Write Protect bit (Protection Disabled)
#pragma config CP = OFF // Code Protect (Protection Disabled)
// Defines
#define SYSCLK 40000000L
#define RAM_WRITE_CMD (0x2000000) // top 8 bits -- 24 bits for address this is starting point(2^25))
#define RAM_READ_CMD (0x3000000) // top 8 bits -- 24 bits for address(this is recoverable exception)
// Macros
// Equation to set baud rate from UART reference manual equation 21-1
#define Baud2BRG(desired_baud) ( (SYSCLK / (16*desired_baud))-1)
// Function Prototypes
int SerialTransmit(const char *buffer);
unsigned int SerialReceive(char *buffer); //, unsigned int max_size);
int UART2Configure( int baud);
char a2dvals[30000];
int adcptr,num_channels,k,i;
char sampling;
int ADC_RSLT0,totaldata,totaldata1,chunks_sent,data_count,l;
short temp;
BOOL a2don;
volatile unsigned int channel4;
volatile SpiChannel spiChn = SPI_CHANNEL2 ; // the SPI channel to use
volatile int spiClkDiv = 2 ; // 20 MHz max speed for this RAM
int dummy,dummy1,junk;
unsigned char tempstr[5];
inline void Mode16(void){ // configure SPI2 for 16-bit mode
SPI2CONSET = 0x400;
SPI2CONCLR = 0x800;
}
inline void Mode8(void){ // configure SPI2 for 8-bit mode
SPI2CONCLR = 0x400;
SPI2CONCLR = 0x800;
}
inline void Mode32(void){ // configure SPI2 for 32-bit mode
SPI2CONCLR = 0x400;
SPI2CONSET = 0x800;
}
void modesetbyte(){
int junk;
Mode16();
mPORTBClearBits(BIT_0);
WriteSPI2(0x0100);
while (SPI2STATbits.SPIBUSY); // wait for it to end of transaction
junk = ReadSPI2();
mPORTBSetBits(BIT_0);
}
//void modesetsequential(){
//int junk;
//Mode16();
//mPORTBClearBits(BIT_0);
//WriteSPI2(0x0140);
//while (SPI2STATbits.SPIBUSY); // wait for it to end of transaction
//junk = ReadSPI2();
//mPORTBSetBits(BIT_0);
//}
void ram_write_byte(int addr, char data){
int junk;
// set 32-bit transfer for read/write command ORed with
Mode32();
mPORTBClearBits(BIT_0);
WriteSPI2(RAM_WRITE_CMD | addr); // addr not greater than 17 bits
while (SPI2STATbits.SPIBUSY); // wait for it to end of transaction
junk = ReadSPI2(); // must always read, even if nothing useful is returned
Mode8();// actual address// set 8-bit transfer for each byte
WriteSPI2(data); // data write
while (SPI2STATbits.SPIBUSY); // wait for it to end of transaction
junk = ReadSPI2();
//mPORTBSetBits(BIT_0);
return ;
}
int ram_read_byte(int addr){
int junk, data;
Mode32();
mPORTBClearBits(BIT_0);
WriteSPI2(RAM_READ_CMD | addr); // addr not greater than 17 bits
while (SPI2STATbits.SPIBUSY); // wait for it to end of transaction
junk = ReadSPI2();
Mode8();
WriteSPI2(junk); // force the read
while (SPI2STATbits.SPIBUSY); // wait for it to end of transaction
data = ReadSPI2();
//mPORTBSetBits(BIT_0);
return data;
}
void __ISR(_ADC_VECTOR, IPL2AUTO) ADCHandler(void) // Fonction d'interruption Timer 3
{
int junk;
mAD1ClearIntFlag();
//junk = 0xcccc;
PORTBbits.RB7 ^= 1;
temp = ReadADC10(0);
WriteSPI2((temp&0x300)>>8);
while (SPI2STATbits.SPIBUSY); // wait for it to end of transaction
junk = ReadSPI2();
WriteSPI2(temp&0x0ff);
while (SPI2STATbits.SPIBUSY); // wait for it to end of transaction
junk = ReadSPI2();
//a2dvals[k] = (temp);
k++;
if (k>totaldata1)// && sampling == 's')
{
T3CONCLR = 0x8000;
mPORTBSetBits(BIT_0);
a2don=FALSE;
chunks_sent = 0;
totaldata = k/2;
k = 1;
PORTBbits.RB7 = 0;
}
}
void main(void)
{
char buf[1024]; // declare receive buffer with max size 1024
//volatile SpiChannel spiChn = SPI_CHANNEL2 ; // the SPI channel to use
//volatile int spiClkDiv = 4 ; // 20 MHz max speed for this RAM
PPSOutput(2, RPB5, SDO2);//SDO2 (MOSI) is in PPS output group 2, could be connected to RPB5 which is pin 14
PPSInput(3,SDI2,RPA2);//SDI2 (MISO) is PPS output group 3, could be connected to RPA2 which is pin 9
mPORTBSetPinsDigitalOut(BIT_0);//
mPORTBSetBits(BIT_0);
SpiChnOpen(spiChn, SPI_OPEN_ON | SPI_OPEN_MODE16 | SPI_OPEN_MSTEN | SPI_OPEN_CKE_REV , spiClkDiv);
PPSInput (2, U2RX, RPB11); //Assign U2RX to pin RPB11 -- Physical pin 22 on 28 PDIP
PPSOutput(4, RPB10, U2TX); //Assign U2TX to pin RPB10 -- Physical pin 21 on 28 PDIP
SYSTEMConfigPerformance(SYSCLK);
UART2Configure(9600); // Configure UART2 for a baud rate of 9600
U2MODESET = 0x8000; // enable UART2
ANSELBbits.ANSB2 = 1; // set RB2 (AN4) to analog
TRISBbits.TRISB2 = 1; // set RB2 as an input
//adcConfigureManual(); // Configure ADC
//AD1CON1SET = 0x8000; // Enable ADC
SYSTEMConfig(SYSCLK, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE);
// the ADC ///////////////////////////////////////
// configure and enable the ADC
CloseADC10(); // ensure the ADC is off before setting the configuration
// define setup parameters for OpenADC10
// Turn module on | ouput in integer | trigger mode auto | enable autosample
// ADC_CLK_AUTO -- Internal counter ends sampling and starts conversion (Auto convert)
// ADC_AUTO_SAMPLING_ON -- Sampling begins immediately after last conversion completes; SAMP bit is automatically set
// ADC_AUTO_SAMPLING_OFF -- Sampling begins with AcquireADC10();
#define PARAM1 ADC_MODULE_ON|ADC_FORMAT_INTG32 | ADC_CLK_TMR | ADC_AUTO_SAMPLING_ON //
// define setup parameters for OpenADC10
// ADC ref external | disable offset test | disable scan mode | do 1 sample | use single buf | alternate mode off
#define PARAM2 ADC_VREF_AVDD_AVSS | ADC_OFFSET_CAL_DISABLE | ADC_SCAN_OFF | ADC_SAMPLES_PER_INT_1 | ADC_ALT_BUF_OFF | ADC_ALT_INPUT_OFF
//
// Define setup parameters for OpenADC10
// use peripherial bus clock | set sample time | set ADC clock divider
// ADC_CONV_CLK_Tcy2 means divide CLK_PB by 2 (max speed)
// ADC_SAMPLE_TIME_5 seems to work with a source resistance < 1kohm
#define PARAM3 ADC_CONV_CLK_SYSTEM | ADC_SAMPLE_TIME_5 | ADC_CONV_CLK_Tcy2 //ADC_SAMPLE_TIME_15| ADC_CONV_CLK_Tcy2
// define setup parameters for OpenADC10
// set AN4 and as analog inputs
#define PARAM4 ENABLE_AN4_ANA
// define setup parameters for OpenADC10
// do not assign channels to scan
#define PARAM5 SKIP_SCAN_ALL
// use ground as neg ref for A | use AN4 for input A
// configure to sample AN4
SetChanADC10( ADC_CH0_NEG_SAMPLEA_NVREF | ADC_CH0_POS_SAMPLEA_AN4 ); // configure to sample AN4
OpenADC10( PARAM1, PARAM2, PARAM3, PARAM4, PARAM5 ); // configure ADC using the parameters defined above
ConfigIntADC10(ADC_INT_PRI_2 | ADC_INT_ON);
EnableADC10(); // Enable the ADC
OpenTimer3(T3_ON | T3_SOURCE_INT | T3_PS_1_1,2000);
INTEnableSystemMultiVectoredInt();
mPORTBSetPinsDigitalOut(BIT_7); //Set port as output
PORTBbits.RB7 = 0;
SerialTransmit("Hello! Enter 'a' to do ADC conversion \r\n");
unsigned int rx_size;
while( 1){
rx_size = SerialReceive(buf); //, 1024); // wait here until data is received
SerialTransmit(buf); // Send out data exactly as received
SerialTransmit("\r\n");
}
/*while(1)
{
while(a2don);
a2don=TRUE;
}*/
return 1;
} // END main()
/* UART2Configure() sets up the UART2 for the most standard and minimal operation
* Enable TX and RX lines, 8 data bits, no parity, 1 stop bit, idle when HIGH
* Input: Desired Baud Rate
* Output: Actual Baud Rate from baud control register U2BRG after assignment*/
int UART2Configure( int desired_baud){
U2MODE = 0; // disable autobaud, TX and RX enabled only, 8N1, idle=HIGH
U2STA = 0x1400; // enable TX and RX
U2BRG = Baud2BRG(desired_baud); // U2BRG = (FPb / (16*baud)) - 1
// Calculate actual assigned baud rate
int actual_baud = SYSCLK / (16 * (U2BRG+1));
return actual_baud;
} // END UART2Configure()
/* SerialTransmit() transmits a string to the UART2 TX pin MSB first
*
* Inputs: *buffer = string to transmit */
int SerialTransmit(const char *buffer)
{
unsigned int size = strlen(buffer);
while(size)
{
while( U2STAbits.UTXBF); // wait while TX buffer full
U2TXREG = *buffer; // send single character to transmit buffer
buffer++; // transmit next character on following loop
size--; // loop until all characters sent (when size = 0)
}
while( !U2STAbits.TRMT); // wait for last transmission to finish
return 0;
}
/* SerialReceive() is a blocking function that waits for data on
* the UART2 RX buffer and then stores all incoming data into *buffer
*
* Note that when a carriage return '\r' is received, a nul character
* is appended signifying the strings end
*
* Inputs: *buffer = Character array/pointer to store received data into
* max_size = number of bytes allocated to this pointer
* Outputs: Number of characters received */
unsigned int SerialReceive(char *buffer) //, unsigned int max_size)
{
//unsigned int num_char = 0;
/* Wait for and store incoming data until either a carriage return is received
* or the number of received characters (num_chars) exceeds max_size */
while(1)
{
while( !U2STAbits.URXDA); // wait until data available in RX buffer
*buffer = U2RXREG; // empty contents of RX buffer into *buffer pointer
if (*buffer == 'a')
{
ram_write_byte(0x0,0x0);
mPORTASetBits(BIT_0);
num_channels = 1;
totaldata1 = 25500;
a2don=TRUE;
T3CONSET = 0x8000;
k=0;
PORTBbits.RB7=1;
while(a2don);
//(i=0);
//for (i=0;i<5000;i++);
int temp1=ram_read_byte(0x0) ;
for(i=0;i<2000;i++)
{
WriteSPI2(junk); // force the read
while (SPI2STATbits.SPIBUSY); // wait for it to end of transaction
temp1 = (ReadSPI2()&0x03)<<8;
WriteSPI2(junk); // force the read
while (SPI2STATbits.SPIBUSY); // wait for it to end of transaction
temp1 += ReadSPI2();
dummy = temp1/1000 ;
tempstr[0] = dummy + 0x30;
dummy1 = temp1- dummy*1000;
dummy = dummy1/100;
tempstr[1] = dummy + 0x30;
dummy1 = dummy1 - dummy*100;
dummy = dummy1/10;
tempstr[2] = dummy + 0x30;
dummy1 = dummy1 - dummy*10;
tempstr[3] = dummy1 + 0x30;
//tempstr[4] = "\0";
//printf("%d\n",a2dvals[i]);
//PORTBbits.RB7=0;
printf("%c%c%c%c \n", tempstr[0],tempstr[1],tempstr[2],tempstr[3]);
}
a2don=TRUE;
mPORTBSetBits(BIT_0);
}
PORTBbits.RB7=0;
}
return 1;
}// END SerialReceive()
AI: You will not be able to sustain that data rate through standard serial communication and OS drivers. The maximum normal data rate is 115200bps, which translates to 11520 bytes per second (8-N-1), or ~5700 samples per second at 2 bytes per sample (with no intervening commas, carriage returns, or tabs). Some UARTs and programs might be able to handle faster data rates than that, but you are outside of standard territory.
Even if you use a USB-capable micro controller, the OS driver in your computer would limit your data rate. Although in principle 2Mb/s is possible with some Arduino boards, your PC driver will determine what is the maximum data rate you will achieve. While a Mac or Linux serial driver would be able to handle such data rates, a standard Windows USB serial driver would quickly exceed its limits.
If you do not need continuous sampling and you have enough internal memory, store your samples in memory first and then, after you are done, send the data to the PC. That way the communications will not interfere with your sampling rate. It is a good idea to do this anyway, provide some local buffering so that your sampling rate is not affected by small hiccups in communications. |
H: Question about a high voltage setup/scenario
I was wondering what would occur in the following setup. Say you have an circuit basically like this:
V1 is a source of high voltage (high enough for corona discharge to occur), and no current can flow through the source. The resistor has a high enough resistance that most of the current from the source leaves as corona discharge through the open wires. The capacitor is initially charged to the same voltage as V1, and no corona discharge or leakage can occur from the capacitor, so it can only discharge by arcing across the small air gap and then through R1. What I was wondering is does/can the corona discharging electricity from V1 prevent the capacitor from discharging?
AI: Corona will create a conductive (ionized) path between the two nodes labeled V1, and they will have the same voltage as long as the path exists.
If you turn off the high-voltage generator, both nodes will discharge through the resistor until the ionization disappears. After that, the left node will continue to discharge, but the capacitor will not. |
H: Why do designers use op-amps with fractional gains?
I often find designs like the following
simulate this circuit – Schematic created using CircuitLab
Where the gain is less than one (\$\ R_2/R_1 < 1\$)
Why not simply use a resistive voltage divider? Beyond the inversion (which tends to be irrelevant in many applications), a divider with \$\ (R_1-R_2) \& R_2 \$ would produce the same output with the same input impedance. Plus, it will not have an offset problem, an input bias current problem, a transistor noise problem, or a bandwidth problem (adding a couple of capacitors can make it basically flat in frequency).
Although my first instinct is to regard this as a possible instability (gain beyond the op-amp specification), I see that it is basically a stable trans-conductance amplifier with the input current given by \$\ V_{in}/R_1 \$, so that is not a valid objection.
AI: Why not use just a voltage divider? It decouples the input and output circuits.
The output impedance is low
The input impedance is R1
The load has no effect on the input impedance
The last one is particularly important, as changing the load on the previous stage can have unexpected effects, e.g. changing frequency response or nonlinearity.
Why use this rather than a voltage divider and unity gain follower, for applications where phase doesn’t not matter?
Same number of components
The opamp’s inputs are at ground which is best for performance. |
H: Choosing correct relay for LED power supply rating
I have a 500W 24V power supply for running 24V LED strips. The power supply says it's rated for ~21 amps (500W / 24V). Assume input is US 120V household power.
I want to control the 120V supply with a relay driven by 5V Arduino logic signal.
I'll be driving 4x 24V 96W LED strips.
From A = W / V:
A = (4 * 96W) / 24V = 16
Does this mean I need a relay rated for 16 Amps or 21 amps listed on the power supply specs?
OR
Do I work back to Watts from the relay's specs?
Example relay is rated at 5A / 220V AC:
W = 5A * 220V = 1100
Though I've read choosing a 16A or above relay is a good idea since it shouldn't be the first thing that fails in a power surge.
More info:
Here's the power supply I have:
https://www.amazon.com/gp/product/B01IU8QBCO/ref=oh_aui_detailpage_o07_s00?ie=UTF8&psc=1
And will be purchasing one of these for 12V landscape lighting:
https://www.amazon.com/gp/product/B06XR3ZLSG/ref=ox_sc_saved_title_8?smid=A3S4SVMWTDK1H2&psc=1
Looking at a relay like this to be on the safe side:
https://www.amazon.com/AC100V-250V-2-Channel-High-low-Trigger-Arduino/dp/B077W1NVLM/ref=pd_ybh_a_15?_encoding=UTF8&psc=1&refRID=RAE8FR66XX0GN9YQANXR
EDIT: Suggested alternative:
Though I'm confident wiring mains I like to avoid it. I'd suggest anyone not confident to go buy one of these (I'll be getting one for my project):
https://www.adafruit.com/product/2935
https://www.amazon.com/Iot-Relay-Enclosed-High-Power-Raspberry/dp/B00WV7GMA2/ref=sr_1_1?s=wireless&ie=UTF8&qid=1542226953&sr=1-1&keywords=Controllable+Four+Outlet+Power+Relay#customerReviews
AI: It depends on which side you are switching.
If you're switching the secondary then you got it right.
A = (4 * 96W) / 24V = 16
Choosing a 16 A relay here is fine but it might be a good idea to choose a higher rating to be on the safe side.
If you are switching the mains voltage, I suggest the following:
Looking at the information given we can see that the power supply has an efficiency of 82% and a maximum power output of 500W. With this information we can calculate the maximum power input by taking:
500 W / 0.82 = ~610 W
With this information we can now calculate the current on the primary side:
610 W / 120 VAC = ~5,1 A
So a relay rated for atleast 5 A would be enough in your case since you won't be using the full 500W.
Be careful if you choose to control the primary side! |
H: Why high quality broadcast studio monitors use a middle range AB amplifier?
I had an issue with my Genelec 8010A studio monitors. Until recently I was truly happy with these monitors. The sound quality is exceptional, pure, precise the dynamic is impressive even though you need a subwoofer to have a better cover the low frequencies.
Anyway, one of my speaker stopped working few days ago and I decided to take a deep look. The active monitor is based on a embedded TDA7269A (AB, 2x14W, 0.03..0.7% THD). I am not an expert in audio electronics, but I am a bit surprised that such products use a very middle range integrated amplifier.
Is this something surprising. I would like to get an "engineering rationale" for this kind of technical choices.
AI: Monitor speakers are made like any other product, and therefore made to cater for a certain type of customers. Monitor speakers are a bit of a niche market, which means that the manufacturer has to maximise the amount of profit on the amount the customers are willing to pay for.
The engineer's job is to make the best product possible for the lowest cost, and here is where compromised come into play. In this case the lowest cost is defined by how much the sales department allows you to spend.
This budget will define the components that can be used in this product, so if the best transducers that can be fitted into the monitor have a distortion of, let's say 1%, there is no point in selecting an amplifier that has a distortion of 0.1%. In the same way selecting an A class amplifier, will require a much larger power supply which will eat into the already small budget.
It is all down to compromises, and the engineer's job is to design the best product that a limited amount of money can buy.
An experienced engineer will also choose the components in a way that speakers will have a frequency response that is as linear as possible to the human ear, and therefore compensating for any of the flaws of the other parts in the system. |
H: How do I remove the offset from the DAC output and change the range?
This DAC has an output range of 1-3 volts. Here's the datasheet:
Datasheet
I'm getting pulses with different amplitudes, frequencies, duty cycles and widths varying from 0.2 ms to 2 s from the DAC. I want an output range of 0-4 volts instead (Vcc=5v). I tried a high-pass RC filter, and then amplified it with an op-amp, but the output doesn't look like a pulse anymore. Also, I tried the circuit suggested in the datasheet (page 8) with no luck. I'm not sure what values I should assign to this circuit, since I don't understand how it functions.
How should I go about this?
AI: If you want pulses to stay looking like pulses, you need to avoid any circuitry that has any frequency response at all, but this DAC is clearly intended for audio use, where the output would be AC coupled to the next stage by a capacitor, but that's not possible if you want a near-DC response.
If the output at a '0' input is predictable at 2V, to get from a 1-3V output to your desired 0-4V output you need to to subtract 1V and multiply by 2. Fortunately that's easy to do with a single op-amp.
V2 is a reference voltage, you can do that with a divider of reasonably low impedance, or a reference voltage source. If you have a spare op-amp, using that as a buffer for the reference will stabilize things. V1 is the input from your DAC. |
H: Is this capacitor polarized?
I recovered a few capacitors of this style from an old cassette player. As far as I can tell, it seems like Mylar film, but the “100⊖” marking has me wondering. Is this some peculiar shaped tantalum capacitor, or is the indicator not a polarity marking?
AI: My guess would be 10 nF mylar (first 2 digits = 10, third = multiplier 10^3 pF) 100 V. J = 5 %. I reckon that 10 nF is too small for a tantalum so I don't think this is polarized. |
H: Operational amplifier for higher slew rate
what are the possible ways to improve slew rate of an operational amplifier in CMOS technology?
AI: What defines the SlewRate? dv/dt = I/C
Many opamps have an internally-compensated "BIG CAP" approach.
Examine the schematic of the Fairchild UA709, find its several Rs and Cs that provide the stabilization, and understand that.
Then ask yourself once again ----- what defines the SlewRate?
Its still working with Q = C * V, differentiated and assuming C is constant, to arrive at dV/dT = I/C. |
H: DSP Library not working in MPLAB X
I have to make a digital filter with a dsPIC30F4011 (I'm completely new to microcontrollers). I was reading the documentation about the DSP Library to figure out how to use it. I created a simple C program based on a piece of code I saw in the documentation:
#include <stdio.h>
#include <stdlib.h>
#include <p30F4011.h>
#include <dsp.h>
#include <xc.h>
int main(int argc, char** argv) {
fractional *dstV;
fractional srcV1[2] = {Q15(0.2), Q15(0.2)};
fractional srcV2[2] = {Q15(0.5), Q15(0.5)};
dstV = VectorAdd(2, dstV, srcV1, srcV2);
int n = 1;
return (EXIT_SUCCESS);
}
But when I build it, I get the following messages:
build/default/production/main.o(.text+0x22): In function `_main':
: undefined reference to `_VectorAdd'
make[2]: *** [dist/default/production/test-dspic.X.production.hex] Error 255
make[1]: *** [.build-conf] Error 2
make: *** [.build-impl] Error 2
nbproject/Makefile-default.mk:135: fallo en las instrucciones para el objetivo 'dist/default/production/test-dspic.X.production.hex'
make[2]: se sale del directorio '/home/adrian/MPLABXProjects/test-dspic.X'
nbproject/Makefile-default.mk:90: fallo en las instrucciones para el objetivo '.build-conf'
make[1]: se sale del directorio '/home/adrian/MPLABXProjects/test-dspic.X'
nbproject/Makefile-impl.mk:39: fallo en las instrucciones para el objetivo '.build-impl'
BUILD FAILED (exit value 2, total time: 1s)
It says that the function VectorAdd isn't defined. Is there something wrong or missing?
AI: Adding the libdsp-elf.a library to the project from the appropriate xc16/lib directory lets the above program link properly (at least in my environment).
Review section 1.2 in the 51456b.pdf document for different ways to set it up (environment variables, including it in the library section of the project, etc. |
H: What are the optimal methods for controlling specific header pins via Micro-USB?
Besides buying a Raspberry Pi with GPIO, what is involved in creating a circuit board that can send data to specific pins through a micro-USB cable, as well as read from data from sensors? I am open to designing my own PCB or using low-cost I/O controllers, but my knowledge is limited in what is actually required to design these interfaces.
For example, one usage would be:
1) Read temperature from an external sensor
2) send data to Android application through micro-USB
3) if temp > 80, turn on LED on the PCB
If I want to create many of these circuit boards without spending a solid amount of money, what would be the best method?
AI: There are literally hundreds of micro-controllers with a USB interface, all of which can do what you want.
Most of them have example USB software.
Some of them have built-in temperature sensors, but adding an external chip like a I2C temperature sensor is easy and also eliminates the effect of the power of the controller.
You have to develop a tiny PCB with the chip(s) on them.
I found writing the USB software at the PC/Android side the most challenging.
My guess is a prototype can be made for about $100 if you do it all yourself.
Production price greatly depends on the volume.Your biggest cost in 10-100 up volume will be the assembly house. I estimate the materials at that volume are between $5 and $10 per board. |
H: Sense resistance based current sensing
http://www.carotron.com/articles/current-sensing-circuit/
http://ww1.microchip.com/downloads/en/appnotes/01332b.pdf
https://www.arrow.com/en/research-and-events/articles/how-to-maximize-low-side-sensing-performance
All the above article and many other articles says that in low side current sensing, if there is any short circuit is there between power supply and ground, it goes undetected. Can anyone explain me how it is detected in high side current sensing.
AI: Here is the two in one.
simulate this circuit – Schematic created using CircuitLab |
H: Can anyone actually explain how electrons flow in a circuit?
Can anyone actually explain properly how the electrons flow in a circuit?
None of this nonsense like, electrons flow like a chain.. in some cases
Electrons flow like water in other cases
Imagine this, imagine that, no tell me what exactly happens to the electrons please
In the below diagram, a charge separation in the battery causes an electric field. When the wire is connected between the 2 terminals, what is causing the current to flow? Is it the electrons from the battery adding to the electrons in the wire, or the electric field within the battery (caused by a charge separation)?
Do electrons exert a force on one another causing them to move like a chain of marbles?
At the resistor section of the wire, electrons lose electrical energy and transfer to heat energy. Electrical energy is due to force of attraction or repulsion between charged particles.
Does the resistor slow down electrons by collision and therefore the distance separation between each electron now is greater leading to a decrease in repulsive force?
The charge per second would then be decreased
Please explain using simple words and diagrams, Mathematical equations are built from the observations and testing of processes. Which means processes come first before mathematics
AI: In the below diagram, a charge separation in the battery causes an electric field. When the wire is connected between the 2 terminals, what is causing the current to flow? Is it the electrons from the battery adding to the electrons in the wire, or the electric field within the battery (caused by a charge separation)?
A conductive wire is composed of atoms that have one or more outer electrons that are loosely bound to it. So it's "easy" for the outer electrons to walk from one atom to another: when an electron leaves an atom, a "hole" appears which needs to be filled by another electron (else the atom would become negatively charged).
When the wire is not connected to the battery, loosely bound electrons move in a "kind of random" way, from atom to atom, so the sum of all displacements is zero (hence there is no current in the wire).
When the wire is connected to the charged battery, on the right of the wire there is a deficit of electrons, meaning "a lot of holes to fill", and on the left of the wire, there is a surplus of electrons, and no "hole to fill".
So if we zoom-in on the left of the wire: if an atom A0 of the wire loses an electron, this electron will very likely go "to the right" because on the left there is no hole to fill. And the electron filling the hole of A0 will "very likely" come from the left (the battery), because on that side there are a lot more free electrons than on the other side. So this is how electrons from the battery "enter" the wire.
Now if we zoom-in on the right of the wire, we see the opposite effect, electrons leave the wire: if an atom loses an electron, this electron needs to fill a hole, and since the battery has a lot of holes, it's more likely that the electron will go to the side of the battery. And the electron replacing that electron will likely come from the wire (the left) because on the right there is a deficit of free electrons.
This is how electrons start to flow through the wire, because the sum of electron movements is now non-zero.
Do electrons exert a force on one another causing them to move like a chain of marbles?
I don't like this analogy because there is no "chain of electrons": the diameter of a wire is so huge compared to the size of an electron... It's more a "flow" of electrons.
Does the resistor slow down electrons by collision and therefore the distance separation between each electron now is greater leading to a decrease in repulsive force?
Not really, in a resistor, the outer electrons of the atoms can move from one atom to another, but they are more bound to the atom than in a conductor, so the probability that they will move is smaller. Hence, a resistor slows down the flow of electrons. |
H: Amplify my 3.3V DAC signal to 220V
In one of my projects I need to generate different kind of 220V amplitude waveform signals in order to send commands to a heater using the pilot wire protocol. Here are the needed waveforms:
Is there a way to use a DAC and then amplify the output of the DAC to a 220V amplitude. If yes which circuit and components can I use.
Otherwise I am open to other price and size optimal circuits to get such waveforms.
Many thanks
AI: A DAC and amplifier would be the expensive and complicated way to control the heater.
You have 230VAC at hand - you must, because that's what the heater operates on.
Use that 230VAC source, a few SSRs (solid state relays,) and a couple of diodes.
The control signal doesn't seem to drive the heating element directly. The commands seem to be just that: commands to a controller in the heater. That means you don't have to switch high power, and can use small SSRs and diodes to make the control signals.
Take the simple cases first:
Confort
Confort -1
Confort -2
Eco ou reduit
All four can be handled by one relay:
Relay open
Cycle relay 4 min 57 seconds off, 3 seconds on
Cycle relay 4 min 53 seconds off, 7 seconds on
Relay on
Each of the other two cases require a diode and relay each. Put a diode in series with each relay, each diode points in a different direction.
Now, you turn off the main relay, and turn on one of the two relays with a diode. Each sends a different command
Use zero crossing SSRs. These switch when the AC voltage crosses zero volts.
Use SSRs rated for use on 230VAC.
Use diodes rated with a peak inverse voltage of more than 300V.
Use diodes rated to handle more current than the command circuit requires.
Doing that, you can use three digital outputs from a microprocessor to send all commands.
Be very careful when working with 230VAC. There are many safety practices you should follow: look them up, learn them, apply them. Failure to do so can kill you.
There are many design practices to follow when designing and laying out circuits that use 230VAC. Look them up. Learn them. Follow them. Failure to do so might burn down your house or electrocute you or someone using the device. |
H: How much is the permeability of this attached inductor core?
I want to use this inductor for AC line filter as line reactor. Its inductance value is 6 mH but I don't know the exact value of permeability of the material. It will be used with VFD at the input to remove the harmonics. The input current will be from 2 to 7 A.
Could you please tell me the exact value of the permeability of this material?
AI: You need some geometrical inputs (internal and external radii, height):
Be careful: permeability depends on the magnetic field, which depends on current. |
H: How is the tuning-word of a DDS sent and coded?
I have read that a DDS have two inputs one for master clock another for the tuning word. By processing these two inputs the DDS generates the output waveform at a desired frequency.
And if I'm not wrong we need to send this tuning word to the DDS via its SPI interface.
But I cannot find information about the tuning word and is a little confusing.
What I mean is when we program a micro-controller, we code and compile and upload the data to it. And we do the coding part by using lets say C language we know what instructions do what.
But when it comes the DDS, how is the tuning word is sent/uploaded and how it is coded? Do we send it through an IDE? I have no picture about it. Can someone simplify this and give maybe an example how it is done.
That sequence with FQ UD CLKIN W CLK looks complicated to me. Is that about how SPI functions? It also seems DDS has no memory -- does it need that sequence nonstop as an input? The articles I found were too advanced for me. That's why I'm asking primitive questions.
AI: Look at page 10 and further in the AD9850 DDS datasheet to see in what sequence the data needs to be presented to the DDS. Often a microcontroller is used to generate the signals as described in this datasheet.
It is similar to how you would write data to a memory chip. A certain sequence must be observed. This DDS is not very different in that respect.
I suggest to first familiarize yourself with the concept of communication over SPI and then look at the details of how that works on this DDS.
SPI just describes how the (data) bits get from A to B. The FQ, UD, CLKIN etc.. are just names for the registers in the DDS.
It also seems DDS has no memory needs that sequence nonstop as an input?
Fortunately the DDS does have memory, although they're called registers in essence these are just small memories. The DDS would be unable to function in a useful way without it. When you write settings, it uses those until you write new values or you switch the DDS off (obviously).\
There are some projects available on using an Arduino with the AD9850 |
H: How can a dominant state be the one with bigger voltage difference?
I am studying about CAN buses, and there is one thing I just can't find an explanation for. I understand that the idea of a wired-and connection is, that if any node is driving the bus to the dominant state, the bus will get to the dominant state regardless of the number of nodes transmitting a recessive state.
However, I find that in CAN the dominant and recessive states are as shown in the image below.
I could easily image an implementation like this, if it was the other way around, and the dominant state was the one where the wires are on the same voltage level:
But this implementation would result in the states being swapped. So how is it possible for the dominant state to be the state with the voltage difference?
AI: CAN drivers are like this
simulate this circuit – Schematic created using CircuitLab
For example. |
H: Asynchronous write to EEPROM
There is Stm32l052 with built-in EEPROM (2k). 4 ADC channels are used, data is collected by the trigger every 40 microseconds. Data from the ADC is processed in the interrupt (determined by the output of values beyond the boundaries). So, using the standard Hal libraries during recording in EEPROM points are lost (3 milliseconds standard write speed in EEPROM data), even if you write one byte from the ring buffer. Is there any way to get the controller to write to the EEPROM asynchronously without blocking the ADC interrupts?
AI: STM32L052 appears to have a single bank NVM controller, therefore a write access to any EEPROM address would block data reads and fetches from flash.
It would work only if you can relocate all relevant code, except initialization, but including the vector table, to RAM. It would be quite a challenge to do in 8 kbytes, but it might work. Forget about HAL, it has too much overhead and complexity.
I'd recommend doing it this way:
Relocate NVIC to RAM
ADC interrupt handler in RAM, puts data in the ring buffer, invokes PendSV (SCB->ICSR=SCB_ICSR_PENDSVSET).
PendSV fault handler in RAM, as long as there is data to be written, puts a single 32 bit word† in EEPROM, and waits until the write completes. Do not return while NVM is still busy.
ADC handler should have higher priority as PendSV.
The rest of the code can be left in flash as long as the delay is acceptable. Interrupt handlers in flash should have lower priorities than PendSV.
This arrangement would prevent any code in flash from running as long as an EEPROM write is in progress, but lets higher priority handlers run as long as they do not touch nonvolatile memory.
To relocate a function to RAM
With gcc, use __attribute__((section(".data"))) in the function declaration. Do it recursively to each function it calls. Use -ffreestanding to prevent gcc from generating calls to library functions unexpectedly. The .data section will be copied from flash to RAM after reset, along with initialized variables, by the startup code.
To relocate the vector table
The vector table of the STM32L052 is 192 bytes long (Reference manual 12.3 Interrupt and exception vectors). I'd just move the beginning of RAM up by 192 bytes in the linker script
RAM (xrw) : ORIGIN = 0x200000C0, LENGTH = 8000 /* 8192 - 192 */
copy the vector table there, and set the vector table pointer
memcpy((void*)0x20000000, (void*)0x08000000, 192);
SCB->VTOR = 0x20000000;
before any interrupt is enabled.
Using STM32L072 instead, it would be possible to let the program run from Bank 1, and placing EEPROM data in Bank 2, they would not interfere with each other. Of course it would still take 3 ms (or 6 ms if it's not empty) to write a 32 bit word† into EEPROM, attempting to write more data before the first write is completed would still block program execution until the first one completes. Check the Reference manual for the bank layout (3.3.1 NVM Organization)
† AFAIK EEPROM data is written in 32 bit units, writing 1 or 2 bytes at a time takes just as much time as writing a full 4-byte word. |
H: VHDL Error " Integer literal is not of type ieee.std_logic_1164.STD_LOGIC_VECTOR."
I'm new to VHDL and I'm getting the following error when I try to compile my code:
** Error: F:\midterm night\assg 3\toplevel_design.vhd(18): near "<byte 0x93>": illegal character found in source
** Error: F:\midterm night\assg 3\toplevel_design.vhd(18): near "<byte 0x94>": illegal character found in source
** Error: F:\midterm night\assg 3\toplevel_design.vhd(18): Integer literal 0 is not of type ieee.std_logic_1164.STD_LOGIC_VECTOR.
Seems the problem is variable memory_block assignment.
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity mem8_16 is
port( clk,wr_rd : in std_logic;
din : in std_logic_vector ( 15 downto 0);
addr : in std_logic_vector ( 2 downto 0);
dout : out std_logic_vector (15 downto 0));
end entity;
architecture memory of mem8_16 is
signal memory_temp :unsigned (127 downto 0);
begin
process(clk,wr_rd)
variable memory_block: integer range 0 to 7;
begin
if (rising_edge(clk))then
case addr is
when “000” => memory_block := 0;
when “001” => memory_block := 1;
when “010” => memory_block := 2;
when “011” => memory_block := 3;
when “100” => memory_block := 4;
when “101” => memory_block := 5;
when “110” => memory_block := 6;
when “111” => memory_block := 7;
end case;
if (wr_rd ='1') then
memory_temp((memory_block * 16 + 15) downto (memory_block * 16)) <= din (15 downto 0);
end if;
end if;
dout <= memory_temp((memory_block * 16 + 15) downto (memory_block * 16));
end memory;
AI: The problem is that you have used some sort of word processor to create your source code, and it has inserted left- and right-double-quote characters (“ - 0x93 and ” - 0x94) rather than a proper ASCII double quote (" - 0x22) as delimiters around your string literals.
Use a code editor to edit code, and use the word processor to edit documentation.
Note also that there's no end statement for your process. |
H: A question on factors affecting the offset removal of an opamp circuit
I will use a function generator module which outputs 0-1V sine-wave for frequencies of interest from 0.5Hz to 30kHz importance. So my input will be 0-1V sine wave but I want to obtain an AC sine wave with 1V amplitude and 0V offset i.e symmetric swing. I also want to achieve this not by using too complicated circuitry.
Theoretically below circuit works to eliminate such offset:
And here is the output 1V with symmetric swing:
I don't have experience with these but I have couple of questions:
1-) What component in practice should replace Voff for a better accuracy? Voff can be a voltage divider or a reference voltage; but what in practice is better for a reliable offset removal?
2-) The circuit above assumes that the incoming sine is always a 1Vpp with 0.5V offset. What if the Vin's offset varies, is there a solution for that? I mean is there a zero offset Vout solution for a possible varying offset of Vin?
I don't know what is the main issue in such circuits so these are the questions I need to figure out. Maybe some other things like power supply stability, opamp type ect. more important. It would be great to hear if some could share experience.
AI: Within the limits of the frequency band that you are interested in the "easiest" way to remove DC offset from an AC waveform would be to use AC coupling at the input of your amplifier using a suitable capacitor.
Another possible way is to sample the input AC waveform with a long time constant low pass filter filters enough to pass just the average value of the AC signal. You could then try to use that filtered voltage to subtract the offset from the original AC waveform.
Both of these approaches will self adjust for variation in input signal amplitude and offset. They are not a perfect solutions however because if the changes in amplitude or offset happen too fast they will not be tracked by the long time constants in the respective circuits. |
H: Measuring phase shift between current and voltage with microcontroller
I am trying to understand how this design is used to measure phase shift between current and voltage of an AC signal. From my understand there should be a PWM signal generated on the output. Resistors R3 and R4 are there to drop the 12 V output of the OP amp to 5 V. Resistor R2 is limiting the current through the diodes D1 and D2. However, I do not understand how the voltage drop on R1 and R5 is phase shifted by the same phase as the current and voltage of the source V1. Can someone please explain that?
simulate this circuit – Schematic created using CircuitLab
UPDATE: Schematic has been corrected.
AI: From my understand there should be a PWM signal generated on the output.
Yes, the pulse width being the difference in phase.
Resistors R3 and R4 are there to drop the 12 V output of the OP amp to 5 V.
Correct.
Resistor R2 is limiting the current through the diodes D1 and D2.
Correct.
However, I do not understand how the voltage drop on R1 and R5 is phase shifted by the same phase as the current and voltage of the source V1. Can someone please explain that?
It isn't. The schematic is not correct. One of the transformers should be monitoring the supply voltage so it should be directly across the supply. The other transformer should be monitoring the supply or load current so it should be in series with the load - and there is no load in the schematic!
Once the transformer problems are addressed the rest should work.
Safety: remove the primary-secondary link at the bottom of XFMR2.
simulate this circuit – Schematic created using CircuitLab
Figure 1. Modified schematic showing load connection point.
Note that the load current goes through the CT - usually one or a few turns. I've shown the current path in thicker lines. |
H: Norton's equivalent circuit with independent sources
I need to find the current flowing through \$R_{5}\$ by using Norton's theorem.
What I tried to do was:
Open-circuit the part of the circuit where there is \$R_{5}\$.
Calculate \$R_{n}\$ by open-circuiting the independent current sources (that is, \$I_{1}\$) and short-circuiting the voltage sources (\$V_{1}\$).
Calculate \$I_{n}\$ by short-circuiting the part where there is \$R_{5}\$.
So,
2.
$$R_{n}=R_{4}+\frac{R_{2}R_{3}}{R_{2}+R_{3}}=7.5ohms$$
3.
I used KCL to find \$V_{C}\$:
$$\frac{V_{1}-V_{C}}{R_{3}}+\frac{0-V_{C}}{R_{2}}+\frac{0-V_{C}}{R_{1}}-I_{1}=0$$
$$V_{C}=4.18V$$
Then,
$$I_{n}=\frac{V_{C}}{R_{4}}=\frac{4.18}{6}=0.696A$$
Apparently, \$I_{n}\$ is wrong, but I can't find any mistake in my reasoning. Any idea?
AI: I'm assuming all the currents are coming into the node, and I always
leave Vc at the end of the subtraction (v1-vc, 0-vc, etc.)
For sure you can do that. But notice that the \$I_1\$ current is leaving the \$V_C\$ node.
So the \$I_1\$ current needs to have a different sign.
I will show you two cases:
First case:
I will give a minus sign if the current entering the node (coming into the node).
And the plus sign if the current is leaving the node.
$$-\frac{V_1 - V_C}{R_3} - \frac{0 - V_C}{R_2} - \frac{0 - V_C}{R_4} + I_1 =0$$
Notice that I give \$I_1\$ the plus sign because \$I_1\$ is leaving the node (current source).
Second case:
Plus sign to all the currents that are entering the node.
$$\frac{V_1 - V_C}{R_3} + \frac{0 - V_C}{R_2} + \frac{0 - V_C}{R_4} - I_1 =0$$
Do you know why I give a minus sign to \$ I_1\$?
So what is important here is that you always must be consistent with the sign convention you have chosen when you are writing nodal equations.
And of course, those two "method" will give the same answer.
And we do not take \$R_1\$ resistor into account because \$R_1\$ is in series with the constant current source. Hence, it won't change the current in this branch. |
H: What happens when an op amp misses one of the power rails?
I would like to know what happens when a dual power supply op amp misses one of the power rails and what kinds of damage I can expect for op amp.
What prompted this question:
I have a analog PID module from SRS (SIM960). It usually works in a mainframe that supplies the power but because of space constraints I had to supply powers myself (+5V for digital and +/-15V for analog). It worked for a while, but yesterday I discovered that -15V connection had been un-plugged by accident, and the PID module was not behaving correctly. I promptly fixed the connection but now the module seems damaged. At least the input pre-amp section is damaged. The (P gain * error) value does not read correctly, and it seems to be at an almost fixed value, not responding to change in polarity, P gain, or error itself.
The online manual for SIM960 does not show the schematic diagram, and I don't think I can post a copy of the diagram from the paper manual, so the input preamp section looks like instrumentation amplifier followed by some op amps for proportional gain. All the op amps are OPA228/OPA2228.
AI: It depends a lot on the topology and the specific devices involved, so without a schematic to review this will be a fairly general answer, but generally the damage conditions are similar to those that occur when a device's IO voltage ratings are exceeded. Essentially, the op-amps power rails will be floating, but likely pulled towards ground (or the opposite supply rail) by all of the devices connected across those same power rails. This includes other ICs, as well as voltage dividers, indicator LEDs, bulk/bypass caps, etc.
So as a a starting condition we can assume that the floating rail--which we'll assume is the negative one since that's the case in your situation--is at the same voltage as the positive rail. Thus, any voltage applied to an input or output pin that is less than the positive rail is effectively outside of the op-amps supply rails. On many devices, this will cause current to flow through parasitic junctions or ESD protection diodes from the input pin to the negative supply rail. If the source impedance is low enough, enough current can flow that the floating negative rail can start to be pulled further negative--essentially the negative rail is being supplied through that signal pin. Because these parasitic junctions were never intended to supply current to the entire IC, let alone all of the surrounding circuitry, this can cause them to fail. Likewise, the ESD diodes, if present, were meant to conduct brief surges where, even though the instantaneous current may be substantial, the total energy is limited. Sustained DC current can cause these to fail as well.
It's quite common for semiconductors to fail short, in which case, depending on the exact nature of the internal failure, a device may wind up with an input or output pin shorted to a supply rail, or may even wind up with both supply rails internally shorted together, which will obviously disrupt the entire surrounding circuit. More subtle failures may also occur, that simply compromise the internal function of the device. Total failures are common, but partial failures, including changes to device parameters, are certainly possible. |
H: PID Run Away Motor Control
I have a PID controlling a DC motor. I am attempting to control the speed of the motor very precisely. My controller allows me to change the direction of the motor and give it a pwm for speed. Therefore, I have a PID that has a plus and minus maximum and minimum. In order to speed up the device and slow down the device quick enough. The output of the PID is for the pwm and therefore is a absolute value of the PID, just changing a direction pin when PID < 0. I am using the opposite direction of the motor only as a braking system. Thus the motor should always be going in one direction but should slow it self down faster by applying reverse torque.
I am writing C firmware in MCUXpresso. The graphs come from sending data over UART to an Arduino to graph data easily.
My problem is that sometimes when the process variable hits 0 or close to it, the PID inverts and needs to go negative and thus spins the motor at full speed in the opposite direction. The two pictures below show the certain cases of when it happened. The red line is the set point and the blue line is the process variable.
The code controlling the device and PID is below.
I am having a hard time understanding why the PID would run away like this. Any help would be amazing. Thank you!
Main Control
int dir = FORWARD; //Controls direction of motor
motorPID.setpoint = vehicleSpeed;
motorPID.input = SM_GetRPM();
motorPID.input = motorPID.input * speedConversion;
UART_SendPID((uint8_t)motorPID.input, (uint8_t)motorPID.setpoint);
PID_Compute(&motorPID);
if(motorPID.output < 0){
dir = BACKWARD;
}
if(motorPID.setpoint == 0){
motorPID.output = 0;
}
if(motorPID.input > 60){
MC_SetMotorSpeed(0, dir);
int test = 0;
}
MC_SetMotorSpeed(abs(motorPID.output),dir);
PID Code
//Find all error variables
self->lastError = self->error;
double input = self->input; //Only so input can't change during compute
self->error = self->setpoint - input;
self->integral += self->error;
double derivative = self->error - self->lastError;
//Anti-integral Windup
if(self->integral > self->Outmax)
self->integral = self->Outmax;
else if(self->integral < self->Outmin)
self->integral = self->Outmin;
//Calculate PID
self->output = (self->Kp*self->error) + (self->Ki * self->integral) + (self->Kd * derivative);
//Set limits
if(self->output > self->Outmax)
self->output = self->Outmax;
else if(self->output < self->Outmin)
self->output = self->Outmin;
EDIT: Turns out this was a combined error of the problem described and a hardware issue.
AI: Try changing the line that reads
self->integral += self->error;
to
self->integral += self-> Ki * self->error;
and match that by changing the line that reads
self->output = (self->Kp*self->error) + (self->Ki * self->integral) + (self->Kd * derivative);
to
self->output = (self->Kp*self->error) + self->integral + (self->Kd * derivative);
That will scale the integral term correctly for your integrator limiting step. |
H: Why is my DC motor making a rattling scraping sound?
The DC motor on my hob extractor fan is making a rattling and scraping sound when I switch it on. I know it is coming from just the motor because I have tried running the motor on its own. What could be causing this sound? How can it be fixed? Thanks!
AI: Its almost always bearings. chances are if its scraping already, they'll be right full of tiny metal filings in the grease. If you have the luxury of being able to dissassemble it somewhat, check them all with an IR thermometer or similar, the hot one is the one you want to fix, but perhaps you should give them all a little grease for longevity's sake.
then pull the bearing (there are tools, but sometimes you just have to get creative), and just find the same bearing again online... just like electronics, everything's marked and described on the part... or there's a datasheet.
I'll entertain the possibility of the brushes being worn out too, but that tends to result in near total failure rather than rattling and scraping |
H: Current spikes on rising and falling edge of NPN BJT switch
I am simulating a simple NPN BJT switch for PWM in LTspice, and I observe some current transients on the rising and falling edges that I do not understand. The circuit is here:
Picture of the falling edge:
Picture of the rising edge:
On the falling edge, why does the current through base resistor R3 go negative by ~1 mA? Is there a way to eliminate this such that the PWM voltage source does not have to sink this current?
On the rising edge, why does the load (R6) current go negative by ~1 mA? Is there a way to eliminate this such that the voltage source V3 does not have to sink this current?
EDIT: I put D1 there to prevent Q1 from entering saturation (Baker clamp with a single Schottky diode). The current through D1 on the falling edge mimics the current through R3, but slightly smaller in magnitude. On the rising edge, the current through D1 is plotted in the following picture:
Edit 2: Removing D1 only serves to increase the turn-off delay, as expected. With D1, adding a 22 pF capacitor across ce junction of Q1 has no effect. Why the value of 22 pF anyways? Adding 100pF or more across R6 appears to help reduce the negative current draw on the rising edge.
AI: Unless you over dampen the circuit with 100pF capacitors across R6, fast rise and fall times will always cause some type of overshoot and undershoot. If it is bad enough it becomes a decaying ring wave. D1 may play some part in the negative current, as it does bypass the cb junction of Q1. But Schottky diodes do help with overall rise and fall times by lowering the effect of base capacitance. You do not want to over-dampen circuits that switch power, as this can increase overall power consumption itself.
If you look at the output waveform of fast logic IC's or PWM supplies you will notice at least some amount of overshoot and undershoot. The best you can do is make it small enough not to cause ringing or exceed the voltage rating of the driver (Q1 in this case) or cause the next stage (logic gate, etc) to behave in the wrong way.
Run the same test without D1 and see the results. Run the same test with D1 and a 22pF capacitor across the ce junction of Q1. You may find that no compromise is perfect, as having one issue reduced brings up another issue.
NOTE: If you can slow down the rise and fall times of your signal source then overshoot and undershoot problems should go away, but your design using a Schottky diode implies you are doing this intentionally? |
H: What does 1 and 0 mean on this power supply?
I have a Shaw Scientific power supply. On the front there is a switch to set the voltage from 0 to 12 volts. There is an on/off switch. There are connections for ac and also for dc. Then there is a switch with two options, 1 and 0. What could this function be ?
AI: If you are referring to the two dials, they are used to set the voltage - hence the label "Set Voltage".
At a rough guess you select the voltage you want from the sum of the two dials. The left dial gives you even voltages (multiples of two), and then use the right dial to achieve odd numbers.
For example 9V would be selecting the "8" on the left dial, and "1" on the right dial, to give you 8+1=9V. You can select 4V by selecting "4" on the left dial, and "0" on the right dial giving 4+0=4V.
You can confirm or reject this assumption by testing the power supplies. |
H: How does the transistor topology look like for a gate of this logic inverter?
How does a single inverter gate of this hex inverter, look like in transistor level?
I don't mean the actual photo, but how does the transistor topology look like?
Does the BJT inverter (see below), with two resistors, represent the exact topology of the gate of a hex inverter IC?:
AI: The schematic you show is a very primitive RTL (resistor-transistor-logic) inverter.
The datasheet you linked to is for a 74HCT04. The "C" stands for CMOS — it doesn't use BJTs at all. For some reason, they don't usually show the transistor-level schematics for CMOS gates — probably because the logic schematic would be totally obfuscated by input and output protection circuits.
If you want to see how it's done in other logic families, just look at the datasheets. For example the 7404 datasheet from TI covers 7404, 74LS04 and 74S04. |
H: Average Inductor Voltage equals Zero?
Okay I already read this post which answers the question mathematically
here,
at the end of the top answer the poster said:
"Thus, the only way to keep current from going to infinity is the condition I(T)=0
"
So does this means that the indcutor does not have some property that it magically makes any periodic waveform have an average voltage of zero, but WE are setting that integral equal to ZERO and solving for that case?
So this thing about "average inductor voltage always equals 0" is more of a rule we must impose on it, rather than something it does on its own?
If i apply a voltage to an inductor for 50mS it will rise linearly and i remove the voltage for only 1ms it will return to the initial voltage? thats a periodic waveform if i keep doing it but seems to me it would rise for ever. Which makes me wonder how then is the average zero?
and same would apply to a capacitor?
This highlighted integral.
Basically , will it always equal zero because of some physical trait of the inductor that makes it always be in a steady state, or is this telling me that we must SET it equal to zero to operate in steady state?
AI: So, that's a rule that applies to perfect inductors with the implied property that Bad Things happen if the current goes to infinity.
This is a pretty good model for the real world of power supply design, where long before you get to infinite current you get to enough current so that the magic smoke leaks out of something on your board (usually a chip, but sometimes the inductor or the board itself).
So it's only a condition imposed by the inductor in the sense that your circuit is damaged (or at least malfunctions badly) if you don't make sure it happens. |
H: How do I find the current equations for the RLC Series Circuit?
Let's talk about a RLC series circuit. R, L and C are in series with a battery and a switch. The switch is open. L and C are discharged.
At t=0, the switch is closed and the battery (V1) feeds the circuit.
To find the equation for the voltage across the capacitor, I apply KVL to the circuit and get this:
\$ V_1(t) = Ri + L\frac{di}{dt} + V_C(t) \$
this later turns in to this:
\$ \frac{V_1}{LC} = \frac{d^2V_C(t)}{dt^2} + \frac{R}{L} \frac{dV_C(t)}{dt} + \frac{1}{LC}V_C(t) \$
After a few hours or brain melting, I get the final result for the equation of voltage across the capacitor
CRITICALLY DAMPED
\$ V_C(t) = (At + B) \thinspace e^{-\alpha t} \$
OVERDAMPED
\$ V_C(t) = Ae^{m_1t} + Be^{m_2t} \$
UNDERDAMPED
\$ V_C(t) = e^{- \alpha t}[K_1 \thinspace Cos(\omega_d t) + K_2 \thinspace
Sin(\omega_d t) ] \$
The question now is: how do I find the current equations for the three cases?
The only thing I can see is that the current on a capacitor is equal to
\$ i_c = C \frac{dv}{dt} \$
If R, L and C are in series, the current is the same for the three.
So, all I have to do is to take the derivative of the voltage equations, that will give me, if there is no error in my math, the current equations...
CRITICALLY DAMPED
\$ i(t) = e^{-\alpha t}(A -\alpha At -\alpha B) \$
OVERDAMPED
\$ i(t) = m_1Ae^{m_1t} + m_2Be^{m_2t} \$
UNDERDAMPED
\$ i(t) = -\alpha e^{- \alpha t}(K1 Cos(\omega_d t) + K_2 Sin(\omega_d t) ] + \omega_d e^{- \alpha t}(K_2 Cos(\omega_d t) - K_1 Sin(\omega_d t) ] \$
Questions:
is this how you find the current equations for that kind of circuit, if not, please point me in the right direction.
are these equations for the current correct?
thanks
EDIT: I have found this page that gives the same equations for current that I have found for voltage (??)
AI: In your first equation, write \$\small V_c= \frac{1}{C}\large \int \small i\:dt \$, then differentiate the whole of this equation (including the constant source voltage).
This gives:
$$\small 0=R \frac{di}{dt}+L\frac{d^2i}{dt^2} +\frac{1}{C}i $$
Rearranging:
$$\small \frac{d^2i}{dt^2}+ \frac{R}{L} \frac{di}{dt}+\frac{1}{LC}i=0 $$
Then the auxiliary equation is: \$\small m^2+\frac{R}{L}m+\frac{1}{LC}=0 \$, etc... |
H: Expected and actual unity gain bandwidth LM324N
I have an LM324N configured as a unity gain voltage follower. The split rail power supply +/- 4.5V is provided using AA batteries. I am aware that better opamps exist, but this is for study purposes only.
simulate this circuit – Schematic created using CircuitLab
As a lab exercise, I am testing performance of the circuit at various input frequencies whilst maintaining a constant input voltage (2V sine wave). The test circuit is soldered onto prototyping board with short traces.
At low frequencies (e.g. 10kHz), the output signal closely follows the input signal. However, at 60kHz the output signal is distorted (closely resembling a triangular wave form) and has an amplitude approximately 70% of the input signal. At 1MHz, the output has an amplitude of 0.1V.
Reading the datasheet, I understand the LM324N has a Gain Bandwidth Product (GBP) of 1MHz, which suggests to me that I should not expect significant attenuation of the signal at only 60kHz. A GBP of 1MHz suggests an ideal bandwidth of 1MHz at a gain of unity. Is this really achievable and/or have I done something wrong?
AI: Gain-bandwidth product is a small signal specification. It only applies to signals under which the op-amp circuitry remains in a linear regime. That is on the order of 100mV or less for a conventional differential input stage.
With the relatively high frequency 2V you are applying you are well into a large signal regime in which non-linear effects take precedence. The specification that applies in that regime is the slew rate of the amplifier.
Slew rate limitations are caused by how fast the internal bias currents are able to charge the internal (compensation) capacitances. |
H: High voltage to low voltage in ps/nanosecond time (Zener/opamp?)
So I have a signal that goes from 0 to ~800volts in 30ns. I would like to use this signal to trigger a camera (input impedance of 50ohm) which takes a max of 10 volts and requires the rise time to be 1ns for this 10 volts.
I tried a 10 volt zener diode which works... but delays the signal a lot (not sure why) so I get 10 volts in 8ns instead of 1ns. [People said zeners are made for DC and not so much for high frequencies, so maybe thats why]
I then thought of using attenuators to make the signal go from 0 to 10 volts (instead of 800V) in 30ns then use an opamp as a comparator with a 10volt DC battery connected to +Vs and Ref, Vin-, -Vs connected to the negative side of the battery. (and ofc the main signal going to Vin+)
Since different opamps got different operating frequencies and slew rates I got this one: THS3491IDDAT
Which got a 320 MHz operating frequency and 8 kV/us slew rate
However, I was getting weird results that I wasnt able to understand and shortly after multiple legs of the op amp broke, so I wasn't able to capture the output signal
Here is the input signal which is attenuated using 38dB (div 80) [time scale is 10ns/div and voltage scale is 10v/div
Was I doing something wrong? or is there an easier circuit to use? Any recommendation for other opamps that are easy to handle? (this one was tiny)
The source is a Rogowski coil with a resistance of 4ohm and inductance of 1.4e-7 H. (1 turn coil).
Thanks in advance.
AI: Try this
simulate this circuit – Schematic created using CircuitLab |
H: Identify 4 pin Connector
I need to get some more of this connector and solder my own cables however I can't find this exact one online.
It looks like some variant of JST but from looking up the different types of JST I can't find one that matches this.
The cable came with a LiDAR sensor. One end is a JST SH 1mm and the other end is the connector I'm having trouble finding.
Can anyone help identify this connector?
Male end
Female end
AI: It appears to be a Male JST GH 4 pin connector "crimp style" with 1.25mm spacing as found here (download the catalogue page).
Part NO: GHR-04V-S |
H: Confusion on Servo and PWM (AVR)
For reference im using an AVR Atmega 328p, and the servo specs i'll be using says this:
Pulse Cycle: 20 ms (I assume this means the "period")
Pulse Width: 600-2400 µs
So from my understanding, using fast PWM and lets say a 1Mhz clock. I make the Width by setting 2 values. One when it reaches TOP-whatever width (lets pretend 1800 ms, I think people use ICR1 for this) and then the top (I think they usually use OCR1A here).
So the time between ICR1 and OCR1A (Which is the top) is where I turn the "Pin" to the Servo on correct? And then it turns off when OCR1A ends
IE: Turn on when it reaches ICR1, turn off when it reaches OCR1A. If I want a width of 1.8 ms i'd need to make that 1800 steps correct? Since 1800 "ticks" would be 1.8ms (If Im understanding my units correct)
The pulse cycle is where I get confused. That would just be the "TOP" value right? IE: if I need a 20ms pulse cycle. and every tick at 1MHz is 1/1000 of a milliseconds, so to do 20ms pulse cycle, ill need 20000 ticks. because every tick is 1/1000 of a ms
Am I thinking of this correctly? I think the "Ticks" with the CPU Frequency and then trying to get that figured out with cycles and widths is just sort of throwing me for a loop.
AI: Pulse Cycle: 20 ms (I assume this means the "period")
Yes, that's correct. You need to send 1 pulse every 20ms.
Pulse Width: 600-2400 µs
This is more or less also correct although I would note that most RC parts are designed to operate between 1000 and 2000 uS.
What you'll want to do is create a timer that overflows every 20ms. This can be a software or hardware timer.
Then, every time the timer overflows turn the output ON.
Map the timer ticks into uS, and turn the output OFF once the correct number of uS have elapsed. For example, if your timer ticks 2000 times per 20ms, and you want a pulse of 1500uS, then you turn the output off after 150 ticks.
The resulting signal looks like this (note that the angles will vary depending on the servo):
Most micros will have a PWM timer mode that can do all of this automatically. Take a look at the atmega 328p datasheet, section 16.9.3 "Fast PWM Mode":
The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x, and set at BOTTOM. In inverting Compare Output mode out put is set on compare match and cleared at BOTTOM.
BOTTOM according to the datasheet just means 0. ..I don't know why they don't just say that. So anyway, what you need to do is set TOP and the timer pre-scaler so that the period is 20ms. Then you need to set OCR1x, to an appropriate fraction of that to get your desired output pulse length. You'll want to use non-inverting compare mode.
Edit: Changed "OC1x" to "OCR1x" in this paragraph. That was a typo, sorry.
There are online calculators that can help you figure out the values for TOP, and the timer pre-scaler. |
H: i want to duplicate a signal generator output
I want to duplicate signal generator output to dual. since i want to use same signal to two different place. Is this possible without amplifying and inverting the signals. Let me share some circuit.
i just tried using two OP-AMP 741 and failed.
I have only basic knowledge in electronics.
Finally found working using below circuit...
AI: You should use 2 unity gain buffer parallel for this. You may find details about unity gain buffer in google.
output of signal generator will be connected to the input of each unity gain buffer input. output of each buffer will be same. |
H: Low power design, choosing correct buck-boost converter for LiPo battery
I want your opinion on subject considering low power applications. I want to build basic loraWan tracker with Murata Lora module(3V3), and I want to use LiPo battery. What Im struggling with is power design circuit. I want a dc/dc buck-boost converter which can work from very low voltage input(to use maximum from the battery) and very low power consumption.
For now Im considering this IC(other suggestions welcomed):
https://www.analog.com/media/en/technical-documentation/data-sheets/3106f.pdf
What do you think about it?
Sorry about my bad english.
AI: This converter will work but there are much less complex converters available if you dont need all the extras the IC you mentioned is offering. Its also depending on your converter output requirements or rather the input requirements of the circuitry you want to supply. Also there are ICs available with a much smaller footprint which i guess is a factor in a portable application. Consider for example BD70522GUL from rohm, which is more than 10 times smaller. Also Keep in mind that LiPo batteries are not very happy about getting discharged too low. |
H: Is there a 74HCT03 equivalent I can just replace "as is"
Is there a 74HCT03 equivalent I can just replace "as is"?
Of course, it will be better to buy the same exact chip reference but is it always the case?
Many chips are equivalents pin-to-pin, right? If so, (in limits of current & voltages of course)...is this possible in most cases or is this always a stupid idea?
Thanks.
AI: That completely depends on the circuitry. Both in terms of logic levels, signal delays, and transition speeds.
The 74HCTxxx logic family was precisely designed to be TTL-compatible high-speed CMOS. That is, fast and low-power like the 74HCxxx family but capable of accepting TTL-level outputs from the 74xxx and 74LSxxx families.
If the circuitry around it is 74HC or 74HCT, it is very likely that it can be substituted by a 74HC or faster component. If it is a different logic family, your mileage might vary. |
H: Trying to understand floating voltage
I'm trying to understand the concept of a floated voltage, and why it is needed in some cases.
For my own case, I am using a variac connected to a rectifier to provide a DC voltage for a circuit, (charging a large capacitor for discharge). The circuit needs a ground connection, but connecting a ground to complete the circuit also grounds the rectifier, which I am told will damage the rectifier.
(I do not fully understand why this is the case, and would like to find out more.)
But it was suggested to me to use an isolation transformer before the variac and to float the voltage, and in this way rectifier would be kept safe. I would like to know understand how this works.
(I am aware another option could be to add a switch and just disconnect the rectifier from the capacitor, but I am more interested in understand the above).
AI: Usually a raw AC power feed is grounded on the neutral wire and, if tapping off a voltage via a variac, you are "keeping" one wire tied to earth. This is because variacs do not isolate. Adding a bridge rectifier to the output isn't a problem but earthing the DC output of the bridge rectifier is because you end up with a diode that is from the "hot" feed (as opposed to the neutral feed) that gets blasted with a lot of current 50/60 times per second and destroys.
Just draw out the circuit and see. Use an isolating transformer for safety, peace of mind and protection for the diodes. |
H: Battery first time charging duration
Why does some manufacturer which I know using NiMH battery in their products recommends to charge the product for like 24 hours the first time you charge it, yet the seller usually tells to charge only 8-10 hours the first time you charge it. Which one should we follow? If we should charge it based on the sellers recommendation, then why did these manufacturers recommended to charge it 24 hours in the first place?
As side note the battery is usually around 1300-1500 mAh 2.4 V.
And There is no indicator whatsoever which tells how much charge is left on the battery. The charger itself is around 100 mA 3V (is this categorized as slow charging? ).
AI: I would ignore the seller's advise and follow the manufacturer's advise to charge for 24 hours when charging for the first time. The seller didn't design the product so how can they know better than the manufacturer?
What can happen is that after a long time in storage the NiMh cells lose their charge completely. NimH cells can handle that. After the full discharge NiMh cells can be "revived" by just charging them slowly. Many products always charge NiMh cells slowly because that is the cheapest, safest and easiest solution.
When the cells are fully depleted it might take some time for them to "recover" especially when charged slowly. That might be the reason to charge for 24 hours. That way the cells have a couple of hours to regain their nominal voltage and when they do there is still enough charging time to fully charge them.
Lithium based cells generally should not be fully discharged so they need a protection circuit to prevent that. Also Lithium based cells do need a proper charge controller, just trickle charging them continuously is not recommended as these cells cannot handle that very well.
So charge control and full-state detection as mentioned in a comment only applies to Lithium based cells, not NiMh cells. For NiMh cells charging can be done safely using a resistor and a diode at C/10. Charging then takes long but completely safe. |
H: What are the initial conditions used to find the coefficients in the current equations?
Suppose a RLC series circuit. R, L and C are in series with a battery and a switch. The switch is open. L and C are discharged.
At t=0, the switch is closed and the battery (V1) feeds the circuit.
I apply KVL to the circuit and find three equations:
CRITICALLY DAMPED
\$ V_C(t) = (At + B) \thinspace e^{-\alpha t} \$
OVERDAMPED
\$ V_C(t) = Ae^{m_1t} + Be^{m_2t} \$
UNDERDAMPED
\$ V_C(t) = e^{- \alpha t}[K_1 \thinspace Cos(\omega_d t) + K_2 \thinspace
Sin(\omega_d t) ] \$
To find the coefficients of those equations I apply the two initial conditions:
I solve the equations for t=0 and for the initial voltage across the capacitor.
I take the derivative of the equation and solve for t=0.
Now lets talk about the current equations.
I never understood why but apparently the current equations are the same, or
CRITICALLY DAMPED
\$ i(t) = (At + B) \thinspace e^{-\alpha t} \$
OVERDAMPED
\$ i(t) = Ae^{m_1t} + Be^{m_2t} \$
UNDERDAMPED
\$ i(t) = e^{- \alpha t}[K_1 \thinspace Cos(\omega_d t) + K_2 \thinspace
Sin(\omega_d t) ] \$
What are the two conditions I must use for the current equations to find the coefficients?
In the voltage equations I used the initial voltage across the capacitor and the derivative of voltage (current).
Now I have the current equations.
One condition must be to solve the equations for t=0, but what about the second condition? How do I find the coefficients of the current equations?
AI: For a series RLC network, think about what the circuit looks like at DC steady state. After the switch closes, current will start to flow through all the components. However, eventually the capacitor will charge fully.
At this point, what does the capacitor look like? What does this say about the current in the circuit? How do these descriptions relate to your initial and final conditions? |
H: Inverting, single-supply comparator not working as expected
I am trying to convert an input sine wave to a square wave. The sine wave is centered at 2.5V and has an amplitude of 2V, with a frequency of 100kHz.
I am looking for a hysteresis of 100mV centered around 2.5V. (ie. 50mV below and 50mV above 2.5V)
I am trying to achieve something like the following (except that the output is inverted), where both waves are centered about 2.5V:
To do so I looked through Design with Operational Amplifiers and Analog ICs, and I thought that I could work with a VTC offsetting single-supply inverting Schmitt trigger.
I then calculated the resistance values according to my parameters.
VTH = 2.55V
VTL = 2.45V
VCC = 5V
Assuming R3 = 100kΩ and R4 = 2.2kΩ, I calculated R1 and R2 both being 4.1kΩ`.
I proceeded to construct the circuitry on Proteus software using the LM311 comparator.
And here is my output.
Yellow is Channel A, Blue is Channel B.
I zoomed in on the square wave can be seen from the dials.
The output is not only attenuated, but also unevenly centered. The book mentions none of these effects, so I suspect that I am missing something more fundamental here. Any suggestions on what I am doing wrong would be appreciated.
AI: You've tied the collector of the NPN output to ground and you are trying to take an output from the emitter - you have this the wrong way round. Tie emitter to ground and use a pull-up on the collector like most folk (who still use this ancient part): - |
H: How does Wi-Fi deal with multiple frames received at once?
Right now I'm trying to establish a network of 30+ transceivers with NRF24L01 modules - one of them acting as central. However there are big problems, whenever two or more nodes try to send data to one node.
As far as I know, WiFi devices are able to receive multiple frames at once with no problems. How is this possible? Are they listening on multiple (like 100) channels at once? And when there are two frames received in the same moment on one channel are there errors just like with NRF24l01 network?
AI: Talking about IEEE 802.11 a/g/n/ac… here.
As far as I know, WiFi devices are able to receive multiple frames at once with no problems.
That's wrong.
WiFi isn't designed to allow working with collisions. It has systems in place to avoid these.
So, a single WiFi device can only receive a single frame at once. It might be that complex devices were designed to work on multiple separate WiFi channels at once, but that's definitely not the norm, and it's actually like multiple devices doing multiple independent things at once; the frames don't collide.
How is this possible?
Aside from the system being neither specified nor designed to allow that:
Since a collision of two frames means that the preamble of the second one would be heavily damaged, I doubt it's overly possible practically.
Principally, even systems that weren't designed to allow collisions (those would typically be CDMA systems) can achieve reception of overlaying frames if the signal strength of one is significantly better than the other:
In that case, the receiver might be able to actually correctly receive one, recreate the "unininterrupted" signal as it would have sounded to itself, subtract that from the receive signal (that it has magically saved somewhere), and then receive the next weaker one. We call that technique Successive Interference Cancellation; again, as far as I know, that's not a part of any WiFi standard.
Also, MIMO/beamforming techniques can be used to "detangle" signals arriving from different partners/paths at the receiver, but that is a whole different kind of business. |
H: Will an AC series motor work with DC supply?
I have read that a DC series motor can be operated using AC supply, but there will be excessive heating in the core and yoke and also a low power factor. So, construction is modified to have laminated core and yoke to reduce eddy current losses (heating) and also compensating winding and inter-pole windings to keep the torque same while reducing the turns of the field winding (to improve power factor (but reducing torque)). This is an AC series motor.
My question is, whether this AC series motor will run on DC supply or not?
I am also aware of universal motors, but they seem to be very similar to these AC series motors.
AI: The AC series motor you describe is a universal motor, and will work fine on DC. The speed characteristics will be a little different, since when running on AC there's a significant reactive drop in the field windings that reduces the available driving emf.
Difference between AC series and universal motor -
With the field winding in series with the armature current the motor is insensitive to the direction of current, so once you have the necessary laminations to keep losses down when running on AC the motor becomes universal. Small DC series motors - though there aren't a lot of these, most have permanent magnet fields - are often made with laminated fields, since it's a cost-effective way of achieving the geometry. With bigger DC series motors, the field yoke and pole pieces are often solid steel pieces, forgings, extrusions or PM parts. |
H: How to find max load limit in datasheet?
I have а datasheet but I don't understand: how to find max load limit in datasheet?
Can I use this SSR to switch the load (12V DC), and what current can I count on?
Thanks.
AI: The maximum current through the output is listed in the datasheet:
So do not exceed 150 mA.
But how can I get the maximum current for this temperature range?
You can't. And you should not. Designing something so close to the edge is asking for trouble. What you need is margin, that means that you stay far away from that maximum current. So instead of going up to 150 mA or 120 mA (for 85 C) you should not exceed 50 mA. Yes, that's a large margin.
But that should not be an issue if your load consumes less than 50 mA. If you have a load that needs more then don't use this switch to directly switch that load. Instead, use a relay of transistor to do the actual switching of the load. Relays for 12 V 50 mA can easily be found. Often such a relay can switch 2 A or more at 12 V or more. Problem solved. |
H: MOSFET driver circuit configuration for half bridge MOSFETs for power amplifier
I am making a class D audio amplifier and I am using a MOSFET driver to control two MOSFETs in a half bridge configuration as shown in the circuit below
When I connected the circuit without the MOSFET half-bridge, I grounded Vs and I got a neat output according to my needs 15 V peak at HO & LO, The problems started when I connected the MOSFETs, The HO & LO terminals started sending out the same signal but with a max voltage of 3 V or probably less, then the circuit drew around 1 AMP from my voltage source and burned the MOSFET driver chip, I knew for sure that it was burned because the resistance between the VDD terminal and the COM terminal was 26 Ohms instead of the high resistance a new chip had. An engineer in my uni suggested that the problem might be caused because I was providing the 15 volts to the MOSFETs from the same node that supplies the same voltage 15 V to my entire circuit, although my circuit was drawing only 40 milliamps from the power supply before connecting the MOSFETs.
I would like to note that the chip is FAN7390. I have fried two so far. I would guess that the common power supply might be the problem?, or it might be that the switching frequency of 125kHz the problem? The Hin and Lin signals are PWM signals with 15 V peak.
AI: Several things wrong with that design!
Where is the decoupling? That 15V line needs a whole pile of cap on it....
C4???! 22uF for a boost cap, just insane, get rid of it, the 220n should be fine on its own.
R13/14 1k, try more like 100k.
Those mosfets, 140nC maximum gate charge?! Yea they are very, very butch fets, but you really want something much smaller and with a very much lower Qg.
Layout? It really, really matters.
Not the cause of the blowup, but R11/12 seem very high in value, especially given the Qg of those mosfets. |
H: kicad: LM1117 can't choose Power output line
I have an LM1117 regulator and I have this problem:
When I "Perform electrical rules check" I have this error:
ErrType(5): Conflict problem between pins. Severity error.
- @ (224,79 mm,92.71 mm): Pin 4 (Power output) of component U1 is connected to
- @ (224,79 mm,92.71 mm): Pin 4 (Power output) of component U1 (net 1)
Well I can see an 2 and 4 numbers in the VO, I click here and I have a list to choose values:
- Clarify selection
- Component LM1117-3.3, U1
- Pin 2, Power output, Line
- Pin 4, Power output, Line
Whatever I choose it doesn't work.
AI: Please update your component library
This was taken by kicad-5
[ebuild R ] sci-electronics/kicad-5.0.0-r1::gentoo
What you have is an illegal part. It has two pins on top of each other and when you try to connect it is unable to resolve which one. The LM1117-3v3 is a 3pin part and it is therefore questionable what the 4th is.
If it is a part that has a 4th pin associated with the exposed substrate for improved cooling then the symbol would clearly show the pin. |
H: How Does Line Frequency Affect Coils of a Contactor?
I am using a generator as my source voltage, which produces 240VAC @ 240Hz. I was planning to use the following contactor from TE: CONTACTOR 4PST 40A 240V
In the datasheet it says this contactor's coil's activating voltage needs to be 50/60Hz. Now what happens if I feed 240VAC @ 240Hz to the activating coil?
I have asked the same question from DigiKey and TE support people, and they just said it won't work; but they did not explain WHY it won't work. So, I was hoping if someone could explain it to me why it won't work.
Thanks
AI: An AC coil presents a specific impedance at a specific frequency.
\begin{equation}
X = 2\pi fL
\end{equation}
Where:
L = coil inductance in Henrys
f = frequency
X = impedance
Your contactor's coil is specified at 50-60Hz. If you instead use 240Hz, then the impedance will be higher, and not enough current will flow through the coil to activate it.
X above can be substituted as R in Ohms law V=IR => V=IX to show how much current will flow. |
H: Explanation of 3 Tone Control Circuit
I'm building an analog drum machine and want to have a 3 tone control circuit to individually adjust the bass, midtones, and treble frequencies on each of my instrument channels.
I thought it would be fairly simple to find a circuit that I could modify to my liking, but it's proving to be more difficult than I thought. I found this Three-Band Active Tone Control circuit using the OPAx22x Low Noise Operational Amplifier from Texas Instruments (Page 26 of Datasheet)
This is exactly what I'm looking for, except no design equations are given and no description of how the circuit works is provided. I really want to understand how this circuit works intuitively/mathematically and would greatly appreciate any explanations and equations.
AI: I'm not going to try and give you a full treatise but give you a high-level overview.
simulate this circuit – Schematic created using CircuitLab
Figure 1. A simplified variable gain inverting amplifier.
The gain of Figure 1a is \$ - \frac {R_f}{R_i} \$. Figure 1b allows adjustment of the gain by adjusting the pot. The gain increases as the wiper moves towards the IN. In practice a fixed value resistor would be added at each end of the pot to set minimum and maximum gains and present "silly" gain values being set by the pot at either end.
It should be fairly obvious to see that your circuit consists of three such circuits around one op-amp. What may not be so obvious is that the inverting op-amp's inverting terminal is a virtual earth (ground) for the audio signal due to the feedback and the configuration makes it a summing amplifier. The main trick of the circuit now is to feed in the three bands of interest to be summed.
We'll use a slightly different schematic for the discussion for reasons that will be made clear.
Figure 2. A better circuit? Source: Interface Bus.
Looking at the treble circuit we see that the signal to the summing point is
fed through a 5 nF capacitor. The capacitor will block low frequencies and pass high frequencies so this part of the circuit will only affect the treble.
Looking at the bass we see that there is a high frequency bypass on the pot so there is no high-frequency potential difference across it and so it will only affect bass frequencies.
The mid-range is a combination of the bass and treble and forms a band-pass filter for the mid-range.
Now spot the difference: your circuit has no bypass capacitor on the bass control. I suspect that the result would be that the bass control would work as a volume control only and that to boost the bass one would have to turn the "bass" control up and turn the other two down. This may be rather unsatisfactory as there may be a "hump" in between the middle and treble ranges.
I really want to understand how this circuit works intuitively/mathematically ...
I've never done the maths for this so you'll have to do some digging. If you analyse the circuit one band at a time (and removing the other two) you may be able to figure out the equations yourself. |
H: Why is it that true random number generators are not in every computer?
I understand that one of the fundamental pillars of the programmable computer, is that we should implement features with software rather than hardware, anytime it is possible & more efficient (or less efficient but to a degree that we can deal with); but I believe that random number generating should be an exception. There are many things that, in theory, are undermined by PRNGs (e.g., in 1949, Claude Shannon proved that any "unbreakable" encryption method must utilize TRNGs for key generation).
For some reason people like to say that TRNGs have longer generation times (https://www.random.org/randomness/) but that is wrong! Some TRNG architectures are only limited by sampling rate & the speed of their ADC (if they are still too slow then you can just run them in parallel). PRNGs are slower because they require computation steps. With TRNGs the "computation" is performed by the environment (at roughly the speed of light). The only thing PRNGs have going for them is that they are inherently more power efficient than TRNGs...
So my questions is, why did TRNG circuits never find their place in the standard computer architecture? From my perspective, every modern day computer should have a TRNG circuit & they should be used in place of PRNGs in most situations.
AI: A random number generator has to output random numbers that are uniformly distributed. The possibility must be exact for all possible numbers. That constaintis very difficult to obtain with kind of noise generator circuit, however it is possible to make this with computation aka PRNG - pseudo random number generator.
PRNG is used for all gaming machines, because it has to have a statistic log that prooves that hit numbers are uniformly distributed. Another bad thing with white noise generator is that is susceptible to the environment noise, it would be very easy to jam a slot machine with some external device. |
H: How much current will this LED draw?
Sorry if this is a really basic question - software engineer here, so I'm a little out of my element.
I'm working on an IoT project, and I'm planning on using this button with a red LED inside of it.
For most of their products, this manufacturer lists how much current their stuff draws. However, in this case, they don't. The information they give is:
The forward voltage of the LED is about 2.2V so connect a 220 to 1000 ohm
resistor in series just as you would with any other LED to your 3V or higher
power supply.
I'm planning on powering it using a 2N2222 transistor connected to the 5V rail on a Raspberry Pi.
I would have naively tried simple Ohm's law, but I know that can't be correct here.
EDIT: I did a little digging through some old textbooks.
Since I'm powering it from the 5V rail, $$V = 5V = 2.2V_{LED} + V_{RESISTOR}$$
So,
$$V_{Resistor} = 2.8 V$$
Which, from Ohm's law, then gives:
$$ I_{Resistor}=I_{LED}={2.8V\over1000\Omega}=2.8mA$$
Are my calculations/reasoning correct?
AI: At 5V you have V = I*R equivalent to (5V-2.2V) = I * R(from 220 to 1000 ohm).
The 2.2V varies slightly based on the source voltage but in this case it's safe to approximate that your current would be between 2.8V/220ohm=12mA and 2.8V/1000ohm=2.8mA
2.8mA should be a decent amount for any red LED you're playing with. Blue LEDs can be a lot brighter at the same current so just keep that in mind before you solder anything because there are tons of examples of blue LEDs that are way too bright because somebody expects the same luminance curve.
The 220 ohm resistor would be appropriate if you were running at 3V (would give you ~3.6mA) but at 5V you would have 12mA through the LED which would almost certainly get it way brighter and hotter than you need it to be. |
H: STM32F407 discovery board jumpers
What is the usage of Jumper1(JP1), Jumper2(JP2) and Jumper3(JP3) on the STM32F407 discovery board?
AI: The manual is pretty clear — JP1 is for measuring the current consumed by the board. It's even labeled "Idd" in the silkscreen.
JP2 and JP3 on the back are just extra ground connections (for scope probes, etc.). You can see them in the schematic diagram. |
H: Can I use the external trigger to simultaneous capture waveforms on two oscilloscopes?
I want to look at synchronization in a 6 oscillator network (oscillators are about 100 kHz, 1.5 V_pp, if this matters). I have a 4 channel oscilloscope (Tektronix TDS 2024B) and a 2 channel oscilloscope (Tektronix TDS 1001B). Can I use a signal generator as an input to the External Trigger of both oscilloscopes so that I can perform a screen capture at the same time on both scopes? I was imagining that I could input a triangle wave and capture at the peak, or something like this.
I am just learning electronics (chemical engineer/applied mathematics background), so if the answer is yes, please keep in mind that my curiosity is great but my knowledge is shallow.
AI: From this document: "Most Tektronix oscilloscopes also provide a discrete output that delivers the trigger signal to another instrument—a counter, signal source, or the like."
It's probably on the back of the scope, and you may need to read the manual to get it working right.
If you were operating at 100MHz I'd also caution you that there's probably some timing skew -- but unless the oscillators have much sharper rise times than their frequencies and you're comparing nanoseconds of difference, then you're probably OK. If you do need to resolve things that fine, get everything working and swap inputs between the two scopes to see how much they change timing. Ideally you'll be able to calibrate for any timing offsets. |
H: Calculate input impedance of this circuit
I'm not too sure about this. It says neglecting all other capacitances so then surely the Cgs capactior is zero and thus that connection from the gate to between the two caps is relevant. So isn't the input impedance just the series combination of C1 and C2:
$$Z_{in}=\frac{(\frac{1}{jwC_1})(\frac{1}{jwC_2})}{\frac{1}{jwC_1} + \frac{1}{jwC_2}}$$
I feel like I'm missing something very important.
AI: This looks like an inverting opamp circuit, with enough gain to sustain the GATE voltage changes at near ZERO voltage.
Thus the gate barely moves.
Input capacitance is just the first capacitor.
This assumes the FET is somehow biased ON, with Vdrain sitting near VDD/2 for best signal swing. |
H: Difference between low signal and no signal for a SR latch?
I am struggling to understand how the SR latch works.
When an input has designation 0, this means "low signal" correct? Is this completely different than "no signal"? Doesn't a logic gate need some kind of signal in both input wires in order to produce an output signal?
If so I don't understand how an SR latch can ever product any kind of output. Even if we sent signal in through S and R at the exact same time, neither gate can produce an output until the other input on each gate receives a signal, but both gates rely on each other for those inputs, so...?
At the same time it can't be "no signal" either because this would imply the NOR gates could send a signal even when no power is being sent through.
Where is my understanding wrong?
AI: When an input has designation 0, this means "low signal" correct?
Uh, usually. Sometimes people will work with "negative true" or "active low" logic, which doesn't change the parts, it only changes the meaning of the voltages.
Is this completely different than "no signal"?
Yes and no. When you're talking boolean logic there's only two possible states. When you're talking electronics, the "gates" act like high-gain amplifiers.
Doesn't a logic gate need some kind of signal in both input wires in order to produce an output signal?
Uh -- beep, does not compute. See above. There's always a "signal".
If so I don't understand how an SR latch can ever product any kind of output. Even if we sent signal in through S and R at the exact same time, neither one can produce an output until the other input receives a signal, but they both rely on each other for this.
Look at the logic elements as if they're circuit elements. When you turn on the power, the latch is in some unknown state, or it may even be in a real live indeterminate state, with both outputs stuck in between low and high. Now think of those two NOR gates as amplifiers with negative gains of amplitude more than one. If one of those outputs is just a bit above center, it'll cause the other output to drive down, which will drive the one output even higher, and the latch will quickly settle into one state or another.
(A similar thing happens if you tie the S and R inputs together and toggle them simultaneously -- with both inputs high, the outputs are held low, but it's like balancing a penny on a needlepoint. As soon as the inputs go low the outputs will fight briefly, then the latch will go to one state or another).
At the same time it can't be "no signal" either because this would imply the NOR gates could send a signal even when no power is being sent through.
There is no question mark here, but I think you're unclear on the concept of power vs. the concept of signal. In the real world, the gates would be powered; in the theoretical world, the gates just magically act the way they do, without requiring power.
Where is my understanding wrong?
I'm not sure. But I hope that I've clarified things. |
H: Why is there a minimum input resistance?
I was looking at this multimeter, and it says,
Output rate: 0.1 V/A (use with a device having a 1 M-ohm input resistance or higher)
Where can I read why this minimum resistance is required? Alternatively, what would happen if my voltmeter has smaller resistance?
AI: You can read it here:
It's not a multimeter, it's a current probe.
You connect it to a multimeter in order to see its output voltage, which is a measure of the current that you are measuring with the probe.
So as the output voltage rises with \$ 0.1 \, V \$ for every Ampere (\$ A \$) it measures, it also has an output impedance which causes the voltage to decrease if you draw a current from the output.
That's why they advise you to take a multimeter with an input impedance of at least \$ 1 \, M\Omega \$. |
H: Vias not connected to ground plane
I recently designed my first 2 PCBs. Both have a 5v copper plane on the top layer and a ground plane on the bottom layer. I use short traces and vias to connect top components to the ground plane.
As you can see in my image, the bottom PCB was manufactured as expected. The top PCB was not. The vias in the top PCB have rings around them where there is no copper (thermal relief?) which means nothing connects to ground and my board does not work.
I designed these using EasyEDA and have viewed them in Eagle. I don't see any difference in my two designs, even though they came out differently.
Is there a term for the vias seen in my top board ( the ones that don't connect)? I obviously need to order these again, but I'm not 100% sure I won't get the same faulty vias.
AI: What probably happened is that you forgot to assign the GND net to the plane. Thus the software saw it as different nets and did not connect the vias.
Software has the nasty habit of doing what you tell it to do, not what you really want or intend. |
H: Which suppresor device will be use for 2pole AC contactor 240v coil voltage in coil as well as contact side?
I need an AC contactor for a 1 hp motor. For the contactor safety I'm goint to use the suppression device on the both coil and contact side. Please suggest me which suppressor device will be use!
I have read all question and answer about suppressor for contactor from your forum, that was a good understandable.
Which would have a good suppresor nature for both side (contact & coil) like diodes, RC snubber or Varistor Coil Suppressor?
If Yes of these once (diodes, RC snubber or Varistor Coil Suppressor), please explain why?
My desired AC contactor details are given below:
Coil voltage :240v
Pole :2
Contact type :DPST
Any suggestions would be greatly appreciated?
Kindly clear and explain above question, share your suggestion.
AI: There are cons and pros for each type of suppressor. Since you use the AC then the diode as well zener+diode are excluded. You can choose between RC snubber and MOV. Usually the MOV suppresors are embedded into a contactor itself, you need just to order the correct one. RC snubber is more bulky and has to be mounted as add-on.
You can find details on: Simatic contactor
Using RC snubber on contacts, will produce a leakage current trough. A device connected to the contactor will always have some voltage, also the electric tester will show you a voltage presence even when contactor is disengaged. Usually you won't find any real application with suppressor mounted on switching side, it is done only for high inductive loads. |
H: Is this an artifact of DDS technique?
When I sample a sine wave output of a DDS based bench function generator I have noticed there is always harmonics of the fundamental frequency. For example, below is the function generator's output set for 2Hz 1Vrms sine wave in time series and this is sampled by a 16-bit single ended DAQ at 1kHz sampling rate:
And here is the FFT spectrum of the above stored signal.
Then I went to a DDS chip's datasheet and observed this type of harmonics in some of the plots. I'm not sure whether these two are related but here below from page 9, one of such spectrum:
What could be said about these observations about the harmonics? Is that because DAC part of the DDS? Or can that be a totally unrelated cause?
AI: What could be said about these observations about the harmonics?
Let's get this into perspective; the 2 Hz fundamental has an amplitude that is about 60 dB greater than the 2nd harmonic at 4 Hz. In real numbers 60 dB is a ratio of 1000:1 or 0.1%. This is not really that significant and given that the output of a DAC has an integral non-linearity error that can be several LSb it doesn't surprise me at all.
Above 6 Hz the spectrum is getting muddier but you are down in the real basement of the signal and DDS will produce artefacts at this very small level. |
H: Voltage across LED and source when LED is floating from one end
Refer to these pictures and can you explain why is there 3.335V coming across LED and the LED isn't even turning on. Also to note is that changing the resistor value does not change voltage at D2(A2) when switch is open. (I am using the D2(A2) point as an input for a microcontroller).
(This is also the same voltage coming in my real life circuit)
Addition!!!
Extra Points:
Also is it safe to use the point D2(A2) as input to a micro-controller (PIC18F46K22) with it being brought to 0V when SW1 is closed and being brought to high logic level when the SW1 is open.
AI: You have the answer there in the properties page. The drive current is 10mA. With your 10k resistor, how much current do you think is going through the LED?
The forward voltage of the LED is (almost) constant (is does vary with current/temperature slightly), so changing the resistor value won't change the voltage over the LED. What it will do, is change the current going through it.
Your properties page shows a 2.2V drop over the LED. You have a source voltage of 5V. To find the current through the LED, use the formula: Iled = Vs-Vled/R
Using this, you can see the current going through your LED is: (5-2.2)/10000 = 280uA which is nowhere near enough to turn it on.
Try changing your resistor to something like 220 or 330 ohms and you will see it turn on.
Here is your circuit as you have it set up (using the exact same components):
Look at the current. Not enough to light it up.
Here it is with the resistor changed:
LED on.
EDIT
It was pointed out by brhans that I may have misread the question. If you are wondering why the voltage you are measuring is not the 2.2V you are expecting, it is because you are not measuring across the LED. You are actually measuring the voltage across the switch. This means anything you change above it will not affect the voltage across it, as the switch is constant. If you want to measure the voltage over the LED, then you need to move your probe above it. With the switch open, it will be near enough 5V, and the bottom probe will be the voltage you are measuring, which is the diode drop with zero current flowing. Close the switch and you will see the voltage changes. To show you what I mean:
This shows the expected results. Close the switch and you will see the numbers change:
Note that the switch has an open resistance of 100Mohms. As andy aka points out, this will account for the voltage level you see. |
H: ULN2003 Saturation Voltage help
I'm busy designed a PCB that will use a Raspberry Pi's GPIOs to to drive several optoisolators. Additionally I'm also interfacing with an IO module that works with HIGH > 1V.
Because of the number of optoisolators I'm using I don't want to overload the Pi's GPIO's and planned on using a ULN2003 to do the heavy lifting and drive the opto's.
Additionally, I would like to use the inverted output of the ULN2003 to drive the aforementioned IO module. My knowledge is mostly in digital systems, so the only place I have used the ULN2003 before was to drive some LEDs from GPIOs.
[Keep in mind, my knowledge is mostly digital systems, and the occasional n-channel mosfet, which in my mind is also "digital". I have virtually zero knowledge of transistors.]
Now I'm struggling to understand the 1.0V approximate "collector-emiter saturation voltage". I thought that there would be a close-to-zero ohm resistance between the OUT pin and GND of the ULN when the IN pin is high. But now I read on a guide:
Keep in mind that you will have a voltage drop of about 0.9v-1.0v over
the UL2003 when in circuit.
I'm a little bit lost here. I've drawn up a schematic to help. All GND's are common.
Does this saturation voltage mean that XMM1 will measure about 1V when the input is high? Multisim doesn't want to simulate the ULN.
I found a Toshiba component that looks identical to the ULN2003 but uses DMOS (I assume this is closer to N-channel mosfets, which I'm more familiar with). The Toshiba TBD62003 (datasheet) which is also slightly cheaper than the ULN2003.
Can anyone tell me if it can be used as a drop in replacement for
the ULN2003 in the schematic above. (Just hook up the GND pin,
load's negative side connected to OUT1 and GPIO drives IN1)? By the
looks "equivalent circuit" it uses a n-type mosfet?
EDIT: I found a very useful application note by Toshiba which shows that is pretty much a drop-in replacement.
AI: While Michael Karas' answer is correct, it does not simply answer your questions, so I will.
Does this saturation voltage mean that XMM1 will measure about 1V when the input is high? Multisim doesn't want to simulate the ULN.
That's exactly correct. The saturation voltage is simply the voltage across the output when it is fully turned on. You'll notice that it increases with increasing load current.
I found a Toshiba component that looks identical to the ULN2003 but uses DMOS (I assume this is closer to N-channel mosfets, which I'm
more familiar with). The Toshiba TBD62003 (datasheet) which is also
slightly cheaper than the ULN2003. Can anyone tell me if it can be
used as a drop in replacement for the ULN2003 in the schematic above.
(Just hook up the GND pin, load's negative side connected to OUT1 and
GPIO drives IN1)?
Again, you're correct. And you'll find that the saturation voltage for the Toshiba part is generally lower than for the ULN, at least for lower currents, like 100 mA. This will let the part run cooler. At higher currents, about 350 mA, the two are comparable in voltage drop. |
H: Rising Edge-Triggered Truth Tables
I'm trying to debug some issues in an old (early-90's is old now, isn't it?) circuit, and noticed something in at least two different chip's truth-tables, and thought I'd ask here..
In the 74LS74 (Positive Edge-Triggered Flip-Flop) and the 74LS374 (Edge-Triggered Latch) datasheets, there are truth tables, showing in summary how data inputs are latched to output when the CLK input rises.
The truth-table then shows the status of the outputs when the CLK is driven low.
However, looking at this old design, it looks like the original designers are holding the CLK high; not low. There's nothing in the truth-table and no mention (that I've found) in the datasheets about what to expect when the CLK is held high. (Is it safe to assume, since it's NOT a rising edge, the outputs are already latched and will hold, just like if the CLK was low?
Edit to add, per comment: I was looking at copies of the TI sheets for both the chips above. ONE of the chips I got another vendor's sheet - and realized it was just a word-for-word copy of the Ti sheet I had, formatted differently.
AI: Using the TI datasheet sdls119.pdf description section (sheet 1) and schematic analysis on sheet 3, if the clock is high or low the D input is ignored.
BTW the TI datasheet is the only one so far that I've found that doesn't explicitly mention this, old Motorola and Fairchild datasheets specifically say once the clock is high or low the outputs are frozen.
If outputs follow a static "clock" signal then it's referred to as a transparent latch. |
H: Base current and Vce relation in NPN transistor output characteristics
Regarding the active region of an NPN transistor and output curves, for a fixed Ib when the Vce is increased the Ic increases; namely Early effect.
The reason if Im not mistaken is that the increase in Vce makes the base thinner.
How can we logically derive the rest from here?
Here is what I assume when I look at the output characteristics:
Vce increases--> Base gets thinner ---> The recombination in the base happens less
hence Ib tends to decrease---> To keep the Ib same Vbe is
increased-->Ic increases because it is directly a function of Vbe
But there is a part in my logical arguments which is: "The recombination in the base happens less hence Ib tends to decrease".
But the base current is not only occurring because of the recombination but also because of the holes in base diffusing into the emitter. And to me if the base gets thinner the diffusion should be easier and Ib tends to increase.
So my confusion is when the Vce is increased Ib tends both to decrease and increase. That then invalidates my logic.
Where am I wrong?
AI: The depletion region inside base widens with increasing collector voltage. Because of this, the neutral base width reduces. This leads to reduced base recombination current (\$I_{Br}\$). Now Let us think what happens to collector current and base current.
Since the electrons (majority carriers) injected from emitter experience less recombination in the base, the collector current increases.
Since recombination current is reducing, the back injection of holes (minority carriers) from base to emitter will increase to maintain the base current fixed. This slightly increases the base-emitter voltage.
I think you have slightly mixed up the above two points. |
H: How to reduce noise in SMPS (Switching mode power supply) circuit
I am just using a reference design of SMPS (from Microchip) to boost input voltage from 12V to 90V as the image below:
It's working normally but the problem is the noise at the output of 90V.
I measured the amplitude Vpeak-peak of noise around 150mV and the repetition frequency is 110kHz = switching frequency of HV9110 controller.
My question is how can I reduce this noise to 20mV because it will affect on my signal analysis.
Please help me and thanks in advance!!!
AI: For the Boost convertor like other convertor you have output ripple and EMI.
For output ripple reduction the best way is adding a good CLC filter.
Increasing the value of C12 and C16 could have direct effect on your output ripple.
For the EMI reduction adding an Snubber RC circuit over the D8 diode or from its anode to ground is also a good practice. Reducing the switching speed of M3 also has direct effect on the generated EMI.
Please look at the following document:
http://www.westmichigan-emc.org/archive/SMPS_Teune_Mee.pdf
Texas Instrument document "slva790" is also a good guide for EMI reduction. |
H: Can I charge each Lithium ion battery, that are connected in series, with individual charger?
I don't know if I can do this and just want to make sure that it can work before I actually test it so that I don't have to worry about blowing my room up... The batteries have the same capacity so there won't be over discharge or charge on each battery (I will connect a battery protection on the ends of the series). The charger that I used is TP4056. The batteries that I use are actually 18650s but I accidentally wrote LiPo in the schematic.
simulate this circuit – Schematic created using CircuitLab
AI: This would work with a charger where the output is isolated from the input, but the one you link to is not isolated so definitely no.
I found this diagram here which shows the issue, the low side is common through the module, so connecting as you show will short out the right two cells.
What you would need is a dc-dc switching converter with a dual wound inductor that lets the secondary side float, but I don't see one readily available, there are modules for 120V input that have this arrangement, since isolation from the mains is obviously important.
A better aproach is to get a single regulator module for the whole chain, which also has charge balancing between the cells to ensure that one doesn't get over- or undercharged. |
H: Can a relay be used to power a 3.3 V appliance?
I'm a programming student and I got into an Arduino class this semester. Here's some backstory behind this question:
I need to make a Bluetooth module switch modes from master to slave and back, but I found out that the module only switches modes by being unpowered then powered again (and doing some specific things). This means I would have to unpower it manually by unplugging its power, but that'd mean it wouldn't be completely automated, so it's a no-no.
Because of that, I'm considering using a relay to be able to power it down then back on again via code, and found some relays that can be controlled by supplying 3.3-5 V.
However, all relays I've seen state that they work on 30/110/220 V.
So, if I use 3.3/5 V to control the relay, and 5 V to power the module through the relay, will the circuit through the relay work?
AI: This could work. The voltage requirement you must meet is for the coil. The contacts are rated for the maximum voltage they can safely interrupt. You will start to run into problems with the contacts with very small voltages, but 3.3V is high enough for the vast majority of relays out there to not have a problem. |
H: Buffer with TL084CN and resistors
simulate this circuit – Schematic created using CircuitLab
There are two buffers made with the TL084CN, which is part of the conditioning of an LTS25-P transformer. Currently, I have put a 100ohm resistor in the non-inverting input, and the feedback is without the resistor.
Is it advisable to add a resistor in feedback? Will the reading be influenced if I do not?
AI: Summary: For your case and your sensor is not important. your 100ohm resistance is negligible.
when your input resistance (\$100\:\Omega\$) * Input Offset Current_max (\$20\:\text{nA}\$) in the worst case generate \$2\:\mu\text{V}\$ offset voltage, your opamp typical input offset is in range \$3\:\text{mV}\$. so it is not important!
Why we compensate the opamp:
opamp input is a symmetric architecture and if you change the symmetry this generates offset and gain temperature drift. the opamp input impedance is base on the substrate, for example for your case is \$10^{12}\:\Omega\$. when you put a resistance in the input, the quiescent current of the input pin generate offset voltage in input and difference of current in two sides generate different behavior in temperature.
When R compensation is important:
when input_resistance* Input_Offset_Current_max > Voffset or comparable.
When the source has a high built-in impedance
If you need a high gain system.
If drift in temperature is very important even \$1\:\mu\text{V}\$! |
H: Schematic Feedback
I am looking for design feedback regarding the following schematic.
The idea is very simple.
The Controller board pulls the relay coil terminal low on the relay board to activate the relay.The relay board is 6 feet away from the controller board.
Once the relay is activated the brushless pump turns on.
The 220uf caps on the 12v line is used to keep the voltage high enough momentarily to have the microcontroller save a value in EEPRom before shutting down.
Looking to hear your comments/feedback.
The relay contact generates a bit of contact noise upon closure. Attached is the scope shot taken across the relay Common contact as it forms contact with the pump 12v line.
Will the contact noise interfere with the microcontroller function at some point?
Thank you
AI: that should work ok.
one possible improvement would to separate the 330uF used before the 5V regulator from the 12V supply using a diode, this stops the the pump sdtart-up current from draining the capacitor, and reduces wear on the relay contacts.
simulate this circuit – Schematic created using CircuitLab |
H: NMOS - connect body to source or ground?
I've had some weird occurances in labs etc. (using Cadence) where sometimes we would be told to connect the body/bulk/substrate terminal of our NMOS devices to the most negative part of the circuit (ground) and sometimes we were told to connect the body/bulk/substrate terminal to the source?
Which is it and why? I can recall it did change my circuit simulation results too by a bit. Also, I have the same question for a PMOS (connect to Vdd(most positive part in circuit) or to source?)??
AI: Although in most situations (particularly in instructional settings) this is ignored, FETs are a four-terminal device. The substrate/body of the device acts as a second gate that influences the device behavior. In traditional material this is referred to as the body effect and there are equations to account for how it modifies other device parameters such as the threshold voltage, connecting the substrate to the source is the easiest way to get rid of these equations. In some non-traditional circuit designs this second gate is used to provide additional functionality. E.g., as a lower-gain input to increase the linear range of the circuitry.
In most applications this body terminal must be kept at a potential that guarantees that the drain-body and source-body diodes are kept reverse-biased so that the device can function as a FET. In most cases this can be guaranteed by connecting the body junction to the source, this creates a reverse-polarized drain-source diode. In some power applications, this diode is part of the circuit design and power-FETs include this diode characteristics as part of the available design parameters. In other power applications, such as battery-backup circuitry where reverse polarities are normal, the substrate is actually connected to the effective drain terminal of the FETs.
However, in most IC technologies the substrate itself is the body of the integrated FETs. P-doped wafers are used as a substrate over which NFETs are built. This means that there is only one substrate node for all of the NFETs in the the whole IC. The only way to ensure that the NFET diodes are kept reverse-polarized is to connect the substrate of the IC to the lowest potential in the whole circuit.
For PFETs (which reside in separate N-wells), and in technologies in which both N-wells and P-wells are available, the reason is more about better use of the available space. Connecting the substrate node of such FETs to a different potential, means that the wells have to be kept separated by relatively large distances (the related parasitic devices could destroy the IC otherwise) and that different well contact regions have to be provided. This is done for some designs, but it is better avoided for space efficiency and reliability. |
H: Can i use an AC 15A 250V / 30A 125V rocker in place of a 15A 125V / 10A 250V one?
Amazon sent me the wrong replacement switch so i am wondering if i can use it?
Original switch is AC 15A 125V / 10A 250V
new one is AC 15A 250V / 30A 125V
can i use it without damaging the appliance?
AI: Yes you can use it. The replacement is more capable than the part it is replacing. This is a good thing. |
H: How to know the size (W/L) for a circuit to source or sink a minimum of 4 times as much current as a minimum sized conventional inverter?
Consider the tri-state NAND below (i.e. if EN is high, output is NAND of A&B; if EN low, output is
floating. Assume EN and ~EN always track). Show work.
a) Label each transistor with a size which would allow the circuit to source or sink a minimum of 4
times as much current as a minimum sized conventional inverter through its output Y.
I dont know how to know how to get the sink or source, is there a formula for that? like if the size (W/L) = 2, then what is the current?, would size = 4 double the current of size 2?
AI: For a problem like this, you need to look at the worst case scenarios. For example, when sinking current, the three transistors from below the output Y, need to be on. In that case, there are 3 on resistances associated with the NMOS.
A conventional inverter looks like this:
Reference:
http://vlab.amrita.edu/index.php?sub=59&brch=165&sim=901&cnt=1
Say the W/L for the inverter NMOS is 'n'. As you can see, for a conventional inverter, you only have a single NMOS transistor pulling low the output whereas in your circuit, you have 3. So if the NMOS transistors have the same W/L (and are matched), you have 3 times as much on resistance in your circuit.
That is what you want to address. It turns out that the W/L ratio is inversely proportional to the on-resistance of the transistors. Something like:
$$R_{on} \propto \dfrac{1}{W/L} \tag1$$
Or equivalently
$$R_{on} \propto \dfrac{L}{W} \tag2$$
So by increasing the width, for a fixed length, you can reduce the on-resistance. You want the 3 transistors (NMOS) in the pulldown side, to combine in such a way that they have the 4 times less on-resistance than in the case in the inverter.
We said that the W/L ratio in the conventional inverter case was 'n', so you want your 3 NMOS to combine to this:
$$\dfrac{1}{4n}=\dfrac{1}{x}+ \dfrac{1}{x}+\dfrac{1}{x}$$
Where 'x' is the unknown W/L for the NMOS in the pulldown network. They add up because they are in series. With that, you find:
$$x=12\cdot n $$
So you need to size these 3 NMOS 12 times the size of the transistor used in the conventional inverter. This will allow for 4 times the current capability.
You can do the same thing for the pullup network composed of PMOS. In your circuit, however, the worst case sceneario happens when one of the top two transistors (the ones in parallel) are ON and the one with the complemented EN is ON too, so you have two on-resistances to worry about. Again in the conventional inverter you only have one.
Say that the W/L ratio for the PMOS in the conventional inverter is 'p'. Since you have two transistors on when sourcing current in the worst case you need to adjust their W/L ratio i such a way that:
$$\dfrac{1}{4p}=\dfrac{1}{y}+ \dfrac{1}{y} $$
Which results in:
$$y=8\cdot p $$
So you need to size the PMOS to have 8 times the W/L of the PMOS in the conventional inverter to achieve a current capability 4 times greater.
In general, when the transistors are in series, think of it as adding more length 'L' which according to equation (2), means that the on resistance will go up. To counteract that, you need to correspondingly add more width.
When the transistors are in parallel, you could think of it as adding more 'W', which results in lower on-resistance as per equation (2).
In your circuit when all three PMOS in the pullup circuit are ON, you could in fact source more than 4 times the current a conventional inverter would (because the two transistors in parallel combine for half on resistance), but you have to design for the worst case scenario, which happens when two of the transistors are ON in the pullup branch.
Hope it helps. |
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