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H: Why don't we use decoupling capacitors for open-drain outputs?
If an IC with open-drain outputs (and hence pull-up resistors) is used, we of course put decoupling capacitors on the IC supply, but why don't we also add decoupling capacitors between the power pin of each pull-up and ground?
When an output switches high, current will flow from the supply through the wiring inductance, and through the pull-up. A decoupling capacitor here would reduce/eliminate the effect of the wiring inductance, leading to much cleaner switching, especially at higher frequencies, as well as lesser noise conducted from the switching output to the rest of the circuit. Yet I have never seen a data sheet or application note even recommend this.
Is it because the decoupling capacitor for the IC will be enough to provide for the outputs too? If this is the case, when laying out a PCB, this would mean all pull-ups have to be placed as physically close as possible to the decoupling cap right?
AI: Generally with an open-drain output, we use a fairly weak pull-up. Somewhere betweeen 2k and 50k ohms. The stronger the pull-up (the lower the resistance value) the more power would be consumed when the output is held low.
This pull up also limits the current that can be drawn from the power supply by this pin, generally to less than 1 mA and often to less than 0.1 mA.
Since the amount of current being switched is fairly low, it's usually not not necessary to use a dedicated bypass capacitor for the pull-up resistor. |
H: How to fix ERC error for power pins
I'm working on a board in KiCad that is supplied with 12V regulated power which comes from a terminal block (1725753) and then it's routed to a DRV8871 DC motor driver's supply pin. Now the ERC flags this with "Error: Input Power pin not driven by any Output Power pins" because I'm not able to assign the terminal block that's hooked uup to the +12V rail as output. How do i best resolve that issue?
AI: Similar to: Why does kicad complain about a voltage source not being driven?
This is KiCad telling you that you have a pin that should be driven by a net that can supply power. An example is an op-amp V_DD pin is expected to be driven by a constant voltage source that can supply a reasonable amount of current. So if you hook up a regulator that have a pin with the "Output Power" type, the op-amp will be happy. If you just have a passive connection, you will get an ERC telling you that the power input is attached to a passive pin, and isn't driven adequately.
Excerpt from my own work:
See top left for where the PWR_FLAGs are. |
H: What are the tradeoffs between NPN vs PNP power transistors?
I'm working on a linear power supply design leveraging the uA723 regulator and I need power transistors to meet the current requirements (~2-3A). When looking looking through the regulators datasheet, they provide examples (see figures 4 and 5) for external NPN and PNP output transistors for achieving currents > 150mA limit of the IC.
Source of images: Texas Instruments - uA723 datasheet
My natural inclination is to go with a high side NPN transistor like in figure 4 but I've noticed this second high side PNP technique leveraged in other designs I've reviewed.
As I understand it, power PNPs are harder to manufacture resulting in less available options.... so why would I go with PNP over NPN? What am I missing?
AI: Without fully exploring the topic (which could go on forever), just some points to highlight:
An external-transistor regulator like '723 may have lower voltage drop with PNP. Notice, as long as base bias can be supplied, VO can be arbitrarily close to VIN (as close as VCE(sat), minus any current-sense resistance of course).
PNP also has voltage gain, and additional phase shift, so therefore incurs a stability penalty. A direct substitution (as shown here, but without knowing anything else about the feedback network) is likely to cause oscillation. Check stability and adjust compensation as needed.
Conversely, NPN emitter followers tend to be lenient on stability, and have good PSRR (ripple on VIN is isolated by the collector impedance (Early effect)).
PNPs aren't harder to manufacture, they're made inversely to NPNs -- starting with p- instead of n- substrate (collector), epitaxy/diffuse n/p base layer, diffuse p+/n+ emitter layer and (degenerately doped) ohmic contacts, done. They may be more difficult in IC process, where either the collector is hard-wired to the substrate, or additional isolation wells have to be manufactured. The additional process steps then cost more up-front (masks, production tuning) and per-part (more steps, somewhat lower yield).
PNPs perform slightly poorer than NPN, on the order of about 10% in terms of overall conduction parameters IIRC. They actually perform better in some respects, or can, such as hFE being a little bit higher, but overall figure-of-merit tends to favor NPN. Basically, nothing that's strong enough to matter here; regulators are a very modest application.
If you've been reading a lot from contemporary sources (contemporary of µA723 that is; it's ancient, and there is no reason or need to use it today, unless perhaps as a requirement for homework assignment or something), then it was true back then that the NPN process was most amenable to consumer production parts, and thus lateral PNP was the go-to method to create them, when they were required at all. (Lateral PNP have very poor hFE, so they aren't easy to use as output devices.)
Such contemporary books are still good information, by the way -- just beware whatever advice is either dependent on available devices (all they had back then were simple regulators and controllers like '723, op-amps like '741, etc.), and changes over time (linear regs give way to LDOs and SMPS nowadays), or based on assumptions that were relevant at the time (speaking of SMPS, a big one that comes to mind is "minimize stray inductance" -- with many devices today, it's fundamentally impossible to minimize it to the degree required by what that rule of thumb is actually trying to achieve, and stating that underlying purpose makes much more sense). We also have much better means of simulation and calculation now -- compare signal filter tables to from-scratch analytical and Monte Carlo simulation techniques, and, just, the broad availability of SPICE and other simulators (which have been reasonably available since the 90s, but if we're talking 723s here, we're probably talking books from the 70s, maybe even 60s?).
MOSFETs are a highly viable option these days, from CMOS regulators (integrated) to external-device types (few of the linear type, but they are out there..!). The negligible gate current can improve efficiency, the RDS(on) can improve saturation (dropout), and devices are available with wider SOA than BJTs -- but on that same note, beware that modern MOSFETs can be as prone to 2nd breakdown as BJTs can be, and always check the datasheet for DC SOA, for an application like this.
MOSFETs do suffer from a large difference between N- and P-channel types. In silicon, P-ch is about 2.5 times worse in terms of RDS(on) and capacitance; basically the ratio of electron to hole mobility in the channel. Thus, there's no meaningful complementary pairs in MOS, as there are for BJTs; typically a compromise is chosen, such as P-ch twice the width of the N-ch to get a modest 25% higher RDS(on) and only double the capacitance, for CMOS gates for example. "Complementary" duals are available for power switching application as well. For a linear regulator, again we aren't generally too concerned about this figure-of-merit, and either type is usable; the main downside is, for N-ch, we need a gate drive voltage higher than the output, which makes low-dropout design awkward. (There are, in fact, LDOs where a higher bias voltage can be applied; thus you can regulate, say, 3.3V down to 2.5V, with help from a 5V supply, but without incurring the penalty of dropping directly from 5V to 2.5V.)
Compensation is probably more difficult with MOS, as the capacitances, and transconductance, all vary strongly with voltage, especially at low voltages (near dropout). BJTs do vary strongly as well, but capacitance is more gradual, and transconductance only near VCE(sat). |
H: 6 to 0 count down timer
I'm making a 60 second timer. I already made the 1st digit in my previous question. I want it to start at 6 not 0, basically 6,5,4,3,2,1,0. I made the flipflop state table and followed the similar process I used in the first digit.
But when simulating it, it starts at 0,7,6.... I want it to start at 6. How can I do this?
Below are the table and schematic I made:
AI: When facing this question (and exactly how it is faced depends on whether you are building something physically with genuine parts or using a simulator), I simply use the power-up reset state as the initial state and select either the \$Q\$ or \$\overline{Q}\$ output, as appropriate.
(In some physical reality cases, you don't know the power-up state. In such cases, they will usually provide a CLR and/or SET pin. I'd attach a power-on reset circuit so that the FFs are held in either CLR or SET state while the power supply becomes stable, releasing that line only after the supply is known-stable.)
So, in this case, the JK FF powers up with \$Q=0\$ and \$\overline{Q}=1\$. Since you want the initial state to be \$6\$ this just means that you set things up so that your actual output is taken as \$\overline{Q_2}\:\overline{Q_1}\:Q_0\$.
So the states will be \$0\$, \$3\$, \$2\$, \$5\$, \$4\$, \$7\$, and \$6\$. And take \$\overline{Q_2}\$, \$\overline{Q_1}\$, and \$Q_0\$ as the counter output.
You have proven yourself being able to produce the rest, I believe. |
H: ESP32 VSPI/HSPI SPI channels only support 3 slave devices?
From what I understand there are two methods for multi-subnode SPI - Regular Method and Daisy Chain Mode [1]. In the regular method, each slave device is designated a separate CS (chip select) pin on the master device which is driven low when the master wants to communicate with the slave.
Since the CS pin behaves like a GPIO pin, I would think the number of devices on an ESP32's SPI bus would be limited by the number of GPIO pins available. However, according to the Espressif's documentation Overview of ESP32’s SPI peripherals:
SPI2 and SPI3 are general purpose SPI controllers, sometimes referred
to as HSPI and VSPI, respectively. They are open to users. SPI2 and
SPI3 have independent signal buses with the same respective names.
Each bus has three CS lines to drive up to three SPI slaves.
Is it not an option to put more than three slaves on the VSPI/HSPI bus by designating more GPIO as CS pins?
[1]: Introduction to SPI Interface.
AI: The ESP32 Technical Reference Manual has the following in the Overview of the SPI Controller section:
Controllers SPI2 and SPI3 can be configured as either a master or a slave.
When used as a master, each SPI controller can drive multiple CS signals (CS0~CS2) to activate multiple slaves.
I.e. the SPI peripheral can control up to three CS lines which matches the maximum number of SPI slaves mentioned in the question.
The description of the spics_io_num field in the spi_device_interface_config_t structure of the ESP32 SPI Master Driver has the following description which means the SPI driver can be told that a CS pin is not to be driven by the SPI peripheral:
CS GPIO pin for this device, or -1 if not used.
W.r.t. this part of the question:
Is it not an option to put more than three slaves on the VSPI/HSPI bus by designating more GPIO as CS pins?
From looking at the ESP32 documentation, the SPI Master Driver doesn't directly support more than three slave per bus. An alternative scheme could be to:
Configure the SPI driver with spics_io_num set to -1 so the SPI peripheral doesn't automatically control the CS pin.
In the application use GPIO to control the CS pin. I.e. each transfer with a SPI slave would involve:
Setting the GPIO CS pin for one slave active.
Call the SPI driver to perform a transfer.
Once the transfer has completed on the SPI bus, set the GPIO CS pin for the slave inactive.
The downside of the above approach is more timing overhead per SPI transfer, as the application has to control the GPIO CS pin timing, rather than being done by the SPI peripheral. The question doesn't seem to specify the data rate required for multiple SPI slaves, to be able to determine if the above suggestion will meet the requirements. |
H: Power amplifier vs voltage amplifier
I am trying to learn more about the different types of amplifiers.
I have built a voltage amplifier but I am trying to learn how to build a power amplifier and I don't understand the design differences between them.
When I try to look up a class A power amp and a class A voltage amp the circuit looks the same.
What are the design differences between a class A power amplifier and a class A voltage amplifier? What makes them different?
AI: There are a couple of ways that a class A amplifier can deliver power to something. The first case is when the "load" being powered is connected between the transistor's collector and the supply rail, and the second is when the load does not form part of the amplifier itself, and is an external, subsequent element.
Load between collector and supply
By "load", I mean whatever element is supposed to be receiving power from the amplifier. In this scenario, the load forms part of the amplifier itself, and is connected between the transistor's collector and the power supply. That is what is meant by "class A operation" in the strict sense of the term:
simulate this circuit – Schematic created using CircuitLab
In these scenarios, the load always receives power according to whatever voltage is placed across it, and whatever resulting current flows through it:
$$ P = V \times I $$
Given that your choice of R2 determines voltage gain, or transconductance, this class A design always presents the intended voltage across the load, or passes the intended current through it. In this sense the amplifier is already a "power amplifier". It needs no additional "power stage" or "buffer", since it inherently delivers power to the load in the intended quantity, and what the load does with that power is not this amplifier's concern.
On the left we are powering a loudspeaker via an audio transformer. We wish to modulate the voltage across the transformer's primary winding, whose resistance we know to be 600Ω. As we would do for a regular class A voltage amplifier, we choose R2a to produce the required voltage gain \$A\$:
$$ A = \frac{600\Omega}{120\Omega} = 5 $$
That is, a signal of amplitude 1V peak-to-peak at Q1's base will produce a variation of voltage across the winding of 5V peak-to-peak:
The resulting current depends on the load's impedance, and delivered power will depend on both voltage across and current through it, but unless you connect something else to Q1's collector, that's where the story ends. Even though this circuit has voltage gain, which we designed to be 5, the load takes whatever current it takes, getting all the power it needs, and we can call this circuit a "power amplifier" already, with nothing else to add.
The right hand circuit aims to modulate LED current in proportion to a potential at Q2's base. This time, the LED decides its own voltage, which will remain more or less constant over a wide current range, meaning that collector potential will hardly change at all. Consequently voltage gain will be near zero! Here we are interested in how collector current changes with base potential, not collector voltage. Gain will be in units of amps-per-volt, not volts-per-volt, called "transconductance" \$G\$:
$$ G = \frac{1}{R_{2B}} = \frac{1}{120} = 8.3\frac{mA}{V}$$
Here's what happens to LED current, when a 1V peak-to-peak sinusoid is applied to Q2's base:
Once again, there's no "power stage" or "buffer" or other modification needed to transform this amplifier into a "power amplifier". It already delivers exactly the right power to the load, because it already is a power amplifier.
I reiterate that the load, in this case an LED, gets exactly the power that this class A amplifier is designed to deliver to it, and for this reason can say that this design is already a power amplifier.
This is not to say, though, that you can insert any old load there. The problem inherent to the class A design is that quiescent current (current passing through the load and the transistor when input is "quiet") is always substantial. Typically, when the collector is half-way between the positive and negative supplies (+6V in the above examples), current is also half-way between maximum and minimum. There's always current flowing, and always power wasted because of that.
If you connected an 8Ω speaker directly as the load (no transformer) in schematic above left, and adjusted R2a to suit, on average you'd have 6V across the loudspeaker, and the remaining 6V across the transistor, even with a quiescent input. Both transistor and speaker would pass current, and dissipate heat:
$$
\begin{aligned}
I = \frac{6V}{8\Omega} = 0.75A \\ \\
P_{Q1} = {P_{SPEAKER}} = 6V \times 0.75A = 4.5W \\ \\
\end{aligned}
$$
Either you use components that can tolerate such conditions, or you use a different design.
Subsequent external load
Sometimes we use a class A amplifier as a simple voltage amplifier, and we take its output from the transistor collector. We replace the load from before with a simple resistance, which allows us to set voltage gain, and our signal of interest is now collector potential:
simulate this circuit
Note: Voltage source V2 is used in this example to "bias" the system so that the output is centered (has a mean value) at 0V.
That's an amplifier that has a voltage gain of about \$\frac{R_1}{R_2}=5\$, subjected to two different loads. On the left there's no load at all. On the right, though, R3 is a "heavy" 1kΩ. They are still both class A amplifiers, but where we had a transformer/speaker or LED before, now we have a simple resistor R1. Power is delivered to R1, as you would expect, but that power now is wasted as heat, and unused. This is now a plain old voltage amplifier.
Whatever is connected to that output is going to draw some current from it, and an amplifier's ability to maintain its intended output voltage under that load is what differentiates it between "power amplifier" and just a regular voltage amplifier.
In other words, a voltage amplifier that deserves the title "power amplifier", is one that is is able to maintain its intended output voltage even under heavy load. It's still a voltage amplifier, but it is able to provide whatever current the load demands.
As an analogy, all cranes are supposed to be able to lift their load to a height of 1m. All cranes are cranes. However, some cranes can lift 10,000kg to that height, but some cranes will fail to lift even 100kg only 1mm off the ground. Not all cranes are "power" cranes.
For this amplifier to successfully maintain its output at 10V, even with that load present, then it must simultaneously provide the requisite current through R3, which by Ohm's law would be:
$$ I_{R3} = \frac{V_{R3}}{R_3} = \frac{10V}{1k\Omega} = 10mA $$
In the schematic above, that's clearly not the case, as ammeter AM1b shows. This is a good voltage amplifier with no load, but as soon as we demand any current from it, if fails to attain adequate output swing, and gain drops. It cannot be considered to be a power amplifier in any sense. Graphs of \$V_{IN}\$ (blue), \$V_{OUT1}\$ (orange) and \$V_{OUT2}\$ (tan) will illustrate:
The input signal \$V_{IN}\$ (blue) is 4V peak-to-peak, and we would expect an output of 5 times greater amplitude. That's not a problem for this amplifier when unloaded, as we can see \$V_{OUT1}\$ is 20V peak-to-peak, but the moment we add the 1kΩ load, our amplifier's output \$V_{OUT2}\$ (tan) is attenuated by 50%.
To reiterate, a power amplifier is a voltage amplifier that is able to meet the current demands of its load. This one cannot.
To turn this circuit into a power amplifier, not only must it have a voltage gain of 5, but also the ability to provide all the current that would be demanded by any reasonable load, such as an 8Ω loudspeaker.
If you wanted that ±10V signal to appear across an 8Ω speaker, then expect a commensurate demand for current:
$$ I_{OUT} = \frac{V_{OUT}}{R_{OUT}} = \frac{\pm 10V}{8\Omega} = \pm 1.25A $$
You must therefore endow your amplifier with the ability to produce at least +1.25A when its output is required to be +10V, and also −1.25A when the output should be −10V. The application may only call for positive output voltages (or only negative!), and so how you go about this depends on the application.
R1 and R2 both introduce resistance in the path from power supply rails to the eventual output, so its ability to source/sink current into and out of its output is "impeded" by them. Any such resistance in an amplifier's output path affects its ability to source and sink current to/from the load, and is called "output impedance". This particular design has an output impedance of many hundreds of ohms. With a load of 8Ω you need to aim for an output impedance of much less than that.
It's worth noting that it is of course possible to decrease a class A amplifier's output impedance simply by reducing R1 and R2, but the cost is greater quiescent current, and the improvement is only minor.
Usually we would add an additional "buffer" stage to the amplifier, able to reproduce the voltage output of the first stage, but with much greater ability to satisfy the load's current demands. In applications where output is of one polarity only, a simple emitter follower may be all that's needed. In audio system, it's usually achieved by a push-pull pair of emitter followers:
simulate this circuit
Because the first stage has such high output impedance, we must avoid excessive loading there. Power stage 2 (the "buffer") must draw as little current as possible from stage 1. To achieve that, I've used two darlington pairs, with extremely high current gain, to keep base current down to microamps, which you can see on ammeter AM2. This places such a small load on the first stage, that the signal at OUT1 is hardly affected at all.
The power stage has a voltage gain of about 1, so its role is solely to offload the first stage, and take on responsibility for current provision for the load. This can seen on ammeters AM2 and AM4. When the output is (nearly) 10V, the first stage is being asked to provide only a few tens of microamps. Contrast that with current in the 8Ω loudspeaker load, over 1A!
Note that all this load current is now being drawn not from the first stage power supply (which ammeter AM1 shows to be only a few milliamps), but rather from the supply to the power stage, which is visible on AM3.
Combined, these two stages form a "power amplifier with a voltage gain of 5".
This power stage is very flawed. Take a look at the graphs of \$V_{IN}\$, \$V_{OUT1}\$ and \$V_{OUT2}\$ over time:
Notice how the potential at OUT1 is now unaffected, because it's almost completely unloaded, and achieves full swing.
Notice also how the power stage output OUT2 has problems. Its amplitude is a couple of volts short of what we would like, and there are flats in the waveform. This is due to crossover distortion, a side effect of using emitter followers, which can be mitigated in many ways that I won't cover here. |
H: Nodal analysis doubt
Can we apply nodal analysis to find out the current in each branch for this circuit:
I am having trouble to find the correct reference point where I can take V = 0.
(If you are down voting the question, please mention the reason.)
AI: Explicitly done based on comments: I have swapped the elements in the middle branch. |
H: DSP system step response
I am preparing for my DSP exam and have this question about block diagram of DSP system: "Fsampling = 16 kHz, Delay = 4000 samples, Gain = 0.75. Provide impulse response of this system:"
I assume that this is FIR filter, so impulse response would be finite. I tried drawing impulse response, how I assume it should look like for this system (sorry for my bad job, but I hope you could understand that). Is this correct?
Also, if impulse has a 1 in 1000th sample, how would the output look? since there is no Gain on n (current) sample, impulse response would be 1 at 1000th sample ,then 0 and then 0.75 at 4000th sample?
AI: You have it correct now.
It is a FIR system. It simply provides direct output, and attenuated output delayed by 4000.
Nobody claims it is a filter. For us humans, that would be maybe an echo effect for audio, because you hear a single delayed and attenuated echo after 250ms. |
H: PIC assembler to perform arithmetic on 10-bit number spanning 2 registers
I wondered if there was any 'clever' way of decrementing a 10-bit value which is stored across 2 registers. In this case, its the PWM duty cycle value which has its 8 MSB in PWM1DCH and its 2 LSB in PWM1DCL (in bit positions 6 and 7).
I've figured out a way of incrementing the 10-bit value, but the decrementing logic looks as though its going to get very messy.
The code below counts up to the max held by the 10 bits, then switches to the code which decrements the 10 bit value until it is zero. It's the decrement logic that I'm looking for help with.
banksel PWM1DCL
; lsb are in pos 6 and 7 or PWM1DCL register
; copy into W register
movf PWM1DCL
; or with 00111111 to set all other bits high
xorlw 00111111b
; now increment W Reg and check if its rolled over
addlw 1
btfsc STATUS,Z
; if zero, then goto increment PWM1DCH
goto PWM1DCL_HAS_ROLLED_OVER
; store W reg MSBs back in PWM1DCL
andlw 11000000b
movwf PWM1DCL
goto leave_incrementing_logic
PWM_HAS_ROLLED_OVER:
clrf PWM1DCL ; zero out the low bits
INCFSZ PWM1DCH ;INCREMENT high register
goto leave_incrementing_logic
; high order bits have rolled over, so its time to start decrementing
goto REVERSE_DIRECTION
I can see a way of using a brute force method to do this, but its likely someone will have a more elegant way of doing this. The only criteria is that it must be possible to detect when the 10 bit value has hit zero so that the cycle can be reversed and begin incrementing once more.
The code will be running on a PIC16F1503 processor.
Cheers,
Mike
AI: Increment:
banksel PWM1DCL
; lsb are in pos 6 and 7 or PWM1DCL register
movlw 01000000b
addwf PWM1DCL,f
btfsc STATUS,C
incfsz PWM1DCH,f
goto non-rollover code
(rollover code)
Decrement:
banksel PWM1DCL
; lsb are in pos 6 and 7 or PWM1DCL register
movlw 01000000b
subwf PWM1DCL,f
btfss STATUS,C
decfsz PWM1DCH,f
goto non-rollover code
(rollover code)
Note that in either case, if the btfsc/btfss condition is true (no rollover of the LSBs), you go straight to the non-rollover code; otherwise, the incfsz/decfsz controls that decision.
Note also that when the "rollover code" is reached, it may need to apply some fix-ups to the values. When the increment rolls over, the value will already be set to zero (not 0xFFC0), and when the decrement rolls over, the value will be 0x00C0. These values might not be suitable for the application.
One way to address this is to apply the above code to "shadow registers" in RAM rather than operating directly on the hardware registers. Then, once any needed fix-ups are done, the shadow values can be copied into the hardware registers.
My main intention here is to demonstrate how it's often better to think in terms of operations on f rather than operations on W in PIC code. It's been a while, but there was a time in my life when I was doing quite a lot of PIC assembly-language coding. |
H: With what can I replace a MLCC capacitor to ground of 6.3V and 4.7uf
I have a mobo and the cap highlighted above in the picture C4 (6,3V 4,7uF) has broken off, I want to know what can I replace it with if I dont have specifically the same voltage and capacitance but the same dimensions 0805. The mobo is h61mxv v2.0 but the schematic is is for v1.0 still the circuit and caps are the same. if someone wants the schematic for further details I can give you a link.Also what does the "dummy" text signify?
AI: Any capacitor about that capacitance and rated for at least 6.3V.
If you don't have anything close, order a replacement. That's a few cents a part. |
H: Does a ATTINY88 Micro Arduino clone have a quartz crystal? (LaserTag project)
Is the square thingy under the Reset switch (on the right side) a quartz crystal?
I have found this board crazy cheap (1 euro) compared with a real Arduino Nano.
I need to generate a 36kHz signal, so it needs a quartz.
AI: It surely looks like it has a crystal.
But you never know if the clone selling website photo will match what you get.
And since you're not even sure why you need the crystal, it's questionable that
you actually need a crystal to generate a sufficiently precise 36 kHz signal, and
if you actually have specifications for how accurate your frequency needs to be, then not having a datasheet that specifies how precise the on-board crystal / oscillator are is a non-starter. |
H: How to prevent photoresistor sensor from draining battery
I'm looking for a simple hack to minimise current when detecting change in light intensity using photoresistor.
I'm using ATTiny85 in deep sleep (power down, ADC disabled, using below 1 microamp) waking by pin change (interrupt pin). After pin change ATTiny executes some operations and goes to sleep again. Device is powered with small battery and the battery should last for a year.
The event that wakes microcontroller is change on pin PB3. PB3 is connected to ground by photoresistor.
Everything works as expected. Change in light conditions wakes the microcontroller, and after some actions it goes to sleep again.
The photoresistor, when it is dark, has 1 megohm resistance, so the current is minimal. But when it is sunny, the resistance falls below 10 kilohm, and the PB3 pin leaks above 50 microamps all day, even though the microcontroller is in deep sleep, not doing anything. I'm interested only in pin change, so after it gets sunny, and the low photoresistor resistance triggers PB3 I'd like somehow to block the current flow till the next change.
Is there any simple circuit (possible using capacitor?) to achieve that?
AI: Sleep on the watchdog timer (or other low power timer) instead and then only power the photodetector at the end of each sleep.
Connect the top of the photoresistor circuit to a GPIO so that you can power the circuit off.
simulate this circuit – Schematic created using CircuitLab |
H: Noninverting input voltage seen on V+ pin of OpAmp
I've built this exact circuit here, except for one variation: SHDN is connected via a 10K resistor to ground. The opamp should be off!!!
What happens is when I connect a battery (or power supply) to VBAT, somehow that voltage is makes it way to the V+ pin, which is connected to 5V (turned off ATM, I'm only focusing on Vin rn). If I connect a 100k resistor between 5V and GND, the circuit draws about 200uA when 3V is on VBAT. SHDN is at GND, the output is also at GND.
What on earth is happening here? This opamp is supposed to have an input bias current in the pA range. How is the input "getting through" the chip?
This is very important because this is a battery powered device, and I need uA of consumption when the circuit is off, not in the 100s.
The only ideas I've found from google so far are more decoupling (I tried adding 2x 10uFs, same problem) or that the input impedance was too high...
AI: What happens is when I connect a battery (or power supply) to VBAT, somehow that voltage is makes its way to the V+ pin
It sounds like you are expecting no voltage on V+ (because the 5v rail is off in shutdown mode), but there is. This is likely because you are operating the op amp outside of the absolute maximum ratings. From the datasheet, the voltage on an input pin should never exceed 0.2v + V+. In this case you are exceeding it by 3v.
To fix this, you could disconnect the inputs to the op amp when in shutdown, or, if possible for your application, power it directly from the battery. |
H: Single Ended to Differential Conversion with Opamp and Correct DC Biasing Method
First schematic below is the initial gain stage of the intermediate signal generated by mixer of radar. It is passed through sallen key high pass filter.
Second schematic for differential to single ended conversion with some gain. And then another stage with digital potentiometer for adjusting the gain with a microcontroller.
At last stage i need to convert signal back to differential for driving the SAR ADC. I have found 2 reference designs from links below and converted accordingly.
Page 28 of the datasheet for single to differential convertion
Single to differential convertion reference 2
ADC range is 0-3.3V and DC Bias should be around 1.65V.
My questions are:
Is this design correct, especially the second schematic. When you check the stages, is there any problem that i could not see such as wrong conversion, wrong dc bias apply or connection etc. For example can i directly connect pin 14 of the ADA4807 to pin 5.
For DC Bias generation, can i simply use a LDO regulator with high PSRR. I had oscillation problems when i generated DC Bias with op-amp voltage follower.
ADA4807 Datasheet
LT6232 Datasheet
Later Update for further details of the system:
For radar, a closest target at 1 meter distance will reflect 1 to 3 kHz 0.05-0.1V IF signal but the signals coming from further targets are a lot weaker down to microvolts. The reason of the high pass sallen key is that distant target will reflect microvolt level signal therefore it is like a noise on closer target. When 40 dB/dec high pass filter is used, the closer signals will become weaker meaning lower amplitudes (fc = 400 kHz, Q = 0.5, damp = 1 for this setup because radar cannot see beyond 200-250 meters but it can be changed for higher cutoff later). This is the end of first schematic. Overall we amplified signal and prepare it for filtering. After the high pass filter section the signal is compensated but still needs a lot more amplification because after first gain stage filtering decreased amplitudes.
Higher sampling rate improves SNR performance along with differential input thats why i kept it differential, but converting single ended would be easier in case of number of components as well. Sampling will be around 3.3 to 5.6 MHz (higher sampling and down sampling is better. It will be certain according to the USB throughput). For now it will be 3.3 MHz sampling rate.
AI: The one thing that I have encountered in the past, is oscillataion do to positive feedback through the common mid-point bias connections. I have shown one such positive feedback path in the diagram as a red line. If the gain around this loop is greater than 1, then it will oscillate.
Look at pin 3 of U32A. A signal <3MHz on this pin will be multiplied by 11. So the rest of the path must attenuate by at least the same amount.
You can find other such positive feedback paths on both schematic diagrams.
If I am not mistaken, there is one long path from DCBIAS on U15A pin 3 through IFF+,through U32A Pin 3, and returning to DCBIAS through U32D Pin 12.
There are 3 non-inverting gain sections for signals on this positive feedpack path totaling about 1700.
This is likely the source of your oscillation.
There is another source for oscillation. As the bias network grows, the capacitive load on an op-amp driver will increase. If the capacitive load is too great for the opamp, it will oscillate. Using a regulator instead may be better. Choose a regulator that can work with 10s of microfarad capacitance on its output.
An op-amp used for mid-point bias must be able to handle all the ac current that must pass through the bias network.
An LDO regulator can sink current only through its output capacitor so may not be appropriate either.
Even if a perfect source is available, the inductance and resistance of the bias distribution network (BDN) will cause the voltage to bounce depending which way the current passes.
To correct this problem, the positive feedback loops must be broken or decoupling applied at each tap from the BDN. Both these methods are shown below.
In Figure 1. R1,C1 and R2,C2 decouple the OA1 and OA2 respectively from the BDN and from each other, But there is still a hardwired connection between each stage.
In Figure 2, The voltage dividers provide a local bias voltage while the capacitors provide an ac ground. The stages are completely separate from each other so cannot interfere with each other. The voltage dividers each can be buffered with an op-amp if necessary, but usually just the bypassed voltage divider is enough. You may not need the capacitor depending on configuration.
I have used both methods successfully and prefer the method in figure 2.
simulate this circuit – Schematic created using CircuitLab |
H: Time function for an equivalent circuit
In the IEEE magazine 6. NO. 3. JULY 1991 A Novel Soft-Switching Full-Bridge DC/DC Converter: Analysis, Design Considerations, and Experimental Results at 1.5 kW, 1OOkHz the following converter has the active state when any of the pair of transistors S1-S4 and S2-S3 are on.
C1 and C2 represents the parasitic capacitance ( Snubber, Trafo, etc ).
The converter has the following equivalent circuit for the passive state, the state in which no power is transferred through the Transformer.
simulate this circuit – Schematic created using CircuitLab
All the energy needed to charge the capacitance must be accounted for and the the author came up with the following time function for voltage across C1. What was his approach to it?
$$\begin{aligned}
V_{C1}(t) =& V'_O \frac{L_m}{L_m+L'_O}(1-\cos{\omega t}) \\
-& (I_m+I'_P)\sqrt{\frac{L_1+L_C+L_m||L'_O}{C_1}}\sin{\omega t} \\
+& V_{in}\cos{\omega t}
\end{aligned}$$
EDIT: Franc enlightened me! Thank you!
AI: Assuming that the applied voltage has a sinusoidal time trend with pulsation ω and unit amplitude and that the initial conditions are zero, the calculation of the voltage across the capacitor is simple: |
H: Using UART/USB Bridge vs straight USB stm32
I've been doing some research over the last few days into implementing usb communication protocol on the stm32. I know that the stm32 has dedicated pins for USB communication, however I still see a lot of designs using a UART-USB bridge despite the existence of these pins. I haven't been able to find much in the way of what the advantages/disadvantages of using a UART-USB bridge is vs just using the USB pins directly.
If it makes a difference, for my application I am planning just to use the USB port for programming after the initial bootloader is uploaded, however I am considering making an GUI that goes with this circuit at some point. For the design I am using a STM32F103RCT6
AI: With a USB UART bridge, you can see the virtual COM port in your PC and communicate with it, even if there is no firmware on MCU.
Also the MCU then does not need firmware that supports USB in any way and can simply communicate with UART.
Which means that since the F103 does not support DFU with factory bootloader, you are forced to write your own firmware and/or custom bootloader that supports USB enough to be able to update the firmware portion.
The factory bootloader does support UART so with a USB to UART chip, you don't need any special custom firmware or bootloader, as you can simply boot (somehow, maybe with a button) into factory bootloader and program the MCU, and you are never locked out of the system.
However, using the MCU USB interface allows you to present itself as any device you want, such as keyboard, mouse or mass storage, etc, which isn't possible through the USB UART chip.
So it really depends what you want to do. If you don't use the USB for anything else than uploading new firmware, then you need to develop software yourself that you trust has no bugs when you upload the firmware. And then you need to implement the PC side too if you use your own custom protocol. This is something you don't need at all if you put a hardware USB UART chip there.
The other option is also not to use the F103. If you use an STM32 which supports USB in the factory bootloader, then you don't need the USB UART chip and can upload with existing GUI tools. |
H: Adding on and off state in a 555 timer clock circuit
I'm making a clock signal for my circuits, and I'm utilizing the 555 timer for this. I made this circuit below which outputs a clock signal. And now I'm trying to figure out how can I add on and off state on it.
I want the clock turn on when a constant high input is in and turns off when it is low (kind of like a switch).
Below is the schematic I made.
AI: Basically i want the clock turn on when a constant high input is in and turns off when the it is low (kinda like a switch)..
Use \RST pin (pin #4).
It's an active-low input so when it's tied to ground the 555 stops (i.e. output becomes zero). And, when it's high i.e. tied to VDD just like in your schematic the 555 runs (generates clock).
Check the datasheet of the particular device you are using (or about to use) for the correct voltage levels of the \RST pin.
PS: The 10u cap across the output may filter out the clock signal. It also loads the output. Remove it, or at least connect across the supply input (i.e. across VDD and GND) instead. |
H: PSPICE non sinking voltage source
In an ideal world, most power supplies have a current sourcing feature but not a sinking feature. In this circuit, you can see that the 15V supply is sinking current. How can I prevent this in Pspice?
AI: There's a clue in the 72.73 μA flowing into R2 (330 kΩ): -
That current and that resistance implies a voltage source of 24 volts somewhere in your circuit and, hey-presto, there it is on the 2nd and 3rd diagram: -
So, it seems to me that the current you see running into your supply is negative and this should be no surprise given the 24 volts at the input. It's likely that PSPICE calculates the currents at the initial point (rather than waiting for everything to settle down.
How can I prevent this in Pspice?
If it's a problem then you have to redesign your circuit. It isn't a PSpice problem that requires some kind of PSpice fix. |
H: Arduino Nano in PCB for a controlled heating rig - Can't get it to work
Background
I'm making a heat sealing machine. The mechanical side is all OK but the electronics is challenging me. Here's the gist of the setup. I've put it all in the image below. Apologies for the rather unconventional circuit diagram...
The Target
I need to make a PCB that has all the components together with the Arduino Nano - everything soldered on one board -- so that I can install it in my machine.
What works so far
I have built the circuit on a breadboard. It works great, so the circuit itself and the Arduino code is functional (as is the PID algorithm).
The problem
After testing on a breadboard, naturally the next step is to translate it to a PCB.
Using Altium CircuitMaker, I have made the circuit and routed it as in the image below.
Here is the schematic
and here is the routed PCB.
After transferring, etching and soldering, I have found that the circuit does not work. It actually burnt the regulator on my Nano and fried it but I am unable to tell why this is happening. This is even before I attach the external 15V supply for the higher power part of the circuit. It literally burns out even when I put the 9V into Vin.
I'm using a single-sided copper clad board for my PCB so I am limited to a single conductive surface. My transfer mechanism is also rather coarse, so I'm sticking with 70mil pads and 40mil traces.
Here are some images of the final board
And here's the solder side of the PCB
Where I'd like some help
I'd like to learn what's wrong with my board routing, and anything else that I'm doing wrong from a circuit-making perspective, that's preventing my circuit from operating correctly.
I'm a little stumped because I have routed everything as in the breadboard version of the circuit, but it doesn't work. I suspect there is something seriously wrong with how I've routed the board, but I have no idea what it could be. I just don't have the knowledge.
Happy to share the CircuitMaker files and Arduino code if necessary.
AI: Looks like your etching is incomplete and it has left some 'whiskers' between traces. There may be more (I think I see the 9V too, but maybe the input power has burned that out): |
H: Leakage inductance in a series resonant converter
I know that the leakage inductance is present due to the imperfect linking of flux between the two transformer windings. I have selected a core for the transformer to be used within a series resonant converter.
Using FEMM, I have simulated the transformer core along with the windings to get some idea about the leakage inductance for the transformer. I have calculated the leakage inductance value from the simulation results to be about 7 μH.
In this case, if I require a leakage inductance value of about 100 μH for the SRC to work for my application, can I keep an external inductor in series with the transformer primary to get the required value? If this is not possible, are there any other ways to achieve the required inductance value?
I am trying to implement a PCB transformer in this case, as inter-winding isolation is important.
AI: From the point of view of your source, adding an inductor in series with the transformer is fine, since it will see the inductance of the transformer (and downstream circuit) summed up with the inductor.
Regarding your FEMM calculations, I would recommend you to make sure your inductance calculation is properly done. For a transformer, there is an important difference between leakage inductance and magnetizing inductance.
In the diagram below, you can see the leakage inductance split in two different inductors (L1 and L2) in the transformer model and the magnetizing inductance (Lm) (note that this model is just one among many transformer models available). The magnetizing inductance is related to the core excitation by the voltage in the primary while the leakage inductance is defined by the stray field between two transformer coils. |
H: Maximum voltage applied to the BJT base
I have a functional circuit designed for return line reverse protection, and a relevant portion of the circuit is shown below:
simulate this circuit – Schematic created using CircuitLab
In this circuit, I anticipate that when +28V is connected to the return line, it will turn on Q1, causing point B to be at 0.7V. However, if point A is at 28V, point B would theoretically be 2 * 28V = 56V. Although the transistor (Q1) stabilizes point B to 0.7V, there is still dissipation heat generated that could potentially damage the transistor. According to the MMBTA06 datasheet, the maximum emitter-base voltage is specified as 4.0V, which suggests that Q1 might be at risk of failure. Surprisingly, despite this, Q1 does not blow up. Upon consulting my teacher, he indicated that the use of 0805-sized resistors R3 and R2 may be preventing any issues. But it does not make sense to me. Please advise.
AI: The voltage will not exceed about 0.7V with 28V at point A because the current is limited to 27.3V/47.5kΩ or less than 0.6mA.
The maximum emitter-base voltage is specified at 4V, you are applying (forward) base-emitter voltage. In other words the data sheet is telling you that -4V base voltage wrt emitter is the limit. This is because of potential reverse breakdown in the base-emitter junction. Most jellybean NPN silicon transistors are rated for -5V. RF transistors, often less.
Can't say as the rest of the circuit makes much sense- the MOSFET is connected as a source follower and diode D1 provides a path to destroy the BJT as well as itself. |
H: Inductors - understanding the depth of its working
When there is an initial change in current, I understand that the inductor resists the change. but how does it eventually give in with the flow of current?
can someone give me the nuances of the working of the inductor?
AI: The inductor acts against a change in current. For an ideal step change, i.e. a forcible change of current in no time, the resulting voltage is infinite.
\$V = L \cdot \frac{\Delta I}{\Delta t} \qquad[Volt;Henry;\frac{Amper}{second}]\$
For a finite slope of current over time, you get a finite voltage. |
H: How to limit current for this LED in circuit with a load?
I'm a newbie in electronics and just recently decided to get some deeper knowledge and try to start some projects. But it didn't take that long before I became stuck. Here's my problem.
I want to design a circuit with 12DC output that will be connected to two loads in parallel and each load would have its own signal LED diode. This diode will light up if everything works correctly and be off in case of a open circuit. I was thinking about using transistors or making some sort of a logic gate but I'm not sure how to continue:
I came up with this diagram, R1 and R2 being the loads that use 10W (so there needs to be 14.5ohm resistance in the circuit, right?). But curcuitlab doesn't even think that's a valid circuit (neither do I, haha)
So could you please help me understand how to make that circuit work? Also that would be an option only for an open circuit, for a short circuit fault would something like a fuse be an appropriate solution? Thanks
AI: This circuit will light the respective LED when current is flowing through the respective 14.5Ω resistor, typically turning on about 1/2 of the expected current. In other words, if the resistors are less than about 28 ohms you can expect the LEDs to light when the switches are 'on'.
simulate this circuit – Schematic created using CircuitLab
It uses a single 8-pin DIP integrated circuit dual op-amp. I don't think the circuit can be much simpler. You should connect a bypass capacitor of 100nF across and near the op-amp supply pins.
Vr is about 40mV and the resistors R1/R3 drop about 80mV when the switches are 'on'. R1 and R3 are low resistance so they waste very little heat and can be small parts. |
H: Hold button for UK Landline telephone
We have retro rotary telephones, and I'd like to make a hold button for the one in my office in the UK.
This is literally a "ye olde rotary phone" (1940s) made from bakelite
I have fairly basic electronics skills but I don't actually know how the phone works, in that sense anyway.
Is this just a case of switching out the circuit to one playing "The girl from Ipenema" or is it more complicated than that?
For example, what is it that keeps the line open if I make an outgoing call? Could I accidentally cut the call or does the line need to go open circuit to do that? What are the voltage limits?
(I would just buy one, but can't find any!)
[UPDATE]
Some good points have been made in the comments that bear
highlighting.
When I used to work in a shop repairing computers (about 40 years ago)
we also sold telephone handsets to the public; the ones with green
stickers were allowed to be connected to the phone network, the ones
without - or with red stickers - were not. I'm pretty sure the same or
similar system exists today, especially with digital exchanges,
"digital voice" etc.
So, to be clear, nobody should be connecting unauthorised equipment of
any kind to the telephone network.
AI: If these are phones that work the same as genuine ye olde rotary dial phones, then, a telephone line will be "held" by placing a resistor across the line that draws at least the minimum required by the system. This will vary by system but I'd guess that a 1k resistor would work. This can be determined experimentally or by asking the system supplier or finding a specification (which probably does exist for most systems).
To place a call on hold (other than leaving the phone 'off hook', "The girl from Ipenema" needs a suitable resistance across the line, and switching must becarried out "make before break".
To make an outgoing call "The girl from Ipenema" must be first removed |
H: Calculate the output IP3 of this transmitter
The following is a tutorial question from my teacher.
A transmitter requires the IM3 products to be -65dB below the main tones when the total output power is 20 dBm. Calculate the output IP3 of this transmitter.
This is what I think.
The output IP3 is the third-order intercept point, which is the input power level at which the third-order intermodulation distortion (IM3) products are 30 dB below the main tones. In this case, the IM3 products are -65 dB below the main tones,
$$OIP3[dBm] = P1 [dBm] + \frac{\Delta P [dBc]} {2} = 62.5 dBm$$
$$OIP3 = 30dBm + \frac{65 dB} {2} = 62.5 dBm$$
But the book give me 49.5 \$dBm\$.
AI: You have made several errors, not all of which contribute to your wrong answer
The output IP3 is the third-order intercept point, which is the input power level at which the third-order intermodulation distortion (IM3) products are 30 dB below the main tones.
The output IP3 is the power level at which an IM3 component is equal to one of the main signals, not 30 dB below.
It's worth correcting this, even though it doesn't contribute to your error, as you then give the correct formula for IP3
$$OIP3[dBm] = P1 [dBm] + \frac{\Delta P [dBc]} {2} = 62.5 dBm$$
Having given the correct formula, when you evaluate it, 30 dBm creeps in again instead of the actual P1, which for two equal tones with a total power of 20 dBm is 17 dBm.
Using the correct P1 gives the book answer
$$OIP3 = 17dBm + \frac{65 dB} {2} = 49.5 dBm$$ |
H: 5V to 3.3V LD1117 voltage regulator design
I am using two 5V 1W voltage sources in parallel and I want to regulate the output to 3.3V using an LD1117. I need help calculating the R2 value for the LD1117.
I have read the datasheet linked below but I find it confusing. How do I calculate the value for R2, given that R1 is 120 Ohm?
I know it is described in the datasheet but I do not understand Vref.
Source: LD1117 Datasheet
AI: Vref is a voltage reference inside the IC. It fixes the voltage between OUT and the ADJ pin to 1.25 V, regardless of Vin. You can use Vref to manipulate the voltage on the ADJ pin through the feedback network provided by R1 and R2.
For regulation, you should use the formula:
Vout = Vref (1 + R2/R1)
where Vref is 1.25 V and R1 is 120 Ω (or something between 100 Ω and 200 Ω)
For example, if you set R1=120 Ω and R2=240 Ω you will get the following output voltage:
Vout = 1.25(1+240/120) = 3.75 V
The second part of the long formula in the datasheet can be ignored, as it explains, because Iadj is in the order of microamps, so very small.
So, with ADJ tied to GND you would get 1.25 V in Vout. But with the voltage divider you force a higher value in Vout that, once divided, matches with the 1.25 V difference between both pins. It's a feedback system to increase Vout and it doesn't depend on Vin, because of the internal absolute voltage reference. |
H: How can we know reason \$9.6[dB]\$ from this graph?
The diagram can be found at graph link
A lot of textbook give this formula.
$$IP3 = P_{1dB} [dBm] + 9.6[dB]$$
This equation is valid for both input and output referred quantities.
But how can we know reason \$9.6[dB]\$ from this graph?
AI: But how can we know reason 9.6[dB] from this graph?
That comes from heavy math and approximations using Taylor expansion.
I will not do the entire math here but here's a summary:
The presence of harmonics allows us to approximate a system's output (for a sinusoidal input e.g. \$v_i=v \cos(\omega t)\$) using Taylor expansion and half-angle formulas (trigonometry):
$$
\begin{align}
v_o&=a \ v_i \\
&=a (v \cos (\omega t))\\
&=a_0+a_1 (v \cos (\omega t))+a_2(v \cos (\omega t))^2+a_3 (v \cos (\omega t))^3+... \\
&=(a_0+\frac{1}{2}a_2v_2+\frac{3}{8}a_4v_4+...)+(a_1+\frac{3}{4}a_3v_2+...) \ v\cos(\omega t) +...
\end{align}
$$
\$P_{1\mathrm{dB}}\$ (1 dB compression point) can be calculated from ideal vs real fundamental components of the approximation above i.e. ideal fundamental: \$a_1v \cos(\omega t)\$ and real (approx) fundamental: \$(a_1+\frac{3}{4}a_3v_2+...) \ v\cos(\omega t)\$
Using the expansion you can also find IP3 (\$P_{\mathrm{IP3}}\$) i.e. the point (input power) where the output third harmonic and the output fundamental powers are equal. But this first requires the Taylor expansion above to be re-written from a multi-frequency input e.g. \$v_i=v_1\cos (\omega_1 t)+v_2\cos (\omega_2 t)\$.
Now the main assumption is that the system's output has components up to the 4th order. This allows you to write the IP3 point in terms of \$P_{1\mathrm{dB}}\$. Therefore
$$
R=\frac{P_{\mathrm{IP3}}}{P_{1\mathrm{dB}}}=\frac{1}{1-10^{-1/20}}\approx 9.2 \ \mathrm{W/W}
$$
Or in dB:
$$
R_{dB}=10\log (R)\approx 9.6 \ \mathrm{dB}
$$ |
H: Dual channel control using a single switch
I have a circuit that uses an EMG module that requires a V+, GND and V- input. When only one of these lines are turned off, the module remains on.
simulate this circuit – Schematic created using CircuitLab
I need to be able to open and close any two lines with a single switch. I have tried to use a PNP and NPN transistor for the V+ and V- lines with little success.
Any help would be greatly appreciated.
AI: I have tried to use a PNP and NPN transistor for the V+ and V- lines with little success.
You can still use either BJTs or MOSFETs but I prefer the latter. Here's a simple circuit for you:
simulate this circuit – Schematic created using CircuitLab
When the switch is open both of the MOSFETs have their Vgs (gate-source voltage) zero. When the switch is closed the NMOS (M1) Vgs will be 3V and the PMOS (M2) Vgs will be -3V.
I put BSS138 and BSS84 as example but you can use any MOSFETs having gate-threshold voltages of less than 2 V for NMOS and higher than -2 V (e.g. -1.8 V, -1.2 V, etc) for PMOS.
One problem here is that there's no guarantee of turning on or off both of the MOSFETs right at the same time. The difference can be in nanoseconds or seconds or microseconds. I'm not sure if this is going to be a problem for your application. |
H: Ground fault detection on an ROV
I'm helping my friend's kid with a school project where their team has to produce a small ROV. Most of their design I was able to review and help make corrections with them but I'm stumped at one junction, because it's not something I've had to work with much... Ground Faulting. They need to detect a ground fault to the metal hull/frame of the ROV.
They currently have no design to accommodate this, and I had suggested they start by looking at current on the supply compared to return, but that's where I got stuck because that only accounts for the power use and will always have less current on the return due to energy converted to heat.
I've heard of people using a negative voltage on the hull/frame and monitoring that for ground fault detection. Does anyone have any experience with this and can suggest a design or point to a resource for this application?
Edit: There is no battery connection to the frame, but some control boards are mounted to it. The system is supposed to be fully isolated. The thruster motors are also mounted to the frame. They are home made thrusters, so the core laminations may not be isolated from the frame, despite being encapsulated.
Update - I probably should have said this the first time. There's an isolated power system, and a non isolated battery bus. I cannot supply schematics - they're not mine to supply. Does one use only one ground fault detection circuit or does it not matter if the impedance is large enough?
AI: To detect a grounding fault it is, perhaps counter-intuitively, necessary to create a deliberate connection to ground.
simulate this circuit – Schematic created using CircuitLab
Figure 1. Ground fault indication circuit. The lamps form a weak "pull to centre" arrangment so a meter would read 6 V between each terminal and the chassis.
How it works:
In normal operation there is no connection between battery positive or negative to ground.
Both lamps (which are rated for the full supply voltage) will only have half the supply voltage on each so they will glow dimly.
If the negative rail gets connected to the chassis then L2 will be short-circuited and turn off. Meanwhile L1 will have full voltage across it and glow at rated brightness.
Similarly if the negative reail gets connected to the chassis then L1 will turn off and L2 will glow at rated brightness.
This may satisfy the requirements of the project as you didn't mention that the supply needs to switch off in the event of a fault. |
H: What is the exact function of this device connected between ground and neutral?
This is the photo of the power distribution panel inside industrial building. On the left most, next to the two thick wires colored yellow/green so as it is likely to be the "ground" we see a strange looking device connected between the two copper rods. There are two more blue wires more on the right. Deciding from color and letter N, the blue wires are connected to the horizontal rod that is "neutral".
Hence deciding from labeling and cables, the device seems connecting neutral and ground in the distribution box that I would expect to be directly connected here. However the device appears more complex than just a simple rod. Why does it appear more mechanically complex? I assume the complexity is somehow related to its less than trivial electric functionality.
AI: Looking at the object close up reveals what looks like two parts. The first, on top, is a simple shorting bar. This is a hunk of copper designed to be easily connected or disconnected from its place between two screws--loosen the screws and slide the bar down and they're disconnected. This one appears to be stamped with a rating, 600 A.
These are very common to see on lab power supplies, to connect one side of the supply to ground without needing to use a cable. This one is much more heavy-duty than those, though--it would have to be, since it's apparently rated for 600 amps!
The second part is harder to see. Underneath the shorting bar there appears to be another metal element, though this one is a different color (perhaps a different metal, or plated) and (to my eye, at least) appears thinner. This could be one of two things:
It may be completely electrically isolated, purely there to hold the other ends in place. In this case, disconnecting the shorting bar would disconnect neutral from PEN--why you might want to do that, I'm not sure, but there may be some reason.
Or, it may be a high-current shunt resistor--a large version of one of this type of metal-element current shunt. In this case, disconnecting the shorting bar would allow one to measure the current passing through it, while connecting it would bypass the current shunt, preventing it from wasting power. |
H: Is an RF sampler a good way to protect my network analyzer during high voltage impedance measurements?
When I characterise ultrasound transducers, I normally do it with a network analyzer in a shunt configuration - ie, I connect the transducer across port 1 of the network analyzer. This gives me plots of phase and resistance across a range of frequencies.
Now I want to see if the impedance changes when the stimulus voltages are higher than what the network analyzer can supply (I need ~15Vpp). To do this I will boost the output of the NA using a 40 dB power amplifier. I came across this document which describes different ways you might protect the NA. The second configuration in this document is the easiest to implement and uses an attenuator to dissipate the excess power. But I don't think this is what I want as it will also reduce the current going through the DUT:
I am wondering if instead of an attenuator I can use an RF sampler between port 1 and the DUT, whilst connecting the sample port to port 2 on the NA. The sample connection will have a 40dB attenuator, and the RF connection will have a very low impedance path to the DUT. Like this:
My questions are:
Is this a good way to protect the NA?
Will I get accurate measurements?
What information will I not get doing it this way? The document mentions that I cannot get reflection measurements, but I don't see why the NA can't deduce that from the forward measurements going into port 2. (presuming my amplifier is fairly linear in phase and gain).
By the way, the nominal resistance is 70 Ohms in the region of interest. I care most about 100 kHz - 1 MHz range.
AI: The diagram you showed is for measuring a 2-port device, not a 1-port. Each port is shown as a single point on the DUT block rather than as two distinct terminals, and each transmission line is shown as a single line rather than as distinct signal and return conductors.
The set-up you want, (from the same Agilent app note) is this one:
I've erased a line from the original drawing because you are measuring a 1-port device rather than a 2-port.
This uses a directional coupler to pick off the reflected wave from the DUT's input port and return it to the 'R' port of the network analyzer. The 'R' port is available on a certain style of VNA that requires an external test set. If your VNA doesn't have an 'R' port, you could connect the reflection signal to the '2' port instead, and treat your DUT plus the directional coupler as a single 2-port DUT. You would then need to do some calibrations to determine how to scale the measurement to accurately determine the reflection coefficient of your DUT.
The difference between this arrangement and your proposal is that the directional coupler preferentially directs the reflected wave to its coupled output, while your "sampler" circuit doesn't distinguish between the forward-travelling wave and the reflected wave.
I should add one other comment:
Now I want to see if the impedance changes when the stimulus voltages are higher than what the network analyzer can supply (I need ~15Vpp).
If your device's behavior changes when the stimulus amplitude increases, then it is a nonlinear device. When you provide a stimulus at frequency f, the reflection will have components at 2f, 3f, etc. The basic VNA is, by design, only meant to measure linear devices, and won't correctly deal with the harmonics of the reflected wave.
You may have a "special" VNA designed for this purpose, but if you don't, you need to be very careful about how you interpret your measurement results...or consider doing the measurement with a different instrument. |
H: How can I enter boot mode with an STM32F411CEU6?
I ordered a PCB with the following schematic based on an STM32F411. As you can see, the NSRT pin is connected to a LP filter. I think I should have connected it to a switch to easily enter boot mode, but I still have 6 external pins: GND, +3V3, SWDIO, SWO, SWCLK, and NRST.
I tried to connect NRST to GND but I still could not enter boot mode.
First I connected the USB power supply to my laptop.
I shorted NRST to GND, still could not boot.
Then I tried pushing BOOT0 to high before plugging the USB connector in.
How can I boot an STM32F411CEU6 with NRST based on the following schematic? Can I still do it with the SWDIO ?
The following picture is from a personal project:
AI: It might not work with SWD either due to core voltage cap issue.
DFU surely does not work at all because it needs a correctly connected external clock.
And the crystal is not correctly connected.
If it still does not when you fix the crystal connections, try a different crystal.
It does not need to have that high frequency, slower crystals are easier and simpler to get working, and the bootloader appnote recommends to prefer slower than faster crystals for more reliably detecting the crystal frequency.
I have not mentioned any other possible problems, but they should not be showstoppers.
For example, no bypass caps visible in the schematics. If the design really has no MCU bypass caps then it may be an additional reason why it does not work.
There should not be a 10k pull-up on the NRST pin, unless you know what you are doing and know it is needed, so I hope you know you need it.
Also C13 is 1000x too small. The MCU core voltage may be unstable. Changing the cap might fix it, if the regulator voltage never exceeded max ratings. |
H: Is it worth adding a transistor on shift register output to drive a LED?
I want to light some LEDs (from 1 to 5 at the same time) using a shift register. I read that the shift register is supposed to output 6mA per pin: ±6-mA output drive at 5 V, which seems a bit low so I figured I could use transistors like described below. I'm a bit confused though:
Are the transistors actually required or could I send the shift register output directly to the LED ?
What if I connect the shift register output directly to the LED (with or without a resistor) ? Will the current be safely limited to 6mA, or is it going to raise and damage the chip ?
I'll use the shift-register to multiplex with other outputs, which means the leds won't be turned on continuously. Does that change anything to the maximum current I can send in the LEDs/shift register ?
[edit]: the LED should be moved to the collector-side, as mentioned by @vir.
Option A: with transistors
Option B: The more basic approach:
AI: The use of a transistor may be required, be desirable, be optional or be superfluous depending on how much peak current you need to pass through the LEDs.
Driven continuously, a few mA is often plenty for an indicator. If you are multiplexing LEDs and they are on 1/n of the time you need roughly n times as much peak current to get similar visual brightness to the brightness with continuous drive.
If you are driving directly, it's often better (in terms of voltage drop in the output under load) to sink current than source it as you've shown when dealing with CMOS outputs. So low = 'on'.
A series resistor (with or without a transistor) is required in order to get a predictable and reasonable current from the output and through the LED.
Exceeding the maximum current from the chip may cause short term damage or long term reduction in reliability. There is also an absolute maximum total current for GND or Vcc (70mA in the TI datasheet) which also should be respected (in that your circuit should pass nowhere near that much current, less if temperature is elevated or if you want really good reliability). If you limit yourself to 40mA that's 5mA per output if they can all be sinking or sourcing at once. |
H: Is it wise to determine heating element temperature from resistivity?
Context
I'm making an electric furnace for melting metal, and aiming to make my own controller.
Everyone seems to just use thermocouples and a control loop, I thought perhaps I could just measure the resistivity from the heating element.
I'm planning on using Kanthal A-1 (rated for 1400°C/2552°F) at temperatures that can reach 1200°C/2192°F. Highest temperature thermocouples I've been able to find were 1250°C/2282°F which is a bit too close for comfort.. a control loop overshoot may kill it and then.. kanthal isn't cheap.
Current Thinking
Now while kanthal has a quite low tempco of ~50ppm/°K, we're talking about a big delta here and precision in the single digits isn't required, so I think it could work. Calibration could be done with the thermocouple.
Since I'm aiming for somewhere around 3-4kw, I was thinking of just rectifying some mains AC, and using 3 ADCs to take the resistivity reading.
Here's the rough idea:
(The switching mechanism for controlling the temperature just isn't drawn, I'm not forgetting it needs to exist).
ADC for this doesn't need to be fast, 100Ksps will give me 1000 readings per every cycle (though I'm thinking 1Msps for switching headroom). And for a 16-bit adc, the 4% change in resistivity over the full temperature swing still gives me a range with 2^16 x 0.04 ≈ 2621 values - about half a degree celsius per increment.
To take the kelvin reading, I'm thinking of using kanthal leads. That way they won't melt. Just tig weld them near the ends of the heating element on the inside of the furnace. The point at which they reach the controller should be ambient temperature, so thermal EMF issues are avoided too.
There are a couple vishay 20ppm/°K 1mΩ shunts for very cheap on mouser, so even though we're talking high currents I think very good precision can be achieved. Could also use multiple, use a heatsink, or even do both.
At 20ppm/°K, in the eggagerated scenario of a 40°C temperature rise we get 20/1,000,000*40 = 0.0008 ≈ 0.1%. That would be 1/40 of that 4% resistivity change.
Wind-Up
I realize this has more possible points of failure than the typical implementation - reading a thermocouple and running a PID loop is tried, tested and rhobust. I'm not asking whether this is the simplest solution to my problem as I know it isn't.
But it does seem the most reasonable for the resources I have at my disposal.
So, provided what I wrote above is right (and please, tell me if it's not), is this sensible? Or is there something I'm missing?
AI: Measuring the temperature of the heater is not really measuring the temperature of whatever it is you are trying to control. I'm also not sure the Kanthal elements will last all that long if you're operating that close to the maximum but it really depends on the atmosphere they will be exposed to. You also need to find a way to calibrate it (a thermocouple or an optical pyrometer) and 50ppm/°C means you will have trouble with tight control. I think it can be made to work at least for a short time (without my doing a lot of evaluation of your proposed method) but I don't think it will be comparable to a thermocouple controller unless you have a very special need to control the temperature of the heating elements themselves.
A not insignificant problem is that the resistance and the elements themselves will change significantly during use so that your actual controlled temperature will drop continuously as the elements erode away and the resistance increases.
A standard platinum-rhodium thermocouple can easily handle those temperatures (type R or S are most common, and work up to 1450°C). They don't have to be fat like AWG 8 thermocouples, even a fine wire will last a long time, because Pt is very non-reactive ('noble'). The output is quite a bit less than common base-metal thermocouples such as K or N type, but still not a problem for modern electronics. |
H: Is this the correct isolated circuit to control a relay output from a Raspberry Pi GPIO?
I am making a circuit for an optically isolated relay output controlled by a Raspberry Pi GPIO pin.
I am not sure if this is the correct way of doing it. Can someone please help me out on this?
Edit: Modified circuit based on answer from JustMe.
AI: Technically, it will work.
But it does not isolate, because you used the same ground and same 5V supply on both sides of the optoisolator.
So if you wanted to have isolation over the optocoupler between two different supplies and grounds to keep them separate, then the opto is useless and based on that the design is not correct.
Also any off leakage current through optoisolator to Q1 base may turn it on. |
H: Is resistor needed for Flash IC?
I am making my first micro controller board with the rp2040. It requires external flash and so I picked the MT25QL128ABA1EW7 since it seems to match all the requirements based on this document: https://datasheets.raspberrypi.com/rp2040/hardware-design-with-rp2040.pdf#_supported_flash_chips.
However, in the datasheet of the flash IC, there is a two inputs(W#/DQ2) that share a pin: https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qlhs_l_128_aba_0.pdf#unique_10. It says the following for "This signal does not have internal pull-ups, it cannot be left floating and must be driven, even if none of W#/DQ2 function is used".
I plan to use this pin as DQ2 for the QSPI_SD2 pin from the rp2040, but I don't know if I can just connect them directly or if I need a resistor close to the DQ2 pin of the flash chip in order to prevent unwanted behavior. And if the resistor is need, how can I figure out the resistance value because it is not mentioned in the datasheet.
AI: From the datasheet: "... it cannot be left floating and must be driven..."
If you use DQ2 for the QSPI_SD2 pin then it's driven by the SPI hardware interface and you don't need to add any external pull-up resistor.
You must add an external pull-up resistor only if you, for some reason, leave that pin floating. |
H: Is there concept called dual ethernet?
I came across a word called dual ethernet while working on a project and it got me curious like is the word misspelled or is there any real concept on this?
AI: 'Dual ethernet' may well be referring to bonded ethernet.
This is where two physical ethernet cable connections are logically linked to appear so they appear a single logical connection to their host systems. This gives two benefits:
Redundancy. If a cable breaks or becomes disconnected, the other cable can provide the logical connection.
Speed. While both are working, the logical connection has a theoretical speed of twice that of a single physical connection.
You'll find plenty of detail about this on the internet, with this Wikipedia article a good start on the subject. |
H: How can I utilize PSpice for ESD simulation?
Issue: I do not know how to build a ESD simulation model in PSpice Orcad capture.
Question: What is wrong with the simulation circuit? The simulation result seems like the ESD is not discharging properly. Why I cannot see the same response as the simulation result in the reference?
For the second simulation result, I set to close the switch at 5 μs. How come the voltage at C2 behaves as if it is connected to 25 kV before the first 5 μs?
Simulation conditions:
Conform ISO 10605 (voltage range -25 kV to +25 kV, discharge capacitor: 330 pF, discharge resistor: 2000 Ohm)
Simulation time: 20 μs
Switch opens at 0.1 μs
Switch closes at 5 μs
ESD circuit with open switch at T:
Simulation result 1:
ESD circuit with close switch at T:
Simulation result 2:
Reference:
How to choose capacitor voltage rating for ESD protection?
Could anyone give a guidance or feedback?
AI: Switch opens at 0.1 uS
Prior to the switch opening, all the capacitors in your circuit will be fully charged to 25 kV. This is an inevitability of your circuit and, your graph indicates that. After the switch opens, the state of charge of all the capacitors will be exactly the same. This is also as shown in the graph.
Could anyone give a guidance or feedback?
If you are simulating an ESD gun then you should charge C1 (330 pF) with the switch open then, close the switch but, you should also disengage V1 at that very moment to prevent V1 from having any effect. Some point later you should open the switch labelled U1 and restart the process as desired. |
H: Square wave of oscilloscope for RC circuit
I have some ceramic capacitors and would like to know for sure what capacitance they have.
I don't have a multimeter (or any other instrument) that allows me to measure capacitance directly, so I build a simple RC filter that filters a square wave input, I know that the voltage at the output at the time constant R*C is 63% of Vinput ... I reverse the formula and find C.
The question (which is probably stupid) is whether I can use as input the square wave produced by the oscilloscope (is usually used to check before each measurement if the probe is correctly calibrated) .. otherwise I would need a square wave generator :/
After the responses I received, I will upload the photo of the calculations made and ask if they are correct:
(565mV is the V measured with the CH1 probe at the ends of 220 ohms)
EDIT: missing a multiplication by 2 in the equation! With that multiplication, the result is about 560 ohms which is correct because I used a 500ohm + 100ohm series finding about 1Vpp at the output .. which is half of 2Vpp
I tried measuring a 100nF capacitor but obtained 36nF:
AI: That in-scope square wave generator will be fine.
Measure its output resistance, as that will add to the effective value of any series R you are using with your C. Do that by loading it with a resistor. Either do the standard voltage-divider sums, or without calculation, when its output voltage drops to half, the external resistor is equal to the square-wave generator's output impedance. If the output voltage doesn't drop appreciably even with lowish values of loading resistor, then the output impedance is near zero.
IIRC, most oscilloscope calibrators are designed to also deliver a squarewave current into a short circuit, so have a finite output resistance, often 1 kΩ.
If your resistor in your RC is well above 1 kΩ, then you don't need to worry too much about the effect of the calibrator output resistance. Bear in mind though that now the loading resistance of your scope probe now becomes significant, reducing the effective value of the R as it's now in parallel to it. They are typically 1 MΩ on a x1 probe, and 10 MΩ on a x10 probe.
Be aware that many ceramic capacitors, especially ones that have an unusually high value of capacitance for their physical size, have a very large and negative voltage coefficient of capacitance. That means the actual value of C when biassed to 5 V might be less than half of what you measure with a 2 V squarewave.
This voltage coefficient also means that you might not find a consistent time constant for the RC combination versus voltage, as the capacitance is changing as the voltage changes. |
H: Can I use thicker wires or twisted pair for Ethernet?
I'm planning to use 2 types of connectors:
A : GND + 24V + 100Mbps ethernet (4 wires) + 2 wires with various functions
B : 1 Gbps ethernet with PoE (8 wires)
For type B, I found of the shelf connectors meeting my needs (small size + subssea,) but I haven't found any for type A that can handle at least 3A (ideally 5A) while also being rated for use with Ethernet (so I might need to have it custom made.)
Using 2 different connectors, one of which custom made, is quite sub-optimal. Is it possible to reliably do one of the 2 things below:
Use a single custom connector with 4 twisted pairs, with some pairs thick enough to carry 3 or 5A? (Either a single thin pair, or the 2 pairs not used for 100Mbps, or all pairs.) This way, I could use the same custom connector for everything.
Use non-twisted (and thicker) wires for the 100Mb connection, knowing that there will be up to 3 or 5A flowing next to them? Maximum length is 3m. This way, I could use only standard connectors (2 different models.)
NB: Reliability is very important to me. If it can't be done in a reliable way, I'd rather use 1 standard + 1 custom connector rather that take any risk (no security risk, but downtime costs >1k$/day, vs connectors about 200$.)
AI: I wouldn't want to try 100MBit Ethernet over non-twisted wires. If reliability is crucial, use proper cables.
For me, that means that your option 2 is out. Ethernet needs proper cables. 100MBit wiring is less picky than 1GBit, but even so there are limits to what it will accept.
I'd go with standard Ethernet cables and connectors and a separate power cable and connectors. If there's some horribly important reason why two cables are not acceptable, then I'd go with option 1.
There was a building I worked in where they pulled too many Ethernet cables through a slightly too small hole in a concrete foundation. Some of the wires lost their proper twist while being forced through the hole.
The computers on those connections had really poor Ethernet.
A cheap Ethernet cable tester couldn't tell the difference - it said things were fine. It was only checking continuity, though.
A far more expensive cable tester that checked impedance and losses and crosstalk rejected those cables - that agreed with the absolutely crummy network performance of the affected PCs. |
H: Charging li-ion 72V with solar MPPT controller
I have an EV 72V li-ion battery with given charger (peaks at 11 A).
My MPPT solar charger is designed among other types for li-ion up to 96V ie 12/24/36/48/60/72/84/96V settable at 72 V. 50 A max.
Given the amps will vary depending on sunshine it will provide the correct volts but limit the amps based on available sun. (Between 0.0 A to 11 A). And has all the features to vary the amps based on charge state, (float etc). and user defined max of, in my case 11 A.
Given that from time to time the input amps may fall short of the amps a wall unit may provide, my question is this.
Can I use this controller to charge my EV battery pack safely? It has all the protections etc. Essentially the amps may, from time to time, fall short of the 11 A (I'm sure the wall unit too varies amps likewise, based on charge state, averaging around 6 A, lets say.)
AI: Yes, that should work fine.
Just one caveat: Li-ion ion cells degrade while connected to a charger that keeps them at the full voltage. Either shut off the charger when the battery is full. Otherwise, you may want to reduce the max voltage from the charger to the equivalent of 3.4 V / cell for LFP cells or 4.0 V for LCO/NMC cells. |
H: Electrician Theory: Delta Star Induction motor question
This is the question I am trying to solve:
A delta connected fully loaded induction motor draws 90A from a 400V supply when started direct online. Show by calculation the current at start up that the motor would draw when connected to a star delta starter in the star position.
I was under the impression with delta star, that when voltage goes up, current goes down, however here the answer to the question shows that the ratio between delta star is 1.732.
With Delta-Star I understand this to be a ratio of 1.732:1 (Delta:Star) So when the phase voltage gets divided by 1.732 the phase current should be increasing by 1.732 times.
This is the solution given.
Why at the final step of the solution do the say 52/sqrt(3) instead of 52*sqrt(3) as I was under the impression that if the phase voltage goes down (is lower in star than in delta) then the current in star should be higher than in delta?
AI: When the motor is at zero RPM it can be seen as a transformer with the stator as primary winding and the rotor as secondary winding.
The secondary winding is shorted hence the startup current is a short circuit current of that transformer. The short circuit current is proportional to the voltage applied, as it is solely determined by the inductance and resistance of the components.
This is different from a motor running close to its synchronous RPM. Running at exactly synchronous RPM is, to stay with that analogy an open secondary winding of that transformer.
That's where the analogy reaches its limit. Close to synchronous RPM lies the nominal RPM and when loaded the motor runs just below the nominal RPM.
When a load is applied the behaviour of the motor is defined by its resistances and inductances and additionally by the behavior of the load. The load of most machinery has a rather flat curve at nominal RPM in comparison to the curve of the motor.
Lets say the induction motor moves a conveyor belt. If the conveyor belt moves some material horizontally the torque will increase slowly with the RPM. But near the nominal RPM the M-n curve of the motor is extremely steep. The amplitude of the whole M-n curve however is proportional to the voltage.
Consider a flat curve crossing the steep section of the curve. If the voltage is reduced, the operating point moves faintly to a lower RPM and even more faintly the torque will drop. In total the mechanical power delivered by the motor will be almost the same. However, the power must be delivered by the motor. So if the voltage drops significantly the current has to increase reciprocally.
Those effects at 0 RPM and with typical load near nominal RPM shouldn't be confused. |
H: Op-amp schematic connection questions and DC biasing
In the first stage the signal is converted to single-ended, and it is amplified using a digital potentiometer in the second stage to be able to change the gain with a microcontroller.
In the last stage I have converted the signal back to differential again.
Thd ADC range is 0-3.3 V and the max. sampling frequency is 5.6 MHz, or 3.3 MHz will be used.
The reason for the differential input is because it has 6 to 8 dB better SNR performance. The signal frequency range of interest is 1 kHz to 1.5 MHz or so.
If you can answer each question specifically it would be great.
ADA4807 Datasheet
My questions are:
Is this schematic correct in the case of cascade connections and especially the part where the signal converted back to differential again (the last stage)? The gain is adjusted in the second stage, so the first and last stages are just for proper conversion. Please correct any wrong resistance value I selected, if any.
What should be the values of R12 and R14? One reference design uses 1 kΩ, another one uses 10 kΩ. Is it important?
Does R10 (10 kΩ) have to be the same as R13 (1 kΩ)? Another way of asking is, is the value of R10 important in this conversion?
Do I need R9 and R19 before the DC bias voltage connection?
SAR ADC recommends an RC filter at the input for filtering and capacitance recharging, so I have placed 20 Ω and 2.7 nF. Is this correct?
AI: I am answering your question based upon what I believe you are apparently trying to accomplish, rather than what you ask directly.
I believe what you are trying to accomplish is to amplify a differential signal, with a variable gain based upon a single variable resistance. The following circuit will do that job:
simulate this circuit – Schematic created using CircuitLab
R1 and R2 should be precision resistors and have the same value. The differential mode gain will be:
$$A_{V(diff)} = 1 + 2\frac{R1}{R{gain}}$$
You may want to put a fixed resistor in series with the variable resistor to prevent the total resistance going to near 0, and the gain being unreasonably high.
The common mode input voltage is "passed through" this circuit. Thus, if the input signals are centered around 1V, instead of 0V, the output signals will also be centered around 1V. |
H: Screw post or binding post on PCB for lugged gnd wire?
I need to attach these four wires to a PCB I am designing.
The three ferruled wires will be connected through a terminal block. I have space next to the terminal block for the lug but I need a method for connecting the lug to the PCB.
A simple solution is just a plated through hole, connected to ground. I could then bolt the lug directly to the PCB.
I would prefer a binding post of some kind I could solder directly to the PCB and then attach the lug to the binding post.
Does anyone know where I can find a connector like this? I'm coming up empty searching the usual places. I don't know what the correct name for this part would be.
AI: PCB solderable binding posts don't exist.
All-metal PCB solderable screw terminal things do though but unfortunately the names they go by (such as screw terminals) overlaps with terminal blocks so you have to search. Usually a random visual search of images in Mouser or Digikey. These things:
https://www.keyelco.com/category.cfm/keyelco/Screw-Terminals-Terminal-Blocks/id/476 |
H: Differential amplifier op-amp schematic connection and DC biasing
I have a differential IF (intermediate frequency) signal generated by an ADL5801 RF mixer.
Stage 1: the signal is amplified before active filtering and it has LC LPF in the beginning for filtering unwanted frequencies above 2 MHz.
Stage 2: the signal is passed through a Sallen-Key HPF with -40 dB/dec, Fc= 400 KHz.
Stage 3: the signal needs more amplification because of filtering in stage 2. The gain is not fixed. It will be controlled by an MCU with a digital potentiometer.
Stage 3 is suggested in this section as an answer to my other question which simplified the circuit.
ADC range is 0 - 3.3 V and max sampling frequency is 5.6 MHz or 3.3 MHz will be used. Signal frequency range of interest is 1 kHz to 1.5 MHz or so. 1.65 V is generated by an LDO which is stable with 10 μF output capacitance.
My questions are:
Do I need biasing at stage 3 (ADA4807 part of the first schematic)? Is stage 3's design correct in general?
Both the LT6232 and the ADA4807 have a low differential input resistance (7.5 kΩ and 35 kΩ). What resistor values should I select for gain, or do I need another op-amp?
ADA4807 Datasheet
LT6232 Datasheet
ADL5801 Datasheet
AI: Question 1
I don't think you need biasing but, if you plan to use the Digi-pot at anything above audio, the terminal capacitances of the wiper and A/B will become very significant. Have you looked at the capacitances in the data sheet? Why not try simulating stage 3 and see what I mean: -
I believe that the gain is likely to start to increase above audio (around 20 kHz) and become just too high at 1.5 MHz. Digi-pots are very difficult to use at these sorts of frequencies due to internal parasitic capacitances. Also, they have a natural imbalanced capacitance between A/B and wiper that might disturb the balanced signal you are trying to amplify.
Looking at your circuit a bit more reveals that you are using 10 kΩ feedback resistors in the stage 3 op-amps. The effect of this and 120 pF to ground on the wiper means a 3 dB increase in gain at 137 kHz. If this resistor was reduced to 1 kΩ that 3 dB change would occur at 1.37 MHz. You might be able to live with this but, if you can't then you'll just have to keep on lowering it.
But then you might run into op-amp loading problems and, the current into the Digi-pot input might exceed limits. Maybe you can also find a better low-capacitance Digi-pot. It's been a while since I looked so I can't recall what I chose but, my circuit was limited to 100 kHz.
Question 2
A low differential input resistance isn't as bad as what it seems; given that op-amps are used in linear applications, due to the virtual ground effect, both inputs of the op-amp will be at very close to the same voltage hence, the differential current into the op-amp inputs will be quite low. |
H: Undervolting magnetically held switches
I have acquired a Honeywell ET series switch (best datasheet I could find) whose holding coil is rated to run on 28 VDC. I know it is often deployed in aeronautical environments where voltage can drop to near 24 V when operating on battery.
From my testing, the switch seems to hold reliably with voltages as low as 7 V. With such low voltages, the force required to bring the switch to the OFF position without cutting power is much lower.
Up until now, I've considered its coil analogous to the one of a relay. I know most of these really shouldn't be undervolted, but is that only coming from the fact their construction is usually of lower quality and thus wouldn't operate reliably on lower voltages?
Would I need to beware of undervolting this switch to something like 9 V to reduce the force required to turn it off mechanically? What precautions should I take if I go forward with such a design?
This is only for a personal project of mine and wouldn't be deployed at scale so any variance in the manufacturing of different switches is not a factor to me. I can adapt my system to the tolerances of mine if need be.
I find it very hard to find such information on the limits of MIL spec components since they are almost never used by most hobbyists.
AI: Looking at the datasheet, it appears as though the solenoid is only used to hold the internal plunger in the activated position once it has been placed there manually with the switch baton, not to electrically remotely activate the switch, hence the absence of separate "pull-in" and "holding" current ratings. However, the switch is qualified for flight deck use on military aircraft, where the plunger must not move under extreme shock or vibration conditions so the holding force is probably far in excess of what you'd need to hold it in under "normal" use.
For casual, non-critical use, I'd do a few tests (let the coil warm up) to see where it drops out and then give yourself a healthy margin (25-50%) between the highest measured voltage and 28V.
Or you could try emailing Honeywell. I've had long, involved conversations with TDK-Lambda engineers about products that cost less than one of those switches. |
H: What is the function of CCM1 and CCM2 in this resistive bridge measurement circuit?
The circuit below can be found on page 59 of the ADS122C04 chip datasheet. The purpose is to take the differential input of two voltages from a resistive bridge. For example, I am using it to collect data from a load cell. I understand the point of CDIF1, which is to mirror noise from one signal to the other so that the differential input is not affected by said noise. I also understand the point of RF1 and RF2, which would be to allow the capacitor to do its job just as any RC circuit functions. What I don't understand is what the point of CCM1 and CCM2 are. I would have thought they were there to filter out noise, but isn't that what CDIF1 is for? Are they redundancy layers for each other, any noise that isn't filtered to ground gets mirrored to the other signal, and vice versa?
AI: There's two components of noise at play, both of which are worth trying to mitigate:
one is the noise in the differential measurement across the bridge
the other is the noise seen symmetrically on both sides of the bridge
The chip is intended to perform a differential measurement, and represent the difference between the two inputs as its output, so at first glance it seems that the common-mode noise should be ignored. However, this common-mode rejection is not perfect, and is characterized a specification known as "common-mode rejection ratio" (CMRR). At quick glance, I wasn't able to find a CMRR-vs-frequency plot in the datasheet(^), but often, CMRR gets worse with increasing frequency.
The names of the capacitors provide a key clue as well: C_DIF (for differential) vs C_CM (for Common Mode). The two CM capacitors are placed symmetrically on the two lines to ground, thus symmetrically attenuating common-mode components of any high-frequency noise.
Meanwhile, C_dif will not attenuate the common-mode component to any appreciable extent; since the common-mode noise is seen equally on both terminals, no high-frequency current flows through C_dif in response.
As the datasheet points out, the two capacitors (and likewise the two upstream series resistors) ought to be well-matched, as their mismatch will convert common-mode noise into differential noise (which then gets measured directly by the chip if not well-attenuated by C_dif).
I understand the point of CDIF1, which is to mirror noise from one signal to the other
Not quite. It doesn't "mirror" noise from one to the other (in the sense of turning DM noise into CM noise), but rather it shunts that noise away by allowing current to pass at high frequencies in response to differential voltages, which creates a low-pass filter structure
^ CMRR is given in plots on page 14 and the table on page 8. The provided spec seems to only discuss CMRR at DC and for 50/60 Hz (likely expected powerline noise).
^^ A mechanical analogy for CMRR, for readers that prefer an intuitive visualization: Imagine measuring an object with a ruler while on a bumpy train ride; while all of the motion is common-mode (both ends of the object move together), you'll still have a difficult time with yourself, your workpiece, and the floor thrashing about. |
H: Is it safe to remove this LED from that motherboard?
So, I've bought this SATA case from internet but it has a really bright light on it and annoys me. I don't haver any kind of tool to manage any electronic component, and neither have electrical tape to hide this light, so I would like to know if it is safe and it will continue working if I remove it with a knife or something like that (touching only the light, ofc)
I want to remove the LED2.
AI: Take a black Sharpie and apply some physical dimming to the led. it may take several applications.
Other brands of permanent marker will also work. the ink is non-conductive and will not alter the electrical perfomance of the circuit.
Removing the LED will probably work and not compromise the performance of the circuit, but there is an increased risk especially if you're a klutz like me. |
H: Positionally aware 360° (or beyond) motor (DC or stepper)?
Most servo motors out there are driven within 180° (at least hobby ones). There are more bulky and expensive servos out there as well. Since, I have tight space constraints, I am looking for a solution to have full positional awareness (0-360°), an can even cross 360° boundary for shortest path rotation.
e.g. from 350° to 10° in 20° step and not with a 340° backwards rotation.
The servo modifications, which I have found remove positional awareness for continuous drive. I have been wondering, what solutions are common out there? I remember taking apart an inkjet printer to find a transparent disk attached to the motor with black stripes for opto-interrupt encoding. I guess, this would be solution. I might as well use a geared DC motor or a stepper motor for this purpose.
I was wondering, what solutions are commonly used for this purpose. I will have an IC to do the controlling but more plug and play solutions are welcome.
AI: The "servo" you are describing is a hobby "servo-actuator" with its origins in the RC model aircraft, etc., hobbies.
servo /ˈsəːvəʊ/
noun
short for servomechanism or servomotor.
"the servos should faithfully follow the input commands"
relating to or involving a servomechanism.
modifier noun: servo
"hydraulic and electrical servo systems"
Source: https://languages.oup.com/google-dictionary-en.
Most industrial servo motors and actuators will use a rotary encoder to track position. These are available in two types:
Incremental: These just need two sensors looking at an encoder disk with radial stripes as you described in your question. The servo controller keeps track of the position and adjusts the drive to the motor to move the actuator to the target position (or velocity). If necessary, a homing sequence is run on power up or reset to give a zero reference to the position counter after which the controller can keep track until the next power cycle.
Absolute: These have a more complex coding pattern and allow the controller to read the current position on power-up without a homing sequence. There are also multi-turn versions which use a variety of techniques to keep track of how many turns have been used.
Stepper motors may be an option for you. They generally run without encoders and this is fine for many applications where stalling is unlikely. The motor is referenced on power-up and then its position is determined by the number of pulses sent to the driver. Resolution is typically 200 steps per revolution.
It sounds as though you're looking for a BLDC (brushless DC servomotor) of suitable power and matching controller. |
H: Simple TTL: Is there a way to "detect" a high-z state and easily use that to drive other logic?
I have two TTL style logic chips, call them A and B (*), where the outputs of A are the inputs to B (think: 8 data lines). A has tri-state outputs, so when they are turned off they float. B is an inverting buffer which also offers tri-state outputs (if you toggle off its chip enable)
What I'd ideally like to do is "detect" the high-z state seen at the A outputs and use that state to disable the chip enable for B (thus causing it to go to hi-z on its outputs). This is because, otherwise, when the output of A is floating and "meaningless", the output of B is also meaningless, but will be driven and not predictable.
A is an interface chip that goes into high-z outputs based on internal state, so there's no trivial enable line to A that I can simply also use for B.
I'm a still-learning hobbyist here. This question suggests that using a voltage divider on an output from A can result in three well-known states, which could be used to do other stuff. I'm not sure exactly how, or what would be involved in that? Could someone offer a thought on how they might think about achieving this?
(The backup plan, which seems less elegant, is simply to use pull-ups or downs on all of the inputs to B so that B's outputs may be always-on but are always predictable.)
(*) A is a 6820 PIA and B is a 74LS240, but I don't think that's critical to the question.
AI: It should be sufficient to watch just one of the outputs of the 6820 to detect the high impedance state of the output driver.
simulate this circuit – Schematic created using CircuitLab
The series resistor ladder R1-R4 sets half of the supply voltage at V_BUS for the high impedance state. In this state none of the MOSFETs is conducting, Vgs is below the threshold. NOE_B is high and so the output driver of the 74LS240 is disabled.
The resistor values are relative low to ensure fast switching of the MOSFETs. Higher values may be acceptable if the circuit deals only with slow I/O signal changes. This was not specified.
The switches SW1 and SW2 represent the tri-state buffers of the ICs.
If NOE_A is low, V_BUS is either high, which turns M2 on, or it is low, which turns M1 on. If M1 is conducting this also turns M2 on via R8, so M2 is always conducting if V_BUS is not in the high impedance state. This reconstructs the original NOE_A signal with around 200 ns delay at NOE_B.
R9 just emulates the estimated output driver strength of the 6820.
R6 and R7 are added to show the high impedance state of the 74240 in the simulator, so V_BUS and OUT_B can be compared in the diagram.
There is a very short glitch in V_G during a high/low level change of V_BUS, but this does not reach NOE_B. |
H: Gate driver selection for digitally controlled via PFM, LLC resonant half bridge charger
I am designing a LLC half bridge charger. I am going to use a microcontroller to control the switching frequency, with feedback from the output to smoothly control the switching requency.
I don't understand how can I control the MOSFET's switching cycle with control input of gate drivers. In the market there is a resonant driver but I don't understand how to control it digitally with, for example, an FAN7621.
AI: I don't understand how can I control the MOSFET's switching cycle with control input of gate drivers. In the market there is a resonant driver but I don't understand how to control it digitally with, for example, an FAN7621.
FAN7621 is not what you are looking for. You can't control it digitally as it's an analog controller which has everything internally.
What you need is a combined high- and low-side driver, not a controller. There are many gate drive ICs in the market. IR2112 is one of them, though I don't recommend it.
These ICs generally use bootstrapping to drive the high-side switch, so make sure the IC's bridge node (generally named as VS node) voltage rating is higher than your maximum DC input voltage. For example, IR2112's VS node rating is 600V, and if your max DC input voltage is 450V then it's suitable.
For LLC HB converter the dead time is important, especially for ZVS (zero voltage switching), overall efficiency and general operation. So make sure the IC you select does NOT generate a fixed dead time or if it does it should match your needs. Ideally, it should be under your control for maximum performance.
You may also want a high peak drive current capability (generally around 1 A) for simplicity. Although the turn on time is not important in an LLC so a relatively high gate stopper resistor (which means lower peak gate drive current) generally works, the turn off time is important. So if you don't want external transistors (i.e. totem pole or push-pull) it's better to choose an IC with high peak current capability.
Another options are:
Drive the low-side switch directly and the high-side with a dedicated high-side driver.
Use gate drive transformers. |
H: Why do the metal sticks (for the ground) on the ground plane antenna reflect and not absorb?
From my current knowledge, any metal whether grounded (and or earthed) or not will reflect radio waves as seen on dishes, Faraday cages, etc. On the other side the ground in transmission lines or the ground planes in PCB, I see more as a place where the fields are absorbed, as the energy travels between the two. It’s always constantly stated to have proper grounding for high speed signals.
All in all it seems in different scenarios, metal absorbs the fields, and other times reflects/guides the fields.
What is the main reason for this?
I am assuming it is to do with the impedance seen to the metal, for instance a Faraday cage or ground plane for antennas is certainly not seen as the impedance of the propagating waves, but that's only my limited knowledge understanding.
Which brings on to the actual question: Why would the wires acting as the ground plane on those monopole ground plane antennas be reflecting the signal, when they are directly connected to the coax shield?
AI: Taking example of the ground plane antenna, consider the case with a monopole, perpendicular to multiple ground spokes in a plane:
Suppose we have a feedpoint voltage Vs (and more generally a port, with feedline and incident and reflected waves, not shown).
Within a certain degree of symmetry, we can consider each ground spoke as its own monopole with respect to the rest.
Notice the geometric symmetry is not perfect, because the remaining spokes and the monopole element (considering Vs = 0 by superposition) do not form a plane perpendicular to the spoke in question, whereas they do for the monopole. This moderately affects the characteristic impedance of the element in question, but does not change the overall argument.
Considering a spoke as a driven element, like any other element, it exhibits a characteristic impedance, looking into its feedpoint. In normal use, that feedpoint is connected to an approximate short circuit -- Rg being a small value. But "approximate" is not "perfect". The element has some resistance along its length, which for reasons not important to go into here, can be represented as an equivalent total resistance at the base, and the rest of the element assumed ideal.
Given the symmetry (and limitations as noted), the characteristic impedance of the spoke as an element, will be comparable to the monopole element itself, typically 30-40Ω. We can understand the effect of Rg, when it is small in relation to this impedance, as the reflection coefficient at that port.
The reflection coefficient is given by,
$$ \Gamma = \frac{Z_L - Z_0}{Z_L + Z_0} $$
For \$Z_0 = 40\,\Omega\$ and say \$Z_L = R_g = 0.1\,\Omega\$, we have \$\Gamma = 0.995\ldots\$, quite high but not exactly one.
So, we have some energy absorbed in the element, but most of the incident energy is reflected in phase.
Important take-away: real situations are always both absorption and reflection simultaneously. (Or transmission, if applicable.) How much of each, is the question. Real in-practice ground planes, wires, shields, waveguides, etc. act as guides or mirrors to incident waves, usually to quite a good degree (a mirror below 90% reflectivity might be considered poor even at optical frequencies, and over 99% is typical at radio frequencies). But we must keep in mind there is always absorption in that small remainder below 100%.
We also have high reflectance for \$\Gamma \rightarrow -1\$. What would that do?
We could connect the element(s) open-circuit, which gives this condition. The meaning of negative Γ is that waves reflect in opposing phase. What does this do to the monopole-with-ground-plane antenna? Well, the reflected waves would oppose the driven element's waves, and... nothing happens. Which is as we expect: Vs would be essentially open-circuit on one side (all Rg's infinite), so feedline current cannot flow. |
H: Can you detect when an incrementing counter has reached N by AND'ing the expected set bits?
With a incrementing counter, starting from zero, I can tell when 128 is reached by looking for a positive edge on bit:7.
I can detect when 129 is reached by looking for a positive edge on (bit:7 & bit:0)
I think that I can detect when 130 is reached by looking for a positive edge on (bit:7 & bit:1)
Can I AND all the expected set bits together to detect when an incrementing counter reaches a expected value? This will be used to reset the counter.
AI: Yes, this always works! The value you're checking for is the first one for which the AND gate will output a 1. This means that the AND gate detects when the counter first passes the expected value, and after that, it may or may not output additional pulses (which your circuitry will likely ignore).
It's really easy to prove why, too: If any of the other bits is set that you're not checking for, the value of the counter is already larger than the value you're expecting. So any value with additional bits set is not the first one which the AND gate detects.
For example, the value 130 is 1000'0010 in binary. If you AND only the two set bits in that value (bit #7 and bit #1), the AND gate will output a 1 for any value of the form "1xxx'xx1x". 130 is the smallest one of them (all of the x = 0), so it's the first one for which the AND gate will output a 1. Since the counter counts up starting at a value smaller than 130, you know that 130 is reached when the AND gate outputs a 1 for the first time.
This works regardless of the width of the counter and the value you're checking. It even works for down-counters if you check the cleared bits (0) instead of the set bits (1).
As Neil_UK mentioned in the comments, there might of course be glitches in the AND gate's output value when the counter switches from one value to the next, just like there might be glitches in the counter's output value itself. Ideally, the circuitry downstream from the AND gate should be synchronous logic clocked from the same clock as the counter, or otherwise qualified on that clock signal. Asynchronous logic might cause issues, as usual. This issue is, however, independent of the technique used to detect the desired counter value. |
H: Differential output resistance with LTSpice
I have a simple NMOS FET where I would like to plot the differential output resistance at the operating point of Vgs = 1.7V (which is the Vgs voltage for Id=9.4mA)
I managed to plot the output resistance with the help of the behavioural source B1 as follows:
I can read from the difference of cursors 1 and 2 in the plot that the differential resistance should be about 2386 Ohms at Vgs ~= 1.7V.
Main question: How can I get a plot of this differential resistance? Is there for example a way to plot the derivative of a trace in LTSpice?
Bonus question: How could I plot the small signal gain of this amplifier?
AI: As proposed by @Ste Kulov, waveform arithmetic is exactly what I was looking for. I took the derivative function d(V(out)/Id(M1)).
Concerning the small signal gain, this can be done by right-click on V1, specify a (small) AC amplitude like 0.01V and change the simulation command to .ac and desired frequency range. |
H: Voltage divider for symmetrical DC power
Let's imagine there is a symmetrical DC power supply +10V and -10V and two resistors, R1=10k and R2=100k. What is the voltage in point A? What is the correct formula for this kind of calculation?
AI: The voltage between two points is called a potential difference. In most cases, the potential difference between two points is well defined. When one speaks of the voltage at a single point, one usually means the potential difference between that point, and some point that is arbitrarily defined as 0 volts. We call this point ground. (Unfortunately, the word "ground" also has other meanings). We add a ground symbol to a schematic to identify the node that we have arbitrarily chosen to be the O V reference. If a schematic lacks a ground symbol, a reference to "the voltage" at a single point is likely not well defined.
However, in your schematic, there is a node that is labelled +10V, and this node can serve a similar purpose in providing a reference.
The total resistance of the circuit is 110 k\$\Omega\$. The total voltage across those resistors is 20 V. Thus the current through them is 20/11k. When that current passes through the 10 k resistor, a voltage of 10k*20/110k = 1.818 V will devop across it. Since one end of the 10 k resistor is at 10 V, node A will be at 10-1.818=8.182 V. |
H: Is it safe to connect a µUSB bus to another voltage bus?
If I connect my µUSB bus to the other 5V bus what are the consequences?
What can I put in place to make it safe?
The µUSB would be plugged in while the circuit is active to reach a µC by default.
The other two states are that 5V will be off and 5V will not physically be present because it will be disconnected from the other PCB.
AI: "Or" the supplies together, or shut down the 5V supply if the USB is plugged in.
Here is and example of how to share power supplies
OR-ing power supplies (diode or mosfet)
If you aren't going to use the power from VBUS on usb then don't connect it at all (you may need to connect it to the a processor or IC for VBUS detection)
If I connect my µUSB bus to the other 5V bus what are the
consequences?
If there are any differences in voltage between the supplies then one will feed the other, take for example if VBUS on usb is 4.9V and the +5V rail is 5.01V. You will get an indeterminate amount of current transfering from one to the other dependent on the series resistance of the line and the supplies. Sometimes they even out, sometimes they don't, its anybody's guess. So the best thing to do is use a power sharing scheme or just not use VBUS. |
H: DC/DC step-down converters: what trade-offs prevent lower minimal input voltages?
I'm currently looking into isolated step-down DC/DC converters, to convert from high voltages (a few hundreds volts) to 24 V.
I'm surprised that the minimum input voltage is often quite high (like 200 V for a 300 V nominal input voltage (example)).
When the input voltage is close to the output voltage, I understand that keeping a few volts of difference makes things far easier.
But I'm wondering : what tradeoffs can explain why most DC/DC converters with 300 V nominal input have a lower input limit >150 V?
I'm referring to switching power supplies, in the 500-2000 W range. For the topology, I haven't looked at those in detail yet for this kind of power (and manufacturers often don't specify it), so whatever classical topology in this power range is interesting.
AI: I'm currently looking into isolated step-down DC/DC converters, to convert from high voltages (a few hundreds volts) to 24 V.
Apart from some exotic exceptions, all these DC-DC converters use transformers that provide both isolation and a good efficiency at high step-down ratio. There are many different topologies: flyback, push-pull, resonant... In the case of flyback, the transformer is used as coupled inductor.
But there's always a primary winding, a secondary winding, and therefore there is a turns ratio between primary and secondary. This turns ratio will usually be optimized for best efficiency at the nominal input and output voltage ratios.
Therefore, the further away you get from this nominal ratio, the worse it gets. In fact, it's already pretty good to get a 1:2 input voltage range with a transformer that has a fixed turns ratio.
There are other factors too: at constant output power, input power is inverse proportional to input voltage. As input voltage gets lower, more current is needed to provide the same power. Extending the input voltage range down will require switching devices capable of higher current, larger dies, with more capacitance, and more switching losses. Also it needs thicker wire in the primary, which costs more and makes the transformer bulkier. If the application does not require it, there's no reason to incur the extra costs and loss of efficiency.
The usual "universal wall wart" supplies with 85-240V AC input generally use flyback topologies, which offer a wider voltage range at a low cost, but at the expense of higher losses. It's okay for a low power converter, but at 500W there are much better options.
For high power AC-DC converters with "universal input" you'll usually get a boost power factor correction stage or a capacitive voltage doubler, which compresses the allowed input voltage range into a much narrower DC bus voltage range, followed by a resonant converter which allows very high efficiency. So the actual isolated DC-DC converter in these supplies does not have to handle the full input range.
When the input voltage is close to the output voltage, I understand that keeping a few volts of difference makes things far easier.
This would apply to a buck converter, which is a non-isolated topology using an inductor. It's a completely different topology from a transformer-isolated converter. |
H: Connecting 25MHz crystal to STM32H7
I want to connect a 25MHz crystal to STM32H750. However, I've trouble finding a part which is suitable for use with this particular MCU.
From AN2867:
In addition:
The gm for STM32H750 is 1.5 mA/V (datasheet). This means that in order to meet the recommendation, the crystal has to have gmcrit equal to or lower than 0.3 mA/V.
The only crystals which come close to this recommendation are the ones in bigger packages and with low load capacitance (The best one I've been able to find has gmcrit of 0.478 mA/v). So, I have few questions:
How much should I be worried about the gain margin > 5 recommendation?
My circuit will be exposed to EMI from relays and contactors. Which parameters of a crystal are the most important for stability in this case?
The 25MHz crystal is not a strict requirement - I wanted to use HSE as source for the Master Clock Output for a Ethernet PHY. Should I just opt in for a lower frequency crystal and use a different source for the MCO instead?
AI: The MCO output does not depend on your crystal, so there is no real reason to want a 25 MHz crystal even if you want a 25 MHz output.
However, if the MCO output comes from a PLL, it might be a problem. This configuration was specifically not recommended on STM32F2 due to jitter.
If you really want a single 25 MHz clock source for both, why bother with a crystal, if you can buy a 25 MHz crystal oscillator module and feed the 25 MHz square wave to both devices. The problem anyway is routing 25 MHz clocks properly between the chips.
Or, it may be cheaper to get a 25 MHz crystal for the Ethernet PHY and separate crystal for STM32.
I forgot the answers:
Somewhat worried. Depends a bit who you ask. 3 to 5 might be acceptable or not safe. 5 to 10 is just safe or very safe. Sometimes above 10 is very safe. ST themselves say 5 is minimum to ensure proper operation and if margin is less than 5 you should change the crystal. They know their own MCUs and their internal oscillator circuitry best.
I don't know if crystal parameters matter much. Crystal circuits are very sensitive so any EMI is bad. I think what affects more is proper PCB layout than any of the crystal parameters. Refer to STM32 hardware design guides for crystal layout guidelines.
Based on what I wrote above, likely yes. |
H: Usability of COB LED filaments as replacement for traditional filaments
COB LED filament household lightbulbs are a thing now. Can someone explain to me what limitations there are to using these COB filaments in car headlights? They emit a very similar light pattern if you preserve the geometry and glass shape. I believe there must be a reason why manufacturers kept clear of this approach for the past 10 years.
AI: A car headlight requires about 1000-3000 lumens.
With LED lumen efficacy in the 100-200 lm/W, this means 10-30W electrical power.
This means 7-20W dissipation in the LED that must be evacuated to outside air.
An object the size of a headlamp filament needs to be at extremely high temperatures to be able to transfer this amount of heat through the gas in the bulb envelope.
The filament is about the same size as a 1/4W resistor, and the resistor will usually reach this dissipation around 125°C which is too high for LEDs.
LEDs are limited to low temperatures, and best used under 80°C, so there is absolutely no way to have a LED this powerful in free air. It has to be on a rather chunky heat sink.
This is why all LED retrofit bulbs look like this:
The alternative is to have a headlight that does not use a bulb, in this case the LEDs, heatsink and optics can be designed as a whole. |
H: IPC 7251 annular ring meaning
When looking at IPC-7251 Table 3-3 (see the table in Sergei Gorbikov's answer at How to determine annular ring width for thru-hole pads?), for a through-hole pad in Level B the annular ring is given as 0.35mm. Is that the actual annular ring width or the total width to add to the hole size?
What I mean is suppose you have a 0.4mm diameter hole, would you have a 0.75mm diameter pad or a 1.1mm diameter one?
AI: Annular ring is the width of the ring. So for a 0.35mm minimum annular ring the hole is no more than 0.7mm smaller diameter than the pad diameter.
There seem to be some differences whether "minimum annular ring" should account for misalignment of the holes, and whether the drilled hole size or the finished hole size should be used.
PCB manufacturers generally accept a minimum annular ring which assumes perfect hole alignment and using finished hole size, in my experience.
IPC has a definition of minimum annular ring that includes all the factors, so it does not necessarily correspond to what you would set as a DRC limit in an EDA program. In other words they are referring to the minimum ring you would actually measure under a microscope with misalignment and other manufacturing tolerances and not the nominal difference between hole and pad radius.
According to IPC, for Level B there is a 0.25mm fabrication allowance for 1oz or less copper thickness and 8 or fewer layers.
So according to IPC, the minimum pad diameter for external layers is the maximum diameter of the finished hole plus double the minimum annular ring (including etch back allowance) plus the fabrication allowance. For internal layers, the same numbers are used but the maximum drill diameter is used.
The fabrication allowance increases for more than 8 layers, and for heavier copper. See IPC-2221A.
Refer to the actual standards if the slight differences are important. |
H: Alternative to pull-up resistor
I am building this AND gate, and I managed to get it to work properly. However, I had to increase the value of the pull-up resistor to 3 megohms which is too big for what I need. However if I don't make this value big enough, when my input is (0, 0) for example, I won't get an output signal < 0.5 V.
How can I ensure that (0,0) (0,1) (1,0) < 0.5V and that (1,1) > 4V. Thank you in advance.
AI: What you are seeing is the forward voltage drop of D11 or D21 when either is low. This follows an exponential curve and is typically 0.6 to 0.7 V at moderate currents.
As you have found, you can reduce the output voltage by limiting the current but at the expense of other characteristics. (You've limited it to something in the order of 1 μA.)
We generally don't use simple diode logic for pure logic circuits although it can be a handy trick when logic gates aren't available or the voltage / power requirement is higher than standard logic gates can handle.
Beware of the tutorials that suggest two NPN transistors in series to create an AND gate. They have several problems. |
H: Using an op-amp to produce a low-current voltage rail
I'm working on a CubeSat project and I need to produce a 3.3 V voltage rail for an ADC (ADC128S102). The ADC only needs 3 mA total when in active mode. I'm selectively upgrading the most critical parts on the bus to versions that are radiation tolerant/hardened.
I have a +5 V rail and I want to avoid buying another voltage regulator just to produce this 3.3 V line if I can. I have an unused op-amp (OPA4H199-SEP) that I think I could use to produce a 3.3 V line for the ADC. This 3.3 V is only used for the digital signals reference, not the analog reference voltage itself.
The ADC needs 0.1 μF + 1 μF of decoupling on the digital line and I simulated the op-amp feeding these capacitors and it looks like an isolation resistor of 100 Ω makes the op-amp stable.
If the ADC drew its maximum rated current from this supply constantly, the voltage would drop to 3.0 V on the digital input of the ADC. This is still within the operating conditions of the part and seems like it would still produce valid logic levels for an MCU to read.
Is there any reason that this wouldn't work in practice or wouldn't behave like I've simulated? I know op-amps could be used to drive the base/gate of a transistor to produce a linear regulator, but based on everything here, it looks like I can get away with just using the op-amp to drive it directly.
The circuit would probably look something like this (with the +5 V line replaced with a +10 V line):
simulate this circuit – Schematic created using CircuitLab
AI: Here's a fragment snipped from the schematic of an actual spaceflight instrument (NICER), using an opamp as a low current voltage regulator. Basically take DC feedback from the the output RC, but leading AC from inside it. The C8*R18 time constant should be a few times the C16*R17 time constant for good stability. |
H: How can there be no Thévenin voltage with only a dependent voltage source?
I don't understand why the Thévenin equivalent is equal to zero in this case because, if the load is a resistance, then yes, the circuit would be dead as there would be no voltage drop across Vx. But if there is a voltage or current source in the load section then the circuit would have power (not dead) and therefore there'd be a voltage drop across Vx, so the dependent source would have a voltage produced over it, therefore negating the fact that Vth is equal to 0 in this case.
My question is: Why is there no Thévenin source if there are cases when the dependent source would have voltage over it.
Update: point B is the lower wire point.
The circuit is equivalent to only a resistor, no Thevenin voltage equivalent.
Edit: I don't know what more detail to add, I just want to know why if there is a voltage source in the load circuit between points A and B, then wouldn't that case a current through the resistor Vx? Therefore, that would active the dependent source and Vth would no longer be 0.
AI: The circuit is composed only of linear components - impedances and a linear dependent voltage source. Hence the overall circuit is linear. From the linearity of the circuit, it follows that the voltage across the A-B terminal (and likewise the current) is a linear function of the (only) excitation, the voltage source externally attached to the port.
This implies two key things:
First, if there is no external excitation, the voltage and current at the port are 0. This should make intuitive sense - the voltage from the dependent source is proportional to some excitation, but there is not excitation to drive the dependent source to produce its own nonzero voltage and current. Thus, the Thevenin voltage is zero.
Second, because the circuit is linear, the voltage and current at the port are related proportionally. This means that the circuit's behavior is still representable as a Thevenin impedance. Given the active source, it's plausible that the effective impedance need not necessarily be positive -it could be zero, infinite, or negative depending on the exact topology, and the circuit must be solved to find its value.
But, if there is a voltage or current source in the load section then the circuit would have power (not dead) and therefore there'd be a voltage drop across Vx so, the dependent source would have a voltage produced over it therefore negating the fact that Vth is equal to 0 in this case.
There is no contradiction here. The voltage drop and current are adequately represented by the Thevenin impedance component of the Thevenin equivalent. In the end, the Thevenin equivalent is an affine relationship of the form
$$ V_x = V_{th} + I_x R_{th} $$
with the exact form and sign depending on the sign convention you choose, and the proportional relationship between e.g. an applied current and the voltage seen at the port is perfectly represented by that impedance term, even if it's physically realized by some kind of active circuit rather than just a network of resistors. |
H: How do P-type transistors conduct current?
Going through a Introduction to Computing Systems by Yale N. Patt and Sanjay J. Patel and currently reading a chapter on MOS transistors. From what I understand, N-type transistors "close" a circuit when supplied with current and break it if absent. P-type transistors act in the opposite way. When supplied with current then it closes the circuit and breaks if present.
Now according to the textbook regarding the image below, "...if both A and B are supplied with 0 volts, the two P-type transistors conduct, and the output C is connected to 1.2 volts."
What I don't understand is where the 1.2 volts is coming from if input A and B are supplied with 0 volts? Based on the quote, I would assume that the power supply is coming from A and B but the only alternative I could think is that it is coming from the area indicated in red and that A and B are sort of like a light switch dictating the behaviour of the transistors
AI: MOSFETs are controlled by their gate-to-source voltage, called Vgs. No current flows through the 'input' (gate). Rather, current flows through the other two terminals, called source and drain.
In typical CMOS logic, the n-FET sources is tied to GND, while the p-FET sources are tied to the supply (often called Vdd or Vcc).
Where does the logic-high voltage come from? Vdd is the logic voltage, which could be 5V, 3.3V, or some lower voltage such as 1.2V as mentioned in your example. Again, in your example, this logic-high power supply is connected to the top p-FET, as shown by your red arrow.
How do you get a logic high? When both p-FETs are on, the output is connected to power supply through both FETs in series.
On the low side, GND, or logic low, is supplied through the n-FETs. When either FET is on, the output is connected to GND.
Now, back to that gate-to-source voltage and what it does to the FETs:
n-FET is 'on' when gate-source (Vgs) is positive, or logic '1'
p-FET is 'on' when gate-source (Vgs) is negative, or logic '0'
If you work out the diagram and how the FETs behave, you can see 4 cases:
A, B = 0, 0 => both p-FETs are 'on', n-FETs are off => output is HIGH
A, B = 0, 1 => one p-FET is 'on', one n-FET is on => output is LOW
A, B = 1, 0 => other p-FET is 'on', other n-FET is on => output is LOW
A, B = 1, 1 => both p-FETs are 'off', both n-FETs are on => output is LOW
So what you have is a NOR gate. Try one out (simulate it here): |
H: Is this relay circuit valid?
This is my current circuit draft
Which had the SPST-NO symbol adapted from the supplier's symbol
I have not chosen any specific parts for diode, resistor or transistor.
ALDP105W Relay datasheet: here
I am new to circuitry and PCB design, I was wondering if anyone could help me:
Spot any issues or areas for concern
Suggest some simple specs that I should look out for when buying a diode and transistor.
Thank you
EDIT:
The GND error flag seems to be invalid. I just have it connected to a screw terminal with a PWR_FLAG and the default KiCad NPN symbol as the emitter as Open Emitter
AI: The circuit looks fine. A 2N3904 or other general purpose NPN would work since the coil current is 40mA at 5V which is pretty undemanding. Aim for a base current of 4mA with a Vbe of 0.95V for a 2N3904 or whatever your transistor's Vbe(sat) is, which gives you a base resistor of ~500 ohms. 510 or 470 would both work. For the diode, you want something that can handle at least the same current as the relay coil with at least the same reverse voltage rating, and fast. It shouldn't be hard to find a Schottky diode with these specs. |
H: NAND-based bistable with momentary switch
I want to create a circuit that has two outputs, and two states, where the outputs are either "on, off" or "off, on". The state should be switchable using a momentary SPST switch.
I am using two inverters from a CD40106.
Here is the current circuit:
Here, VCC is 9V (the cd40106 is powered by VCC). The unused inverters have their inputs tied to ground, and the unused outputs are floating. I used two LEDs to test the "on" and "off" states.
I built this on a breadboard, using red LEDs. The circuit worked as expected: on power-up, one of the LEDs was lit, the other dark. Pressing the switch caused the dark LED to light up, and the light LED to go dark.
Question 1:
I swapped one of the red LEDs for a blue LED. Now, the blue LED never goes fully dark: it's fully on when the red LED is off, but when the red LED is on, the blue is just a little bit on.
Using this schematic, assume D2 is the blue LED: even if I jumper Q2's gate to ground, the blue LED is still slightly dim.
If I completely remove Q2, D2 goes dark.
I also tried using a diode to connect Q2's gate to ground, with the anode to the gate and cathode to ground: this actually creates a negative voltage at Q2's gate (per my DMM). D2 still never goes completely dark.
I tried changing the pull-up resistors (R10, R10) to pull-down resistors (i.e. having them go to ground rather than VCC). D2 still not completely dark.
Question 2:
Are the pull-up resistors (R10, R11) actually necessary? I basically copied this circuit from this discussion post, where it is suggested to use the pull-up resistors, but doesn't say why. I've seen countless other variations of this circuit posted in various places on the internet, and don't see them using pull-up (or pull-down) resistors.
AI: You shouldn't need Pull-up resistors for those invertors - pull-up resistors are only necessary when you have open-collector outputs. These do not.
If the LED is still on when you short the gate to ground, that means your transistor is destroyed or highly leaky. Try swapping the transistor with either the one that you know works in the circuit or a new one. Also try swapping the position of the Red and Blue LEDs to see if the behavior is the same. If the red LED exhibits the same behavior, it is definitely the transistor. Of course, try swapping the LEDs BEFORE you introduce new transistors into the circuit.
If the blue LED is still behaving the same after being installed in the "known good red LED" side, then it is almost entirely due to leakage - it only takes a few uA to get an LED to glow brightly. The red LED could have the same issue as the blue one, but you just can't perceive it because it has worse luminous efficiency. As a kludge, you can try putting a relatively high (~47k?) resistor across the blue LED to ensure that it stays off even with some leakage. I don't personally like this solution - it's bad design and you shouldn't have to do this. But given the nature of this circuit, it's obviously not that critical. So if it works for your application, it works!
Putting the diode from gate to ground isn't causing any negative voltage; it's not real - you are either measuring wrong or this could be related to the already mentioned leakage issue.
One unlikely reason that you could be having, that I will include for completeness, is that the transistor is acting as an antennae and picking up and rectifying a nearby EMI source. This phenomenon would also explain why you are reading negative voltage on you DMM - it too may be affected by local interference. |
H: Avoiding overshoot in step response for robustness
In Systematic Design of Analog CMOS Circuits (Jespsers, Murmann) page 343, the following is stated in the context of where to place the non-dominant pole in a second-order loop transfer function of a switched-capacitor amplifier:
The case of ωp2/ωu1 = 4 (Q = 0.5) results in a critically damped step response. This corresponds to the fastest possible settling without overshoot [7] and is the preferred choice for SC [switched capacitor] circuits that are designed for maximum speed. Designing for ωp2/ωu1 < 4 is not recommended to avoid overshoot, which is difficult to manage if the goal is to create a robust design.
The emphasis is mine, and also see the figure below if helpful. Note that the reference [7] in the quote is this paper. (I don't think this paper addresses my question, below).
My questions are:
Why is overshoot "difficult to manage" in a "robust" design?
What are the main problems that overshoot could cause? The above quote comes from the context of switched-capacitor circuits, so that may be relevant. The main thing I can think of is maybe the overshoot could result in dropping the output stage devices / input devices of the next stage out of saturation if the overshoot makes the signal swing too big, I'm unsure if this is one such problem / if there are others.
AI: A robust design implies that the circuit is highly tolerant to component-to-component variation. The Q=0.5 condition is the theoretical limit that can be achieved without overshoot while minimizing the settling time (fastest response). The issue is that slight variation (tolerances) could cause Q>0.5 which results overshoot in the response. Some applications can't tolerate any overshoot for any duration. This is why you don't want to place the pole at the limit when you are trying to achieve a robust design. In practice, you would want to shift the pole a bit to the left (Q<0.5) to assure you have adequate damping (at the expense of speed) to mitigate any overshoot over all operating conditions.
In other words, it's a sensitive balance between performance (fast response) and robustness (insensitive to component values). |
H: LTspice: simulating temperature
I want to simulate the effect of temperature on a semiconductor.
I can use .temp ... or .option temp ... or .step temp ..., but all of these show multiple lines and I am not able to do anything with it in the simulation, for instance, having an op-amp/comparator react on the change in the forward voltage of the semiconductor.
LTspice has some tricks to convert a voltage to a resistance, like this:
Is there something similar to create a gradient in temperature from 0°C at the beginning of the simulation to 100°C at the end?
AI: I think you just want a linear sweep of the temperature. If so, just use a card like this one:
.step temp 0 100 1
That sweeps from \$0^\circ\text{C}\$ to \$100^\circ\text{C}\$ in \$1^\circ\text{C}\$ increments.
I'd then set up a behavioral voltage supply and set it equal to temp. Then set the x-axis to its output.
Here's an example to illustrate:
Let me know if there's something I missed. |
H: How much power to drive this actuator?
I have a linear actuator that I need to design a circuit for, where an Arduino is going to control it.
Here's the datasheet (pdf) for the actuator: https://www.red-magnetics.com/en/product-groups/linear-solenoids/cylinder-solenoids/its-lz-2560-z/?pdf=1
It's the first time I'm using an actuator so I'm not sure how to read this datasheet which doesn't seem to have much information. So I have to choose a power supply and an appropriate MOSFET for this, but what would be the power rating?
I have the 6V version of the actuator, and it says in the datasheet that at 100% duty cycle, it uses 100 W of power. Would the power supply need to be able to deliver 100/6 = 16,7 A?
Related question:
Linear solenoid specifications
AI: As AndyAka has pointed out - thank you very much - the table does not refere to electical power.
Therefore, you need to find the DC-Resistance of the Actuator from some other source.
Once you have determined it, you can use the Driver-Stage found below. Just design the 6V source, Q1 and D1 to whatever nominal current is required.
Here you have: Full Driver stage with 100% test-point coverage during developement and production.
simulate this circuit – Schematic created using CircuitLab
R1 Sets the Default-state for the Actuator to "OFF" if Arduino is in RESET or POWER-UP.
R2 Limits the peak drive current into the FET Gate to 5V/1K = 5mA.. Could go down to 333Ohms to get faster turn on time.
R3 Prevents resonance between C1 and the Actuator Coil during switching. Make sure, it can handle the power impulse when charging/discharging C1.
C1 Supplys current during switching events so the DC/DC or LDO does not have to do all the heavy lifting. Can be reduced to 33uF i guess.
NOTE: The C1/R3 components are optional. I would include generic footprints in the layout, and check if they are really required during testing.
D1 Prevents negative voltage spikes during switch-off of the actuator. Use any low Reverse-Voltage Diode. Make sure the reverse voltage stays low even for high current surges.
Q1 Use a N-Channel FET to switch. use some type with low RDSon which can handle the power dissipation for approx. 3A cont.
NOTE: While using a N-Channel FET will give you a lower voltage drop across the switch and therefore more voltage across the actuator which results in higher drive strength, FETs are more "sensitive" than good old NPN-Transistors. To make the circuit more reliable in case increased power-loss is no concern, i would use a NPN.
If you use a NPN, you could use 7V nom. to drive the Actuator. The 0V7 drop across the NPN will then be "compensated".
LDO/DC-DC Convert your input power to the &V required to drive the actuator. Design for approx. 2A cont. current. Make sure, it can handle the initial current surge when switching without dropping in voltage to much. This increases switch-on time. Make sure the bypass capacitors do not resonate with the Actuator coil.
R7/C2 Forms a RC-Snubber across Q1 if ringing is a problem. Can be unpopulated if not.
D2/D3 These TVS-Diode are just for good measure, as your actuator is connected via a Terminal-Block and external cabeling. Place close to the Terminal block and use any "reasonable sized" VBr > 9V device.
R4 Is a dummy footprint which can be populated with a 0-Ohm jumper during production. Is used for in-series measurements during developement or can be populated with a resistor in case there are resonance problems.
TP1/TP5 Can be used to verify the "driver side" during developement.
TP2/TP3 can be used to validate the power supply and switch performance during developement.
TP6 can be used to verfiy the "buffer" performance during developement.
NOTE: You can use R3 for in-series measurements during developement.
TP7 Can be used to verfiy the power source performance.
R5 Can be used for in-series measurements of the LDO/DC-DC input during developement. Can be replaced with a 0-Ohm jumper during production.
R6 Can be used for in-series measurement of D1 during developement. Can be repalced with a 0-Ohm link during production.
TP8/TP9 Can be used to validate the RC-Snubber.
NOTE: Can use R7 for in-series measurements.
NOTE: You can use the screw-terminals for voltage measurements across the actuator during developement. |
H: How do I configure a negative clamper in LTspice?
I am trying to make a negative clamper in LTspice. The pulse source goes from 10V to -10V harmonically. My aim is to lower it's voltage by 7.3V, so it will have a pulse graph going from 2.7 to -17.3V, but I don't know how to configure the circuit for that.
AI: My aim is to lower it's Voltage by 7.3V, so it will have a pulse graph
going from 2.7 to -17.3V. But I don't know how to configure the
circuit for that
You need D2 to be equivalent to an ideal diode in series with a voltage source of 2.7 volts: -
This prevents the voltage on the anode of D2 rising any higher than +2.7 volts. If the only model of diode you have has a forward volt drop that isn't zero (ideal) you will have to play around the the 2.7 volt source by lowering it maybe 0.5 volts. Experiment!!! |
H: Why don't the C1 and C2 capacitors discharge?
In the circuit, we know that when D1 is connected then the C1 capacitor is also in the circuit until it's fully charged. Why when D1 is disconnected and D2 and C2 are in the circuit, C1 can't discharge? What is the reason behind it? And so doesn't C2?
AI: In the circuit, we know that when D1 is connected then the C1 capacitor is also in the circuit until it's fully charged.
Terminology: D1 is permanently (always) connected. You mean "when D1 is forward biased (conducting)".
Why when D1 is disconnected and D2 and C2 are in the circuit, C1 can't discharge?
The characteristic of a diode is to allow current to flow in one direction only - the direction of the arrow in its symbol.
The result is that C1 and C2 can't discharge back to the voltage source but they can discharge to the load, RL. The result of this will be to cause some ripple on the otherwise steady DC supply.
What is the reason behind it?
You might find the non-return valve analogy useful on my page, What is an LED.
And so doesn't C2?
D2 and C2 form in inverse of the D1 and C1 circuit. They generate a negative voltage relative to the C1 - C2 common node. |
H: Bizarre behavior with SIN LTSpice
I have this circuit I'm supposed to analyze. I am asked to set v1 to a sine wave V1= A sin (2pi f t) with a frequency f = 1 kHz and A = 5mV. I think I did everything right, but when I run the simulation I have 2 issues:
Edit: I just realized that it should be SIN(0 0.005 1k), but it doesn't change my problem.
One: It takes REALLY long to simulate, like much longer than all my other circuits and most importantly,
Two: Instead of showing a sine wave, I get this instead:
It should, however, show a normal sine wave. Can anyone explain why this is happening?
AI: The simulator is doing exactly what it was told to do.
The capacitors are 2000000 farads, which means that the RC timeconstant will be roughly 9.2 billion seconds or 291 years, so simulating 10 seconds and graphing a few 10's of us won't show that capacitor charging much.
According to Quora the largest capacitor ever made was 30000F |
H: Where am I wrong in understanding feedback network?
The following is from the book Design of Analog CMOS Integrated Circuit, Page 314.
Calculate the open-loop and closed-loop gains of the circuit shown in Fig. 8.66(a). Assume that λ = γ = 0.
For feedback network
consisting of \$R_S\$ and \$R_F\$,
$$h_{21} = -\frac{R_S} {R_S + R_F}$$
How did the author get this \$h_{21}\$?
The author has a similar example for this.
In this case, the feedback network is
$$g_{21} = \frac{R_S} {(R_F + R_S)}$$
Similarly, we can also use this method for example 8.66.
$$h_{21} = \frac{R_F} {R_S + R_F}$$
AI: I think in the linked document the terminology (A_open) and the used symbols (beta=h21) are somewhat confusing. More than that, to use an ideal current source to drive a MOSFET complicates the whole analysis. Nevertheless, I think that everything is correct.
At first, we should realize that we have current-controlled feedback and we need - at the same time - a voltage to drive the FET M1 in Fig. 8.66.
1) How works the feedback? The current source I_in drives the current through the Rf-path and creates a gate voltage at node Y (across Rs||1/g) which will be reduced by the voltage drop across Rs caused by the current I_out (no feeedback current through RF). This describes the feedback effect in words (180deg phase inversion due to common-source/common drain): Two currents with opposite sign meet in node Y and create the gate voltage for M1.
2.) My explanation starts with the well-known classical feedback model applied (as an example) to an inverting opamp (voltage-controlled current feedback). We will se that the used quantity "Aopen" in the linked doc needs an interpretation (because it is NOT identical to the opamps open-loop gain Ao).
3.) The closed-loop gain of the inverting opamp is Acl=-(Hf * Ao)/[1+(Hr * Ao)]
with forward damping Hf=R2/(R1+R2) and feedback factor Hr=R1/(R1+R2).
For Ao approaching infinity we arrive at the well-known expression Acl=-Hf/Hr=R2/R1.
4.) Now let us compare the expression for the closed-loop expression in 3. with the closed-loop gain in the linked document (ignoring the negative sign):
Acl=(Hf * Ao)/[1+(Hr * Ao)]=Aopen/(1+ h21 * Aopen)
As we can see, both open-loop gain expressions are not identical because Aopen does not equal Ao. Therefore, the feedback factor Hr is not identical to the used feedback quantity h21.
The comparison gives: Hr=h21 * Hf or h21=Hr/Hf.
5.) Applying the (classical) definitions for Hf and Hr (see 3.) on the shown circuit in Fig. 8.66 we can write:
Hr=Rs (feedback voltage across Rs and no current through Rf) and Hf=Rs+Rf (input voltage caused by the signal source I_in).
Therefore: h21=beta=Hr/Hf=Rs/(Rs+Rf).
(Because of current feedback the quantities Hf and Hr are not dimensionless; the are given in V/A).
Comment: From the circuit it was by simple visual inspection not evident to me that the feedback factor is Rs/(Rs+Rf). I think the reason is that (1) we have current-controlled feedback and (2) an input current source and - at the same time - a FET which does not consume any input current. And another reason was a definition for the gain without feedback (A_open) which - in contrast to the opamp example - contains also the input damping of the feedback network. Consequently, also the feedback factor beta=h21 has another definition if compared with the opamp example which I am more familiar with.
Finally, it must be mentioned that Razavis "A_open" is NOT identical to the commonly used term "loop gain".
EDIT : Upon request I have added the example circuit (inverter) and the corresponding block diagram (feedback model, Hf and Hr as defined in the text above). |
H: Is there a component that can record circuit on-time without a battery?
I don't know if such a thing exists already. I'm looking for a component that can record how long a circuit has been powered on. Kind of like the "change filter" light on a fancy vacuum cleaner. It must be able to resume recording after being powered off and on again and cannot use a battery backup.
I've already implemented this before using a microcontroller and FRAM, but i'm curious if such a thing already exists on the market in one package.
edit: the component must also be resettable.
AI: The Curtis Instruments Solid State Elapsed Time Monitor 200 SERIES description contains:
Safe, reliable EEPROM memory storage of data without battery back up
The datasheet linked above shows the data format used to read the elapsed time:
Some models have a pin which can reset the elapsed time. It looks like there is some protection against inadvertent reset of the elapsed time since:
The supply voltage range is 4.75 – 10 VDC
The reset voltage is 20 VDC +/– 5%, supplied on a dedicated pin.
This was just the first example of a Solid State Elapsed Time Monitor I found where the datasheet described how the elapsed time was recorded in non-volatile memory (in this example EEPROM). |
H: Trying to design a synchronous sequential counter circuit with a given sequence
I'm trying to design a counter circuit that counts 6 → 4 → 2 → 0 →
2 → 5 → 3 → 1 using T flip flops and I haven't been able to achieve it. I tried the steps below and designed the circuit below in CircuitVerse, but it doesn't work properly. Where am I making a mistake? Some people have pointed out I needed to use a Mealy machine, but I haven't been able to understand why.
AI: initial state, general comments
One of the first issues encountered in a problem like this is the initial state, itself. In simulators, FF's usually start up with \$Q=0\$ and \$\overline{Q}=1\$.
In some physical reality cases, there's no way to know the power-up state. In such cases, am asynchronous CLR and/or SET pin is needed. (Or some other mechanism to delay use until the initial states can be established.) Here, I'd attach a power-on reset circuit so that the FFs are held in either CLR or SET state while the power supply becomes stable, releasing that line only after the supply is known-stable.
But in these purposes I'll assume that at the beginning \$Q=0\$ and \$\overline{Q}=1\$.
initial state assumptions
In this case, I'll take it that each T FF powers up with \$Q=0\$ and \$\overline{Q}=1\$.
Antonio51 brings up an important point: state 2 comes up twice and it doesn't transition to the same next state. So this means you need an additional T FF to distinguish one from the other, or four T FFs not three.
It doesn't matter what it's initial state is, you can work with it either way. But for simplicity's sake, let's assume that the first state \$2\$ uses the added T FF as \$Q=0\$ and \$\overline{Q}=1\$ and the second state \$2\$ uses it, oppositely.
This distinguishing bit can be placed anywhere you want. Doesn't matter. But I'll make it the higher-order bit of the sequence, again for simplicity's sake.
Since you want the initial state to be \$6\$ this just means that you set things up so that your actual output is taken as \$\overline{Q_2}\:\overline{Q_1}\:Q_0\$.
To get the desired result, 6 → 4 → 2 → 0 → 2 → 5 → 3 → 1, the states will be \$0\$, \$2\$, \$4\$, \$6\$, \$12\$, \$3\$, \$5\$, and \$7\$.
Take \$\overline{Q_2}\$, \$\overline{Q_1}\$, and \$Q_0\$ as the counter outputs.
FF options
The following is just a note. You've already said that you want T FF. Granted.
But to be pedantic it doesn't hurt to keep in mind there are at least these options for FFs:
$$\begin{array}{c|c|c}
\text{Transition} & \text{JK FF} & \text{T FF} & \text{D FF}\\\hline
{\begin{smallmatrix}\begin{array}{c}
\text{start }\to\text{ end}\\\\
0 \quad \to \quad 0\\
1 \quad \to \quad 1\\
0 \quad \to \quad 1\\
1 \quad \to \quad 0
\end{array}\end{smallmatrix}} &
{\begin{smallmatrix}\begin{array}{cc}
J & K \\\\
0&x\\
x&0\\
1&x\\
x&1
\end{array}\end{smallmatrix}} &
{\begin{smallmatrix}\begin{array}{c}
T\\\\
0\\
0\\
1\\
1
\end{array}\end{smallmatrix}} &
{\begin{smallmatrix}\begin{array}{c}
D\\\\
0\\
1\\
1\\
0
\end{array}\end{smallmatrix}}
\end{array}$$
counter table
The table I see for this problem is:
$$\begin{array}{c|c}
\text{States} & \text{FF Inputs}\\\hline\\
{\begin{smallmatrix}\begin{array}{cccc}
Q_D & Q_C & Q_B & Q_A\\
\vphantom{\left.\overbrace{\begin{array}{ccc}J & K & T & D\end{array} } \right.}\\
0&0&0&0\\
0&0&1&0\\
0&1&0&0\\
0&1&1&0\\
1&1&0&0\\
0&0&1&1\\
0&1&0&1\\
0&1&1&1\\\\
0&0&0&1\\
1&0&0&0\\
1&0&0&1\\
1&0&1&0\\
1&0&1&1\\
1&1&0&1\\
1&1&1&0\\
1&1&1&1
\end{array}\end{smallmatrix}} &
{\begin{smallmatrix}\begin{array}{cccc}
Q_D & Q_C & Q_B & Q_A\\
\left.\overbrace{\begin{array}{cccc}T\\
0\\
0\\
0\\
1\\
1\\
0\\
0\\
0\\\\
x\\
x\\
x\\
x\\
x\\
x\\
x\\
x
\end{array} } \right. &
\left.\overbrace{\begin{array}{cccc}T\\
0\\
1\\
0\\
0\\
1\\
1\\
0\\
1\\\\
x\\
x\\
x\\
x\\
x\\
x\\
x\\
x
\end{array} } \right. &
\left.\overbrace{\begin{array}{cccc}T\\
1\\
1\\
1\\
1\\
1\\
1\\
1\\
1\\\\
x\\
x\\
x\\
x\\
x\\
x\\
x\\
x
\end{array} } \right. &
\left.\overbrace{\begin{array}{cccc}T\\
0\\
0\\
0\\
0\\
1\\
0\\
0\\
1\\\\
x\\
x\\
x\\
x\\
x\\
x\\
x\\
x
\end{array} } \right.
\end{array}\end{smallmatrix}}
\end{array}$$
k-maps
I'm not going to draw out the k-maps. You can take the above table and generate those, if you like. And it's good practice.
However, you can also readily plug any part of the above information into Steve Rickman's Logic Friday program (the latest version I have is 1.1.4.) It will minimize the logical algebra. If you do your own k-maps, verifying your findings using Logic Friday makes sense.
When using Logic Friday, also make sure that you select its minimize option as shown below:
From there, you should be able to set up the logic for your T FFs.
Don't forget that your output is not taken from the \$Q\$ outputs the lower-order three T FFs. Take \$\overline{Q_2}\$, \$\overline{Q_1}\$, and \$Q_0\$ as the counter outputs! |
H: Testing wheelchair motors on an AC to DC power supply
I recently purchased 2 Jazzy Wheelchair Gearbox Motors (12-24 VDC) to use in a robotics project. I've done tons of LED, Arduino, and smaller motor projects but this is my first time doing a project with heavier duty electronics so I want to make sure I don't burn out any expensive parts before I start tinkering.
Naturally the finished robot will eventually run on two 12 V batteries in series. Wheelchair batteries are easy to come by so I'm not too worried about finding a proper unit, though I don't really want to deal with batteries until the build is done. I'm not 100% sure as the motor listing omitted this, but I believe it to be rated at 250 W.
How many amps must a power supply be rated for in order to run both motors?
(24 V x 10 A = 240 W) Does that mean I need 20 A? More? The motors won't be working too hard during testing; they'll be mounted on my workbench for this part.
AI: If the motors are rated at 250W, then you need a 500W supply, 20.83A unless you test at your desired max torque (but how will you power the test?). However the starting current surge can be 3x the rated current, regardless of how much current you intend to use to drive the motors steady-state. You can reduce this somewhat with soft-start circuits, ramped PWM, or inrush current limiters, but expect to have to deal with this. Some power supplies can support brief 50% or 100% overloads but some will trip off on overcurrent protection. Consult the datasheet. |
H: How to improve my son's solar bobble head
My son has a minecraft solar bobble head (in this case a bobble Steve). Under light it swings a diamond sword this exact one (Puckator Officially Licensed Minecraft Steve Solar Pal https://amzn.eu/d/gH1XvAn).
It is made up of a small solar cell, connected to a circuit board that holds a single capacitor and the board is connected to the copper coil. A magnet sits in a plastic housing that is connected to Steve by automaton connections and dynamics (photos can be added if needed).
It is dismal it barely moves under any light regardless of source (sun, room, phone, torch, plant grow UV). How can I increase its magnetic resistance? A better solar cell? A smaller capacitor? A smaller/larger voice cell copper coil? I've already tried swapping out the magnet for neodymium button magnets but it seems the issue isn't in the strength of the magnet
Ps. I know it's silly and probably never worked in the first place but me and my son are going to fix it or make it better, so any suggestions aren't wasted they are all in the name of my son learning electronics and physics. (He's 8 and rather ahead for his age.)
AI: magnetic resistance
I know what you mean, but that's not really a term in widespread use. Electromagnetic force would be quite descriptive instead.
a better solar cell?
Yes, definitely. A larger solar cell would help. The square ones you'd find on top of solar lights should be sufficient for this.
a smaller capacitor?
Not at all. The bigger the better. But of course it will take longer to charge up. I'd leave the capacitor unchanged for now. There is a possibility that the capacitor itself is bad (electrically leaky). But I wouldn't replace for a larger capacity value. Leave be for now.
It's likely that the toy doesn't have an "undervoltage lockout" and wastes energy that way.
Solar toys that have insufficient solar input to work just off solar power - and this one is of that kind, due to a very small cell - need to first charge up a capacitor from the solar cell. Once the voltage on that capacitor is high enough, the "motor" is turned on and the toy will "run" for some time.
There are modern, single-chip, ultra-low-power (they don't use much electricity) voltage monitors that can be used to detect when a capacitor is charged up high enough and turn on the electromagnet and its driving logic. Such a chip uses so little power that it won't be discharging the capacitor while the latter is charging up ("soaking up the Sun").
I'm sure the toy is salvageable, but how much reengineering it will need is anyone's guess unless they opened a similar toy before.
Perhaps getting it to work from a regular small battery - say one or two AAA cells, so 1.5V or 3V - would be a good starting point. Just to make sure the thing functions at all. Only then will it make sense to mess with the solar cell, capacitor, etc. |
H: When should you use default operators vs. implementing your own hardware?
When using Verilog, when should you use default operators like a + b, and when should you implement your own version of the hardware, like writing a full adder? Is it only when you need a specific need, or is it better practice to know exactly what hardware is being generated?
AI: It is best to describe your hardware using the highest level of abstraction as possible with Verilog. This means you should prefer a + b over creating full-adder instances.
You end up with fewer lines of Verilog code, which makes the code easier to understand and maintain. As your design becomes larger and larger, the amount of code will become huge when creating gate instances, relative to the more abstract + (and the like) operators. Less code also means faster simulation times.
Generally, you will want to take advantage of synthesis software to convert your Verilog code into hardware, be it FPGA or ASIC. Using the higher level abstractions could allow your synthesis tool more freedom to implement more efficient hardware (faster, smaller area, etc.).
Creating basic building blocks like full-adders has its use for teaching purposes, but you'll quickly find yourself out-growing the need for modeling at such a low level of abstraction. |
H: Help with N-Channel MOSFET circuit and behaviour
I have a bare PCB with N-Channel MOSFET in the input (12V), however when connecting the power source, no voltage comes out from the MOSFET, and when connecting with reverse polarity, the output from the MOSFET is -12V.
Tried three different MOSFETs, all give the same results.
The MOSFET is - https://www.lcsc.com/product-detail/MOSFETs_HUAYI-HYG025N06LS1C2_C2827231.html
I initially tried with the original circuit attached, and after also tried to remove everything (The Diode and Capacitor)except the MOSFET - same results.
Nothing comes out from the (S)ource when connecting (+12V) (maybe 500mV...), but if connecting (-12V) (reveres polarity) the (S)ource outputs (-12V).
Is this a faulty schematic or faulty MOSFET?
AI: The circuit works as intended. The source terminal of the MOSFET is the ground connection, not 12V.
Swap the output terminals around - you have them backwards.
If you want to switch the +12V line (instead of ground), you need a reverse polarity protection circuit based on a P-Channel MOSFET instead. The N-Channel version always switches ground. |
H: Is this behavior for a Murata PIR motion sensor test circuit expected?
I am using a Murata IRA-S500ST01A01 PIR motion sensor. This is the datasheet. Based on a description of the pyro-electric effect from part 2 of these application notes for the IRA S210 (same family of sensors), the output voltage of the sensor should change in reaction to a change in temperature of the pyro-electric element.
I have built this circuit from this data sheet for the IRA S210:
The op-amp I am using is actually the LM324N. I have connected the OUT line to a 10K resistor and then to GND, and placed the nodes of a multi-meter on either side of the resistor to measure voltage. What I have observed is that the voltage is stable at about 850mV. When I wave my hand across the sensor I get no response, but when I cup my hands around it or wave a stove-heated spatula across it I do see an increase in voltage of about 10mV. Is this to be expected?
If so, how would it be able to detect a person walking in front of it?
AI: how would it be able to detect a person walking in front of it?
I'd be looking at the other test circuit they show and recognize that to measure small changes in signal you need an AC amplifier as shown in the test circuit for white noise output: -
Everything to the right of the red arrow needn't be built. But, you really need an oscilloscope. What you may find is that the 2.1 MΩ resistor (feedback on the left op-amp) might be adequate or, it might need adjusting for your actual needs. You might also find that the 22 μF capacitor might need to be bigger to adequately detect slow moving changes in IR picked-up. |
H: Neutral to ground bonding place question
Does the neutral-ground bonding need to be done before the RCD/GFCI breaker? If there is an energized metal frame due to a fault, will the RCD/GFCI breaker see a difference between live and neutral only if the bonding is done before the breaker?
AI: Maybe this is a very stupid question but to be sure. Does the
neutral-ground bonding needs to be done before the RCD/GFCI breaker?
It absolutely does (as indicated in your diagram).
If there is an energized metal frame due to a fault, the RCD/GFCI
breaker will see a difference between live and neutral only if the
bonding is done before the breaker?
Correct. |
H: Help demonstrating mathematically the behaviour of a passive filter
Consider the following circuit:
By inspection, it can be said that the complex impedance of the circuit will be \$R_2\$ for very low frequencies and \$R_1\$ for very high ones, as the inductor will behave as an open circuit for very high frequencies and the capacitor will do the same for very low ones.
I have tried to demonstrate the second statement (the impedance will be \$R_1\$ for very high frequencies) mathematically but I can't. Below are my calculations (let \$s\$ be \$j\omega\$):
$$Z_t = \frac{1}{\frac{1}{R_1 + \frac{1}{sC}} + \frac{1}{R_2 + sL}} = $$
$$\frac{1}{\frac{sC}{sCR_1 + 1} + \frac{1}{R_2 + sL}} = $$
$$\frac{(sCR_1 + 1)(R_2 + sL)}{sC(R_2+sL) + sCR_1 + 1} = $$
$$\frac{sCR_1 R_2 + s^2CR_1 L + R_2 + sL }{s^2L + 1 + s(CR_1 + CR_2)} = $$
$$\frac{-w^2CR_1 L + R_2 + j\omega(L + CR_1 R_2)}{-w^2L + 1 + j\omega(CR_1 + CR_2)}$$
Then, I calculate the module of \$Z_t\$ as:
$$|{Z_t}| = \frac{\sqrt{(R_2 - \omega^2CR_1L)^2 + (\omega(L+CR_1R_2))^2}}{\sqrt{(1-\omega^2L)^2 + (\omega(CR_1+CR_2))^2}}$$.
For very high frequencies, I do:
$$\lim_{\omega \to \infty}\frac{\sqrt{(R_2 - \omega^2CR_1L)^2 + (\omega(L+CR_1R_2))^2}}{\sqrt{(1-\omega^2L)^2 + (\omega(CR_1+CR_2))^2}}$$
As \$(\omega^2)^2 = \omega^4\$, I cancel out the squared terms to the right, leaving the following:
$$\lim_{\omega \to \infty}\frac{\sqrt{(R_2 - \omega^2CR_1L)^2}}{\sqrt{(1-\omega^2L)^2}}$$
which yields
$$\frac{\sqrt{C^2R_1^2L^2}}{\sqrt{L^2}} = CR_1$$
But it should be \$R_1\$. What am I missing?
AI: In the last formula with s ( in denominator),
the term \$s^ 2 L\$ should be \$ s^2 L C \$ -> \$-w^2LC\$.
NB: you don't need passing to \$w\$.
Just search the "limit" when s-> infinity = \$(s^2 C R1 L)/(s^2 L C) = R1\$.
And it is R2 when s-> zero. |
H: Linear system - causal and memoryless system (integral)
\$T{(x(t))} = \int _{-\infty }^{+\infty }sin\left(t+\tau \right)x\left(\tau \right)d\tau\$
Is this system causal or not? Is it memoryless or not?
At first I thought it was not causal and with memory since the boundaries are from \$-\infty\$ to \$+\infty\$.
I later realized that since the boundary does not depend on \$t\$ then it is not correct to do it that way.
I guess it means that the system is causal and memoryless, since it does not have dependence on \$t\$ at integral.
How do I show it?
If this helps:
The system is linear, not time invariant, not stable (according to what I managed to find,) regarding invertible I guess it is not, but could not prove it. My intuition says it is not.
AI: Let \$x(t)=\delta(t)\$. The output (the impulse response) is \$h(t) = \sin(t)\$, which is not strictly zero for \$t<0\$. Therefore, the system is not causal. A non-causal system is also not memoryless.
The output signal for \$x(t)=\delta(t-2\pi)\$ is also \$\sin(t)\$. Since the inputs \$\delta(t)\$ and \$\delta(t-2\pi)\$ produce the same output, the system is not invertible. |
H: Transmitting input through USB from microcontroller
I am making a device, similar to a cross between a controller and a mouse, and I wondered how I would send input to the computer.
For example:
Transmitting movement, buttons pressed etc.
Also, how would I make it so the computer automatically detects it as a mouse.
Thanks in advance.
AI: You need to look up how USB works.
When plugged in, there is an enumeration process where PC asks what kind of device was connected, and in this case, your device likely wants to tell the PC that it a mouse or some other standard HID device. Then you need to send movement and button changes in USB packects according to HID standard. |
H: How to filter noise/ripple for a JFET audio amplifier?
In my first realization of a common source JFET preamplifier, I encountered a rather predictable problem but for which I was unable to find any documentation: the power supply ripple and noise are reflected in the output signal, which comes out amplified and audible in the audio output!
The ripple has a frequency of about 120Hz and a Vpp of 7mV, this is the picture of the power supply output:
This is the ripple at the output of a 4.7μH π LC filter and ~4mF placed after the 600kHz step-up, which falls within the audibility threshold. This ripple also contains noise at 265kHz and 2MHz, which, being well beyond the audibility threshold, should not be a problem.
So I wonder: what are the best ways to obtain a clean output of the signal to be amplified? Would an RC filter of 200Ω and 47μF only attenuate the issue, but not be a real solution? I would like to use a solution that requires discrete components and does not overly complicate the circuit.
Can the noise at 265kHz and 2MHz have a negative impact for an audio application?
Additional information required:
Power Source:TLV61048, 3.7V input and 14V output,600kHz,4.7μH;
JFETs tested: 2SK208, BF862;
Inductor:SWPA5040S4R7NT
Amplifier design source:Fetzer Valve R17=~2.3k
Audio input: Tone Stack from pre-amplified guitar
AI: Those high-frequency components could be filtered with an LC filter, but the low-frequency 120 Hz component requires a different approach. One must be careful that the 120 Hz component doesn't ride in with the input signal - a ground loop might cause this.
A capacitor multiplier might address the 120 Hz component, if it really does enter via Vdd. It does consume some Vdd, dropping a few volts, but has good attenuation of 120 Hz:
simulate this circuit – Schematic created using CircuitLab
One has to be careful that Q1 doesn't oscillate at hundreds of MHz. Even printed-circuit construction can oscillate at low amplitude. Ferrite beads on base and/or emitter might be advised. |
H: What temperature should I use to desolder a FPC connector by heating the back side of the PCB with a hot air gun?
I am learning how to use a hot air gun on PCBs.
I saw some videos of FPC connectors being desoldered by heating the back side of the PCB with a hot air gun. I am assuming it is being done to prevent melting of the plastic of the connectors.
Is that an acceptable or even the preferred way of doing it? If so, at what temperature and airflow rate would one do that?
AI: There are a lot of videos of repair processes by really skilled electronics technicians. Here is one, and he frequently mentions the temperatures and flow rates he is using to repair iPhones and such like, but keep in mind the flow rate settings are going to be different for different hot air rigs. There are others, of course, and watching a variety of techs work won't hurt at all. Rework is a physical skill with some technical aspects and I think a video or in-person instruction is most helpful in learn it.
It's not just temperature, but how you play the airflow around and how much airflow there is.
Also practicing on something that doesn't matter before you tackle something that is valuable to you. You need to be able to see what is going on, so lots of light and a microscope or magnifier is invaluable when dealing with smaller parts.
The best method depends what is around it, and what kind of solder was originally used and what all is around the part you are trying to remove. One method uses special very low melting point solder (eg. Chip Quik- some of which melt at less than 65°C) to dilute the original high melting point lead-free solder, which is then thoroughly removed using fresh desoldering braid and replaced with medium melting point solder such as leaded eutectic 63/37 to place the replacement connector. And with relatively copious quantities of liquid flux applied very locally at each step, then cleaned off with pure isopropanol and inspected before proceeding to the next step.
If the connector is broken, overheating it is not so much of an issue but you might want to shield adjacent parts from the air flow to prevent them from being blow off or overheated. |
H: How to extend up-time after power supply is gone
I just started to work on a small home project. I have an indoor bike that I use quite a lot. The resistance of the bike can be adjusted manually in a purely mechanical way (by tightening a screw). And I have some 24V DC motors laying around, so I thought, why not combine the two and create a smarter bike.
My plan is to connect the motor to the bike and use a MOSFET and PWM to set the resistance level. When I exercise, the generator is going to generate some DC voltage, depending on the speed. I feed it through a bridge rectifier, just in case, then I place an N-channel MOSFET for setting the resistance level using a PWM signal.
This is very simple so far, but now comes the fun part. I also want to run the circuit that handles the automatic difficulty setting using the power generated from the motor. But since the resistance is set using a PWM signal, the output voltage is also a square wave. Therefore, I add some capacitance after a diode to smooth out the voltage. I also added a zener diode to prevent too high voltages, just in case. I convert the output DC voltage of the motor to 5V (needed for the encoder of the motor and maybe some other circuitry) using a buck converter, and then I convert the 5V to 3.3V using an LDO. There, I will place my ESP or STM-based microcontroller circuit, which should not draw much current.
I also want to measure both the input voltage and the 5V voltage line, and when it drops to an insufficient level, I want to have enough time to persist some data by writing it to a flash memory or an SD card. I will work on the low voltage detection later with some transistor-based interrupt line.
You can find my current design later. Is this a viable idea? To use capacitors to extend the uptime with a couple of milliseconds for persisting data? Where should I place the capacitances, on which voltage line? I thought about putting them on the 3.3V line, because that is the most crucial circuit that would need to be up the longest. But when the supply voltage is gone and the circuit draws current from the capacitor, then the voltage of the capacitor will start to drop as well. Therefore, maybe I should pack capacitors on the 5V line or even the 24V line, so that even if that voltage drops, I will still have a stable 3.3V for the circuit. But then if I put the capacitances on the 24V or 5V line, then the additional circuitry will drain it faster. Or maybe put extra capacitances everywhere, so that every line has its own storage, and then the 3.3V line is up for the most time. But I don't necessarily want to overload the circuit with capacitances either. What capacitance size would you recommend using?
AI: That's what supercaps are used for. Use a diode before them so they so they do not get reverse drained in the wrong direction once power is lost.
For a capacitor of the same capacitance, if it can tolerate the voltage on the input side of the LDO it is better to put it there because that provides voltage overhead to compensate for the voltage dropping when you lose power. The LDO then regulates it down and you get a flatter supply voltage for longer.
If you place a capacitor on the output side of the LDO, your supply voltage will immediately begin to drop below nominal when you lose power.
If you want to bypass extraneous circuitry to reduce loading, you can put a dedicated regulator for the components in question.
Make sure to choose an LDO with a PMOS pass element. These will essentially become pass-through when the regulator enters drop out allowing you to squeeze every last bit of charge from the capacitor that is in your operating voltage range. Other types of LDOs may not do this and just cut the voltage off when entering dropout. |
H: LED Fails to illuminate, what am I not seeing in my configuration(s)?
I'm working on a super simple circuit, I want to light the LED.
Power Source 1: 5.5v from 9v battery through breadboard power supply module
Power Source 2: 5.5v from lab bench PSU
LED Info: Vf - 3v to 3.2v; If = 20mA;
Resistor: 150 +/- 2% - brown/green/black/black/brown (the close-up picture makes the browns look purple, but they are brown)
Things to note:
I have used a multimeter to test the connectivity, it beeps
I have used a multimeter to verify voltage is getting through, it does
I have used several different breadboards AND multiple tie points for each breadboard.
I have used multiple different colors (adjusting the resistor for each based on Vf & If for the color)
Whenever I check the LED connectivity with the 3.3v with an LED that can hold up to it, it lights up, again in multiple tie points
weirdly, if I use a jumper cable to connect row abcde to fghij, the LED does not light up (again checking multiple tie points, and multiple boards), but when I directly connect the anode to abcde and the cathode to fghij it does light up.
Yes I make sure that the anode and cathode or appropriately placed
Yes I use the multimeter to check everything every new setup
Yes I have used multiple values of Resistors pushing the resistance as low as is safely possible for the LED
Yes I have checked the Ohms of for each resistor that I have used
Yes, I have used both sides of the power tie strips
Working Configurations:
3.3v from lab bench PSU
3.3v from 9v via power supply module
Non-Working Configurations:
5.5v from lab bench PSU
5.5v from 9v battery via power supply module
close up of parts
AI: Classic beginner's breadboard mistake.
Figure 1. We somehow expect the green connections to be zero ohms while the red one is an open-circuit!
All five sockets in a row are the one terminal strip. The LED is short-circuited. |
H: Small Speaker with High dB. Loud enough?
I need a compact speaker suitable for a 16mm diameter tubular enclosure. The speaker must be capable of playing voice audio clips with sufficient clarity and volume to be easily hearable and understandable for 1-2m away in a small room. I'm thinking about 30% of a modern iPhones volume level would be fine.
I'm looking at CUI Devices speakers page, they have good filters for width/height and tons of options that physically fit.
I think I might have found a possibility: CMS-151125-076L100B
15 x 11mm
S.P. Level (dB): 92.5 (0.7 W / 1 m)
Product page (links to data sheet)
I'm worried though, is this as loud as I think it might be / how loud will it be? Maybe I'm missing something? It's pretty tiny.
According to some random Quora answer from 5y ago about iPhone volume: "I have read that one can get up to 85–90 db at 0.5 meters". (an iPhone) So if this answer is accurate, then it should be relatively loud and meet my requirements as it?
Is a speaker like this even capable of playing voice clips?
AI: If you only do care about understandability of the voice and not some other voice characteristics and your environment is not particularly noisy, 85-90dB are way above the pleasant sound level and will probably scare the hell of an unexpecting user. The normal human talking is 50-60dB and this is ~1000 times less power than 90dB.
In practice, if you throw 10-100mW at whatever speaker you dig from the junk bin, you will get enough sound level to recognize speech. This is the power level most people listen to radio at in small and more or less quiet rooms.
You may want to limit the bandwidth of the signal to e.g. 300-3000Hz just like older phone systems do in order to get good recognition vs distortion and used power. |
H: What resistors for a 4 LED Arduino/breadboard project?
I am currently working on a school project for my work-study. The project is super simple: light up 4 LEDs, in various patterns, using a push button to cycle through the modes. I'm using 4 colored LEDs, a breadboard, resistors, jumpers, and an Arduino UNO.
I am brand new to electrical engineering, and have spent the night learning about resistors. I have 5 band resistors, cheap blue ones, and I have been trying to use Ohm's Law to figure out the right resistor to use.
By my calculations @ 5V power, ~2V for the LED (taking voltage drop into consideration), and ~10-20mA current you end up with something like a 150ohm resistor.
My professor used 1000ohm resistors when he helped me start building my setup, so now I am confused as to why he would have chosen 1000 if Ohm's Law states you ought to need closer to 150? I have all sorts of resistor values, including 100, 220, and 1000. I am using a separate resistor for every LED, since they must be separately controlled.
My setup, with 1000ohm resistors used:
AI: For most modern LEDs, 15mA or 20mA is way more than you need, and close to the maximum that can be driven directly from the Atmel/Microchip MCU chip you are using.
Consequences of using too low a resistance are reduced reliability, excessive power consumption and sometimes annoyingly and unnecessarily bright LEDs. For example, I have a computer case that has a blue LED so bright it casts shadows on my office wall. People actually sell stickies to reduce the brightness of indicator LEDs, so this problem has created a capitalist solution. Of course if you need your indicators to be visible in direct sunlight you will need more brightness than if they are to be used in subdued lighting of an office or home.
So I suggest you try various resistors (of higher value than the minimum, of course) with the LEDs and see what brightness looks good to you. The values in general will be different for different colors, but maybe you can use just one value. You may find 1K or even 10k yields enough current. |
H: How does the second flip-flop in a naive synchronizer "prevent a metastable state from propagating"?
In this very nice answer it's explained that, fundamentally, a two flip-flop synchronizer's basic operation is to prevent the propagation of a metastable state (effectively, an invalid logic level) from propagating down a system. I still don't totally follow how this actually works though.
Suppose the worst happens and FF1 enters a metastable state. Its output is floating somewhere near mid-rail but (slowly) moving one way or the other. Now based on the required MTBF we arrange for some \$T_c\$ in the receiving system such that it is very likely that the output has settled before launching the FF1 output to the FF2 output.
I have two questions:
Q1) If we didn't have FF2, what would go wrong? Is the issue that driving combinational logic with a potentially invalid input burns power? That is, I just want to be clear that the role of a synchronizer is not (necessarily) to ensure that the correct value is captured so much as that some valid logic value is captured.
Q2) Since the argument above is probabilistic, it's possible that FF1's output will not have settled when FF2 launches and we thus get an invalid D2 input when FF2 launches. Does this basically mean FF2's Q2 output will be (potentially) metastable/mid-rail and thus we're led to whatever problem answers Q1? If this is correct, is the precise statement to be made that FF2 "prevent[s] a metastable state from propagating [with a high degree of probability]", whereas a single-flip-flop solution would be guaranteed to have a metastable state propagate?
AI: Q1 -- likely the additional power from the signal being in the metastable state is not significant. The main unwanted effect of metastability is that the perceived value (by a subsequent logic gate) may change between clock cycles which is not what is intended by using a DFF in the first place. This may upset the performance (logic correctness) of the downstream circuits.
Similar to the above, different logic gates being driven by the same metastable signal may have different opinions on what the logic value is -- one may thing it's TRUE, while the other may consider it FALSE -- which may happen depends on the electrical 1/0 voltage threshold of that individual gate sample (and this also depends on the gate type -- inverter, NOR, ... etc.)
What DFF2 does it reduce (but not 100.0 % eliminate) the probability of a metastable start propagating. Consider that a single DFF may reduce the probability by a factor of 10^9; then two cascaded ones will reduce the probability by another factor of 10^9, for a total of 10^-18. So a 1 GHz signal clocked continuously would then have an MTBF of about 10^9 s -- over 30 years. |
H: Why are drain and source not actually perfectly symmetric?
In textbook treatments, one has that the source and drain of a MOSFET are completely symmetrical and therefore interchangeable -- the distinction is only made by which is at a higher voltage in the circuit in which the MOSFET is used. Gray and Meyer (Analysis and Design of Analog Integrated Circuits, 5e) however note that "In practice, the symmetry is good but not perfect."
Why is the symmetry not perfect? Is it the case that fab processes actually design drain and source diffusions slightly differently (for, say, the unit transistor in a given process) or is the "in practice" caveat simply to note that drains will be connected to, for example, an output node with lots of other connections thereto whereas a source might not be. That is, is the "in practice" distinction between source and drain intrinsic to the process or simply about how we electrically connect them in most circuit designs?
AI: Generally, transistors used in logic circuits do have symmetrical source and drain characteristics. This includes the basic design and layout of the device, halo doping effects, VT adjusts and strain effects.
Devices used for analog circuits may, and all high voltage devices have asymmetrical source and drain structures. This is because the source will not be biased more than a small voltage (say < 5 V) above the bulk, and VGS will not exceed a similar small value. However the drain may need to withstand very high voltages (to 1000 V) -- therefore it needs a lighter doping than the source (and portions of it need to be spaced further aways from the gate structure).
For HV devices, this has the effect of adding a significant resistance in series with the drain (which is not present in the source side). This alone gives a different DC characteristic to the device. The additional capacitance associated with the drain gives a different AC characteristic. |
H: SN74LV4052APW as UART Switch
I am using SN74LV4052APW as UART switch with ESP32-S2 SoC Design. I have 3X UART in the design but since ESP32-S2 supports only two UART channels so I had to use this electronic switch to switch between 2 UARTs. One UART is for Firmware upload via USB and 2nd UART is connected to a dispenser. I am attaching my schematic and Channel select diagram from datasheet.
Will it work fine?
AI: With your circuit, you need to add pull-ups to your TXD1 and TXD2 lines so that they are not floating when they are not connected to the common TX line. Other than that, I don't see anything wrong logic-wise, and the switching speed of your device seems fast enough for typical UART baud rates. If you're using controlled impedance traces, the ON resistance of the analog switches may complicate things.
Instead of an analog switch, you can use a digital 2-line to 1-line data selector such as the 74LVC157, which incorporates 4 selector circuits controlled by the same A/B and enable pins.
The 74LVC157 could be wired as follows for your application (DOUBLE-CHECK, NOT TESTED):
IC Pin
Connection
1A
MCU TX
1B
VCC
1Y
TXD1
2A
VCC
2B
MCU TX
2Y
TXD2
3A
RXD1
3B
RXD2
3Y
MCU RX
4A
GND or VCC
4B
GND or VCC
4Y
Not connected
nG
GND
nA/B
MCU A/B select output
The truth table would be:
nA/B
MCU RX
TXDA
TXDB
L
RXDA
MCU TX
H
H
RXDB
H
MCU TX
If supply current is important for your application, the supply current of a TI SN74LVC157A is only 1µA @ 25°C, compared to 20µA for the SN74LV4052A. |
H: Capacitance displacement probe guard ring circuitry
I am attempting to build my own capacitance probe for high precision displacement measurements. The working principle is simple - a constant current AC signal (~100kHz) is passed through the probe sensing electrode, and the surface being probed is grounded. As the capacitance between the probe and probed surface changes with distance, the voltage amplitude of the resulting AC signal is directly proportional to the distance.
The circuit for providing the constant current AC signal can be found in literature, so for the sake of this post assume that I already have an AC current source. The probe architecture I have decided on is one with a guard ring as shown below.
From my understanding, the guard ring is held at the same potential as the sensing electrode so it helps ensure the electric field between the sensing electrode and the probed surface is as uniform as possible. My question is how to accomplish this in practice?
Simply connecting the sensing electrode to the guard ring would accomplish this, but it wouldn't work as the edge effects at the guard ring would be included in the measurement, defeating the entire purpose of the guard ring. I am wondering if using an op-amp buffer would work?
AI: You need a buffer amplifier (e.g. opamp connected as a unity gain buffer) to drive the guard from the sensing electrode signal. That way the voltage difference between the guard and the sensing electrode will be (ideally) zero; thus that capacitance won't draw any current and so the guard won't affect the sensed signal.
Note that the opamp will (slightly) load the sensing signal -- you will have to calibrate this out of your system.
Note that there are many sources of error in this type of setup that require care and high performance circuits to get accurate and reproducible results. |
H: Is feedback positive or negative for this closed-loop circuit?
The following is from the book Design of Analog CMOS Integrated Circuit, Page 307.
I think feedback is negative in my opinion.
Here is what I think, see picture below.
AI: Simple analysis: Have a look at the closed loop (the loop gain with Vin=0) and find the number of signal inversions within the loop. For negative feedback, there must be an uneven number of inversions.
In your example: M1 does not cause a signal inversion between source and droain (common gate principle). However, and M2 in common source operation will cause a 180deg phase shift. T
Therefore, we have negative feedback (one single sign inversion).
Comment to your last figure: For loop gain analysis, you should try to find a node within the loop where a relatively low output resistance is connected to a much larger input resistance.
Then you can open the loop at this point and you can inject a test signal without changing too much the loading conditions at this point. Therefore, open the path at the gate of M2 and inject the test signal BETWEEN the drain node of M1 and the gate of M2. This is important, in particular, for loop gain simulation because otherwise you would destroy the DC operational point of the circuit.
However, for a rough loop gain analysis (visual inspection only) you can use the scheme as shown in the figure: Test voltage Vf at the gate of M2 and output at the drain of M1 (with Vin=0). |
H: Voltage follower generates voltage by itself
I am currently working on a project that requires me to measure a capacitor voltage that can reach up to 250 V.
To measure such a high voltage I first created a voltage divider with very high resistor values so the capacitor doesn't discharge very fast (resistor1 = 10 MΩ, resistor2 = 200 kΩ). The problem is that with such high resistor values the Arduino doesn't measure the voltage exactly, since the max. resistor recommendation for the Arduino ADC is 10 kΩ.
I decided to wire an op-amp as a voltage follower to have lower impedance on the output, but the voltage follower doesn't measure capacitor voltages lower than 100 V (or 1.96 V after the divider) and what happens is that, when the voltage falls below that, the follower produces a small voltage by itself (around 1.9 V), thus tricking the Arduino into calculating the wrong voltage of the capacitor. The op-amp I'm using is the UA741 and I'm powering it with single rail supply.
Does anyone know why the voltage follower doesn't work?
AI: The output of the 741 can't get closer to the rails than about 2 V, so with a single supply of, say, 0 and 12 V, the output would be limited to between about 2 and 10 V.
You could use a split supply, but it would be easier to use a rail-to-rail op-amp, and avoid the obsolete 741.
You could also try smaller voltage divider resistors.
BTW: The recommendation for the ADC is what it is, but the standard Arduino library for the ADC allows a very long time for the ADC to settle (which is why it is slow when you use the default settings), so you can get away with a higher impedance than the recommendation. |
H: Confused about skin effect
Why skin effect is respected when it comes to transformers but not to filters, even when they are dealing with same high frequencies?
For example, in full bridge SMPS, with more than 100 kHz, we found that the wire thickness is too small in transformer and too thick in the output filter.
Image source
AI: The product photo shown in your question is an 800W (400V in, 12V out) ZVS full bridge converter. The inductor you marked is the output choke. The answer below applies to DC-DC converters in general and buck-derived topologies specifically.
Why skin effect is respected when it comes to transformers but not to filters, even when they are dealing with same high frequencies?
The current flowing through the output choke has two components:
The DC component, which is the output current that flows to the load
The AC component, which is the ripple current that flows through the output capacitor(s)
For DC-DC converter applications, the amplitude of this ripple is generally much lower than the DC component (usually between 10% and 40% of the DC current but depends on the application). Therefore, the copper loss component due to the AC current and the skin effect is generally much lower compared to the core loss or the DC copper loss (If the operation mode is DCM the amplitude drops further therefore the loss becomes much less).
Img Src
The inductor shown in the product photo has a DC resistance of 1 mOhm. Since the output current is 67 ADC, the copper loss due to the DC current will be 4.5 W. If we assume the ripple current is 5 App (peak-to-peak), the RMS current of the ripple will be ~1.5 A. Even if we assume the AC resistance peaks up to 100 mOhm which is a very pessimistic guess, the AC copper loss becomes approx 0.23 W.
But for the main transformer, especially for the primary winding, the entire copper loss comes from the AC current and the skin effect. So the designer should be more careful when designing the transformer windings. |
H: How can I drive an LC tank with a transistor?
I've been exploring the idea of making an induction heater.
Mostly I see people using the ZVS circuit to do it, but I would like to get an understanding as to how you would do it if you had an ADC and a microcontroller (where you could switch the transistor/s at any given point in the wave).
I've read Can a PWM source be used to drive an LC circuit to get it to resonate? and Question - LC Tank - Resonance , Duty Cycle , Back EMF.
In both questions there's user Andy aka showing a circuit with a transistor driving the LC tank on the low side. I recreated it in falstad:
The 2.5μH and ~1μF do resonate at 100kHz.
However, no matter what I do, I can never get the voltage within the LC circuit to go above the supply voltage. The swing across the inductor is ±5v which means that there is at most 10V at the collector. It always looks like this (green is voltage across inductor/capacitor, yellow is current through the inductor, red is the pulses):
(voltage and current are not 1:1 in terms of scale due to some automatic scaling falstad does)
It seems the oscillation always 'synchronizes' with the pulses, such that the transistor only conducts when the voltage across the capacitor is the same as the supply voltage. This ultimately makes it have no effect on the current, because the inductor is still getting the same voltage across it that it would get from the capacitor alone.
Seems to me like the more opportune time to turn on the transistor is the point where the capacitor voltage is equal to the supply (so the capacitor isn't disturbed), and the current is increasing:
Here the current should also keep it's slope as the voltage across the inductor doesn't change.
I tried this manually by just manually switching a switch, and it seems to work:
The resistor is to simulate losses.
In the aforementioned scenario where an ADC is used (or I suppose a comparator could achieve the same goal) with a microcontroller, this could be the point at which to do the switching. The only issue I see with doing so is that it would reduce frequency based on how long it was switched on.
Am I doing something wrong that my simulation doesn't work like Andy aka's?
Is the above switching 'moment' the appropriate one if the goal is to get as much amplitude as possible? Or for an induction heater application?
AI: Without delving into a full design, I'll just contribute some high-level hints:
Presumably, you want high efficiency, so you aren't stuck bolting big transistors to huge heatsinks and making a big linear amplifier for nothing.
Amplifier dissipation is (mostly) the average power dissipated by its transistors. When voltage and current are both high, power is high, and when this happens most of the time, average power is also high.
If we can arrange a circuit so that voltage and current are alternately very close to zero, and only very little time is spent inbetween (when both are simultaneously high), we can push the average down quite far. Almost arbitrarily in fact. That's a big win. It means smaller components, lower cost (to a point), and most of the input power makes it to the output. Cool.
To do this, already assumes some things about the circuit. We need an element connected to the transistor, whose voltage can change ~instantly, without drawing huge current (or change) from the transistor. Conversely, the transistor's current needs to change ~instantly, and we need somewhere for that current to go.
Inductor voltage can change instantly without a corresponding (instant) change in current, so that's promising. We could switch directly into the inductor, then. But a single switch would set the inductor's current to zero as soon as it turns off, and all the inductive energy is lost. (Where? Switch arcing, or transistor avalanche. Even with a truly ideal switch, it'll go into radiation loss or something; only some of which will be the work we're trying to induce power in, so, still efficiency would be poor.)
Note that inductive energy is necessary here: typical induction coils have a loaded Q factor of at least a few, and industrial applications and wireless power transmission can have a Q factor in the 100s. That is, for every watt we want to transmit, we need Q times more VARs circulating in the coil.
VARs are watts, but "sideways": the peak power might be Vrms * Irms, but because V and I are phase-shifted, the power is oscillating up and down around zero average. In terms of dimensional analysis, we're putting volts and amps together but not getting watts, for the same reason torque is a force times a length but isn't mechanical work -- work is when those quantities are parallel, torque when perpendicular.
Anyway, if we use two switches alternating, we can conserve the magnetic energy, recirculating it to a supply. This is a half-bridge direct-drive circuit:
simulate this circuit – Schematic created using CircuitLab
Give the simulation a try. Note that switch currents alternate from negative to positive, i.e. current is fed back into the supply, then draw out later. This is done at low voltage drop, or high voltage and low current when off, so the efficiency is good, at least with respect to putting VAs into the coil.
Downside: the switches have to handle full apparent power (VAs, watts and VARs). We can use transistors in switching mode so it's not a complete freakshow, but it's unsatisfying that we still need so much capacity -- if the Q factor is 10, and we want 100W, we need 1kVA inverter capacity, and we could otherwise get 1kW (or at least a modest fraction, like 1/2 or 1/4 of that capacity) from the same transistors in a conventional DC-DC converter for example. Seems unfair, right? And it's hardly scalable if we want to drive a high-Q inductor.
We can cancel out the inductive reactance by capacitive reactance. We then have a resonant frequency, and sinusoidal voltage and current. Control is more tricky because we have to track resonance, but we don't have to deal with all that reactive power.
We can connect the capacitor in series, or in parallel (or a combination thereof, I suppose). In series, we can change the voltage suddenly (thanks to the inductor, current changes more gradually); in parallel, we can change current suddenly (thanks to the capacitor, voltage changes more gradually).
We can use switches to work with either arrangement, but for reasons I won't go into here, voltage-sourcing inverters are preferred; sort of, more fundamental. So, we would prefer inverter types of voltage-fed push-pull, or half- or full-bridge, with honorable mention to quarter-bridge and class E types.
So, your circuit. The nice part is: comparing to the single-switch case mentioned above, inductive energy does have somewhere to go -- it flies back into the capacitor, and resonates (as your simulations show, more or less). The problem is turning on: if we open and close the switch arbitrarily, at some rates we will find residual charge on the capacitor; switching on into the capacitor ~instantly discharges it, and thus its energy (the energy difference from whatever voltage it had, to whatever voltage the transistor is forcing it to) is dissipated in the switch, while a huge gulp of current flows. This is bad. We can control the switching such that this is avoided most of the time, but it still must occur at least at startup, and we don't get much control over what it's doing -- the capacitor voltage has to be charged to at least the supply voltage in order for the switching transistor to saturate (reach a low voltage drop). We can't have less power than this, unless we skip pulses and just wait.
Such circuits do find use -- primarily where the control range is not an issue, and the startup impulse happens infrequently enough to tolerate. Induction cooktops are typically such an example. See:
Help me to understand the working of induction cooker circuit
and related topics. A class-E circuit is used, which is like a flyback circuit, but instead of clamping the voltage with a diode, it resonates into the capacitor; the switch voltage waveform is basically a free-ringdown wave, truncated to show only the top part, repeated every cycle inbetween a flat charging period. It's quasi-resonant, because the actual operating frequency is below resonance: during the switch-on time, the inductor is charged with current, reaching a peak current proportional to on-time. Thus as frequency goes lower, power goes higher; but off-time must be kept constant, corresponding to the flyback phase of the waveform.
Note that, because the switch drives the inductor directly for part of the cycle, this technique isn't very scalable to higher Q loads -- it's typically used for low-Q loads. Cooktop coils typically have a loaded Q of 3-10, so this isn't a bad compromise; a bit of extra switch capacity is required, but only one switch (and drive and control circuit) is needed, so it's cost-effective.
For general use and experimentation, I would recommend something a little safer to operate. As long as you avoid shoot-through (both switches on simultaneously; this can be enforced by choice of drive IC), the half-bridge circuit, with a series resonant tank circuit, can be driven above or below resonance, with a relatively small penalty in power dissipation below resonance (where hard switching occurs). An example:
Source: Breadboarded_Induction_Test.pdf | Seven Transistor Labs, LLC (disclosure: my site)
Discussion thread: Simple induction heater - T3sl4co1l | EEVblog Forum
C3/C6 makes a virtual ground point, allowing single-supply operation instead of the double voltage sources shown above. Alternately, these can be two halves of the resonant capacitor (they act in parallel), with the bulk capacitors moved across the supply (+15/GND) rails. (Bulk bypass, across the supplies, is required regardless. The series combo C3/C6 serves this purpose as well.)
C4 needs to be a high-Q type; polypropylene is preferred. Note that a 555 timer can generate the waveform if you don't have a signal generator handy. Also the transistor inverter can be eliminated if a complementary type driver is used (various in the IR21xx family and others apply). IR2101 is a direct type, no deadtime included, so C7 and C8 here provide a little turn-on delay to prevent shoot-through.
A control circuit is greatly encouraged before scaling this up in power -- fixed frequency means wildly uncontrolled power output, depending on what the load and tuning is. Control design is a huge topic unto itself, but the upside is, everything this circuit does, a larger one will do, but you have the relative safety of nothing blowing up -- or if you badly abuse the transistors, just cheap ones fried, or some melted breadboards or smoked coils.
I would consider current feedback and phase limit as minimal requirements, with power feedback a plus, and peak current and desat fault protection as nice-to-haves, and a requirement above a few kW. |
H: Mounting an 11W SCR with a Flat Profile
I have two SCRs in my design that will be switching up to 15A at 120-240VAC. The two devices will split the power, with each one conducting a half cycle. I'm considering using the S6025 by Littelfuse.
The power through each device works out to...
(15A * 1.5V) / 2 = 11.25W per device
I'd like a flatter profile for my PCB so it can fit in a slim enclosure. I'm considering a few options...
Using a D2Pak. I'm skeptical of a D2Pak carrying so much power because the metal tab is connected to the PCB, not a heat sink. Can this be done?
Mounting a TO220 like a D2Pak but with with the metal tab upwards and attached to a heat sink (see diagram). The leads of the TO220 don't seem to have enough clearance to get past an NRTL. They're only ~1.44mm apart in the worst case.
Edit: Just to clarify, I believe both the clearances from leads to heatsink and leads to other leads aren't enough.
Using an alternative, wider-pitched package like TOP-3 or TO-247. These cost ~3-10x as much as the TO220 alternatives.
Is there a cost-effective way to dissipate 11.25W from an SCR without a TO220 standing 2cm tall?
AI: Yes, this is fine. Note that you should leave a fairly large hole in the PCB to provide access for the screw and screwdriver, which may make routing more challenging. Alternately, position the device near the board edge, so the screw can be accessed freely (almost as shown).
If insulation is required, the usual route is a thermal pad, with shoulder washer for the screw. With isolated tab an option, the shoulder washer could be omitted, and insulation used just for clearance around the leads if needed (or if thermal pad is more convenient for manufacturing than grease).
Another option is to use spring retention, like these,
MAX07NG Aavid, Thermal Division of Boyd Corporation | Digikey
combined with a thermal pad (plain, no hole). You might prefer the non-isolated version SCR for slightly lower RthJC, which helps make up for the higher resistance of the thermal pad.
The PCB itself can also be used as mounting clamp, though it's a bit sketchy because of straining the board (makes putting ceramic capacitors nearby problematic, for example), plus board material isn't great at retaining stress (FR-4 cold-flows a bit). A typical build might flank the component with two screws into the heatsink. On the upside, this scales well when a row of devices needs to be clamped down, since a screw can sit inbetween pairs.
If the problem is clearance around the leads, partial potting might be considered. It could be gooped around just the base of the part; probably an approved application and inspection process will be needed.
As for SMTs, I wouldn't recommend it for this power level. You need thermal vias and enough pour area to spread out the heat, until it can get into a thermal pad and the bulk heatsink. It's good up to 5W or so, but 10 would be pushing it. Potential improvements include: thinner PCB (shorter vias, lower Rth from board material itself), heavier plating (e.g. 1oz foil plated 2oz+, thus leaving heavy walls in the vias), heavier copper in general (spread heat out further in the first place), heat spreader components around the tab (whether bits of SMT metal, or those AlN chips -- the latter are probably too expensive, but interesting especially where isolation is required), etc. Enough such improvements should get you there, but maybe that starts to drive the fab cost up as well, and you'll want to compare quotes versus other assembly methods.
There's also metal-core PCB. Limitations are few layers (preferably just one!), and possibly poor insulation between conductor and core (I haven't checked offhand what typical ratings are; enough for nominal voltage, but safety I'm not sure?). If nothing else, it could be useful as a heat spreader -- treat the core as live, and use a thermal pad between it and the heatsink.
Also, to avoid clamping forces and hardware, you might consider a bonding TIM like this,
BERGQUIST BOND PLY TBP 1400LMS-HD Technical Data Sheet
parts can be clamped in place (perhaps with a jig for accurate positioning) and is self-adhesive to start, then can be cured for a permanent bond. |
H: Active crossover filter for AB AMP
I want to use a STA540 amplifier IC in Stereo plus bridge configuration (page 11, figure 6).
The idea is to have the chip drive two 4 Ohm tweeters and one 8 ohm Mid/Woofer.
Since passive crossover are quite expensive, I thought of using an active one before amplification. Could this work? Are there any fall backs?
The input signal comes from a Baxandall active volume control (not shown) and is biased at VCC/2.
VCC is 16V to aim to:
1x16W into 8 Ohm and
2x8W into 4 Ohm
AI: Yes, this will work. It is essentially equivalent if the crossover (filter) is before or after the amplifier.
Basically the crossover is a filter. However the common implementations do have dependency on the source and load impedance driving it, so the same component values used in the load end won't work equivalently when placed in the source (e.g. amplifier input) end of the signal chain. |
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