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H: How many amperes to choose for a Schottky diode after a current limiting power supply?
I have a power supply (original Raspberry Pi power supply, datasheet) with 5.1 V which delivers up to 3 A. In case of a short-circuit or if more than ~ 3.4 A is drawn, the power supply will change to a short-circuit state.
This behaviour is used for a simple reverse voltage protection. A Schottky diode is placed anti-parallel and therefore will cause a short-circuit in case of reversed polarity. It will draw all the current and cause a high voltage drop below 0.3 V and so will protect the circuit.
The question though is, how many amperes do I need for the Schottky diode considering that the power supply will switch to a short-circuit state in that case? I consider that the diode will only get the ~ 3.4 A for milliseconds. Will I really need a diode with >= 3 A or isn't a diode with 1 A also be enough?
The Schottky diode I use is this one (SB 140 DIO, 40 V, 1 A), see datasheet. I also have one with 5 A, but I doubt if such a huge diode is really required.
AI: The conservative (i.e. worst case) assumption is that a power supply that's shorted becomes a current source: it will provide 3A continuously as long as the output voltage is below the nominal.
Switching power supplies may well revert to a pulsed mode of operation when their output is short-circuited, but you can't depend on that if you want to be robust (otherwise why have the diode at all).
So, the diode needs to be sized for continuous 3A operation.
Instead, I'd suggest using an ideal diode IC on the input. These days they are cheap and plentiful. Then you won't be shorting the power supply. And if you use four ideal diodes, you can have a full bridge, and won't even care about what the supply polarity is :) |
H: What material exactly is used in the shiny antistatic bags?
I have another question, and in discussing the root cause of the issue there with an experienced RF engineer, he suggested placing a piece of antistatic ziplock component bag between the two most important PCBs (the GPRS PCB and the main PCB with the affected sensors). This was in attempt to attenuate the signal induced onto the main board, if that was the culprit.
We cut out a piece of a Farnell component bag, which is made of opaque silvery-reflective material (I think it's called conductive antistatic bag - like the one on the right here), and shaped it so to snugly fit the underside of the GPRS PCB, with a cutout for the only header between the PCBs. Probing the bag material with a multimeter, we found it is non-conductive, i.e. likely covered in a thin plastic layer, so we weren't worried about shorts. We placed it and tested the device. The problem practically disappeared, so we can now subdivide and cover only a part of the area below the GPRS PCB to pinpoint the offending location, or the affected trace below.
Yet, the RF engineer asked whether we grounded the "shield" we made with the antistatic bag. We didn't and I thought that would be an easy experiment to do, but I found it impossible to connect electrically to the shiny material, which I thought was some kind of metal foil. We melted the plastic with a soldering iron, and tried puncturing the bag, as to expose the metal. But again, the DMM is showing infinite resistance, and even trying with a lab PSU at 20, 35, 50V shows no current flowing when the probes touch the shiny material. We punctured the bag with the probes so the probes can touch all layers. Still no conductivity even at 50V.
So the question is - what material is this bag really made of? Why can't we connect to it electrically?
AI: Its usually made from mylar (plastic) that is coated with a metal (usually aluminum) which forms a thin conductive layer on the plastic ( the correct term is metallized mylar). They take plastic and then coat it with a very thin layer of metal with a chemical vapor deposition process. This layer is only nm - um thick so there isn't any conductivity that can carry current from a meter. But it is enough to dissipate static.
I couldn't find any scientific papers of metalized mylar in the MHz/GHz range, but there is could be enough metal there to conduct RF. In that case the high frequency RF could be reflected or absorbed by the metalized mylar.
You can't do a conductivity test with a meter because the resistance is more than the meter can measure, probably in the 100MΩ's to 1GΩ range. It might also be that the outside aluminum oxide layer is oxidized in which it wouldn't be conductive but the small layer of aluminum on the inside is conductive. You might be able to measure the conductivity of mylar if it has a very thick layer. |
H: Ideal diode IC (TPS2419D) not working
I have recently integrated an ideal diode circuit based on the TPS2419D chip from TI.
The schematic is the following:
When I apply 48 V to the input of the DC/DC, I do get 12 V at the output of the DC/DC, but almost nothing at the output of the ideal diode.
I've probed the values in this phase and they are like this :
pin1 (RSET): 0 V
pin2 (EN): 3.017 V
pin3: 0 V
pin4 (GND): 0 V
pin5 (GATE): 0 V
pin6 (C): 0.1 V
pin7 (A): 12 V
pin8 (BYP): 10.88 V
As I've discovered (not on purpose), if I shunt pin 6 & pin 7 briefly, the circuit will "wake-up" and I get 12 V at the output.
I've put a mild load (0.5 A) and it seems to work, but as soon as I unplug it the circuit has to be "woken up" again.
I'm a bit lost so any leads will be appreciated.
ADDENDUM (15/03/23) :
After @Tom-Carpenter pointed out that my FET was the wrong way around, I managed to cobble a test circuit together.
However, the circuit remains unfunctional.
the FET might have been damaged in the rework process but I doubt it.
I now obviously get a voltage at the output of the MOSFET all the time at the +12 V out, but it's more than likely the body diode conducting since I get a steep voltage drop (11.4 V with 12.05 V before the FET) even at very low current.
Also, the gate voltage is only 12 V (referenced to ground) so Vgs is not where it should it be, correct?
The voltage at pin 8 (BYP) is 22 V so it seems like the bootstrap/charge-pump is working, but why doesn't it drive the gate?
Last but not least: when I use it as a blocking diode (U_post_mosfet > U_pre_mosfet), the MOSFET heats up quite quickly and I get a rapid clicking noise (2 Hz maybe), not exactly the behaviour I expected.
AI: As can be seen from the typical application schematic in the datasheet, your MOSFET is wired up backwards:
The source should go to the input (voltage source), and the drain to the output. However, you have connected the source to the output.
As to why it starts working if you briefly short the A-C pins together, this is because the C pin is what is actually powering the ideal diode controller.
C is both the cathode voltage sense and the bias supply for the gate-drive charge pump and other internal circuits. This pin must be connected a source that is 3 V or greater when the external MOSFET is to be turned on
With the MOSFET the correct way round, current can flow through the body diode from the input to the output, which in turn applies power to the C pin allowing the device to be turned on using the EN signal.
With the MOSFET reversed, the body diode now points the opposite way and so when the MOSFET is off, no power is applied to the C pin (you measure as 0.1 V showing this).
If you momentarily short out A to C, then you now have power applied to the C pin which allows the device to turn the MOSFET on. As the ideal diode is now in the on state, you are able to remove the short because the device remains powered through the MOSFET.
However, when turned on by this shunting method, your ideal diode is basically backwards and does not function correctly. When off, power can flow through the body diode in the wrong direction. When on, the MOSFET is not being controlled correctly. |
H: Is it right to route AC L/N on different layers on a PCB?
I'm working on a PCB for a trailing-edge dimmer. Is it OK to route the AC live and neutral in opposite layers?
In the image, you can't see the AC neutral (blue), behind the AC_L, but it is there.
This is for a 110 VAC, 1 A per channel. The AC bar in the bottom is 2.5 mm thick (1 oz). I made this bar without the mask, so I can add some solder to increase thickness. I don't know if it is needed though.
This is what it looks like:
If anyone is interested: the project is on GitHub.
AI: FYI, some comments regarding the overall design:
D10/D11 (and similar) aren't needed; the body diode is rated more current than 1N4007, and at lower voltage drop.
MOSFETs aren't rated for fusing current, so it's not obvious that the fuse will open before they fail. (In particular, they will come out of saturation by 30A or so, and fail in under 100µs at that condition; meanwhile, under fault conditions, the fuse can let through over 1kA before opening in a few ms.)
Remember the fuse is only to protect the wiring; if anything else survives, it's only a bonus.
Rectifier diodes, or a thyristor type switch, can survive these conditions; and are typically rated with a fusing I2t so can be designed to survive the let-through of a given fuse. If you wish to have this level of robustness, consider a thyristor (TRIAC) type SSR (which will displace the trailing-edge aspect, of course).
MOV to protect semiconductors is dubious, in general; be careful. In this case, the choice of a 130VAC MOV gives clamping voltage under 700V (MOSFET rating) up to 1kA surge; which is unlikely to be seen by the switch into a typical load. This is acceptable. Notice it will not function on 240V mains, and higher rated MOV, and likely MOSFETs, are required.
Regarding the layout:
Good overall, at a glance! The remaining points are fairly minor.
I wouldn't expose traces for thickening them. Better to just splurge for 2oz copper instead: it's standard proto service at most fabs, and costs little extra.
PCB traces must not break before the fuse does. Fusing ratings aren't easy to find, and I'm not sure that there's a general standard regarding it. Generally speaking, traces designed for low temperature rise (say 10°C at rated current) will handle it fine.
(When inspecting a design for approval, UL (and etc.) will test mains-connected traces for 5× overload or thereabouts, and make recommendations as needed. Trace ampacity depends widely on trace length, heatsinking (connected wide areas / pours, as well as inner copper planes) and spacing, so it's probably easier/more certain to just test everything.)
The ground plane section can be improved some. Pour doesn't need to extend around the isolator pads, improving creepage (this is a minor difference, with the slot there already); the output traces can be grouped tighter under the MCU, staying under the pour (mind the inside corner), and the pin-5 trace can be routed on the bottom.
Several top-side traces can be routed on the bottom to avoid cutting up the plane. The SMT jumpers could be placed closer to J4, avoiding the trace crossing to J4 pins 3/4. ZC and +5V as well. Don't be afraid to use more vias: they're practically free.
The above steps will improve ground continuity, preserving its solidity as a plane. Grounding can be improved further by pouring both layers and adding stitching vias, so that any given stretch of trace is surrounded by a loop closed between top/bottom layers, within say a couple inches. This hardly seems worth it for such a simple board, but can be important on more complicated designs.
Check the PSU datasheet if you should have more bypass/filtering on board (input or output). Typically, SMPS modules are a bit dirty, or skimp on these for space and cost reasons. A full EMI evaluation would be necessary to know for sure how much EMI filtering might be needed, but it would be safe enough to toss in a common-mode choke at its AC input and some Y-type capacitors between AC_N, and GND and/or chassis GND (if available on screws).
Speaking of screws, consider removing copper ring/plating on the one in the middle. Or maybe many of them, if you're not making an electrical connection to them. This improves isolation to AC_N/L at the middle-bottom of the board for example.
A somewhat higher priority note about I2C: it's not good off-board. I suppose for a display, you might not have much choice, but do keep lead lengths to an absolute minimum, and add filtering (and perhaps ESD protection) on both ends of the link if possible. (Very little filtering is possible without greatly compromising bitrate; again, it's not good off-board.) If any length at all is required, use a shielded cable, and preferably use connectors with alternating ground and signal lines (VCC counts as ground for RF purposes). These requirements are relaxed if the project resides inside a metal enclosure, but beware that the display is exposed (you've got to be able to see it..!) so can be struck by ESD either directly, or from nearby conductive objects inducing ESD onto it. An insulating coverlay helps (and in extreme cases, a conductive (fine mesh, metallization, or ITO coated glass) cover can be used, but that's probably overkill here!).
Good luck! |
H: Thevenin Theorem Question
I am supposed to find the Thevenin equivalent of the above circuit. My method was to take the 33 ohm and 10 ohm resistors in series and turn that into a 43 ohm resistor. I then turned the 43 ohm resistor and the 15 ohm resistor into the parallel equivalent, which is exactly 645/58 ohms. I was left with a 20/15 A source in parallel with a 645/58 ohm resistor and a 12 ohm resistor which is in series with a 2 A source. From there, I used source transformation to turn the 20/15 A source into a 430/29 V source, in series with the same 645/58 ohm resistor. The 645/58 ohm resistor is then in series with the 12 ohm resistor, making a 1341/58 ohm resistor. I then turned the voltage source back into a current source, which was in parallel with the 2 A source. I added together these sources together, then turned it back into a voltage source by multiplying the new current source with the 1341/58 ohm resistor and eventually got a Thevenin voltage rounded to 60.1V. The answer is 28.44 V.
I have checked my working multiple times and cannot find the issue. Can someone please tell me what was wrong with my method. Thank you in advance.
This is what the answers did:
AI: You're actually right in your answer. My first comment was about you not having access to terminal B, but it seems that you accounted for it towards the end of your process (Sorry, but I'm not going to decipher exactly what you did from your text).
Here's the path I would have taken to arrive at the same answer. It appears that your teacher made a mistake in step 3) by writing the current divider formula wrong. If you write it with 43 ohms on the numerator, then you get 60V at the end, but this is wrong.
Apply source transformation on the left-most current source and its 15-ohm resistor in parallel -> it'll become a 20V voltage source with a 15 ohm resistor in series.
Apply superposition (find this the easiest): find the voltage drop across the load with respect to the 20V source found in 1). You'll see that the 12-ohm resistor can disregarded because the 2A current source is open. Then, the current through the load is also the current flowing through the 15 and 10 ohm resistor; i.e.:
$$ I_{20V} = \frac{20V}{15\Omega + 33\Omega + 10\Omega} = 0.345A$$
Multiply this current by 33-ohms load to find out its voltage drop. It equals 11.38V.
Now, find the voltage drop across the load due to the 2A current source. We apply superposition again, so the 20V source becomes a short.
You have the following schematic.
simulate this circuit – Schematic created using CircuitLab
We'd like to find out the voltage drop across R4.
To this end, we recognize that R3 also has 2A flowing through it, so we might as well imagine that the 2A current is flowing out R3.
From here, we recognize that there's current division between branches R1 and R4+R2, we can, therefore, write:
$$I_{R4} = 2A \frac{15\Omega}{15\Omega + 33\Omega + 10\Omega} = 0.517A$$
This is, effectively, the current flowing through R4, the 33-ohm load. Multiply to get the voltage and you find 17V. Added to the 11.38V I got earlier you find:
$$ 17V + 11.38V = 28.38V$$
If you write the \$I_{R4}\$ formula with the 33+10ohms on the numerator, then you get 1.48A, which then you'd multiply (erroneously) by 33ohms and you find 48.9V, which added to the 11.38V, equals 60.2V.
Whoever wrote that solution for this problem screwed up. |
H: H-Bridge blows the fuses in my house
Transistors: FDP18N50
Optocouplers: EL817B
I have been struggling with this for several days. I want to make a 230V AC/230V AC inverter that extends the wave to control the speed of a blower. When I have 12VDC from the power supply on the input and a 10W 12V light bulb on the output, everything works fine, but when I put 230V AC on the input (it's actually 247V because I have a photovoltaic system) and a 116W light bulb (eventually it should be an 85W 230V AC motor) on the output, everything burns out and blows the fuses. What am I doing wrong?
I inserted those diodes there because without them the light bulb was very dim and the upper transistors were getting very hot. I don't know why but it works.
Arduino code:
void setup() {
Serial.begin(9600);
pinMode(9, OUTPUT);
pinMode(10, OUTPUT);
}
double val, t;
double freq = 2;
const double pi2 = 2.*3.1415;
const double amplitude = 255;
bool flip = true;
void loop()
{
t = millis();
val = amplitude*sin(pi2*(freq/1000)*t);
if (Serial.available()) {
String txt = Serial.readStringUntil('\n');
txt.replace(",", ".");
freq = txt.toDouble();
Serial.println(freq);
}
if (val > 0) {
if (!flip) {
flip = true;
delayMicroseconds(1);
}
analogWrite(9, val);
analogWrite(10, 0);
}
else {
if (flip) {
flip = false;
delayMicroseconds(1);
}
analogWrite(9, 0);
analogWrite(10, -val);
}
}
Update
After numerous warnings from your side, and especially after seeing the video sent by "@Lorenzo Donati supporting Ukraine", I gave up on create a inverter. I decided to modify the project so that triac control would be sufficient. The controller has been working for several weeks now and I am very satisfied with the results.
I would like to thank everyone for their great interest, your answers were very helpful.
AI: Disclaimer first: what you are doing is dangerous, and will kill you if you so much as look at it the wrong way. Everything I say here is for your education, not because I think you should continue with this project, because I actually think you should not. If you implement anything I suggest here, and something bad happens, like a fire, or damage or injury, that's on you.
Your rectifier setup produces 340V DC, not 240V. That means your H-Bridge is applying +340V, or -340V across the load. I doubt this is what you intended.
Put a fuse somewhere in the path of mains current to protect everything.
The upper transistors in the bridge have common drains, and are operating as source followers. The name says it all, source potential follows gate potential, but a few volts lower. That means +12V at the gate produces about +9V at the source, not +340V. The consequence is that the remaining 331V are between drain and source, and anything over a few milliamps of current through that transistor will fry it very quickly. For example, \$P = IV = 10mA \times 331V = 3.3W\$.
As source followers, not only do you need +343V at the gate to switch them fully on, you also need near 0V to switch them fully off. That's a big ask. Your best bet is to replace both upper transistors with P-channel devices. Then you will require their gates to be +340V to switch them off, and +330V or so to switch them on, a difference of only a few volts.
The lower transistors do not have this problem, because they are connected in "common-source" configuration. The existing arrangement applying 0V or +12V to their gates is sufficient.
I'll illustrate this behaviour difference below. Left is common-source (as used by your lower two transistors), and right is common drain (or source-follower, the configuration employed by your upper transistors):
simulate this circuit – Schematic created using CircuitLab
Here are plots of the input IN (blue), OUT1 (common-source, orange) and OUT2 (source-follower, tan):
The important features of the common-source setup (orange output signal) are:
The output is more "digital", on or off, and extends all the way to each supply potential.
The output is inverted, with respect to the input. Low input, high output, and vice versa.
The main points to note for the source follower (tan output) are:
The output is always 4V below the input, "following" variations in input.
The output is not inverted with respect to the input.
The transistor is never fully on. the output is unable to reach +20V unless the input rises well beyond 20V.
The reason you are tripping breakers is almost certainly because you are failing to ensure that there is never the condition where two MOSFETs on the same side (the two FETS down the left side, or the two right-hand ones) are simultaneously on (even only partially). If that happens, you have a very small resistance across your 340V source, permitting huge currents to flow. This is called shoot-through.
This problem is exacerbated by the fact that your circuit switches MOSFETs off very slowly, causing them to spend considerable time in some intermediate, partially conductive state. This is because gate capacitance in these devices is 2nF or worse, and combined with 10kΩ gate resistances, the gate discharges over a period of about \$R\times C = 2nF \times 10000\Omega = 20\mu s\$. At a guess, I'd say that if you switch these MOSFETS on and off at more than a kilohertz or so, they are going to spend a large percentage of their time partially conductive, causing shoot-through, and getting very hot.
Those issues aside, here's an implementation employing P-channel MOSFETs at the high side:
simulate this circuit
It uses two independent 12V batteries, one for obtaining gate potentials between +340V and +328V (for the upper PMOS transistors), and the other for obtaining gate potentials between 0V and +12V. The additional battery allows us operate the upper MOSFETs with appropriately high gate potentials.
You will require each transistor gate to be driven by its own opto-isolator, since you may no longer connect the gates of diametrically opposed transistors together. Remember, now they are operating at potentials well over 300V different from each other.
I can't stress this enough: don't ever switch M1 and M2 on at the same time, or even allow their transition from one state to the other to overlap. Same goes for M3 and M4. Avoid shoot-through by ensuring all MOSFETs are off prior to switching any MOSFET on. In other words, introduce a delay between switching MOSFETs off and switching others on, a delay we call "dead-time". I estimate that this delay should be at least 20μs, probably longer due to the slow response of the opto-isolators.
I reiterate that what you are trying to do is dangerous, even reckless. I recommend you don't build my circuit, because I haven't tested it, never will, and make no promises about it. The only reason I answered your question is to illustrate some important concepts you should become familiar with. |
H: How can I power a bulb filament with a mixture of series and parallel circuit?
I am trying to power a bulb filament that has a rating of 3.0 V and 2.5 A.
First I made sure the filament worked by powering it with a variable power supply and setting the voltage at 2.5 V:
This was successful in heating the filament and it was drawing a maximum of 2 A.
When trying to do the same with a battery power supply, the filament wouldn't turn on.
The battery pack consists of two sets of NiCd batteries rated at 1.2 V and 1000 mAh connected in series. Those two sets are then connected in parallel.
My thinking is that it should supply the same amount of power because the series circuit will sum the voltage to 2.4 V. Furthermore the parallel circuit will sum the current to 2000 mAh.
I am unsure where I went wrong and would appreciate more insight on how to properly power the bulb.
AI: Furthermore the parallel circuit will sum the current to 2000 mAh.
2000 mAh is the battery capacity, not the output current capability of the battery. A parallel connection does indeed sum the capacities. It will also sum the output currents. Unfortunately you've not told us what the maximum output current is for those cells.
Usually, AA NICds ought to be able to output an amp or more.
Check the contacts in the battery holders for high contact resistance. Are the cells fully charged, and not at the end of their useful life? Check each cell individually with a DMM. |
H: Reverse current blocking for P-channel MOSFET
I'm using a P-channel MOSFET Q57 as a switch for current from VIN_ALW_GATED to +VIN_ALW when VIN_ALW_GATED > 17.259 V.
In case VIN_ALW_GATED was not connected to any reference voltage (floating), and we connect another voltage source to +VIN_ALW, how I can prevent back current to go from the drain of Q57 to the source through the drain-bulk diode? Is this scenario possible?
I'm confused between connecting VIN_ALW_GATE (Gate of Q57) to GND or keep it floating, because, in case VIN_ALW_GATE was connected to GND, and assuming there was leakage current through this bulk-drain diode, it will go to the board GND. I'm trying to compare this with the gate left floating, in which I think there will no be such problem. Is my analysis right?
Simulate this circuit with CircuitLab (Credit to KHFM from my previous question)
AI: If VIN_ALW_GATED is floating and VIN_ALW is connected to a voltage source, there will be a leakage through the drain-bulk diode of Q5 of few mA which I do not expect to cause any other issue. If the few mA (~5mA) leakage current is acceptable, you could live with it.
If you want to avoid this leakage and if a small diode drop is ok, simplest would be to add a diode in series between VIN_ALW and Q57 drain. |
H: USB used for programming
I am working on a design for an STM32F103.
I use a Micro USB-B connector (as you can see in the following picture).
Can I use this USB to program my STM32 or does it only supply the microprocessor with power?
This would be the power supply with a regulator.
AI: The USB port of your STM32F103 can mainly be used for two things:
Provide power to the device
USB communication in case your firmware implements it (be it a serial over USB, a custom protocol, ...)
The USB port can usually not be used to upload firmware, unless:
Your firmware implements uploading a new version of the firmware (using a standard or custom protocol).
You install a special bootloader (e.g. https://github.com/rogerclarkmelbourne/STM32duino-bootloader/tree/master)
Note that such a bootloader is in addition the built-in bootloader and uses part of the flash. It often requires special configuration of the firmware project. The one mentioned above is designed for the Arduino IDE. The first time, it must be uploaded through SWD or serial.
Also note that other STM32 MCU have built-in bootloaders that support USB natively. |
H: Input common-mode offset voltage ranges of op-amp
I'm using an MCP6V81 op-amp.
While trying to understand, I see that the output of the op-amp can't be greater than Vdd and less than Vss. If that's the case, could someone clarify how the common-mode input voltage ranges can be greater than Vdd by 0.3 V and lesser than Vss by 0.2 V? How does the op-amp accept these inputs when the supply limits are exceeded? These values are mentioned in the electrical characteristics table of the datasheet.
From my understanding, the common-mode input voltage of an op-amp is the voltage that is applied to the input terminals of the op-amp. From the above datasheet, it is Vdd + 0.3 V and Vss - 0.2 V.
So, if my power supply terminals are +2 V and -2 V, then how should I give my inputs?
AI: could someone clarify how the common-mode input voltage ranges can be
greater than Vdd by 0.3 V and lesser than Vss by 0.2 V? How does the op-amp accept these inputs when the supply limits are exceeded?
Basic differential amplifiers using NPN
A simple differential input amplifier forms the basis of most (if not all) op-amp input stages. A drawback of this arrangement (when using NPN transistors), is that if the input voltage falls below a certain level (about 2 volts above the negative rail), the NPN transistors can no longer be adequately base-biased and, they don't function.
On the other hand, you can raise the bases of the differential pair to the positive supply voltage and, the input stage operates correctly. Raising the inputs higher than the positive supply voltage is also possible to a certain degree. A simple NPN differential input amplifier: -
Image from Differential Amplifier using Transistors.
However, as the input rises above the positive rail, you start to forward bias the base-collector region and this results in signal inversion; the base directly couples to the collector resistor (via the now forward biased base-collector region) and what was an inverting stage becomes a non-usable non-inverting stage.
So, an NPN differential amplifier can work providing its inputs are in the range of approximately 2 volts above the negative rail to slightly more than the positive rail.
Basic differential amplifiers using PNP
If we then considered a PNP differential input stage (used in well-known devices as the LM324), the opposite is true; the inputs can range from about 2 volts below the positive rail to slightly below the negative rail. LM324: -
Hint - what we would really like is to be able to combine both NPN and PNP differential transistors so that inputs can range from slightly below the negative rail to slightly above the positive rail.
However, this desirable combination isn't usually implemented using NPN or PNP differential input stages but, it is done with MOSFET input stages on many modern op-amp devices.
Rail-to-rail differential amplifiers using MOSFETs
Here's a typical MOSFET input example from the TLV379 data sheet: -
It's quite a bit more complicated than a simple BJT differential amplifier but, hopefully you can see how it works.
if my power supply terminals are +2 V and -2 V, then how should I give
my inputs?
The maximum input range is -2.2 volts to +2.3 volts (for the device that you specified). |
H: MPU6050 ESP32 No Acknowledge
I am struggling to get an acknowledge from the MPU6050 using ESP32 with Arduino framework. I am unable to derive if the problem is hardware or firmware.
I have copied Sparkfun's breakout board schematic, setting the FSYNC, CLKIN and AD0 pins to GND and SDA, SCL and INT to GPIOs 25, 26 and 27 respectively (INT is unused/floating). I am using 2.7 kΩ pull-ups for the I2C lines.
I am using the following code to test the I2C comms:
#include <Wire.h>
#define I2C_SDA 25
#define I2C_SCL 26
void setup() {
Wire.setClock(100000UL);
Wire.begin(I2C_SDA, I2C_SCL);
delay(3000);
Serial.begin(115200);
Serial.println("\nI2C Scanner");
}
void loop() {
byte error, address;
int nDevices;
Serial.println("Scanning...");
nDevices = 0;
for(address = 1; address < 127; address++ ) {
Wire.beginTransmission(address);
error = Wire.endTransmission();
if (error == 0) {
Serial.print("I2C device found at address 0x");
if (address<16) {
Serial.print("0");
}
Serial.println(address,HEX);
nDevices++;
}
else if (error==4) {
Serial.print("Unknow error at address 0x");
if (address<16) {
Serial.print("0");
}
Serial.println(address,HEX);
}
}
if (nDevices == 0) {
Serial.println("No I2C devices found\n");
}
else {
Serial.println("done\n");
}
delay(5000);
}
I have probed the I2C line using a logic analyser. The code behaves as expected but I get no acknowledge.
I have checked that the chip has power, lowered the speed from 200 kHz (default) to 100 kHz. I have tried using internal pull-ups on ESP32 instead of external. I have tried a different MPU6050 chip.
Any help diagnosing would be greatly appreciated.
AI: Your schematic doesn't show any voltage source being connected to the MPU-6050 VLOGIC pin (just a decoupling capacitor connected there).
However the VLOGIC pin must be connected to a suitable voltage source, as it is used by the digital I/O part of the MPU-6050. Without that, the I2C I/O won't work (as you have seen).
Typically VLOGIC would be the I2C supply voltage, where 3.3 V and 1.8 V are common standards, depending on what else is on the I2C bus. In your case (although your schematic doesn't show everything) I think you are running the I2C bus at 3.3 V so just connect VLOGIC to your VDD for the MPU-6050.
From the MPU-6050 datasheet:
On the Sparkfun schematic, you can see there is a net label VIO on the VLOGIC pin, which goes to the VIO terminal on the Sparkfun board's header. That must be connected to a suitable voltage. This seems to not be well-documented by Sparkfun (surprisingly for them) and this omission is mentioned in a review on their product page, which says:
I didn't see anything in the provided documentation from Sparkfun about having to connect the VIO line to a 3V3 source as an IO Reference voltage. This should be documented better. |
H: What is the function of the Zener diode in this BMS schematic?
I am drawing the schematic of a battery management system (BMS) based on the BQ76920. The application circuit in the datasheet shows the MOSFETs for balancing the voltage of each cell:
I compared it with a github project with the same circuit. It uses a Zener diode in paralel to the MOSFET.
What is the purpose of using a Zener diode in this? I have read that Zener diodes conduct energy in reverse polarity instead of rectifier diodes.
Could somebody explain me the operation of the circuit please? How do the MOSFETs perform the balancing process?
AI: What is the function of the Zener diode in this BMS schematic?
The Zener diode limits the peak gate-to-source voltage to around 15 volts typically and, protects the MOSFET's gate-source region from over-voltages. In your particular circuit, a 16 volt Zener diode is used (MMSZ5246B).
I have read that Zener diodes conduct energy in reverse polarity
instead of rectifier diodes.
They conduct current when the "Zener" voltage is exceeded and act as a "shunt" voltage regulator. |
H: Can I run a dedicated power source through along with Ethernet?
Instead of utilizing POE, what if I used a seperate power supply for power and Ethernet for data using 2-pair shielded Cat5. Has anybody ever tried this, or thought of it? Are there any theoretical problems?
AI: It have to be done in a way it is safe. This means, if you connect your power-RJ45 connector/cable to an ordinary socket, then nothing should happen.
If you have a RJ45 cable, then you have to use one pair TX+ and TX- as GND. RX+ and RX- as +48V. (these wires are very long and have a high resistance, because of this the voltage should be relatively high)
The reason for this is, each pair is connected in the receiver over a little coil and if the voltage on the two wires is the same, then there is no current flow and the coil will not be damaged.
If you connect the cable accidentally to an other network device with POE, then there should not be any current flow in the wrong direction. This means "POE 48V" and "POE GND" have to be on the same position as in the standard-cable.
Look at "10BASE-T, 100BASE-TX mit PoE Alternative B" in the table as an example:
https://de.wikipedia.org/wiki/RJ-Steckverbindung#Anwendungen |
H: USB 5V and 5V AC/DC Power Module protection needed?
Im designing a small board that with have an input 220VAC and with an AC/DC module will generate the 5V for my 5V components and then with a regulator I generate 3.3V for my 3V3 components.
There will be also and a usb to uart interface for development purposes.
The way im going to use this board is firstly with the usb power supply I will power all the components. Does the AC/DC module need a protection for reverse current on its output?
And secondly while the board is working via the ac/dc module, I may need to plug the usb to programm the board. Is it safe or I need some kind of protection in that case too?
UPDATE Question:
Thank you for your advice. I think I will implement an ideal diode OR-ing but with a quick simulation it seems that it doesn't block reverse current in my case. Simulation Here
I think this circuit is for reverse polarity protection? I need reverse current protection?
AI: Does the AC/DC module need a protection for reverse current on its output?
I don't think so. Considering the electrical and mechanical specs, I'm pretty sure this is a flyback regulator. The output has a series diode already, so there's no need to place a diode to block reverse current.
And secondly while the board is working via the ac/dc module, I may need to plug the usb to programm the board. Is it safe or I need some kind of protection in that case too?
No. As I stated above, the flyback regulator has a series diode at its output so there's no need to place another one. D6 allows the circuit to be powered from USB as well, and if you don't want this functionality then you can remove it.
One thing here: USB specification dictates the output voltage to be within 4.75 .. 5.25V range. And the output accuracy of your module is 2% which means the output voltage can be as low as 4.9V. So, if the USB bus voltage is spec max (5.25V) and the module's output voltage is spec-low (4.9V) then D6 will quite possibly be forward biased, so the circuit will be supplied partially by USB as well. This unlikely causes a problem, but if you want the circuit to be supplied from module only then you should consider this. |
H: Sensorless BLDC motor alignment methods
I have been trying to make a FOC for BLDC motor controlling, but I am stuck at the state that before open loop state which single alignment of the motor control. The question and the explanation is below :
I have applied 24V to the motor from a DC source and made motor's phases A(+) and B(-). I was hoping it should be alignment in same position whenever I apply 24V as it says in the documentation.
Documentation that I have been used:
Link 1
Link 2 (video)
The problem is that it is not happening as it should be (like the links above.) It always gets to different position and locks itself (I know because I cannot turn it by hand.) How can solve this issue? I want to obtain same certain position every time like in these documents.
AI: I want to obtain same certain position every time like in these documents.
You do, and you don't :)
The position is indeed the same every time, but it's the electrical position. There is usually more than one equivalent electrical position across one revolution. That number of those repeating positions also called the number of electromagnetic or "electrical" poles.
The FOC sees the motor in terms of this electrical position, not the mechanical position, so everything is all right. There's no reason to expect the same mechanical position every time - it's not needed to get the FOC going, as long as the starting electrical position is the same. So far from what you described it works just as it should! |
H: 741 in non inverting - single +5V suppl;y?
I need to amplify a +1mV to +100mV input with a gain of 10.
I was thinking of using a 741 with this circuit
https://www.electronics-tutorials.ws/opamp/opamp_3.html
The specs say it's dual supply, however I don't ever remember using them with anything other than a single supply (over 20 years ago).
Will the above circuit work with a single +5v supply?
AI: Wrong tool for the job. The 741 doesn’t have enough reserve swing to work on low voltage.
The LM324 is a better old-school choice for single ended low voltage operation. Go newer and you can choose much superior op-amps that offer even wider swing on a single ended supply, such as the LMV324. |
H: XL4016e1 maximum input current
I have an XL4016e1 dc-dc converter circuit,
the output of the circuit is 12V 6 A .
What should be the current value of the power supply to obtain this current?
thanks
AI: This is a step down converter. Refer to the 24 volt to 12 volt, 6A example in the datasheet.
The power efficiency \$\eta\$ is given at 93%.
The power relationship is
$$P_{in}=\frac{P_{out}}{\eta}=\frac{(12)(6)}{0.93}=77\text{W}$$
Roughly then the input current is
$$I_{in}=\frac{P_{in}}{V_{in}}=\frac{77}{24}\approx3.2\text{A}$$
Of course if your input voltage is different( the efficiency may depend on input voltage), then the input current will be different as well.
From the comments:
I am considering using a 36 V 10 A power supply
A 36V input would require only 2.2 A. |
H: Identify part and how/where to order it from
I'm trying to fix a board in my overhead fan unit above my oven (there was a power event at the house). I have located the chip that was burned, but couldn't identify the chip.
I was forced to purchase the replacement board and now have a good ID on the part needed. I would like to try and repair the old one, and if possible swap it back in the unit and sell the now nearly new one.
So could someone please help me identify the chip? I can see ST1S14 but I'm not sure what the 8202 means. I just want to buy the correct part. Here's the pictures of the old and new chips.
AI: From the part number it appears to be a ST1S14, switching regulator.
That identifies the part, as for where to buy it, buying recommendations are considered off topic but you should be able to find it yourself. |
H: Why are the voltage ratings of switch contacts so much lower than breakdown voltage?
I need a switch for a high voltage application, say 5 kV, and I'm looking at relays. From a breakdown voltage standpoint, a contact with a 5 mm gap should be able to withstand 15 kV, which is 3x what I need, so I figure it should be fine. Yet the rated voltage of the contacts is far lower, in the 100's of volts.
Are there rules that are not directly technical in nature that mandate a manufacturer must rate a switch lower? For instance, does law or UL have guidelines that spell out how much a switch can be rated for?
I figure (perhaps naively) a factor of 5 ought to be enough to shut current off, but is that true? Does it need to be more like a factor of 20? What am I missing here?
AI: When contacts that are carrying a current are opened there will always be an arc due to the inductance of the circuit. The switch cannot be considered in isolation.
If the contacts are opened then the voltage is applied, the breakdown voltage is not necessarily of the air but of the insulating material used to mount the contacts. Depending on the mounting, the most likely path from one contact to another is along the surface of the insulating material.
Again the contacts cannot be considered in isolation.
Both the circuit and the mounting hardware must be included in the analysis of voltage breakdown.
Even though the breakdown rating is indicated for the contacts, it is really for the insulating material that has the lowest breakdown voltage: the air between the contacts or the material holding the contacts.
Update: An HV electric field can compromise the lattice structure of the insulating material throughout the volume. AC HV fields also cause heating which can vaporize chemicals near the surface leaving behind a carbon rich track. This is not caused by current, but the electric field. Jagged tracks are left on the surface of materials like plastic. If these tracks reach from contact to contact then a high current may flow. This is a voltage breakdown effect that will lower the rating
………………………………………
This breakdown voltage can be considerably lower than the breakdown in the air. |
H: Is it possible to use two N-channel MOSFETs as motor driver with one driving and the other being used as a brake?
I have two PSMN7R5-60YLX and also using a IR2101S. I can use the 2101 and the MOSFET to drive the motor just using one of the drivers on the chip. Is the circuit below correct to use one as a brake (the bottom one) as long as I put a small delay before turning on the brake? Would this circuit work without giving me problems?
AI: Yes, you can brake like this, although you should probably add a resistor in series with the drain of Q4 to dissipate the energy that the motor generates while spinning down (it acts as a generator during that time).
There's a huge problem with your circuit, though: You can't actually use the IR2101 to drive the high-side MOSFET like that. The MOSFET will just overheat and die because it gets insufficient gate voltage when the motor is turned on. You need a different MOSFET driver or a floating supply for the bootstrap voltage. Alternatively, you could connect an 18V supply to VB, but that requires your 12V supply to never get any higher than 12V (using a lead-acid battery is out of the question, for example).
Check out this article from Analog Devices for more info on how to wire up the high side driver in an N-MOS-only half-bridge. (You'll have to use a dedicated isolated supply, such as a standard 1W isolated DC/DC brick.) Note that you can't use a regular bootstrap circuit since those can't keep the high-side MOSFET on for extended periods of time. |
H: How does one choose the overdrive voltages of the transistors in a differential amplifier?
Question
Hi there,
So in the following image taken from Razavi, the part highlighted confuses me. He states the sum of all the overdrive voltages in each cascode branch is equal to 1.5V. Now, is this 1.5V because that's Vdd/2, or is that 1.5V because it states previously that node X and Y must swing 1.5V p2p?
For example, if we only were require the output voltage to swing between 1V-2V, how would that affect the equation involving \$V_{OD}\$?
Furthermore, if instead we wanted have the output swing from 2V-3V, we'd best (I assume) bias it so that the common-mode output voltage is 2.5V and have there be a 0.5V p2p swing each way. In that case, what would be the restriction on the overdrive voltage in the same way that it is stated below?
Circuit
AI: The sum of the overdrives must be 1.5V because peak-peak differential output needed is 3V i.e., single-ended peak-peak at X or Y is 1.5Vpp.
VDD minus the single-ended peak-peak swing is the budget available for the overdrives provided the output common mode is set at the right value i.e., mid-point of VDD-VOD7-VOD5 & VOD9+VOD1+VOD3
The moment you constrain the common mode voltage of the output, we need to have additional constraints.
If you say that the single ended output (X or Y) needs to swing between 1-2V, then,
VOD9+VOD1+VOD3 < 1V &
VOD7+VOD5 <1V (i.e., VDD-2V).
If you say that the single ended output (X or Y) needs to swing between 2-3V, then,
VOD9+VOD1+VOD3 < 2V &
VOD7+VOD5 <0V (i.e., VDD-3V). So, this is not possible
In all this discussion, we make a fundamental assumption that you bias the cascode gate at a voltage such that the mirror transistor's VDS is equal to the over-drive voltage. |
H: Value of resistor clarification
I'm using this device - USB2514B
Table 3-3 says that the required resistor value is: "47 - 100 kohm". I assumed that the 47 was 47 ohms and not 47 kohms. I used 10 kohm resistors in my designs. Everything seemed to work OK. Now I have some boards that do not work consistently. I replaced the 10 kohm resistors with 100 kohm and the board works. Does the 47 really mean 47 kohm?
AI: I would read that as [47 to 100] Kohm. Since the unit is only mentioned once, it should apply to both numbers.
Also, looking at the material after Table 3-3, resistor values are shown as "R K Ohm" |
H: Measure a PWM signal with an oscilloscope
I am new to electronics and now I wanted to try to use an oscilloscope to measure a PWM output signal.
I made a simple circuit with a Raspberry Pi Pico microcontroller and connected an LED on a breadboard with a resistor to a GPIO. I wrote some code to use PWM on this GPIO and got the result that I expected, the LED is lit up, but not fully. The frequency I tried to use is 40kHz.
Then I connected my oscilloscope for the first time. It is a GW Instek GDS-1054B. I only use a single channel probe for this task. The only adjustments I made on the oscilloscope is to adjust the vertical scale and the horizontal scale while running.
I expected to see a clear square wave and hopyfully some interesting data about time and frequency, but instead, even when in a stopped mode, I get multiple quite blurry square wave lines. This is the best result I could get when using the scale adjustments. What am I missing? Is this the best it gets? There are almost no useful numbers in the picture. I see a frequency data point, but it seem to change when I change the scale. When I scale out, it seem to be about ~49kHz and when I scale in, it gives me a number around ~2.x kHz - not what I expected to see.
AI: Your trace looks like there's no common ground between the scope and the circuit under test, the Raspberry Pi. I suspect this because the output doesn't have clear 0 or 3.3V levels, possibly indicative of capacitive coupling between disparate grounds.
Make sure your Raspberry Pi's ground and the oscillosope's ground are connected together. You can use the ground clip on the probe to connect to 0V on the Raspberry Pi:
Remember that the 'scope is measuring the difference between two potentials, and so you have to give it two potentials, one which we call "zero volts", or ground, and the other being some signal that varies in potential relative to that zero point.
However, be careful. Once you have connected grounds together, you can't then connect the ground clip on another probe to a different node in the circuit under test, because those inputs all share the same ground, which is connected to mains Earth. There are serious hazards to avoid.
For scope safety tips, watch the video entitled "how not to blow up your oscilloscope", by the legendary Dave Jones, from the EEVBlog. |
H: How to choose an appropriate N-FET for a BMS?
I am drawing an schematic for a battery management system (BMS) based on the BQ76920 and I have trouble with the N-channel FETs. How could I know an appropriate part?
This is the schematic:
I am following the datasheet design guide and it says something about voltage and current but I am confused what is that value in the N-FET datasheet.
This is the text of the design guide:
In a github project that is based in the same chip (BQ76920), the developer uses the PSMN7R0-100BS, but I want to know the considerations to pick another one for reasons such as availability in stock.
The datasheet of the PSMN7R0-100BS is here How could I know that the PSMN7R0-100BS N-FET is appropriate?
AI: First, consider how the MOSFETs are used in the application. They are not switched continuously like in a SMPS, but are used more like a load switch. So dynamic characteristics are less important.
The drain-source voltage rating VDS should be higher than your maximum battery stack voltage and leave some margin for transients. The datasheet suggests 10 V per battery cell, so a minimum VDS requirement of 50 V for the five cells in your schematic.
You also need to consider the maximum current of your application. The current through the MOSFETs will lead to power dissipation of:
$$P=R_{DSon} I^2$$
This will heat up the MOSFETs. Depending on the FET package, you will probably need a heat sink for P > 1 W. Look into thermal resistance (Rth,jc and Rth,ja) if you want to know more. For the linked MOSFET a thermal resistance junction-ambient of 60 K/W is given, meaning 60 degrees temperature rise at 1 W power which is already quite significant.
I would also consider the gate drive voltage that is used. The voltage on REGSRC is used for the gate drive. If REGSRC > 12 V, the gate drive voltage will be limited to 12 V. Pretty much all silicon FETs should be fine with 12 V VGS. |
H: Effective Mass of Electrons
In electronics, the fact that mobility of electrons is higher than the mobility of holes is frequently used. How can we explain this using effective mass of electrons and holes ?
AI: Effective mass is not a good way of thinking about this.
Conduction in both N and P type semiconductors occurs due to the movement of electrons. Holes do not exist as an entity they are the absence of an electron in one of the bonds in the silicon crystal.
In a N type semiconductor the electrons move as free electrons in the conduction band with little impedance to their movement.
In a P type semiconductor the electrons move from bond to bond within the crystal matrix, it takes more energy to achieve that than to move a free electron.
At a simplistic level I think of this as throwing a ball through open air as compared to trying to throw a ball through light twigs. |
H: Voltage loss on drain to source using PSMN7R5-60YLX
I am using a IR2101S to drive a PSMN7R5-60YLX logic level N-channel MOSFET. My battery is 12.59V but the motor is only receiving 7.62 volts. The signal coming out of the IR2101 is exactly 5V to the gate of PSMN7R5-60YLX. Can someone teach me how to read this datasheet to figure out why I'm losing so much voltage?
Here is my schematic:
AI: If you are not feeding the gate driver IC with a PWM signal, and it's just on all the time (LIN is permanently low), then:
LO should be high, at +12V, not +5V.
The MOSFET should be fully on, even with +5V at its gate.
Since you have 0Ω between LO and the gate, it's not possible to say if the MOSFET is dragging the gate voltage down, or the IR2101 is unable to pull the gate up to +12V. However, since the transistor should be on even with +5V at the gate, and it clearly isn't...
My money is on the MOSFET being dead. |
H: Control 12V 90mA alarm from 2N2222
I have an alarm rated for 12V 90mA. I want to turn the alarm on/off with a 2N2222. The base of the 2N2222 is connected to an ESP32. Circuit diagram is attached. Will it work?
AI: Placing a resistor (10k to 47k) across the base-emitter of Q1 prevents false turn-on in case of a physical disconnection with the Wi-Fi module.
If the wire that connects the alarm to the Q1's collector is long (e.g. >1m) then unwanted spikes can be induced when you turn the alarm off and these spikes can damage Q1. So a diode (silicon such as 1N4148, 1N4007) can be placed: anode to Q1's collector, cathode to 12V (place as close to Q1 as possible).
And finally, make sure R9 is enough to force the Q1 saturate. Calculate R9 for a base current of one tenth to one twentieth of the load current, i.e. 4mA minimum. So R9 can be \$R_9=(3.3-0.6)/0.004=680\Omega\$ but 750R is okay. |
H: When the transistor is working as a closed switch, is the collector current equal to the emitter current?
When the transistor is working as a closed switch like the one to the right in the attached figure, is \$I_{C}=I_{E}\$?
In other words, is \$I_{C}\$ gonna make it down to the ground?
AI: The collector current is slightly (to moderately) less than the emitter current, because the emitter current is the collector current PLUS the base current.
$$I_E = I_C + I_B$$
When a BJT is operated in saturation, as it is when used as a switch, the base current can be 10% (or more) of the emitter current.
When the BJT is not in saturation, the base current may be 0.5% of the emitter current (or even less). |
H: Need help driving the enable pin on a TPS2595 with a voltage divider; not exactly sure which method is better to use
I'm a hobbyist at best, and am trying to overcome the learning curve as far as pull-up and pull-down resistors, N channel transistors and P channel transistors, etc, etc.
I've got a USB Type-C charge module that absolutely will not work correctly unless it has a hard start. It barely ever activates when I give it a soft start (slowly ramping input voltage up from 0). It seems as though it needs a minimum of a 5V hard start for it to power-on correctly. Which stinks, because when the module pulls a load, it will pull the input voltage from my wind turbine down to 4V. If the wind suddenly dies down, the module will drop below 4V and kick off, and it WILL NOT turn back on again unless it receives a 5V hard start like previously mentioned. Due to this, I need something that can switch it on and off with a wide window of hysteresis; at least 1V.
The big issue here is that it's only powered by a wind turbine. So, 99.9% of the time, it's activated with a soft start and never a hard start.
So right now, I'm currently designing a circuit in EasyEDA to allow hard-starting only. It involves using a TPS3700 to sense for a turn-on voltage, and a turn-off voltage. To be safe, I want a turn-on voltage of 5.2V, and a turn-off voltage of 3.8V
I chose the TPS3700 because it has separate high and a low sense features.
I was originally going to have the TPS3700 drive an SR Latch which would switch on a MOSFET, but I also want current limiting and overheat protection, so I went and used a TPS2595 in place of the MOSFET(The TPS2595 has an internal FET).
The challenge I'm facing right now, is the "Enable" pin on the TPS2595. This pin has an on/off threshold voltage of 1.2V, and a max voltage of 7V. Since my wind turbine puts out anything between 3.5V and 18V, I connected a voltage divider to the pin to keep the voltages within spec.
So my main question is:
Is it better to drive the "Enable" pin with an N channel transistor, which would pull the voltage down ahead of the divider through a resistor? Or, would it be better to use a P channel transistor ahead of the divider?
Also: The TPS2595 datasheet says the "Enable" pin must not be left floating.
Here's a link to the TPS2595 datasheet:
https://www.ti.com/lit/gpn/tps2595
Here's a link to the TPS3700 datasheet:
https://www.ti.com/lit/gpn/tps3700
AI: The MMBT3904 (bipolar NPN transistor) should work well as you have it, you may just want to add a resistor (maybe 1k-10k) in series with the base (depending on how it is being driven). An actual N-Channel MOSFET could also be used in place of the NPN (with just a pull down resistor on the gate).
Using a PNP bipolar transistor or a P-Channel MOSFET on the high side of the line would add some complication as these would require a high signal to be in the off state.
To protect the EN line from a possible over voltage just place a 5V Zener diode on the line to GND. With that change you would not need a precision resistor divider, but still use R8 and R13 with values selected just to give the minimum voltage for EN. R10 shouldn't even be needed in any case. |
H: How to find datasheet or pinout for this DC-DC IC? OB2560NAP
I have this power board on a WiFi extender and I'm trying to find the datasheet for this IC.
I believe this is the switching IC that generates the low 3.3V voltage from the high ~220V input voltage after passing through a coil and a capacitor
I cannot find anything for L23371 but I see listings for OB2560NAP online on Google on Chinese sites. I cannot find a datasheet for the chip anywhere - is this some standard chip pinout that I'm perhaps not searching the right words for? or is this chip really that elusive?
AI: It's a chip made by Shanghai-based OB(On-Bright Elec). Datasheet here.
In general the right-hand portion of the part number refers to the package and rated temperature range, and possibly other kinds of variants, so try omitting it.
Here's the pinout of the DIP version, which just doubles up on a couple of the pins (the higher current ones): |
H: Open-loop BLDC motor control using SPWM
I am a student who is still very new to developing sensorless FOC software. What I'm trying to do now is to open-loop control a BLDC motor using SPWM (to get theBEMF values required for the close loop.)
I installed the necessary hardware for this and wrote the software for an STM32F407. The code produces a 10kHz carrier (PWM frequency) and 28Hz reference frequency (240RPM*14pole/120) with 3 phases and 120 degree phase difference between them. I used 3 channels and connected the main pwm channel modulated to the Hin part of the IR2110 and the CHxN to the Lin part (I applied this for 3 separate IR2110s.) On the oscilloscope, I saw the 10kHz carrier I wanted and the 120 degree sines with 28Hz reference.
The motor needs to be rotated by hand at the beginning. Apart from that, the motor continues to rotate at the speed I want. Another problem is that my motor draws currents like 4 amperes and this is a bit too much for me (while rotating.) The motor I have is a 12V BLDC drone motor. If you want, I can share the code I wrote and the hardware I prepared with you.
AI: If I understand you correctly, you are running the motor at 28 Hz, which should produce 240 RPM. The motor will turn at this speed when this frequency is applied if you start it by hand.
First of all, FOC motor controllers must have a start-up algorithm. Your motor cannot instantly achieve 240 RPM from a standing start; accelerating the motor up to running speed requires torque. So you must start it by hand if you are applying a fixed frequency.
The speed of the motor in your design is fixed at 240 Hz; you have correctly calculated the speed-to-frequency using the number of pole pairs. Since the Back EMF is dependent on the speed only, the back EMF is fixed during this experiment. As you increase the duty cycle, the amplitude will exceed the back EMF, and the motor will draw high current.
In FOC, a controller uses the PWM for two functions, to generate sinusoidal current waveforms and to provide the amplitude for speed control. To determine your back EMF, you need to run the motor unloaded (remove propeller if possible) and run at the lowest amplitude you can. In a theoretically perfect motor, the back EMF would equal the drive voltage and the current would be zero when the motor was idling. In real life, some current is required to provide torque to overcome friction, and the back EMF must be exceeded by the drive voltage to account for the voltage drop in the windings from this current.
If you can spin the motor externally, you could measure the back EMF directly since there would be no current in the windings. If you are trying to measure using your setup, get the unloaded motor spinning at the lowest duty cycle you can, then decrease the duty cycle until you stall. This will get you about as close as you can. |
H: Keysight bandwidth and rise time
According to the following application note from Keysight, one way to know what device to take for measuring a signal is to measure the rise time. Then according to the rise time of the system under studies, the bandwidth of the measurement device can be known. The formula is the following :
The 0.35 is only true for a first order transfer function Vout/Vin. Nevertheless, if I took, for example, a differential probe, the transfer function does not look like a first order transfer function:
Is the formula given by Keysight really reaslistic?
AI: It's a rough rule of thumb, not a precise metrology-grade calculation.
The app note you referred to suggests using it to estimate the bandwidth of your signals, and suggests other methods for determining the bandwidth of your probe, such as using a VNA, using a swept sine-wave source, and using a step-response measurement and FFT.
Of course the step response method will require using a step source with a substantially higher bandwidth (or shorter rise time) than the probe you are trying to measure. The differentiation process also tends to enhance high-frequency noise so you may want to use trace averaging in the scope before capturing the data for analysis. |
H: Capacitor for quartz crystal in harmonics
I saw a FM transmitter radio circuit, which was an easy one and had a 20 MHz quartz crystal, on internet. It promised to fix the frequency at 100 MHz. I soldered the components together and tried at home. It worked as expected. As the transmission was online, there was silence in radio. I integrated a sound source to circuit and I could listen to it in radio. The efficiency of the transmitter was about 10 meters.
I know that quartz crystals behave in harmonic frequencies too, like for 20 MHz so in 40, 60, 80 MHz ... I decided to change the 20 MHz crystal with an 8 MHz one. I hoped to get an 88 MHz, which is an 11th harmonic frequency of 8 MHz. This time I had no luck. All I got was a strange sound when I was scratching the pins of my microphone.
After all, I was in doubt of choosing the wrong resistor and capacitor for the circuit. In the example below, the resistor is 47K and the capacitor is a 68pF. The quartz crystal is a hc-49s one.
I know the calculation of cutoff frequency.
$$fc = 1 / (2 * pi * R * C)$$
My question is about the relevance of resistor, capacitor and crystal in circuit. How can this circuit work with these components without problem? Is there a shortcut formula to calculate them? Do these components work like a filter?
AI: Having thought a bit about this circuit, I don't think it is a proper overtone oscillator but, because the OP says "it works" there has to be a reason. Now, it's no use trying to simulate this (unless someone has a model of a crystal that can produce overtone operation) so it's partly guesswork...
...Anyway, the upshot of my contemplation is that you may think that it produces a clean overtone frequency at 100 MHz but, it's more than likely, that the distorted waveform it generates will feed harmonics directly on to the antenna.
This is not the same as an overtone oscillator BTW.
So, there will likely be an infinite diminishing series of "odd" harmonics based at the 20 MHz fundamental that could be picked up at an FM broadcast frequency of 100 MHz (the fifth harmonic). And, there's a pretty good chance that if you could find a receiver that could tune to 60 MHz (the third harmonic), you would also pick-up a signal. You might also receive "even" harmonics (typically 80 MHz) at a lower level.
As an experiment, try putting an oscilloscope on the antenna or the collector (via a 1 kohm resistor) and, look at the waveform. I'll bet it's a distorted 20 MHz square-ish wave. This means that the fifth harmonic (100 MHz) will be quite significant and, will "blank" that region on an FM broadcast receiver.
I integrated a sound source to circuit and I could listen to it in
radio.
This has happened so, why is the big question. Well, the oscillator is basically a badly designed Colpitts oscillator that uses the antenna's capacitance as part of the phase shift network. But the OP also said this: -
I integrated a sound source to circuit and I could listen to it in
radio
It's quite feasible that the BJT's miller capacitance is pulled up and down in value by the audio modulation signal and, this will give rise to a small amount of frequency modulation i.e. the crystal can be pulled and pushed off-centre a little. This is well-known to anyone looking into Colpitts oscillators.
I hoped to get an 88 MHz, which is an 11th harmonic frequency of 8
MHz. This time I had no luck.
The 20 MHz crystal oscillated but, the 8 MHz crystal probably didn't oscillate until you "was scratching the pins of my microphone" and, that may have introduced just enough capacitance to cause it to sporadically oscillate and get something at 88 MHz (11th harmonic).
And, as I said above, if you get an oscilloscope you can check this out. You might also add 20 pF from the antenna connection to ground to see if it kick-starts it into oscillation at 8 MHz. |
H: 9 pin npn transmission relay issue
I've visited this site before never posted until now.
I just recently graduated with a bachelors in electrical engineering, and I'm trying to teach myself car electronics. I ran into this 9 pin relay that is supposed to be for a transmission. however I'm running into an issue when attempting to powering the transistors T2, and T3 in order to activate inductor L1 to close the switch attached to it.
Since this is a vehicle transmission I assume the power inputs are 12V DC.
I tried pin5 at 12V and pin7 at GND, then I tried tapping on and off pin9 with the same power source I plugged to pin5 and I cannot get current to flow from pin 5 to ground to get L1 to activate. maybe there is something simple Im missing. It's the first time I see this type of circuit on my and Im trying to activate it on my own. I assume pin3 triggers the inductors L1 or L2. Ive tried powering pins5, 6, and 9 at the same time, ive tried other configurations and nothing.
I tested the relays by tapping directly accross the inductors and they work. I just cant trigger them with the numbered pins out of the relay.
if anyone could guide me, or show me how to power it up and trigger the relays, I would greatly appreciate it.
enter image description here
AI: Transistor T3 must be turned on (forward biased) in order to conduct current from collector to emitter and energise the coil L1. This means that pin 9, which provides the forward bias current for T3 through R1 and R4, must be "high" (probably at 12V, since this is a 12V relay). Pins 1 and 3 form a diode-logic NAND gate. Any one of these pins being low will pull down the base of T3 (by diverting the bias current through R1 to ground) and turn it off, so both pins 1 and 3 must be "high". |
H: PNP: What happens if the base voltage is higher than the emitter voltage?
Can a PNP transistor switch a 5 volt load such that in the off state the base is supplied with 12 volts and the on state is pulled to ground (Vb > Ve)?
I remember hearing that the base voltage needs to be lower than the emitter voltage, but I do not remember why or what the side effect might be. I think this is just a reverse bias and as long as the reverse bias voltage is below the breakdown voltage then it should work, but please fill in any information that I might be missing here, or best practices that should be considered.
https://crcit.net/c/a9e88922bcae40ce8d8a41e197bc3603
We need to power a 5v LNA at the end of a bias tee when the radio isn't transmitting. It emits 13.8V out the control line while idle, hence PNP. The 100-ohm load in the circuit is the LNA.
AI: The maximum reverse bias on the base-emitter junction is around 6 V for many small signal transistors. You could damage the transistor which may not be obvious at first. Over time, the transistor could become noisier if an over-voltage condition exists at the B-E junction.
A fun thing happens with B-E breakdown, the junction emits light.
[Edit]
Just for fun I cut apart a 2N2222 transistor and took a picture of the glowing reverse biased junction. The breakdown voltage is 7.0 V and current set to 8.8 mA. Barely visible with the naked eye.
right image: ISO=800, f/5.0, 1/25 sec shutter speed
Photo credits: own work |
H: Why P-Ch FETs values are in negative?
I have a doubt about why the P-Channel FET values in the datasheet are negative:
The reason why I am asking about this FETs is that I am drawing the schematic for a Battery Management System based on BQ76920 and the P-Channel FET Q3 is used to keep CHG terminal away from any voltages below VSS according to the datasheet:
I am drawing the schematic based on this github project for guidance but the schematic says (Q4: 30 V, 2.5 A)
Could I use the AO3401A P-CH FET I listed above? (considering the Vds=-30V and Id=-4.0A)
AI: FET parameters are referenced to the source/body terminal. In a p-FET the source/body is connected to a more-positive voltage while in the n-FET it's connected to a more-negative voltage.
For the p-FET to do anything useful, it needs to see gate and drain voltages lower (more negative) than the source, compared to the n-FET where these biases are higher (more positive). The datasheet polarity reflects this fact. (Nevermind that it's possible to have FET drain current in either direction. The datasheet specs here are for the FET operating in 'normal' forward mode, which it is for Q3 in the schematic.)
For example, threshold voltage Vgs for a logic FET might be:
n-channel: gate to source threshold, Vgs(th), 2.5V
p-channel: gate to source threshold, Vgs(th), -2.5V
Same for Vds, Id:
n-channel: drain to source max, Vds(max), 30V
p-channel: drain to source max, Vds(max), -30V
n-channel: drain to source current max, Id(max), 2.5A
p-channel: drain to source current max, Id(max), -2.5A
Bipolar transistors are similar in the NPN and PNP opposite symmetries. Compare for example 2N3904 vs. its PNP complement 2N3906. Similar, but opposite.
As for the drawing, yes, that part will work even though they didn't list (-) values for Vds and Id.
That is, they meant to specify the FET as:
Vgs (max) -30V
Id (max) -2.5A |
H: How to design a schematic and PCB for an ADC using separated grounds
I want to measure a DC voltage with very high resolution (uV) and send the value to a PLC (based on an Arduino Mega.)
Initially I selected an ADS1115, but I got some power noise due to loop currents (discussion in this question). I decided to replace this ADC by another of higher resolution (ADS1219) but I got similar noise as before. I think that the reason could be that both analog/digital grounds are connected on the ADS1219 evaluation board (explained in this question).
As a visual reference, find the following image of possible ADS1219 breakboard (found in here) which does not separate the grounds:
To avoid the evaluation board, I am designing a new board with an ADS1219 where I will separate the grounds. These are my questions:
How do I connect each ground to the rest of the circuit? My idea is to separate both analog and digital parts and include a new connector to have both AGND and DGND, like this image modified by myself but based on the reference circuit mentioned above:
Do the analog and digital ground/paths need special design at PCB level? That is, do they need separated ground planes? Do the traces need to be special, or it is just normal connections as AVDD and DVDD?
Does it make sense to have a digital isolator for the I2C communication? As commented in here it helped a lot with the ADS1115, but I am not sure if it makes sense for the ADS1219 if I separate the grounds.
AI: To avoid the evaluation board, I am designing a new board with an ADS1219 where I will separate the grounds.
The datasheet shows why this is not going to work:
The red circle is around an electrical circuit between the analog and digital parts. Current flows between them. If the grounds are not connected, then you break that circuit and the device doesn't work. If you route the grounds a long distance before connecting them, that current sees a high impedance, which leads to voltage drop and thus noise. The line directly connecting them in the datasheet is to remind you that you must directly connect them as closely as you can.
The datasheet's recommended solution is pretty good
Here is what the datasheet recommends, with the analog parts of the chip shown in red and the digital parts shown in green.
Everything is over single ground plane, but since all the digital currents go down off the bottom, and all the analog currents go up over the top, they're effectively isolated from one another. This gives you a very low impedance connection between analog and digital ground while also making sure that ground currents don't cross between domains. You could be even more elaborate with ground cuts and star grounds, but this simple solution accomplishes the same thing.
What I would do
If absolute lowest cost is not a major factor, and you are ok spending an extra dollar per board, I would make VCC on your connector 5V and run that to the side of the board. I would then put a separate LDO (2 total) for both the analog and digital (on the appropriate half of the board of course) and generate separate clean 3.3V for both AVDD and DVDD right next to where it is needed. Finally, I would split the analog and digital lines into separate connectors, and put each on their respective ends of the board. That way analog ground currents don't meet digital ones at a connector. Finally, I would put one ground per analog line on the analog connector.
Note that a 25 cent part is fine for the digital LDO, and you don't need to buy a very high end part for the analog one either. |
H: Safe Operating Area
This is my LDO. 3A part.
Input is 12V
Output is 5V.
Load current is 2A.
As per Figure 2-41 on page 15, at 85degC, I am limited to 0.2A of max load current.
How can I get the 2A load current with the Vin-Vout of 7V?
If I calculate the Tj of device at this condition, it is = (14*56)+85 = 869degC. That's not within the limits.
I'm actually using a TO-263 package, but I have taken values of 56 thermal resistance for the TO-252 package which is a close one.
Even if 2A load at Vin-Vout=7V is OK from the SOA graph, my Tj is very high. The device is not actually safe, right? What is wrong in my understanding?
AI: If you look at the bottom axis of that chart you see that at a \$V_{in}-V_{out}\$ of 7 V and \$T_A\$ of \$85^\circ C\$ the current is around 1/4 A, so a 2 A load at that voltage is not okay by the SOA graph. Figure 2-42 shows pretty much the same thing. If you want to get 2 A out of it you'd need to reduce the input voltage or maybe heat sink it enough to keep it in the SOA, but that might not be possible. When you look at an SOA chart you want to stay at that horizontal part of the curve before it starts to drop. For high \$V_{in}-V_{out}\$ a switching regulator is generally better. |
H: Can unused USB Type C pins be shorted together?
Can the unused USB Type C connector pins be shorted together?
Can someone please verify if my terminations for the connector pins are correct or do they require modifications?
AI: No. It's not advisable to short them together.
Leave them unconnected. |
H: Origin of the signal in an oscillator composed of a Schmitt trigger and an integrator
Following instructions, we built this oscillator as part of our electronics course:
I was surprised at first that we could get those signals without any initial signal connected to the op-amps input. Is it correct that the op-amp (via the positive feedback on the Schmitt trigger) is simply amplifying random noise (always present in the circuit, for various reasons such as ambient magnetic radiation or temperature gradient which results in movement of 'electrons) until it first flips the switch?
EDIT: I'm only talking about the very first moment the signal is created and the very first flip of the switch. I agree that the regular operation of the Schmitt trigger and the integrator take over without any link with this phenomenon afterward.
AI: Is it correct that the op-amp (via the positive feedback on the
Schmitt trigger) is simply amplifying random noise (always present in
the circuit, for various reasons such as ambient magnetic radiation or
temperature gradient which results in movement of 'electrons) until it
first flips the switch?
No, that is not entirely correct.
Once the circuit has overcome the (theoretical only) initial start-up problem of an op-amp/comparator with positive feedback, the circuit is implicitly unstable without any of the influences you mention It's a type of relaxation oscillator and this link explains about the theoretical unstable equilibrium problem: -
The system is in unstable equilibrium if both the inputs and outputs
of the comparator are at zero volts. The moment any sort of noise, be
it thermal or electromagnetic noise brings the output of the
comparator above zero (the case of the comparator output going below
zero is also possible, and a similar argument to what follows
applies), the positive feedback in the comparator results in the
output of the comparator saturating at the positive rail. |
H: Increase the bandwidth of an RF transformer
I'm building an RF transformer for a custom application (~500KHz to ~5MHz) and my band edges are bumping into the roll off region on the transformer. It's not the end of the world, but it would be nice to increase the bandwidth to avoid this. Is there any practical way to increase the bandwidth of a transformer?
Here's another image showing Vin and Vout.
Edit: There is a very dumb mistake here - I was looking at 500Hz on the plot instead of 500KHz. The overall question regarding transformer bandwidth remains the same though.
AI: Start with a 2nd-order equivalent circuit of a transformer:
T1 is a pair of coupled inductors with \$k = 1\$, equal to the magnetizing inductance of each winding, and giving the desired turns ratio. LLp and LLs (for \$k \rightarrow 1\$, we might pull both together into a single-side-referred equivalent) are the leakage inductance, the flux that isn't shared by both windings. (These are implemented by the \$k\$ factor in SPICE.) Rp and Rs are the winding DC resistances. Together, these give the 1st order transformer model. We can add capacitance Cp, Cs, Ciso1 and Ciso2 to approximate the winding self- and coupled (isolation) capacitances, which manifests because a winding is made of wire, and any two conductors (or portions of one, should it happen to approach itself as in a coil) have capacitance between them.
We can transform this into a common-ground equivalent, ignoring the isolation characteristics for now. In that case, we have:
simulate this circuit – Schematic created using CircuitLab
We can further transform this into LF and HF equivalent circuits, assuming the cutoff points will be far apart (which will be the case in a wideband transformer):
simulate this circuit
Note that these are all primary-referred values; the load resistance and secondary capacitance have been "pulled through" the transformer as their reflected equivalents, and the output voltage is simply assumed to be N2/N1 times the modeled value.
Note also I've replaced Rs and Rp (winding resistances) with source and load resistances, in the assumption that they dominate over the winding resistance (which is a safe assumption as we generally want to design transformers with low insertion loss).
Now we can analyze the two cases.
Low frequency cutoff
Simply the single-pole L/R highpass filter formed by the Thevenin equivalent source and load resistances, and magnetizing inductance. (We can increase accuracy slightly by adding LL with LM, but by the above definitions, LL ≪ LM, so we don't care very much.)
To solve for the -3dB point, we enumerate three convenient conditions:
Source and load termination
Take the Thevenin equivalent, RS || RL. (I'm not writing the turns ratio here; replace RL with the reflected value.) This combines with the magnetizing inductance to give the cutoff: \$F_c = \frac{R_{eq}}{2 \pi L_M}\$. For the special case RS = RL, the cutoff is half what we would expect given the magnitude impedance alone (i.e., we get 25 ohms in a doubly-terminated 50-ohm system).
Source termination (load open-circuit)
Take just RS as the equivalent resistance above. This condition sometimes manifests in amplifier coupling applications, where the input impedance might be high (as in a MOSFET gate or vacuum tube grid). The source resistance defines the bandwidth in this case.
Load termination (source short-circuit)
RS has a minimum value equal to primary winding DCR; of course we cannot achieve the ideal case of zero, but we can approach it using low impedances (such as an op-amp, or with a switching circuit). This does maximize bandwidth, but the low impedance also quickly loses track of magnetizing current and therefore easily saturates the transformer. (Saturation is a nonlinear characteristic which can be covered by a separate question.)
We might also consider the current-mode case (load shorted), in which case the reciprocal of case 3 applies (swap load and source). Likewise for a CCS ("open circuit") source, such as an open-collector (or drain, or pentode plate) amplifier, case 2 applies (swap load and source).
High Frequency Cutoff
We can use the same rubric as above, but notice the network is much more complicated: 3rd order as shown. It might be that one or the other capacitor is negligible (i.e. few turns). It might also be that we do not have three full degrees of freedom, so cannot make an optimal (e.g. named characteristic, e.g. Butterworth etc.) 3rd-order filter here, or that higher-order (inter-layer, inter-turn, or transmission line) effects begin to dominate and our analysis falls apart.
If nothing else, we can still calculate a lower cutoff in terms of the minimum given by any one element (Cp, LL or Cs) with respect to the system impedance, or respective (source or load) impedance if one or the other is short or open. That is, up to this frequency, we can expect flat frequency response; beyond, there may be peaks or dips that are not easy to predict from these (measured or assumed) values, and there may be more (flat within some tolerance) bandwidth available but we cannot predict it so easily beyond this point.
We might also work backwards from some Cp, LL and Cs, and find the bandwidth and characteristic impedance. Again, three parameters do not define these two in a unique manner, but in the event one parameter can be excluded, or all three work together to give a useful filter prototype, we will have a meaningful relation.
The relations are:
\$Z_0 = \sqrt{\frac{L}{C}}\$
\$F_c = \frac{1}{2 \pi \sqrt{L C}}\$
or \$F_c = \frac{R}{2 \pi L}\$ or \$F_c = \frac{1}{2 \pi R C}\$ if an L or C dominates, respectively.
Applying the above termination conditions, we have:
Source and load termination
Potentially all three elements participate. I'm not going to write out a cubic transfer function, nor the analysis of solving for an analytical type -- but suffice it to say, try all the above cases, and you should at least get something close.
LL dominant: Cp and Cs are small enough to ignore. Note that RS and RL act in series, so \$F_c = \frac{R_S + R_L}{2 \pi L_L}\$.
Cp or Cs dominant: \$F_c = \frac{1}{2 \pi R_S C_P}\$, or RL and CS.
We have maximum bandwidth when system and characteristic impedances match, i.e. \$R_S = R_L = Z_0\$, which will have
Source termination (load open-circuit)
LL-Cs acts as a resonant stub upon the input node. This causes a complementary dip and then peak in the voltage gain, where they act to resonate against or with Cp. Bandwidth is maximized when the peak and valley are kept shallow (meaning, \$\sqrt{\frac{L_L}{C_S}} \sim R_S\$; they will differ by a factor depending on the relative value of Cp, which also limits how well damped this response can be).
Load termination (source short-circuit)
We can ignore Cp (it's shorted out!), so Zo and Fc are given by LL and Cs alone. Of course if we're using Zo mismatched to RL, we also have to consider if one or the other element dominates, and may want to address the gain peak (say by adding a snubber network).
As for what dimensions these parameters correspond to, in a real transformer design: it seems that would be well scoped to a separate question.
As a short hint: for transmission line transformer (TLT) type designs, the upper cutoff is simply the electrical length of the windings. So, for say 30MHz bandwidth, less than 10m of wire must be used, and preferably less than 2.5m (maximum length of either winding). The lower cutoff is simply turns and inductivity of the core (\$L_M = N^2 A_L\$). |
H: How do I convert a battery's 3.7 V, 2.7 A input to 24 V, 400 mA output? 12 V, 800 mA would also work
I want to use a single Li-ion cell to drive a 24 V, 10 W PTC heater cartridge in a cost-effective manner with closed loop control from a MCU (RPico + 10 kΩ NTC thermistor).
Is boost or boost-buck suitable here? Are there modules that satisfy the 3 A, 3.7 V specs and are under 10£ (if not, I still would be curious)?
Are there any safety concerns here? Might I need a flyback diode due to induction if doing boost-buck?
I'm not really expecting 96% efficiency. 70%+ is fine.
AI: No reason to do a buck-boost here, a boost will work just fine. The main reason you would use a buck-boost over a boost is if you expect the input voltage to rise above the targeted output voltage.
With such a high voltage gain, you won't get the efficiency you are asking for. The specs you are suggesting would require a 96% efficiency, you'll likely get something closer to 70-80%, depending on what specific IC and inductor you chose.
Also, you do not want to be enabling and disabling the regulator at 10Hz. DC-DC regulators have lots of inductance and capacitance, so they don't switch on and off particularly well. Instead, add a high-side PMOS in series of the output of the regulator and connect that up to the 10Hz PWM signal. This will give you a much cleaner PWM output.
One thing to consider is if you can put some battery cells in series. If your are using multiple Lion cells, putting them in series will allow a much lower voltage gain, allowing increased efficiency and therefore longer battery life. |
H: NAND gate with two vs. one BJT transistor(s)
Why is everybody discourage from this paired NAND BJT Transistor "design"? I already saw a few posts where somebody asked something about the paired BJT NAND "design" and the answers only say: don't do it like this, use only one transistor and as many resistors as you want on the base for the inputs?
When I refer to the one/two BJT circuits, I mean these:
One BJT NOR:
Two BJT NAND:
To list a few:
https://electronics.stackexchange.com/a/72416/334371
https://electronics.stackexchange.com/a/281320/334371
https://electronics.stackexchange.com/a/300116/334371
And a further question, isn't the one BJT Transistor "design" bad, because current can also flow out of the gate input and interfere with other gates?
AI: Practical monolithic 1960s RTL NOR gates used two transistors rather than one (eg. Fairchild \$\mu\$L914). You have to distinguish between something that might work in a given special situation and a general-purpose gate that could be reliably connected (with good fan-out) to outputs of similar gates and would drive inputs of similar gates. Here is what the ca. 1963 NOR gate looked like (1 of two circuits shown):
simulate this circuit – Schematic created using CircuitLab
Claimed (by Fairchild) fan-out was 16, but I would think much more than 4 or 5 would be pushing things in practice because of noise immunity, and variations between chips and variations in temperature. Shown above working with nominal values and perfectly matched transistors, each at exactly the same temperature.
A very similar arrangement but with 3 transistors (also two independent circuits) was used in the Apollo on-board computer. Two 3-input NOR gates in one flat-pack.
Of course you can make a NAND gate with three inverters and a NOR gate. NOR gates are sufficient to implement any logic function (as are NAND gates). |
H: Fast unidirectional level switch from 5 V to 3.3 V
I came up with this circuit. Is it good or bad to use diodes? In my opinion, this is better than a divider or a FET, at least faster, as you can see from the waveforms. Will such a circuit create bounce and noise? My oscilloscope has a bandwidth of 50 MHz and does not accurately measure voltage.
I also tried using a 2.4 V Zener diode, but it has a large capacitance so I got bursts below GND and above 3.3 V.
AI: If you use diodes to drop the voltage from 5V to 3.3V, I see atleast 2 issues:
you cannot achieve a proper level across temperature because the diode drop will vary with temperature.
Other issue is if the 5V supply is at 5.5V (all supplies have tolerance) and 3.3V supply is at 3V, the IN_3V3 voltage will go 800mV higher and create a low impedance path from the 5V supply to the 3.3V supply through the ESD diodes of the destination IC and huge current can flow from 5V supply to 3.3V supply which is a big issue
So, I'd recommend a level shifter IC for this like mentioned by few others in the comments. |
H: Inverting buffer
I want to buffer a signal with a 7404 IC, but this is an inverting IC. With feedback from the input to the output the signal becomes non-inverting again. Is this method correct and can it be used in circuits?
AI: All you're doing there is shorting the input to the output which at best just passes the input through unbuffered, but might also have other unwanted affects.
You can either put two 7404 inverters in series or you can use a non-inverting buffer such as the 7407, although that one is open-collector output so you would need a pullup resistor on the output. You can see a list of some TTL logic ICs here although some may be obsolete. You can also search on one of the electronics suppliers' sites for non-inverting buffers. There are different varieties such as Schmitt trigger, open collector, tri-state outputs, and a number of different logic families for different voltages and speeds. You can learn a lot by looking though some data sheets. |
H: How to automatically change the project name and rev in the output file name in Altium 22
How could I make the project name and rev name change (possibly from the parameters) in the output generation file names in Altium 22?
Right now I rename them individually but that's not very fun.
AI: This can be done in outjob (as you already suspected).
Create a 'container' that configures the output job - like I have for this PDF output:
Right-click on the output container of a manually managed output, and select 'Properties'.
In the pop-up properties window edit the output filename with a mixture of text strings, special strings, and Project Parameters, as you see fit:
My text string, in this case is:
=ProjectName+'_'+VariantName+_+PCBRev+'-'+MinorRev+'.pdf'
(Notice how single characters need not be quote-wrapped. ¯\(ツ)/¯ ) |
H: ESD safe soldering without PE
I live in a very old house that has no PE in it, so I can't ground the tip of the iron and myself as I should to solder in a ESD safe way. Is there any method to improve ESD safety of soldering, when I work with static sensitive components? I have the following idea, and I would like to know if it make any sense:
Connect the tip of the iron (run a wire from the PE pin of the iron inside the soldering station) to ESD mat through 1 MOhm resistor
Connect myself to the ESD mat using a wrist strap that comes with it
A 1MOhm resistor between me and the mat and thevsoldering station should prevent electric shock in case of some disaster inside the soldering station. My potential, potential of the iron, potential of components on the table and PCB I work with should be the same. Right? However we are floating together and we are not grounded.
Questions:
Is this any better then ignoring ESD safety and just hoping for the best? If I leave tip of the iron floating I see a distorted sine signal on the tip of the iron with the scope. Freq: ~60Hz, peak-to-peak: 50V.
What extra safety risks does this approach bring (remember, baseline is a house without PE, this is already not very safe.)
Do you have a better idea how to improve ESD safety in this situation? Building my own PE is not an option - 5th floor, unauthorized construction of this kind can get me in trouble with the law here.
AI: The main thing about ESD is that everything on your workbench should the at same voltage. It's nice if that voltage is ground, but not really that important.
So if you can get an antistatic mat, leads and a wrist strap, then that's a good thing. Even better, connect another lead to the ground of the soldering iron.
For safety, all anti-static leads should have a built-in resistor. Usually about one megohm. |
H: What's the best solution for creating a magnetic field around a small cylinder?
I'm a beginning electronics hobbyist so forgive the naive question.
I'd like to have a small cylinder (1cm radius, 3-4cm length) where I could control a magnetic field around the cylinder with voltage.
Basically, if you were looking down at the circle, I would like to control the clock's hand position magnetically. Is that possible with inexpensive electronic components?
AI: Required geometry is two loop coils, wound longwise around the cylinder:
The windings don't need to cover the top/bottom of the cylinder, they can make a semicircle around to the other side; in that case, group half the turns to one side, and half to the other, so equal numbers of turns make the shape of a full circle on the face but half are carrying current counterclockwise the other half, thus canceling out their field contributions.
This is precisely how an AC motor is wound, albeit in more sections, which gives higher efficiency (efficiency probably won't matter for "twisting a compass needle" sort of applications). You could just as well open up a three-phase two-pole motor, remove the rotor, and use the space within -- with suitable drive of course (namely much lower voltage, as it won't handle rated voltage without the original rotor in place).
To run from an MCU, set up the following system:
In software: generate quadrature i.e. sine and cosine values. These are either driven by an angle setting, or the angle advances at a regular rate (consider a DDS algorithm) to get some spin rate. Or maybe you want to put acceleration or funny waveforms or whatever into it, you can do that at this point as well; you're just inputting an angle in any case.
Send the sin/cos values to a pair of DACs. They will need to be either bipolar output range, or offset around a mean value (in which case add the necessary offset in software). (If you don't need rapid changes, you can use PWM outputs, with an adequately low cutoff lowpass filter to remove most of the ripple.)
Wire the DACs to a pair of transconductance amplifiers (i.e., voltage input, current output). These should be bipolar, and can be single op-amps for example. Power op-amps may be used for additional current capacity.
You'll need either a bipolar power supply, or differential-output amplifiers (or pairs of single-ended type amps, set up to generate complementary outputs i.e. one inverts the voltage of the other) to drive the coils.
What this does:
At the center of each loop, a magnetic field is generated, pointing perpendicular to the plane of the coil. Magnetic field can point in any direction, between all three axes -- it's a vector. Two coils are thus required to generate a field in any direction in one plane, or three to point in any direction, period.
The magnitude (strength) of the field is the sum of applied fields. If you have coils in the same (spacial) direction but opposite direction of current flow, they cancel out; if you have coils at perpendicular angles, the field is the vector sum of their contributions; if the coils are identical (same dimensions, turns, and applied current), and 90° apart, then the vector will point at 45° with magnitude \$\sqrt{2}\$ times a single coil's strength.
Because the angle is, well, an angle, and because the magnitude depends on applied fields in this way, the smoothest motion is had by applying sine waves to each coil, with one being phase-shifted 90° (hence, sine and cosine). The simplest (naive?) approach would be to set one coil to ±max, and vary the other linearly, then set the other to ±max and vary the one, etc.; but this describes a diamond, not a circle, so the angle won't be proportional to the linear fraction, and the magnitude will vary (not that a compass needle will notice, but the varying strength has implications for the smoothness of rotation, and hence is carefully controlled in practical motors).
Or, if you don't care much about smoothness, and want to optimize for speed -- or are going fast enough that smoothness doesn't matter anyway -- the sin/cos waveforms can be smashed into square waves, and you get a quadrature pulse sequence, just as is used to drive a stepper motor (something else to read up on, perhaps).
With the magnetized rotor, this is a PMAC or synchronous machine, by the way! |
H: CAN bus transceiver as I2C differential driver is not working
I am trying to make a differential I2C bus signal that is compatible with SparkFun's QWIIC.
OK: convert the standard I2C's SDA and SCL to TX/RX lines using P82B96D
NOT WORKING: convert TX/RX to differential signals using PCA82C251
Below is the schematic for transforming between the TX/RX signal and the differential signal.
And this is the waveform at SDA1_TX line when the microcontroller is trying to search the bus for a specific address:
As the waveform shows, the SDA1_TX is correctly outputting a 5 V pulse. The other SCL1_TX was also outputting a clock signal in the same way to another PCA82C251, but the differential lines are not outputting any signal. They are just kept at a steady 2.5 V without changing.
What could be causing this problem?
Full schematic of the I2C to dI2C conversion part:
AI: The problem caused by my mistake of setting oscilloscope's trigger level.
The transceiver circuit was working fine.
While debugging, I checked the SDA_RX and SCL_RX pins, too.
To my surprise, the RX lines were repeating the same signal sent to TX lines.
This means, the CAN bus transceiver is working correctly.
These pictures are from SCL_TX (yellow) / SCL_RX (blue) and SDA_TX (yellow) / SDA_RX (blue).
SCL TX/RX
SDA TX/RX
Then I realised that the CAN bus signal level is oscillating around 2~3V and the oscilloscope cannot detect the CAN signal with the default trigger level 0V. (the oscilloscope's ground is contacted to the board's ground pad).
After adjusting the trigger level as 2.5V, I could see the differential signals!
SCL +/-
SDA +/-
With missing just a very basic Oscilloscope setting, I had to waste 2+ hours!
(I tired to replace the PCA82B251 with other CAN bus transceiver chips, SN65HVD232 I had. I tried to adjust the sloping limit resistor, etc. Like in the following picture.)
The above result was not correct, though.
To be correct differential signal, it should be like this at logic 1.
"-" line should raise over "+"
"+" line should fall below "-"
So the two signal should cross each other.
To fix it, I should modify the transceiver circuit a little more.
I'd like to write a blog article about this project and add link here later. |
H: What does a 9 A battery do to a 3 A motor when using the battery for movement?
I am trying to figure out why my battery keeps discharging so quickly. I have a 12 V, 9 Ah (valve regulated) SLA battery that I use on the bench to test motors. I write a small program, test the source, and then attach the hardware while my board is powered down and the motor is not excited.
All electrical is off and I connect the negative from the driver to the battery negative. I then connect the positive from the driver to the positive battery terminal.
At some point the battery, new batteries also, seem to discharge too rapidly.
My driver can handle 4 A maximum and the motor in question can handle 3 A maximum.
After the SBC has the source written to it, I run the program and find that a fairly new, 12 V, 9 Ah SLA battery whimpers at best against the motor and driver along with the SBC challenges.
I have a couple of battery books, but I have not read exactly about the issue at hand in clear text.
I have my driver set to 2.8 A while the motor has a maximum current limit of 3.0 A.
I have no other circuitry outside of what is located in the driver that handles battery technology, chemical makeup, or any other charging/discharging circuitry. The driver is a TB6600.
I think some of the issues I am seeing is that the current is too large for the driver and can't accept enough current as it is overloading it with current.
It is not a deep cycle battery. I see that the driver IC only handles up to 5 A and that is most likely peak current. I may have to downsize batteries or use a PSU with switching characteristics.
Here are some more ideas on the IC and amperage of the driver.
Input Current: 0~5 A
Output Current: 0.5-4.0 A
Control Signal: 3.3~24 V
Power (MAX): 160 W
Micro Step: 1, 2/A, 2/B, 4, 8, 16, 32
Temperature: -10～45℃
Humidity: No Condensation
Dimension: 96*56*33 mm/ 3.78*2.2*1.3 inches
Weight: 0.2 kg
Drive IC: TB67S109AFTG
AI: The Ah/hr rating on a battery tells you how much power you can draw over what time period. The Amp-hour rating tells you that the product of the current drawn and the time drawn will be 9 Ah, so you could draw for instance 100 mA for 90 hours.
The hour rating tells you how much time you can draw that power over, so in this case you can draw 9 Ah over a period of 20 hours. Doing the math:
$$ \frac{9~\mathrm{Ah}}{20~\mathrm{h}} = 0.45~\mathrm{A}$$
So to get the full 20 hours out of it you would have to limit the current draw to 450 mA. |
H: Recommeneded method to monitor rotary position and speed of machinery shaft
I am building a piece of industrial machinery that will operate between 10-200 RPM. I would like to know the rotational position and speed of the shaft (2in diameter steel crankshaft). I am currently considering building a small attachment for my shaft in order to mount on a rotary encoder as pictured below ? I also have considered mounting a trigger wheel with hall effect sens to the shaft as seen in the second picture. I am sure there is a standard procedure for monitoring shaft position in industrial equipment.
AI: I will need an absolute position rotary encoder. There are hollow shaft options that allow the shaft to enter the encoder.
As recommended by the other users, I can use a product similar to these: |
H: Analysing the behaviour of inductor in the circuit
Suppose we have an L circuit with DC power supply of emf \$\mathscr{E}\$
simulate this circuit – Schematic created using CircuitLab
By KVL,
\$\mathscr{E}=L\frac{dI}{dt}\$.
This suggests that \$\frac{dI}{dt}=\frac{\mathscr{E}}{L}\$
As at \$t=0\$, \$I=0\$
So, current increases at a constant rate from \$0\$.
But, I am not able to understand why this is so physically.
My interpretation
The above situation is analogous to the situation in which we have a coil placed between the Helmholtz coil, of which we are increasing the current at constant rate. Thus magnetic field increases at constant rate between the Helmholtz coil so the magnetic flux increases at a constant rate in the first coil and a constant emf will be induced in the first coil by Faraday's law. But in this case, "we" are increasing the current in Helmholtz coil at a constant rate. But how this is achieved in the original circuit?
KVL forces that voltage across the inductor has to be \$\mathscr{E}\$, and then by Faraday's law thus \$\frac{dI}{dt}\$ has to be constant.
But I am not able to understand how this has been achieved in a circuit when we close the switch.
When we close the switch, suddenly the charge carriers gets accelerated and thus \$\frac{dI}{dt}\neq 0\$, but the inductor does not like that. So it will induce emf instantly and when \$V_L=\mathscr{E}\$, \$I=0\$. As that corresponds to opposing batteries of same emf. As long as \$V_L=\mathscr{E}\$, no current in the circuit, thus no change in current and thus \$\frac{dI}{dt}=0\$. So, as a result the inductor's induced voltage will go to \$0\$. When it starts decreasing, \$V_L-\mathscr{E}\neq 0\$, thus \$I\$ starts increasing and \$\frac{dI}{dt}\neq 0\$ but inductor will again increase the induce emf to oppose this \$\frac{dI}{dt}\$. As soon as \$V_L=\mathscr{E}\$, \$I=0\$ again. So, this suggests that \$V_L=\mathscr{E}\$ always, which is also given by KVL.
But this corresponds to \$I=0\$ at all the time. But this leads to the problem that as current is not changing then \$V_L\$ should be \$0\$. But I think that one can argue that as \$V_L\$ starts to decrease from \$\mathscr{E}\$, net voltage in the circuit won't be \$0\$ and this leads to the change in the current and thus to oppose this change in current inductor has to maintain the \$V_L=\mathscr{E}\$. So, the KVL and Faraday's law still holds in the sense to oppose the "tendency" of changing current.
Same is the case of the limiting friction, it won't be 0, till the object has tendency to have a relative motion with the surface. But as the guiding force exceeds the limiting friction the object moves. In that case, there is an upper limit to the value of limiting friction (depends on the type of surface) which when the guiding force exceeds that value, the object starts moving. But here the guiding force is constant (i.e, constant voltage source), the opposing force has no upper limit (i.e, \$V_L\alpha\frac{dI}{dt}\$ which has no upper bound).
But the point is that the above analysis suggests that we have a constant current in the circuit and as at \$t=0\$, \$I=0\$, thus at all other times \$I\$ should be \$0\$. One can give another argument that for \$\frac{dI}{dt}\$ to be non-zero, the charge carriers have to be accelerated, but the net voltage in the circuit is \$0\$. So, there is nothing that accelerates the charge carriers. Thus they move with constant speed, thus passes with same amount through a given area at all the times, thus constitute constant current.
My question is how \$\frac{dI}{dt}\neq 0\$ as suggested by KVL? What actually cause this?
Definitely one can't say that as \$V_L=\mathscr{E}\$, thus \$\frac{dI}{dt}\neq 0\$. This is kind of a circular argument. I have seen several posts and physics books which bypasses the question by making the above argument.
Can somebody please help me in understanding this. I am very confused.
AI: You are over thinkling it. The defining relationship says it all. $$v_{L}=L\frac{di_{L}}{dt}$$
If a voltage is applied across an inductor the current will change at a rate defined by the inductance. The higher the inductance, the slower the rate of change. So the inductance opposes the rate of change but cannot stop it.
If the current is changing in the inductor (for whatever reason) then there will be a voltage across it. The faster the change and the greater the inductance, the higher the voltage that is created. The inductor opposes the rate of change with a voltage, but cannot stop it.
The inductor has no likes or dislikes. Its behaviour is described completely by the defining relation.
Addition to speak to the Helmholtz part of the question.
The above situation is analogous to the situation in which we have a coil placed between the Helmholtz coil, of which we are increasing the current at constant rate
Not so! If there is an inductor with nothing connected and aligned with the magnetic field of the Helmoltz coil, then a voltage will appear scross the inductor by Faraday's Law.$$v=-N\frac{d\phi}{dt}$$
There is no current in the inductor. The inductor is not required for the voltage field to exist. It is alreaady there. Placing the several series connected loops of wire so that they align with the voltage field allows the voltage to be displayed by the wire.
If the inductor is shorted from one terminal to the other a current will appear in the inductor driven by the "induced" voltage.
But how this is achieved in the original circuit?
In the original circuit, an external voltage is applied across the inductor. By Faraday's Law, the rate of change of flux is constrained to a fixed value different from zero.$$\frac{d\phi}{dt}=-\frac{1}{N}V$$
This is like accelerating a mass. The actual velocity can be zero but the acceleration can be very large at the same time.
The applied voltage also places an electric field along the wire accelerating the electrons.
But Farady's Law does not include inductance or current. So let's take a closer look by introducing current into the law by writing:$$v=-N\frac{d\phi}{di}\frac{di}{dt}$$
Inductance can easily be recognized$$L=-N\frac{d\phi}{di}$$as the ability for current to establish a magnetic flux in a region of space. It depends on the medium and the number of turns.
it is not evident what is the cause of constant rate of change of current which leads to a constant emf across the inductor.
So the applied voltage does double duty.
The current is produced by the electric field created by the voltage.
The rate of change of current is constrained by the voltage and the inductance to a fixed value.
The constant emf is because the applied voltage is making it so. The constant applied voltage leads to a constant rate of change of current. Not the other way around. |
H: Is reading multiple buttons presses with ATtiny analog input a reliable method?
I need to read the input from 8 different push buttons on an ATtiny microcontroller.
After researching how to do this with the least number of pins, I found out about using a voltage divider with resistors and reading the input voltage with an analog pin.
This seems to work fine "in the lab", as I'm getting a constant voltage from a power supply or an Arduino.
Now, I was thinking that, since the analog reading is based on the voltage provided, if this voltage changes then the reading won't be the same anymore, right?
I do all my schematics and code using a 3.3 V input, but then I want the final project to run on two 1.5 V batteries connected in series (~3 V). The voltage will be changing depending on the charge of the batteries, so my code won't be able to register the button presses properly anymore.
If this is the case, what solutions or alternative methods can I implement? I don't think using one pin per button is feasible.
AI: The ADC for the ATTiny devices can be selected to use the VCC pin as the voltage reference. Given you are only interested in measuring ratios between resistors, this option would be the one to use (as opposed to the internal band-gap reference(s)).
This mode means that the code values recorded by the ADC will always be proportional to the supply voltage, whatever it is (i.e. for 5V supply then 5V => 1023, for 3.3V supply then 3.3V => 1023).
If your button potential divider is also sourced from the same VCC, then you should get the same code ranges for each push button regardless of the supply voltage.
The only slight problem with the lower voltage is that noise will have a larger influence on the code values - if you had say 50mV noise for a 5V supply, that corresponds to 10 codes. For a 3.3V supply, that same 50mV noise corresponds to 16 codes. This probably wont be an issue for 8 buttons. |
H: How can I estimate the inductance of an inductor operating at different frequencies than the test frequency?
I am looking for a 10uH inductor to operate under 200kHz. I found this inductor, but its test frequency is 100kHz instead.
How can I determine if it's ok to use this inductor? Is there a way to estimate the inductance when it's operating at different frequencies?
I can't find a recommended range of frequencies to use this inductor anywhere in the datasheet.
AI: Generally speaking, inductor properties change gradually with frequency. You are very unlikely to find a problem over such a small difference in frequency.
Or put another way, any inductor that changes aggressively, so close to its rated frequency, isn't a good inductor to begin with. (Now, whether they're selling it as an inductor regardless of that -- well, that's another issue.)
Depending on what you're doing with them, though, you may still have problems.
First, regarding frequency range.
The SRP1038A family isn't terribly well specified. The best data they provide are linked from the product page,
AEC-Q200 Compliant Electronic Components | Bourns Power Inductors
which offers a spreadsheet containing these parameters:
This low-order[1] model has few degrees of freedom, so probably won't be very accurate. At best it can exhibit a single self-resonant mode, and will have Q most accurate at whatever point it's calculated around. But it will not be accurate over a wide range of frequencies -- certainly not from DC to SRF.
To be clear, this is not a physical model of the inductor -- it's just a bunch of calculated parameters. We can still associate them with physical aspects: Rser is the winding DC resistance; L is the overall inductance; Rp is core loss (imagine the core as an array of very small shorted turns coupled to the inductor[2]); and Cp is the winding capacitance (anywhere we have two conductors, there is capacitance between them -- even if they're two ends of the same piece of metal, as in a winding).
The provided model however doesn't seem to fit the measured parameters. I get a Q factor of 204, not 20, at 100 kHz. So, for our purposes, we can discard these data as meaningless. That's unfortunate, but shows the reality of the market: manufacturers are under no obligation to give anything more than what they're selling. (My guess is, at best, they fit parameters to the SRF peak; but the resistance (Rp) even then seems very unrealistic. That or they made a typo in the datasheet and meant 200 Q instead of 20, but needless to say, I wouldn't stake a design on that.)
Since we can't rely on better measurements or modeling provided by the manufacturer, we are left to our assumptions, and what little is in the datasheet.
We can generally assume a reasonably-straight impedance around the test frequency (i.e., \$|Z| \cong 2 \pi f L\$), leveling out to DCR at low frequencies, and peaking and then falling back down at the SRF. (10 µH at 10 MHz implies a peak in the ballpark of 630 Ω, but it can be higher or lower depending on actual core losses.) That is, from about 1 kHz to a bit under 10 MHz, we should expect reasonably-inductive behavior.
Over the inductive range, Q factor also cannot change very quickly. For instance, for air-core inductors, it varies typically as \$\sim \sqrt{f}\$. At 200 kHz, we expect no more than \$20 \sqrt{\frac{200k}{100k}}\$ or 28, and based on my experience with similar materials, I would guess it's instead lower than 20, not higher. Maybe 15-18.
(It's worth noting that the datasheet only specifies minimum Q, so it could be any number higher than that. But if they could specify more, they would; I would guess the actual value is not much higher than given here, perhaps 21-23 typical.)
[1] Just as we can fit a polynomial curve to a data series, we can fit a schematic to an impedance curve. A lumped-element (RLC) circuit is in fact a graphical representation of a rational polynomial; to which we can always add more elements to raise the order and improve accuracy. Containing one L and one C, this is a 2nd-order fit, and so is only correct at, at most, four points.
[2] The datasheet notes they use "carbonyl iron", a form of iron powder that is commonly used for inductors. The analogy of "small shorted turns" is quite apt here: eddy currents flow around the microscopic iron particles (or between, where they touch). This material has the downside that, when packed densely (to give high permeability, that is, high inductance for a given shape, size and number of turns), it also has high losses (lots of particles are touching). And this is borne out by the datasheet, with no parts in the family offering a Q above 20.
Second, regarding use.
As a use was not suggested, I'll go through a typical example of a buck converter application. This is a common enough application to be representative, and demanding enough to illustrate the limitations of a part like this. Less demanding applications, like EMI filtering, will be much less sensitive to core losses; though the loss, and capacitance, will affect the damping and RFI response of the filter.
For a buck converter, we apply a square wave voltage to one side of the inductor (we can ignore voltage ripple on the other side), and get a triangular current waveform through it. The product of these (square times triangle) gives the reactive power flowing through the inductor. Thus, the reactive power is related to the current ripple. Which is in turn related to the output (DC) current by the ripple fraction, RF = Ipk / Idc.
Q factor is defined as the ratio of reactive to real power, so for a given reactive power, we divide it by Q to get real inductor loss. Mind this is in addition to DC loss (given by DC resistance, 27 mΩ for this part).
The maximum power rating of this part is apparently 1.5 W (it's rated 7.5 A at 40°C temp rise). If we were delivering just DC, this would be a sufficient rating, but if we must also account for AC losses, we must derate Idc accordingly.
If we assume half core losses, then 0.75 W, or 15 VA reactive, should be the typical capacity of this inductor. (This requires derating current to 5.3 A or less.)
Now we come to a problem: the reactive power of a nonsinusoidal wave isn't well-defined, and Q isn't constant with frequency anyway. We can take waves specific to this application (square wave voltage, triangle wave current), and come up with a solution. Keep in mind this is not a general result, but only applies for this case. We can also just wave our hands and assume Q is constant -- it won't be, but the harmonics of these waveforms drop off quickly as well, so we're probably only incurring a few percent of error by doing this, even if Q drops to 1 or less at some point.
That said, for a 50% square wave of \$\pm \frac{V_{in}}{2}\$ applied to an inductor, we expect a ripple current of \$I_{pk} = \frac{V_{in}}{8 L f_{sw}}\$. The product of which dissipates an average power of:[3]
$$ P_L = \frac{2 {V_{in}}^2}{\pi^2 Q L f_{sw}} $$
Inputting the 0.75 W from before, and the component parameters and \$f_{sw}\$, we get \$V_{in}\$ about 12 V, implying about 6 V output, and given the 5 A RMS rating, around 30 W. Which corresponds to a 15% ripple fraction (implying VAR = \$\frac{5}{3} V_{in} I_{pk}\$), which suggests an average current mode controller will be required (peak mode controllers are mode common, but unsuitable for such low ripple fractions due to the nature of the control scheme; constant-on-time or other types may also be suitable).
[3] I've omitted a small correction factor that arises from the waveforms:
$$\sum_{n=0}^{\infty} \frac{1}{(2n+1)^3} = \frac{7 \zeta(3)}{8} \approx 1.0518\ldots $$
The (2n+1) is simply the odd harmonics of the waves, which go as 1/n (n odd) for square and 1/n2 for triangle, hence the cube product. This factor depends on duty cycle; this is only for the special case at 50% duty. |
H: Understanding PID controller output value
Consider a PID controller that needs to regulate the temperature of a small object. This will be implemented in software in a microcontroller.
A thermistor is closely bonded to a heater (a small 3 watt power resistor driven by an 8-bit PWM through a suitable MOSFET.) The system is able to correctly read the temperature and is able to modulate the heating output of the resistor. All the features work in isolation but now I need to bring it all together using a PID controller.
The ultimate output needs to be an integer in the range 0 - 255 for use with the PWM generator, where 0 is the heater turned off and 255 is the heater at maximum output.
It is not clear to me how to scale the values so they fit into 0 - 255. Is that something that the PID math is able to do if you choose the right P, I and D coefficient values, or should I have the PID system output values such as -1 to +1 and then just scale that linearly so it maps to 0 - 255?
Basically the point where the clever math ends and the tangible hardware begins. How do people usually set this up?
I'm after a "best practice" type of answer, or perhaps a rule-of-thumb.
Further information:
The ADC that reads the thermistor is of 10-bit resolution, but I'm taking an average of 25 samples to mitigate noise effects (this sampling is interrupt driven and at a fixed frequency). The averaged temperature is updated at about 4.3 Hz. The heater PWM frequency is about 136 Hz.
It works!
With the accepted answer below I was able to implement a full PID control system. I'm using a few simple checks to ensure that the integral term doesn't become unmanageable: setting the integral to zero when the error is very small and also an upper limit on its absolute value. I'm simply clamping the final PWM value between 0 and 255.
The preliminary PID constants that produced the image below are P=50, I=3 and D=5. My set point is 60 Celsius and the system seems to stabilise at about 59.4 Celsius. It's still a bit sensitive and there is a lot of latency between the heater and the thermistor, but on the whole I'm pretty happy with the outcome. I'll continue to tweak the variables and see how good it can get.
AI: A PID controller is linear. As a result, it doesn't make any difference whether you scale the PID coefficients or the output of the PID controller (or even the input for that matter).
For example, if you want the proportional (P) part of the PID controller to have a gain of 100%/10°C (that is, a 100% increase in output for a 10°C decrease in temperature), the proportional gain has to be 25.5/°C so that a change of 10°C causes the output to go from 0 to 255.
The same applies to the integral and differential parts. Note, though, that the sampling rate of your system also influences the gain for these, as they are time-dependent. If you sample more often while keeping the coefficients the same, the integral gain goes up, while the differential gain goes down.
Additionally, for the PID controller to work properly, the sensor must have a surprisingly large resolution. If the resolution is too low, the discrete differentiation becomes noisy and unstable. For example, if you have an 8-bit input value range (0-255) for temperature, and your differential gain is 50, this would mean that a single-digit change in the input temperature will cause the output to swing by 50 units (which is about 20% of your 0-255 range). As a result, the output will constantly jump up and down by 20%, or more if the input is slightly noisy, making the PID controller potentially unusable. It'll be even worse if the resolution of your sensor is even lower (i.e. only whole degrees Celsius).
Ideally, for the differential part of the PID controller to work properly, the input value range should bigger than the output value range by a factor of the differential gain. So, if you have a differential gain of 50 and an output value range of 0-255 (8 bit), the input value range should be 0-12749, or about 14 bits. In practice, you can go a little lower, but not by much before you introduce excessive noise and instability into the system. 12 bits is probably fine in this case, which is a typical resolution of microcontroller ADCs. In practice, you'll have to tune the PID parameters by hand, so the best you can do is to make an educated guess or just use the highest resolution available to you.
Your 10-bit ADC with 25x oversampling gives you a bit more than 2 extra effective bits of resolution, bringing you to that 12 bit figure I mentioned earlier. As a result, you can use differential gains of up to 64 without suffering any ill effects from quantization noise in your discrete differentiator.
The proportional and integral gains are not affected by this effect.
If you want to calculate the integral and differential gains instead of just adjusting them by guessing, you will need to know the time constants of your system (which you can measure by turning the heater on and plotting the resulting values from the temperature sensor). Using this curve, you can estimate the system's frequency response (via a Fourier transform), and then you can calculate a viable frequency response for your PID controller or just tune it in a simulation (with LTSpice, for example). |
H: How often can an ATtiny85 be flashed?
I wonder how often I can flash an ATtiny85 before the EEPROM will give up.
Solved
Sometimes it is just on the first page of the datasheet:
AI: It reads on the first page of the data sheet.
EEPROM is specified for 100000 write/erase cycles.
It does not depend on how often you do it, no matter how fast or slow it still is 100000 write/erase cycles. |
H: 74HC221 negative edge trigging
How to use 74HC221 for output variable pulse width on negative edge.
I tried connect B and MR pins to HIGH and A pin to input as tells in datasheet. But it give huge pulse like 1 second.
Probably I must use RX and CX pins but don't know how to use and datasheet doesn't tell.
The pulse that i want, must be between 0-10 ms.
I add R4, R5 and C3 change the values of R4 and C3 multiple times but it didn't change the output.
Then realized this:
"Pin 'CX' is not modelled.
Pin 'RX/CX' is not modelled."
in simulation log. Could this be the problem?
AI: I find an alternative solution because RX and RX/CX pins aren't functional i think.
So in edit properties window for component there is "Monostable Time Constant" value. Default value is 1 second so the output was always 1 second. But you can change it whatever you want.
And there is hidden pins for VCC and GND so You must add VCC and GND terminal in your circuit.
Also B and MR pins must be HIGH and A input for falling edge trigger.
This is result. You can see i add VCC terminal and set monostable time constant value to 5ms so BLUE line in graph shows that. |
H: Is this way of maximum current calculation correct for this voltage regulator?
Regarding using the LD39050PU33R voltage regulator which is 5V to 3.3V fixed voltage regulator without any heatsink, its maximum current is given as 500mA. I was trying to figure out how they calculated this 500mA. So I tried to calculate the maximum current by myself by using the thermal resistances and maximum junction temperature as follows:
From the thermal data below:
The junction to case thermal resistance R_jc is sum of those above; so R_jc = 65 °C/W.
For 5V input the voltage drop across the regulator will be Vd = 5V-3.3V = 1.7V.
Max junction temperature is 125°C. And in the worse case if we have 55°C ambient temperature the ΔT = 70°C.
That means maximum power dissipated Pd can be found from:
ΔT = Pd * R_jc
Pd = 70 / 65 = 1.077W
This makes the max current I = Pd / Vd then I = 1.077 / 1.7 = 633mA.
In my calculation I took max ambient temperature 55°C. To obtain 500mA, the ambient temperature would be taken as around 70°C. Is my conclusion correct?
AI: The reason for the 500mA rated current is actually much simpler than that: The chip has an integrated current limit that may be as low as 600mA depending on tolerances (typically 800mA). Even if the chip is sufficiently cooled, it won't output any more than that. The manufacturer therefore rates it for 500mA, with some safety margin to the 600mA current limit.
Your calculation also breaks down for the other variants of the regulator (i.e. the fixed 1.0V version, or the adjustable version), which all have the same 500mA rated current - assuming sufficient cooling.
You are right in your conclusion that you can use the 3.3V variant of the regulator with 5V input voltage without any additional cooling at 55°C ambient temperature. |
H: Understanding the flux linkage in transformers
I am having difficulty understanding the concept of flux linkage in transformers, particularly how the secondary winding receives its flux when all the flux is said to be confined to the iron core. I understand that the primary winding produces an alternating flux when excited by an AC source, but I am unsure how this flux links to the secondary winding when it is wound over the core.
I have read that some flux lines will pass through the secondary winding, but I do not understand how this is possible when all the flux is said to be confined to the core. I would appreciate a physical and intuitive explanation of this concept or any relevant simulations or visualizations to help me understand.
Additionally, if there are any books or resources that are recommended for better understanding this concept, I would appreciate any suggestions.
AI: It is good if the flux is confined to inside the core. Magnetic flux changes result in a circular electric field. Any closed loop wire encircling the flux, no matter what diameter and how located, will exhibit a voltage difference no matter where you cut the loop open. Multiple loops, multiple voltage.
The flux only needs to pass through a wire loop, it doesn't need to touch it: the flux is a magnetic field, but what the wire picks up is not the magnetic field but the circular electric field surrounding the flux change.
There is an converse device, a current clamp which encloses a conductor with a magnetic circuit and uses the strength of the circular magnetic field to deduce the electric current passing through. Again, it doesn't matter just how the magnetic loop encloses the electric conductor or whether it touches it or not. |
H: Can I charge 604050 LiPo battery using USB charger and single resistor?
The battery I got off Aliexpress has a protection chip:
I'm wondering - Will the chip protect the battery against overcharging if I use a standard 5V USB charger and a single resistor in series?
EDIT: I'm fixing a toy worth fiver. There is no room for the proper charger inside the toy.
AI: The protection chip is designed to prevent the battery from lighting on fire. It won't prevent the battery from getting damaged.
Don't do this. Use a proper charger.
The protection circuit disconnects the battery when the voltage on the battery terminals gets excessively high. The trip voltage is quite a bit higher than the regular (safe) maximum voltage of the battery. The popular DW01 protection IC specifies it as up to 4.35V, while the maximum charge voltage for a LiPo is typically 4.2V. At that point, the battery will be damaged, but it (hopefully) won't explode or catch on fire yet.
You can get really tiny LiPo charging boards that aren't much bigger than a USB connector. Not using a proper charger is simply not an option - charging the battery with nothing but a resistor and 5V will kill the battery in almost no time. It might not even last 10 cycles if you overcharge it this way. See: https://apps.dtic.mil/sti/pdfs/ADA572554.pdf |
H: How does a bootstrap circuit work and how can I calculate the resistor and capacitor values?
I am designing an H-bridge with an N-channel MOSFET to control a 12V - 1.35A DC motor. The H-bridge will be controlled with the digital outputs of an Arduino. I did some research and found that I need to use a bootstrap circuit, which from what I understood is to improve the linearity of the MOS switch (on resistance of transistor) by making sure that the signals from the source and the gate of the NFET follow each other. For this, a capacitor is added between the gate and the source of the transistor, so that the gate and source signals follow each other.
I found a bootstrap circuit and included it in the H-bridge design, but didn't end up understanding how the boostrap works.
Where is the capacitor supposed to find its way to ground?
How do I calculate the value of the boostrap resistor and capacitor?
Is the circuit correct? It works in the simulator, but I don't know if it works in real life.
AI: The bootstrap circuit is needed when you use an N-channel MOSFET as a high-side switch. That's because the MOSFET is operating as a source follower (common drain), which means that source potential is always a few volts lower than gate potential. Obviously you need the source to rise all the way to the positive supply, so in order to get minimum on-resistance, you need to raise the gate several volts higher than the positive supply.
The principle is to charge a capacitor to the full supply potential (say 12V), and whenever you want the transistor "on", "insert" the capacitor into the path between the normal digital 12V gate drive signal, and the gate, so that the gate actually sees the sum of the digital signal and the capacitor's voltage, 12V + 12V = 24V.
You only want this to happen when the transistor is supposed to be on, because to switch that transistor off again requires that the gate be at 0V. In that case, you obviously don't want the capacitor's voltage to be added, so you have to somehow remove the capacitor from that path when the transistor is supposed to be off.
I can't see how the circuit that you provided in your question can do that. The switches pull up to +5V, which cannot possibly cause the bootstrap circuit to operate correctly. For it to work, those switches must pull down to ground, which requires other changes.
For instance, R18 in your circuit is supposed to pull down the gate to ground, but it can't possibly overcome the upwards pull from R16, and its presence has little effect. I will leave that resistor present in my own circuit below, for illustration purposes, but for now understand that when your upper switch is open, there's nothing except the ineffective R18 to lower gate potential. That's why your switches need to do that, pull down.
This is how one side of the bridge should look:
simulate this circuit – Schematic created using CircuitLab
Switches SW1 and SW2 operate in anti-phase, while one is on the other is off, and vice versa. They both pull gate potential low to 0V. Therefore R4 should be a pull-up, to 12V.
Start by understanding the state of the circuit when SW1 is on, and SW2 is off. M1's gate is at 0V now, which is necessary to switch that transistor fully off, regardless of the state of charge of C1. Conversely, with SW2 open, M1 is fully on, since its gate is pulled high by R4.
To answer to your first question, regarding the capacitors "ground", in this state, there is a low impedance path from +12V, through D1, C1 and M2 right down to ground. That causes C1 to charge up to 12V (actually slightly less since D1 has a small voltage across it).
When the switches change state, M2 turns off because its gate is now at 0V. Gate potential of M1 is pulled up via R1 and D1 to almost +12V (the diode drops a bit), which raises M1's source (remember it's working as a source follower) to few volts below that, say +8V. However, during the rise of potential at OUT to +8V, the bottom of C1 goes up with it. The top of C1 is almost 12V above that. During this rise, D1 becomes reversed biased and leaves the picture, leaving only R1 to apply this rising potential (well over 12V now) to M1's gate. It's a kind of positive feedback.
With its gate at well over +12V, M1 actually switches completely and utterly on, and OUT rises all the way to 12V, dragging its own gate way way up to nearly twice the power supply potential!
Here's a graph of the potentials at the gates over a few cycles:
Now to answer your second question, about calculation of the value of C1, you must understand how it discharges. You already get that it charges, gets "topped up" every time OUT goes low, but in the state where OUT is high, the current route for discharge is different. D1 is reverse biased, so that's not a route. The switch is open, so that's not a route.
The only route for the capacitor to discharge is via R1, R2 and R3 to ground. Their combined resistance, \$R_1+R_2+R_3 \approx 11k\Omega\$, combined with C1 produce a time constant of \$\tau=11k\Omega \times 330nF = 3.6ms\$.
You can see discharging happening above, the blue trace in the region between the green markers, where the voltage at M1's gate is decaying. The more frequently you switch states (ie. the higher the PWM frequency), the less time C1 has to discharge, so for higher frequencies C1 can be smaller.
This discharging can only happen for a few reasons, such as:
Via R3, to ground
The capacitor's own self-discharge
leakage current through D1 or elsewhere
The biggest cause, by far, for capacitor discharge here, is R3. As I mentioned before, you don't even need R3, since the switch does all the pulling to ground. So I recommend you simulate that circuit without R3, to witness how the capacitor effectively never discharges:
In practice I would suggest a capacitance significantly greater than the MOSFET's own gate capacitance, say 100nF, but I welcome comments about this.
Any current path to DC (ground or +12V for example) via which the capacitor can discharge, will determine the rate at which it discharges.
Here's the main point: you must never allow the capacitor to discharge so much that gate gets anywhere near the point at which the source starts to drop in potential, when the source starts to "follow". In other words, gate potential must always be significantly greater than \$V_{SUPPLY}+V_{GS(TH)}\$, where \$V_{GS(TH)}\$ is the MOSFET's gate threshold voltage, typically 3V or more.
From the first graph above, where gate potential decay is evident, since my MOSFET has \$V_{GS(TH)}=4V\$ the lower green marker must never get anywhere near +16V. That happens when I reduce C1 to cause faster discharge:
The orange curve is the potential at OUT. Notice how when the gate drops below +16V, the transistor's source begins to follow its gate, but 4V lower. This "linear" region is what you are trying to avoid with a bootstrap system. As you can see, it's simply not enough to apply +12V at the gate of M1, to turn it on. You need at least 16V at the gate, and that extra boost is provided by C1.
To your third question, "is my circuit good", I say no, it isn't. Make your switches pull down, and remove R18.
May I suggest you replace the physical switches with a MOSFET, to get this circuit:
simulate this circuit
M3 not only pulls down, but also inverts, so you only need the one signal to drive both M1 and M2.
As a final word, this is still not a good design, since there's nothing to implement dead-time to prevent shoot-through. |
H: How to sense if a heater is plugged and on
I want to remotely check if one of my home sockets (which happens to power a heater) is transmitting current or not. I do this as a hobby project, so my main priority is to learn through the process of building it, therefore I don't want to buy 'ready-to-use' devices. Also, this is a heater and I have carpet so, for safety reasons, I would like to not need to peal and connect wires that carry several amps. In particular, my heater is 2000W at 230V, so it will be using ~8.7 amps if I'm not mistaken.
I have been looking at different alternatives. Ideally, I would like to have a socket adaptor that sits between the wall socket and the heater, and the only thing it does is producing 3.3V or so on an external pin when it detects for instance 1 amp going through it. I can then feed that signal to an MCU and do whatever I need. At this point, I'm interested in the step of sensing when there is current flowing through the socket, but I don't need to measure the exact amount of current.
The alternatives I have found (that are safe enough) are:
Hall effect sensors This is not ideal, but it's safe as I don't need to manipulate any part transferring a respectable amount of amps.
Socket adapter with LED: I could break the LED part and solder a wire to it to use it as an input signal for my MCU.
Am I looking at the right parts? What are other options I could use?
AI: After reading all the comments, the adapter with LED is discarded. That leaves 2 main options:
Current transformer
Hall-effect detector
Both devices work by passing a current carrying wire through the hole they expose, thus it's necessary to, somehow, expose only one of the wires that go to the target device (such device will have a single cable with, at least, 2 wires in it: phase an neutral).
Still, out of the 2 options, the hall-effect detector seems safer as the output it generates is a low voltage, which will vary depending on the amount of current going through the sensed wire. The current transformer induces a current on the output, which has a problem: it's necessary to solder a burden resistance in between the outputs to avoid a (theoretical) infinite voltage between them. There are online burden-resistor calculators but again, this is an added difficulty and, if by any chance the burden resistor is damaged or the solder points fail, it can be unsafe as far as I can see. |
H: Basic capacitor in circuit
I’m new with electronics. I really don’t know how to search up this circuit. This circuit will make the LED turn on when it has microphone input. Could someone explain or suggest what should I search to know how this works?
AI: I have no idea why someone added C2 there. It will probably stop the circuit working, and the + symbol is on the wrong side.
C1 is to block DC and let AC through. It's one of the common uses of a capacitor.
Q1 is an NPN transistor. It amplifies current. Pass a small current from the base to the emiter, and it allows through a larger current from the collector to the emitter. |
H: How to limit current going into DC/DC
In my project, I am using 12 solar cells in series as a power source. This is the link to the cell. Doing that will give me a power source of (3.6W * 12 = 43.2W) maximum and output voltage is (0.6 * 12 = 7.2V).
I want to use this source to power some sensors, such as this current sensor. I will power the sensors with 3.3V, therefore, I use this 3.3V DC/DC to get 3.3V. If I'm not wrong, the input current to the DC/DC should be milliamperes while my source can generate (43.2W / 7.2V = 6A) maximum.
I want to limit this current by using a resistor by connecting it to the input power pin of the DC/DC. Here are some questions I have at this point:
Does the solution of using a current-limiting resistor sound like a potential solution to my problem?
If so, how should I determine the value of the resistor? Should we look at the full load or no load current?
Is there any other solution besides using a current-limiting resistor?
AI: I got the answer I wanted: There is no need for limiting current because the DC/DC will draw as much current as it needs. |
H: How to determine power needed for an IC
I want to use solar cells as power source. Let's say I am using 12 cells, and that gives me 43W of power. I will use this power source to power multiple ICs, such as this current sensor. How can I determine how much power the sensor consumes? I want to know this because if I want use multiple of them or any other ICs, I may want to make sure that my power source has enough power.
I am very new to schematic design. I wonder if power is a must thing that we need to think about while doing schematic design.
AI: You can read the data sheet how much the sensor chip itself requires for operation. It's commonly called supply current or quiescent current.
And strictly speaking, you really don't consider the power consumption of chips at the schematic design stage any more. Those considerations should be done at a step that happens before starting the schematic design, where you decide what chips you have to use and how to power them, and then start with the schematics when you have determined what parts to use and how to power them, and what kind of connections they need to work and perform their function. |
H: Equivalent impedance of a circuit
I'm trying to figure out the equivalent impedance of the right side of this circuit (so the capacity, inductance and right resistance) :
I see this result in the solution of my exercice:
But I don't see how L et R are in parallel, are they not in series?
AI: The point of view for the impedance is not clear.
The solution that shown is for the part of the circuit as shown in my diagram.
$$Z_{\text(ab)}=Z_C//(Z_L+Z_R)$$
You should be able to find the solution from here.
And yes, the inductor and the resistor are in series. And the solution is correct.
simulate this circuit – Schematic created using CircuitLab |
H: How can I connect multiple potentiometers (~20) to my Arduino without having to have 20 analogue pins?
I'm trying to build a MIDI controller and I'm looking for a clever way of using 20 potentiometers without having to have 20 analogue ports on the Arduino. So far all the functionality I need is for every potentiometer to print its current value on the serial monitor when I turn the knob. Is it possible at all?
AI: By using an analogue multiplexer, like the 74HC4067, you can select which signal gets "routed" to the Arduino:
simulate this circuit – Schematic created using CircuitLab
It works by using four of the Arduino's digital outputs as an "address", to select which path from Ix to COMMON is selected. They you can read the value of the analogue input A0.
This will handle 16 inputs only, so you'll need another multiplexer one for the remaining 4. Actually, this will give you capacity for 32 potentiometers in total. Since the Arduino has another analogue input, you don't need to do any address manipulation, and can share D0 to D3 with both multiplexers. Something like this will do:
simulate this circuit
If you can't get multiplexers quickly enough, or you have a bunch of small MOSFETs lying around, and you wish to punish yourself for something, then you could try the approach below.
By switching on M1 and M2, you connect a group of up to 8 potentiometers to the power rails, thereby "enabling" them. You switch them on by bringing D0 low. Then you can read their analogue values from A0 to A7.
Then you enable the second group of 8 potentiometers by taking D0 high (disabling the first group), and bringing D1 low, read the values, and so on.
simulate this circuit
You must ensure you never have two groups enabled at the same time, (by having D0, D1 etc simultaneously low), but if you do, resistors R1, R2 ... R7, R8 ... R10 prevent any accidental short circuiting of the power supply rails.
You can have as many groups as you have spare digital outputs to enable them. You'll need two N-channel MOSFETs and 1 P-channel, for each group of potentiometers.
Update
User misk94555 had a brilliant idea. Power the groups of potentiometers from the Arduino's digital outputs! That's genious, but it does require that you take care to not overload the IO ports. I recommend trying to keep each IO sourcing/sinking less than 2mA, to keep their voltages as close to the power rails as possible. That means ideally the potentiometers should have a resistance of 20kΩ or more.
The circuit would be as follows:
simulate this circuit
This time, set all digital outputs D0, D1, D2 and D3 to high impedance, normally. If you want to read the first group of potentiometer positions, you set their power rails, controlled by D0 and D1, to high and low respectively, read the values and then return D0 and D1 to high impedance.
To read the second group, set D2 and D3 to high and low respectively, read the analogue values, and return D2 and D3 to high impedance.
You have as many groups as you have pairs of spare digital outputs.
I've never done this, so I can't vouch for its effectiveness, but it sure beats everything else for simplicity. All the complexity is in software.
The only concern I have is that the digital outputs will not be exactly 0V or 5V, so you may lose some precision in your readings. I think it's worth a try though.
Update 2
I have overlooked the fact that there is still interference from unpowered groups in the last two circuits. It was pointed out that their effect can be compensated for with maths in software (some application of superposition, perhaps), but I doubt it's worth the effort.
Maybe there's something that can be done with diodes, to redeem the idea. Perhaps hold all groups' positive rails high, and only one group's negative low, and use diodes to isolate inactive groups. It reminds me of keyboard scanning, but with pots. |
H: What is a chip generator?
I've been trying to learn more about the RISC-V environment. I've encountered a chip generator called Rocket Chip.
What is a chip generator, and how does it differ from a core? I'm trying to understand how and why it is used.
AI: A chip generator is a tool that automates the process of designing custom computer chip. it enables you to create a new chip from scratch by specifying its features and functionality.
Rocket Chip is an open-source chip generator that is designed specifically for creating chips based on the RISC-V.
With a core, the design is fixed, and you cannot modify its functionality. However, with a chip generator, you can create a chip design that is tailored to your specific needs |
H: Finding equivalent resistance if each resistance is 100 ohms
The method to follow here is wye delta transformation, the resistors across red and purple nodes are in series so 2R and using delta to wye in green-pink-blue, and pink-black-blue
after that there are many options to convert delta to Y or Y to delta like the pink Y or green Y, all leading to more complex circuit, what approach must be taken to get answer as fast a possible (answer 125 Ω), can it be solved using some other method?
AI: what approach must be taken to get answer as fast a possible (answer
125 Ω), can it be solved using some other method?
Here's a clue (we only give hints on homework sounding questions): -
In other words there can be no current flow in those resistors due to symmetry. But you can also short those resistors out to get the same answer: -
The answer is indeed 125 Ω. It took me 8 minutes of which 3 minutes was recognizing the symmetry and the implications. |
H: Logic signals have too high a voltage - Solved
I am trying to control a 5 inch display from a Raspberry Pi Pico controller. I am using a display from BuyDisplay.com which uses the RA8875 driver chip and has an 8080 parallel interface (Note: BuyDisplay have changed their product line since I brought the display so one with the same pinout is not yet available - in any case there was no schematic supplied).
I am trying to write the driver (in Rust). I have done this in the past with other displays and found the rats nest of cables I had to connect was a source of unreliability in development. As such I decided to take the risk and design and get manufactured a PCB that:
Has the Pico mounted,
Has the power supply regulators,
Has sockets for other peripherals
Can be plugged directly into the back of the board.
Schematics (work in progress) and PCB (ground and power planes shown hatched) are:
(also available as Kicad project at https://github.com/adoble/modular-audio/tree/main/hardware/controller)
After being unsuccessful in getting my code to drive the display, I had a more detailed look at the signals that were coming off the PCB (with hindsight, something I should have done before!). A typical signal for one of the data lines looked like:
There was a “ringing” on the edges and the voltage peaked to 4.08 V. I fear that I have fried the RA8875 drive chip!
Before buying another display, I tried adding on a “termination” circuit for each signal between where it “exits” the PCB and “enters” the display board. The circuit looks like:
I was assuming that the PCB tracks were the culprit and also that they have an impedance of about 50 Ohm - hence the 47 Ohm resistor. The data signals now looked like this.
I’m thinking this looks reasonable with a Vmax of 3.6 V (but more about that later).
However, other signals look terrible, for instance the chip select (CS) looks like this:
So:
What can I do to get decent logic signals without high voltage peaks?
I also mentioned that the logic signals have a Vmax of 3.6 V. I would have expected 3.3V from the Pico. I don't understand where this is coming from and how I can change it?
Thanks for any help.
Update
I used the suggestion of @Justme and removed the termination and then measured the signal with a ground coil. Results for both the CS (yellow) and DATA0 (blue) signal are:
These both look very good - it seems that my measuring technique was leaving me to the wrong conclusions.
Display still does not work, but I'm pretty confident now that this is a software problem.
AI: A simple series resistor for source termination would likely work fine. On the other hand, what you see on the scope is what the probe sees, and you migh be probing the signal in a way that the scope sees ringing. Likely the RC termination on display side is not needed.
If scope sees a peak of overshoot, then that is the maximum voltage it measures. The DC level should be 3.3V. |
H: Where and how are the carrier and message signal multiplied in this circuit?
I have this circuit diagram of an AM modulator and I am trying to understand what is going on.
I know that the c(t) is taken from the collector of transistor Q1 and the multiplication of signals : m(t)c(t) is taken from the collector of transistor Q2.
I want to know at what point and how the two signals m(t) and c(t) are multiplied.
AI: I find this 2-quadrant (Broadcast AM) multiplier explanation to be quite useful: -
What it's basically saying is that if you change \$I_{EE}\$ you can change the slope of the graph: -
I've drawn the red line on the graph above to indicate a lower value of \$I_{EE}\$. The linked document also goes on to show how \$I_{EE}\$ is "varied" using another transistor: -
I want to know at what point and how, are the two signals m(t) and
c(t) multiplied.
It's all done around Q1, Q2 and Q3 in your circuit. The differential amplifier that follows Q1 and Q2 converts the differential output of Q1 and Q2 to a single ended output.
Images above taken from Analog Multipliers by School of Electronic and communications engineering.
Another useful link from Analog Devices MT-079 Analog Multipliers. |
H: What happens when a CC/CV charger fails to give the required output voltage during CV charging and instead provides a lower constant voltage?
Lets say that I have a CC/CV charger based on buck topology and it is charging a 12V lead-acid battery through a solar panel. The lead acid-battery is being charged in CV (Constant Voltage) mode and requires 14.6V to be maintained across it until the charging current drops below a preset current threshold. However, the solar panel is no longer able to provide the voltage required for the buck converter to maintain 14.6V at its output and instead is providing a maximum constant voltage of 14.2V to the battery. What would happen in this scenario? And what would happen if the voltage goes much lower?
My understanding of this scenario is that if 14.2V is given to the battery during CV charging instead of 14.6V, it would just take longer to "top it off" and for the charging current in that situation to drop to the current threshold where it is considered completely charged.
My reasoning is that (imagining a simple battery model with a resistor in series with an ideal voltage source) if the charging voltage across the battery is less than the required charging voltage then there is a smaller potential difference across the resistor and therefore a smaller current will flow into the battery. And assuming that the total amount of charge that needs to be pumped into the battery during CV mode is constant and irrespective of the charging voltage used, then with a smaller current it will take longer to deliver that same quantity of charge at 14.2V then at 14.6V.
And if the voltage goes lower than the "ideal voltage source" in the simple battery model, then the battery will start discharging into the buck converter and solar panel. Though, I have no clue what that voltage threshold would be for the battery to discharge into the buck converter but I'm guessing it would probably be lower than its floating voltage.
AI: The charger can only charge the battery to the voltage that is input to the charger.
If the battery is required to reach some constant voltage to be full, then the charger that can only output a lower voltage can never fully charge the battery.
So it does not matter how long you charge, the output voltage to battery can't climb any higher than the input voltage.
There must also be some discharge protection, as if the voltage is lower at the charger input, it may start discharging that battery, but obviously a good charger would not discharge the battery. |
H: Which model of MBT desoldering station is this?
From Commodore 128 Complete Restoration and Board Repair @ 11:55, Raymond, the chap doing the desoldering, appears to be using one of these:
There is, however, no model number on the front.
From an ancient eBay item description, I found one (and the image above) described as a Pace MBT 250, but the MBT250 has a digital front end, so that can't be right.
Does anyone know, or is familiar with, this desoldering station and know the model number?
Note: For full disclosure, I have previously looked into this in 2019 and suspected that it might be a PPS80A (aka MBT201) - which I made a note about about on my blog.
AI: It appears to be a Pace MBT PPS80A. Here is a link to the Pace Service Manual. |
H: What value will be assigned to x, is it a or ~x?
I have some Verilog code for which I am unsure of the outcome of the non-blocking assignment of x as shown below :
always @(posedge clk, negedge rst)
if (~rst)
x <= 1'b0;
else
begin
x <= a; // Some value by default.
if (~y)
begin
ack <= 1'b1;
if (z)
x <= ~x;
end
end
Assuming a reset is done at some point before the always block execution, then once the reset is cleared the always block should execute the rest of the code. The initial value of x would be 0.
So I assume this is set to schedule x <= a,
then if y==0, ack is set to 1,
and then if z==1 the x value is toggled.
Now if I've correctly understood how the scheduling is done for the non-blocking assignments, the right-hand side of the statements are all calculated first simultaneously, and then are all assigned simultaneously to the left-hand side of the corresponding statements, just before the start of the next positive edge of the clock-cycle (or possibly at the posedge of the next clock cycle).
This leaves me wondering what happens to x since it's scheduled to be assigned with a, and also assigned to be toggled if the condition is satisfied.
My question is what is the value that will be assigned to x in this case, is it a or ~x ?
AI: When there are two non-blocking assignments to the same variable scheduled in the same event region, and the order of those assignments is determinate, the last write wins. See section 4.6 Determinism in the IEEE 1800-2017 SystemVerilog LRM
In your example, the last conditional assignment to x uses the current value of x, not the unconditional default value that has been scheduled, but has not occurred yet. So it will toggle of all the conditions are met. |
H: Power Regulation
I have a Li-Ion 3S1P Battery Pack with built in BMS rated:
Typ. Capacity: 5000 mAh
Nominal Voltage: 10.8V – 11.1V
Charging Voltage: 12.6V
Discharging Voltage: 9V
I need to power an STA540 in stereo plus bridge drive configuration (page 11/25) and I would like to regulate the power supply. If I use an LDO I need to count for at least 1 volt for dropout calculated for my worst case scenario more or less 9v, that is the voltage at which the BMS should disconnect the load, giving me a regulated 8V.
Is my assumption so far correct?
If so I would like to know if there is perhaps a way to higher my regulated voltage to aim at a higher output power without of course having to change the battery pack.
AI: Your supply voltage is already quite low for the STA540. The chip can directly consume your battery voltage without any regulation, so don't add a regulator. You don't need it and it will just limit the maximum output power for no good reason.
Additionally, please add a proper under-voltage lock-out to the amplifier that turns it off at your target discharge voltage of 9V. The BMS over-discharge protection is only a last line of defense, and when it triggers, the battery may have already been damaged. |
H: Jack audio 3.5mm PJ 215 (PJ 325) pins
I'm doing a simply audio frequency power amplifier circuit on breadboard. The input is the audio output of laptop or smartphone. I need to bring the input into the circuit:
I have this thing, it has 5 pins:
I'm going to use it to connect the audio to the breadboard. However, I don't know the roles of these 5 pins. After searching for it, I found out it is called Jack Audio 3.5mm PJ 215 (PJ 325) and found this datasheet image:
So its pin out diagram is:
I don't even know what does this image describe. When searching, I have read something like there is one pin connect to left channel and one to right channel of audio, but it's not clear.
Can you explain to me about this jack audio: Which pin do what thing, and how should I connect it to my circuit?
AI: The diagram is pretty much self-explanatory:
The connections to 2 and 4 are opened when a pin is inserted (this can be used to disable speakers, for example). Think of the plug being inserted and the contacts bending from a pivot point on the right and opening the switches. You can ignore 2 and 4 if you don't need them, and connectors are available (as you can see) without these pins.
There are 3 remaining pins. Tip, Ring and Sleeve, connected to 5, 3, and 1 respectively. The chevron shapes represent the shape of the contacts which touch the sides of the male 3.5mm plug when it is inserted.
If you look at a pinout guide, Tip is typically Left, Ring is Right and Sleeve is the common. |
H: E-Ink with Atmega and avr-libc
I am trying to understand how to drive an E-Ink display like the Adafruit 4196 with i.e. an Atmega328 with avr-libc.
From what I could learn so far, I would write the image/text to a frame buffer and push it to the display when done. Because the 8k frame buffer needed for the 200x200 pixel monochrome display is way too large for the 2k SRAM of the Atmega328, I would create the frame buffer in an external SRAM via SPI, and when done, push it from the SRAM to the display.
The Adafruit 4196 already includes an SRAM.
Adafruit has a library for Arduino which depends on Adafruit GFX allowing to render text and so on, so I guess all this would have to be implemented with "plain" avr-libc.
Did I get that right so far? Isn't all that quite a lot of work even for just displaying some plain text? Are there any libraries that could be useful here, like probably this one for SPI?
Update: What came out of this is here: Project to drive an E-Ink display with an AVR MCU and avr-libc
AI: You don't specifically need a frame buffer. That specific module just offers you one in the form of external SPI bus SRAM chip. You don't have to or need use it as a frame buffer or for anything if you don't want to, but since the Adafruit module includes it, the Adafruit code driver will use it.
If you want to just send strings of text to the display, you can do so without a frame buffer.
But the display does not work with text, it works with pixels that may contain anything.
So you still need to store a bitmap pixel font on your MCU, for example a 8x8 bitmap for 128 ASCII characters takes one kilobyte. But when you have the font, the 200x200 display can show 25x25 characters, and you only need 625 bytes of RAM to store 25x25 characters if you need to store them. |
H: Applications for Comparators Stable in Linear Region
These two comparators here MAX913 and MAX9013 are comparators that do not contain hysteresis. They are advertised to remain stable in the linear region and not exhibit instability for slow moving signals at the threshold.
I have two questions:
Wouldn't other comparators that do not have built-in hysteresis also behave in the same way? Is this behaviour actually special? Does the the output not transition smoothly for a comparator with no hysteresis? Now that I think about it, I guess this is one of the differences between an opamp and a comparator and the comparator has some kind of circuitry to quickly drive the output between logic states that tends to result in instability in this region?
What kind of applications would you use this comparator for? It seems to me that even though the output might transition smoothly, this output is always fed into a digital input which does have a region of indeterminant logic so what good is it?
AI: This behavior is quite special. As shown in the MAX913 datasheet on page 5 (bottom right, response to slow-moving triangle wave), a lot of comparators without hysteresis start to oscillate as they approach their linear region. The reason for that is that the gain of the comparator is so high (to ensure saturated digital output signals) that even the tiniest coupling from the output to one of the inputs (or an internal node) introduces enough feedback into the system that it starts to oscillate. Comparators usually don't employ any form of frequency compensation as they aren't meant to be used in a closed-loop system, and due to their high gain, even the tiniest bit of parasitic feedback is enough for oscillation to start. This kind of coupling can (and will) even happen internally to the chip; for example, the comparator's power draw will change as its output transitions from one state to the other, thereby introducing small voltage drops along the bond wires or even along the metallization layers of the silicon chip itself. If care isn't taken to ensure that these tiny disturbances can't influence the comparator's input stage, oscillation ensues. Most comparators therefore employ a very small hysteresis that biases the input stage away from the ultra-high-gain linear region in all cases, bringing the loop gain below unity even in the presence of parasitic coupling from the output to the input (which you can never avoid).
A slow-moving signal is any signal that doesn't get into and back out of the comparator's linear region within the propagation delay of the comparator. For example, if your comparator has an output voltage of 0V/5V (CMOS levels) and a gain of 50k, its linear region is 100µV wide. Assuming that it has a propagation delay of 100ns (at low input overdrive), the input signal has to slew at a rate of at least 100µV in 100ns, which is 1 volts per millisecond. The example scope trace shown in the MAX913 datasheet shows what happens to a "normal" comparator at 0.5 volts per millisecond: It oscillates like crazy. These aren't just "mechanical" timescales (milliseconds), but electrical timescales (microseconds / nanoseconds) in which the linear region has to be crossed, which is why most fast comparators these days have a bit of hysteresis, typically on the order of 1mV - a bit more than the size of the linear region.
As far as I can tell, the MAX913 simply doesn't strive for maximum voltage gain as other comparators do, but instead only has a modest gain of typically 3500. This is also a perfectly valid way to bring the loop gain below unity in the presence of parasitic output-to-input coupling, so it allows the comparator to be stable even without hysteresis.
You'd usually employ a comparator like the MAX913 in a circuit where you need to detect the level of a slow-moving signal with extremely high precision. Hysteresis introduces a fair amount of uncertainty to the exact level of the input signal as the hysteresis of many comparators is only loosely specified. Let's assume you want to detect whether a signal is above or below a certain set threshold with 1mV accuracy. If your comparator has 5mV hysteresis, you can simply forget about ever reaching that accuracy goal. However, you can't just use any old comparator that doesn't have hysteresis if your signal moves slowly, or else you're going to get oscillations, as previously described. You need a comparator that is specifically designed to not become unstable when it operates at or near its linear region, and the comparators you listed are ideal candidates for that.
The extremely low offset voltage drift of just 2µV/°C of the MAX913 is another dead giveaway that this comparator is designed to detect tiny variations in an input voltage that constantly hovers around the detection threshold with great precision.
When you employ the MAX913 in a circuit where you need an extremely accurate detection threshold (and consequently, where the MAX913 will spend a lot of time operating near its linear region), you would usually cascade two comparators: The MAX913 first to get an accurate, but potentially slowly-transitioning logic output signal, followed by a second comparator that has a bit of hysteresis to turn the MAX913's output into a logic signal with fast edges. That way, you get the accuracy and freedom of oscillations of the MAX913, as well as the fast edges from the secondary comparator.
In such a cascaded circuit, the hysteresis of the secondary comparator is effectively attenuated by the gain of the MAX913 (which is at least 1500), which means that you can reach single-digit microvolt precision even if your secondary comparator has a hysteresis of a few millivolts. |
H: Why can't I get rid of shoot-through in my half-bridge circuit?
I am building a class D amplifer and I have getting shoot-through despite my best efforts to mitigate them using dead-time, miller clamping, and using high V_GS_threshold MOSFETs.
Here is the circuit on LTspice:
The problem occurs when the high side switches on. You can see in the image below that the current through M1 and M2 spikes up. Building the circuit works but only if V2 is under 7 V and a PC audio volume less than 40%. If I increase either variable, the current spikes, activating my power supply's overcurrent protection and sometimes burning the UCC27282 MOSFET driver (I've burnt over 20 MOSFET drivers already, each costing me 4 CAD).
I initally thought I would need external dead-time, which I can add by adding two reverse parallel diodes on the inverting input of the comparator U3, thereby reducing Square-'s duty cycle:
Now going into the simulation, the shoot-through current is even worst, going from about 5 A previously, to about 27 A.
So, I undid the changes to the comparator U3 and decided I would test what would happen if I replaced the Square- signal on the MOSFET driver's LI with ground (I think doing this might affect the bootstrap circuit as the bootstrap capacitor is now charging through a higher impedance path via the load) and this is what I get.
WOW! 40 A of shoot-through current?! How is the low-side MOSFET turning on even though its gate voltage is zero? Or... is it? Upon further inspection there appears to be spike of 1 V of V_GS before completely going to zero. But the 1 V spike occurs when the shoot-through current drops and 1 V is less than the IRFZ44N's V_GS_threshold of 2 V. Is this actually not shoot-through current? Does the MOSFET enter the linear region? How am I in engineering?
If I replace the 10 kΩ resistors on the MOSFET's gate to source with 1 kΩ, there is a slight decrease in shoot-through current, it's almost negligible. I ended up reading about miller clamp circuits and thought that its low ON impedance would quickly discharge the MOSFET's gate-source capacitance as opposed to using a resistor. Still negligible effects.
I ended up trying a higher V_GS_threshold MOSFET (IRF530) instead, and the shoot-through current did decrease to about 1 A, but adding dead-time is still not completely getting rid of it.
Could someone please help me figure out this mysterious shoot-through problem (assuming it is even shoot-through) and finally put me out of my misery?
Here is the working circuit on a real scope. x10 attenuation is used to minimise probe capacitance. You can find the board layout link in one of the comments below (sorry, not enough reputation apparently).
In the image below, we have yellow as High (M1's V_G to GND), and blue as Low (M2's V_GS).
The yellow signal in the image below shows M1's V_DS, so my thinking here is that, M1 is ON when the V_DS is zero as that is the voltage drop across it.
Finally we have M2's V_DS as a yellow signal again. I can't have both V_DS show on the scope, since their reference points are not the same and I don't have differential probes. Yes, this is probably going to limit the information we have. Anyways, M2's V_DS looks weird since the wave is slanted a bit.
UPDATE 2023/03/25:
I made a new circuit board for the MOSFET driver and I discovered that using a different brand of capacitors for C7 (noise decoupling capacitor) fixed the slanted voltage curves from above. Below is an image M2's V_DS
You will notice that I'm using a higher supply voltage compared to the image above. That's because the current draw has decreased dramatically. Before, my circuit wouldn't even function above 7 V as the current would start rising exponentially over time. Now this circuit at 12 V is running only 27 mA without sound playing.
I've also tried out Simon Fitch's Miller clamping circuit on the actual circuit this time and here are the results. Blue is High (M1's V_G to GND), and yellow is Low (M2's V_GS).
Before
After
You can see that the signal to M2 turns off a little faster and reduced the ringing on the High signal after it switches on. These results were taken after I replaced C7. I would also like to mention that before C7 replaced the ringing was much higher that it was outputing a constant high pitched noise on my speaker.
Conclusion
So the issue in the live circuit was a bad brand of capacitors that were used for the MOSFET driver's noise bypass. I found out they were Tantalum capacitors and I believe all Tantalum capacitors are polarised and Ceramic capacitors are non-polarised. I blame the electronics shop for putting them in the non-polarised section.
My circuit now works as intented and even works in FULL-BRIDGE mode.
I am still not sure why LTspice is showing shoot-through. Even using Simon's miller clamp circuit didn't do much on the simuluations, but his answer proved to be useful in supressing ringing and quickening turn off times
I didn't end up trying Russel's snubber circuit as an extra 10 Ω would cause a huge voltage drop, reducing my output volume. However, I think his method is worth a try in combination with Simon's miller clamp circuit if anyone decides to use very low V_GS_threshold MOSFETs for their projects. I think in the live circuit, the MOSFET's V_GS while OFF is not reaching the V_GS_threshold, so there are no false turn ON's caused by it. Instead, it was the due to a wrong capacitor type that was adding a lot of noise into the MOSFET driver which caused the false turn ON's or semi-turn ONs as you saw in the M2's V_DS figure, where the voltage was slanted.
I would like to thank everyone for contributing their ideas. I know it's kind of lame that I'm solving my own problem, so I do apologise. However, Simon and RusselH provided a solution that improved the overall performance of my live circuit, which helped supress some of the noise from my speaker. The question regarding the shoot-though in the LTspice simulation is still up for grabs as I'm still very confused what is happening there.
AI: I think it's Miller capacitance giving you grief. I think that the single-diode implementation of the miller clamp, that you have used (see below) is not working as you expect:
simulate this circuit – Schematic created using CircuitLab
V1 and V2 are ideal sources, producing the following potentials:
I've removed all capacitance from the transistor models, \$C_{ISS}\$, \$C_{OSS}\$ and \$C_{RSS}\$, and inserted a single capacitance C1 to mimic Miller capacitance. Obviously, this is an exaggerated scenario, but it's just to illustrate why the solution I propose at the end can work.
Without a clamp diode, Miller current causes a large voltage drop across R2, switching M2 back on momentarily. M1's drain current looks like this:
When we insert the diode, remembering that the source is ideal, Miller current is effectively bypassed, so only a volt or so appears across R2, and M2 stays off. Drain current stays low:
The diode does well, but its effectiveness depends on the source impedance of the driver. Since all that miller current is being fed right back into the driver's output, any impedance there will cause gate potential to rise, also. The diode is only bypassing R2, not the driver's own output impedance. Here I use R4 to mimic a source impedance of just a few ohm. Miller current through it will cause M2's gate potential to rise again:
simulate this circuit
Below is the resulting gate potential, where you can clearly see that it's enough to switch M2 back on momentarily. After that, the drain current spike returns:
I suggest you try to divert Miller current direct to ground, with a PNP bipolar transistor:
simulate this circuit
In this way only 1% or so of Miller current makes it back through R2 and the driver's output impedance, and the rise in gate potential is attenuated, hopefully enough to prevent M2 from switching on again. Drain current is suitably dampened to a reasonable amount: |
H: How do D flip flops know the correct count sequence?
Let's say we want to show the count sequence 001->010->100->111 using D flip flops. Next step would be making a state table.
After simplifying using K-map, we get D^A=C', D^B=B', D^C=A. Then I built the circuit with two 7474 ICs and it works. If the counter starts with 000, it will go through the wrong sequence (000->110->101->011) . I am confused about how the counter is able to 'avoid' the wrong starting sequences and always get the correct starting sequences every time. I am using 74LS74N IC with both the clear and preset input activated FYI. The function table for both PRE and CLR set high is as follows. Given that it can also start with 000 or any other combination not in the correct sequence, it seems to be magical to me with the fact that it always begins with one of the combinations in the correct sequence every time I powered up the circuit.
AI: When we don't initialize the flipflop, at startup, I think you are expecting the state to be sometimes 0 & sometimes 1. It need not be so. In fact, if it is starting with a 1, it may throw up a 1 always at startup under the same voltage and temperature conditions. However, nothing is guaranteed that is why we say it is unknown state.
Since you confirmed that startup state is 111 always in your measurements, you are not seeing the wrong sequence. |
H: How can I avoid twisting wires in a circuit that rotates?
I am working on a project where I used a hollow pipe whose one end has a circuit board so that the wires will go through the pipe to the other end completing the connections. That pipe has to be rotatable, too. Rotation speed will not be too high, it will be minimal as in a steering wheel and it won't be rotated in only single direction. The problem is that it will result in wires being twisted and broken.
In short : I have an old gaming controller and I am turning into a steering wheel. I have other things designed and was thinking of integratimg afew buttons in the middle of the steering wheel.
I googled and found about slip rings, but I will appreciate if I get other alternative methods and if possible some DIYs.
Circuit brief:
Gamepad used: Quantum QHMPL QHM7468 USB game pad.
When opened, this gamepad has one main circuit board, two triggers (extendable by wires,) one joystick (two integrated) (extendable by wires.)
I have used the triggers as pedals, left the joystick for future use, used a spare mouse (optical sensor) at the end of steering wheel to get signals and convert input signals of mouse to joystick signals using a software.
Now I have the main circuit board left which I want to add on top of the steering wheel for more controls.
Edit :
Main circuit board has four connecting wires, and from that, there originates 10 wires , 4 for joystick, 3 each for a trigger.
You can also tell a way to stop rotation of wheel after some specific angle, example - consider the wheel in initial position so that it can rotate about 480 degrees in both the direction after that it restricts motion (like some barrier inside the arrangement), as wire twisting problem will be only if the user rotates the wheel too much. If the motion will be restricted the wire will be experience much stress.
AI: You can also tell a way to stop rotation of wheel after some specific angle,
You could connect the wheel to the steering mechanism take from an old car
Or you can build your own rotation limiter - you can get more than 360 degrees by stacking limiter sections.
https://www.youtube.com/watch?v=3airCg2Xd-4 |
H: Help with MOSFETs to switch sensor on and off
I have a question, I have noticed similar solution for voltage divider to measure voltage on battery with ESP32 using one pin to enable the divider and have it otherwise off the voltage to save power. My question is if the same principle can be used for sensors, let's say the ESP32 wakes up and depending on time it wants to read a specific sensor, so no need to power all of them all the time. Would this work l? Or is there some glaring issue with this schematic? We are talking about 3.3 V logic and power to the sensors.
AI: Other than Q5 being upside down, it looks great.
Pay attention to the parallel "body diode" between drain and source in a MOSFET.
It may take some time for the sensor to stabilize, check the datasheet or experiment.
A tiny portion of this delay will come from R5 and the capacitance of Q3. (Do not remove R5, it reduces ringing and current spikes.)
\$ t = 2 \cdot R \cdot C \$
Ought to be enough time for the MOSFET, but the sensor may also need some time to stabilize. |
H: TP4056 / thermal pad
I am preparing a circuit using a TP4056. This circuit has a thermal pad. The datasheet says that this pad must be connected to ground or nothing.
However, some forum discussions talk about connecting it to GND or even VIN. Curious, I took apart a commercial module implementing a TP4056 and indeed the pad is connected to VIN. So I'm looking for the best truth. GND, VIN or nothing? Do you have this experience?
AI: This is probably what you are talking about:
Quite possibly they mean "floating" by "impending", a bad translation (Impend means a form of hanging, if I'm not wrong).
The exposed pad appears to be electrically floating. This is the substrate that the chip is made on top of, and is not connected to to anything/anywhere chip-level. That's why the datasheet suggests it to be connected to GND, or left floating.
The voltage levels are low, so I don't think that the layer breaks down easily with voltages less than 20V. So it doesn't matter whether the pad is connected to GND or VIN. I don't know what could be the reason that it's connected to VIN in some designs, but it could be for easier layout. |
H: Why does this circuit stop breaking down with a stronger flyback diode?
On a PCBA, I am using a LED driver to drive a high-power LED. Here is the schematics:
V_IN = 16 V
R_OSC is set so that the gate of the MOSFET is controlled at 150 kHz
R_CS is set so that the current in the LED is 1.5 A
Q1 = STT6N3LLH6 (V_DS = 30 V, I_DS = 6 A)
L1 = SDR1105-150ML (I_RMS = 3.5 A, I_SAT = 8 A)
D1 = PMEG3050EP,115 (I = 5 A, V = 30 V)
I am experiencing something strange. If I manually raise the temperature of the circuit with a hot air station, the diode and/or the transistor always break down (short circuit) at approx. 80°C. If I replace D1 with PMEG4030EP,115 (I = 3 A, V = 40 V), I can raise the temperature to 130°C and it still works.
Looking at the signals with a scope, I was not able to detect any change while the temperature is rising. Here are the signals:
At the gate :
At R_CS:
At the cathode of the LED:
The only two differences between the diodes are:
The reverse voltage (30 -> 40 V)
The reverse current (2.6 mA -> 35 uA)
I am glad that the new diode resolves the temperature breakdown, but I would like to understand why. Do you have an idea?
Thanks.
AI: If I replace D1 with PMEG4030EP,115 (I = 3 A, V = 40 V), I can raise
the temperature to 130 °C and it still works. I am glad that the new diode resolves the temperature breakdown, but I would like to understand why.
Do you have an idea?*
It's quite likely to be reverse current problems as the temperature rises. Here's a side-by-side comparison of the PMEG3050 and the PMEG4030 diodes: -
The reverse leakage current at higher temperatures can get high on Schottky diodes and, the 3050 is massively nastier than the 4030 in this respect. I've used +85 °C for the junction temperature and compared it with 25 °C for both devices.
If I manually raise the temperature of the circuit with a hot air
station, the diode and/or the transistor always break down (short
circuit) at approx. 80°C.
In an ambient of 80 °C the junction might be up at 125 °C and the 3050 will be conducting about 300 mA when reverse biased. On a supply of 16 volts, that's a power dissipation of ~5 watts and it'll burn then fail short circuit and, then the switching transistor fails. |
H: Identify PCB component
Last week my living room thermostat "exploded" when adjusting the room temperature. Well, something inside sounded like exploding and since then it behaves erratically: the measured temperature shows 40 degrees C and the temperature-setting goes up and down automatically.
I'm trying to fix it now, and the only components that could possibly have exploded are shown in the picture:
Two parallel coin-cell-like capacitors I suppose (also considering the marking C21 and C22,) which seem to have a brown-ish smudge around the bottom. The marking shows "113N".
Before I start removing it, what are C21 and C22 and what special properties does it have? What should it be replaced with?
The thermostat is a Honeywell opentherm modulation touch 4T40.
AI: Looking at the PCB, they appear to be wired in parallel. That's a little odd for batteries - you'd just use a bigger battery. They've been spot-welded so you can't replace them like a battery when it's run-out.
So, yes, super capacitors like this or this.
The thermostat has a clock so the super capacitor probably keeps it running when power fails. That implies you can just remove them and it will all work fine - until the power fails.
If/when you replace them, the capacitance won't matter much but measure the voltage with a meter. Some super capacitors can take 3.3V and some 5V. |
H: DI2C differential pair with controlled impedance?
on my project I'm using two PCA9615DPZ chips to extend an i2c bus between two boards.
The situation is:
PCA9615DPZ -> 15cm track -> connector -> 1m cable (CAT5) -> connector -> 15cm track -> PCA9615DPZ
But I have a couple of doubts:
1 - Do I have to use differential traces with controlled impedance? I didn't find a note about this in the datasheet, but is it necessary to use 100 ohm or 120 ohm differential traces?
2 - In case controlled impedance traces are needed, using a calculator I get that for a basic 4 layer stackup, the traces are about 0.1 mm, therefore very small. Could I have problems with my situation using such small traces? (I think they carry very little current)
3 - I have exactly the same problem with an RS-422 Transceivers MAX3077EASA+T, in which I find myself in exactly the same condition, are the same 1 & 2 considerations valid for this too?
In both cases I use a fairly low baud rate, but if it helps I can also go down to quite low baud rates.
AI: For all questions, in theory, as you have a 100 ohm impedance cable for differential data and 100 ohm termination, you should also use 100 ohm differential pair for PCB tracks.
Another thing is what happens if you don't, as that is difficult to guess, as the PCB trace length is only 15cm. But any discontinuities in the impedance means that part of the signal gets reflected back.
And it does not depend on how fast the data rate is, but how fast the signal edges are. Of course even with fast edges, slowing the data rate helps.
Unfortunately the MAX3077E is intended for 16 Mbps and higher data rates so it has very fast edges. The slew rate is less than 15ns, while a 15cm PCB track has 1ns propagation time. It may work without issues.
The track width should handle any normal situation. |
H: RC circuit oscillator
I want to make a simple RC oscillator circuit that produces waveforms of
How can I do so?
AI: Two options:
Use 555 to generate very low on-time. I'm not sure whether it'll be practical as you may end up with ridiculously low component values.
Generate a clock with 555 or relaxation oscillator (doesn't have to have 50% duty-cycle but better to keep on- and off-times long enough). And run it through a CR high-pass filter. Thanks to its differentiating behaviour the output will be rising and falling edges of the input clock (with short decaying due to the presence of R). So it won't give you perfectly short edges. But you can play with values to find a sweet spot. The cut-off frequency of the filter should be, of course, higher than the input's frequency. But should be low enough to chop off the pulses.
Img Source: this et.ws article
With a diode placed across the R the negative pulses can be chopped off (clamped to Vf of the diode, so it's better to use a schottky for minimum voltage drop). Also, it's better to pick the C first and calculate R accordingly. Note that as you decrease R the pulses will get shorter but the amplitude will drop as well.
Here's a quick example for 100 kHz (blue: input, green: output): |
H: Thermally insulating peltier cell
I'm trying to build a small cloud chamber using peltier cells. I've been using a TEC2 25408 and a cooler master 412S. So far I've tried to measure the lowest temperature the peltier can reach by placing it on the top of the fan cooler using thermal paste. With this setup I was able to obtain a temperature of about -29.4°C on the cold side of the peltier cell (which is acceptable, I think, since, to make the isopropyl alchool reach the superaturate state, there are required at least -25°C). To make the base of the cloud chamber, I've then tried to place on the cold side of the peltier a 100mm x 100mm x 2mm copper plate, using thermal paste. Since I increased the mass, I was expecting that it would have been cooled down much more slowly, and I was also expecting that the temperature reached could have been higher than -25°C: the reached temperature was about -12°C, indeed, measured directly above the peltier.
To me the problem seems to be that the peltier is not properly thermally insulated. Hence, I thought that it would be useful to insert the peltier inside a layer of polystyrene so that the cooling power concentrates on the copper plate. But I'm not sure this configuration works. Moreover closing the chamber with a plexiglass block limits the mass of air with which the peltier thermally interacts, so this should help lowering the temperature.
I wanted to ask, is the thermal insulation the actual problem? And in that case, have you got any ideas on how to properly insulate the peltier such that plate could reach at least -25°C not only in the center but almost on each point?
P.S. Thanks a lot in advance for any eventual answer and excuse my english, as I'm still learning it!
on top there is the copper plate, then the peltier, then the fan
AI: What you're seeing is that when you add the copper plate, not just the thermal mass is increased, but also the surface area increases, and hence the thermal resistance decreases. Effectively the copper plate is acting as a radiator.
If you're building a cloud chamber, then presumably you'll be putting this in glass so you'll get some insulation from that. You could also insulate the bottom of the copper in order to only radiate from the useful side.
As for getting -25 *C across the plate, you could make it a bit thicker, and thus it would be more thermally conductive and the temperature across it would be more closely matched, but for the most part, I think you might need to increase the power of your Peltier. The cooling on the hot side of the Peltier is also a limiting factor, so you could see a benefit if you increased this. |
H: Why is my oscilloscope’s output stuck at 0?
I am new to using oscilloscopes. When I was consistently getting zero voltage in an experiment I was doing, I decided to test whether my oscilloscope was working properly.
I set up a very simple circuit consisting of only a power supply at 3 volts and a resistor. However, the measurement on the oscilloscope of the voltage drop across the resistor remains jittering around zero.
Increasing the voltage causes a brief increase in the reading before it falls back down to zero. Is there something I am doing wrong or is the oscilloscope faulty?
AI: Both channels are set to AC from your image. The ~ sign denotes AC.
You need to switch to DC in the scope settings. |
H: Electrical fast transient waveform (switching circuit) load
I am simulating a circuit to model the EN 61000-4-4 waveform for electrical fast transients using LTspice. The idea is to have the generator for some in house testing.
Here is an old question I have that shows some of the progress done so far.
The waveform is a high voltage low energy pulse. Here is what the waveform looks like:
I do not need the exact waveform specification as this is needed for in house testing.
The standard provides with a very simplified equivalent circuit, but it is so simplified it is useless:
I want to model the switching circuit.
The idea is to feed the switching circuit with a high DC voltage and by performing ON/OFF function to generate these high voltage, low current pulses that will be then injected to various loads (I/O cables, power cables,etc.)
Here is a block diagram for that:
I have already modeled the circuit in LTspice, and simulated a few results that can be seen in the previous post. For simplicity I will reattach it here.
Here is the switching circuit:
It does not work as intended because the load R_LOAD presents a small resistance compared to the C1 capacitor, the capacitor does not charge to the input voltage level.
Here are some simulations:
This is the ideal result that I would like to get for all loads:
Here is the result for a 50 ohm load:
AI: C1 is not doing anything in your circuit, in fact it's actively harming its operation. When you turn on the MOSFET, C1 just discharges through the FET, heating it up. It does not transfer any energy to the output. You should therefore remove C1.
C2 actually stores the energy that gets delivered to the load. Its "left side" charges up to 500V, while the "right side" stays at 0V. When the MOSFET pulls the left side to ground, the right side will then be at -500V, producing your desired transient (although negative, but this shouldn't matter). C2 then slowly discharges, producing the decaying waveform.
Your MOSFET is also currently not switching on fast enough for the transient to reach its maximum voltage - the voltage across C2 decays already while the FET is still turning on. As a result, you have to switch your FET faster, which you can do by decreasing the value of R1, or maybe even removing it entirely.
So, in short: Remove C1, replace R1 with a short, and then adjust the value of C2 until you get the desired waveform (with the load in place).
If you actually need the full 1kV output voltage, you'll have to use a different MOSFET, i.e. a silicon carbide FET. Note, though, that a rise time of 10ns or less is more than just unrealistic with this circuit. |
H: Why do some DC to DC converters use high inductor values (ie: 220uH or more), while some of them use much lower value inductors (ie: 3.3uH or less)
I've noticed that many DC to DC converters that have have almost the same current output will have inductors that vary vastly in their rating.
For instance, I've got two separate buck-boost modules for battery charging and discharging. They have roughly the same technical specs, with one of them being slightly higher power (120 watt vs 100 watt.)
The 120W module has a 3.3uH inductor, while the 100W module has a 100uH inductor. In fact, I've got another similar module that has a 330uH inductor.
I've tried watching videos on how people select their inductors, but can't seem to figure out what exactly makes them require a low value inductor vs a high value inductor. The datasheets for the ICs will tell you what they prefer, but won't say why or much else.
My only assumption is that it has to do with the switching frequencies being different.
AI: If the switching regulator is using a lower frequency, then the inductor must have a higher value.
The current through the coil should not going to zero with time gaps, this would create a "ringing", what leads to energy loses. The minimum current must match to the inductance.
Here you can simulate a bit with different values with this StepDown example:
http://schmidt-walter-schaltnetzteile.de/smps/abw_smps.html |
H: Controlled impedance stackup questions
In this stackup (I know that it is not the best stackup but it is a general question,) if I choose to use controlled impedance on L4 (let's say 50 ohm), what is the reference that needs to L4 signals?
It's a stripline so it should be two layers (3 and 5.)
Is it possible to route a stripline signal with only 1 reference layer in L5?
AI: The power & ground planes above/below Layer-4 are significant. This is a stripline.
If you routed on Layer-5 and keep it mostly as a plane, then you will have a coplaner stripline. Most of the effects will be between the ground plane on L5 and the trace. Any traces crossing the stripline conductor on L4 & L6 will affect the impedance. Generally, not recommended unless you can avoid crossing traces. |
H: Complex number or absolute number for impedance
I am reading about high speed PCB layout design from TI (Texas pdf)
This document mentioned the software AppCAD from Agilent to calculate impedance. Here is the snapshot.
My question here is whether this Z0 a complex number or not.
If it omits imaginary part, why will we use this software instead of calculator? Does H(Height) and dielectric \$\varepsilon_r\$ matter in this scenario?
AI: \$Z_0\$ is the characteristic impedance of a transmission line is given as:$$Z_{0}=\sqrt{\frac{R+j\omega L}{G+j\omega C}}$$
\$R\$ and \$L\$ are the series resistance and inductance per unit length. \$G\$ and \$C\$ are the parallel conductance and capacitance per unit length across the transmission line.
If \$R\$ and/or \$G\$ are significant then energy is lost to heating resulting in what is called a lossy line.
If these two are insignificant, then they are approximated as zero, reducing the expression to:$$Z_{0}=\sqrt{\frac{L}{C}}$$ which is purely resistive.
If it omits imaginary part...
Actually it doesn't. The linear resistivity of the copper and the conductivity of the fibreglass is sufficiently small that the \$j\omega\$ factors cancel out from the numerator and the denominator.
The real parts are the ones being ignored, or put in a better way are treated as being insignificant.
Addition:
why will we use this software instead of calculator? Does H(Height) and dielectric \$\epsilon_r\$ matter in this scenario?
The IPC-2141 standard provides a calculation for L and C. Cadence has some good information. I repeat the IPC-2141 microstrip equations to show the need for \$H\$ and \$\epsilon_r\$:
$$Z=\frac{87}{\sqrt{\epsilon_r + 1.41}}\text{ln}\left(\frac{5.98H}{0.8W+T}\right)$$
$$C=\frac{0.67(\epsilon_r + 1.41)}{\text{ln}\left(\frac{5.98H}{0.8W+T}\right)}\text{pF/in}$$
$$L=5.071\text{ln}\left(\frac{5.98H}{0.8W+T}\right)$$
Clearly all the parameters including the thickness \$T\$ are needed. Either the software or a hand calculator can be chosen to calculate. |
H: Can a small signal BJT handle small currents of reverse voltage (Vce) for a short time?
I have this piece of circuit with a 12V supply. I think it will work better in my application without the reverse diode. Do you think it can handle the reverse voltage of C8 that remains charged for a minute or so until it is discharged through the resistors?
AI: D16 prevents any reverse current through the emitter. As a result, Q2 essentially becomes a plain diode from collector to base during this reverse discharging operation. This is completely fine and D13 can be safely removed.
In general though, don't trust LTspice on this reverse bias behavior. It doesn't account for B-E reverse breakdown. |
H: Transmission Line Powering Load
Consider a long transmission line (4 km). Its a single conductor line with the inner conductor insulated. The outer shell is steel ground.
Consider two scenarios.
Scenario A: 120 V DC power supply, positive is hooked up to long transmission line, which is connected to 30 Ω load. Negative on the power supply is connected directly to the load.
Scenario B: 120 V DC power supply, positive AND negative are hooked up to long transmission line, which are both connected to the same load in Scenario A.
My question is, will scenario B draw more power or the same power than scenario A? The ground wire is taking a major shortcut in scenario A, so intuitively I would suspect that scenario B would take twice the power to drive the load then scenario A, since the ground wire is adding twice the length of effective wire length.
Excuse me if this is a rookie question, I just can't wrap my mind around it.
AI: The power in the load is $$P_L = I^2 R_L=\left(\frac{V}{R_L + R_{cond} + R_{ground}}\right)^2R_L ,$$ and the power drawn from the supply is $$P_S= IV=\frac{V^2}{R_L + R_{cond} + R_{ground}}$$
For the resistances given, $$P_{LA} = \left(\frac{120}{30+40+0}\right)^2 x 30 = 88.2 W and P_{SA} = 205 W$$ and $$P_{LB} = \left(\frac{120}{30+40+40}\right)^2 x 30 = 35.7 W and P_{SB} = 130 W.$$
In either case, a very inefficient power delivery.
In any case, it's impossible for scenario A to draw twice the supply power unless $$R_L = 0$$ and $$R_{cond}=R_{ground}.$$ |
H: Input resistance of an op-amp circuit
I need to find the input resistance of this circuit. There are two parts of this exercise:
The first one is to find the input resistance of the circuit without the capacitor.
The second is to the find the input resistance of the circuit with the capacitor ( C = 1nF.)
It is not mentioned if the op-amp is ideal or not.
I have seen a lot of topics related to this subject but I haven't figured it out yet. Do I need to find the equivalent resistance of the circuit? Do I have to take into account the interior components of the op-amp?
AI: Whether C is in place or not has no effect on the characteristics of the non-inverting input. Considering that the system consisting of \$v_S\$, \$R_1\$ and \$R_2\$ is effectively disconnected from anything else in the circuit (by the opamp's high input resistance), you can ignore everything else.
I suppose that this particular op-amp could have terribly low input impedance, or significant input bias current, or \$R_1\$ and \$R_2\$ are so large that its input impedance becomes significant. Then \$C\$ might feature in your calculations, but one of the benefits of op-amps, to remove such nuisance dependencies between inputs and everything else, is defeated anyway.
So, without further context, I don't think your question requires anything more than a simple addition. |
H: Find the equivalent resistance
I have to simplify the following circuit by using equivalent resistance. I know it probably should be very simple to do it, but for some reason, I can’t tell if the two resistors in the “internal” mesh are in series or in parallel with the other resistor R, in the external mesh.
MY GUESS
I was able to simplify the circuit only to this point, by using the fact that:
There is a short circuit between node a and node b
The two resistors in the internal mesh are equivalent to one resistor of resistance 2R, since they are in series
My question is: are these two in series or in parallel? I would say in parallel, but the fact that there is just one node confuses me, I think.
AI: You did well. You can imagine that the dot in parallel with 2R is a wire. In other words they are shorted.
However, normally, an equivalent resistance is usually taken between 2 nodes (sometimes, one of them is ground). In your network, after getting rid of the 2R, I still see a loop of wire in parallel with R. In that case, I'd say the total R of the network is 0. |
H: Input resistance of an inverter op-amp circuit
I need to find the input resistance of this circuit. There are two parts of this exercise:
The first one is to find the input resistance of the circuit without the capacitor.
The second is to the find the input resistance of the circuit with the capacitor ( C = 10 nF.)
It is not mentioned if the op-amp is ideal or not.
Do i make it by finding the equivalent impedance of R3, R4, C and R5?
AI: I need to find the input resistance of this circuit. Do I make it by finding the equivalent impedance of R3, R4, C and R5?
It's slightly simpler than that. Because the -Vin input is a virtual ground, you can regard it as a short-circuit to ground and hence, R5 can be ignored. This then makes the input impedance: -
$$Z_{IN}\hspace{1cm}=\hspace{1cm}R_3 + X_C||R_4$$
This answer assumes an ideal op-amp.
Can you take it from here? |
H: Connecting FETs to make a push pull GPIO
We have a circuit that generates pulses via GPIO. We use FETs for the push-pull mechanism.
Our schematic:
Description of the push-pull mechanism.
According to this source, connecting two FETS like that is a bad practice which can cause short-circuit.
Should we change our design? Is this considered bad practice?
AI: In the case of bipolar transistors in that role:
simulate this circuit – Schematic created using CircuitLab
The base-emitter junctions of these transistors are just diodes. Look carefully, for a couple of problems:
The direction of the diodes clearly show a route for current from the positive supply right down to ground. That's almost a short circuit, and current will be huge. Junctions will die.
Both junctions have well over 0.7V across them. Both transistors are switched very, very on, if they haven't died already from excessive base current. That's another path for unlimited current to flow between the supply rails. One or both of those transistors will soon be toast.
Whatever is connected to those bases will also have to supply a lot of current, and may also fall victim to this design.
In the case of MOSFETS, the base current issue goes away, because there's extremely high impedance between the MOSFET's gate and its channel. Let's have a look at the situation where the power supply voltage is very small, 3.3V, and the gate threshold voltage for each MOSFET is 2.0V:
simulate this circuit
Both of those transistors are off right now, because neither has sufficient \$V_{GS}\$ to switch them on. The top transistor can only switch on when the potential at its gate falls below 1.3V (3.3V - 1.3V = 2.0V). The lower transistor requires a gate potential of +2.0V to switch on. Clearly the situation where both transistors are on simultaneously (creating a short circuit across the supply, and causing current to "shoot-through") is not possible here.
Look at what happens when we increase the power supply to +12V, using the same components, and placing their gates half way between supply potentials:
simulate this circuit
Now both transistors are switched fully on, even though all we did was increase the supply voltage, keeping the gates at a half way potential. That's obviously going to cause some smoke somewhere.
When we connected BJT bases together, we formed a near short-circuit across the power supply, but that problem is gone here because the gates are electrically insulated from the channels. That's not to say that gate current won't be an issue at all; even though the gates are isolated, they have capacitance with the channel, and that capacitance is a very low impedance at high frequencies. When gate potentials are switched between high and low very fast and frequently, a very significant amount of current can flow into and out of them.
Still, nothing bad will happen if the both gates are at +12V, or both are at 0V. It's during the transition between those states that the problem of shoot-through occurs.
Aside from shoot-though, this design is a good one, and is in common use. There are a number of approaches designers can take regarding shoot-through:
Make sure gate transition is as fast as possible, spending as little time as possible in that zone where both transistors are on.
Use transistors with gate thresholds closer to (or greater than) half-supply.
Include deliberate resistance in the channels, to limit current.
Change how we drive the gates, to introduce "dead-time" that ensures that one transistor is switched off before the other is switched on.
Suck it up, accept that shoot-through occurs, that's the price you pay for speed.
The other thing that someone is bound to bring up in the comments. |
H: What is the purpose of this diode in the battery management system schematic?
I have a doubt about the function of the diode D6 shown in this schematic
The schematic is for a battery management system and the diode is between the +,- terminals of the total voltage:
I do not know about that diode since I could not find its datasheet and I also looked for different diode symbols but no succeed, I guess it is a kind of schottky diode and it is to protect against reverse polarity when charging the battery pack.
Could somebody explain me please?
AI: D6 is an TVS diode. It's an ESD supressor, as PACK+ signal is placed in the connector, it's susceptible to receive and ESD if someone touch the pin or something. For that reason, a TVS is placed to avoid damage other circuitry because of that event. It's a safety feature.
Here is the datasheet of the diode if you want to have a look to it: https://eu.mouser.com/datasheet/2/115/DIOD_S_A0000285740_1-2541913.pdf
;) |
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