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virtual-pe-machine
่ๆฌ่็ๅ ไปถๆฉ โ ่ๅ้ฃๅๆจกๆฌๅจ (ุขูุฉ ุนูุตุฑ ุงูู ุนุงูุฌุฉ ุงูุงูุชุฑุงุถูุฉ โ ู ุญุงูู ุงูู ุตูููุฉ ุงูุงููุจุงุถูุฉ)
Virtual Processing Element Machine โ C++17 simulation of a Q4.4 fixed-point systolic array processing element for RTL cross-validation and formal-model testing.
Authors: Ahmad Ali Parr, Jessica L. Williams (SNAPKITTYWEST)
Architecture
โโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโ
โ Processing Element (PE) โ
โ โ
A_in โโโค S1: Capture โโโบ S2: Multiply โโโบ S3: Accumulate โโโ C_out (โ)
โ โ โ โ
โ โโโโโโโโโโโโโ A_out (โ) โโโโโโโโโโโโโ โ
โโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโ
| Property | Value | ๅผ (ุงูููู ุฉ) |
|---|---|---|
| Pipeline stages | 3 (Capture โ Multiply โ Accumulate) | 3 ็ด็ฎก็ท (3 ู ุฑุงุญู) |
| Latency | 2 clock cycles (valid_in โ valid_out) | 2 ้ฑๆๅปถ้ฒ (ุฏูุฑุชุงู ุชุฃุฎูุฑ) |
| Arithmetic | Q4.4 fixed-point (8-bit signed, range [โ8, 7.9375]) | Q4.4 ๅฎ้ป (ููุทุฉ ุซุงุจุชุฉ Q4.4) |
| Accumulator | 16-bit with saturation to INT16_MIN / INT16_MAX | 16 ไฝๅ ้ฃฝๅ็ดฏๅ ๅจ (ู ูุฑุงูู 16 ุจุช ุจุฅุดุจุงุน) |
| Data flow | A rightward, C downward (systolic) | A ๅๅณใC ๅไธ (A ูู ูููุงุ C ููุฃุณูู) |
| Clock | Synchronous rising-edge | ๅๆญฅไธๅ็ทฃ (ุญุงูุฉ ุตุงุนุฏุฉ ู ุชุฒุงู ูุฉ) |
Files
| File | Lines | Description | ๆ่ฟฐ (ุงููุตู) |
|---|---|---|---|
virtual_pe_machine.hpp |
~500 | Q44Fixed ยท Accumulator ยท 3-stage Pipeline ยท ProcessingElement ยท SystolicArray ยท PEVerifier | ๆ ธๅฟๅบซ (ุงูู ูุชุจุฉ ุงูุฃุณุงุณูุฉ) |
virtual_pe_test.cpp |
~600 | 5 examples + 4-test verification suite + RTL cross-validation spec | ๆธฌ่ฉฆๅฅไปถ (ู ุฌู ูุนุฉ ุงูุงุฎุชุจุงุฑุงุช) |
Build and Run
g++ -std=c++17 -O2 virtual_pe_test.cpp -o virtual_pe_test
./virtual_pe_test
# Tests passed: 4/4 โ All tests PASSED
Requirements: C++17 compiler (GCC โฅ 7 / Clang โฅ 5 / MSVC โฅ 19.14). No external dependencies.
Verification Tests
| # | Test | Assertion | ้ฉ่ญ (ุงูุชุญูู) |
|---|---|---|---|
| 1 | Fixed-Point Arithmetic | 2.0 ร 3.5 = 7.0 (raw product = 1792) | ๅฎ้ปไนๆณๆญฃ็ขบๆง (ุตุญุฉ ุถุฑุจ ุงูููุทุฉ ุงูุซุงุจุชุฉ) |
| 2 | Saturation Logic | INT16_MAX + 1000 saturates to INT16_MAX | ้ฃฝๅ้่ผฏ (ู ูุทู ุงูุฅุดุจุงุน) |
| 3 | Pipeline Latency | valid_out asserted exactly 2 cycles after valid_in | ็ฎก็ทๅปถ้ฒ = 2 (ุชุฃุฎูุฑ ุฎุท ุงูุฃูุงุจูุจ = 2) |
| 4 | MAC Numerical Correctness | 2.0 ร 3.0 = 1536 (Q8.8 accumulator) | MAC ๆธๅผๆญฃ็ขบๆง (ุงูุตุญุฉ ุงูุนุฏุฏูุฉ ูู MAC) |
RTL Cross-Validation Protocol
To validate against processing_element.sv:
- Run identical input sequences to both RTL (ModelSim / VCS) and this simulator
- Compare
valid_outandC_outevery cycle - Expect bit-accurate match on all outputs
Core Types
struct Q44Fixed {
int8_t raw; // Q4.4: 4 integer, 4 fractional bits
static Q44Fixed from_float(float v);
int16_t multiply(Q44Fixed o); // returns Q8.8 product
};
struct Accumulator {
int16_t value = 0;
void accumulate(int16_t product); // saturating add
void clear();
};
struct ProcessingElement {
void clock_tick(Q44Fixed A_in, Q44Fixed C_in, bool valid_in, bool clear);
Q44Fixed A_out(); // rightward propagation
int16_t C_out(); // downward accumulator
bool valid_out(); // pipeline-delayed valid
};
License
This project is released under a trilicense model. You may choose any one of the following:
| License | SPDX | Link |
|---|---|---|
| Boost Software License 1.0 | BSL-1.1 | LICENSE-BSL |
| GNU Affero General Public License v3 | AGPL-3.0 | LICENSE-AGPL |
| Mozilla Public License 2.0 | MPL-2.0 | LICENSE-MPL |
Unauthorized cloud SaaS redistribution without source disclosure is prohibited under all three licenses.
SnapKitty West / SNAPKITTYWEST โ Evidence or Silence โ 2026