float FMA: fused multiply-add with a single rounding (F extension). A composed gate netlist (pre-normalize a/b/c, full product, dual sticky align shifters into a max-exponent field, cancellation-correct signed-magnitude add, normalize, one round-to-nearest-even, gradual underflow, full specials) for float16 and float32, validated bit-exact against the single-rounding oracle. FMADD/FMSUB/FNMADD/FNMSUB.S wired into the RV32 assembler, reference, and threshold CPU (gate-computed, lockstep-verified); composed FMA test in the eval suite; all variants and neural_rv32 rebuilt.

remove the superseded standalone float normalize stages from the core generators and their structure checks; the composed pipelines carry their own normalizers

float div: full IEEE subnormal support (pre-normalize both operands, then right-shift the aligned quotient by max(0,1-er) for gradual underflow); oracle validated bit-exact against numpy; all float variants rebuilt. add/mul/div subnormals now complete.

float mul: full IEEE subnormal support via a unified right-shift renormalizer (right-shift the product by F+1-min(nlz,exp_base)); oracle validated bit-exact against numpy over all classes including deep underflow; all float variants rebuilt

float add: full IEEE subnormal support (subnormal operands and gradual-underflow results) via effective exponent, implicit-bit selection, and a clamped normalize shift; oracle validated bit-exact against numpy float32/float16

Move source library into src/; repoint module, tool, and README paths