diff --git "a/build/webgpu/test.json" "b/build/webgpu/test.json" --- "a/build/webgpu/test.json" +++ "b/build/webgpu/test.json" @@ -1,5 +1,4 @@ { - "op": "com.microsoft.FusedConv", "fixtureArrays": { "input_x_relu_1x1_sgmat_c32_hw64": [-0.9157503247261047, -0.4178330898284912, 1.049560546875, 1.1539052724838257, -0.6441117525100708, 1.0497760772705078, 0.22678443789482117, 0.8246340751647949, -1.611849069595337, 0.3388766646385193, -0.8985162973403931, -0.5346295833587646, 1.3242034912109375, -1.4821581840515137, 0.3748220205307007, -0.46265047788619995, 0.9666540622711182, 0.5917047262191772, 0.46700504422187805, -0.5195906162261963, -0.3704409599304199, 0.29766780138015747, 0.9497795104980469, -1.038686990737915, -0.6015446186065674, -0.253448486328125, -1.915745735168457, 2.1778969764709473, -1.4943428039550781, -0.3997105360031128, 2.327956199645996, -0.21661806106567383, 0.5250077247619629, -0.6107833981513977, 1.4030895233154297, -0.33188870549201965, 1.9051439762115479, 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explicit kernel_shape while leaving strides, dilations, and pads omitted." + "notes": "A one-dimensional HardSwish fusion supplies `kernel_shape` explicitly while using default strides, dilations, and pads." }, "attrs": { "activation": "HardSwish", "kernel_shape": [1] }, "inputs": { @@ -71,7 +70,7 @@ "provenance": { "source": "onnxruntime/test/contrib_ops/fused_conv_test.cc", "test": "FusedConvTest.Conv2D_HardSigmoid", - "notes": "Same compact ORT HardSigmoid shape, but with non-default activation_params to catch kernels that bake the default alpha/beta." + "notes": "A compact ORT HardSigmoid case with non-default `activation_params` verifies that alpha and beta are not fixed to their defaults." }, "attrs": { "activation": "HardSigmoid", "activation_params": [0.1, 0.4] }, "inputs": { @@ -158,7 +157,7 @@ "provenance": { "source": "onnxruntime/test/providers/coreml/coreml_basic_test.cc", "test": "CoreMLExecutionProviderTest.FusedConvTestSigmoid", - "notes": "Compact deterministic projection of ORT/CoreML FusedConv Sigmoid activation dispatch coverage." + "notes": "A compact deterministic ORT/CoreML case exercising the fused Sigmoid activation." }, "attrs": { "activation": "Sigmoid" }, "inputs": { @@ -190,7 +189,7 @@ "provenance": { "source": "onnxruntime/test/providers/coreml/coreml_basic_test.cc", "test": "CoreMLExecutionProviderTest.FusedConvTestTanh", - "notes": "Compact deterministic projection of ORT/CoreML FusedConv Tanh activation dispatch coverage." + "notes": "A compact deterministic ORT/CoreML case exercising the fused Tanh activation." }, "attrs": { "activation": "Tanh" }, "inputs": { @@ -304,7 +303,7 @@ }, { "name": "relu_1x1_sgmat_c32_hw64", - "provenance": { "source": "generated reference values", "test": "sgmat-eligible FusedConv epilogue" }, + "provenance": { "source": "synthetic", "test": "sgmat-eligible FusedConv epilogue" }, "attrs": { "activation": "Relu" }, "tolerance": 0.001, "relTolerance": 0.001, @@ -333,7 +332,7 @@ }, { "name": "relu_1x1_sgmat_bias_z_c32_hw64", - "provenance": { "source": "generated reference values", "test": "sgmat-eligible FusedConv epilogue" }, + "provenance": { "source": "synthetic", "test": "sgmat-eligible FusedConv epilogue" }, "attrs": { "activation": "Relu" }, "tolerance": 0.001, "relTolerance": 0.001, @@ -378,7 +377,7 @@ }, { "name": "relu_1x1_sgmat_bias_c32_hw64", - "provenance": { "source": "generated reference values", "test": "sgmat-eligible FusedConv epilogue" }, + "provenance": { "source": "synthetic", "test": "sgmat-eligible FusedConv epilogue" }, "attrs": { "activation": "Relu" }, "tolerance": 0.001, "relTolerance": 0.001, @@ -415,7 +414,7 @@ }, { "name": "relu_1x1_sgmat_z_c32_hw64", - "provenance": { "source": "generated reference values", "test": "sgmat-eligible FusedConv epilogue" }, + "provenance": { "source": "synthetic", "test": "sgmat-eligible FusedConv epilogue" }, "attrs": { "activation": "Relu" }, "tolerance": 0.001, "relTolerance": 0.001, @@ -481,7 +480,7 @@ }, { "name": "relu_3x3_im2col_sgmat_c32", - "provenance": { "source": "generated reference values", "test": "sgmat-eligible FusedConv epilogue" }, + "provenance": { "source": "synthetic", "test": "sgmat-eligible FusedConv epilogue" }, "attrs": { "activation": "Relu" }, "tolerance": 0.001, "relTolerance": 0.001, @@ -510,7 +509,7 @@ }, { "name": "relu_3x3_im2col_sgmat_bias_z_c32", - "provenance": { "source": "generated reference values", "test": "sgmat-eligible FusedConv epilogue" }, + "provenance": { "source": "synthetic", "test": "sgmat-eligible FusedConv epilogue" }, "attrs": { "activation": "Relu" }, "tolerance": 0.001, "relTolerance": 0.001, @@ -555,7 +554,7 @@ }, { "name": "relu_3x3_im2col_padded_c16", - "provenance": { "source": "generated reference values", "test": "sgmat-eligible FusedConv epilogue" }, + "provenance": { "source": "synthetic", "test": "sgmat-eligible FusedConv epilogue" }, "attrs": { "activation": "Relu" }, "tolerance": 0.001, "relTolerance": 0.001, @@ -584,7 +583,7 @@ }, { "name": "relu_3x3_im2col_padded_bias_z_c16", - "provenance": { "source": "generated reference values", "test": "sgmat-eligible FusedConv epilogue" }, + "provenance": { "source": "synthetic", "test": "sgmat-eligible FusedConv epilogue" }, "attrs": { "activation": "Relu" }, "tolerance": 0.001, "relTolerance": 0.001, @@ -629,7 +628,7 @@ }, { "name": "relu_direct_z_nobias", - "provenance": { "source": "generated reference values", "test": "sgmat-eligible FusedConv epilogue" }, + "provenance": { "source": "synthetic", "test": "sgmat-eligible FusedConv epilogue" }, "attrs": { "activation": "Relu" }, "tolerance": 0.001, "relTolerance": 0.001, @@ -753,8 +752,8 @@ { "name": "reg_im2col_3x3_bias_m256_n1024_below_prior_floor", "provenance": { - "source": "authored for route coverage", - "notes": "Sits at 64 register tiles: above the shared im2colRegMinWorkgroups floor, below the 128 the im2col bias gate used to hand-type. Nothing selected im2col_gemm_tiled_bias_reg between 64 and 127 tiles before." + "source": "synthetic", + "notes": "The 3x3 biased convolution produces 64 register tiles, exercising the register-tiled im2col GEMM specialization at its shared workgroup floor." }, "attrs": { "activation": "Relu" }, "tolerance": 0.002, @@ -824,8 +823,8 @@ { "name": "reg_1x1_bias_m256_n1024_below_prior_floor", "provenance": { - "source": "authored for route coverage", - "notes": "Sits at 64 register tiles: above the shared im2colRegMinWorkgroups floor, below the 128 the 1x1 bias gate used to hand-type. Nothing selected gemm_1x1_tiled_bias_reg between 64 and 127 tiles before." + "source": "synthetic", + "notes": "The biased 1x1 convolution produces 64 register tiles, exercising the register-tiled direct GEMM specialization at its shared workgroup floor." }, "attrs": { "activation": "Relu" }, "tolerance": 0.002, @@ -885,18 +884,13 @@ }, { "name": "clip_neginf_residual_defined_result", + "provenance": { + "notes": "A negative-infinity residual drives every clipped position to the activation minimum whatever the convolution produced, so the activation and weight fills are uniform." + }, "attrs": { "activation": "Clip", "activation_params": [-0.5, 0.5], "strides": [1, 1], "pads": [1, 1, 1, 1] }, "inputs": { - "x": { - "dtype": "float32", - "shape": [1, 8, 6, 6], - "data": { "kind": "fillFloat32", "sinStep": 0.5, "cosStep": 0.25, "scale": 0.3, "offset": 0.0 } - }, - "w": { - "dtype": "float32", - "shape": [8, 8, 3, 3], - "data": { "kind": "fillFloat32", "sinStep": 0.17, "cosStep": 0.31, "scale": 0.05, "offset": 0.0 } - }, + "x": { "dtype": "float32", "shape": [1, 8, 6, 6], "data": { "kind": "constant", "value": 0.3 } }, + "w": { "dtype": "float32", "shape": [8, 8, 3, 3], "data": { "kind": "constant", "value": 0.05 } }, "zResidual": { "dtype": "float32", "shape": [1, 8, 6, 6], "data": { "kind": "negativeInfinity" } } }, "outputs": { "y": { "dtype": "float32", "shape": [1, 8, 6, 6] } } @@ -921,7 +915,7 @@ { "name": "relu_3x3_unaligned_k_c48m64_8x8", "provenance": { - "notes": "Compact companion for bench case fusedconv-3x3-unalignedK-c48m64-32x32, where the subgroup-matrix im2col path has a large no-subgroups fallback gap." + "notes": "A compact 3x3 convolution with 48 input and 64 output channels exercises an unaligned im2col reduction and its no-subgroups fallback." }, "attrs": { "activation": "Relu", "strides": [1, 1], "pads": [1, 1, 1, 1] }, "tolerance": 0.002, @@ -943,7 +937,7 @@ { "name": "relu_3x3_aligned_k_c64m64_8x8", "provenance": { - "notes": "Compact companion for bench case fusedconv-3x3-alignedK-c64m64-32x32, where the subgroup-matrix im2col path has a large no-subgroups fallback gap." + "notes": "A compact 3x3 convolution with 64 input and output channels exercises an aligned im2col reduction and its no-subgroups fallback." }, "attrs": { "activation": "Relu", "strides": [1, 1], "pads": [1, 1, 1, 1] }, "tolerance": 0.002, @@ -965,11 +959,11 @@ { "name": "relu_3x3_dense_c256m256_8x8", "provenance": { - "notes": "Compact companion for bench case fusedconv-3x3-dense-c256m256-32x32, preserving the wide im2col K/M shape that exposes the subgroup-matrix fallback gap." + "notes": "A compact 3x3 convolution with 256 input and output channels preserves the wide im2col reduction and output-channel dimensions of the subgroup-matrix fallback regime." }, "attrs": { "activation": "Relu", "strides": [1, 1], "pads": [1, 1, 1, 1] }, - "tolerance": 0.006, - "relTolerance": 0.006, + "tolerance": 0.001, + "relTolerance": 0.001, "inputs": { "x": { "dtype": "float32", @@ -987,7 +981,7 @@ { "name": "relu_3x3_reg_tile_c32m256_32x32", "provenance": { - "notes": "Correctness lock for the 128-lane 32x32 register-blocked im2col GEMM route. The model-like channel and spatial dimensions cross its derived workgroup-saturation gate while keeping reference cost bounded." + "notes": "A 3x3 Relu convolution from 32 input channels to 256 output channels over a 32x32 image exercises the 128-lane register-blocked im2col multiplication." }, "attrs": { "activation": "Relu", "strides": [1, 1], "pads": [1, 1, 1, 1] }, "tolerance": 0.004, @@ -1047,7 +1041,7 @@ "name": "conv1d_relu_direct", "provenance": { "source": "ONNX Runtime com.microsoft.FusedConv (CPUExecutionProvider)", - "notes": "FusedConv has the same N-dimensional convolution schema as Conv. This compact rank-3 NCW case is accepted by ORT and evaluates Relu(Conv1D(X,W)) on the direct 1-D fallback." + "notes": "A compact rank-3 NCW case accepted by ORT evaluates `Relu(Conv1D(X, W))` on the direct one-dimensional path." }, "attrs": { "activation": "Relu" }, "inputs": { @@ -1071,7 +1065,7 @@ "name": "conv3d_relu", "provenance": { "source": "com.microsoft FusedConv contract and ONNX Conv volumetric semantics", - "notes": "FusedConv is defined over N-dimensional convolution. The generic direct kernel already emits a 3D loop nest for ai.onnx.Conv; this is the same nest with the fused epilogue on top. The trusted reference evaluates it as Relu(Conv3D(X,W))." + "notes": "A volumetric case evaluates `Relu(Conv3D(X, W))` through the generic three-dimensional convolution loop and fused activation epilogue." }, "attrs": { "activation": "Relu", "strides": [1, 1, 1], "dilations": [2, 1, 1] }, "inputs": { @@ -1122,7 +1116,7 @@ { "name": "conv3d_residual_relu", "provenance": { - "notes": "Volumetric residual: Y = Relu(Conv3D(X,W) + Z). Z is Y-shaped, which is what let the rank-4 shape check on the residual become a plain sameShape." + "notes": "A volumetric residual computes `Y = Relu(Conv3D(X, W) + Z)` with `Z` exactly matching the output shape." }, "attrs": { "activation": "Relu", "strides": [1, 1, 1], "dilations": [1, 1, 1] }, "inputs": { @@ -1149,7 +1143,7 @@ { "name": "conv3d_grouped_no_activation", "provenance": { - "notes": "Grouped volumetric convolution with no activation, so the new per-group channel derives are exercised at rank 5 and the epilogue renders to the plain store." + "notes": "A grouped rank-5 volumetric convolution exercises per-group channel indexing and the plain no-activation output store." }, "attrs": { "group": 2, "strides": [1, 1, 1], "dilations": [1, 1, 1] }, "inputs": { @@ -1204,7 +1198,7 @@ "name": "hardswish_conv1d_tiled_k3_s1_p1_bias_c16m128_w1024", "provenance": { "source": "onnxruntime/contrib_ops/cpu/fused_activation.cc", - "notes": "Large NCW convolution with bias and provider-backed HardSwish on the register-tiled implicit-GEMM path." + "notes": "A large NCW convolution with bias and HardSwish exercises register-tiled implicit multiplication." }, "attrs": { "activation": "HardSwish", "strides": [1], "pads": [1, 1] }, "inputs": { @@ -1230,7 +1224,7 @@ "name": "hardswish_conv1d_tiled_k3_s2_p1_c16m128_w2047", "provenance": { "source": "onnxruntime/contrib_ops/cpu/fused_activation.cc", - "notes": "Strided NCW convolution over an odd input width with provider-backed HardSwish and no bias; covers the unbiased register-tiled path." + "notes": "A strided NCW convolution over an odd input width exercises unbiased register-tiled multiplication with HardSwish." }, "attrs": { "activation": "HardSwish", "strides": [2], "pads": [1, 1] }, "inputs": { @@ -1277,7 +1271,7 @@ { "name": "relu_2x2_im2col_sgmat_bias_c8m32", "provenance": { - "notes": "Biased twin of relu_2x2_im2col_sgmat_z_c8m32 without the residual: a non-1x1 kernel on the exact im2col alignment (kernelRows=32, outputPixels=64) is the only way the biased exact subgroup-matrix GEMM outranks the 1x1 shortcut." + "notes": "A biased 2x2 convolution with `kernelRows = 32` and 64 output pixels exercises the exact im2col subgroup-matrix GEMM without a residual input." }, "attrs": { "activation": "Relu", "strides": [1, 1] }, "tolerance": 0.002, @@ -1356,7 +1350,7 @@ { "name": "group2_3x3_direct_bias_inchan4_4x4", "provenance": { - "notes": "Grouped twin of group2_3x3_direct_z_inchan4_4x4 with a bias and no residual: pins the biased direct unrolled kernel, unreachable while every biased fixture is dense-group." + "notes": "A group-2 3x3 convolution with bias and no residual exercises the biased direct unrolled kernel." }, "attrs": { "group": 2, "activation": "Relu", "strides": [1, 1], "pads": [1, 1, 1, 1] }, "inputs": { @@ -1412,7 +1406,7 @@ "name": "same_lower_stride2_autopad", "provenance": { "source": "ONNX Runtime com.microsoft.FusedConv CPUExecutionProvider", - "notes": "ONNX auto_pad SAME_LOWER puts the odd padding element at the START of the axis, so unlike its SAME_UPPER twin this case has a non-zero leading pad and fails if the kernel is handed the explicit pad attributes instead of the derived ones." + "notes": "ONNX `SAME_LOWER` places an odd padding element at the start of the axis. The nonzero leading pad must be derived from `auto_pad` and strides rather than from explicit pad attributes." }, "attrs": { "auto_pad": "SAME_LOWER", "activation": "Relu", "strides": [2, 2] }, "inputs": { @@ -1428,8 +1422,8 @@ { "name": "grouped_k5_relu_w4_group4", "provenance": { - "source": "authored for route coverage", - "notes": "Grouped 5x5 with a fused Relu on the wide-output kernel FusedConv had no grouped route to reach at all; every grouped shape went to direct_unrolled." + "source": "synthetic", + "notes": "A group-4 5x5 convolution with fused ReLU exercises the four-wide grouped large-kernel route." }, "attrs": { "activation": "Relu", "group": 4, "strides": [1, 1], "pads": [2, 2, 2, 2] }, "tolerance": 0.0002, @@ -1443,8 +1437,8 @@ { "name": "grouped_k5_relu_w4_group4_odd_width_tail", "provenance": { - "source": "authored for route coverage", - "notes": "The same grouped shape with a width that is not a multiple of four, covering the odd-width tail arm with the activation applied." + "source": "synthetic", + "notes": "A group-4, 5x5 convolution with output width not divisible by four exercises the odd-width tail with fused activation." }, "attrs": { "activation": "Relu", "group": 4, "strides": [1, 1], "pads": [2, 2, 2, 2] }, "tolerance": 0.0002, @@ -1458,7 +1452,7 @@ { "name": "grouped_k3_hardswish_depthwise", "provenance": { - "source": "authored for route coverage", + "source": "synthetic", "notes": "Depthwise 3x3 with a fused HardSwish, exercising the non-Relu branch of the activation partial on the grouped kernel." }, "attrs": { "activation": "HardSwish", "group": 32, "strides": [1, 1], "pads": [1, 1, 1, 1] }, @@ -1469,6 +1463,2212 @@ "w": { "dtype": "float32", "shape": [32, 1, 3, 3] } }, "outputs": { "y": { "dtype": "float32", "shape": [1, 32, 16, 20] } } + }, + { + "name": "grouped_dilated_lanes_relu_k9_d4_g2_16x40", + "provenance": { + "notes": "Dilated-lane grouped route with the fused activation applied per strided output column." + }, + "attrs": { "activation": "Relu", "group": 2, "strides": [1, 1], "dilations": [4, 4], "pads": [16, 16, 16, 16] }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 8, 16, 40], + "data": { "kind": "fillFloat32", "scale": 0.25, "sinStep": 0.037, "cosStep": 0.013 } + }, + "w": { + "dtype": "float32", + "shape": [8, 4, 9, 9], + "data": { "kind": "fillFloat32", "scale": 0.2, "sinStep": 0.017, "cosStep": 0.029 } + } + }, + "outputs": { "y": { "dtype": "float32", "shape": [1, 8, 16, 40], "tolerance": 0.0001, "relTolerance": 0.0001 } } + }, + { + "name": "implicit_sgmat_identity_tails", + "provenance": { + "notes": "Direct-gather boundary lock: K27 pads to32, M tail where nonmultiple, N4097 ends in a one-column output tile; optional bias and residual precede activation in f32 before the single output cast. Nonzero residual/bias prevents a missing epilogue from matching. Uses the narrowed default spatial floor, without forcing tunables." + }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 3, 19, 243], + "data": { "kind": "fillFloat32", "sinStep": 0.013, "cosStep": 0.027, "scale": 0.2, "offset": 0.0 } + }, + "w": { + "dtype": "float32", + "shape": [33, 3, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.031, "cosStep": 0.017, "scale": 0.2, "offset": 0.0 } + } + }, + "outputs": { + "y": { "dtype": "float32", "shape": [1, 33, 17, 241], "tolerance": 0.0001, "relTolerance": 0.00002 } + } + }, + { + "name": "implicit_sgmat_relu_bias_direct_tail", + "provenance": { + "notes": "Direct-gather boundary lock: K27 pads to32, M tail where nonmultiple, N4097 ends in a one-column output tile; optional bias and residual precede activation in f32 before the single output cast. Nonzero residual/bias prevents a missing epilogue from matching. Uses the narrowed default spatial floor, without forcing tunables." + }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 3, 19, 243], + "data": { "kind": "fillFloat32", "sinStep": 0.013, "cosStep": 0.027, "scale": 0.2, "offset": 0.0 } + }, + "w": { + "dtype": "float32", + "shape": [64, 3, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.031, "cosStep": 0.017, "scale": 0.2, "offset": 0.0 } + }, + "bias": { + "dtype": "float32", + "shape": [64], + "data": { "kind": "fillFloat32", "sinStep": 0.37, "cosStep": 0.13, "scale": 0.05, "offset": 0.03 } + } + }, + "outputs": { + "y": { "dtype": "float32", "shape": [1, 64, 17, 241], "tolerance": 0.0001, "relTolerance": 0.00002 } + }, + "attrs": { "activation": "Relu" } + }, + { + "name": "implicit_sgmat_tanh_residual_tails", + "provenance": { + "notes": "Direct-gather boundary lock: K27 pads to32, M tail where nonmultiple, N4097 ends in a one-column output tile; optional bias and residual precede activation in f32 before the single output cast. Nonzero residual/bias prevents a missing epilogue from matching. Uses the narrowed default spatial floor, without forcing tunables." + }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 3, 19, 243], + "data": { "kind": "fillFloat32", "sinStep": 0.013, "cosStep": 0.027, "scale": 0.2, "offset": 0.0 } + }, + "w": { + "dtype": "float32", + "shape": [33, 3, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.031, "cosStep": 0.017, "scale": 0.2, "offset": 0.0 } + }, + "zResidual": { + "dtype": "float32", + "shape": [1, 33, 17, 241], + "data": { "kind": "fillFloat32", "sinStep": 0.023, "cosStep": 0.041, "scale": 0.08, "offset": 0.04 } + } + }, + "outputs": { + "y": { "dtype": "float32", "shape": [1, 33, 17, 241], "tolerance": 0.0001, "relTolerance": 0.00002 } + }, + "attrs": { "activation": "Tanh" } + }, + { + "name": "implicit_sgmat_leaky_bias_residual_batch_tails", + "provenance": { + "notes": "Direct-gather boundary lock: K27 pads to32, M tail where nonmultiple, N4097 ends in a one-column output tile; optional bias and residual precede activation in f32 before the single output cast. Nonzero residual/bias prevents a missing epilogue from matching. Uses the narrowed default spatial floor, without forcing tunables." + }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [2, 3, 19, 243], + "data": { "kind": "fillFloat32", "sinStep": 0.013, "cosStep": 0.027, "scale": 0.2, "offset": 0.0 } + }, + "w": { + "dtype": "float32", + "shape": [65, 3, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.031, "cosStep": 0.017, "scale": 0.2, "offset": 0.0 } + }, + "bias": { + "dtype": "float32", + "shape": [65], + "data": { "kind": "fillFloat32", "sinStep": 0.37, "cosStep": 0.13, "scale": 0.05, "offset": 0.03 } + }, + "zResidual": { + "dtype": "float32", + "shape": [2, 65, 17, 241], + "data": { "kind": "fillFloat32", "sinStep": 0.023, "cosStep": 0.041, "scale": 0.08, "offset": 0.04 } + } + }, + "outputs": { + "y": { "dtype": "float32", "shape": [2, 65, 17, 241], "tolerance": 0.0001, "relTolerance": 0.00002 } + }, + "attrs": { "activation": "LeakyRelu", "activation_params": [0.25] } + }, + { + "name": "implicit_sgmat_f16_relu_tails", + "provenance": { + "notes": "Direct-gather boundary lock: K27 pads to32, M tail where nonmultiple, N4097 ends in a one-column output tile; optional bias and residual precede activation in f32 before the single output cast. Nonzero residual/bias prevents a missing epilogue from matching. Uses the narrowed default spatial floor, without forcing tunables." + }, + "inputs": { + "x": { + "dtype": "float16", + "shape": [1, 3, 19, 243], + "data": { "kind": "fillFloat32", "sinStep": 0.013, "cosStep": 0.027, "scale": 0.2, "offset": 0.0 } + }, + "w": { + "dtype": "float16", + "shape": [33, 3, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.031, "cosStep": 0.017, "scale": 0.2, "offset": 0.0 } + } + }, + "outputs": { "y": { "dtype": "float16", "shape": [1, 33, 17, 241], "tolerance": 0.001, "relTolerance": 0.001 } }, + "attrs": { "activation": "Relu" } + }, + { + "name": "implicit_sgmat_relu_bias_direct_tail_f16", + "provenance": { + "notes": "Float16 bias/residual counterpart for the dtype-specific implicit subgroup-matrix config route. M33 stays within the two-tile f16 gate and exercises guarded output storage." + }, + "inputs": { + "x": { + "dtype": "float16", + "shape": [1, 3, 19, 243], + "data": { "kind": "fillFloat32", "sinStep": 0.013, "cosStep": 0.027, "scale": 0.2, "offset": 0.0 } + }, + "w": { + "dtype": "float16", + "shape": [33, 3, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.031, "cosStep": 0.017, "scale": 0.2, "offset": 0.0 } + }, + "bias": { + "dtype": "float16", + "shape": [33], + "data": { "kind": "fillFloat32", "sinStep": 0.37, "cosStep": 0.13, "scale": 0.05, "offset": 0.03 } + } + }, + "outputs": { "y": { "dtype": "float16", "shape": [1, 33, 17, 241], "tolerance": 0.001, "relTolerance": 0.001 } }, + "attrs": { "activation": "Relu" } + }, + { + "name": "implicit_sgmat_tanh_residual_tails_f16", + "provenance": { + "notes": "Float16 bias/residual counterpart for the dtype-specific implicit subgroup-matrix config route. M33 stays within the two-tile f16 gate and exercises guarded output storage." + }, + "inputs": { + "x": { + "dtype": "float16", + "shape": [1, 3, 19, 243], + "data": { "kind": "fillFloat32", "sinStep": 0.013, "cosStep": 0.027, "scale": 0.2, "offset": 0.0 } + }, + "w": { + "dtype": "float16", + "shape": [33, 3, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.031, "cosStep": 0.017, "scale": 0.2, "offset": 0.0 } + }, + "zResidual": { + "dtype": "float16", + "shape": [1, 33, 17, 241], + "data": { "kind": "fillFloat32", "sinStep": 0.023, "cosStep": 0.041, "scale": 0.08, "offset": 0.04 } + } + }, + "outputs": { "y": { "dtype": "float16", "shape": [1, 33, 17, 241], "tolerance": 0.001, "relTolerance": 0.001 } }, + "attrs": { "activation": "Tanh" } + }, + { + "name": "implicit_sgmat_leaky_bias_residual_batch_tails_f16", + "provenance": { + "notes": "Float16 bias/residual counterpart for the dtype-specific implicit subgroup-matrix config route. M33 stays within the two-tile f16 gate and exercises guarded output storage." + }, + "inputs": { + "x": { + "dtype": "float16", + "shape": [2, 3, 19, 243], + "data": { "kind": "fillFloat32", "sinStep": 0.013, "cosStep": 0.027, "scale": 0.2, "offset": 0.0 } + }, + "w": { + "dtype": "float16", + "shape": [33, 3, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.031, "cosStep": 0.017, "scale": 0.2, "offset": 0.0 } + }, + "bias": { + "dtype": "float16", + "shape": [33], + "data": { "kind": "fillFloat32", "sinStep": 0.37, "cosStep": 0.13, "scale": 0.05, "offset": 0.03 } + }, + "zResidual": { + "dtype": "float16", + "shape": [2, 33, 17, 241], + "data": { "kind": "fillFloat32", "sinStep": 0.023, "cosStep": 0.041, "scale": 0.08, "offset": 0.04 } + } + }, + "outputs": { "y": { "dtype": "float16", "shape": [2, 33, 17, 241], "tolerance": 0.001, "relTolerance": 0.001 } }, + "attrs": { "activation": "LeakyRelu", "activation_params": [0.25] } + }, + { + "name": "implicit_buffer_fallback_compact_float32", + "attrs": { "activation": "Relu" }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 16, 5, 45], + "data": { "kind": "fillFloat32", "sinStep": 0.013, "cosStep": 0.021, "scale": 0.05, "offset": 0.2 } + }, + "w": { + "dtype": "float32", + "shape": [96, 16, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.009, "cosStep": 0.029, "scale": 0.07, "offset": 0.3 } + } + }, + "outputs": { "y": { "dtype": "float32", "shape": [1, 96, 3, 43], "tolerance": 0.0001, "relTolerance": 0.00002 } }, + "tunables": { "IMPLICIT_SGMAT_MAX_M_TILES": 4, "IMPLICIT_SGMAT_MIN_OUTPUT_PIXELS": 128 }, + "provenance": { + "notes": "Compact multi-tile implicit gather with K/N tails. Tunables exercise the kernel without allocating the large memory-boundary workload; selector unit tests separately pin the actual device-limit boundary." + } + }, + { + "name": "implicit_buffer_fallback_compact_float16", + "attrs": { "activation": "Relu" }, + "inputs": { + "x": { + "dtype": "float16", + "shape": [1, 16, 5, 45], + "data": { "kind": "fillFloat32", "sinStep": 0.013, "cosStep": 0.021, "scale": 0.05, "offset": 0.2 } + }, + "w": { + "dtype": "float16", + "shape": [96, 16, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.009, "cosStep": 0.029, "scale": 0.07, "offset": 0.3 } + } + }, + "outputs": { "y": { "dtype": "float16", "shape": [1, 96, 3, 43], "tolerance": 0.001, "relTolerance": 0.001 } }, + "tunables": { "IMPLICIT_SGMAT_MAX_M_TILES": 4, "IMPLICIT_SGMAT_MIN_OUTPUT_PIXELS": 128 }, + "provenance": { + "notes": "Compact multi-tile implicit gather with K/N tails. Tunables exercise the kernel without allocating the large memory-boundary workload; selector unit tests separately pin the actual device-limit boundary." + } + }, + { + "name": "implicit_splitk_preferred_grid16_k144", + "attrs": { "activation": "Relu" }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 16, 34, 34], + "data": { "kind": "fillFloat32", "sinStep": 0.013, "cosStep": 0.021, "scale": 0.05, "offset": 0.02 } + }, + "w": { + "dtype": "float32", + "shape": [64, 16, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.019, "cosStep": 0.037, "scale": 0.05, "offset": 0.01 } + } + }, + "outputs": { "y": { "dtype": "float32", "shape": [1, 64, 32, 32], "tolerance": 0.0001, "relTolerance": 0.0001 } }, + "provenance": { + "notes": "Selects the preferred implicit split-K route at its output-grid boundary; nonuniform data exercises reduction and fused activation." + } + }, + { + "name": "implicit_splitk_preferred_bias_m_tail_grid32", + "attrs": { "activation": "LeakyRelu", "activation_params": [0.125] }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 64, 34, 34], + "data": { "kind": "fillFloat32", "sinStep": 0.013, "cosStep": 0.021, "scale": 0.05, "offset": 0.02 } + }, + "w": { + "dtype": "float32", + "shape": [65, 64, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.019, "cosStep": 0.037, "scale": 0.05, "offset": 0.01 } + }, + "bias": { + "dtype": "float32", + "shape": [65], + "data": { "kind": "fillFloat32", "sinStep": 0.13, "scale": 0.1, "offset": -0.2 } + } + }, + "outputs": { "y": { "dtype": "float32", "shape": [1, 65, 32, 32], "tolerance": 0.0001, "relTolerance": 0.0001 } }, + "provenance": { + "notes": "Selects the preferred implicit split-K route at its output-grid boundary; nonuniform data exercises reduction and fused activation." + } + }, + { + "name": "direct_matrix_inputs_m32_c32_h8_w8_mode0", + "provenance": { + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 32, 8, 8], + "data": { + "kind": "fillFloat32", + "sinStep": 0.013, + "cosStep": 0.022099999999999998, + "scale": 0.2, + "offset": 0.0 + } + }, + "w": { + "dtype": "float32", + "shape": [32, 32, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.031, "cosStep": 0.0527, "scale": 0.2, "offset": 0.0 } + } + }, + "attrs": { "pads": [1, 1, 1, 1] }, + "outputs": { "y": { "dtype": "float32", "shape": [1, 32, 8, 8], "tolerance": 0.0001, "relTolerance": 0.00002 } } + }, + { + "name": "direct_matrix_inputs_m32_c32_h8_w8_mode1", + "provenance": { + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. 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