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Datasets:
SAIFIINDUSTRIES
/
verilog_data-2
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Files
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xet
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main
verilog_data-2
/
ConstStrings_GoWinSDR
/
FPGA
/
Submodule
/
ETH_TransRecv
/
src
58.3 kB
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History:
1 commit
SAIFIINDUSTRIES
Add Batch 5 with 10 repos
387c3d6
verified
25 days ago
gowin_ddr
Add Batch 5 with 10 repos
25 days ago
gowin_pll
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25 days ago
arp_responder.v
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8.12 kB
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25 days ago
crc.v
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3.63 kB
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25 days ago
eth_transceiver.v
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19.2 kB
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25 days ago
pll_init.v
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15.8 kB
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25 days ago
timeconstrain.sdc
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467 Bytes
Add Batch 5 with 10 repos
25 days ago
top.v
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1.84 kB
Add Batch 5 with 10 repos
25 days ago
