Hugging Face
Models
Datasets
Spaces
Buckets
new
Docs
Enterprise
Pricing
Website
Tasks
HuggingChat
Collections
Languages
Organizations
Community
Blog
Posts
Daily Papers
Hardware
Learn
Discord
Forum
GitHub
Solutions
Team & Enterprise
Hugging Face PRO
Enterprise Support
Inference Providers
Inference Endpoints
Storage Buckets
Log In
Sign Up
Datasets:
SAIFIINDUSTRIES
/
verilog_data-2
Like
0
Dataset card
Files
Files and versions
xet
Community
main
verilog_data-2
/
ConstStrings_GoWinSDR
/
FPGA
/
Submodule
/
DDR_FIFO
/
src
1.64 MB
Ctrl+K
Ctrl+K
1 contributor
History:
1 commit
SAIFIINDUSTRIES
Add Batch 5 with 10 repos
387c3d6
verified
25 days ago
ddr3_memory_interface
Add Batch 5 with 10 repos
25 days ago
fifo_top
Add Batch 5 with 10 repos
25 days ago
gowin_ddr
Add Batch 5 with 10 repos
25 days ago
gowin_pll
Add Batch 5 with 10 repos
25 days ago
gowin_pll_eth
Add Batch 5 with 10 repos
25 days ago
crc.v
Safe
3.63 kB
Add Batch 5 with 10 repos
25 days ago
ddr_fifo_test.v
Safe
8.44 kB
Add Batch 5 with 10 repos
25 days ago
eth_transceiver.v
Safe
19.2 kB
Add Batch 5 with 10 repos
25 days ago
fifo_ddr.v
Safe
21.2 kB
Add Batch 5 with 10 repos
25 days ago
gw60.sdc
Safe
745 Bytes
Add Batch 5 with 10 repos
25 days ago
pll_init.v
Safe
15.8 kB
Add Batch 5 with 10 repos
25 days ago
top.v
Safe
10.1 kB
Add Batch 5 with 10 repos
25 days ago
top_test.v
Safe
6.33 kB
Add Batch 5 with 10 repos
25 days ago
