File size: 3,851 Bytes
d1be154 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 | #include <ot/verilog/verilog.hpp>
namespace ot::vlog {
// Operator <<
std::ostream& operator << (std::ostream& os, const Gate& inst) {
os << inst.cell << ' ' << inst.name << " ( ";
size_t i {0};
for(const auto& [pin, net] : inst.cellpin2net) {
if(i++ != 0) {
os << ", ";
}
os << '.' << pin << '(' << net << ')';
}
os << " );";
return os;
}
// ------------------------------------------------------------------------------------------------
// Operator: <<
std::ostream& operator << (std::ostream& os, const Module& m) {
os << "module " << m.name << " (\n";
for(size_t i=0; i<m.ports.size(); ++i) {
os << m.ports[i];
if(i != m.ports.size() - 1) {
os << ",\n";
}
}
os << ");\n\n";
os << "// Start PIs\n";
for(const auto& pi : m.inputs) {
os << "input " << pi << ";\n";
}
os << '\n';
os << "// Start POs\n";
for(const auto& po : m.outputs) {
os << "output " << po << ";\n";
}
os << '\n';
os << "// Start wires\n";
for(const auto& wire : m.wires) {
os << "wire " << wire << ";\n";
}
os << '\n';
os << "// Start cells\n";
for(const auto& gate : m.gates) {
os << gate << '\n';
}
os << '\n';
os << "endmodule";
return os;
}
// ------------------------------------------------------------------------------------------------
// Function: info
std::string Module::info() const {
return "verilog module \""s + name + "\" " +
"[gates:" + std::to_string(gates.size()) + "]";
}
// Procedure: read_verilog
Module read_verilog(const std::filesystem::path& path) {
Module module;
static std::string_view delimiters = "(),:;/#[]{}*\"\\";
static std::string_view exceptions = "().;";
auto tokens = tokenize(path, delimiters, exceptions);
//for(const auto& token : tokens) {
// std::cout << token << std::endl;
//}
// Set up the iterator
auto itr = tokens.begin();
auto end = tokens.end();
// Read the module name
if(itr = std::find(itr, end, "module"); itr == end) {
OT_LOGF("can't find keyword 'module'");
}
else {
if(++itr == end) {
OT_LOGF("syntax error in module name");
}
module.name = std::move(*itr);
}
while(++itr != end && *itr != ";") {
if(*itr != "(" && *itr != ")") {
module.ports.push_back(std::move(*itr));
}
}
// Parse the content.
while(++itr != end) {
if(*itr == "endmodule") {
break;
}
else if(*itr == "input") {
while(++itr != end && *itr != ";") {
module.inputs.push_back(std::move(*itr));
}
}
else if(*itr == "output") {
while(++itr != end && *itr != ";") {
module.outputs.push_back(std::move(*itr));
}
}
else if(*itr == "wire") {
while(++itr != end && *itr != ";") {
module.wires.push_back(std::move(*itr));
}
}
else {
Gate inst;
inst.cell = std::move(*itr);
if(++itr == end) {
OT_LOGF("syntax error in cell ", inst.cell, ")");
}
inst.name = std::move(*itr);
// Read the mapping
std::string cellpin;
std::string net;
itr = on_next_parentheses(itr, end, [&] (auto& str) mutable {
if(str == ")" || str == "(") {
return;
}
else if(str[0] == '.') {
cellpin = str.substr(1);
}
else {
net = str;
inst.cellpin2net[cellpin] = net;
inst.net2cellpin[net] = cellpin;
}
});
if(itr == end) {
OT_LOGF("syntax error in gate pin-net mapping");
}
if(*(++itr) != ";") {
OT_LOGF("missing ; in instance declaration");
}
module.gates.push_back(std::move(inst));
}
}
return module;
}
}; // end of namespace ot. -----------------------------------------------------------------------
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