File size: 5,394 Bytes
d1be154 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 | #include <ot/timer/arc.hpp>
#include <ot/timer/pin.hpp>
#include <ot/timer/net.hpp>
namespace ot {
// Constructor
Arc::Arc(Pin& from, Pin& to, Net& net) :
_from {from},
_to {to},
_handle {&net} {
}
// Constructor
Arc::Arc(Pin& from, Pin& to, TimingView t) :
_from {from},
_to {to},
_handle {t} {
}
// Function: name
std::string Arc::name() const {
return _from._name + "->" + _to._name;
}
// Function: is_self_loop
bool Arc::is_self_loop() const {
return &_from == &_to;
}
// Function: is_loop_breaker
bool Arc::is_loop_breaker() const {
return _has_state(LOOP_BREAKER);
}
// Function: is_net_arc
bool Arc::is_net_arc() const {
return std::get_if<Net*>(&_handle) != nullptr;
}
// Function: is_cell_arc
bool Arc::is_cell_arc() const {
return std::get_if<TimingView>(&_handle) != nullptr;
}
// Function: is_tseg
bool Arc::is_tseg() const {
if(auto ptr = std::get_if<TimingView>(&_handle); ptr) {
return (*ptr)[MIN]->is_constraint();
}
else return false;
}
// Function: is_pseg
bool Arc::is_pseg() const {
if(auto ptr = std::get_if<TimingView>(&_handle); ptr) {
return !(*ptr)[MIN]->is_constraint();
}
else return false;
}
// Function: timing_view
TimingView Arc::timing_view() const {
if(auto tv = std::get_if<TimingView>(&_handle); tv) {
return *tv;
}
else return {nullptr, nullptr};
}
// Procedure: _remap_timing
void Arc::_remap_timing(Split el, const Timing& timing) {
(std::get<TimingView>(_handle))[el] = &timing;
}
// Procedure: _reset_delay
void Arc::_reset_delay() {
FOR_EACH_EL_RF_RF(el, frf, trf) {
_delay[el][frf][trf].reset();
_ipower[el][frf][trf].reset();
}
}
// Procedure: _fprop_slew
void Arc::_fprop_slew() {
if(_has_state(LOOP_BREAKER)) {
return;
}
std::visit(Functors{
// Case 1: Net arc
[this] (Net* net) {
FOR_EACH_EL_RF(el, rf) {
if(_from._slew[el][rf]) {
if(auto so = net->_slew(el, rf, *(_from._slew[el][rf]), _to); so) {
_to._relax_slew(this, el, rf, el, rf, *so);
}
}
}
},
// Case 2: Cell arc
[this] (TimingView tv) {
FOR_EACH_EL_RF_RF_IF(el, frf, trf, (tv[el] && _from._slew[el][frf])) {
auto lc = (_to._net) ? _to._net->_load(el, trf) : 0.0f;
if(auto so = tv[el]->slew(frf, trf, *_from._slew[el][frf], lc); so) {
_to._relax_slew(this, el, frf, el, trf, *so);
}
}
}
}, _handle);
}
// Procedure: _fprop_delay
void Arc::_fprop_delay() {
if(_has_state(LOOP_BREAKER)) {
return;
}
std::visit(Functors{
// Case 1: Net arc
[this] (Net* net) {
FOR_EACH_EL_RF(el, rf) {
_delay[el][rf][rf] = net->_delay(el, rf, _to);
}
},
// Case 2: Cell arc
[this] (TimingView tv) {
FOR_EACH_EL_RF_RF_IF(el, frf, trf, (tv[el] && _from._slew[el][frf])) {
auto lc = (_to._net) ? _to._net->_load(el, trf) : 0.0f;
auto si = *_from._slew[el][frf];
auto delay = tv[el]->delay(frf, trf, si, lc);
_delay[el][frf][trf] = delay;
auto ipower = tv[el]->internal_power.power(frf, trf, si, lc);
_ipower[el][frf][trf] = ipower;
//std::cout << " name:" << _from._name << " delay:" << *delay << " slew:" << si << " lc:" << lc << " ipower:" << *ipower << "\n";
}
}
}, _handle);
}
// Procedure: _fprop_at
void Arc::_fprop_at() {
if(_has_state(LOOP_BREAKER)) {
return;
}
FOR_EACH_EL_RF_RF_IF(el, frf, trf, _from._at[el][frf] && _delay[el][frf][trf]) {
_to._relax_at(this, el, frf, el, trf, *_delay[el][frf][trf] + *_from._at[el][frf]);
}
}
// Procedure: _bprop_rat
void Arc::_bprop_rat() {
if(_has_state(LOOP_BREAKER)) {
return;
}
std::visit(Functors{
// Case 1: Net arc
[this] (Net* net) {
FOR_EACH_EL_RF_IF(el, rf, _to._rat[el][rf] && _delay[el][rf][rf]) {
_from._relax_rat(this, el, rf, el, rf, *_to._rat[el][rf] - *_delay[el][rf][rf]);
}
},
// Case 2: Cell arc
[this] (TimingView tv) {
FOR_EACH_EL_RF_RF_IF(el, frf, trf, tv[el]) {
// propagation arc
if(!tv[el]->is_constraint()) {
if(!_to._rat[el][trf] || !_delay[el][frf][trf]) {
continue;
}
_from._relax_rat(this, el, frf, el, trf, *_to._rat[el][trf] - *_delay[el][frf][trf]);
}
// constraint arc
else {
if(!tv[el]->is_transition_defined(frf, trf)) {
continue;
}
if(el == MIN) {
auto at = _from._at[MAX][frf];
auto slack = _to.slack(MIN, trf);
if(at && slack) {
_from._relax_rat(this, MAX, frf, MIN, trf, *at + *slack);
}
}
else {
auto at = _from._at[MIN][frf];
auto slack = _to.slack(MAX, trf);
if(at && slack) {
_from._relax_rat(this, MIN, frf, MAX, trf, *at - *slack);
}
}
}
}
}
}, _handle);
}
// Procedure: _remove_state
void Arc::_remove_state(int s) {
if(s == 0) _state = 0;
else {
_state &= ~s;
}
}
// Procedure: _insert_state
void Arc::_insert_state(int s) {
_state |= s;
}
// Function: _has_state
bool Arc::_has_state(int s) const {
return _state & s;
}
}; // end of namespace ot. -----------------------------------------------------------------------
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