VERSION 5.8 ;
NAMESCASESENSITIVE ON ;
DIVIDERCHAR "|" ;
BUSBITCHARS "<>" ;
DESIGN counter ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 100 200 ) ( 400 600 ) ;

PROPERTYDEFINITIONS
    DESIGN ER_routing_mode STRING "trial_opt" ;
    NET alpha_value REAL 1.0 ;
    COMPONENT RE REAL ;
    COMPONENT IN INTEGER 2 ;
    COMPONENTPIN PP INTEGER ;
    ROW X STRING ;
    DESIGN FE_CORE_BOX_LL_X REAL 0.420 ;
    DESIGN FE_CORE_BOX_UR_X REAL 67.032 ;
    DESIGN FE_CORE_BOX_LL_Y REAL 0.448 ;
    DESIGN FE_CORE_BOX_UR_Y REAL 66.208 ;
  DESIGN strprop STRING "aString" ;
  DESIGN intprop INTEGER 1 ;
  DESIGN realprop REAL 1.1 ;
  DESIGN intrangeprop INTEGER RANGE 1 100 25 ;
  DESIGN realrangeprop REAL RANGE 1.1 100.1 25.25 ;
  REGION strprop STRING ;
  REGION intprop INTEGER ;
  REGION realprop REAL ;
  REGION intrangeprop INTEGER RANGE 1 100 ;
  REGION realrangeprop REAL RANGE 1.1 100.1 ;
  GROUP strprop STRING ;
  GROUP intprop INTEGER ;
  GROUP realprop REAL ;
  GROUP intrangeprop INTEGER RANGE 1 100 ;
  GROUP realrangeprop REAL RANGE 1.1 100.1 ;
  COMPONENT strprop STRING ;
  COMPONENT intprop INTEGER ;
  COMPONENT realprop REAL ;
  COMPONENT intrangeprop INTEGER RANGE 1 100 ;
  COMPONENT realrangeprop REAL RANGE 1.1 100.1 ;
  NET strprop STRING ;
  NET intprop INTEGER ;
  NET realprop REAL ;
  NET intrangeprop INTEGER RANGE 1 100 ;
  NET realrangeprop REAL RANGE 1.1 100.1 ;
  SPECIALNET strprop STRING ;
  SPECIALNET intprop INTEGER ;
  SPECIALNET realprop REAL ;
  SPECIALNET intrangeprop INTEGER RANGE 1 100 ;
  SPECIALNET realrangeprop REAL RANGE 1.1 100.1 ;
  ROW strprop STRING ;
  ROW intprop INTEGER ;
  ROW realprop REAL ;
  ROW intrangeprop INTEGER RANGE 1 100 ;
  ROW realrangeprop REAL RANGE 1.1 100.1 ;
  COMPONENTPIN strprop STRING ;
  COMPONENTPIN intprop INTEGER ;
  COMPONENTPIN realprop REAL ;
  COMPONENTPIN intrangeprop INTEGER RANGE 1 100 ;
  COMPONENTPIN realrangeprop REAL RANGE 1.1 100.1 ;
  NONDEFAULTRULE strprop STRING ;
  NONDEFAULTRULE intprop INTEGER ;
  NONDEFAULTRULE realprop REAL ;
  NONDEFAULTRULE intrangeprop INTEGER RANGE 1 100 ;
  NONDEFAULTRULE realrangeprop REAL RANGE 1.1 100.1 ;
END PROPERTYDEFINITIONS

ROW CORE_ROW_0 CoreSite 840 896 FS DO 793 BY 1 STEP 168 0 + PROPERTY X "DOG" ;

TRACKS Y 52 DO 857 STEP 104 ;
TRACKS Y 52 DO 857 STEP 104 ;

GCELLGRID X 0 DO 100 STEP 600 ;
GCELLGRID Y 10 DO 120 STEP 400 ;

REGIONS 2 ;
- region1 ( -500 -500 ) ( 300 100 ) ( 500 500 ) ( 1000 1000 )
  + TYPE FENCE
  + PROPERTY strprop "aString" 
  + PROPERTY intprop 1 
  + PROPERTY realprop 1.1 
  + PROPERTY intrangeprop 25
  + PROPERTY realrangeprop 25.25 ;
- region2 ( 4000 0 ) ( 5000 1000 )
  + TYPE GUIDE ;
END REGIONS

COMPONENTS 12 ;
- _d0_ DFFPOSX1 + PROPERTY RE 1.1 IN 2 ;
- _d1_ DFFPOSX1 + SOURCE NETLIST ;
- _d2_ DFFPOSX1 + FIXED ( 1 2 ) N ;
- _d3_ DFFPOSX1 + WEIGHT 10 ;
- _d4_ DFFPOSX1 + REGION region1 ;
- _d5_ DFFPOSX1 ;
- _d6_ DFFPOSX1 ;
- _d7_ DFFPOSX1 ;
- _d8_ DFFPOSX1 ;
- _g0_ NOR2X1 ;
- _g1_ NOR2X1 ;
- _g2_ NOR2X1 ;
END COMPONENTS

GROUPS 1 ;
- group1 _g0_ _d0*
  + REGION region1
  + PROPERTY strprop "aString" 
  + PROPERTY intprop 1 
  + PROPERTY realprop 1.1 
  + PROPERTY intrangeprop 25
  + PROPERTY realrangeprop 25.25 ;
END GROUPS


PINS 12 ;
- inp0 + NET inp0 + DIRECTION INPUT + LAYER metal1 ( 0 0 ) ( 10 20 ) + FIXED ( 50 50 ) N ;
- inp1 + NET inp1 + DIRECTION INPUT ;
- clk + NET clk + DIRECTION INPUT ;
- out[8] + NET out[8] + SPECIAL ;
- out[7] + NET out[7] + SUPPLYSENSITIVITY clk ;
- out[6] + NET out[6] + GROUNDSENSITIVITY inp0 ;
- out[5] + NET out[5] + USE ANALOG ;
- out[4] + NET out[4] + COVER ( 1 2 ) E ;
- out[3] + NET out[3] + DIRECTION OUTPUT ;
- out[2] + NET out[2] + DIRECTION OUTPUT ;
- out[1] + NET out[1] + DIRECTION OUTPUT ;
- out[0] + NET out[0] + DIRECTION OUTPUT ;
- vdd + NET VDD ;
END PINS

PINPROPERTIES 1 ;
- PIN clk + PROPERTY PP 3 ;
- _d0_ CLK + PROPERTY PP 1 ;
END PINPROPERTIES

SPECIALNETS 2 ;
- VDD  ( * vdd ) ( PIN vdd )
  + USE POWER
  + SOURCE TIMING
  + ROUTED metal1 20 + SHAPE RING ( 0 0 ) ( 0 20 )
       NEW metal2 20 + SHAPE STRIPE ( 20 0 ) ( 0 * )
 ;
- VSS  ( * gnd )
  + USE GROUND
  + SOURCE NETLIST
  + FIXEDBUMP
  + WEIGHT 99
  + RECT metal1 ( 0 0 ) ( 10 20 )
 ;
END SPECIALNETS

BLOCKAGES 4 ;
 - LAYER metal1
   + COMPONENT _d0_
   + DESIGNRULEWIDTH 6
     RECT ( 1 2 ) ( 3 4 ) 
     RECT ( 5 6 ) ( 7 8 ) ;
 - LAYER metal2
   + SLOTS
   + SPACING 5
     RECT ( 1 2 ) ( 3 4 ) ;
 - LAYER metal2
   + PUSHDOWN
     RECT ( 5 6 ) ( 7 8 ) ;
 - LAYER metal3
   + FILLS
     POLYGON ( 0 0 ) ( 5 * ) ( * 5 ) ( 3 * ) ( * 2 ) ( 0 * ) ;
 - PLACEMENT
   + COMPONENT _d0_ RECT ( 1 2 ) ( 3 4 ) ;
 - PLACEMENT
   + PARTIAL 12.34
   + PUSHDOWN RECT ( 1 2 ) ( 3 4 ) ;
 - PLACEMENT
   + SOFT
   RECT ( 1 2 ) ( 3 4 ) ;
END BLOCKAGES

FILLS 1 ;
 - LAYER metal1 RECT ( 1 2 ) ( 3 4 ) ;
 - LAYER metal1 + OPC + MASK 2 RECT ( 1 2 ) ( 3 4 ) ;
END FILLS

VIAS 36 ;
- VIA1
 + RECT metal2 ( 1 2 ) ( 3 4 )
 + RECT via2 ( 1 2 ) ( 3 4 )
 + RECT metal3 ( 1 2 ) ( 3 4 ) ;

- VIAGEN12_0
    + PATTERNNAME VIAGEN_12_12.800_7.600_I5
    + RECT metal1 ( -4400 -3800 ) ( 4400 3800 )
    + RECT metal2 ( -4500 -3800 ) ( 4500 3800 )
    + RECT via1 ( -3600 -3800 ) ( -2000 -2200 )
    + RECT via1 ( -3600 2200 ) ( -2000 3800 )
    + RECT via1 ( 2000 -3800 ) ( 3600 -2200 )
    + RECT via1 ( 2000 2200 ) ( 3600 3800 ) ;

- VIAGEN12_2
    + PATTERNNAME VIAGEN_12_5.0000_3.000_1.5600_-0.1600_1.0400_1.0400_D
    + RECT metal1 ( -2500 -1500 ) ( 2500 1500 )
    + RECT metal2 ( -2500 -1500 ) ( 2500 1500 )
    + RECT via1 ( -2360 -960 ) ( -760 640 )
    + RECT via1 ( -1320 -960 ) ( 280 640 )
    + RECT via1 ( 760 -960 ) ( 2360 640 ) ;

- VIAGEN12_3
    + PATTERNNAME VIAGEN12
    + RECT metal1 ( -1600 -1600 ) ( 1600 1600 )
    + RECT metal2 ( -1600 -1600 ) ( 1600 1600 )
    + RECT via1 ( -800 -800 ) ( 800 800 ) ;

- VIAGEN12_4
    + VIARULE M2_M1
    + CUTSIZE 1600 1600
    + LAYERS metal1 via1 metal2
    + CUTSPACING 5600 6100
    + ENCLOSURE 100 100 150 150
    + ROWCOL 5 14
    + PATTERN 2_FFE0_3_FFFF 
    + ORIGIN 10 -10
    + OFFSET 0 0 20 -20 ;

- M2_M1rct_0
  + RECT via1 ( -25 -65 ) ( 25 65 )
  + RECT metal1 ( -35 -95 ) ( 35 95 )
  + RECT metal2 ( -65 -65 ) ( 65 65 ) ;
      
- myvia1
    + RECT metal1 ( 0 0 ) ( 40000 40000 )
    + RECT via1  ( 0 0 ) ( 40000 40000 )
    + RECT metal2 ( 0 0 ) ( 40000 40000 ) ;

END VIAS

NONDEFAULTRULES 1 ;
 - DEFAULT
  + HARDSPACING 
  + LAYER poly
      WIDTH 10.1
      SPACING 2.2
      WIREEXT 1.1
  + LAYER metal1
      WIDTH 10.1
      SPACING 2.2
      WIREEXT 1.1
  + LAYER metal2
      WIDTH 10.1
      SPACING 2.2
  + LAYER metal3
      WIDTH 11.1
      SPACING 3.2
      WIREEXT 3
  + LAYER metal4
      WIDTH 11.1
      SPACING 3.2
      WIREEXT 3
  + LAYER metal5
      WIDTH 11.1
      SPACING 3.2
      WIREEXT 3
  + LAYER metal6
      WIDTH 11.1
      SPACING 3.2
      WIREEXT 3
  + LAYER metal7
      WIDTH 11.1
      SPACING 3.2
      WIREEXT 3
  + LAYER metal8
      WIDTH 11.1
      SPACING 3.2
      WIREEXT 3
  + LAYER metal9
      WIDTH 11.1
      SPACING 3.2
      WIREEXT 3
  + VIA M2_M1_via
  + VIA M3_M2_via
  + VIARULE M2_M1
  + MINCUTS via1 2
  + PROPERTY strprop "aString" 
  + PROPERTY intprop 1 
  + PROPERTY realprop 1.1 
  + PROPERTY intrangeprop 25
  + PROPERTY realrangeprop 25.25 ;
END NONDEFAULTRULES

NETS 24 ;
- _w0_ ( _g0_ Y ) ( _d1_ D ) ( _d0_ D ) ( _d2_ D ) 
      + ROUTED metal3 ( 1 2 ) ( 3 * ) VIA1
        NEW    metal3 ( 4 5 ) ( 6 * ) ;        
- _w1_ ( _d5_ D ) ( _g1_ Y ) ( _d3_ D ) ( _d4_ D ) ;
- _w2_ ( _g2_ Y ) ( _d6_ D ) ( _d8_ D ) ( _d7_ D ) ;
- _xout0 ( _d0_ Q ) + NONDEFAULTRULE DEFAULT + ROUTED  metal2 ( 0 0 ) M2_M1_via E 
           NEW metal2 TAPER ( 0 0 ) ( * 10 ) ;
- _xout1 ( _d1_ Q ) + FIXEDBUMP ;
- _xout2 ( _d2_ Q ) ;
- _xout3 ( _d3_ Q ) ;
- _xout4 ( _d4_ Q ) ;
- _xout5 ( _d5_ Q ) ;
- _xout6 ( _d6_ Q ) ;
- _xout7 ( _d7_ Q ) ;
- _xout8 ( _d8_ Q ) ;
- clk ( PIN clk ) ( _d5_ CLK ) ( _d3_ CLK ) ( _d6_ CLK ) ( _d4_ CLK ) ( _d1_ CLK ) ( _d8_ CLK )
  ( _d0_ CLK ) ( _d2_ CLK ) ( _d7_ CLK ) ;
- inp0 ( _g2_ A ) ( PIN inp0 ) ( _g1_ A ) ( _g0_ A ) ;
- inp1 ( _g2_ B ) ( PIN inp1 ) ( _g0_ B ) ( _g1_ B ) ;
- out[0] ( PIN out[0] ) ( _d0_ Q ) ;
- out[1] ( PIN out[1] ) ( _d1_ Q ) ;
- out[2] ( PIN out[2] ) ( _d2_ Q ) ;
- out[3] ( PIN out[3] ) ( _d3_ Q ) ;
- out[4] ( _d4_ Q ) ( PIN out[4] ) ;
- out[5] ( PIN out[5] ) ( _d5_ Q ) ;
- out[6] ( PIN out[6] ) ( _d6_ Q ) ;
- out[7] ( PIN out[7] ) ( _d7_ Q ) ;
- out[8] ( PIN out[8] ) ( _d8_ Q ) ;
END NETS

SCANCHAINS 2 ;
- chain1
  + PARTITION part1
  + START _d0_ D
  + STOP _d1_ Q
  + FLOATING
  _d2_ ( IN D ) ( OUT Q )
;
- chain2
  + PARTITION part2
  + START PIN inp0
  + STOP PIN out[0]
  + ORDERED
  _d3_ ( IN D ) ( OUT Q )
  _d4_ ( IN D ) ( OUT Q )
;
END SCANCHAINS

END DESIGN