set_early_celllib_fpath simple_Early.lib
set_late_celllib_fpath simple_Late.lib
set_verilog_fpath simple.v
read_sdc simple.sdc

# report the top-4 critical paths
report_timing -num_paths 4

# change the weight of the circuit
read_spef simple.spef

# report the top-4 critical paths
report_timing -num_paths 4

# dump the timing graph / task graph
dump_graph