[INFO ODB-0227] LEF file: Nangate45/Nangate45_tech.lef, created 22 layers, 27 vias [INFO ODB-0227] LEF file: Nangate45/Nangate45_stdcell.lef, created 135 library cells [INFO ODB-0227] LEF file: array_tile.lef, created 1 library cells [INFO IFP-0001] Added 3528 rows of 26000 site FreePDK45_38x28_10R_NP_162NW_34O. [INFO ODB-0303] The initial 3528 rows (91728000 sites) were cut with 225 shapes for a total of 52263 rows (14219856 sites). [INFO IFP-0100] Die BBox: ( 0.000 0.000 ) ( 4940.000 4940.000 ) um [INFO IFP-0101] Core BBox: ( 0.000 0.000 ) ( 4940.000 4939.200 ) um [INFO IFP-0102] Core area: 24399648.000 um^2 [INFO IFP-0103] Total instances area: 20260174.500 um^2 [INFO IFP-0104] Effective utilization: 0.830 [INFO IFP-0105] Number of instances: 2475 [INFO CTS-0050] Root buffer is BUF_X4. [INFO CTS-0051] Sink buffer is BUF_X4. [INFO CTS-0052] The following clock buffers will be used for CTS: BUF_X4 [INFO CTS-0049] Characterization buffer is BUF_X4. [INFO CTS-0007] Net "clk" found for clock "clk". [INFO CTS-0011] Clock net "clk" for macros has 225 sinks. [INFO CTS-0011] Clock net "clk_regs" for registers has 2250 sinks. [INFO CTS-0008] TritonCTS found 2 clock nets. [INFO CTS-0097] Characterization used 1 buffer(s) types. [INFO CTS-0201] 225 blockages from hard placement blockages and placed macros will be used. [INFO CTS-0027] Generating H-Tree topology for net clk. [INFO CTS-0028] Total number of sinks: 225. [INFO CTS-0029] Macro sinks will be clustered in groups of up to 4 and with maximum cluster diameter of 600.0 um. [INFO CTS-0030] Number of static layers: 0. [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). [INFO CTS-0204] A clustering solution was found from clustering size of 4 and clustering diameter of 600. [INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering. [INFO CTS-0019] Total number of sinks after clustering: 120. [INFO CTS-0024] Normalized sink region: [(1.09571, 44.4286), (661.096, 680.704)]. [INFO CTS-0025] Width: 660.0000. [INFO CTS-0026] Height: 636.2757. Level 1 Direction: Horizontal Sinks per sub-region: 60 Sub-region size: 330.0000 X 636.2757 [INFO CTS-0034] Segment length (rounded): 164. Level 2 Direction: Vertical Sinks per sub-region: 30 Sub-region size: 330.0000 X 318.1379 [INFO CTS-0034] Segment length (rounded): 160. Level 3 Direction: Horizontal Sinks per sub-region: 15 Sub-region size: 165.0000 X 318.1379 [INFO CTS-0034] Segment length (rounded): 82. Level 4 Direction: Vertical Sinks per sub-region: 8 Sub-region size: 165.0000 X 159.0689 [INFO CTS-0034] Segment length (rounded): 80. Level 5 Direction: Horizontal Sinks per sub-region: 4 Sub-region size: 82.5000 X 159.0689 [INFO CTS-0034] Segment length (rounded): 42. Level 6 Direction: Vertical Sinks per sub-region: 2 Sub-region size: 82.5000 X 79.5345 [INFO CTS-0034] Segment length (rounded): 40. Level 7 Direction: Horizontal Sinks per sub-region: 1 Sub-region size: 41.2500 X 79.5345 [INFO CTS-0034] Segment length (rounded): 20. [INFO CTS-0038] Stop criterion found. Sink region hpwl is smaller than max wirelength (692.813 um) and max number of sinks is 15. [INFO CTS-0035] Number of sinks covered: 120. [INFO CTS-0201] 225 blockages from hard placement blockages and placed macros will be used. [INFO CTS-0027] Generating H-Tree topology for net clk_regs. [INFO CTS-0028] Total number of sinks: 2250. [INFO CTS-0059] Register sinks will be clustered with maximum cluster diameter of 100.0 um and based on buffer max cap. [INFO CTS-0030] Number of static layers: 0. [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). [INFO CTS-0204] A clustering solution was found from max clustering size of 20 and clustering diameter of 100. [INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering. [INFO CTS-0019] Total number of sinks after clustering: 136. [INFO CTS-0024] Normalized sink region: [(189.626, 2.41643), (661.055, 670.416)]. [INFO CTS-0025] Width: 471.4286. [INFO CTS-0026] Height: 668.0000. Level 1 Direction: Vertical Sinks per sub-region: 68 Sub-region size: 471.4286 X 334.0000 [INFO CTS-0034] Segment length (rounded): 166. Level 2 Direction: Horizontal Sinks per sub-region: 34 Sub-region size: 235.7143 X 334.0000 [INFO CTS-0034] Segment length (rounded): 118. Level 3 Direction: Vertical Sinks per sub-region: 17 Sub-region size: 235.7143 X 167.0000 [INFO CTS-0034] Segment length (rounded): 84. Level 4 Direction: Horizontal Sinks per sub-region: 9 Sub-region size: 117.8572 X 167.0000 [INFO CTS-0034] Segment length (rounded): 58. Level 5 Direction: Vertical Sinks per sub-region: 5 Sub-region size: 117.8572 X 83.5000 [INFO CTS-0034] Segment length (rounded): 42. Level 6 Direction: Horizontal Sinks per sub-region: 3 Sub-region size: 58.9286 X 83.5000 [INFO CTS-0034] Segment length (rounded): 30. Level 7 Direction: Vertical Sinks per sub-region: 2 Sub-region size: 58.9286 X 41.7500 [INFO CTS-0034] Segment length (rounded): 20. [INFO CTS-0038] Stop criterion found. Sink region hpwl is smaller than max wirelength (692.813 um) and max number of sinks is 15. [INFO CTS-0035] Number of sinks covered: 136. [INFO CTS-0018] Created 453 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 21. [INFO CTS-0013] Maximum number of buffers in the clock path: 21. [INFO CTS-0015] Created 453 clock nets. [INFO CTS-0016] Fanout distribution for the current clock = 1:131, 2:107.. [INFO CTS-0017] Max level of the clock tree: 7. [INFO CTS-0018] Created 453 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 19. [INFO CTS-0013] Maximum number of buffers in the clock path: 19. [INFO CTS-0015] Created 453 clock nets. [INFO CTS-0016] Fanout distribution for the current clock = 1:93, 2:20, 3:1, 5:2, 10:44, 20:90.. [INFO CTS-0017] Max level of the clock tree: 7. [INFO CTS-0098] Clock net "clk" [INFO CTS-0099] Sinks 225 [INFO CTS-0100] Leaf buffers 120 [INFO CTS-0101] Average sink wire length 9627.53 um [INFO CTS-0102] Path depth 21 - 21 [INFO CTS-0207] Dummy loads inserted 12 [INFO CTS-0098] Clock net "clk_regs" [INFO CTS-0099] Sinks 2290 [INFO CTS-0100] Leaf buffers 136 [INFO CTS-0101] Average sink wire length 4227.48 um [INFO CTS-0102] Path depth 17 - 19 [INFO CTS-0207] Dummy loads inserted 40 [INFO CTS-0033] Balancing latency for clock clk [INFO CTS-0036] inserted 0 delay buffers Total number of Clock Roots: 2. Total number of Buffers Inserted: 906. Total number of Clock Subnets: 906. Total number of Sinks: 2475. Cells used: BUF_X4: 907 Dummys used: BUF_X4: 42 INV_X8: 10 [INFO RSZ-0058] Using max wire length 693um. [INFO RSZ-0047] Found 60 long wires. [INFO RSZ-0048] Inserted 80 buffers in 60 nets. Clock clk 1.19 source latency inst_12_3/clk ^ -1.29 target latency inst_13_3/clk ^ 0.00 CRPR -------------- -0.10 setup skew Startpoint: inst_1_1 (rising edge-triggered flip-flop clocked by clk) Endpoint: inst_2_1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk (in) 0.04 0.04 ^ wire8/Z (BUF_X8) 0.04 0.08 ^ wire7/Z (BUF_X16) 0.07 0.15 ^ wire6/Z (BUF_X32) 0.06 0.21 ^ wire5/Z (BUF_X32) 0.06 0.27 ^ wire4/Z (BUF_X32) 0.06 0.34 ^ wire3/Z (BUF_X32) 0.06 0.40 ^ wire2/Z (BUF_X32) 0.07 0.46 ^ clkbuf_0_clk/Z (BUF_X4) 0.04 0.50 ^ clkbuf_1_0_0_clk/Z (BUF_X4) 0.04 0.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4) 0.04 0.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4) 0.03 0.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4) 0.04 0.65 ^ clkbuf_1_0_4_clk/Z (BUF_X4) 0.03 0.68 ^ clkbuf_2_0_0_clk/Z (BUF_X4) 0.03 0.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4) 0.03 0.75 ^ clkbuf_2_0_2_clk/Z (BUF_X4) 0.03 0.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4) 0.04 0.83 ^ clkbuf_2_0_4_clk/Z (BUF_X4) 0.03 0.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4) 0.03 0.89 ^ clkbuf_3_0_1_clk/Z (BUF_X4) 0.03 0.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4) 0.04 0.97 ^ clkbuf_4_0_0_clk/Z (BUF_X4) 0.03 1.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4) 0.03 1.04 ^ clkbuf_5_0_0_clk/Z (BUF_X4) 0.04 1.07 ^ clkbuf_5_0_1_clk/Z (BUF_X4) 0.04 1.11 ^ clkbuf_6_0_0_clk/Z (BUF_X4) 0.03 1.14 ^ clkbuf_7_1_0_clk/Z (BUF_X4) 0.04 1.18 ^ clkbuf_leaf_0_clk/Z (BUF_X4) 0.00 1.18 ^ inst_1_1/clk (array_tile) 0.21 1.40 ^ inst_1_1/e_out (array_tile) 0.00 1.40 ^ inst_2_1/w_in (array_tile) 1.40 data arrival time 5.00 5.00 clock clk (rise edge) 0.00 5.00 clock source latency 0.00 5.00 ^ clk (in) 0.04 5.04 ^ wire8/Z (BUF_X8) 0.04 5.08 ^ wire7/Z (BUF_X16) 0.07 5.15 ^ wire6/Z (BUF_X32) 0.06 5.21 ^ wire5/Z (BUF_X32) 0.06 5.27 ^ wire4/Z (BUF_X32) 0.06 5.34 ^ wire3/Z (BUF_X32) 0.06 5.40 ^ wire2/Z (BUF_X32) 0.07 5.46 ^ clkbuf_0_clk/Z (BUF_X4) 0.04 5.50 ^ clkbuf_1_0_0_clk/Z (BUF_X4) 0.04 5.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4) 0.04 5.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4) 0.03 5.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4) 0.04 5.65 ^ clkbuf_1_0_4_clk/Z (BUF_X4) 0.03 5.68 ^ clkbuf_2_0_0_clk/Z (BUF_X4) 0.03 5.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4) 0.03 5.75 ^ clkbuf_2_0_2_clk/Z (BUF_X4) 0.03 5.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4) 0.04 5.83 ^ clkbuf_2_0_4_clk/Z (BUF_X4) 0.03 5.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4) 0.03 5.89 ^ clkbuf_3_0_1_clk/Z (BUF_X4) 0.03 5.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4) 0.04 5.97 ^ clkbuf_4_0_0_clk/Z (BUF_X4) 0.03 6.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4) 0.03 6.04 ^ clkbuf_5_1_0_clk/Z (BUF_X4) 0.05 6.08 ^ clkbuf_5_1_1_clk/Z (BUF_X4) 0.04 6.12 ^ clkbuf_6_2_0_clk/Z (BUF_X4) 0.02 6.15 ^ clkbuf_7_4_0_clk/Z (BUF_X4) 0.02 6.16 ^ clkbuf_leaf_60_clk/Z (BUF_X4) 0.00 6.16 ^ inst_2_1/clk (array_tile) 0.00 6.16 clock reconvergence pessimism -0.05 6.11 library setup time 6.11 data required time --------------------------------------------------------- 6.11 data required time -1.40 data arrival time --------------------------------------------------------- 4.71 slack (MET) Startpoint: inst_2_1 (rising edge-triggered flip-flop clocked by clk) Endpoint: inst_1_1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk (in) 0.04 0.04 ^ wire8/Z (BUF_X8) 0.04 0.08 ^ wire7/Z (BUF_X16) 0.07 0.15 ^ wire6/Z (BUF_X32) 0.06 0.21 ^ wire5/Z (BUF_X32) 0.06 0.27 ^ wire4/Z (BUF_X32) 0.06 0.34 ^ wire3/Z (BUF_X32) 0.06 0.40 ^ wire2/Z (BUF_X32) 0.07 0.46 ^ clkbuf_0_clk/Z (BUF_X4) 0.04 0.50 ^ clkbuf_1_0_0_clk/Z (BUF_X4) 0.04 0.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4) 0.04 0.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4) 0.03 0.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4) 0.04 0.65 ^ clkbuf_1_0_4_clk/Z (BUF_X4) 0.03 0.68 ^ clkbuf_2_0_0_clk/Z (BUF_X4) 0.03 0.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4) 0.03 0.75 ^ clkbuf_2_0_2_clk/Z (BUF_X4) 0.03 0.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4) 0.04 0.83 ^ clkbuf_2_0_4_clk/Z (BUF_X4) 0.03 0.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4) 0.03 0.89 ^ clkbuf_3_0_1_clk/Z (BUF_X4) 0.03 0.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4) 0.04 0.97 ^ clkbuf_4_0_0_clk/Z (BUF_X4) 0.03 1.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4) 0.03 1.04 ^ clkbuf_5_1_0_clk/Z (BUF_X4) 0.05 1.08 ^ clkbuf_5_1_1_clk/Z (BUF_X4) 0.04 1.12 ^ clkbuf_6_2_0_clk/Z (BUF_X4) 0.02 1.15 ^ clkbuf_7_4_0_clk/Z (BUF_X4) 0.02 1.16 ^ clkbuf_leaf_60_clk/Z (BUF_X4) 0.00 1.16 ^ inst_2_1/clk (array_tile) 0.21 1.37 ^ inst_2_1/w_out (array_tile) 0.00 1.37 ^ inst_1_1/e_in (array_tile) 1.37 data arrival time 5.00 5.00 clock clk (rise edge) 0.00 5.00 clock source latency 0.00 5.00 ^ clk (in) 0.04 5.04 ^ wire8/Z (BUF_X8) 0.04 5.08 ^ wire7/Z (BUF_X16) 0.07 5.15 ^ wire6/Z (BUF_X32) 0.06 5.21 ^ wire5/Z (BUF_X32) 0.06 5.27 ^ wire4/Z (BUF_X32) 0.06 5.34 ^ wire3/Z (BUF_X32) 0.06 5.40 ^ wire2/Z (BUF_X32) 0.07 5.46 ^ clkbuf_0_clk/Z (BUF_X4) 0.04 5.50 ^ clkbuf_1_0_0_clk/Z (BUF_X4) 0.04 5.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4) 0.04 5.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4) 0.03 5.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4) 0.04 5.65 ^ clkbuf_1_0_4_clk/Z (BUF_X4) 0.03 5.68 ^ clkbuf_2_0_0_clk/Z (BUF_X4) 0.03 5.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4) 0.03 5.75 ^ clkbuf_2_0_2_clk/Z (BUF_X4) 0.03 5.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4) 0.04 5.83 ^ clkbuf_2_0_4_clk/Z (BUF_X4) 0.03 5.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4) 0.03 5.89 ^ clkbuf_3_0_1_clk/Z (BUF_X4) 0.03 5.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4) 0.04 5.97 ^ clkbuf_4_0_0_clk/Z (BUF_X4) 0.03 6.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4) 0.03 6.04 ^ clkbuf_5_0_0_clk/Z (BUF_X4) 0.04 6.07 ^ clkbuf_5_0_1_clk/Z (BUF_X4) 0.04 6.11 ^ clkbuf_6_0_0_clk/Z (BUF_X4) 0.03 6.14 ^ clkbuf_7_1_0_clk/Z (BUF_X4) 0.04 6.18 ^ clkbuf_leaf_0_clk/Z (BUF_X4) 0.00 6.18 ^ inst_1_1/clk (array_tile) 0.00 6.18 clock reconvergence pessimism -0.05 6.13 library setup time 6.13 data required time --------------------------------------------------------- 6.13 data required time -1.37 data arrival time --------------------------------------------------------- 4.76 slack (MET)