SAIFIINDUSTRIES's picture
Add batch 1 (YosysHQ_picorv32, alexforencich_verilog-ethernet, The-OpenROAD-Project_OpenROAD, darklife_darkriscv, corundum_corundum)
f61bac1 verified
Raw History Blame Contribute Delete
125 Bytes
import utl
try:
utl.error(utl.CTS, 99, "Arbitrary CTS error message")
except Exception as inst:
print(inst.args[0])