Add batch 1 (YosysHQ_picorv32, alexforencich_verilog-ethernet, The-OpenROAD-Project_OpenROAD, darklife_darkriscv, corundum_corundum)
f61bac1 verified Download The-OpenROAD-Project_OpenROAD/src/tap/test/avoid_overlap.ok from SAIFIINDUSTRIES/verilog_data-1: direct link, hf CLI and curl.
- Browser
- Download file 457 Bytes
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https://huggingface.co/datasets/SAIFIINDUSTRIES/verilog_data-1/resolve/main/The-OpenROAD-Project_OpenROAD/src/tap/test/avoid_overlap.ok
- Command line
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hf download hf://datasets/SAIFIINDUSTRIES/verilog_data-1/The-OpenROAD-Project_OpenROAD/src/tap/test/avoid_overlap.ok
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curl -L -o avoid_overlap.ok https://huggingface.co/datasets/SAIFIINDUSTRIES/verilog_data-1/resolve/main/The-OpenROAD-Project_OpenROAD/src/tap/test/avoid_overlap.ok
457 Bytes
| [INFO ODB-0227] LEF file: sky130hs/sky130hs.tlef, created 13 layers, 25 vias | |
| [INFO ODB-0227] LEF file: sky130hs/sky130hs_std_cell.lef, created 390 library cells | |
| [INFO ODB-0128] Design: gcd | |
| [INFO ODB-0130] Created 54 pins. | |
| [INFO ODB-0131] Created 366 components and 2656 component-terminals. | |
| [INFO ODB-0133] Created 402 nets and 1192 connections. | |
| [INFO TAP-0004] Inserted 168 endcaps. | |
| [INFO TAP-0005] Inserted 817 tapcells. | |
| No differences found. | |