Add batch 1 (YosysHQ_picorv32, alexforencich_verilog-ethernet, The-OpenROAD-Project_OpenROAD, darklife_darkriscv, corundum_corundum)
f61bac1 verified Download The-OpenROAD-Project_OpenROAD/src/rsz/test/cpp/TestBufferRemoval3_1.v from SAIFIINDUSTRIES/verilog_data-1: direct link, hf CLI and curl.
- Browser
- Download file 394 Bytes
-
https://huggingface.co/datasets/SAIFIINDUSTRIES/verilog_data-1/resolve/main/The-OpenROAD-Project_OpenROAD/src/rsz/test/cpp/TestBufferRemoval3_1.v
- Command line
-
hf download hf://datasets/SAIFIINDUSTRIES/verilog_data-1/The-OpenROAD-Project_OpenROAD/src/rsz/test/cpp/TestBufferRemoval3_1.v
-
curl -L -o TestBufferRemoval3_1.v https://huggingface.co/datasets/SAIFIINDUSTRIES/verilog_data-1/resolve/main/The-OpenROAD-Project_OpenROAD/src/rsz/test/cpp/TestBufferRemoval3_1.v
394 Bytes
| module top (clk, | |
| in1, | |
| out1, | |
| out2); | |
| input clk; | |
| input in1; | |
| output out1; | |
| output out2; | |
| wire net1; | |
| wire net2; | |
| BUF_X1 drvr (.A(in1), | |
| .Z(net1)); | |
| BUF_X2 buf (.A(net1), | |
| .Z(net2)); | |
| BUF_X4 load (.A(net2), | |
| .Z(out1)); | |
| SUBMOD sub_inst (.in(net2), | |
| .out(out2)); | |
| endmodule | |
| module SUBMOD (in, | |
| out); | |
| input in; | |
| output out; | |
| BUF_X1 load0 (.A(in), .Z(out)); | |
| endmodule | |