Add batch 1 (YosysHQ_picorv32, alexforencich_verilog-ethernet, The-OpenROAD-Project_OpenROAD, darklife_darkriscv, corundum_corundum)
f61bac1 verified | .model tmp_circuit | |
| .inputs n1 n2 n3 n4 | |
| .outputs n17 | |
| .clock clk | |
| .gate AND2_X1 A1=n1 A2=n2 ZN=t1 | |
| .gate AND2_X1 A1=n3 A2=n4 ZN=t2 | |
| .mlatch DFF_X1 D=t3 Q=n17 QN=dummy_0 clk | |
| .gate OR2_X1 A1=t1 A2=t2 ZN=t3 | |
| .end | |