Add batch 1 (YosysHQ_picorv32, alexforencich_verilog-ethernet, The-OpenROAD-Project_OpenROAD, darklife_darkriscv, corundum_corundum)
f61bac1 verified | VERSION 5.8 ; | |
| DIVIDERCHAR "/" ; | |
| BUSBITCHARS "[]" ; | |
| DESIGN centered_dpl ; | |
| UNITS DISTANCE MICRONS 2000 ; | |
| DIEAREA ( 76000 140000 ) ( 91200 151200 ) ; | |
| ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 76000 140000 FS DO 40 BY 1 STEP 380 0 ; | |
| ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 76000 142800 N DO 40 BY 1 STEP 380 0 ; | |
| ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 76000 145600 FS DO 40 BY 1 STEP 380 0 ; | |
| ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 76000 148400 N DO 40 BY 1 STEP 380 0 ; | |
| COMPONENTS 6 ; | |
| - u0 BUF_X1 + PLACED ( 76000 140000 ) N ; | |
| - u1 BUF_X1 + PLACED ( 76380 140000 ) N ; | |
| - u2 BUF_X1 + PLACED ( 76760 140000 ) N ; | |
| - u3 INV_X1 + PLACED ( 77140 140000 ) N ; | |
| - u4 INV_X1 + PLACED ( 77520 140000 ) N ; | |
| - u5 BUF_X1 + PLACED ( 77900 140000 ) N ; | |
| END COMPONENTS | |
| END DESIGN | |