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verilog_data-1 / The-OpenROAD-Project_OpenROAD /src /dbSta /test /cpp /TestReadVerilog_EscapedBracketScalarNames.v

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Add batch 1 (YosysHQ_picorv32, alexforencich_verilog-ethernet, The-OpenROAD-Project_OpenROAD, darklife_darkriscv, corundum_corundum)

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	module top (\foo[3] ,
	out);
	input \foo[3] ;
	output out;

	child u_child (.\foo[3] (\foo[3] ),
	.out(out));
	endmodule

	module child (\foo[3] ,
	out);
	input \foo[3] ;
	output out;

	BUF_X1 load (.A(\foo[3] ),
	.Z(out));
	endmodule