Add batch 1 (YosysHQ_picorv32, alexforencich_verilog-ethernet, The-OpenROAD-Project_OpenROAD, darklife_darkriscv, corundum_corundum)
f61bac1 verified Download The-OpenROAD-Project_OpenROAD/src/dbSta/test/cpp/TestDbSta_StalePrevPath.v from SAIFIINDUSTRIES/verilog_data-1: direct link, hf CLI and curl.
- Browser
- Download file 231 Bytes
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https://huggingface.co/datasets/SAIFIINDUSTRIES/verilog_data-1/resolve/main/The-OpenROAD-Project_OpenROAD/src/dbSta/test/cpp/TestDbSta_StalePrevPath.v
- Command line
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hf download hf://datasets/SAIFIINDUSTRIES/verilog_data-1/The-OpenROAD-Project_OpenROAD/src/dbSta/test/cpp/TestDbSta_StalePrevPath.v
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curl -L -o TestDbSta_StalePrevPath.v https://huggingface.co/datasets/SAIFIINDUSTRIES/verilog_data-1/resolve/main/The-OpenROAD-Project_OpenROAD/src/dbSta/test/cpp/TestDbSta_StalePrevPath.v
231 Bytes
| module top (clk, | |
| in2, | |
| out1); | |
| input clk; | |
| input in2; | |
| output out1; | |
| wire n0; | |
| wire n1; | |
| BUF_X1 b1 (.A(clk), | |
| .Z(n0)); | |
| INV_X1 inv1 (.A(n0), | |
| .ZN(n1)); | |
| NAND2_X1 nd1 (.A1(n1), | |
| .A2(in2), | |
| .ZN(out1)); | |
| endmodule | |