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verilog_data-1 / The-OpenROAD-Project_OpenROAD /src /dbSta /test /clock_pin.v

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Add batch 1 (YosysHQ_picorv32, alexforencich_verilog-ethernet, The-OpenROAD-Project_OpenROAD, darklife_darkriscv, corundum_corundum)

f61bac1 verified 29 days ago

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	module top (in1, clk1, out1);
	input in1, clk1;
	output out1;

	DFF_X1 r1 (.D(in1), .CK(clk1), .Q(out));
	endmodule // top