Add batch 1 (YosysHQ_picorv32, alexforencich_verilog-ethernet, The-OpenROAD-Project_OpenROAD, darklife_darkriscv, corundum_corundum)
f61bac1 verified Download The-OpenROAD-Project_OpenROAD/src/dbSta/test/clock_pin.tcl from SAIFIINDUSTRIES/verilog_data-1: direct link, hf CLI and curl.
- Browser
- Download file 461 Bytes
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https://huggingface.co/datasets/SAIFIINDUSTRIES/verilog_data-1/resolve/main/The-OpenROAD-Project_OpenROAD/src/dbSta/test/clock_pin.tcl
- Command line
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hf download hf://datasets/SAIFIINDUSTRIES/verilog_data-1/The-OpenROAD-Project_OpenROAD/src/dbSta/test/clock_pin.tcl
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curl -L -o clock_pin.tcl https://huggingface.co/datasets/SAIFIINDUSTRIES/verilog_data-1/resolve/main/The-OpenROAD-Project_OpenROAD/src/dbSta/test/clock_pin.tcl
461 Bytes
| # Set clock pin from Liberty when LEF is missing it | |
| source "helpers.tcl" | |
| read_liberty Nangate45/Nangate45_typ.lib | |
| read_lef Nangate45/Nangate45.lef | |
| read_verilog clock_pin.v | |
| link_design top | |
| set type [get_property [get_lib_pins NangateOpenCellLibrary/DFFRS_X1/CK] is_register_clock] | |
| puts "STA is_register_clock: $type" | |
| set db [ord::get_db] | |
| set master [$db findMaster DFFRS_X1] | |
| set mterm [$master findMTerm CK] | |
| set type [$mterm getSigType] | |
| puts "ODB type: $type" | |