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Add batch 1 (YosysHQ_picorv32, alexforencich_verilog-ethernet, The-OpenROAD-Project_OpenROAD, darklife_darkriscv, corundum_corundum)
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module top (in, out, clk);
input clk;
input [3:0] in;
output [3:0] out;
bus4 bus1(.clk(clk), .in(in), .out(out));
endmodule