The-OpenROAD-Project_OpenROAD/src/dbSta/test/block_sta1.ok

[INFO ODB-0227] LEF file: example1.lef, created 2 layers, 6 library cells
[INFO ODB-0128] Design: top
[INFO ODB-0130]     Created 6 pins.
[INFO ODB-0131]     Created 5 components and 24 component-terminals.
[INFO ODB-0132]     Created 2 special nets and 10 connections.
[INFO ODB-0133]     Created 10 nets and 14 connections.
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk1)
Path Group: clk1
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk1 (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ r2/CK (DFF_X1)
   0.08    0.08 v r2/Q (DFF_X1)
   0.02    0.10 v u1/Z (BUF_X1)
   0.03    0.13 v u2/ZN (AND2_X1)
   0.00    0.13 v r3/D (DFF_X1)
           0.13   data arrival time

  10.00   10.00   clock clk1 (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ r3/CK (DFF_X1)
  -0.04    9.96   library setup time
           9.96   data required time
---------------------------------------------------------
           9.96   data required time
          -0.13   data arrival time
---------------------------------------------------------
           9.83   slack (MET)


 r 0.0321:0.0321 f 0.0417:0.0417
A -> Z combinational
  ^ -> ^ 0.0163:0.0163
  v -> v 0.0208:0.0208
Z -> b2/A wire
  ^ -> ^ 0.0000:0.0000
  v -> v 0.0000:0.0000
Library: example1
Cell: BUF_X1
Arc sense: positive_unate
Arc type: combinational
A ^ -> Z ^
P = 1.0000 V = 1.1000 T = 25.0000
------- input_net_transition = 0.0000
|       total_output_net_capacitance = 0.9747
|        0.3656     1.8954
v      --------------------
0.0012 | 0.0151     0.0193
0.0047 | 0.0166     0.0208
Table value = 0.0163
PVT scale factor = 1.0000
Delay = 0.0163

------- input_net_transition = 0.0000
|       total_output_net_capacitance = 0.9747
|        0.3656     1.8954
v      --------------------
0.0012 | 0.0043     0.0075
0.0047 | 0.0043     0.0075
Table value = 0.0056
PVT scale factor = 1.0000
Slew = 0.0056
Driver waveform slew = 0.0056

.............................................

A v -> Z v
P = 1.0000 V = 1.1000 T = 25.0000
------- input_net_transition = 0.0000
|       total_output_net_capacitance = 0.8752
|        0.3656     1.8954
v      --------------------
0.0012 | 0.0202     0.0236
0.0047 | 0.0217     0.0251
Table value = 0.0208
PVT scale factor = 1.0000
Delay = 0.0208

------- input_net_transition = 0.0000
|       total_output_net_capacitance = 0.8752
|        0.3656     1.8954
v      --------------------
0.0012 | 0.0043     0.0059
0.0047 | 0.0043     0.0059
Table value = 0.0048
PVT scale factor = 1.0000
Slew = 0.0048
Driver waveform slew = 0.0048

.............................................

Startpoint: r2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk1)
Path Group: clk1
Path Type: max

    Delay      Time   Description
-------------------------------------------------------------
   0.0000    0.0000   clock clk1 (rise edge)
   0.0000    0.0000   clock network delay (ideal)
   0.0000    0.0000 ^ r2/CK (DFF_X1)
   0.0772    0.0772 v r2/Q (DFF_X1)
   0.0233    0.1006 v u1/Z (BUF_X1)
   0.0273    0.1278 v u2/ZN (AND2_X1)
   0.0000    0.1278 v r3/D (DFF_X1)
             0.1278   data arrival time

  10.0000   10.0000   clock clk1 (rise edge)
   0.0000   10.0000   clock network delay (ideal)
   0.0000   10.0000   clock reconvergence pessimism
            10.0000 ^ r3/CK (DFF_X1)
  -0.0390    9.9610   library setup time
             9.9610   data required time
-------------------------------------------------------------
             9.9610   data required time
            -0.1278   data arrival time
-------------------------------------------------------------
             9.8332   slack (MET)