The-OpenROAD-Project_OpenROAD/src/cts/test/check_buffer_inference2.ok

[INFO ODB-0227] LEF file: ModNangate45/ModNangate45.lef, created 22 layers, 27 vias, 135 library cells
[INFO ODB-0128] Design: multi_sink
[INFO ODB-0130]     Created 1 pins.
[INFO ODB-0131]     Created 288 components and 1728 component-terminals.
[INFO ODB-0133]     Created 1 nets and 288 connections.
[DEBUG RSZ-inferClockBufferList] CLKBUF_X1 has input port A with LEF USE as CLOCK
[DEBUG RSZ-inferClockBufferList] CLKBUF_X2 has input port A with LEF USE as CLOCK
[DEBUG RSZ-inferClockBufferList] CLKBUF_X3 has input port A with LEF USE as CLOCK
[DEBUG RSZ-inferClockBufferList] CLKBUF_X1 has been inferred as clock buffer
[DEBUG RSZ-inferClockBufferList] CLKBUF_X2 has been inferred as clock buffer
[DEBUG RSZ-inferClockBufferList] CLKBUF_X3 has been inferred as clock buffer
[DEBUG CTS-buffering] CLKBUF_X1 has cap limit:6.0729997e-16 vs. total cap:0, derate:0.01
[DEBUG CTS-buffering] CLKBUF_X2 has cap limit:1.2145999e-15 vs. total cap:0, derate:0.01
[DEBUG CTS-buffering] CLKBUF_X3 has cap limit:1.81885e-15 vs. total cap:0, derate:0.01
[DEBUG CTS-buffering] CLKBUF_X1 has been selected as sink buffer to drive sink wire cap of 0.00e+00
[INFO CTS-0050] Root buffer is CLKBUF_X3.
[INFO CTS-0051] Sink buffer is CLKBUF_X1.
[INFO CTS-0052] The following clock buffers will be used for CTS:
                    CLKBUF_X1
                    CLKBUF_X2
                    CLKBUF_X3
[INFO CTS-0049] Characterization buffer is CLKBUF_X3.
[INFO CTS-0007] Net "clk" found for clock "clk".
[INFO CTS-0010]  Clock net "clk" has 288 sinks.
[INFO CTS-0008] TritonCTS found 1 clock nets.
[INFO CTS-0097] Characterization used 3 buffer(s) types.
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
[INFO CTS-0027] Generating H-Tree topology for net clk.
[INFO CTS-0028]  Total number of sinks: 288.
[INFO CTS-0029]  Register sinks will be clustered in groups of up to 10 and with maximum cluster diameter of 60.0 um.
[INFO CTS-0030]  Number of static layers: 1.
[INFO CTS-0020]  Wire segment unit: 14000  dbu (7 um).
[INFO CTS-0021]  Distance between buffers: 7 units (100 um).
[INFO CTS-0204] A clustering solution was found from clustering size of 10 and clustering diameter of 60.
[INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering.
[INFO CTS-0019]  Total number of sinks after clustering: 29.
[INFO CTS-0024]  Normalized sink region: [(1.26757, 0.912143), (13.4493, 11.6927)].
[INFO CTS-0025]     Width:  12.1817.
[INFO CTS-0026]     Height: 10.7806.
 Level 1
    Direction: Horizontal
    Sinks per sub-region: 15
    Sub-region size: 6.0909 X 10.7806
[INFO CTS-0034]     Segment length (rounded): 4.
 Level 2
    Direction: Vertical
    Sinks per sub-region: 8
    Sub-region size: 6.0909 X 5.3903
[INFO CTS-0034]     Segment length (rounded): 2.
[INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
[INFO CTS-0035]  Number of sinks covered: 29.
[INFO CTS-0018]     Created 34 clock buffers.
[INFO CTS-0012]     Minimum number of buffers in the clock path: 3.
[INFO CTS-0013]     Maximum number of buffers in the clock path: 3.
[INFO CTS-0015]     Created 34 clock nets.
[INFO CTS-0016]     Fanout distribution for the current clock = 7:3, 8:2, 10:28..
[INFO CTS-0017]     Max level of the clock tree: 2.
[INFO CTS-0098] Clock net "clk"
[INFO CTS-0099]  Sinks 292
[INFO CTS-0100]  Leaf buffers 29
[INFO CTS-0101]  Average sink wire length 129.19 um
[INFO CTS-0102]  Path depth 2 - 3
[INFO CTS-0207]  Dummy loads inserted 4
Found 0 unconnected buffers.