Add batch 1 (YosysHQ_picorv32, alexforencich_verilog-ethernet, The-OpenROAD-Project_OpenROAD, darklife_darkriscv, corundum_corundum)
f61bac1 verified | [INFO ODB-0227] LEF file: Nangate45/Nangate45_tech.lef, created 22 layers, 27 vias | |
| [INFO ODB-0227] LEF file: Nangate45/Nangate45_stdcell.lef, created 135 library cells | |
| [INFO ODB-0227] LEF file: array_tile.lef, created 1 library cells | |
| [INFO IFP-0001] Added 3528 rows of 26000 site FreePDK45_38x28_10R_NP_162NW_34O. | |
| [INFO IFP-0100] Die BBox: ( 0.000 0.000 ) ( 4940.000 4940.000 ) um | |
| [INFO IFP-0101] Core BBox: ( 0.000 0.000 ) ( 4940.000 4939.200 ) um | |
| [INFO IFP-0102] Core area: 24399648.000 um^2 | |
| [INFO IFP-0103] Total instances area: 20260174.500 um^2 | |
| [INFO IFP-0104] Effective utilization: 0.830 | |
| [INFO IFP-0105] Number of instances: 2475 | |
| [INFO CTS-0050] Root buffer is BUF_X4. | |
| [INFO CTS-0051] Sink buffer is BUF_X4. | |
| [INFO CTS-0052] The following clock buffers will be used for CTS: | |
| BUF_X4 | |
| [INFO CTS-0049] Characterization buffer is BUF_X4. | |
| [INFO CTS-0007] Net "clk" found for clock "clk". | |
| [INFO CTS-0011] Clock net "clk" for macros has 225 sinks. | |
| [INFO CTS-0011] Clock net "clk_regs" for registers has 2250 sinks. | |
| [INFO CTS-0008] TritonCTS found 2 clock nets. | |
| [INFO CTS-0097] Characterization used 1 buffer(s) types. | |
| [INFO CTS-0201] 225 blockages from hard placement blockages and placed macros will be used. | |
| [INFO CTS-0027] Generating H-Tree topology for net clk. | |
| [INFO CTS-0028] Total number of sinks: 225. | |
| [INFO CTS-0029] Macro sinks will be clustered in groups of up to 4 and with maximum cluster diameter of 600.0 um. | |
| [INFO CTS-0030] Number of static layers: 0. | |
| [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). | |
| [INFO CTS-0204] A clustering solution was found from clustering size of 4 and clustering diameter of 600. | |
| [INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering. | |
| [INFO CTS-0019] Total number of sinks after clustering: 120. | |
| [INFO CTS-0024] Normalized sink region: [(1.23857, 44.2857), (661.239, 680.704)]. | |
| [INFO CTS-0025] Width: 660.0000. | |
| [INFO CTS-0026] Height: 636.4186. | |
| Level 1 | |
| Direction: Horizontal | |
| Sinks per sub-region: 60 | |
| Sub-region size: 330.0000 X 636.4186 | |
| [INFO CTS-0034] Segment length (rounded): 166. | |
| Level 2 | |
| Direction: Vertical | |
| Sinks per sub-region: 30 | |
| Sub-region size: 330.0000 X 318.2093 | |
| [INFO CTS-0034] Segment length (rounded): 160. | |
| Level 3 | |
| Direction: Horizontal | |
| Sinks per sub-region: 15 | |
| Sub-region size: 165.0000 X 318.2093 | |
| [INFO CTS-0034] Segment length (rounded): 82. | |
| Level 4 | |
| Direction: Vertical | |
| Sinks per sub-region: 8 | |
| Sub-region size: 165.0000 X 159.1046 | |
| [INFO CTS-0034] Segment length (rounded): 80. | |
| Level 5 | |
| Direction: Horizontal | |
| Sinks per sub-region: 4 | |
| Sub-region size: 82.5000 X 159.1046 | |
| [INFO CTS-0034] Segment length (rounded): 42. | |
| Level 6 | |
| Direction: Vertical | |
| Sinks per sub-region: 2 | |
| Sub-region size: 82.5000 X 79.5523 | |
| [INFO CTS-0034] Segment length (rounded): 40. | |
| Level 7 | |
| Direction: Horizontal | |
| Sinks per sub-region: 1 | |
| Sub-region size: 41.2500 X 79.5523 | |
| [INFO CTS-0034] Segment length (rounded): 20. | |
| [INFO CTS-0038] Stop criterion found. Sink region hpwl is smaller than max wirelength (692.813 um) and max number of sinks is 15. | |
| [INFO CTS-0035] Number of sinks covered: 120. | |
| [INFO CTS-0201] 225 blockages from hard placement blockages and placed macros will be used. | |
| [INFO CTS-0027] Generating H-Tree topology for net clk_regs. | |
| [INFO CTS-0028] Total number of sinks: 2250. | |
| [INFO CTS-0059] Register sinks will be clustered with maximum cluster diameter of 100.0 um and based on buffer max cap. | |
| [INFO CTS-0030] Number of static layers: 0. | |
| [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). | |
| [INFO CTS-0204] A clustering solution was found from max clustering size of 20 and clustering diameter of 100. | |
| [INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering. | |
| [INFO CTS-0019] Total number of sinks after clustering: 136. | |
| [INFO CTS-0024] Normalized sink region: [(189.626, 2.41643), (661.055, 670.416)]. | |
| [INFO CTS-0025] Width: 471.4286. | |
| [INFO CTS-0026] Height: 668.0000. | |
| Level 1 | |
| Direction: Vertical | |
| Sinks per sub-region: 68 | |
| Sub-region size: 471.4286 X 334.0000 | |
| [INFO CTS-0034] Segment length (rounded): 166. | |
| Level 2 | |
| Direction: Horizontal | |
| Sinks per sub-region: 34 | |
| Sub-region size: 235.7143 X 334.0000 | |
| [INFO CTS-0034] Segment length (rounded): 118. | |
| Level 3 | |
| Direction: Vertical | |
| Sinks per sub-region: 17 | |
| Sub-region size: 235.7143 X 167.0000 | |
| [INFO CTS-0034] Segment length (rounded): 84. | |
| Level 4 | |
| Direction: Horizontal | |
| Sinks per sub-region: 9 | |
| Sub-region size: 117.8572 X 167.0000 | |
| [INFO CTS-0034] Segment length (rounded): 58. | |
| Level 5 | |
| Direction: Vertical | |
| Sinks per sub-region: 5 | |
| Sub-region size: 117.8572 X 83.5000 | |
| [INFO CTS-0034] Segment length (rounded): 42. | |
| Level 6 | |
| Direction: Horizontal | |
| Sinks per sub-region: 3 | |
| Sub-region size: 58.9286 X 83.5000 | |
| [INFO CTS-0034] Segment length (rounded): 30. | |
| Level 7 | |
| Direction: Vertical | |
| Sinks per sub-region: 2 | |
| Sub-region size: 58.9286 X 41.7500 | |
| [INFO CTS-0034] Segment length (rounded): 20. | |
| [INFO CTS-0038] Stop criterion found. Sink region hpwl is smaller than max wirelength (692.813 um) and max number of sinks is 15. | |
| [INFO CTS-0035] Number of sinks covered: 136. | |
| [INFO CTS-0018] Created 453 clock buffers. | |
| [INFO CTS-0012] Minimum number of buffers in the clock path: 21. | |
| [INFO CTS-0013] Maximum number of buffers in the clock path: 21. | |
| [INFO CTS-0015] Created 453 clock nets. | |
| [INFO CTS-0016] Fanout distribution for the current clock = 1:131, 2:107.. | |
| [INFO CTS-0017] Max level of the clock tree: 7. | |
| [INFO CTS-0018] Created 453 clock buffers. | |
| [INFO CTS-0012] Minimum number of buffers in the clock path: 19. | |
| [INFO CTS-0013] Maximum number of buffers in the clock path: 19. | |
| [INFO CTS-0015] Created 453 clock nets. | |
| [INFO CTS-0016] Fanout distribution for the current clock = 1:93, 2:20, 3:1, 5:2, 10:44, 20:90.. | |
| [INFO CTS-0017] Max level of the clock tree: 7. | |
| [INFO CTS-0098] Clock net "clk" | |
| [INFO CTS-0099] Sinks 225 | |
| [INFO CTS-0100] Leaf buffers 120 | |
| [INFO CTS-0101] Average sink wire length 9787.62 um | |
| [INFO CTS-0102] Path depth 21 - 21 | |
| [INFO CTS-0207] Dummy loads inserted 12 | |
| [INFO CTS-0098] Clock net "clk_regs" | |
| [INFO CTS-0099] Sinks 2290 | |
| [INFO CTS-0100] Leaf buffers 136 | |
| [INFO CTS-0101] Average sink wire length 4225.23 um | |
| [INFO CTS-0102] Path depth 17 - 19 | |
| [INFO CTS-0207] Dummy loads inserted 40 | |
| [INFO CTS-0033] Balancing latency for clock clk | |
| [INFO CTS-0036] inserted 0 delay buffers | |
| [INFO RSZ-0058] Using max wire length 693um. | |
| [INFO RSZ-0047] Found 58 long wires. | |
| [INFO RSZ-0048] Inserted 78 buffers in 58 nets. | |
| Clock clk | |
| 1.18 source latency inst_12_11/clk ^ | |
| -1.24 target latency inst_13_11/clk ^ | |
| 0.00 CRPR | |
| -------------- | |
| -0.06 setup skew | |