Add batch 5 (Luthiraa_TALOS-V2, dawsonjon_fpu, The-OpenROAD-Project_OpenROAD-flow-scripts, antonblanchard_microwatt, alexforencich_verilog-i2c)
784ee2c verified Download The-OpenROAD-Project_OpenROAD-flow-scripts/flow/util/gallery.json from SAIFIINDUSTRIES/verilog_data-1: direct link, hf CLI and curl.
- Browser
- Download file 989 Bytes
-
https://huggingface.co/datasets/SAIFIINDUSTRIES/verilog_data-1/resolve/main/The-OpenROAD-Project_OpenROAD-flow-scripts/flow/util/gallery.json
- Command line
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hf download hf://datasets/SAIFIINDUSTRIES/verilog_data-1/The-OpenROAD-Project_OpenROAD-flow-scripts/flow/util/gallery.json
-
curl -L -o gallery.json https://huggingface.co/datasets/SAIFIINDUSTRIES/verilog_data-1/resolve/main/The-OpenROAD-Project_OpenROAD-flow-scripts/flow/util/gallery.json
989 Bytes
| [ | |
| { | |
| "name" : "floorplan", | |
| "layout_file": "2_floorplan.def", | |
| "min_hierarchy": 0, | |
| "max_hierarchy": 1, | |
| "x_resolution": 2000, | |
| "y_resolution": 2000, | |
| "hide_layers": false | |
| }, | |
| { | |
| "name" : "placement", | |
| "layout_file": "4_1_cts.def", | |
| "min_hierarchy": 0, | |
| "max_hierarchy": 1, | |
| "x_resolution": 2000, | |
| "y_resolution": 2000, | |
| "hide_layers": true | |
| }, | |
| { | |
| "name" : "cts", | |
| "layout_file": "6_final_only_clk.def", | |
| "min_hierarchy": 0, | |
| "max_hierarchy": 1, | |
| "x_resolution": 2000, | |
| "y_resolution": 2000, | |
| "hide_layers": false | |
| }, | |
| { | |
| "name" : "final", | |
| "layout_file": "6_final.def", | |
| "min_hierarchy": 0, | |
| "max_hierarchy": 1, | |
| "x_resolution": 2000, | |
| "y_resolution": 2000, | |
| "hide_layers": false | |
| }, | |
| { | |
| "name" : "final_no_power", | |
| "layout_file": "6_final_no_power.def", | |
| "min_hierarchy": 0, | |
| "max_hierarchy": 1, | |
| "x_resolution": 2000, | |
| "y_resolution": 2000, | |
| "hide_layers": false | |
| } | |
| ] | |