Add batch 5 (Luthiraa_TALOS-V2, dawsonjon_fpu, The-OpenROAD-Project_OpenROAD-flow-scripts, antonblanchard_microwatt, alexforencich_verilog-i2c)
784ee2c verified | utl::set_metrics_stage "finish__{}" | |
| source $::env(SCRIPTS_DIR)/load.tcl | |
| erase_non_stage_variables final | |
| load_design 6_1_fill.odb 6_1_fill.sdc | |
| source_step_tcl PRE FINAL_REPORT | |
| set_propagated_clock [all_clocks] | |
| # Ensure all OR created (rsz/cts) instances are connected | |
| global_connect | |